xref: /openbmc/linux/drivers/nvme/host/pci.c (revision dbf4d133)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NVM Express device driver
4  * Copyright (c) 2011-2014, Intel Corporation.
5  */
6 
7 #include <linux/aer.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/dmi.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
15 #include <linux/io.h>
16 #include <linux/mm.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/once.h>
20 #include <linux/pci.h>
21 #include <linux/suspend.h>
22 #include <linux/t10-pi.h>
23 #include <linux/types.h>
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/sed-opal.h>
26 #include <linux/pci-p2pdma.h>
27 
28 #include "trace.h"
29 #include "nvme.h"
30 
31 #define SQ_SIZE(q)	((q)->q_depth << (q)->sqes)
32 #define CQ_SIZE(q)	((q)->q_depth * sizeof(struct nvme_completion))
33 
34 #define SGES_PER_PAGE	(PAGE_SIZE / sizeof(struct nvme_sgl_desc))
35 
36 /*
37  * These can be higher, but we need to ensure that any command doesn't
38  * require an sg allocation that needs more than a page of data.
39  */
40 #define NVME_MAX_KB_SZ	4096
41 #define NVME_MAX_SEGS	127
42 
43 static int use_threaded_interrupts;
44 module_param(use_threaded_interrupts, int, 0);
45 
46 static bool use_cmb_sqes = true;
47 module_param(use_cmb_sqes, bool, 0444);
48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
49 
50 static unsigned int max_host_mem_size_mb = 128;
51 module_param(max_host_mem_size_mb, uint, 0444);
52 MODULE_PARM_DESC(max_host_mem_size_mb,
53 	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
54 
55 static unsigned int sgl_threshold = SZ_32K;
56 module_param(sgl_threshold, uint, 0644);
57 MODULE_PARM_DESC(sgl_threshold,
58 		"Use SGLs when average request segment size is larger or equal to "
59 		"this size. Use 0 to disable SGLs.");
60 
61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
62 static const struct kernel_param_ops io_queue_depth_ops = {
63 	.set = io_queue_depth_set,
64 	.get = param_get_int,
65 };
66 
67 static int io_queue_depth = 1024;
68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
70 
71 static unsigned int write_queues;
72 module_param(write_queues, uint, 0644);
73 MODULE_PARM_DESC(write_queues,
74 	"Number of queues to use for writes. If not set, reads and writes "
75 	"will share a queue set.");
76 
77 static unsigned int poll_queues;
78 module_param(poll_queues, uint, 0644);
79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
80 
81 struct nvme_dev;
82 struct nvme_queue;
83 
84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
86 
87 /*
88  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
89  */
90 struct nvme_dev {
91 	struct nvme_queue *queues;
92 	struct blk_mq_tag_set tagset;
93 	struct blk_mq_tag_set admin_tagset;
94 	u32 __iomem *dbs;
95 	struct device *dev;
96 	struct dma_pool *prp_page_pool;
97 	struct dma_pool *prp_small_pool;
98 	unsigned online_queues;
99 	unsigned max_qid;
100 	unsigned io_queues[HCTX_MAX_TYPES];
101 	unsigned int num_vecs;
102 	int q_depth;
103 	int io_sqes;
104 	u32 db_stride;
105 	void __iomem *bar;
106 	unsigned long bar_mapped_size;
107 	struct work_struct remove_work;
108 	struct mutex shutdown_lock;
109 	bool subsystem;
110 	u64 cmb_size;
111 	bool cmb_use_sqes;
112 	u32 cmbsz;
113 	u32 cmbloc;
114 	struct nvme_ctrl ctrl;
115 	u32 last_ps;
116 
117 	mempool_t *iod_mempool;
118 
119 	/* shadow doorbell buffer support: */
120 	u32 *dbbuf_dbs;
121 	dma_addr_t dbbuf_dbs_dma_addr;
122 	u32 *dbbuf_eis;
123 	dma_addr_t dbbuf_eis_dma_addr;
124 
125 	/* host memory buffer support: */
126 	u64 host_mem_size;
127 	u32 nr_host_mem_descs;
128 	dma_addr_t host_mem_descs_dma;
129 	struct nvme_host_mem_buf_desc *host_mem_descs;
130 	void **host_mem_desc_bufs;
131 };
132 
133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
134 {
135 	int n = 0, ret;
136 
137 	ret = kstrtoint(val, 10, &n);
138 	if (ret != 0 || n < 2)
139 		return -EINVAL;
140 
141 	return param_set_int(val, kp);
142 }
143 
144 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
145 {
146 	return qid * 2 * stride;
147 }
148 
149 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
150 {
151 	return (qid * 2 + 1) * stride;
152 }
153 
154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
155 {
156 	return container_of(ctrl, struct nvme_dev, ctrl);
157 }
158 
159 /*
160  * An NVM Express queue.  Each device has at least two (one for admin
161  * commands and one for I/O commands).
162  */
163 struct nvme_queue {
164 	struct nvme_dev *dev;
165 	spinlock_t sq_lock;
166 	void *sq_cmds;
167 	 /* only used for poll queues: */
168 	spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
169 	volatile struct nvme_completion *cqes;
170 	dma_addr_t sq_dma_addr;
171 	dma_addr_t cq_dma_addr;
172 	u32 __iomem *q_db;
173 	u16 q_depth;
174 	u16 cq_vector;
175 	u16 sq_tail;
176 	u16 last_sq_tail;
177 	u16 cq_head;
178 	u16 qid;
179 	u8 cq_phase;
180 	u8 sqes;
181 	unsigned long flags;
182 #define NVMEQ_ENABLED		0
183 #define NVMEQ_SQ_CMB		1
184 #define NVMEQ_DELETE_ERROR	2
185 #define NVMEQ_POLLED		3
186 	u32 *dbbuf_sq_db;
187 	u32 *dbbuf_cq_db;
188 	u32 *dbbuf_sq_ei;
189 	u32 *dbbuf_cq_ei;
190 	struct completion delete_done;
191 };
192 
193 /*
194  * The nvme_iod describes the data in an I/O.
195  *
196  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
197  * to the actual struct scatterlist.
198  */
199 struct nvme_iod {
200 	struct nvme_request req;
201 	struct nvme_queue *nvmeq;
202 	bool use_sgl;
203 	int aborted;
204 	int npages;		/* In the PRP list. 0 means small pool in use */
205 	int nents;		/* Used in scatterlist */
206 	dma_addr_t first_dma;
207 	unsigned int dma_len;	/* length of single DMA segment mapping */
208 	dma_addr_t meta_dma;
209 	struct scatterlist *sg;
210 };
211 
212 static unsigned int max_io_queues(void)
213 {
214 	return num_possible_cpus() + write_queues + poll_queues;
215 }
216 
217 static unsigned int max_queue_count(void)
218 {
219 	/* IO queues + admin queue */
220 	return 1 + max_io_queues();
221 }
222 
223 static inline unsigned int nvme_dbbuf_size(u32 stride)
224 {
225 	return (max_queue_count() * 8 * stride);
226 }
227 
228 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
229 {
230 	unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
231 
232 	if (dev->dbbuf_dbs)
233 		return 0;
234 
235 	dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
236 					    &dev->dbbuf_dbs_dma_addr,
237 					    GFP_KERNEL);
238 	if (!dev->dbbuf_dbs)
239 		return -ENOMEM;
240 	dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
241 					    &dev->dbbuf_eis_dma_addr,
242 					    GFP_KERNEL);
243 	if (!dev->dbbuf_eis) {
244 		dma_free_coherent(dev->dev, mem_size,
245 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
246 		dev->dbbuf_dbs = NULL;
247 		return -ENOMEM;
248 	}
249 
250 	return 0;
251 }
252 
253 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
254 {
255 	unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
256 
257 	if (dev->dbbuf_dbs) {
258 		dma_free_coherent(dev->dev, mem_size,
259 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
260 		dev->dbbuf_dbs = NULL;
261 	}
262 	if (dev->dbbuf_eis) {
263 		dma_free_coherent(dev->dev, mem_size,
264 				  dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
265 		dev->dbbuf_eis = NULL;
266 	}
267 }
268 
269 static void nvme_dbbuf_init(struct nvme_dev *dev,
270 			    struct nvme_queue *nvmeq, int qid)
271 {
272 	if (!dev->dbbuf_dbs || !qid)
273 		return;
274 
275 	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
276 	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
277 	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
278 	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
279 }
280 
281 static void nvme_dbbuf_set(struct nvme_dev *dev)
282 {
283 	struct nvme_command c;
284 
285 	if (!dev->dbbuf_dbs)
286 		return;
287 
288 	memset(&c, 0, sizeof(c));
289 	c.dbbuf.opcode = nvme_admin_dbbuf;
290 	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
291 	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
292 
293 	if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
294 		dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
295 		/* Free memory and continue on */
296 		nvme_dbbuf_dma_free(dev);
297 	}
298 }
299 
300 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
301 {
302 	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
303 }
304 
305 /* Update dbbuf and return true if an MMIO is required */
306 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
307 					      volatile u32 *dbbuf_ei)
308 {
309 	if (dbbuf_db) {
310 		u16 old_value;
311 
312 		/*
313 		 * Ensure that the queue is written before updating
314 		 * the doorbell in memory
315 		 */
316 		wmb();
317 
318 		old_value = *dbbuf_db;
319 		*dbbuf_db = value;
320 
321 		/*
322 		 * Ensure that the doorbell is updated before reading the event
323 		 * index from memory.  The controller needs to provide similar
324 		 * ordering to ensure the envent index is updated before reading
325 		 * the doorbell.
326 		 */
327 		mb();
328 
329 		if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
330 			return false;
331 	}
332 
333 	return true;
334 }
335 
336 /*
337  * Will slightly overestimate the number of pages needed.  This is OK
338  * as it only leads to a small amount of wasted memory for the lifetime of
339  * the I/O.
340  */
341 static int nvme_npages(unsigned size, struct nvme_dev *dev)
342 {
343 	unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
344 				      dev->ctrl.page_size);
345 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
346 }
347 
348 /*
349  * Calculates the number of pages needed for the SGL segments. For example a 4k
350  * page can accommodate 256 SGL descriptors.
351  */
352 static int nvme_pci_npages_sgl(unsigned int num_seg)
353 {
354 	return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
355 }
356 
357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
358 		unsigned int size, unsigned int nseg, bool use_sgl)
359 {
360 	size_t alloc_size;
361 
362 	if (use_sgl)
363 		alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
364 	else
365 		alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
366 
367 	return alloc_size + sizeof(struct scatterlist) * nseg;
368 }
369 
370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
371 				unsigned int hctx_idx)
372 {
373 	struct nvme_dev *dev = data;
374 	struct nvme_queue *nvmeq = &dev->queues[0];
375 
376 	WARN_ON(hctx_idx != 0);
377 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
378 
379 	hctx->driver_data = nvmeq;
380 	return 0;
381 }
382 
383 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
384 			  unsigned int hctx_idx)
385 {
386 	struct nvme_dev *dev = data;
387 	struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
388 
389 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
390 	hctx->driver_data = nvmeq;
391 	return 0;
392 }
393 
394 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
395 		unsigned int hctx_idx, unsigned int numa_node)
396 {
397 	struct nvme_dev *dev = set->driver_data;
398 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
399 	int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
400 	struct nvme_queue *nvmeq = &dev->queues[queue_idx];
401 
402 	BUG_ON(!nvmeq);
403 	iod->nvmeq = nvmeq;
404 
405 	nvme_req(req)->ctrl = &dev->ctrl;
406 	return 0;
407 }
408 
409 static int queue_irq_offset(struct nvme_dev *dev)
410 {
411 	/* if we have more than 1 vec, admin queue offsets us by 1 */
412 	if (dev->num_vecs > 1)
413 		return 1;
414 
415 	return 0;
416 }
417 
418 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
419 {
420 	struct nvme_dev *dev = set->driver_data;
421 	int i, qoff, offset;
422 
423 	offset = queue_irq_offset(dev);
424 	for (i = 0, qoff = 0; i < set->nr_maps; i++) {
425 		struct blk_mq_queue_map *map = &set->map[i];
426 
427 		map->nr_queues = dev->io_queues[i];
428 		if (!map->nr_queues) {
429 			BUG_ON(i == HCTX_TYPE_DEFAULT);
430 			continue;
431 		}
432 
433 		/*
434 		 * The poll queue(s) doesn't have an IRQ (and hence IRQ
435 		 * affinity), so use the regular blk-mq cpu mapping
436 		 */
437 		map->queue_offset = qoff;
438 		if (i != HCTX_TYPE_POLL && offset)
439 			blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
440 		else
441 			blk_mq_map_queues(map);
442 		qoff += map->nr_queues;
443 		offset += map->nr_queues;
444 	}
445 
446 	return 0;
447 }
448 
449 /*
450  * Write sq tail if we are asked to, or if the next command would wrap.
451  */
452 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
453 {
454 	if (!write_sq) {
455 		u16 next_tail = nvmeq->sq_tail + 1;
456 
457 		if (next_tail == nvmeq->q_depth)
458 			next_tail = 0;
459 		if (next_tail != nvmeq->last_sq_tail)
460 			return;
461 	}
462 
463 	if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
464 			nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
465 		writel(nvmeq->sq_tail, nvmeq->q_db);
466 	nvmeq->last_sq_tail = nvmeq->sq_tail;
467 }
468 
469 /**
470  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
471  * @nvmeq: The queue to use
472  * @cmd: The command to send
473  * @write_sq: whether to write to the SQ doorbell
474  */
475 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
476 			    bool write_sq)
477 {
478 	spin_lock(&nvmeq->sq_lock);
479 	memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
480 	       cmd, sizeof(*cmd));
481 	if (++nvmeq->sq_tail == nvmeq->q_depth)
482 		nvmeq->sq_tail = 0;
483 	nvme_write_sq_db(nvmeq, write_sq);
484 	spin_unlock(&nvmeq->sq_lock);
485 }
486 
487 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
488 {
489 	struct nvme_queue *nvmeq = hctx->driver_data;
490 
491 	spin_lock(&nvmeq->sq_lock);
492 	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
493 		nvme_write_sq_db(nvmeq, true);
494 	spin_unlock(&nvmeq->sq_lock);
495 }
496 
497 static void **nvme_pci_iod_list(struct request *req)
498 {
499 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
500 	return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
501 }
502 
503 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
504 {
505 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
506 	int nseg = blk_rq_nr_phys_segments(req);
507 	unsigned int avg_seg_size;
508 
509 	if (nseg == 0)
510 		return false;
511 
512 	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
513 
514 	if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
515 		return false;
516 	if (!iod->nvmeq->qid)
517 		return false;
518 	if (!sgl_threshold || avg_seg_size < sgl_threshold)
519 		return false;
520 	return true;
521 }
522 
523 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
524 {
525 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
526 	const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
527 	dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
528 	int i;
529 
530 	if (iod->dma_len) {
531 		dma_unmap_page(dev->dev, dma_addr, iod->dma_len,
532 			       rq_dma_dir(req));
533 		return;
534 	}
535 
536 	WARN_ON_ONCE(!iod->nents);
537 
538 	if (is_pci_p2pdma_page(sg_page(iod->sg)))
539 		pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
540 				    rq_dma_dir(req));
541 	else
542 		dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
543 
544 
545 	if (iod->npages == 0)
546 		dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
547 			dma_addr);
548 
549 	for (i = 0; i < iod->npages; i++) {
550 		void *addr = nvme_pci_iod_list(req)[i];
551 
552 		if (iod->use_sgl) {
553 			struct nvme_sgl_desc *sg_list = addr;
554 
555 			next_dma_addr =
556 			    le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
557 		} else {
558 			__le64 *prp_list = addr;
559 
560 			next_dma_addr = le64_to_cpu(prp_list[last_prp]);
561 		}
562 
563 		dma_pool_free(dev->prp_page_pool, addr, dma_addr);
564 		dma_addr = next_dma_addr;
565 	}
566 
567 	mempool_free(iod->sg, dev->iod_mempool);
568 }
569 
570 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
571 {
572 	int i;
573 	struct scatterlist *sg;
574 
575 	for_each_sg(sgl, sg, nents, i) {
576 		dma_addr_t phys = sg_phys(sg);
577 		pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
578 			"dma_address:%pad dma_length:%d\n",
579 			i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
580 			sg_dma_len(sg));
581 	}
582 }
583 
584 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
585 		struct request *req, struct nvme_rw_command *cmnd)
586 {
587 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
588 	struct dma_pool *pool;
589 	int length = blk_rq_payload_bytes(req);
590 	struct scatterlist *sg = iod->sg;
591 	int dma_len = sg_dma_len(sg);
592 	u64 dma_addr = sg_dma_address(sg);
593 	u32 page_size = dev->ctrl.page_size;
594 	int offset = dma_addr & (page_size - 1);
595 	__le64 *prp_list;
596 	void **list = nvme_pci_iod_list(req);
597 	dma_addr_t prp_dma;
598 	int nprps, i;
599 
600 	length -= (page_size - offset);
601 	if (length <= 0) {
602 		iod->first_dma = 0;
603 		goto done;
604 	}
605 
606 	dma_len -= (page_size - offset);
607 	if (dma_len) {
608 		dma_addr += (page_size - offset);
609 	} else {
610 		sg = sg_next(sg);
611 		dma_addr = sg_dma_address(sg);
612 		dma_len = sg_dma_len(sg);
613 	}
614 
615 	if (length <= page_size) {
616 		iod->first_dma = dma_addr;
617 		goto done;
618 	}
619 
620 	nprps = DIV_ROUND_UP(length, page_size);
621 	if (nprps <= (256 / 8)) {
622 		pool = dev->prp_small_pool;
623 		iod->npages = 0;
624 	} else {
625 		pool = dev->prp_page_pool;
626 		iod->npages = 1;
627 	}
628 
629 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
630 	if (!prp_list) {
631 		iod->first_dma = dma_addr;
632 		iod->npages = -1;
633 		return BLK_STS_RESOURCE;
634 	}
635 	list[0] = prp_list;
636 	iod->first_dma = prp_dma;
637 	i = 0;
638 	for (;;) {
639 		if (i == page_size >> 3) {
640 			__le64 *old_prp_list = prp_list;
641 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
642 			if (!prp_list)
643 				return BLK_STS_RESOURCE;
644 			list[iod->npages++] = prp_list;
645 			prp_list[0] = old_prp_list[i - 1];
646 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
647 			i = 1;
648 		}
649 		prp_list[i++] = cpu_to_le64(dma_addr);
650 		dma_len -= page_size;
651 		dma_addr += page_size;
652 		length -= page_size;
653 		if (length <= 0)
654 			break;
655 		if (dma_len > 0)
656 			continue;
657 		if (unlikely(dma_len < 0))
658 			goto bad_sgl;
659 		sg = sg_next(sg);
660 		dma_addr = sg_dma_address(sg);
661 		dma_len = sg_dma_len(sg);
662 	}
663 
664 done:
665 	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
666 	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
667 
668 	return BLK_STS_OK;
669 
670  bad_sgl:
671 	WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
672 			"Invalid SGL for payload:%d nents:%d\n",
673 			blk_rq_payload_bytes(req), iod->nents);
674 	return BLK_STS_IOERR;
675 }
676 
677 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
678 		struct scatterlist *sg)
679 {
680 	sge->addr = cpu_to_le64(sg_dma_address(sg));
681 	sge->length = cpu_to_le32(sg_dma_len(sg));
682 	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
683 }
684 
685 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
686 		dma_addr_t dma_addr, int entries)
687 {
688 	sge->addr = cpu_to_le64(dma_addr);
689 	if (entries < SGES_PER_PAGE) {
690 		sge->length = cpu_to_le32(entries * sizeof(*sge));
691 		sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
692 	} else {
693 		sge->length = cpu_to_le32(PAGE_SIZE);
694 		sge->type = NVME_SGL_FMT_SEG_DESC << 4;
695 	}
696 }
697 
698 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
699 		struct request *req, struct nvme_rw_command *cmd, int entries)
700 {
701 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
702 	struct dma_pool *pool;
703 	struct nvme_sgl_desc *sg_list;
704 	struct scatterlist *sg = iod->sg;
705 	dma_addr_t sgl_dma;
706 	int i = 0;
707 
708 	/* setting the transfer type as SGL */
709 	cmd->flags = NVME_CMD_SGL_METABUF;
710 
711 	if (entries == 1) {
712 		nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
713 		return BLK_STS_OK;
714 	}
715 
716 	if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
717 		pool = dev->prp_small_pool;
718 		iod->npages = 0;
719 	} else {
720 		pool = dev->prp_page_pool;
721 		iod->npages = 1;
722 	}
723 
724 	sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
725 	if (!sg_list) {
726 		iod->npages = -1;
727 		return BLK_STS_RESOURCE;
728 	}
729 
730 	nvme_pci_iod_list(req)[0] = sg_list;
731 	iod->first_dma = sgl_dma;
732 
733 	nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
734 
735 	do {
736 		if (i == SGES_PER_PAGE) {
737 			struct nvme_sgl_desc *old_sg_desc = sg_list;
738 			struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
739 
740 			sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
741 			if (!sg_list)
742 				return BLK_STS_RESOURCE;
743 
744 			i = 0;
745 			nvme_pci_iod_list(req)[iod->npages++] = sg_list;
746 			sg_list[i++] = *link;
747 			nvme_pci_sgl_set_seg(link, sgl_dma, entries);
748 		}
749 
750 		nvme_pci_sgl_set_data(&sg_list[i++], sg);
751 		sg = sg_next(sg);
752 	} while (--entries > 0);
753 
754 	return BLK_STS_OK;
755 }
756 
757 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
758 		struct request *req, struct nvme_rw_command *cmnd,
759 		struct bio_vec *bv)
760 {
761 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
762 	unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1);
763 	unsigned int first_prp_len = dev->ctrl.page_size - offset;
764 
765 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
766 	if (dma_mapping_error(dev->dev, iod->first_dma))
767 		return BLK_STS_RESOURCE;
768 	iod->dma_len = bv->bv_len;
769 
770 	cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
771 	if (bv->bv_len > first_prp_len)
772 		cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
773 	return 0;
774 }
775 
776 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
777 		struct request *req, struct nvme_rw_command *cmnd,
778 		struct bio_vec *bv)
779 {
780 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
781 
782 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
783 	if (dma_mapping_error(dev->dev, iod->first_dma))
784 		return BLK_STS_RESOURCE;
785 	iod->dma_len = bv->bv_len;
786 
787 	cmnd->flags = NVME_CMD_SGL_METABUF;
788 	cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
789 	cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
790 	cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
791 	return 0;
792 }
793 
794 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
795 		struct nvme_command *cmnd)
796 {
797 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
798 	blk_status_t ret = BLK_STS_RESOURCE;
799 	int nr_mapped;
800 
801 	if (blk_rq_nr_phys_segments(req) == 1) {
802 		struct bio_vec bv = req_bvec(req);
803 
804 		if (!is_pci_p2pdma_page(bv.bv_page)) {
805 			if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2)
806 				return nvme_setup_prp_simple(dev, req,
807 							     &cmnd->rw, &bv);
808 
809 			if (iod->nvmeq->qid &&
810 			    dev->ctrl.sgls & ((1 << 0) | (1 << 1)))
811 				return nvme_setup_sgl_simple(dev, req,
812 							     &cmnd->rw, &bv);
813 		}
814 	}
815 
816 	iod->dma_len = 0;
817 	iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
818 	if (!iod->sg)
819 		return BLK_STS_RESOURCE;
820 	sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
821 	iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
822 	if (!iod->nents)
823 		goto out;
824 
825 	if (is_pci_p2pdma_page(sg_page(iod->sg)))
826 		nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
827 				iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
828 	else
829 		nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
830 					     rq_dma_dir(req), DMA_ATTR_NO_WARN);
831 	if (!nr_mapped)
832 		goto out;
833 
834 	iod->use_sgl = nvme_pci_use_sgls(dev, req);
835 	if (iod->use_sgl)
836 		ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
837 	else
838 		ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
839 out:
840 	if (ret != BLK_STS_OK)
841 		nvme_unmap_data(dev, req);
842 	return ret;
843 }
844 
845 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
846 		struct nvme_command *cmnd)
847 {
848 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
849 
850 	iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
851 			rq_dma_dir(req), 0);
852 	if (dma_mapping_error(dev->dev, iod->meta_dma))
853 		return BLK_STS_IOERR;
854 	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
855 	return 0;
856 }
857 
858 /*
859  * NOTE: ns is NULL when called on the admin queue.
860  */
861 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
862 			 const struct blk_mq_queue_data *bd)
863 {
864 	struct nvme_ns *ns = hctx->queue->queuedata;
865 	struct nvme_queue *nvmeq = hctx->driver_data;
866 	struct nvme_dev *dev = nvmeq->dev;
867 	struct request *req = bd->rq;
868 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
869 	struct nvme_command cmnd;
870 	blk_status_t ret;
871 
872 	iod->aborted = 0;
873 	iod->npages = -1;
874 	iod->nents = 0;
875 
876 	/*
877 	 * We should not need to do this, but we're still using this to
878 	 * ensure we can drain requests on a dying queue.
879 	 */
880 	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
881 		return BLK_STS_IOERR;
882 
883 	ret = nvme_setup_cmd(ns, req, &cmnd);
884 	if (ret)
885 		return ret;
886 
887 	if (blk_rq_nr_phys_segments(req)) {
888 		ret = nvme_map_data(dev, req, &cmnd);
889 		if (ret)
890 			goto out_free_cmd;
891 	}
892 
893 	if (blk_integrity_rq(req)) {
894 		ret = nvme_map_metadata(dev, req, &cmnd);
895 		if (ret)
896 			goto out_unmap_data;
897 	}
898 
899 	blk_mq_start_request(req);
900 	nvme_submit_cmd(nvmeq, &cmnd, bd->last);
901 	return BLK_STS_OK;
902 out_unmap_data:
903 	nvme_unmap_data(dev, req);
904 out_free_cmd:
905 	nvme_cleanup_cmd(req);
906 	return ret;
907 }
908 
909 static void nvme_pci_complete_rq(struct request *req)
910 {
911 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
912 	struct nvme_dev *dev = iod->nvmeq->dev;
913 
914 	if (blk_integrity_rq(req))
915 		dma_unmap_page(dev->dev, iod->meta_dma,
916 			       rq_integrity_vec(req)->bv_len, rq_data_dir(req));
917 	if (blk_rq_nr_phys_segments(req))
918 		nvme_unmap_data(dev, req);
919 	nvme_complete_rq(req);
920 }
921 
922 /* We read the CQE phase first to check if the rest of the entry is valid */
923 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
924 {
925 	return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
926 			nvmeq->cq_phase;
927 }
928 
929 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
930 {
931 	u16 head = nvmeq->cq_head;
932 
933 	if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
934 					      nvmeq->dbbuf_cq_ei))
935 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
936 }
937 
938 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
939 {
940 	if (!nvmeq->qid)
941 		return nvmeq->dev->admin_tagset.tags[0];
942 	return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
943 }
944 
945 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
946 {
947 	volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
948 	struct request *req;
949 
950 	if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
951 		dev_warn(nvmeq->dev->ctrl.device,
952 			"invalid id %d completed on queue %d\n",
953 			cqe->command_id, le16_to_cpu(cqe->sq_id));
954 		return;
955 	}
956 
957 	/*
958 	 * AEN requests are special as they don't time out and can
959 	 * survive any kind of queue freeze and often don't respond to
960 	 * aborts.  We don't even bother to allocate a struct request
961 	 * for them but rather special case them here.
962 	 */
963 	if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) {
964 		nvme_complete_async_event(&nvmeq->dev->ctrl,
965 				cqe->status, &cqe->result);
966 		return;
967 	}
968 
969 	req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id);
970 	trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
971 	nvme_end_request(req, cqe->status, cqe->result);
972 }
973 
974 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
975 {
976 	u16 tmp = nvmeq->cq_head + 1;
977 
978 	if (tmp == nvmeq->q_depth) {
979 		nvmeq->cq_head = 0;
980 		nvmeq->cq_phase ^= 1;
981 	} else {
982 		nvmeq->cq_head = tmp;
983 	}
984 }
985 
986 static inline int nvme_process_cq(struct nvme_queue *nvmeq)
987 {
988 	int found = 0;
989 
990 	while (nvme_cqe_pending(nvmeq)) {
991 		found++;
992 		nvme_handle_cqe(nvmeq, nvmeq->cq_head);
993 		nvme_update_cq_head(nvmeq);
994 	}
995 
996 	if (found)
997 		nvme_ring_cq_doorbell(nvmeq);
998 	return found;
999 }
1000 
1001 static irqreturn_t nvme_irq(int irq, void *data)
1002 {
1003 	struct nvme_queue *nvmeq = data;
1004 	irqreturn_t ret = IRQ_NONE;
1005 
1006 	/*
1007 	 * The rmb/wmb pair ensures we see all updates from a previous run of
1008 	 * the irq handler, even if that was on another CPU.
1009 	 */
1010 	rmb();
1011 	if (nvme_process_cq(nvmeq))
1012 		ret = IRQ_HANDLED;
1013 	wmb();
1014 
1015 	return ret;
1016 }
1017 
1018 static irqreturn_t nvme_irq_check(int irq, void *data)
1019 {
1020 	struct nvme_queue *nvmeq = data;
1021 	if (nvme_cqe_pending(nvmeq))
1022 		return IRQ_WAKE_THREAD;
1023 	return IRQ_NONE;
1024 }
1025 
1026 /*
1027  * Poll for completions for any interrupt driven queue
1028  * Can be called from any context.
1029  */
1030 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1031 {
1032 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1033 
1034 	WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1035 
1036 	disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1037 	nvme_process_cq(nvmeq);
1038 	enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1039 }
1040 
1041 static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1042 {
1043 	struct nvme_queue *nvmeq = hctx->driver_data;
1044 	bool found;
1045 
1046 	if (!nvme_cqe_pending(nvmeq))
1047 		return 0;
1048 
1049 	spin_lock(&nvmeq->cq_poll_lock);
1050 	found = nvme_process_cq(nvmeq);
1051 	spin_unlock(&nvmeq->cq_poll_lock);
1052 
1053 	return found;
1054 }
1055 
1056 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1057 {
1058 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1059 	struct nvme_queue *nvmeq = &dev->queues[0];
1060 	struct nvme_command c;
1061 
1062 	memset(&c, 0, sizeof(c));
1063 	c.common.opcode = nvme_admin_async_event;
1064 	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1065 	nvme_submit_cmd(nvmeq, &c, true);
1066 }
1067 
1068 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1069 {
1070 	struct nvme_command c;
1071 
1072 	memset(&c, 0, sizeof(c));
1073 	c.delete_queue.opcode = opcode;
1074 	c.delete_queue.qid = cpu_to_le16(id);
1075 
1076 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1077 }
1078 
1079 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1080 		struct nvme_queue *nvmeq, s16 vector)
1081 {
1082 	struct nvme_command c;
1083 	int flags = NVME_QUEUE_PHYS_CONTIG;
1084 
1085 	if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1086 		flags |= NVME_CQ_IRQ_ENABLED;
1087 
1088 	/*
1089 	 * Note: we (ab)use the fact that the prp fields survive if no data
1090 	 * is attached to the request.
1091 	 */
1092 	memset(&c, 0, sizeof(c));
1093 	c.create_cq.opcode = nvme_admin_create_cq;
1094 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1095 	c.create_cq.cqid = cpu_to_le16(qid);
1096 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1097 	c.create_cq.cq_flags = cpu_to_le16(flags);
1098 	c.create_cq.irq_vector = cpu_to_le16(vector);
1099 
1100 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1101 }
1102 
1103 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1104 						struct nvme_queue *nvmeq)
1105 {
1106 	struct nvme_ctrl *ctrl = &dev->ctrl;
1107 	struct nvme_command c;
1108 	int flags = NVME_QUEUE_PHYS_CONTIG;
1109 
1110 	/*
1111 	 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1112 	 * set. Since URGENT priority is zeroes, it makes all queues
1113 	 * URGENT.
1114 	 */
1115 	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1116 		flags |= NVME_SQ_PRIO_MEDIUM;
1117 
1118 	/*
1119 	 * Note: we (ab)use the fact that the prp fields survive if no data
1120 	 * is attached to the request.
1121 	 */
1122 	memset(&c, 0, sizeof(c));
1123 	c.create_sq.opcode = nvme_admin_create_sq;
1124 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1125 	c.create_sq.sqid = cpu_to_le16(qid);
1126 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1127 	c.create_sq.sq_flags = cpu_to_le16(flags);
1128 	c.create_sq.cqid = cpu_to_le16(qid);
1129 
1130 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1131 }
1132 
1133 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1134 {
1135 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1136 }
1137 
1138 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1139 {
1140 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1141 }
1142 
1143 static void abort_endio(struct request *req, blk_status_t error)
1144 {
1145 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1146 	struct nvme_queue *nvmeq = iod->nvmeq;
1147 
1148 	dev_warn(nvmeq->dev->ctrl.device,
1149 		 "Abort status: 0x%x", nvme_req(req)->status);
1150 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1151 	blk_mq_free_request(req);
1152 }
1153 
1154 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1155 {
1156 
1157 	/* If true, indicates loss of adapter communication, possibly by a
1158 	 * NVMe Subsystem reset.
1159 	 */
1160 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1161 
1162 	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1163 	switch (dev->ctrl.state) {
1164 	case NVME_CTRL_RESETTING:
1165 	case NVME_CTRL_CONNECTING:
1166 		return false;
1167 	default:
1168 		break;
1169 	}
1170 
1171 	/* We shouldn't reset unless the controller is on fatal error state
1172 	 * _or_ if we lost the communication with it.
1173 	 */
1174 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1175 		return false;
1176 
1177 	return true;
1178 }
1179 
1180 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1181 {
1182 	/* Read a config register to help see what died. */
1183 	u16 pci_status;
1184 	int result;
1185 
1186 	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1187 				      &pci_status);
1188 	if (result == PCIBIOS_SUCCESSFUL)
1189 		dev_warn(dev->ctrl.device,
1190 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1191 			 csts, pci_status);
1192 	else
1193 		dev_warn(dev->ctrl.device,
1194 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1195 			 csts, result);
1196 }
1197 
1198 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1199 {
1200 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1201 	struct nvme_queue *nvmeq = iod->nvmeq;
1202 	struct nvme_dev *dev = nvmeq->dev;
1203 	struct request *abort_req;
1204 	struct nvme_command cmd;
1205 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1206 
1207 	/* If PCI error recovery process is happening, we cannot reset or
1208 	 * the recovery mechanism will surely fail.
1209 	 */
1210 	mb();
1211 	if (pci_channel_offline(to_pci_dev(dev->dev)))
1212 		return BLK_EH_RESET_TIMER;
1213 
1214 	/*
1215 	 * Reset immediately if the controller is failed
1216 	 */
1217 	if (nvme_should_reset(dev, csts)) {
1218 		nvme_warn_reset(dev, csts);
1219 		nvme_dev_disable(dev, false);
1220 		nvme_reset_ctrl(&dev->ctrl);
1221 		return BLK_EH_DONE;
1222 	}
1223 
1224 	/*
1225 	 * Did we miss an interrupt?
1226 	 */
1227 	if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1228 		nvme_poll(req->mq_hctx);
1229 	else
1230 		nvme_poll_irqdisable(nvmeq);
1231 
1232 	if (blk_mq_request_completed(req)) {
1233 		dev_warn(dev->ctrl.device,
1234 			 "I/O %d QID %d timeout, completion polled\n",
1235 			 req->tag, nvmeq->qid);
1236 		return BLK_EH_DONE;
1237 	}
1238 
1239 	/*
1240 	 * Shutdown immediately if controller times out while starting. The
1241 	 * reset work will see the pci device disabled when it gets the forced
1242 	 * cancellation error. All outstanding requests are completed on
1243 	 * shutdown, so we return BLK_EH_DONE.
1244 	 */
1245 	switch (dev->ctrl.state) {
1246 	case NVME_CTRL_CONNECTING:
1247 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1248 		/* fall through */
1249 	case NVME_CTRL_DELETING:
1250 		dev_warn_ratelimited(dev->ctrl.device,
1251 			 "I/O %d QID %d timeout, disable controller\n",
1252 			 req->tag, nvmeq->qid);
1253 		nvme_dev_disable(dev, true);
1254 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1255 		return BLK_EH_DONE;
1256 	case NVME_CTRL_RESETTING:
1257 		return BLK_EH_RESET_TIMER;
1258 	default:
1259 		break;
1260 	}
1261 
1262 	/*
1263  	 * Shutdown the controller immediately and schedule a reset if the
1264  	 * command was already aborted once before and still hasn't been
1265  	 * returned to the driver, or if this is the admin queue.
1266 	 */
1267 	if (!nvmeq->qid || iod->aborted) {
1268 		dev_warn(dev->ctrl.device,
1269 			 "I/O %d QID %d timeout, reset controller\n",
1270 			 req->tag, nvmeq->qid);
1271 		nvme_dev_disable(dev, false);
1272 		nvme_reset_ctrl(&dev->ctrl);
1273 
1274 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1275 		return BLK_EH_DONE;
1276 	}
1277 
1278 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1279 		atomic_inc(&dev->ctrl.abort_limit);
1280 		return BLK_EH_RESET_TIMER;
1281 	}
1282 	iod->aborted = 1;
1283 
1284 	memset(&cmd, 0, sizeof(cmd));
1285 	cmd.abort.opcode = nvme_admin_abort_cmd;
1286 	cmd.abort.cid = req->tag;
1287 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1288 
1289 	dev_warn(nvmeq->dev->ctrl.device,
1290 		"I/O %d QID %d timeout, aborting\n",
1291 		 req->tag, nvmeq->qid);
1292 
1293 	abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1294 			BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1295 	if (IS_ERR(abort_req)) {
1296 		atomic_inc(&dev->ctrl.abort_limit);
1297 		return BLK_EH_RESET_TIMER;
1298 	}
1299 
1300 	abort_req->timeout = ADMIN_TIMEOUT;
1301 	abort_req->end_io_data = NULL;
1302 	blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1303 
1304 	/*
1305 	 * The aborted req will be completed on receiving the abort req.
1306 	 * We enable the timer again. If hit twice, it'll cause a device reset,
1307 	 * as the device then is in a faulty state.
1308 	 */
1309 	return BLK_EH_RESET_TIMER;
1310 }
1311 
1312 static void nvme_free_queue(struct nvme_queue *nvmeq)
1313 {
1314 	dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1315 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1316 	if (!nvmeq->sq_cmds)
1317 		return;
1318 
1319 	if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1320 		pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1321 				nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1322 	} else {
1323 		dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1324 				nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1325 	}
1326 }
1327 
1328 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1329 {
1330 	int i;
1331 
1332 	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1333 		dev->ctrl.queue_count--;
1334 		nvme_free_queue(&dev->queues[i]);
1335 	}
1336 }
1337 
1338 /**
1339  * nvme_suspend_queue - put queue into suspended state
1340  * @nvmeq: queue to suspend
1341  */
1342 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1343 {
1344 	if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1345 		return 1;
1346 
1347 	/* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1348 	mb();
1349 
1350 	nvmeq->dev->online_queues--;
1351 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1352 		blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1353 	if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1354 		pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1355 	return 0;
1356 }
1357 
1358 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1359 {
1360 	int i;
1361 
1362 	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1363 		nvme_suspend_queue(&dev->queues[i]);
1364 }
1365 
1366 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1367 {
1368 	struct nvme_queue *nvmeq = &dev->queues[0];
1369 
1370 	if (shutdown)
1371 		nvme_shutdown_ctrl(&dev->ctrl);
1372 	else
1373 		nvme_disable_ctrl(&dev->ctrl);
1374 
1375 	nvme_poll_irqdisable(nvmeq);
1376 }
1377 
1378 /*
1379  * Called only on a device that has been disabled and after all other threads
1380  * that can check this device's completion queues have synced. This is the
1381  * last chance for the driver to see a natural completion before
1382  * nvme_cancel_request() terminates all incomplete requests.
1383  */
1384 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1385 {
1386 	int i;
1387 
1388 	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1389 		nvme_process_cq(&dev->queues[i]);
1390 }
1391 
1392 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1393 				int entry_size)
1394 {
1395 	int q_depth = dev->q_depth;
1396 	unsigned q_size_aligned = roundup(q_depth * entry_size,
1397 					  dev->ctrl.page_size);
1398 
1399 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1400 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1401 		mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1402 		q_depth = div_u64(mem_per_q, entry_size);
1403 
1404 		/*
1405 		 * Ensure the reduced q_depth is above some threshold where it
1406 		 * would be better to map queues in system memory with the
1407 		 * original depth
1408 		 */
1409 		if (q_depth < 64)
1410 			return -ENOMEM;
1411 	}
1412 
1413 	return q_depth;
1414 }
1415 
1416 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1417 				int qid)
1418 {
1419 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1420 
1421 	if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1422 		nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1423 		if (nvmeq->sq_cmds) {
1424 			nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1425 							nvmeq->sq_cmds);
1426 			if (nvmeq->sq_dma_addr) {
1427 				set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1428 				return 0;
1429 			}
1430 
1431 			pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1432 		}
1433 	}
1434 
1435 	nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1436 				&nvmeq->sq_dma_addr, GFP_KERNEL);
1437 	if (!nvmeq->sq_cmds)
1438 		return -ENOMEM;
1439 	return 0;
1440 }
1441 
1442 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1443 {
1444 	struct nvme_queue *nvmeq = &dev->queues[qid];
1445 
1446 	if (dev->ctrl.queue_count > qid)
1447 		return 0;
1448 
1449 	nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1450 	nvmeq->q_depth = depth;
1451 	nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1452 					 &nvmeq->cq_dma_addr, GFP_KERNEL);
1453 	if (!nvmeq->cqes)
1454 		goto free_nvmeq;
1455 
1456 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1457 		goto free_cqdma;
1458 
1459 	nvmeq->dev = dev;
1460 	spin_lock_init(&nvmeq->sq_lock);
1461 	spin_lock_init(&nvmeq->cq_poll_lock);
1462 	nvmeq->cq_head = 0;
1463 	nvmeq->cq_phase = 1;
1464 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1465 	nvmeq->qid = qid;
1466 	dev->ctrl.queue_count++;
1467 
1468 	return 0;
1469 
1470  free_cqdma:
1471 	dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1472 			  nvmeq->cq_dma_addr);
1473  free_nvmeq:
1474 	return -ENOMEM;
1475 }
1476 
1477 static int queue_request_irq(struct nvme_queue *nvmeq)
1478 {
1479 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1480 	int nr = nvmeq->dev->ctrl.instance;
1481 
1482 	if (use_threaded_interrupts) {
1483 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1484 				nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1485 	} else {
1486 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1487 				NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1488 	}
1489 }
1490 
1491 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1492 {
1493 	struct nvme_dev *dev = nvmeq->dev;
1494 
1495 	nvmeq->sq_tail = 0;
1496 	nvmeq->last_sq_tail = 0;
1497 	nvmeq->cq_head = 0;
1498 	nvmeq->cq_phase = 1;
1499 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1500 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1501 	nvme_dbbuf_init(dev, nvmeq, qid);
1502 	dev->online_queues++;
1503 	wmb(); /* ensure the first interrupt sees the initialization */
1504 }
1505 
1506 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1507 {
1508 	struct nvme_dev *dev = nvmeq->dev;
1509 	int result;
1510 	u16 vector = 0;
1511 
1512 	clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1513 
1514 	/*
1515 	 * A queue's vector matches the queue identifier unless the controller
1516 	 * has only one vector available.
1517 	 */
1518 	if (!polled)
1519 		vector = dev->num_vecs == 1 ? 0 : qid;
1520 	else
1521 		set_bit(NVMEQ_POLLED, &nvmeq->flags);
1522 
1523 	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1524 	if (result)
1525 		return result;
1526 
1527 	result = adapter_alloc_sq(dev, qid, nvmeq);
1528 	if (result < 0)
1529 		return result;
1530 	if (result)
1531 		goto release_cq;
1532 
1533 	nvmeq->cq_vector = vector;
1534 	nvme_init_queue(nvmeq, qid);
1535 
1536 	if (!polled) {
1537 		result = queue_request_irq(nvmeq);
1538 		if (result < 0)
1539 			goto release_sq;
1540 	}
1541 
1542 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1543 	return result;
1544 
1545 release_sq:
1546 	dev->online_queues--;
1547 	adapter_delete_sq(dev, qid);
1548 release_cq:
1549 	adapter_delete_cq(dev, qid);
1550 	return result;
1551 }
1552 
1553 static const struct blk_mq_ops nvme_mq_admin_ops = {
1554 	.queue_rq	= nvme_queue_rq,
1555 	.complete	= nvme_pci_complete_rq,
1556 	.init_hctx	= nvme_admin_init_hctx,
1557 	.init_request	= nvme_init_request,
1558 	.timeout	= nvme_timeout,
1559 };
1560 
1561 static const struct blk_mq_ops nvme_mq_ops = {
1562 	.queue_rq	= nvme_queue_rq,
1563 	.complete	= nvme_pci_complete_rq,
1564 	.commit_rqs	= nvme_commit_rqs,
1565 	.init_hctx	= nvme_init_hctx,
1566 	.init_request	= nvme_init_request,
1567 	.map_queues	= nvme_pci_map_queues,
1568 	.timeout	= nvme_timeout,
1569 	.poll		= nvme_poll,
1570 };
1571 
1572 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1573 {
1574 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1575 		/*
1576 		 * If the controller was reset during removal, it's possible
1577 		 * user requests may be waiting on a stopped queue. Start the
1578 		 * queue to flush these to completion.
1579 		 */
1580 		blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1581 		blk_cleanup_queue(dev->ctrl.admin_q);
1582 		blk_mq_free_tag_set(&dev->admin_tagset);
1583 	}
1584 }
1585 
1586 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1587 {
1588 	if (!dev->ctrl.admin_q) {
1589 		dev->admin_tagset.ops = &nvme_mq_admin_ops;
1590 		dev->admin_tagset.nr_hw_queues = 1;
1591 
1592 		dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1593 		dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1594 		dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1595 		dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1596 		dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1597 		dev->admin_tagset.driver_data = dev;
1598 
1599 		if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1600 			return -ENOMEM;
1601 		dev->ctrl.admin_tagset = &dev->admin_tagset;
1602 
1603 		dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1604 		if (IS_ERR(dev->ctrl.admin_q)) {
1605 			blk_mq_free_tag_set(&dev->admin_tagset);
1606 			return -ENOMEM;
1607 		}
1608 		if (!blk_get_queue(dev->ctrl.admin_q)) {
1609 			nvme_dev_remove_admin(dev);
1610 			dev->ctrl.admin_q = NULL;
1611 			return -ENODEV;
1612 		}
1613 	} else
1614 		blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1615 
1616 	return 0;
1617 }
1618 
1619 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1620 {
1621 	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1622 }
1623 
1624 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1625 {
1626 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1627 
1628 	if (size <= dev->bar_mapped_size)
1629 		return 0;
1630 	if (size > pci_resource_len(pdev, 0))
1631 		return -ENOMEM;
1632 	if (dev->bar)
1633 		iounmap(dev->bar);
1634 	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1635 	if (!dev->bar) {
1636 		dev->bar_mapped_size = 0;
1637 		return -ENOMEM;
1638 	}
1639 	dev->bar_mapped_size = size;
1640 	dev->dbs = dev->bar + NVME_REG_DBS;
1641 
1642 	return 0;
1643 }
1644 
1645 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1646 {
1647 	int result;
1648 	u32 aqa;
1649 	struct nvme_queue *nvmeq;
1650 
1651 	result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1652 	if (result < 0)
1653 		return result;
1654 
1655 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1656 				NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1657 
1658 	if (dev->subsystem &&
1659 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1660 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1661 
1662 	result = nvme_disable_ctrl(&dev->ctrl);
1663 	if (result < 0)
1664 		return result;
1665 
1666 	result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1667 	if (result)
1668 		return result;
1669 
1670 	nvmeq = &dev->queues[0];
1671 	aqa = nvmeq->q_depth - 1;
1672 	aqa |= aqa << 16;
1673 
1674 	writel(aqa, dev->bar + NVME_REG_AQA);
1675 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1676 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1677 
1678 	result = nvme_enable_ctrl(&dev->ctrl);
1679 	if (result)
1680 		return result;
1681 
1682 	nvmeq->cq_vector = 0;
1683 	nvme_init_queue(nvmeq, 0);
1684 	result = queue_request_irq(nvmeq);
1685 	if (result) {
1686 		dev->online_queues--;
1687 		return result;
1688 	}
1689 
1690 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1691 	return result;
1692 }
1693 
1694 static int nvme_create_io_queues(struct nvme_dev *dev)
1695 {
1696 	unsigned i, max, rw_queues;
1697 	int ret = 0;
1698 
1699 	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1700 		if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1701 			ret = -ENOMEM;
1702 			break;
1703 		}
1704 	}
1705 
1706 	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1707 	if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1708 		rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1709 				dev->io_queues[HCTX_TYPE_READ];
1710 	} else {
1711 		rw_queues = max;
1712 	}
1713 
1714 	for (i = dev->online_queues; i <= max; i++) {
1715 		bool polled = i > rw_queues;
1716 
1717 		ret = nvme_create_queue(&dev->queues[i], i, polled);
1718 		if (ret)
1719 			break;
1720 	}
1721 
1722 	/*
1723 	 * Ignore failing Create SQ/CQ commands, we can continue with less
1724 	 * than the desired amount of queues, and even a controller without
1725 	 * I/O queues can still be used to issue admin commands.  This might
1726 	 * be useful to upgrade a buggy firmware for example.
1727 	 */
1728 	return ret >= 0 ? 0 : ret;
1729 }
1730 
1731 static ssize_t nvme_cmb_show(struct device *dev,
1732 			     struct device_attribute *attr,
1733 			     char *buf)
1734 {
1735 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1736 
1737 	return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1738 		       ndev->cmbloc, ndev->cmbsz);
1739 }
1740 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1741 
1742 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1743 {
1744 	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1745 
1746 	return 1ULL << (12 + 4 * szu);
1747 }
1748 
1749 static u32 nvme_cmb_size(struct nvme_dev *dev)
1750 {
1751 	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1752 }
1753 
1754 static void nvme_map_cmb(struct nvme_dev *dev)
1755 {
1756 	u64 size, offset;
1757 	resource_size_t bar_size;
1758 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1759 	int bar;
1760 
1761 	if (dev->cmb_size)
1762 		return;
1763 
1764 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1765 	if (!dev->cmbsz)
1766 		return;
1767 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1768 
1769 	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1770 	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1771 	bar = NVME_CMB_BIR(dev->cmbloc);
1772 	bar_size = pci_resource_len(pdev, bar);
1773 
1774 	if (offset > bar_size)
1775 		return;
1776 
1777 	/*
1778 	 * Controllers may support a CMB size larger than their BAR,
1779 	 * for example, due to being behind a bridge. Reduce the CMB to
1780 	 * the reported size of the BAR
1781 	 */
1782 	if (size > bar_size - offset)
1783 		size = bar_size - offset;
1784 
1785 	if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1786 		dev_warn(dev->ctrl.device,
1787 			 "failed to register the CMB\n");
1788 		return;
1789 	}
1790 
1791 	dev->cmb_size = size;
1792 	dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1793 
1794 	if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1795 			(NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1796 		pci_p2pmem_publish(pdev, true);
1797 
1798 	if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1799 				    &dev_attr_cmb.attr, NULL))
1800 		dev_warn(dev->ctrl.device,
1801 			 "failed to add sysfs attribute for CMB\n");
1802 }
1803 
1804 static inline void nvme_release_cmb(struct nvme_dev *dev)
1805 {
1806 	if (dev->cmb_size) {
1807 		sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1808 					     &dev_attr_cmb.attr, NULL);
1809 		dev->cmb_size = 0;
1810 	}
1811 }
1812 
1813 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1814 {
1815 	u64 dma_addr = dev->host_mem_descs_dma;
1816 	struct nvme_command c;
1817 	int ret;
1818 
1819 	memset(&c, 0, sizeof(c));
1820 	c.features.opcode	= nvme_admin_set_features;
1821 	c.features.fid		= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1822 	c.features.dword11	= cpu_to_le32(bits);
1823 	c.features.dword12	= cpu_to_le32(dev->host_mem_size >>
1824 					      ilog2(dev->ctrl.page_size));
1825 	c.features.dword13	= cpu_to_le32(lower_32_bits(dma_addr));
1826 	c.features.dword14	= cpu_to_le32(upper_32_bits(dma_addr));
1827 	c.features.dword15	= cpu_to_le32(dev->nr_host_mem_descs);
1828 
1829 	ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1830 	if (ret) {
1831 		dev_warn(dev->ctrl.device,
1832 			 "failed to set host mem (err %d, flags %#x).\n",
1833 			 ret, bits);
1834 	}
1835 	return ret;
1836 }
1837 
1838 static void nvme_free_host_mem(struct nvme_dev *dev)
1839 {
1840 	int i;
1841 
1842 	for (i = 0; i < dev->nr_host_mem_descs; i++) {
1843 		struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1844 		size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1845 
1846 		dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1847 			       le64_to_cpu(desc->addr),
1848 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1849 	}
1850 
1851 	kfree(dev->host_mem_desc_bufs);
1852 	dev->host_mem_desc_bufs = NULL;
1853 	dma_free_coherent(dev->dev,
1854 			dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1855 			dev->host_mem_descs, dev->host_mem_descs_dma);
1856 	dev->host_mem_descs = NULL;
1857 	dev->nr_host_mem_descs = 0;
1858 }
1859 
1860 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1861 		u32 chunk_size)
1862 {
1863 	struct nvme_host_mem_buf_desc *descs;
1864 	u32 max_entries, len;
1865 	dma_addr_t descs_dma;
1866 	int i = 0;
1867 	void **bufs;
1868 	u64 size, tmp;
1869 
1870 	tmp = (preferred + chunk_size - 1);
1871 	do_div(tmp, chunk_size);
1872 	max_entries = tmp;
1873 
1874 	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1875 		max_entries = dev->ctrl.hmmaxd;
1876 
1877 	descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1878 				   &descs_dma, GFP_KERNEL);
1879 	if (!descs)
1880 		goto out;
1881 
1882 	bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1883 	if (!bufs)
1884 		goto out_free_descs;
1885 
1886 	for (size = 0; size < preferred && i < max_entries; size += len) {
1887 		dma_addr_t dma_addr;
1888 
1889 		len = min_t(u64, chunk_size, preferred - size);
1890 		bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1891 				DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1892 		if (!bufs[i])
1893 			break;
1894 
1895 		descs[i].addr = cpu_to_le64(dma_addr);
1896 		descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1897 		i++;
1898 	}
1899 
1900 	if (!size)
1901 		goto out_free_bufs;
1902 
1903 	dev->nr_host_mem_descs = i;
1904 	dev->host_mem_size = size;
1905 	dev->host_mem_descs = descs;
1906 	dev->host_mem_descs_dma = descs_dma;
1907 	dev->host_mem_desc_bufs = bufs;
1908 	return 0;
1909 
1910 out_free_bufs:
1911 	while (--i >= 0) {
1912 		size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1913 
1914 		dma_free_attrs(dev->dev, size, bufs[i],
1915 			       le64_to_cpu(descs[i].addr),
1916 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1917 	}
1918 
1919 	kfree(bufs);
1920 out_free_descs:
1921 	dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1922 			descs_dma);
1923 out:
1924 	dev->host_mem_descs = NULL;
1925 	return -ENOMEM;
1926 }
1927 
1928 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1929 {
1930 	u32 chunk_size;
1931 
1932 	/* start big and work our way down */
1933 	for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1934 	     chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
1935 	     chunk_size /= 2) {
1936 		if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
1937 			if (!min || dev->host_mem_size >= min)
1938 				return 0;
1939 			nvme_free_host_mem(dev);
1940 		}
1941 	}
1942 
1943 	return -ENOMEM;
1944 }
1945 
1946 static int nvme_setup_host_mem(struct nvme_dev *dev)
1947 {
1948 	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1949 	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1950 	u64 min = (u64)dev->ctrl.hmmin * 4096;
1951 	u32 enable_bits = NVME_HOST_MEM_ENABLE;
1952 	int ret;
1953 
1954 	preferred = min(preferred, max);
1955 	if (min > max) {
1956 		dev_warn(dev->ctrl.device,
1957 			"min host memory (%lld MiB) above limit (%d MiB).\n",
1958 			min >> ilog2(SZ_1M), max_host_mem_size_mb);
1959 		nvme_free_host_mem(dev);
1960 		return 0;
1961 	}
1962 
1963 	/*
1964 	 * If we already have a buffer allocated check if we can reuse it.
1965 	 */
1966 	if (dev->host_mem_descs) {
1967 		if (dev->host_mem_size >= min)
1968 			enable_bits |= NVME_HOST_MEM_RETURN;
1969 		else
1970 			nvme_free_host_mem(dev);
1971 	}
1972 
1973 	if (!dev->host_mem_descs) {
1974 		if (nvme_alloc_host_mem(dev, min, preferred)) {
1975 			dev_warn(dev->ctrl.device,
1976 				"failed to allocate host memory buffer.\n");
1977 			return 0; /* controller must work without HMB */
1978 		}
1979 
1980 		dev_info(dev->ctrl.device,
1981 			"allocated %lld MiB host memory buffer.\n",
1982 			dev->host_mem_size >> ilog2(SZ_1M));
1983 	}
1984 
1985 	ret = nvme_set_host_mem(dev, enable_bits);
1986 	if (ret)
1987 		nvme_free_host_mem(dev);
1988 	return ret;
1989 }
1990 
1991 /*
1992  * nirqs is the number of interrupts available for write and read
1993  * queues. The core already reserved an interrupt for the admin queue.
1994  */
1995 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
1996 {
1997 	struct nvme_dev *dev = affd->priv;
1998 	unsigned int nr_read_queues;
1999 
2000 	/*
2001 	 * If there is no interupt available for queues, ensure that
2002 	 * the default queue is set to 1. The affinity set size is
2003 	 * also set to one, but the irq core ignores it for this case.
2004 	 *
2005 	 * If only one interrupt is available or 'write_queue' == 0, combine
2006 	 * write and read queues.
2007 	 *
2008 	 * If 'write_queues' > 0, ensure it leaves room for at least one read
2009 	 * queue.
2010 	 */
2011 	if (!nrirqs) {
2012 		nrirqs = 1;
2013 		nr_read_queues = 0;
2014 	} else if (nrirqs == 1 || !write_queues) {
2015 		nr_read_queues = 0;
2016 	} else if (write_queues >= nrirqs) {
2017 		nr_read_queues = 1;
2018 	} else {
2019 		nr_read_queues = nrirqs - write_queues;
2020 	}
2021 
2022 	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2023 	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2024 	dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2025 	affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2026 	affd->nr_sets = nr_read_queues ? 2 : 1;
2027 }
2028 
2029 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2030 {
2031 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2032 	struct irq_affinity affd = {
2033 		.pre_vectors	= 1,
2034 		.calc_sets	= nvme_calc_irq_sets,
2035 		.priv		= dev,
2036 	};
2037 	unsigned int irq_queues, this_p_queues;
2038 
2039 	/*
2040 	 * Poll queues don't need interrupts, but we need at least one IO
2041 	 * queue left over for non-polled IO.
2042 	 */
2043 	this_p_queues = poll_queues;
2044 	if (this_p_queues >= nr_io_queues) {
2045 		this_p_queues = nr_io_queues - 1;
2046 		irq_queues = 1;
2047 	} else {
2048 		irq_queues = nr_io_queues - this_p_queues + 1;
2049 	}
2050 	dev->io_queues[HCTX_TYPE_POLL] = this_p_queues;
2051 
2052 	/* Initialize for the single interrupt case */
2053 	dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2054 	dev->io_queues[HCTX_TYPE_READ] = 0;
2055 
2056 	/*
2057 	 * Some Apple controllers require all queues to use the
2058 	 * first vector.
2059 	 */
2060 	if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)
2061 		irq_queues = 1;
2062 
2063 	return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2064 			      PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2065 }
2066 
2067 static void nvme_disable_io_queues(struct nvme_dev *dev)
2068 {
2069 	if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2070 		__nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2071 }
2072 
2073 static int nvme_setup_io_queues(struct nvme_dev *dev)
2074 {
2075 	struct nvme_queue *adminq = &dev->queues[0];
2076 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2077 	int result, nr_io_queues;
2078 	unsigned long size;
2079 
2080 	nr_io_queues = max_io_queues();
2081 
2082 	/*
2083 	 * If tags are shared with admin queue (Apple bug), then
2084 	 * make sure we only use one IO queue.
2085 	 */
2086 	if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2087 		nr_io_queues = 1;
2088 
2089 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2090 	if (result < 0)
2091 		return result;
2092 
2093 	if (nr_io_queues == 0)
2094 		return 0;
2095 
2096 	clear_bit(NVMEQ_ENABLED, &adminq->flags);
2097 
2098 	if (dev->cmb_use_sqes) {
2099 		result = nvme_cmb_qdepth(dev, nr_io_queues,
2100 				sizeof(struct nvme_command));
2101 		if (result > 0)
2102 			dev->q_depth = result;
2103 		else
2104 			dev->cmb_use_sqes = false;
2105 	}
2106 
2107 	do {
2108 		size = db_bar_size(dev, nr_io_queues);
2109 		result = nvme_remap_bar(dev, size);
2110 		if (!result)
2111 			break;
2112 		if (!--nr_io_queues)
2113 			return -ENOMEM;
2114 	} while (1);
2115 	adminq->q_db = dev->dbs;
2116 
2117  retry:
2118 	/* Deregister the admin queue's interrupt */
2119 	pci_free_irq(pdev, 0, adminq);
2120 
2121 	/*
2122 	 * If we enable msix early due to not intx, disable it again before
2123 	 * setting up the full range we need.
2124 	 */
2125 	pci_free_irq_vectors(pdev);
2126 
2127 	result = nvme_setup_irqs(dev, nr_io_queues);
2128 	if (result <= 0)
2129 		return -EIO;
2130 
2131 	dev->num_vecs = result;
2132 	result = max(result - 1, 1);
2133 	dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2134 
2135 	/*
2136 	 * Should investigate if there's a performance win from allocating
2137 	 * more queues than interrupt vectors; it might allow the submission
2138 	 * path to scale better, even if the receive path is limited by the
2139 	 * number of interrupts.
2140 	 */
2141 	result = queue_request_irq(adminq);
2142 	if (result)
2143 		return result;
2144 	set_bit(NVMEQ_ENABLED, &adminq->flags);
2145 
2146 	result = nvme_create_io_queues(dev);
2147 	if (result || dev->online_queues < 2)
2148 		return result;
2149 
2150 	if (dev->online_queues - 1 < dev->max_qid) {
2151 		nr_io_queues = dev->online_queues - 1;
2152 		nvme_disable_io_queues(dev);
2153 		nvme_suspend_io_queues(dev);
2154 		goto retry;
2155 	}
2156 	dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2157 					dev->io_queues[HCTX_TYPE_DEFAULT],
2158 					dev->io_queues[HCTX_TYPE_READ],
2159 					dev->io_queues[HCTX_TYPE_POLL]);
2160 	return 0;
2161 }
2162 
2163 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2164 {
2165 	struct nvme_queue *nvmeq = req->end_io_data;
2166 
2167 	blk_mq_free_request(req);
2168 	complete(&nvmeq->delete_done);
2169 }
2170 
2171 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2172 {
2173 	struct nvme_queue *nvmeq = req->end_io_data;
2174 
2175 	if (error)
2176 		set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2177 
2178 	nvme_del_queue_end(req, error);
2179 }
2180 
2181 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2182 {
2183 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2184 	struct request *req;
2185 	struct nvme_command cmd;
2186 
2187 	memset(&cmd, 0, sizeof(cmd));
2188 	cmd.delete_queue.opcode = opcode;
2189 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2190 
2191 	req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
2192 	if (IS_ERR(req))
2193 		return PTR_ERR(req);
2194 
2195 	req->timeout = ADMIN_TIMEOUT;
2196 	req->end_io_data = nvmeq;
2197 
2198 	init_completion(&nvmeq->delete_done);
2199 	blk_execute_rq_nowait(q, NULL, req, false,
2200 			opcode == nvme_admin_delete_cq ?
2201 				nvme_del_cq_end : nvme_del_queue_end);
2202 	return 0;
2203 }
2204 
2205 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2206 {
2207 	int nr_queues = dev->online_queues - 1, sent = 0;
2208 	unsigned long timeout;
2209 
2210  retry:
2211 	timeout = ADMIN_TIMEOUT;
2212 	while (nr_queues > 0) {
2213 		if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2214 			break;
2215 		nr_queues--;
2216 		sent++;
2217 	}
2218 	while (sent) {
2219 		struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2220 
2221 		timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2222 				timeout);
2223 		if (timeout == 0)
2224 			return false;
2225 
2226 		sent--;
2227 		if (nr_queues)
2228 			goto retry;
2229 	}
2230 	return true;
2231 }
2232 
2233 static void nvme_dev_add(struct nvme_dev *dev)
2234 {
2235 	int ret;
2236 
2237 	if (!dev->ctrl.tagset) {
2238 		dev->tagset.ops = &nvme_mq_ops;
2239 		dev->tagset.nr_hw_queues = dev->online_queues - 1;
2240 		dev->tagset.nr_maps = 2; /* default + read */
2241 		if (dev->io_queues[HCTX_TYPE_POLL])
2242 			dev->tagset.nr_maps++;
2243 		dev->tagset.timeout = NVME_IO_TIMEOUT;
2244 		dev->tagset.numa_node = dev_to_node(dev->dev);
2245 		dev->tagset.queue_depth =
2246 				min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2247 		dev->tagset.cmd_size = sizeof(struct nvme_iod);
2248 		dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2249 		dev->tagset.driver_data = dev;
2250 
2251 		/*
2252 		 * Some Apple controllers requires tags to be unique
2253 		 * across admin and IO queue, so reserve the first 32
2254 		 * tags of the IO queue.
2255 		 */
2256 		if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2257 			dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2258 
2259 		ret = blk_mq_alloc_tag_set(&dev->tagset);
2260 		if (ret) {
2261 			dev_warn(dev->ctrl.device,
2262 				"IO queues tagset allocation failed %d\n", ret);
2263 			return;
2264 		}
2265 		dev->ctrl.tagset = &dev->tagset;
2266 	} else {
2267 		blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2268 
2269 		/* Free previously allocated queues that are no longer usable */
2270 		nvme_free_queues(dev, dev->online_queues);
2271 	}
2272 
2273 	nvme_dbbuf_set(dev);
2274 }
2275 
2276 static int nvme_pci_enable(struct nvme_dev *dev)
2277 {
2278 	int result = -ENOMEM;
2279 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2280 
2281 	if (pci_enable_device_mem(pdev))
2282 		return result;
2283 
2284 	pci_set_master(pdev);
2285 
2286 	if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)))
2287 		goto disable;
2288 
2289 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2290 		result = -ENODEV;
2291 		goto disable;
2292 	}
2293 
2294 	/*
2295 	 * Some devices and/or platforms don't advertise or work with INTx
2296 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2297 	 * adjust this later.
2298 	 */
2299 	result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2300 	if (result < 0)
2301 		return result;
2302 
2303 	dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2304 
2305 	dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2306 				io_queue_depth);
2307 	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2308 	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2309 	dev->dbs = dev->bar + 4096;
2310 
2311 	/*
2312 	 * Some Apple controllers require a non-standard SQE size.
2313 	 * Interestingly they also seem to ignore the CC:IOSQES register
2314 	 * so we don't bother updating it here.
2315 	 */
2316 	if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2317 		dev->io_sqes = 7;
2318 	else
2319 		dev->io_sqes = NVME_NVM_IOSQES;
2320 
2321 	/*
2322 	 * Temporary fix for the Apple controller found in the MacBook8,1 and
2323 	 * some MacBook7,1 to avoid controller resets and data loss.
2324 	 */
2325 	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2326 		dev->q_depth = 2;
2327 		dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2328 			"set queue depth=%u to work around controller resets\n",
2329 			dev->q_depth);
2330 	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2331 		   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2332 		   NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2333 		dev->q_depth = 64;
2334 		dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2335                         "set queue depth=%u\n", dev->q_depth);
2336 	}
2337 
2338 	/*
2339 	 * Controllers with the shared tags quirk need the IO queue to be
2340 	 * big enough so that we get 32 tags for the admin queue
2341 	 */
2342 	if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2343 	    (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2344 		dev->q_depth = NVME_AQ_DEPTH + 2;
2345 		dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2346 			 dev->q_depth);
2347 	}
2348 
2349 
2350 	nvme_map_cmb(dev);
2351 
2352 	pci_enable_pcie_error_reporting(pdev);
2353 	pci_save_state(pdev);
2354 	return 0;
2355 
2356  disable:
2357 	pci_disable_device(pdev);
2358 	return result;
2359 }
2360 
2361 static void nvme_dev_unmap(struct nvme_dev *dev)
2362 {
2363 	if (dev->bar)
2364 		iounmap(dev->bar);
2365 	pci_release_mem_regions(to_pci_dev(dev->dev));
2366 }
2367 
2368 static void nvme_pci_disable(struct nvme_dev *dev)
2369 {
2370 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2371 
2372 	pci_free_irq_vectors(pdev);
2373 
2374 	if (pci_is_enabled(pdev)) {
2375 		pci_disable_pcie_error_reporting(pdev);
2376 		pci_disable_device(pdev);
2377 	}
2378 }
2379 
2380 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2381 {
2382 	bool dead = true, freeze = false;
2383 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2384 
2385 	mutex_lock(&dev->shutdown_lock);
2386 	if (pci_is_enabled(pdev)) {
2387 		u32 csts = readl(dev->bar + NVME_REG_CSTS);
2388 
2389 		if (dev->ctrl.state == NVME_CTRL_LIVE ||
2390 		    dev->ctrl.state == NVME_CTRL_RESETTING) {
2391 			freeze = true;
2392 			nvme_start_freeze(&dev->ctrl);
2393 		}
2394 		dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2395 			pdev->error_state  != pci_channel_io_normal);
2396 	}
2397 
2398 	/*
2399 	 * Give the controller a chance to complete all entered requests if
2400 	 * doing a safe shutdown.
2401 	 */
2402 	if (!dead && shutdown && freeze)
2403 		nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2404 
2405 	nvme_stop_queues(&dev->ctrl);
2406 
2407 	if (!dead && dev->ctrl.queue_count > 0) {
2408 		nvme_disable_io_queues(dev);
2409 		nvme_disable_admin_queue(dev, shutdown);
2410 	}
2411 	nvme_suspend_io_queues(dev);
2412 	nvme_suspend_queue(&dev->queues[0]);
2413 	nvme_pci_disable(dev);
2414 	nvme_reap_pending_cqes(dev);
2415 
2416 	blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2417 	blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2418 	blk_mq_tagset_wait_completed_request(&dev->tagset);
2419 	blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2420 
2421 	/*
2422 	 * The driver will not be starting up queues again if shutting down so
2423 	 * must flush all entered requests to their failed completion to avoid
2424 	 * deadlocking blk-mq hot-cpu notifier.
2425 	 */
2426 	if (shutdown) {
2427 		nvme_start_queues(&dev->ctrl);
2428 		if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2429 			blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2430 	}
2431 	mutex_unlock(&dev->shutdown_lock);
2432 }
2433 
2434 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2435 {
2436 	if (!nvme_wait_reset(&dev->ctrl))
2437 		return -EBUSY;
2438 	nvme_dev_disable(dev, shutdown);
2439 	return 0;
2440 }
2441 
2442 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2443 {
2444 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2445 						PAGE_SIZE, PAGE_SIZE, 0);
2446 	if (!dev->prp_page_pool)
2447 		return -ENOMEM;
2448 
2449 	/* Optimisation for I/Os between 4k and 128k */
2450 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2451 						256, 256, 0);
2452 	if (!dev->prp_small_pool) {
2453 		dma_pool_destroy(dev->prp_page_pool);
2454 		return -ENOMEM;
2455 	}
2456 	return 0;
2457 }
2458 
2459 static void nvme_release_prp_pools(struct nvme_dev *dev)
2460 {
2461 	dma_pool_destroy(dev->prp_page_pool);
2462 	dma_pool_destroy(dev->prp_small_pool);
2463 }
2464 
2465 static void nvme_free_tagset(struct nvme_dev *dev)
2466 {
2467 	if (dev->tagset.tags)
2468 		blk_mq_free_tag_set(&dev->tagset);
2469 	dev->ctrl.tagset = NULL;
2470 }
2471 
2472 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2473 {
2474 	struct nvme_dev *dev = to_nvme_dev(ctrl);
2475 
2476 	nvme_dbbuf_dma_free(dev);
2477 	nvme_free_tagset(dev);
2478 	if (dev->ctrl.admin_q)
2479 		blk_put_queue(dev->ctrl.admin_q);
2480 	free_opal_dev(dev->ctrl.opal_dev);
2481 	mempool_destroy(dev->iod_mempool);
2482 	put_device(dev->dev);
2483 	kfree(dev->queues);
2484 	kfree(dev);
2485 }
2486 
2487 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2488 {
2489 	/*
2490 	 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2491 	 * may be holding this pci_dev's device lock.
2492 	 */
2493 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2494 	nvme_get_ctrl(&dev->ctrl);
2495 	nvme_dev_disable(dev, false);
2496 	nvme_kill_queues(&dev->ctrl);
2497 	if (!queue_work(nvme_wq, &dev->remove_work))
2498 		nvme_put_ctrl(&dev->ctrl);
2499 }
2500 
2501 static void nvme_reset_work(struct work_struct *work)
2502 {
2503 	struct nvme_dev *dev =
2504 		container_of(work, struct nvme_dev, ctrl.reset_work);
2505 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2506 	int result;
2507 
2508 	if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) {
2509 		result = -ENODEV;
2510 		goto out;
2511 	}
2512 
2513 	/*
2514 	 * If we're called to reset a live controller first shut it down before
2515 	 * moving on.
2516 	 */
2517 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2518 		nvme_dev_disable(dev, false);
2519 	nvme_sync_queues(&dev->ctrl);
2520 
2521 	mutex_lock(&dev->shutdown_lock);
2522 	result = nvme_pci_enable(dev);
2523 	if (result)
2524 		goto out_unlock;
2525 
2526 	result = nvme_pci_configure_admin_queue(dev);
2527 	if (result)
2528 		goto out_unlock;
2529 
2530 	result = nvme_alloc_admin_tags(dev);
2531 	if (result)
2532 		goto out_unlock;
2533 
2534 	/*
2535 	 * Limit the max command size to prevent iod->sg allocations going
2536 	 * over a single page.
2537 	 */
2538 	dev->ctrl.max_hw_sectors = min_t(u32,
2539 		NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2540 	dev->ctrl.max_segments = NVME_MAX_SEGS;
2541 
2542 	/*
2543 	 * Don't limit the IOMMU merged segment size.
2544 	 */
2545 	dma_set_max_seg_size(dev->dev, 0xffffffff);
2546 
2547 	mutex_unlock(&dev->shutdown_lock);
2548 
2549 	/*
2550 	 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2551 	 * initializing procedure here.
2552 	 */
2553 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2554 		dev_warn(dev->ctrl.device,
2555 			"failed to mark controller CONNECTING\n");
2556 		result = -EBUSY;
2557 		goto out;
2558 	}
2559 
2560 	result = nvme_init_identify(&dev->ctrl);
2561 	if (result)
2562 		goto out;
2563 
2564 	if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2565 		if (!dev->ctrl.opal_dev)
2566 			dev->ctrl.opal_dev =
2567 				init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2568 		else if (was_suspend)
2569 			opal_unlock_from_suspend(dev->ctrl.opal_dev);
2570 	} else {
2571 		free_opal_dev(dev->ctrl.opal_dev);
2572 		dev->ctrl.opal_dev = NULL;
2573 	}
2574 
2575 	if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2576 		result = nvme_dbbuf_dma_alloc(dev);
2577 		if (result)
2578 			dev_warn(dev->dev,
2579 				 "unable to allocate dma for dbbuf\n");
2580 	}
2581 
2582 	if (dev->ctrl.hmpre) {
2583 		result = nvme_setup_host_mem(dev);
2584 		if (result < 0)
2585 			goto out;
2586 	}
2587 
2588 	result = nvme_setup_io_queues(dev);
2589 	if (result)
2590 		goto out;
2591 
2592 	/*
2593 	 * Keep the controller around but remove all namespaces if we don't have
2594 	 * any working I/O queue.
2595 	 */
2596 	if (dev->online_queues < 2) {
2597 		dev_warn(dev->ctrl.device, "IO queues not created\n");
2598 		nvme_kill_queues(&dev->ctrl);
2599 		nvme_remove_namespaces(&dev->ctrl);
2600 		nvme_free_tagset(dev);
2601 	} else {
2602 		nvme_start_queues(&dev->ctrl);
2603 		nvme_wait_freeze(&dev->ctrl);
2604 		nvme_dev_add(dev);
2605 		nvme_unfreeze(&dev->ctrl);
2606 	}
2607 
2608 	/*
2609 	 * If only admin queue live, keep it to do further investigation or
2610 	 * recovery.
2611 	 */
2612 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2613 		dev_warn(dev->ctrl.device,
2614 			"failed to mark controller live state\n");
2615 		result = -ENODEV;
2616 		goto out;
2617 	}
2618 
2619 	nvme_start_ctrl(&dev->ctrl);
2620 	return;
2621 
2622  out_unlock:
2623 	mutex_unlock(&dev->shutdown_lock);
2624  out:
2625 	if (result)
2626 		dev_warn(dev->ctrl.device,
2627 			 "Removing after probe failure status: %d\n", result);
2628 	nvme_remove_dead_ctrl(dev);
2629 }
2630 
2631 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2632 {
2633 	struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2634 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2635 
2636 	if (pci_get_drvdata(pdev))
2637 		device_release_driver(&pdev->dev);
2638 	nvme_put_ctrl(&dev->ctrl);
2639 }
2640 
2641 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2642 {
2643 	*val = readl(to_nvme_dev(ctrl)->bar + off);
2644 	return 0;
2645 }
2646 
2647 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2648 {
2649 	writel(val, to_nvme_dev(ctrl)->bar + off);
2650 	return 0;
2651 }
2652 
2653 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2654 {
2655 	*val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2656 	return 0;
2657 }
2658 
2659 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2660 {
2661 	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2662 
2663 	return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2664 }
2665 
2666 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2667 	.name			= "pcie",
2668 	.module			= THIS_MODULE,
2669 	.flags			= NVME_F_METADATA_SUPPORTED |
2670 				  NVME_F_PCI_P2PDMA,
2671 	.reg_read32		= nvme_pci_reg_read32,
2672 	.reg_write32		= nvme_pci_reg_write32,
2673 	.reg_read64		= nvme_pci_reg_read64,
2674 	.free_ctrl		= nvme_pci_free_ctrl,
2675 	.submit_async_event	= nvme_pci_submit_async_event,
2676 	.get_address		= nvme_pci_get_address,
2677 };
2678 
2679 static int nvme_dev_map(struct nvme_dev *dev)
2680 {
2681 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2682 
2683 	if (pci_request_mem_regions(pdev, "nvme"))
2684 		return -ENODEV;
2685 
2686 	if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2687 		goto release;
2688 
2689 	return 0;
2690   release:
2691 	pci_release_mem_regions(pdev);
2692 	return -ENODEV;
2693 }
2694 
2695 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2696 {
2697 	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2698 		/*
2699 		 * Several Samsung devices seem to drop off the PCIe bus
2700 		 * randomly when APST is on and uses the deepest sleep state.
2701 		 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2702 		 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2703 		 * 950 PRO 256GB", but it seems to be restricted to two Dell
2704 		 * laptops.
2705 		 */
2706 		if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2707 		    (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2708 		     dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2709 			return NVME_QUIRK_NO_DEEPEST_PS;
2710 	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2711 		/*
2712 		 * Samsung SSD 960 EVO drops off the PCIe bus after system
2713 		 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2714 		 * within few minutes after bootup on a Coffee Lake board -
2715 		 * ASUS PRIME Z370-A
2716 		 */
2717 		if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2718 		    (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2719 		     dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2720 			return NVME_QUIRK_NO_APST;
2721 	} else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2722 		    pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2723 		   (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2724 		/*
2725 		 * Forcing to use host managed nvme power settings for
2726 		 * lowest idle power with quick resume latency on
2727 		 * Samsung and Toshiba SSDs based on suspend behavior
2728 		 * on Coffee Lake board for LENOVO C640
2729 		 */
2730 		if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2731 		     dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2732 			return NVME_QUIRK_SIMPLE_SUSPEND;
2733 	}
2734 
2735 	return 0;
2736 }
2737 
2738 static void nvme_async_probe(void *data, async_cookie_t cookie)
2739 {
2740 	struct nvme_dev *dev = data;
2741 
2742 	flush_work(&dev->ctrl.reset_work);
2743 	flush_work(&dev->ctrl.scan_work);
2744 	nvme_put_ctrl(&dev->ctrl);
2745 }
2746 
2747 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2748 {
2749 	int node, result = -ENOMEM;
2750 	struct nvme_dev *dev;
2751 	unsigned long quirks = id->driver_data;
2752 	size_t alloc_size;
2753 
2754 	node = dev_to_node(&pdev->dev);
2755 	if (node == NUMA_NO_NODE)
2756 		set_dev_node(&pdev->dev, first_memory_node);
2757 
2758 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2759 	if (!dev)
2760 		return -ENOMEM;
2761 
2762 	dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue),
2763 					GFP_KERNEL, node);
2764 	if (!dev->queues)
2765 		goto free;
2766 
2767 	dev->dev = get_device(&pdev->dev);
2768 	pci_set_drvdata(pdev, dev);
2769 
2770 	result = nvme_dev_map(dev);
2771 	if (result)
2772 		goto put_pci;
2773 
2774 	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2775 	INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2776 	mutex_init(&dev->shutdown_lock);
2777 
2778 	result = nvme_setup_prp_pools(dev);
2779 	if (result)
2780 		goto unmap;
2781 
2782 	quirks |= check_vendor_combination_bug(pdev);
2783 
2784 	/*
2785 	 * Double check that our mempool alloc size will cover the biggest
2786 	 * command we support.
2787 	 */
2788 	alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2789 						NVME_MAX_SEGS, true);
2790 	WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2791 
2792 	dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2793 						mempool_kfree,
2794 						(void *) alloc_size,
2795 						GFP_KERNEL, node);
2796 	if (!dev->iod_mempool) {
2797 		result = -ENOMEM;
2798 		goto release_pools;
2799 	}
2800 
2801 	result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2802 			quirks);
2803 	if (result)
2804 		goto release_mempool;
2805 
2806 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2807 
2808 	nvme_reset_ctrl(&dev->ctrl);
2809 	async_schedule(nvme_async_probe, dev);
2810 
2811 	return 0;
2812 
2813  release_mempool:
2814 	mempool_destroy(dev->iod_mempool);
2815  release_pools:
2816 	nvme_release_prp_pools(dev);
2817  unmap:
2818 	nvme_dev_unmap(dev);
2819  put_pci:
2820 	put_device(dev->dev);
2821  free:
2822 	kfree(dev->queues);
2823 	kfree(dev);
2824 	return result;
2825 }
2826 
2827 static void nvme_reset_prepare(struct pci_dev *pdev)
2828 {
2829 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2830 
2831 	/*
2832 	 * We don't need to check the return value from waiting for the reset
2833 	 * state as pci_dev device lock is held, making it impossible to race
2834 	 * with ->remove().
2835 	 */
2836 	nvme_disable_prepare_reset(dev, false);
2837 	nvme_sync_queues(&dev->ctrl);
2838 }
2839 
2840 static void nvme_reset_done(struct pci_dev *pdev)
2841 {
2842 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2843 
2844 	if (!nvme_try_sched_reset(&dev->ctrl))
2845 		flush_work(&dev->ctrl.reset_work);
2846 }
2847 
2848 static void nvme_shutdown(struct pci_dev *pdev)
2849 {
2850 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2851 	nvme_disable_prepare_reset(dev, true);
2852 }
2853 
2854 /*
2855  * The driver's remove may be called on a device in a partially initialized
2856  * state. This function must not have any dependencies on the device state in
2857  * order to proceed.
2858  */
2859 static void nvme_remove(struct pci_dev *pdev)
2860 {
2861 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2862 
2863 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2864 	pci_set_drvdata(pdev, NULL);
2865 
2866 	if (!pci_device_is_present(pdev)) {
2867 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2868 		nvme_dev_disable(dev, true);
2869 		nvme_dev_remove_admin(dev);
2870 	}
2871 
2872 	flush_work(&dev->ctrl.reset_work);
2873 	nvme_stop_ctrl(&dev->ctrl);
2874 	nvme_remove_namespaces(&dev->ctrl);
2875 	nvme_dev_disable(dev, true);
2876 	nvme_release_cmb(dev);
2877 	nvme_free_host_mem(dev);
2878 	nvme_dev_remove_admin(dev);
2879 	nvme_free_queues(dev, 0);
2880 	nvme_release_prp_pools(dev);
2881 	nvme_dev_unmap(dev);
2882 	nvme_uninit_ctrl(&dev->ctrl);
2883 }
2884 
2885 #ifdef CONFIG_PM_SLEEP
2886 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
2887 {
2888 	return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
2889 }
2890 
2891 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
2892 {
2893 	return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
2894 }
2895 
2896 static int nvme_resume(struct device *dev)
2897 {
2898 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2899 	struct nvme_ctrl *ctrl = &ndev->ctrl;
2900 
2901 	if (ndev->last_ps == U32_MAX ||
2902 	    nvme_set_power_state(ctrl, ndev->last_ps) != 0)
2903 		return nvme_try_sched_reset(&ndev->ctrl);
2904 	return 0;
2905 }
2906 
2907 static int nvme_suspend(struct device *dev)
2908 {
2909 	struct pci_dev *pdev = to_pci_dev(dev);
2910 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
2911 	struct nvme_ctrl *ctrl = &ndev->ctrl;
2912 	int ret = -EBUSY;
2913 
2914 	ndev->last_ps = U32_MAX;
2915 
2916 	/*
2917 	 * The platform does not remove power for a kernel managed suspend so
2918 	 * use host managed nvme power settings for lowest idle power if
2919 	 * possible. This should have quicker resume latency than a full device
2920 	 * shutdown.  But if the firmware is involved after the suspend or the
2921 	 * device does not support any non-default power states, shut down the
2922 	 * device fully.
2923 	 *
2924 	 * If ASPM is not enabled for the device, shut down the device and allow
2925 	 * the PCI bus layer to put it into D3 in order to take the PCIe link
2926 	 * down, so as to allow the platform to achieve its minimum low-power
2927 	 * state (which may not be possible if the link is up).
2928 	 */
2929 	if (pm_suspend_via_firmware() || !ctrl->npss ||
2930 	    !pcie_aspm_enabled(pdev) ||
2931 	    (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
2932 		return nvme_disable_prepare_reset(ndev, true);
2933 
2934 	nvme_start_freeze(ctrl);
2935 	nvme_wait_freeze(ctrl);
2936 	nvme_sync_queues(ctrl);
2937 
2938 	if (ctrl->state != NVME_CTRL_LIVE)
2939 		goto unfreeze;
2940 
2941 	ret = nvme_get_power_state(ctrl, &ndev->last_ps);
2942 	if (ret < 0)
2943 		goto unfreeze;
2944 
2945 	/*
2946 	 * A saved state prevents pci pm from generically controlling the
2947 	 * device's power. If we're using protocol specific settings, we don't
2948 	 * want pci interfering.
2949 	 */
2950 	pci_save_state(pdev);
2951 
2952 	ret = nvme_set_power_state(ctrl, ctrl->npss);
2953 	if (ret < 0)
2954 		goto unfreeze;
2955 
2956 	if (ret) {
2957 		/* discard the saved state */
2958 		pci_load_saved_state(pdev, NULL);
2959 
2960 		/*
2961 		 * Clearing npss forces a controller reset on resume. The
2962 		 * correct value will be rediscovered then.
2963 		 */
2964 		ret = nvme_disable_prepare_reset(ndev, true);
2965 		ctrl->npss = 0;
2966 	}
2967 unfreeze:
2968 	nvme_unfreeze(ctrl);
2969 	return ret;
2970 }
2971 
2972 static int nvme_simple_suspend(struct device *dev)
2973 {
2974 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
2975 	return nvme_disable_prepare_reset(ndev, true);
2976 }
2977 
2978 static int nvme_simple_resume(struct device *dev)
2979 {
2980 	struct pci_dev *pdev = to_pci_dev(dev);
2981 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
2982 
2983 	return nvme_try_sched_reset(&ndev->ctrl);
2984 }
2985 
2986 static const struct dev_pm_ops nvme_dev_pm_ops = {
2987 	.suspend	= nvme_suspend,
2988 	.resume		= nvme_resume,
2989 	.freeze		= nvme_simple_suspend,
2990 	.thaw		= nvme_simple_resume,
2991 	.poweroff	= nvme_simple_suspend,
2992 	.restore	= nvme_simple_resume,
2993 };
2994 #endif /* CONFIG_PM_SLEEP */
2995 
2996 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2997 						pci_channel_state_t state)
2998 {
2999 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3000 
3001 	/*
3002 	 * A frozen channel requires a reset. When detected, this method will
3003 	 * shutdown the controller to quiesce. The controller will be restarted
3004 	 * after the slot reset through driver's slot_reset callback.
3005 	 */
3006 	switch (state) {
3007 	case pci_channel_io_normal:
3008 		return PCI_ERS_RESULT_CAN_RECOVER;
3009 	case pci_channel_io_frozen:
3010 		dev_warn(dev->ctrl.device,
3011 			"frozen state error detected, reset controller\n");
3012 		nvme_dev_disable(dev, false);
3013 		return PCI_ERS_RESULT_NEED_RESET;
3014 	case pci_channel_io_perm_failure:
3015 		dev_warn(dev->ctrl.device,
3016 			"failure state error detected, request disconnect\n");
3017 		return PCI_ERS_RESULT_DISCONNECT;
3018 	}
3019 	return PCI_ERS_RESULT_NEED_RESET;
3020 }
3021 
3022 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3023 {
3024 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3025 
3026 	dev_info(dev->ctrl.device, "restart after slot reset\n");
3027 	pci_restore_state(pdev);
3028 	nvme_reset_ctrl(&dev->ctrl);
3029 	return PCI_ERS_RESULT_RECOVERED;
3030 }
3031 
3032 static void nvme_error_resume(struct pci_dev *pdev)
3033 {
3034 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3035 
3036 	flush_work(&dev->ctrl.reset_work);
3037 }
3038 
3039 static const struct pci_error_handlers nvme_err_handler = {
3040 	.error_detected	= nvme_error_detected,
3041 	.slot_reset	= nvme_slot_reset,
3042 	.resume		= nvme_error_resume,
3043 	.reset_prepare	= nvme_reset_prepare,
3044 	.reset_done	= nvme_reset_done,
3045 };
3046 
3047 static const struct pci_device_id nvme_id_table[] = {
3048 	{ PCI_VDEVICE(INTEL, 0x0953),
3049 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3050 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3051 	{ PCI_VDEVICE(INTEL, 0x0a53),
3052 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3053 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3054 	{ PCI_VDEVICE(INTEL, 0x0a54),
3055 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3056 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3057 	{ PCI_VDEVICE(INTEL, 0x0a55),
3058 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3059 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3060 	{ PCI_VDEVICE(INTEL, 0xf1a5),	/* Intel 600P/P3100 */
3061 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3062 				NVME_QUIRK_MEDIUM_PRIO_SQ |
3063 				NVME_QUIRK_NO_TEMP_THRESH_CHANGE },
3064 	{ PCI_VDEVICE(INTEL, 0xf1a6),	/* Intel 760p/Pro 7600p */
3065 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3066 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
3067 		.driver_data = NVME_QUIRK_IDENTIFY_CNS |
3068 				NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3069 	{ PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3070 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3071 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
3072 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3073 	{ PCI_DEVICE(0x1c58, 0x0023),	/* WDC SN200 adapter */
3074 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3075 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
3076 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3077 	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3078 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3079 	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3080 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3081 	{ PCI_DEVICE(0x1d1d, 0x1f1f),	/* LighNVM qemu device */
3082 		.driver_data = NVME_QUIRK_LIGHTNVM, },
3083 	{ PCI_DEVICE(0x1d1d, 0x2807),	/* CNEX WL */
3084 		.driver_data = NVME_QUIRK_LIGHTNVM, },
3085 	{ PCI_DEVICE(0x1d1d, 0x2601),	/* CNEX Granby */
3086 		.driver_data = NVME_QUIRK_LIGHTNVM, },
3087 	{ PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3088 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3089 	{ PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3090 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3091 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3092 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3093 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3094 		.driver_data = NVME_QUIRK_SINGLE_VECTOR },
3095 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3096 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3097 		.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3098 				NVME_QUIRK_128_BYTES_SQES |
3099 				NVME_QUIRK_SHARED_TAGS },
3100 	{ 0, }
3101 };
3102 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3103 
3104 static struct pci_driver nvme_driver = {
3105 	.name		= "nvme",
3106 	.id_table	= nvme_id_table,
3107 	.probe		= nvme_probe,
3108 	.remove		= nvme_remove,
3109 	.shutdown	= nvme_shutdown,
3110 #ifdef CONFIG_PM_SLEEP
3111 	.driver		= {
3112 		.pm	= &nvme_dev_pm_ops,
3113 	},
3114 #endif
3115 	.sriov_configure = pci_sriov_configure_simple,
3116 	.err_handler	= &nvme_err_handler,
3117 };
3118 
3119 static int __init nvme_init(void)
3120 {
3121 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3122 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3123 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3124 	BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3125 
3126 	write_queues = min(write_queues, num_possible_cpus());
3127 	poll_queues = min(poll_queues, num_possible_cpus());
3128 	return pci_register_driver(&nvme_driver);
3129 }
3130 
3131 static void __exit nvme_exit(void)
3132 {
3133 	pci_unregister_driver(&nvme_driver);
3134 	flush_workqueue(nvme_wq);
3135 }
3136 
3137 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3138 MODULE_LICENSE("GPL");
3139 MODULE_VERSION("1.0");
3140 module_init(nvme_init);
3141 module_exit(nvme_exit);
3142