1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/async.h> 17 #include <linux/blkdev.h> 18 #include <linux/blk-mq.h> 19 #include <linux/blk-mq-pci.h> 20 #include <linux/dmi.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/mm.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/once.h> 28 #include <linux/pci.h> 29 #include <linux/t10-pi.h> 30 #include <linux/types.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 #include <linux/sed-opal.h> 33 34 #include "nvme.h" 35 36 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 37 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 38 39 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40 41 /* 42 * These can be higher, but we need to ensure that any command doesn't 43 * require an sg allocation that needs more than a page of data. 44 */ 45 #define NVME_MAX_KB_SZ 4096 46 #define NVME_MAX_SEGS 127 47 48 static int use_threaded_interrupts; 49 module_param(use_threaded_interrupts, int, 0); 50 51 static bool use_cmb_sqes = true; 52 module_param(use_cmb_sqes, bool, 0444); 53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 54 55 static unsigned int max_host_mem_size_mb = 128; 56 module_param(max_host_mem_size_mb, uint, 0444); 57 MODULE_PARM_DESC(max_host_mem_size_mb, 58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 59 60 static unsigned int sgl_threshold = SZ_32K; 61 module_param(sgl_threshold, uint, 0644); 62 MODULE_PARM_DESC(sgl_threshold, 63 "Use SGLs when average request segment size is larger or equal to " 64 "this size. Use 0 to disable SGLs."); 65 66 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 67 static const struct kernel_param_ops io_queue_depth_ops = { 68 .set = io_queue_depth_set, 69 .get = param_get_int, 70 }; 71 72 static int io_queue_depth = 1024; 73 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 74 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 75 76 struct nvme_dev; 77 struct nvme_queue; 78 79 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 80 81 /* 82 * Represents an NVM Express device. Each nvme_dev is a PCI function. 83 */ 84 struct nvme_dev { 85 struct nvme_queue *queues; 86 struct blk_mq_tag_set tagset; 87 struct blk_mq_tag_set admin_tagset; 88 u32 __iomem *dbs; 89 struct device *dev; 90 struct dma_pool *prp_page_pool; 91 struct dma_pool *prp_small_pool; 92 unsigned online_queues; 93 unsigned max_qid; 94 unsigned int num_vecs; 95 int q_depth; 96 u32 db_stride; 97 void __iomem *bar; 98 unsigned long bar_mapped_size; 99 struct work_struct remove_work; 100 struct mutex shutdown_lock; 101 bool subsystem; 102 void __iomem *cmb; 103 pci_bus_addr_t cmb_bus_addr; 104 u64 cmb_size; 105 u32 cmbsz; 106 u32 cmbloc; 107 struct nvme_ctrl ctrl; 108 struct completion ioq_wait; 109 110 mempool_t *iod_mempool; 111 112 /* shadow doorbell buffer support: */ 113 u32 *dbbuf_dbs; 114 dma_addr_t dbbuf_dbs_dma_addr; 115 u32 *dbbuf_eis; 116 dma_addr_t dbbuf_eis_dma_addr; 117 118 /* host memory buffer support: */ 119 u64 host_mem_size; 120 u32 nr_host_mem_descs; 121 dma_addr_t host_mem_descs_dma; 122 struct nvme_host_mem_buf_desc *host_mem_descs; 123 void **host_mem_desc_bufs; 124 }; 125 126 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 127 { 128 int n = 0, ret; 129 130 ret = kstrtoint(val, 10, &n); 131 if (ret != 0 || n < 2) 132 return -EINVAL; 133 134 return param_set_int(val, kp); 135 } 136 137 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 138 { 139 return qid * 2 * stride; 140 } 141 142 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 143 { 144 return (qid * 2 + 1) * stride; 145 } 146 147 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 148 { 149 return container_of(ctrl, struct nvme_dev, ctrl); 150 } 151 152 /* 153 * An NVM Express queue. Each device has at least two (one for admin 154 * commands and one for I/O commands). 155 */ 156 struct nvme_queue { 157 struct device *q_dmadev; 158 struct nvme_dev *dev; 159 spinlock_t sq_lock; 160 struct nvme_command *sq_cmds; 161 struct nvme_command __iomem *sq_cmds_io; 162 spinlock_t cq_lock ____cacheline_aligned_in_smp; 163 volatile struct nvme_completion *cqes; 164 struct blk_mq_tags **tags; 165 dma_addr_t sq_dma_addr; 166 dma_addr_t cq_dma_addr; 167 u32 __iomem *q_db; 168 u16 q_depth; 169 s16 cq_vector; 170 u16 sq_tail; 171 u16 cq_head; 172 u16 last_cq_head; 173 u16 qid; 174 u8 cq_phase; 175 u32 *dbbuf_sq_db; 176 u32 *dbbuf_cq_db; 177 u32 *dbbuf_sq_ei; 178 u32 *dbbuf_cq_ei; 179 }; 180 181 /* 182 * The nvme_iod describes the data in an I/O, including the list of PRP 183 * entries. You can't see it in this data structure because C doesn't let 184 * me express that. Use nvme_init_iod to ensure there's enough space 185 * allocated to store the PRP list. 186 */ 187 struct nvme_iod { 188 struct nvme_request req; 189 struct nvme_queue *nvmeq; 190 bool use_sgl; 191 int aborted; 192 int npages; /* In the PRP list. 0 means small pool in use */ 193 int nents; /* Used in scatterlist */ 194 int length; /* Of data, in bytes */ 195 dma_addr_t first_dma; 196 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 197 struct scatterlist *sg; 198 struct scatterlist inline_sg[0]; 199 }; 200 201 /* 202 * Check we didin't inadvertently grow the command struct 203 */ 204 static inline void _nvme_check_size(void) 205 { 206 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 207 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 208 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 209 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 210 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 211 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 212 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 213 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 214 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 215 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 216 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 217 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 218 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 219 } 220 221 static inline unsigned int nvme_dbbuf_size(u32 stride) 222 { 223 return ((num_possible_cpus() + 1) * 8 * stride); 224 } 225 226 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 227 { 228 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 229 230 if (dev->dbbuf_dbs) 231 return 0; 232 233 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 234 &dev->dbbuf_dbs_dma_addr, 235 GFP_KERNEL); 236 if (!dev->dbbuf_dbs) 237 return -ENOMEM; 238 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 239 &dev->dbbuf_eis_dma_addr, 240 GFP_KERNEL); 241 if (!dev->dbbuf_eis) { 242 dma_free_coherent(dev->dev, mem_size, 243 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 244 dev->dbbuf_dbs = NULL; 245 return -ENOMEM; 246 } 247 248 return 0; 249 } 250 251 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 252 { 253 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 254 255 if (dev->dbbuf_dbs) { 256 dma_free_coherent(dev->dev, mem_size, 257 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 258 dev->dbbuf_dbs = NULL; 259 } 260 if (dev->dbbuf_eis) { 261 dma_free_coherent(dev->dev, mem_size, 262 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 263 dev->dbbuf_eis = NULL; 264 } 265 } 266 267 static void nvme_dbbuf_init(struct nvme_dev *dev, 268 struct nvme_queue *nvmeq, int qid) 269 { 270 if (!dev->dbbuf_dbs || !qid) 271 return; 272 273 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 274 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 275 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 276 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 277 } 278 279 static void nvme_dbbuf_set(struct nvme_dev *dev) 280 { 281 struct nvme_command c; 282 283 if (!dev->dbbuf_dbs) 284 return; 285 286 memset(&c, 0, sizeof(c)); 287 c.dbbuf.opcode = nvme_admin_dbbuf; 288 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 289 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 290 291 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 292 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 293 /* Free memory and continue on */ 294 nvme_dbbuf_dma_free(dev); 295 } 296 } 297 298 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 299 { 300 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 301 } 302 303 /* Update dbbuf and return true if an MMIO is required */ 304 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 305 volatile u32 *dbbuf_ei) 306 { 307 if (dbbuf_db) { 308 u16 old_value; 309 310 /* 311 * Ensure that the queue is written before updating 312 * the doorbell in memory 313 */ 314 wmb(); 315 316 old_value = *dbbuf_db; 317 *dbbuf_db = value; 318 319 /* 320 * Ensure that the doorbell is updated before reading the event 321 * index from memory. The controller needs to provide similar 322 * ordering to ensure the envent index is updated before reading 323 * the doorbell. 324 */ 325 mb(); 326 327 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 328 return false; 329 } 330 331 return true; 332 } 333 334 /* 335 * Max size of iod being embedded in the request payload 336 */ 337 #define NVME_INT_PAGES 2 338 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 339 340 /* 341 * Will slightly overestimate the number of pages needed. This is OK 342 * as it only leads to a small amount of wasted memory for the lifetime of 343 * the I/O. 344 */ 345 static int nvme_npages(unsigned size, struct nvme_dev *dev) 346 { 347 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 348 dev->ctrl.page_size); 349 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 350 } 351 352 /* 353 * Calculates the number of pages needed for the SGL segments. For example a 4k 354 * page can accommodate 256 SGL descriptors. 355 */ 356 static int nvme_pci_npages_sgl(unsigned int num_seg) 357 { 358 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 359 } 360 361 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 362 unsigned int size, unsigned int nseg, bool use_sgl) 363 { 364 size_t alloc_size; 365 366 if (use_sgl) 367 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 368 else 369 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 370 371 return alloc_size + sizeof(struct scatterlist) * nseg; 372 } 373 374 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 375 { 376 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 377 NVME_INT_BYTES(dev), NVME_INT_PAGES, 378 use_sgl); 379 380 return sizeof(struct nvme_iod) + alloc_size; 381 } 382 383 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 384 unsigned int hctx_idx) 385 { 386 struct nvme_dev *dev = data; 387 struct nvme_queue *nvmeq = &dev->queues[0]; 388 389 WARN_ON(hctx_idx != 0); 390 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 391 WARN_ON(nvmeq->tags); 392 393 hctx->driver_data = nvmeq; 394 nvmeq->tags = &dev->admin_tagset.tags[0]; 395 return 0; 396 } 397 398 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 399 { 400 struct nvme_queue *nvmeq = hctx->driver_data; 401 402 nvmeq->tags = NULL; 403 } 404 405 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 406 unsigned int hctx_idx) 407 { 408 struct nvme_dev *dev = data; 409 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 410 411 if (!nvmeq->tags) 412 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 413 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 415 hctx->driver_data = nvmeq; 416 return 0; 417 } 418 419 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 420 unsigned int hctx_idx, unsigned int numa_node) 421 { 422 struct nvme_dev *dev = set->driver_data; 423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 424 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 425 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 426 427 BUG_ON(!nvmeq); 428 iod->nvmeq = nvmeq; 429 430 nvme_req(req)->ctrl = &dev->ctrl; 431 return 0; 432 } 433 434 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 435 { 436 struct nvme_dev *dev = set->driver_data; 437 438 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 439 dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 440 } 441 442 /** 443 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 444 * @nvmeq: The queue to use 445 * @cmd: The command to send 446 */ 447 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 448 { 449 spin_lock(&nvmeq->sq_lock); 450 if (nvmeq->sq_cmds_io) 451 memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd, 452 sizeof(*cmd)); 453 else 454 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 455 456 if (++nvmeq->sq_tail == nvmeq->q_depth) 457 nvmeq->sq_tail = 0; 458 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 459 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 460 writel(nvmeq->sq_tail, nvmeq->q_db); 461 spin_unlock(&nvmeq->sq_lock); 462 } 463 464 static void **nvme_pci_iod_list(struct request *req) 465 { 466 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 467 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 468 } 469 470 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 471 { 472 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 473 int nseg = blk_rq_nr_phys_segments(req); 474 unsigned int avg_seg_size; 475 476 if (nseg == 0) 477 return false; 478 479 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 480 481 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 482 return false; 483 if (!iod->nvmeq->qid) 484 return false; 485 if (!sgl_threshold || avg_seg_size < sgl_threshold) 486 return false; 487 return true; 488 } 489 490 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 491 { 492 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 493 int nseg = blk_rq_nr_phys_segments(rq); 494 unsigned int size = blk_rq_payload_bytes(rq); 495 496 iod->use_sgl = nvme_pci_use_sgls(dev, rq); 497 498 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 499 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 500 if (!iod->sg) 501 return BLK_STS_RESOURCE; 502 } else { 503 iod->sg = iod->inline_sg; 504 } 505 506 iod->aborted = 0; 507 iod->npages = -1; 508 iod->nents = 0; 509 iod->length = size; 510 511 return BLK_STS_OK; 512 } 513 514 static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 515 { 516 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 517 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 518 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 519 520 int i; 521 522 if (iod->npages == 0) 523 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 524 dma_addr); 525 526 for (i = 0; i < iod->npages; i++) { 527 void *addr = nvme_pci_iod_list(req)[i]; 528 529 if (iod->use_sgl) { 530 struct nvme_sgl_desc *sg_list = addr; 531 532 next_dma_addr = 533 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 534 } else { 535 __le64 *prp_list = addr; 536 537 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 538 } 539 540 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 541 dma_addr = next_dma_addr; 542 } 543 544 if (iod->sg != iod->inline_sg) 545 mempool_free(iod->sg, dev->iod_mempool); 546 } 547 548 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 549 { 550 int i; 551 struct scatterlist *sg; 552 553 for_each_sg(sgl, sg, nents, i) { 554 dma_addr_t phys = sg_phys(sg); 555 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 556 "dma_address:%pad dma_length:%d\n", 557 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 558 sg_dma_len(sg)); 559 } 560 } 561 562 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 563 struct request *req, struct nvme_rw_command *cmnd) 564 { 565 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 566 struct dma_pool *pool; 567 int length = blk_rq_payload_bytes(req); 568 struct scatterlist *sg = iod->sg; 569 int dma_len = sg_dma_len(sg); 570 u64 dma_addr = sg_dma_address(sg); 571 u32 page_size = dev->ctrl.page_size; 572 int offset = dma_addr & (page_size - 1); 573 __le64 *prp_list; 574 void **list = nvme_pci_iod_list(req); 575 dma_addr_t prp_dma; 576 int nprps, i; 577 578 length -= (page_size - offset); 579 if (length <= 0) { 580 iod->first_dma = 0; 581 goto done; 582 } 583 584 dma_len -= (page_size - offset); 585 if (dma_len) { 586 dma_addr += (page_size - offset); 587 } else { 588 sg = sg_next(sg); 589 dma_addr = sg_dma_address(sg); 590 dma_len = sg_dma_len(sg); 591 } 592 593 if (length <= page_size) { 594 iod->first_dma = dma_addr; 595 goto done; 596 } 597 598 nprps = DIV_ROUND_UP(length, page_size); 599 if (nprps <= (256 / 8)) { 600 pool = dev->prp_small_pool; 601 iod->npages = 0; 602 } else { 603 pool = dev->prp_page_pool; 604 iod->npages = 1; 605 } 606 607 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 608 if (!prp_list) { 609 iod->first_dma = dma_addr; 610 iod->npages = -1; 611 return BLK_STS_RESOURCE; 612 } 613 list[0] = prp_list; 614 iod->first_dma = prp_dma; 615 i = 0; 616 for (;;) { 617 if (i == page_size >> 3) { 618 __le64 *old_prp_list = prp_list; 619 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 620 if (!prp_list) 621 return BLK_STS_RESOURCE; 622 list[iod->npages++] = prp_list; 623 prp_list[0] = old_prp_list[i - 1]; 624 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 625 i = 1; 626 } 627 prp_list[i++] = cpu_to_le64(dma_addr); 628 dma_len -= page_size; 629 dma_addr += page_size; 630 length -= page_size; 631 if (length <= 0) 632 break; 633 if (dma_len > 0) 634 continue; 635 if (unlikely(dma_len < 0)) 636 goto bad_sgl; 637 sg = sg_next(sg); 638 dma_addr = sg_dma_address(sg); 639 dma_len = sg_dma_len(sg); 640 } 641 642 done: 643 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 644 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 645 646 return BLK_STS_OK; 647 648 bad_sgl: 649 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 650 "Invalid SGL for payload:%d nents:%d\n", 651 blk_rq_payload_bytes(req), iod->nents); 652 return BLK_STS_IOERR; 653 } 654 655 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 656 struct scatterlist *sg) 657 { 658 sge->addr = cpu_to_le64(sg_dma_address(sg)); 659 sge->length = cpu_to_le32(sg_dma_len(sg)); 660 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 661 } 662 663 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 664 dma_addr_t dma_addr, int entries) 665 { 666 sge->addr = cpu_to_le64(dma_addr); 667 if (entries < SGES_PER_PAGE) { 668 sge->length = cpu_to_le32(entries * sizeof(*sge)); 669 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 670 } else { 671 sge->length = cpu_to_le32(PAGE_SIZE); 672 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 673 } 674 } 675 676 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 677 struct request *req, struct nvme_rw_command *cmd, int entries) 678 { 679 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 680 struct dma_pool *pool; 681 struct nvme_sgl_desc *sg_list; 682 struct scatterlist *sg = iod->sg; 683 dma_addr_t sgl_dma; 684 int i = 0; 685 686 /* setting the transfer type as SGL */ 687 cmd->flags = NVME_CMD_SGL_METABUF; 688 689 if (entries == 1) { 690 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 691 return BLK_STS_OK; 692 } 693 694 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 695 pool = dev->prp_small_pool; 696 iod->npages = 0; 697 } else { 698 pool = dev->prp_page_pool; 699 iod->npages = 1; 700 } 701 702 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 703 if (!sg_list) { 704 iod->npages = -1; 705 return BLK_STS_RESOURCE; 706 } 707 708 nvme_pci_iod_list(req)[0] = sg_list; 709 iod->first_dma = sgl_dma; 710 711 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 712 713 do { 714 if (i == SGES_PER_PAGE) { 715 struct nvme_sgl_desc *old_sg_desc = sg_list; 716 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 717 718 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 719 if (!sg_list) 720 return BLK_STS_RESOURCE; 721 722 i = 0; 723 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 724 sg_list[i++] = *link; 725 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 726 } 727 728 nvme_pci_sgl_set_data(&sg_list[i++], sg); 729 sg = sg_next(sg); 730 } while (--entries > 0); 731 732 return BLK_STS_OK; 733 } 734 735 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 736 struct nvme_command *cmnd) 737 { 738 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 739 struct request_queue *q = req->q; 740 enum dma_data_direction dma_dir = rq_data_dir(req) ? 741 DMA_TO_DEVICE : DMA_FROM_DEVICE; 742 blk_status_t ret = BLK_STS_IOERR; 743 int nr_mapped; 744 745 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 746 iod->nents = blk_rq_map_sg(q, req, iod->sg); 747 if (!iod->nents) 748 goto out; 749 750 ret = BLK_STS_RESOURCE; 751 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 752 DMA_ATTR_NO_WARN); 753 if (!nr_mapped) 754 goto out; 755 756 if (iod->use_sgl) 757 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 758 else 759 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 760 761 if (ret != BLK_STS_OK) 762 goto out_unmap; 763 764 ret = BLK_STS_IOERR; 765 if (blk_integrity_rq(req)) { 766 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 767 goto out_unmap; 768 769 sg_init_table(&iod->meta_sg, 1); 770 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 771 goto out_unmap; 772 773 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 774 goto out_unmap; 775 } 776 777 if (blk_integrity_rq(req)) 778 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 779 return BLK_STS_OK; 780 781 out_unmap: 782 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 783 out: 784 return ret; 785 } 786 787 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 788 { 789 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 790 enum dma_data_direction dma_dir = rq_data_dir(req) ? 791 DMA_TO_DEVICE : DMA_FROM_DEVICE; 792 793 if (iod->nents) { 794 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 795 if (blk_integrity_rq(req)) 796 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 797 } 798 799 nvme_cleanup_cmd(req); 800 nvme_free_iod(dev, req); 801 } 802 803 /* 804 * NOTE: ns is NULL when called on the admin queue. 805 */ 806 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 807 const struct blk_mq_queue_data *bd) 808 { 809 struct nvme_ns *ns = hctx->queue->queuedata; 810 struct nvme_queue *nvmeq = hctx->driver_data; 811 struct nvme_dev *dev = nvmeq->dev; 812 struct request *req = bd->rq; 813 struct nvme_command cmnd; 814 blk_status_t ret; 815 816 /* 817 * We should not need to do this, but we're still using this to 818 * ensure we can drain requests on a dying queue. 819 */ 820 if (unlikely(nvmeq->cq_vector < 0)) 821 return BLK_STS_IOERR; 822 823 ret = nvme_setup_cmd(ns, req, &cmnd); 824 if (ret) 825 return ret; 826 827 ret = nvme_init_iod(req, dev); 828 if (ret) 829 goto out_free_cmd; 830 831 if (blk_rq_nr_phys_segments(req)) { 832 ret = nvme_map_data(dev, req, &cmnd); 833 if (ret) 834 goto out_cleanup_iod; 835 } 836 837 blk_mq_start_request(req); 838 nvme_submit_cmd(nvmeq, &cmnd); 839 return BLK_STS_OK; 840 out_cleanup_iod: 841 nvme_free_iod(dev, req); 842 out_free_cmd: 843 nvme_cleanup_cmd(req); 844 return ret; 845 } 846 847 static void nvme_pci_complete_rq(struct request *req) 848 { 849 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 850 851 nvme_unmap_data(iod->nvmeq->dev, req); 852 nvme_complete_rq(req); 853 } 854 855 /* We read the CQE phase first to check if the rest of the entry is valid */ 856 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 857 { 858 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 859 nvmeq->cq_phase; 860 } 861 862 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 863 { 864 u16 head = nvmeq->cq_head; 865 866 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 867 nvmeq->dbbuf_cq_ei)) 868 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 869 } 870 871 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 872 { 873 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 874 struct request *req; 875 876 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 877 dev_warn(nvmeq->dev->ctrl.device, 878 "invalid id %d completed on queue %d\n", 879 cqe->command_id, le16_to_cpu(cqe->sq_id)); 880 return; 881 } 882 883 /* 884 * AEN requests are special as they don't time out and can 885 * survive any kind of queue freeze and often don't respond to 886 * aborts. We don't even bother to allocate a struct request 887 * for them but rather special case them here. 888 */ 889 if (unlikely(nvmeq->qid == 0 && 890 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 891 nvme_complete_async_event(&nvmeq->dev->ctrl, 892 cqe->status, &cqe->result); 893 return; 894 } 895 896 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 897 nvme_end_request(req, cqe->status, cqe->result); 898 } 899 900 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 901 { 902 while (start != end) { 903 nvme_handle_cqe(nvmeq, start); 904 if (++start == nvmeq->q_depth) 905 start = 0; 906 } 907 } 908 909 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 910 { 911 if (++nvmeq->cq_head == nvmeq->q_depth) { 912 nvmeq->cq_head = 0; 913 nvmeq->cq_phase = !nvmeq->cq_phase; 914 } 915 } 916 917 static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 918 u16 *end, int tag) 919 { 920 bool found = false; 921 922 *start = nvmeq->cq_head; 923 while (!found && nvme_cqe_pending(nvmeq)) { 924 if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 925 found = true; 926 nvme_update_cq_head(nvmeq); 927 } 928 *end = nvmeq->cq_head; 929 930 if (*start != *end) 931 nvme_ring_cq_doorbell(nvmeq); 932 return found; 933 } 934 935 static irqreturn_t nvme_irq(int irq, void *data) 936 { 937 struct nvme_queue *nvmeq = data; 938 irqreturn_t ret = IRQ_NONE; 939 u16 start, end; 940 941 spin_lock(&nvmeq->cq_lock); 942 if (nvmeq->cq_head != nvmeq->last_cq_head) 943 ret = IRQ_HANDLED; 944 nvme_process_cq(nvmeq, &start, &end, -1); 945 nvmeq->last_cq_head = nvmeq->cq_head; 946 spin_unlock(&nvmeq->cq_lock); 947 948 if (start != end) { 949 nvme_complete_cqes(nvmeq, start, end); 950 return IRQ_HANDLED; 951 } 952 953 return ret; 954 } 955 956 static irqreturn_t nvme_irq_check(int irq, void *data) 957 { 958 struct nvme_queue *nvmeq = data; 959 if (nvme_cqe_pending(nvmeq)) 960 return IRQ_WAKE_THREAD; 961 return IRQ_NONE; 962 } 963 964 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 965 { 966 u16 start, end; 967 bool found; 968 969 if (!nvme_cqe_pending(nvmeq)) 970 return 0; 971 972 spin_lock_irq(&nvmeq->cq_lock); 973 found = nvme_process_cq(nvmeq, &start, &end, tag); 974 spin_unlock_irq(&nvmeq->cq_lock); 975 976 nvme_complete_cqes(nvmeq, start, end); 977 return found; 978 } 979 980 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 981 { 982 struct nvme_queue *nvmeq = hctx->driver_data; 983 984 return __nvme_poll(nvmeq, tag); 985 } 986 987 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 988 { 989 struct nvme_dev *dev = to_nvme_dev(ctrl); 990 struct nvme_queue *nvmeq = &dev->queues[0]; 991 struct nvme_command c; 992 993 memset(&c, 0, sizeof(c)); 994 c.common.opcode = nvme_admin_async_event; 995 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 996 nvme_submit_cmd(nvmeq, &c); 997 } 998 999 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1000 { 1001 struct nvme_command c; 1002 1003 memset(&c, 0, sizeof(c)); 1004 c.delete_queue.opcode = opcode; 1005 c.delete_queue.qid = cpu_to_le16(id); 1006 1007 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1008 } 1009 1010 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1011 struct nvme_queue *nvmeq, s16 vector) 1012 { 1013 struct nvme_command c; 1014 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 1015 1016 /* 1017 * Note: we (ab)use the fact that the prp fields survive if no data 1018 * is attached to the request. 1019 */ 1020 memset(&c, 0, sizeof(c)); 1021 c.create_cq.opcode = nvme_admin_create_cq; 1022 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1023 c.create_cq.cqid = cpu_to_le16(qid); 1024 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1025 c.create_cq.cq_flags = cpu_to_le16(flags); 1026 c.create_cq.irq_vector = cpu_to_le16(vector); 1027 1028 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1029 } 1030 1031 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1032 struct nvme_queue *nvmeq) 1033 { 1034 struct nvme_ctrl *ctrl = &dev->ctrl; 1035 struct nvme_command c; 1036 int flags = NVME_QUEUE_PHYS_CONTIG; 1037 1038 /* 1039 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1040 * set. Since URGENT priority is zeroes, it makes all queues 1041 * URGENT. 1042 */ 1043 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1044 flags |= NVME_SQ_PRIO_MEDIUM; 1045 1046 /* 1047 * Note: we (ab)use the fact that the prp fields survive if no data 1048 * is attached to the request. 1049 */ 1050 memset(&c, 0, sizeof(c)); 1051 c.create_sq.opcode = nvme_admin_create_sq; 1052 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1053 c.create_sq.sqid = cpu_to_le16(qid); 1054 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1055 c.create_sq.sq_flags = cpu_to_le16(flags); 1056 c.create_sq.cqid = cpu_to_le16(qid); 1057 1058 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1059 } 1060 1061 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1062 { 1063 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1064 } 1065 1066 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1067 { 1068 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1069 } 1070 1071 static void abort_endio(struct request *req, blk_status_t error) 1072 { 1073 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1074 struct nvme_queue *nvmeq = iod->nvmeq; 1075 1076 dev_warn(nvmeq->dev->ctrl.device, 1077 "Abort status: 0x%x", nvme_req(req)->status); 1078 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1079 blk_mq_free_request(req); 1080 } 1081 1082 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1083 { 1084 1085 /* If true, indicates loss of adapter communication, possibly by a 1086 * NVMe Subsystem reset. 1087 */ 1088 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1089 1090 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1091 switch (dev->ctrl.state) { 1092 case NVME_CTRL_RESETTING: 1093 case NVME_CTRL_CONNECTING: 1094 return false; 1095 default: 1096 break; 1097 } 1098 1099 /* We shouldn't reset unless the controller is on fatal error state 1100 * _or_ if we lost the communication with it. 1101 */ 1102 if (!(csts & NVME_CSTS_CFS) && !nssro) 1103 return false; 1104 1105 return true; 1106 } 1107 1108 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1109 { 1110 /* Read a config register to help see what died. */ 1111 u16 pci_status; 1112 int result; 1113 1114 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1115 &pci_status); 1116 if (result == PCIBIOS_SUCCESSFUL) 1117 dev_warn(dev->ctrl.device, 1118 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1119 csts, pci_status); 1120 else 1121 dev_warn(dev->ctrl.device, 1122 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1123 csts, result); 1124 } 1125 1126 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1127 { 1128 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1129 struct nvme_queue *nvmeq = iod->nvmeq; 1130 struct nvme_dev *dev = nvmeq->dev; 1131 struct request *abort_req; 1132 struct nvme_command cmd; 1133 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1134 1135 /* If PCI error recovery process is happening, we cannot reset or 1136 * the recovery mechanism will surely fail. 1137 */ 1138 mb(); 1139 if (pci_channel_offline(to_pci_dev(dev->dev))) 1140 return BLK_EH_RESET_TIMER; 1141 1142 /* 1143 * Reset immediately if the controller is failed 1144 */ 1145 if (nvme_should_reset(dev, csts)) { 1146 nvme_warn_reset(dev, csts); 1147 nvme_dev_disable(dev, false); 1148 nvme_reset_ctrl(&dev->ctrl); 1149 return BLK_EH_DONE; 1150 } 1151 1152 /* 1153 * Did we miss an interrupt? 1154 */ 1155 if (__nvme_poll(nvmeq, req->tag)) { 1156 dev_warn(dev->ctrl.device, 1157 "I/O %d QID %d timeout, completion polled\n", 1158 req->tag, nvmeq->qid); 1159 return BLK_EH_DONE; 1160 } 1161 1162 /* 1163 * Shutdown immediately if controller times out while starting. The 1164 * reset work will see the pci device disabled when it gets the forced 1165 * cancellation error. All outstanding requests are completed on 1166 * shutdown, so we return BLK_EH_DONE. 1167 */ 1168 switch (dev->ctrl.state) { 1169 case NVME_CTRL_CONNECTING: 1170 case NVME_CTRL_RESETTING: 1171 dev_warn_ratelimited(dev->ctrl.device, 1172 "I/O %d QID %d timeout, disable controller\n", 1173 req->tag, nvmeq->qid); 1174 nvme_dev_disable(dev, false); 1175 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1176 return BLK_EH_DONE; 1177 default: 1178 break; 1179 } 1180 1181 /* 1182 * Shutdown the controller immediately and schedule a reset if the 1183 * command was already aborted once before and still hasn't been 1184 * returned to the driver, or if this is the admin queue. 1185 */ 1186 if (!nvmeq->qid || iod->aborted) { 1187 dev_warn(dev->ctrl.device, 1188 "I/O %d QID %d timeout, reset controller\n", 1189 req->tag, nvmeq->qid); 1190 nvme_dev_disable(dev, false); 1191 nvme_reset_ctrl(&dev->ctrl); 1192 1193 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1194 return BLK_EH_DONE; 1195 } 1196 1197 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1198 atomic_inc(&dev->ctrl.abort_limit); 1199 return BLK_EH_RESET_TIMER; 1200 } 1201 iod->aborted = 1; 1202 1203 memset(&cmd, 0, sizeof(cmd)); 1204 cmd.abort.opcode = nvme_admin_abort_cmd; 1205 cmd.abort.cid = req->tag; 1206 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1207 1208 dev_warn(nvmeq->dev->ctrl.device, 1209 "I/O %d QID %d timeout, aborting\n", 1210 req->tag, nvmeq->qid); 1211 1212 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1213 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1214 if (IS_ERR(abort_req)) { 1215 atomic_inc(&dev->ctrl.abort_limit); 1216 return BLK_EH_RESET_TIMER; 1217 } 1218 1219 abort_req->timeout = ADMIN_TIMEOUT; 1220 abort_req->end_io_data = NULL; 1221 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1222 1223 /* 1224 * The aborted req will be completed on receiving the abort req. 1225 * We enable the timer again. If hit twice, it'll cause a device reset, 1226 * as the device then is in a faulty state. 1227 */ 1228 return BLK_EH_RESET_TIMER; 1229 } 1230 1231 static void nvme_free_queue(struct nvme_queue *nvmeq) 1232 { 1233 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1234 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1235 if (nvmeq->sq_cmds) 1236 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1237 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1238 } 1239 1240 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1241 { 1242 int i; 1243 1244 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1245 dev->ctrl.queue_count--; 1246 nvme_free_queue(&dev->queues[i]); 1247 } 1248 } 1249 1250 /** 1251 * nvme_suspend_queue - put queue into suspended state 1252 * @nvmeq - queue to suspend 1253 */ 1254 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1255 { 1256 int vector; 1257 1258 spin_lock_irq(&nvmeq->cq_lock); 1259 if (nvmeq->cq_vector == -1) { 1260 spin_unlock_irq(&nvmeq->cq_lock); 1261 return 1; 1262 } 1263 vector = nvmeq->cq_vector; 1264 nvmeq->dev->online_queues--; 1265 nvmeq->cq_vector = -1; 1266 spin_unlock_irq(&nvmeq->cq_lock); 1267 1268 /* 1269 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1270 * having to grab the lock. 1271 */ 1272 mb(); 1273 1274 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1275 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1276 1277 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 1278 1279 return 0; 1280 } 1281 1282 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1283 { 1284 struct nvme_queue *nvmeq = &dev->queues[0]; 1285 u16 start, end; 1286 1287 if (shutdown) 1288 nvme_shutdown_ctrl(&dev->ctrl); 1289 else 1290 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1291 1292 spin_lock_irq(&nvmeq->cq_lock); 1293 nvme_process_cq(nvmeq, &start, &end, -1); 1294 spin_unlock_irq(&nvmeq->cq_lock); 1295 1296 nvme_complete_cqes(nvmeq, start, end); 1297 } 1298 1299 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1300 int entry_size) 1301 { 1302 int q_depth = dev->q_depth; 1303 unsigned q_size_aligned = roundup(q_depth * entry_size, 1304 dev->ctrl.page_size); 1305 1306 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1307 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1308 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1309 q_depth = div_u64(mem_per_q, entry_size); 1310 1311 /* 1312 * Ensure the reduced q_depth is above some threshold where it 1313 * would be better to map queues in system memory with the 1314 * original depth 1315 */ 1316 if (q_depth < 64) 1317 return -ENOMEM; 1318 } 1319 1320 return q_depth; 1321 } 1322 1323 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1324 int qid, int depth) 1325 { 1326 /* CMB SQEs will be mapped before creation */ 1327 if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1328 return 0; 1329 1330 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1331 &nvmeq->sq_dma_addr, GFP_KERNEL); 1332 if (!nvmeq->sq_cmds) 1333 return -ENOMEM; 1334 return 0; 1335 } 1336 1337 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1338 { 1339 struct nvme_queue *nvmeq = &dev->queues[qid]; 1340 1341 if (dev->ctrl.queue_count > qid) 1342 return 0; 1343 1344 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 1345 &nvmeq->cq_dma_addr, GFP_KERNEL); 1346 if (!nvmeq->cqes) 1347 goto free_nvmeq; 1348 1349 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1350 goto free_cqdma; 1351 1352 nvmeq->q_dmadev = dev->dev; 1353 nvmeq->dev = dev; 1354 spin_lock_init(&nvmeq->sq_lock); 1355 spin_lock_init(&nvmeq->cq_lock); 1356 nvmeq->cq_head = 0; 1357 nvmeq->cq_phase = 1; 1358 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1359 nvmeq->q_depth = depth; 1360 nvmeq->qid = qid; 1361 nvmeq->cq_vector = -1; 1362 dev->ctrl.queue_count++; 1363 1364 return 0; 1365 1366 free_cqdma: 1367 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1368 nvmeq->cq_dma_addr); 1369 free_nvmeq: 1370 return -ENOMEM; 1371 } 1372 1373 static int queue_request_irq(struct nvme_queue *nvmeq) 1374 { 1375 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1376 int nr = nvmeq->dev->ctrl.instance; 1377 1378 if (use_threaded_interrupts) { 1379 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1380 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1381 } else { 1382 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1383 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1384 } 1385 } 1386 1387 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1388 { 1389 struct nvme_dev *dev = nvmeq->dev; 1390 1391 spin_lock_irq(&nvmeq->cq_lock); 1392 nvmeq->sq_tail = 0; 1393 nvmeq->cq_head = 0; 1394 nvmeq->cq_phase = 1; 1395 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1396 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1397 nvme_dbbuf_init(dev, nvmeq, qid); 1398 dev->online_queues++; 1399 spin_unlock_irq(&nvmeq->cq_lock); 1400 } 1401 1402 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 1403 { 1404 struct nvme_dev *dev = nvmeq->dev; 1405 int result; 1406 s16 vector; 1407 1408 if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1409 unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1410 dev->ctrl.page_size); 1411 nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1412 nvmeq->sq_cmds_io = dev->cmb + offset; 1413 } 1414 1415 /* 1416 * A queue's vector matches the queue identifier unless the controller 1417 * has only one vector available. 1418 */ 1419 vector = dev->num_vecs == 1 ? 0 : qid; 1420 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1421 if (result) 1422 return result; 1423 1424 result = adapter_alloc_sq(dev, qid, nvmeq); 1425 if (result < 0) 1426 return result; 1427 else if (result) 1428 goto release_cq; 1429 1430 /* 1431 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1432 * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1433 * xxx' warning if the create CQ/SQ command times out. 1434 */ 1435 nvmeq->cq_vector = vector; 1436 nvme_init_queue(nvmeq, qid); 1437 result = queue_request_irq(nvmeq); 1438 if (result < 0) 1439 goto release_sq; 1440 1441 return result; 1442 1443 release_sq: 1444 nvmeq->cq_vector = -1; 1445 dev->online_queues--; 1446 adapter_delete_sq(dev, qid); 1447 release_cq: 1448 adapter_delete_cq(dev, qid); 1449 return result; 1450 } 1451 1452 static const struct blk_mq_ops nvme_mq_admin_ops = { 1453 .queue_rq = nvme_queue_rq, 1454 .complete = nvme_pci_complete_rq, 1455 .init_hctx = nvme_admin_init_hctx, 1456 .exit_hctx = nvme_admin_exit_hctx, 1457 .init_request = nvme_init_request, 1458 .timeout = nvme_timeout, 1459 }; 1460 1461 static const struct blk_mq_ops nvme_mq_ops = { 1462 .queue_rq = nvme_queue_rq, 1463 .complete = nvme_pci_complete_rq, 1464 .init_hctx = nvme_init_hctx, 1465 .init_request = nvme_init_request, 1466 .map_queues = nvme_pci_map_queues, 1467 .timeout = nvme_timeout, 1468 .poll = nvme_poll, 1469 }; 1470 1471 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1472 { 1473 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1474 /* 1475 * If the controller was reset during removal, it's possible 1476 * user requests may be waiting on a stopped queue. Start the 1477 * queue to flush these to completion. 1478 */ 1479 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1480 blk_cleanup_queue(dev->ctrl.admin_q); 1481 blk_mq_free_tag_set(&dev->admin_tagset); 1482 } 1483 } 1484 1485 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1486 { 1487 if (!dev->ctrl.admin_q) { 1488 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1489 dev->admin_tagset.nr_hw_queues = 1; 1490 1491 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1492 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1493 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1494 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1495 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1496 dev->admin_tagset.driver_data = dev; 1497 1498 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1499 return -ENOMEM; 1500 dev->ctrl.admin_tagset = &dev->admin_tagset; 1501 1502 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1503 if (IS_ERR(dev->ctrl.admin_q)) { 1504 blk_mq_free_tag_set(&dev->admin_tagset); 1505 return -ENOMEM; 1506 } 1507 if (!blk_get_queue(dev->ctrl.admin_q)) { 1508 nvme_dev_remove_admin(dev); 1509 dev->ctrl.admin_q = NULL; 1510 return -ENODEV; 1511 } 1512 } else 1513 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1514 1515 return 0; 1516 } 1517 1518 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1519 { 1520 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1521 } 1522 1523 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1524 { 1525 struct pci_dev *pdev = to_pci_dev(dev->dev); 1526 1527 if (size <= dev->bar_mapped_size) 1528 return 0; 1529 if (size > pci_resource_len(pdev, 0)) 1530 return -ENOMEM; 1531 if (dev->bar) 1532 iounmap(dev->bar); 1533 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1534 if (!dev->bar) { 1535 dev->bar_mapped_size = 0; 1536 return -ENOMEM; 1537 } 1538 dev->bar_mapped_size = size; 1539 dev->dbs = dev->bar + NVME_REG_DBS; 1540 1541 return 0; 1542 } 1543 1544 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1545 { 1546 int result; 1547 u32 aqa; 1548 struct nvme_queue *nvmeq; 1549 1550 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1551 if (result < 0) 1552 return result; 1553 1554 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1555 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1556 1557 if (dev->subsystem && 1558 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1559 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1560 1561 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1562 if (result < 0) 1563 return result; 1564 1565 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1566 if (result) 1567 return result; 1568 1569 nvmeq = &dev->queues[0]; 1570 aqa = nvmeq->q_depth - 1; 1571 aqa |= aqa << 16; 1572 1573 writel(aqa, dev->bar + NVME_REG_AQA); 1574 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1575 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1576 1577 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 1578 if (result) 1579 return result; 1580 1581 nvmeq->cq_vector = 0; 1582 nvme_init_queue(nvmeq, 0); 1583 result = queue_request_irq(nvmeq); 1584 if (result) { 1585 nvmeq->cq_vector = -1; 1586 return result; 1587 } 1588 1589 return result; 1590 } 1591 1592 static int nvme_create_io_queues(struct nvme_dev *dev) 1593 { 1594 unsigned i, max; 1595 int ret = 0; 1596 1597 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1598 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1599 ret = -ENOMEM; 1600 break; 1601 } 1602 } 1603 1604 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1605 for (i = dev->online_queues; i <= max; i++) { 1606 ret = nvme_create_queue(&dev->queues[i], i); 1607 if (ret) 1608 break; 1609 } 1610 1611 /* 1612 * Ignore failing Create SQ/CQ commands, we can continue with less 1613 * than the desired amount of queues, and even a controller without 1614 * I/O queues can still be used to issue admin commands. This might 1615 * be useful to upgrade a buggy firmware for example. 1616 */ 1617 return ret >= 0 ? 0 : ret; 1618 } 1619 1620 static ssize_t nvme_cmb_show(struct device *dev, 1621 struct device_attribute *attr, 1622 char *buf) 1623 { 1624 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1625 1626 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1627 ndev->cmbloc, ndev->cmbsz); 1628 } 1629 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1630 1631 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1632 { 1633 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1634 1635 return 1ULL << (12 + 4 * szu); 1636 } 1637 1638 static u32 nvme_cmb_size(struct nvme_dev *dev) 1639 { 1640 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1641 } 1642 1643 static void nvme_map_cmb(struct nvme_dev *dev) 1644 { 1645 u64 size, offset; 1646 resource_size_t bar_size; 1647 struct pci_dev *pdev = to_pci_dev(dev->dev); 1648 int bar; 1649 1650 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1651 if (!dev->cmbsz) 1652 return; 1653 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1654 1655 if (!use_cmb_sqes) 1656 return; 1657 1658 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1659 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1660 bar = NVME_CMB_BIR(dev->cmbloc); 1661 bar_size = pci_resource_len(pdev, bar); 1662 1663 if (offset > bar_size) 1664 return; 1665 1666 /* 1667 * Controllers may support a CMB size larger than their BAR, 1668 * for example, due to being behind a bridge. Reduce the CMB to 1669 * the reported size of the BAR 1670 */ 1671 if (size > bar_size - offset) 1672 size = bar_size - offset; 1673 1674 dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1675 if (!dev->cmb) 1676 return; 1677 dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 1678 dev->cmb_size = size; 1679 1680 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1681 &dev_attr_cmb.attr, NULL)) 1682 dev_warn(dev->ctrl.device, 1683 "failed to add sysfs attribute for CMB\n"); 1684 } 1685 1686 static inline void nvme_release_cmb(struct nvme_dev *dev) 1687 { 1688 if (dev->cmb) { 1689 iounmap(dev->cmb); 1690 dev->cmb = NULL; 1691 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1692 &dev_attr_cmb.attr, NULL); 1693 dev->cmbsz = 0; 1694 } 1695 } 1696 1697 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1698 { 1699 u64 dma_addr = dev->host_mem_descs_dma; 1700 struct nvme_command c; 1701 int ret; 1702 1703 memset(&c, 0, sizeof(c)); 1704 c.features.opcode = nvme_admin_set_features; 1705 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1706 c.features.dword11 = cpu_to_le32(bits); 1707 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1708 ilog2(dev->ctrl.page_size)); 1709 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1710 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1711 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1712 1713 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1714 if (ret) { 1715 dev_warn(dev->ctrl.device, 1716 "failed to set host mem (err %d, flags %#x).\n", 1717 ret, bits); 1718 } 1719 return ret; 1720 } 1721 1722 static void nvme_free_host_mem(struct nvme_dev *dev) 1723 { 1724 int i; 1725 1726 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1727 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1728 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1729 1730 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 1731 le64_to_cpu(desc->addr)); 1732 } 1733 1734 kfree(dev->host_mem_desc_bufs); 1735 dev->host_mem_desc_bufs = NULL; 1736 dma_free_coherent(dev->dev, 1737 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1738 dev->host_mem_descs, dev->host_mem_descs_dma); 1739 dev->host_mem_descs = NULL; 1740 dev->nr_host_mem_descs = 0; 1741 } 1742 1743 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1744 u32 chunk_size) 1745 { 1746 struct nvme_host_mem_buf_desc *descs; 1747 u32 max_entries, len; 1748 dma_addr_t descs_dma; 1749 int i = 0; 1750 void **bufs; 1751 u64 size, tmp; 1752 1753 tmp = (preferred + chunk_size - 1); 1754 do_div(tmp, chunk_size); 1755 max_entries = tmp; 1756 1757 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1758 max_entries = dev->ctrl.hmmaxd; 1759 1760 descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 1761 &descs_dma, GFP_KERNEL); 1762 if (!descs) 1763 goto out; 1764 1765 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1766 if (!bufs) 1767 goto out_free_descs; 1768 1769 for (size = 0; size < preferred && i < max_entries; size += len) { 1770 dma_addr_t dma_addr; 1771 1772 len = min_t(u64, chunk_size, preferred - size); 1773 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1774 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1775 if (!bufs[i]) 1776 break; 1777 1778 descs[i].addr = cpu_to_le64(dma_addr); 1779 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1780 i++; 1781 } 1782 1783 if (!size) 1784 goto out_free_bufs; 1785 1786 dev->nr_host_mem_descs = i; 1787 dev->host_mem_size = size; 1788 dev->host_mem_descs = descs; 1789 dev->host_mem_descs_dma = descs_dma; 1790 dev->host_mem_desc_bufs = bufs; 1791 return 0; 1792 1793 out_free_bufs: 1794 while (--i >= 0) { 1795 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1796 1797 dma_free_coherent(dev->dev, size, bufs[i], 1798 le64_to_cpu(descs[i].addr)); 1799 } 1800 1801 kfree(bufs); 1802 out_free_descs: 1803 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1804 descs_dma); 1805 out: 1806 dev->host_mem_descs = NULL; 1807 return -ENOMEM; 1808 } 1809 1810 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1811 { 1812 u32 chunk_size; 1813 1814 /* start big and work our way down */ 1815 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1816 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1817 chunk_size /= 2) { 1818 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1819 if (!min || dev->host_mem_size >= min) 1820 return 0; 1821 nvme_free_host_mem(dev); 1822 } 1823 } 1824 1825 return -ENOMEM; 1826 } 1827 1828 static int nvme_setup_host_mem(struct nvme_dev *dev) 1829 { 1830 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1831 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1832 u64 min = (u64)dev->ctrl.hmmin * 4096; 1833 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1834 int ret; 1835 1836 preferred = min(preferred, max); 1837 if (min > max) { 1838 dev_warn(dev->ctrl.device, 1839 "min host memory (%lld MiB) above limit (%d MiB).\n", 1840 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1841 nvme_free_host_mem(dev); 1842 return 0; 1843 } 1844 1845 /* 1846 * If we already have a buffer allocated check if we can reuse it. 1847 */ 1848 if (dev->host_mem_descs) { 1849 if (dev->host_mem_size >= min) 1850 enable_bits |= NVME_HOST_MEM_RETURN; 1851 else 1852 nvme_free_host_mem(dev); 1853 } 1854 1855 if (!dev->host_mem_descs) { 1856 if (nvme_alloc_host_mem(dev, min, preferred)) { 1857 dev_warn(dev->ctrl.device, 1858 "failed to allocate host memory buffer.\n"); 1859 return 0; /* controller must work without HMB */ 1860 } 1861 1862 dev_info(dev->ctrl.device, 1863 "allocated %lld MiB host memory buffer.\n", 1864 dev->host_mem_size >> ilog2(SZ_1M)); 1865 } 1866 1867 ret = nvme_set_host_mem(dev, enable_bits); 1868 if (ret) 1869 nvme_free_host_mem(dev); 1870 return ret; 1871 } 1872 1873 static int nvme_setup_io_queues(struct nvme_dev *dev) 1874 { 1875 struct nvme_queue *adminq = &dev->queues[0]; 1876 struct pci_dev *pdev = to_pci_dev(dev->dev); 1877 int result, nr_io_queues; 1878 unsigned long size; 1879 1880 struct irq_affinity affd = { 1881 .pre_vectors = 1 1882 }; 1883 1884 nr_io_queues = num_possible_cpus(); 1885 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 1886 if (result < 0) 1887 return result; 1888 1889 if (nr_io_queues == 0) 1890 return 0; 1891 1892 if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1893 result = nvme_cmb_qdepth(dev, nr_io_queues, 1894 sizeof(struct nvme_command)); 1895 if (result > 0) 1896 dev->q_depth = result; 1897 else 1898 nvme_release_cmb(dev); 1899 } 1900 1901 do { 1902 size = db_bar_size(dev, nr_io_queues); 1903 result = nvme_remap_bar(dev, size); 1904 if (!result) 1905 break; 1906 if (!--nr_io_queues) 1907 return -ENOMEM; 1908 } while (1); 1909 adminq->q_db = dev->dbs; 1910 1911 /* Deregister the admin queue's interrupt */ 1912 pci_free_irq(pdev, 0, adminq); 1913 1914 /* 1915 * If we enable msix early due to not intx, disable it again before 1916 * setting up the full range we need. 1917 */ 1918 pci_free_irq_vectors(pdev); 1919 result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 1920 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 1921 if (result <= 0) 1922 return -EIO; 1923 dev->num_vecs = result; 1924 dev->max_qid = max(result - 1, 1); 1925 1926 /* 1927 * Should investigate if there's a performance win from allocating 1928 * more queues than interrupt vectors; it might allow the submission 1929 * path to scale better, even if the receive path is limited by the 1930 * number of interrupts. 1931 */ 1932 1933 result = queue_request_irq(adminq); 1934 if (result) { 1935 adminq->cq_vector = -1; 1936 return result; 1937 } 1938 return nvme_create_io_queues(dev); 1939 } 1940 1941 static void nvme_del_queue_end(struct request *req, blk_status_t error) 1942 { 1943 struct nvme_queue *nvmeq = req->end_io_data; 1944 1945 blk_mq_free_request(req); 1946 complete(&nvmeq->dev->ioq_wait); 1947 } 1948 1949 static void nvme_del_cq_end(struct request *req, blk_status_t error) 1950 { 1951 struct nvme_queue *nvmeq = req->end_io_data; 1952 u16 start, end; 1953 1954 if (!error) { 1955 unsigned long flags; 1956 1957 spin_lock_irqsave(&nvmeq->cq_lock, flags); 1958 nvme_process_cq(nvmeq, &start, &end, -1); 1959 spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 1960 1961 nvme_complete_cqes(nvmeq, start, end); 1962 } 1963 1964 nvme_del_queue_end(req, error); 1965 } 1966 1967 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1968 { 1969 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1970 struct request *req; 1971 struct nvme_command cmd; 1972 1973 memset(&cmd, 0, sizeof(cmd)); 1974 cmd.delete_queue.opcode = opcode; 1975 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1976 1977 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1978 if (IS_ERR(req)) 1979 return PTR_ERR(req); 1980 1981 req->timeout = ADMIN_TIMEOUT; 1982 req->end_io_data = nvmeq; 1983 1984 blk_execute_rq_nowait(q, NULL, req, false, 1985 opcode == nvme_admin_delete_cq ? 1986 nvme_del_cq_end : nvme_del_queue_end); 1987 return 0; 1988 } 1989 1990 static void nvme_disable_io_queues(struct nvme_dev *dev) 1991 { 1992 int pass, queues = dev->online_queues - 1; 1993 unsigned long timeout; 1994 u8 opcode = nvme_admin_delete_sq; 1995 1996 for (pass = 0; pass < 2; pass++) { 1997 int sent = 0, i = queues; 1998 1999 reinit_completion(&dev->ioq_wait); 2000 retry: 2001 timeout = ADMIN_TIMEOUT; 2002 for (; i > 0; i--, sent++) 2003 if (nvme_delete_queue(&dev->queues[i], opcode)) 2004 break; 2005 2006 while (sent--) { 2007 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2008 if (timeout == 0) 2009 return; 2010 if (i) 2011 goto retry; 2012 } 2013 opcode = nvme_admin_delete_cq; 2014 } 2015 } 2016 2017 /* 2018 * return error value only when tagset allocation failed 2019 */ 2020 static int nvme_dev_add(struct nvme_dev *dev) 2021 { 2022 int ret; 2023 2024 if (!dev->ctrl.tagset) { 2025 dev->tagset.ops = &nvme_mq_ops; 2026 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2027 dev->tagset.timeout = NVME_IO_TIMEOUT; 2028 dev->tagset.numa_node = dev_to_node(dev->dev); 2029 dev->tagset.queue_depth = 2030 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2031 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2032 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2033 dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2034 nvme_pci_cmd_size(dev, true)); 2035 } 2036 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2037 dev->tagset.driver_data = dev; 2038 2039 ret = blk_mq_alloc_tag_set(&dev->tagset); 2040 if (ret) { 2041 dev_warn(dev->ctrl.device, 2042 "IO queues tagset allocation failed %d\n", ret); 2043 return ret; 2044 } 2045 dev->ctrl.tagset = &dev->tagset; 2046 2047 nvme_dbbuf_set(dev); 2048 } else { 2049 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2050 2051 /* Free previously allocated queues that are no longer usable */ 2052 nvme_free_queues(dev, dev->online_queues); 2053 } 2054 2055 return 0; 2056 } 2057 2058 static int nvme_pci_enable(struct nvme_dev *dev) 2059 { 2060 int result = -ENOMEM; 2061 struct pci_dev *pdev = to_pci_dev(dev->dev); 2062 2063 if (pci_enable_device_mem(pdev)) 2064 return result; 2065 2066 pci_set_master(pdev); 2067 2068 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 2069 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 2070 goto disable; 2071 2072 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2073 result = -ENODEV; 2074 goto disable; 2075 } 2076 2077 /* 2078 * Some devices and/or platforms don't advertise or work with INTx 2079 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2080 * adjust this later. 2081 */ 2082 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2083 if (result < 0) 2084 return result; 2085 2086 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2087 2088 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2089 io_queue_depth); 2090 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2091 dev->dbs = dev->bar + 4096; 2092 2093 /* 2094 * Temporary fix for the Apple controller found in the MacBook8,1 and 2095 * some MacBook7,1 to avoid controller resets and data loss. 2096 */ 2097 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2098 dev->q_depth = 2; 2099 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2100 "set queue depth=%u to work around controller resets\n", 2101 dev->q_depth); 2102 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2103 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2104 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2105 dev->q_depth = 64; 2106 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2107 "set queue depth=%u\n", dev->q_depth); 2108 } 2109 2110 nvme_map_cmb(dev); 2111 2112 pci_enable_pcie_error_reporting(pdev); 2113 pci_save_state(pdev); 2114 return 0; 2115 2116 disable: 2117 pci_disable_device(pdev); 2118 return result; 2119 } 2120 2121 static void nvme_dev_unmap(struct nvme_dev *dev) 2122 { 2123 if (dev->bar) 2124 iounmap(dev->bar); 2125 pci_release_mem_regions(to_pci_dev(dev->dev)); 2126 } 2127 2128 static void nvme_pci_disable(struct nvme_dev *dev) 2129 { 2130 struct pci_dev *pdev = to_pci_dev(dev->dev); 2131 2132 nvme_release_cmb(dev); 2133 pci_free_irq_vectors(pdev); 2134 2135 if (pci_is_enabled(pdev)) { 2136 pci_disable_pcie_error_reporting(pdev); 2137 pci_disable_device(pdev); 2138 } 2139 } 2140 2141 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2142 { 2143 int i; 2144 bool dead = true; 2145 struct pci_dev *pdev = to_pci_dev(dev->dev); 2146 2147 mutex_lock(&dev->shutdown_lock); 2148 if (pci_is_enabled(pdev)) { 2149 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2150 2151 if (dev->ctrl.state == NVME_CTRL_LIVE || 2152 dev->ctrl.state == NVME_CTRL_RESETTING) 2153 nvme_start_freeze(&dev->ctrl); 2154 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2155 pdev->error_state != pci_channel_io_normal); 2156 } 2157 2158 /* 2159 * Give the controller a chance to complete all entered requests if 2160 * doing a safe shutdown. 2161 */ 2162 if (!dead) { 2163 if (shutdown) 2164 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2165 } 2166 2167 nvme_stop_queues(&dev->ctrl); 2168 2169 if (!dead && dev->ctrl.queue_count > 0) { 2170 nvme_disable_io_queues(dev); 2171 nvme_disable_admin_queue(dev, shutdown); 2172 } 2173 for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2174 nvme_suspend_queue(&dev->queues[i]); 2175 2176 nvme_pci_disable(dev); 2177 2178 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2179 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2180 2181 /* 2182 * The driver will not be starting up queues again if shutting down so 2183 * must flush all entered requests to their failed completion to avoid 2184 * deadlocking blk-mq hot-cpu notifier. 2185 */ 2186 if (shutdown) 2187 nvme_start_queues(&dev->ctrl); 2188 mutex_unlock(&dev->shutdown_lock); 2189 } 2190 2191 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2192 { 2193 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2194 PAGE_SIZE, PAGE_SIZE, 0); 2195 if (!dev->prp_page_pool) 2196 return -ENOMEM; 2197 2198 /* Optimisation for I/Os between 4k and 128k */ 2199 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2200 256, 256, 0); 2201 if (!dev->prp_small_pool) { 2202 dma_pool_destroy(dev->prp_page_pool); 2203 return -ENOMEM; 2204 } 2205 return 0; 2206 } 2207 2208 static void nvme_release_prp_pools(struct nvme_dev *dev) 2209 { 2210 dma_pool_destroy(dev->prp_page_pool); 2211 dma_pool_destroy(dev->prp_small_pool); 2212 } 2213 2214 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2215 { 2216 struct nvme_dev *dev = to_nvme_dev(ctrl); 2217 2218 nvme_dbbuf_dma_free(dev); 2219 put_device(dev->dev); 2220 if (dev->tagset.tags) 2221 blk_mq_free_tag_set(&dev->tagset); 2222 if (dev->ctrl.admin_q) 2223 blk_put_queue(dev->ctrl.admin_q); 2224 kfree(dev->queues); 2225 free_opal_dev(dev->ctrl.opal_dev); 2226 mempool_destroy(dev->iod_mempool); 2227 kfree(dev); 2228 } 2229 2230 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2231 { 2232 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2233 2234 nvme_get_ctrl(&dev->ctrl); 2235 nvme_dev_disable(dev, false); 2236 nvme_kill_queues(&dev->ctrl); 2237 if (!queue_work(nvme_wq, &dev->remove_work)) 2238 nvme_put_ctrl(&dev->ctrl); 2239 } 2240 2241 static void nvme_reset_work(struct work_struct *work) 2242 { 2243 struct nvme_dev *dev = 2244 container_of(work, struct nvme_dev, ctrl.reset_work); 2245 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2246 int result = -ENODEV; 2247 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2248 2249 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2250 goto out; 2251 2252 /* 2253 * If we're called to reset a live controller first shut it down before 2254 * moving on. 2255 */ 2256 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2257 nvme_dev_disable(dev, false); 2258 2259 /* 2260 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2261 * initializing procedure here. 2262 */ 2263 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2264 dev_warn(dev->ctrl.device, 2265 "failed to mark controller CONNECTING\n"); 2266 goto out; 2267 } 2268 2269 result = nvme_pci_enable(dev); 2270 if (result) 2271 goto out; 2272 2273 result = nvme_pci_configure_admin_queue(dev); 2274 if (result) 2275 goto out; 2276 2277 result = nvme_alloc_admin_tags(dev); 2278 if (result) 2279 goto out; 2280 2281 /* 2282 * Limit the max command size to prevent iod->sg allocations going 2283 * over a single page. 2284 */ 2285 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2286 dev->ctrl.max_segments = NVME_MAX_SEGS; 2287 2288 result = nvme_init_identify(&dev->ctrl); 2289 if (result) 2290 goto out; 2291 2292 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2293 if (!dev->ctrl.opal_dev) 2294 dev->ctrl.opal_dev = 2295 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2296 else if (was_suspend) 2297 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2298 } else { 2299 free_opal_dev(dev->ctrl.opal_dev); 2300 dev->ctrl.opal_dev = NULL; 2301 } 2302 2303 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2304 result = nvme_dbbuf_dma_alloc(dev); 2305 if (result) 2306 dev_warn(dev->dev, 2307 "unable to allocate dma for dbbuf\n"); 2308 } 2309 2310 if (dev->ctrl.hmpre) { 2311 result = nvme_setup_host_mem(dev); 2312 if (result < 0) 2313 goto out; 2314 } 2315 2316 result = nvme_setup_io_queues(dev); 2317 if (result) 2318 goto out; 2319 2320 /* 2321 * Keep the controller around but remove all namespaces if we don't have 2322 * any working I/O queue. 2323 */ 2324 if (dev->online_queues < 2) { 2325 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2326 nvme_kill_queues(&dev->ctrl); 2327 nvme_remove_namespaces(&dev->ctrl); 2328 new_state = NVME_CTRL_ADMIN_ONLY; 2329 } else { 2330 nvme_start_queues(&dev->ctrl); 2331 nvme_wait_freeze(&dev->ctrl); 2332 /* hit this only when allocate tagset fails */ 2333 if (nvme_dev_add(dev)) 2334 new_state = NVME_CTRL_ADMIN_ONLY; 2335 nvme_unfreeze(&dev->ctrl); 2336 } 2337 2338 /* 2339 * If only admin queue live, keep it to do further investigation or 2340 * recovery. 2341 */ 2342 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2343 dev_warn(dev->ctrl.device, 2344 "failed to mark controller state %d\n", new_state); 2345 goto out; 2346 } 2347 2348 nvme_start_ctrl(&dev->ctrl); 2349 return; 2350 2351 out: 2352 nvme_remove_dead_ctrl(dev, result); 2353 } 2354 2355 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2356 { 2357 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2358 struct pci_dev *pdev = to_pci_dev(dev->dev); 2359 2360 if (pci_get_drvdata(pdev)) 2361 device_release_driver(&pdev->dev); 2362 nvme_put_ctrl(&dev->ctrl); 2363 } 2364 2365 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2366 { 2367 *val = readl(to_nvme_dev(ctrl)->bar + off); 2368 return 0; 2369 } 2370 2371 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2372 { 2373 writel(val, to_nvme_dev(ctrl)->bar + off); 2374 return 0; 2375 } 2376 2377 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2378 { 2379 *val = readq(to_nvme_dev(ctrl)->bar + off); 2380 return 0; 2381 } 2382 2383 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2384 { 2385 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2386 2387 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2388 } 2389 2390 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2391 .name = "pcie", 2392 .module = THIS_MODULE, 2393 .flags = NVME_F_METADATA_SUPPORTED, 2394 .reg_read32 = nvme_pci_reg_read32, 2395 .reg_write32 = nvme_pci_reg_write32, 2396 .reg_read64 = nvme_pci_reg_read64, 2397 .free_ctrl = nvme_pci_free_ctrl, 2398 .submit_async_event = nvme_pci_submit_async_event, 2399 .get_address = nvme_pci_get_address, 2400 }; 2401 2402 static int nvme_dev_map(struct nvme_dev *dev) 2403 { 2404 struct pci_dev *pdev = to_pci_dev(dev->dev); 2405 2406 if (pci_request_mem_regions(pdev, "nvme")) 2407 return -ENODEV; 2408 2409 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2410 goto release; 2411 2412 return 0; 2413 release: 2414 pci_release_mem_regions(pdev); 2415 return -ENODEV; 2416 } 2417 2418 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2419 { 2420 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2421 /* 2422 * Several Samsung devices seem to drop off the PCIe bus 2423 * randomly when APST is on and uses the deepest sleep state. 2424 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2425 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2426 * 950 PRO 256GB", but it seems to be restricted to two Dell 2427 * laptops. 2428 */ 2429 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2430 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2431 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2432 return NVME_QUIRK_NO_DEEPEST_PS; 2433 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2434 /* 2435 * Samsung SSD 960 EVO drops off the PCIe bus after system 2436 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2437 * within few minutes after bootup on a Coffee Lake board - 2438 * ASUS PRIME Z370-A 2439 */ 2440 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2441 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2442 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2443 return NVME_QUIRK_NO_APST; 2444 } 2445 2446 return 0; 2447 } 2448 2449 static void nvme_async_probe(void *data, async_cookie_t cookie) 2450 { 2451 struct nvme_dev *dev = data; 2452 2453 nvme_reset_ctrl_sync(&dev->ctrl); 2454 flush_work(&dev->ctrl.scan_work); 2455 nvme_put_ctrl(&dev->ctrl); 2456 } 2457 2458 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2459 { 2460 int node, result = -ENOMEM; 2461 struct nvme_dev *dev; 2462 unsigned long quirks = id->driver_data; 2463 size_t alloc_size; 2464 2465 node = dev_to_node(&pdev->dev); 2466 if (node == NUMA_NO_NODE) 2467 set_dev_node(&pdev->dev, first_memory_node); 2468 2469 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2470 if (!dev) 2471 return -ENOMEM; 2472 2473 dev->queues = kcalloc_node(num_possible_cpus() + 1, 2474 sizeof(struct nvme_queue), GFP_KERNEL, node); 2475 if (!dev->queues) 2476 goto free; 2477 2478 dev->dev = get_device(&pdev->dev); 2479 pci_set_drvdata(pdev, dev); 2480 2481 result = nvme_dev_map(dev); 2482 if (result) 2483 goto put_pci; 2484 2485 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2486 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2487 mutex_init(&dev->shutdown_lock); 2488 init_completion(&dev->ioq_wait); 2489 2490 result = nvme_setup_prp_pools(dev); 2491 if (result) 2492 goto unmap; 2493 2494 quirks |= check_vendor_combination_bug(pdev); 2495 2496 /* 2497 * Double check that our mempool alloc size will cover the biggest 2498 * command we support. 2499 */ 2500 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2501 NVME_MAX_SEGS, true); 2502 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2503 2504 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2505 mempool_kfree, 2506 (void *) alloc_size, 2507 GFP_KERNEL, node); 2508 if (!dev->iod_mempool) { 2509 result = -ENOMEM; 2510 goto release_pools; 2511 } 2512 2513 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2514 quirks); 2515 if (result) 2516 goto release_mempool; 2517 2518 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2519 2520 nvme_get_ctrl(&dev->ctrl); 2521 async_schedule(nvme_async_probe, dev); 2522 2523 return 0; 2524 2525 release_mempool: 2526 mempool_destroy(dev->iod_mempool); 2527 release_pools: 2528 nvme_release_prp_pools(dev); 2529 unmap: 2530 nvme_dev_unmap(dev); 2531 put_pci: 2532 put_device(dev->dev); 2533 free: 2534 kfree(dev->queues); 2535 kfree(dev); 2536 return result; 2537 } 2538 2539 static void nvme_reset_prepare(struct pci_dev *pdev) 2540 { 2541 struct nvme_dev *dev = pci_get_drvdata(pdev); 2542 nvme_dev_disable(dev, false); 2543 } 2544 2545 static void nvme_reset_done(struct pci_dev *pdev) 2546 { 2547 struct nvme_dev *dev = pci_get_drvdata(pdev); 2548 nvme_reset_ctrl_sync(&dev->ctrl); 2549 } 2550 2551 static void nvme_shutdown(struct pci_dev *pdev) 2552 { 2553 struct nvme_dev *dev = pci_get_drvdata(pdev); 2554 nvme_dev_disable(dev, true); 2555 } 2556 2557 /* 2558 * The driver's remove may be called on a device in a partially initialized 2559 * state. This function must not have any dependencies on the device state in 2560 * order to proceed. 2561 */ 2562 static void nvme_remove(struct pci_dev *pdev) 2563 { 2564 struct nvme_dev *dev = pci_get_drvdata(pdev); 2565 2566 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2567 2568 cancel_work_sync(&dev->ctrl.reset_work); 2569 pci_set_drvdata(pdev, NULL); 2570 2571 if (!pci_device_is_present(pdev)) { 2572 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2573 nvme_dev_disable(dev, true); 2574 } 2575 2576 flush_work(&dev->ctrl.reset_work); 2577 nvme_stop_ctrl(&dev->ctrl); 2578 nvme_remove_namespaces(&dev->ctrl); 2579 nvme_dev_disable(dev, true); 2580 nvme_free_host_mem(dev); 2581 nvme_dev_remove_admin(dev); 2582 nvme_free_queues(dev, 0); 2583 nvme_uninit_ctrl(&dev->ctrl); 2584 nvme_release_prp_pools(dev); 2585 nvme_dev_unmap(dev); 2586 nvme_put_ctrl(&dev->ctrl); 2587 } 2588 2589 #ifdef CONFIG_PM_SLEEP 2590 static int nvme_suspend(struct device *dev) 2591 { 2592 struct pci_dev *pdev = to_pci_dev(dev); 2593 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2594 2595 nvme_dev_disable(ndev, true); 2596 return 0; 2597 } 2598 2599 static int nvme_resume(struct device *dev) 2600 { 2601 struct pci_dev *pdev = to_pci_dev(dev); 2602 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2603 2604 nvme_reset_ctrl(&ndev->ctrl); 2605 return 0; 2606 } 2607 #endif 2608 2609 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2610 2611 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2612 pci_channel_state_t state) 2613 { 2614 struct nvme_dev *dev = pci_get_drvdata(pdev); 2615 2616 /* 2617 * A frozen channel requires a reset. When detected, this method will 2618 * shutdown the controller to quiesce. The controller will be restarted 2619 * after the slot reset through driver's slot_reset callback. 2620 */ 2621 switch (state) { 2622 case pci_channel_io_normal: 2623 return PCI_ERS_RESULT_CAN_RECOVER; 2624 case pci_channel_io_frozen: 2625 dev_warn(dev->ctrl.device, 2626 "frozen state error detected, reset controller\n"); 2627 nvme_dev_disable(dev, false); 2628 return PCI_ERS_RESULT_NEED_RESET; 2629 case pci_channel_io_perm_failure: 2630 dev_warn(dev->ctrl.device, 2631 "failure state error detected, request disconnect\n"); 2632 return PCI_ERS_RESULT_DISCONNECT; 2633 } 2634 return PCI_ERS_RESULT_NEED_RESET; 2635 } 2636 2637 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2638 { 2639 struct nvme_dev *dev = pci_get_drvdata(pdev); 2640 2641 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2642 pci_restore_state(pdev); 2643 nvme_reset_ctrl(&dev->ctrl); 2644 return PCI_ERS_RESULT_RECOVERED; 2645 } 2646 2647 static void nvme_error_resume(struct pci_dev *pdev) 2648 { 2649 struct nvme_dev *dev = pci_get_drvdata(pdev); 2650 2651 flush_work(&dev->ctrl.reset_work); 2652 pci_cleanup_aer_uncorrect_error_status(pdev); 2653 } 2654 2655 static const struct pci_error_handlers nvme_err_handler = { 2656 .error_detected = nvme_error_detected, 2657 .slot_reset = nvme_slot_reset, 2658 .resume = nvme_error_resume, 2659 .reset_prepare = nvme_reset_prepare, 2660 .reset_done = nvme_reset_done, 2661 }; 2662 2663 static const struct pci_device_id nvme_id_table[] = { 2664 { PCI_VDEVICE(INTEL, 0x0953), 2665 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2666 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2667 { PCI_VDEVICE(INTEL, 0x0a53), 2668 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2669 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2670 { PCI_VDEVICE(INTEL, 0x0a54), 2671 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2672 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2673 { PCI_VDEVICE(INTEL, 0x0a55), 2674 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2675 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2676 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 2677 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 2678 NVME_QUIRK_MEDIUM_PRIO_SQ }, 2679 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2680 .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 2681 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 2682 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2683 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 2684 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2685 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 2686 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2687 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2688 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2689 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2690 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2691 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2692 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2693 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2694 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2695 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2696 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2697 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2698 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2699 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2700 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2701 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 2702 { 0, } 2703 }; 2704 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2705 2706 static struct pci_driver nvme_driver = { 2707 .name = "nvme", 2708 .id_table = nvme_id_table, 2709 .probe = nvme_probe, 2710 .remove = nvme_remove, 2711 .shutdown = nvme_shutdown, 2712 .driver = { 2713 .pm = &nvme_dev_pm_ops, 2714 }, 2715 .sriov_configure = pci_sriov_configure_simple, 2716 .err_handler = &nvme_err_handler, 2717 }; 2718 2719 static int __init nvme_init(void) 2720 { 2721 return pci_register_driver(&nvme_driver); 2722 } 2723 2724 static void __exit nvme_exit(void) 2725 { 2726 pci_unregister_driver(&nvme_driver); 2727 flush_workqueue(nvme_wq); 2728 _nvme_check_size(); 2729 } 2730 2731 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2732 MODULE_LICENSE("GPL"); 2733 MODULE_VERSION("1.0"); 2734 module_init(nvme_init); 2735 module_exit(nvme_exit); 2736