xref: /openbmc/linux/drivers/nvme/host/pci.c (revision b98235d3)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * NVM Express device driver
4  * Copyright (c) 2011-2014, Intel Corporation.
5  */
6 
7 #include <linux/acpi.h>
8 #include <linux/aer.h>
9 #include <linux/async.h>
10 #include <linux/blkdev.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/blk-integrity.h>
14 #include <linux/dmi.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/memremap.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/once.h>
23 #include <linux/pci.h>
24 #include <linux/suspend.h>
25 #include <linux/t10-pi.h>
26 #include <linux/types.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
31 
32 #include "trace.h"
33 #include "nvme.h"
34 
35 #define SQ_SIZE(q)	((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q)	((q)->q_depth * sizeof(struct nvme_completion))
37 
38 #define SGES_PER_PAGE	(PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39 
40 /*
41  * These can be higher, but we need to ensure that any command doesn't
42  * require an sg allocation that needs more than a page of data.
43  */
44 #define NVME_MAX_KB_SZ	4096
45 #define NVME_MAX_SEGS	127
46 
47 static int use_threaded_interrupts;
48 module_param(use_threaded_interrupts, int, 0444);
49 
50 static bool use_cmb_sqes = true;
51 module_param(use_cmb_sqes, bool, 0444);
52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
53 
54 static unsigned int max_host_mem_size_mb = 128;
55 module_param(max_host_mem_size_mb, uint, 0444);
56 MODULE_PARM_DESC(max_host_mem_size_mb,
57 	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
58 
59 static unsigned int sgl_threshold = SZ_32K;
60 module_param(sgl_threshold, uint, 0644);
61 MODULE_PARM_DESC(sgl_threshold,
62 		"Use SGLs when average request segment size is larger or equal to "
63 		"this size. Use 0 to disable SGLs.");
64 
65 #define NVME_PCI_MIN_QUEUE_SIZE 2
66 #define NVME_PCI_MAX_QUEUE_SIZE 4095
67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
68 static const struct kernel_param_ops io_queue_depth_ops = {
69 	.set = io_queue_depth_set,
70 	.get = param_get_uint,
71 };
72 
73 static unsigned int io_queue_depth = 1024;
74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
76 
77 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
78 {
79 	unsigned int n;
80 	int ret;
81 
82 	ret = kstrtouint(val, 10, &n);
83 	if (ret != 0 || n > num_possible_cpus())
84 		return -EINVAL;
85 	return param_set_uint(val, kp);
86 }
87 
88 static const struct kernel_param_ops io_queue_count_ops = {
89 	.set = io_queue_count_set,
90 	.get = param_get_uint,
91 };
92 
93 static unsigned int write_queues;
94 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
95 MODULE_PARM_DESC(write_queues,
96 	"Number of queues to use for writes. If not set, reads and writes "
97 	"will share a queue set.");
98 
99 static unsigned int poll_queues;
100 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
101 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
102 
103 static bool noacpi;
104 module_param(noacpi, bool, 0444);
105 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
106 
107 struct nvme_dev;
108 struct nvme_queue;
109 
110 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
111 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
112 
113 /*
114  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
115  */
116 struct nvme_dev {
117 	struct nvme_queue *queues;
118 	struct blk_mq_tag_set tagset;
119 	struct blk_mq_tag_set admin_tagset;
120 	u32 __iomem *dbs;
121 	struct device *dev;
122 	struct dma_pool *prp_page_pool;
123 	struct dma_pool *prp_small_pool;
124 	unsigned online_queues;
125 	unsigned max_qid;
126 	unsigned io_queues[HCTX_MAX_TYPES];
127 	unsigned int num_vecs;
128 	u32 q_depth;
129 	int io_sqes;
130 	u32 db_stride;
131 	void __iomem *bar;
132 	unsigned long bar_mapped_size;
133 	struct work_struct remove_work;
134 	struct mutex shutdown_lock;
135 	bool subsystem;
136 	u64 cmb_size;
137 	bool cmb_use_sqes;
138 	u32 cmbsz;
139 	u32 cmbloc;
140 	struct nvme_ctrl ctrl;
141 	u32 last_ps;
142 	bool hmb;
143 
144 	mempool_t *iod_mempool;
145 
146 	/* shadow doorbell buffer support: */
147 	u32 *dbbuf_dbs;
148 	dma_addr_t dbbuf_dbs_dma_addr;
149 	u32 *dbbuf_eis;
150 	dma_addr_t dbbuf_eis_dma_addr;
151 
152 	/* host memory buffer support: */
153 	u64 host_mem_size;
154 	u32 nr_host_mem_descs;
155 	dma_addr_t host_mem_descs_dma;
156 	struct nvme_host_mem_buf_desc *host_mem_descs;
157 	void **host_mem_desc_bufs;
158 	unsigned int nr_allocated_queues;
159 	unsigned int nr_write_queues;
160 	unsigned int nr_poll_queues;
161 
162 	bool attrs_added;
163 };
164 
165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
166 {
167 	return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
168 			NVME_PCI_MAX_QUEUE_SIZE);
169 }
170 
171 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
172 {
173 	return qid * 2 * stride;
174 }
175 
176 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
177 {
178 	return (qid * 2 + 1) * stride;
179 }
180 
181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
182 {
183 	return container_of(ctrl, struct nvme_dev, ctrl);
184 }
185 
186 /*
187  * An NVM Express queue.  Each device has at least two (one for admin
188  * commands and one for I/O commands).
189  */
190 struct nvme_queue {
191 	struct nvme_dev *dev;
192 	spinlock_t sq_lock;
193 	void *sq_cmds;
194 	 /* only used for poll queues: */
195 	spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
196 	struct nvme_completion *cqes;
197 	dma_addr_t sq_dma_addr;
198 	dma_addr_t cq_dma_addr;
199 	u32 __iomem *q_db;
200 	u32 q_depth;
201 	u16 cq_vector;
202 	u16 sq_tail;
203 	u16 last_sq_tail;
204 	u16 cq_head;
205 	u16 qid;
206 	u8 cq_phase;
207 	u8 sqes;
208 	unsigned long flags;
209 #define NVMEQ_ENABLED		0
210 #define NVMEQ_SQ_CMB		1
211 #define NVMEQ_DELETE_ERROR	2
212 #define NVMEQ_POLLED		3
213 	u32 *dbbuf_sq_db;
214 	u32 *dbbuf_cq_db;
215 	u32 *dbbuf_sq_ei;
216 	u32 *dbbuf_cq_ei;
217 	struct completion delete_done;
218 };
219 
220 /*
221  * The nvme_iod describes the data in an I/O.
222  *
223  * The sg pointer contains the list of PRP/SGL chunk allocations in addition
224  * to the actual struct scatterlist.
225  */
226 struct nvme_iod {
227 	struct nvme_request req;
228 	struct nvme_command cmd;
229 	struct nvme_queue *nvmeq;
230 	bool use_sgl;
231 	int aborted;
232 	int npages;		/* In the PRP list. 0 means small pool in use */
233 	int nents;		/* Used in scatterlist */
234 	dma_addr_t first_dma;
235 	unsigned int dma_len;	/* length of single DMA segment mapping */
236 	dma_addr_t meta_dma;
237 	struct scatterlist *sg;
238 };
239 
240 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
241 {
242 	return dev->nr_allocated_queues * 8 * dev->db_stride;
243 }
244 
245 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
246 {
247 	unsigned int mem_size = nvme_dbbuf_size(dev);
248 
249 	if (dev->dbbuf_dbs) {
250 		/*
251 		 * Clear the dbbuf memory so the driver doesn't observe stale
252 		 * values from the previous instantiation.
253 		 */
254 		memset(dev->dbbuf_dbs, 0, mem_size);
255 		memset(dev->dbbuf_eis, 0, mem_size);
256 		return 0;
257 	}
258 
259 	dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
260 					    &dev->dbbuf_dbs_dma_addr,
261 					    GFP_KERNEL);
262 	if (!dev->dbbuf_dbs)
263 		return -ENOMEM;
264 	dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
265 					    &dev->dbbuf_eis_dma_addr,
266 					    GFP_KERNEL);
267 	if (!dev->dbbuf_eis) {
268 		dma_free_coherent(dev->dev, mem_size,
269 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
270 		dev->dbbuf_dbs = NULL;
271 		return -ENOMEM;
272 	}
273 
274 	return 0;
275 }
276 
277 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
278 {
279 	unsigned int mem_size = nvme_dbbuf_size(dev);
280 
281 	if (dev->dbbuf_dbs) {
282 		dma_free_coherent(dev->dev, mem_size,
283 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
284 		dev->dbbuf_dbs = NULL;
285 	}
286 	if (dev->dbbuf_eis) {
287 		dma_free_coherent(dev->dev, mem_size,
288 				  dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
289 		dev->dbbuf_eis = NULL;
290 	}
291 }
292 
293 static void nvme_dbbuf_init(struct nvme_dev *dev,
294 			    struct nvme_queue *nvmeq, int qid)
295 {
296 	if (!dev->dbbuf_dbs || !qid)
297 		return;
298 
299 	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
300 	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
301 	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
302 	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
303 }
304 
305 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
306 {
307 	if (!nvmeq->qid)
308 		return;
309 
310 	nvmeq->dbbuf_sq_db = NULL;
311 	nvmeq->dbbuf_cq_db = NULL;
312 	nvmeq->dbbuf_sq_ei = NULL;
313 	nvmeq->dbbuf_cq_ei = NULL;
314 }
315 
316 static void nvme_dbbuf_set(struct nvme_dev *dev)
317 {
318 	struct nvme_command c = { };
319 	unsigned int i;
320 
321 	if (!dev->dbbuf_dbs)
322 		return;
323 
324 	c.dbbuf.opcode = nvme_admin_dbbuf;
325 	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
326 	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
327 
328 	if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
329 		dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
330 		/* Free memory and continue on */
331 		nvme_dbbuf_dma_free(dev);
332 
333 		for (i = 1; i <= dev->online_queues; i++)
334 			nvme_dbbuf_free(&dev->queues[i]);
335 	}
336 }
337 
338 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
339 {
340 	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
341 }
342 
343 /* Update dbbuf and return true if an MMIO is required */
344 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
345 					      volatile u32 *dbbuf_ei)
346 {
347 	if (dbbuf_db) {
348 		u16 old_value;
349 
350 		/*
351 		 * Ensure that the queue is written before updating
352 		 * the doorbell in memory
353 		 */
354 		wmb();
355 
356 		old_value = *dbbuf_db;
357 		*dbbuf_db = value;
358 
359 		/*
360 		 * Ensure that the doorbell is updated before reading the event
361 		 * index from memory.  The controller needs to provide similar
362 		 * ordering to ensure the envent index is updated before reading
363 		 * the doorbell.
364 		 */
365 		mb();
366 
367 		if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
368 			return false;
369 	}
370 
371 	return true;
372 }
373 
374 /*
375  * Will slightly overestimate the number of pages needed.  This is OK
376  * as it only leads to a small amount of wasted memory for the lifetime of
377  * the I/O.
378  */
379 static int nvme_pci_npages_prp(void)
380 {
381 	unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
382 				      NVME_CTRL_PAGE_SIZE);
383 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
384 }
385 
386 /*
387  * Calculates the number of pages needed for the SGL segments. For example a 4k
388  * page can accommodate 256 SGL descriptors.
389  */
390 static int nvme_pci_npages_sgl(void)
391 {
392 	return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
393 			PAGE_SIZE);
394 }
395 
396 static size_t nvme_pci_iod_alloc_size(void)
397 {
398 	size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
399 
400 	return sizeof(__le64 *) * npages +
401 		sizeof(struct scatterlist) * NVME_MAX_SEGS;
402 }
403 
404 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
405 				unsigned int hctx_idx)
406 {
407 	struct nvme_dev *dev = data;
408 	struct nvme_queue *nvmeq = &dev->queues[0];
409 
410 	WARN_ON(hctx_idx != 0);
411 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
412 
413 	hctx->driver_data = nvmeq;
414 	return 0;
415 }
416 
417 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
418 			  unsigned int hctx_idx)
419 {
420 	struct nvme_dev *dev = data;
421 	struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
422 
423 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
424 	hctx->driver_data = nvmeq;
425 	return 0;
426 }
427 
428 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
429 		struct request *req, unsigned int hctx_idx,
430 		unsigned int numa_node)
431 {
432 	struct nvme_dev *dev = set->driver_data;
433 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
434 	int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
435 	struct nvme_queue *nvmeq = &dev->queues[queue_idx];
436 
437 	BUG_ON(!nvmeq);
438 	iod->nvmeq = nvmeq;
439 
440 	nvme_req(req)->ctrl = &dev->ctrl;
441 	nvme_req(req)->cmd = &iod->cmd;
442 	return 0;
443 }
444 
445 static int queue_irq_offset(struct nvme_dev *dev)
446 {
447 	/* if we have more than 1 vec, admin queue offsets us by 1 */
448 	if (dev->num_vecs > 1)
449 		return 1;
450 
451 	return 0;
452 }
453 
454 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
455 {
456 	struct nvme_dev *dev = set->driver_data;
457 	int i, qoff, offset;
458 
459 	offset = queue_irq_offset(dev);
460 	for (i = 0, qoff = 0; i < set->nr_maps; i++) {
461 		struct blk_mq_queue_map *map = &set->map[i];
462 
463 		map->nr_queues = dev->io_queues[i];
464 		if (!map->nr_queues) {
465 			BUG_ON(i == HCTX_TYPE_DEFAULT);
466 			continue;
467 		}
468 
469 		/*
470 		 * The poll queue(s) doesn't have an IRQ (and hence IRQ
471 		 * affinity), so use the regular blk-mq cpu mapping
472 		 */
473 		map->queue_offset = qoff;
474 		if (i != HCTX_TYPE_POLL && offset)
475 			blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
476 		else
477 			blk_mq_map_queues(map);
478 		qoff += map->nr_queues;
479 		offset += map->nr_queues;
480 	}
481 
482 	return 0;
483 }
484 
485 /*
486  * Write sq tail if we are asked to, or if the next command would wrap.
487  */
488 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
489 {
490 	if (!write_sq) {
491 		u16 next_tail = nvmeq->sq_tail + 1;
492 
493 		if (next_tail == nvmeq->q_depth)
494 			next_tail = 0;
495 		if (next_tail != nvmeq->last_sq_tail)
496 			return;
497 	}
498 
499 	if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
500 			nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
501 		writel(nvmeq->sq_tail, nvmeq->q_db);
502 	nvmeq->last_sq_tail = nvmeq->sq_tail;
503 }
504 
505 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
506 				    struct nvme_command *cmd)
507 {
508 	memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
509 		absolute_pointer(cmd), sizeof(*cmd));
510 	if (++nvmeq->sq_tail == nvmeq->q_depth)
511 		nvmeq->sq_tail = 0;
512 }
513 
514 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
515 {
516 	struct nvme_queue *nvmeq = hctx->driver_data;
517 
518 	spin_lock(&nvmeq->sq_lock);
519 	if (nvmeq->sq_tail != nvmeq->last_sq_tail)
520 		nvme_write_sq_db(nvmeq, true);
521 	spin_unlock(&nvmeq->sq_lock);
522 }
523 
524 static void **nvme_pci_iod_list(struct request *req)
525 {
526 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
527 	return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
528 }
529 
530 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
531 {
532 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
533 	int nseg = blk_rq_nr_phys_segments(req);
534 	unsigned int avg_seg_size;
535 
536 	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
537 
538 	if (!nvme_ctrl_sgl_supported(&dev->ctrl))
539 		return false;
540 	if (!iod->nvmeq->qid)
541 		return false;
542 	if (!sgl_threshold || avg_seg_size < sgl_threshold)
543 		return false;
544 	return true;
545 }
546 
547 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
548 {
549 	const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
550 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
551 	dma_addr_t dma_addr = iod->first_dma;
552 	int i;
553 
554 	for (i = 0; i < iod->npages; i++) {
555 		__le64 *prp_list = nvme_pci_iod_list(req)[i];
556 		dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
557 
558 		dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
559 		dma_addr = next_dma_addr;
560 	}
561 }
562 
563 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
564 {
565 	const int last_sg = SGES_PER_PAGE - 1;
566 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
567 	dma_addr_t dma_addr = iod->first_dma;
568 	int i;
569 
570 	for (i = 0; i < iod->npages; i++) {
571 		struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
572 		dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
573 
574 		dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
575 		dma_addr = next_dma_addr;
576 	}
577 }
578 
579 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
580 {
581 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
582 
583 	if (is_pci_p2pdma_page(sg_page(iod->sg)))
584 		pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
585 				    rq_dma_dir(req));
586 	else
587 		dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
588 }
589 
590 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
591 {
592 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
593 
594 	if (iod->dma_len) {
595 		dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
596 			       rq_dma_dir(req));
597 		return;
598 	}
599 
600 	WARN_ON_ONCE(!iod->nents);
601 
602 	nvme_unmap_sg(dev, req);
603 	if (iod->npages == 0)
604 		dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
605 			      iod->first_dma);
606 	else if (iod->use_sgl)
607 		nvme_free_sgls(dev, req);
608 	else
609 		nvme_free_prps(dev, req);
610 	mempool_free(iod->sg, dev->iod_mempool);
611 }
612 
613 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
614 {
615 	int i;
616 	struct scatterlist *sg;
617 
618 	for_each_sg(sgl, sg, nents, i) {
619 		dma_addr_t phys = sg_phys(sg);
620 		pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
621 			"dma_address:%pad dma_length:%d\n",
622 			i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
623 			sg_dma_len(sg));
624 	}
625 }
626 
627 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
628 		struct request *req, struct nvme_rw_command *cmnd)
629 {
630 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
631 	struct dma_pool *pool;
632 	int length = blk_rq_payload_bytes(req);
633 	struct scatterlist *sg = iod->sg;
634 	int dma_len = sg_dma_len(sg);
635 	u64 dma_addr = sg_dma_address(sg);
636 	int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
637 	__le64 *prp_list;
638 	void **list = nvme_pci_iod_list(req);
639 	dma_addr_t prp_dma;
640 	int nprps, i;
641 
642 	length -= (NVME_CTRL_PAGE_SIZE - offset);
643 	if (length <= 0) {
644 		iod->first_dma = 0;
645 		goto done;
646 	}
647 
648 	dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
649 	if (dma_len) {
650 		dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
651 	} else {
652 		sg = sg_next(sg);
653 		dma_addr = sg_dma_address(sg);
654 		dma_len = sg_dma_len(sg);
655 	}
656 
657 	if (length <= NVME_CTRL_PAGE_SIZE) {
658 		iod->first_dma = dma_addr;
659 		goto done;
660 	}
661 
662 	nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
663 	if (nprps <= (256 / 8)) {
664 		pool = dev->prp_small_pool;
665 		iod->npages = 0;
666 	} else {
667 		pool = dev->prp_page_pool;
668 		iod->npages = 1;
669 	}
670 
671 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
672 	if (!prp_list) {
673 		iod->first_dma = dma_addr;
674 		iod->npages = -1;
675 		return BLK_STS_RESOURCE;
676 	}
677 	list[0] = prp_list;
678 	iod->first_dma = prp_dma;
679 	i = 0;
680 	for (;;) {
681 		if (i == NVME_CTRL_PAGE_SIZE >> 3) {
682 			__le64 *old_prp_list = prp_list;
683 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
684 			if (!prp_list)
685 				goto free_prps;
686 			list[iod->npages++] = prp_list;
687 			prp_list[0] = old_prp_list[i - 1];
688 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
689 			i = 1;
690 		}
691 		prp_list[i++] = cpu_to_le64(dma_addr);
692 		dma_len -= NVME_CTRL_PAGE_SIZE;
693 		dma_addr += NVME_CTRL_PAGE_SIZE;
694 		length -= NVME_CTRL_PAGE_SIZE;
695 		if (length <= 0)
696 			break;
697 		if (dma_len > 0)
698 			continue;
699 		if (unlikely(dma_len < 0))
700 			goto bad_sgl;
701 		sg = sg_next(sg);
702 		dma_addr = sg_dma_address(sg);
703 		dma_len = sg_dma_len(sg);
704 	}
705 done:
706 	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
707 	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
708 	return BLK_STS_OK;
709 free_prps:
710 	nvme_free_prps(dev, req);
711 	return BLK_STS_RESOURCE;
712 bad_sgl:
713 	WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
714 			"Invalid SGL for payload:%d nents:%d\n",
715 			blk_rq_payload_bytes(req), iod->nents);
716 	return BLK_STS_IOERR;
717 }
718 
719 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
720 		struct scatterlist *sg)
721 {
722 	sge->addr = cpu_to_le64(sg_dma_address(sg));
723 	sge->length = cpu_to_le32(sg_dma_len(sg));
724 	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
725 }
726 
727 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
728 		dma_addr_t dma_addr, int entries)
729 {
730 	sge->addr = cpu_to_le64(dma_addr);
731 	if (entries < SGES_PER_PAGE) {
732 		sge->length = cpu_to_le32(entries * sizeof(*sge));
733 		sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
734 	} else {
735 		sge->length = cpu_to_le32(PAGE_SIZE);
736 		sge->type = NVME_SGL_FMT_SEG_DESC << 4;
737 	}
738 }
739 
740 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
741 		struct request *req, struct nvme_rw_command *cmd, int entries)
742 {
743 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
744 	struct dma_pool *pool;
745 	struct nvme_sgl_desc *sg_list;
746 	struct scatterlist *sg = iod->sg;
747 	dma_addr_t sgl_dma;
748 	int i = 0;
749 
750 	/* setting the transfer type as SGL */
751 	cmd->flags = NVME_CMD_SGL_METABUF;
752 
753 	if (entries == 1) {
754 		nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
755 		return BLK_STS_OK;
756 	}
757 
758 	if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
759 		pool = dev->prp_small_pool;
760 		iod->npages = 0;
761 	} else {
762 		pool = dev->prp_page_pool;
763 		iod->npages = 1;
764 	}
765 
766 	sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
767 	if (!sg_list) {
768 		iod->npages = -1;
769 		return BLK_STS_RESOURCE;
770 	}
771 
772 	nvme_pci_iod_list(req)[0] = sg_list;
773 	iod->first_dma = sgl_dma;
774 
775 	nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
776 
777 	do {
778 		if (i == SGES_PER_PAGE) {
779 			struct nvme_sgl_desc *old_sg_desc = sg_list;
780 			struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
781 
782 			sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
783 			if (!sg_list)
784 				goto free_sgls;
785 
786 			i = 0;
787 			nvme_pci_iod_list(req)[iod->npages++] = sg_list;
788 			sg_list[i++] = *link;
789 			nvme_pci_sgl_set_seg(link, sgl_dma, entries);
790 		}
791 
792 		nvme_pci_sgl_set_data(&sg_list[i++], sg);
793 		sg = sg_next(sg);
794 	} while (--entries > 0);
795 
796 	return BLK_STS_OK;
797 free_sgls:
798 	nvme_free_sgls(dev, req);
799 	return BLK_STS_RESOURCE;
800 }
801 
802 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
803 		struct request *req, struct nvme_rw_command *cmnd,
804 		struct bio_vec *bv)
805 {
806 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
807 	unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
808 	unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
809 
810 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
811 	if (dma_mapping_error(dev->dev, iod->first_dma))
812 		return BLK_STS_RESOURCE;
813 	iod->dma_len = bv->bv_len;
814 
815 	cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
816 	if (bv->bv_len > first_prp_len)
817 		cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
818 	return BLK_STS_OK;
819 }
820 
821 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
822 		struct request *req, struct nvme_rw_command *cmnd,
823 		struct bio_vec *bv)
824 {
825 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
826 
827 	iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
828 	if (dma_mapping_error(dev->dev, iod->first_dma))
829 		return BLK_STS_RESOURCE;
830 	iod->dma_len = bv->bv_len;
831 
832 	cmnd->flags = NVME_CMD_SGL_METABUF;
833 	cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
834 	cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
835 	cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
836 	return BLK_STS_OK;
837 }
838 
839 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
840 		struct nvme_command *cmnd)
841 {
842 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
843 	blk_status_t ret = BLK_STS_RESOURCE;
844 	int nr_mapped;
845 
846 	if (blk_rq_nr_phys_segments(req) == 1) {
847 		struct bio_vec bv = req_bvec(req);
848 
849 		if (!is_pci_p2pdma_page(bv.bv_page)) {
850 			if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
851 				return nvme_setup_prp_simple(dev, req,
852 							     &cmnd->rw, &bv);
853 
854 			if (iod->nvmeq->qid && sgl_threshold &&
855 			    nvme_ctrl_sgl_supported(&dev->ctrl))
856 				return nvme_setup_sgl_simple(dev, req,
857 							     &cmnd->rw, &bv);
858 		}
859 	}
860 
861 	iod->dma_len = 0;
862 	iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
863 	if (!iod->sg)
864 		return BLK_STS_RESOURCE;
865 	sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
866 	iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
867 	if (!iod->nents)
868 		goto out_free_sg;
869 
870 	if (is_pci_p2pdma_page(sg_page(iod->sg)))
871 		nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
872 				iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
873 	else
874 		nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
875 					     rq_dma_dir(req), DMA_ATTR_NO_WARN);
876 	if (!nr_mapped)
877 		goto out_free_sg;
878 
879 	iod->use_sgl = nvme_pci_use_sgls(dev, req);
880 	if (iod->use_sgl)
881 		ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
882 	else
883 		ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
884 	if (ret != BLK_STS_OK)
885 		goto out_unmap_sg;
886 	return BLK_STS_OK;
887 
888 out_unmap_sg:
889 	nvme_unmap_sg(dev, req);
890 out_free_sg:
891 	mempool_free(iod->sg, dev->iod_mempool);
892 	return ret;
893 }
894 
895 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
896 		struct nvme_command *cmnd)
897 {
898 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
899 
900 	iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
901 			rq_dma_dir(req), 0);
902 	if (dma_mapping_error(dev->dev, iod->meta_dma))
903 		return BLK_STS_IOERR;
904 	cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
905 	return BLK_STS_OK;
906 }
907 
908 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
909 {
910 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
911 	blk_status_t ret;
912 
913 	iod->aborted = 0;
914 	iod->npages = -1;
915 	iod->nents = 0;
916 
917 	ret = nvme_setup_cmd(req->q->queuedata, req);
918 	if (ret)
919 		return ret;
920 
921 	if (blk_rq_nr_phys_segments(req)) {
922 		ret = nvme_map_data(dev, req, &iod->cmd);
923 		if (ret)
924 			goto out_free_cmd;
925 	}
926 
927 	if (blk_integrity_rq(req)) {
928 		ret = nvme_map_metadata(dev, req, &iod->cmd);
929 		if (ret)
930 			goto out_unmap_data;
931 	}
932 
933 	blk_mq_start_request(req);
934 	return BLK_STS_OK;
935 out_unmap_data:
936 	nvme_unmap_data(dev, req);
937 out_free_cmd:
938 	nvme_cleanup_cmd(req);
939 	return ret;
940 }
941 
942 /*
943  * NOTE: ns is NULL when called on the admin queue.
944  */
945 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
946 			 const struct blk_mq_queue_data *bd)
947 {
948 	struct nvme_queue *nvmeq = hctx->driver_data;
949 	struct nvme_dev *dev = nvmeq->dev;
950 	struct request *req = bd->rq;
951 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
952 	blk_status_t ret;
953 
954 	/*
955 	 * We should not need to do this, but we're still using this to
956 	 * ensure we can drain requests on a dying queue.
957 	 */
958 	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
959 		return BLK_STS_IOERR;
960 
961 	if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
962 		return nvme_fail_nonready_command(&dev->ctrl, req);
963 
964 	ret = nvme_prep_rq(dev, req);
965 	if (unlikely(ret))
966 		return ret;
967 	spin_lock(&nvmeq->sq_lock);
968 	nvme_sq_copy_cmd(nvmeq, &iod->cmd);
969 	nvme_write_sq_db(nvmeq, bd->last);
970 	spin_unlock(&nvmeq->sq_lock);
971 	return BLK_STS_OK;
972 }
973 
974 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
975 {
976 	spin_lock(&nvmeq->sq_lock);
977 	while (!rq_list_empty(*rqlist)) {
978 		struct request *req = rq_list_pop(rqlist);
979 		struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
980 
981 		nvme_sq_copy_cmd(nvmeq, &iod->cmd);
982 	}
983 	nvme_write_sq_db(nvmeq, true);
984 	spin_unlock(&nvmeq->sq_lock);
985 }
986 
987 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
988 {
989 	/*
990 	 * We should not need to do this, but we're still using this to
991 	 * ensure we can drain requests on a dying queue.
992 	 */
993 	if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
994 		return false;
995 	if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
996 		return false;
997 
998 	req->mq_hctx->tags->rqs[req->tag] = req;
999 	return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
1000 }
1001 
1002 static void nvme_queue_rqs(struct request **rqlist)
1003 {
1004 	struct request *req, *next, *prev = NULL;
1005 	struct request *requeue_list = NULL;
1006 
1007 	rq_list_for_each_safe(rqlist, req, next) {
1008 		struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1009 
1010 		if (!nvme_prep_rq_batch(nvmeq, req)) {
1011 			/* detach 'req' and add to remainder list */
1012 			rq_list_move(rqlist, &requeue_list, req, prev);
1013 
1014 			req = prev;
1015 			if (!req)
1016 				continue;
1017 		}
1018 
1019 		if (!next || req->mq_hctx != next->mq_hctx) {
1020 			/* detach rest of list, and submit */
1021 			req->rq_next = NULL;
1022 			nvme_submit_cmds(nvmeq, rqlist);
1023 			*rqlist = next;
1024 			prev = NULL;
1025 		} else
1026 			prev = req;
1027 	}
1028 
1029 	*rqlist = requeue_list;
1030 }
1031 
1032 static __always_inline void nvme_pci_unmap_rq(struct request *req)
1033 {
1034 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1035 	struct nvme_dev *dev = iod->nvmeq->dev;
1036 
1037 	if (blk_integrity_rq(req))
1038 		dma_unmap_page(dev->dev, iod->meta_dma,
1039 			       rq_integrity_vec(req)->bv_len, rq_data_dir(req));
1040 	if (blk_rq_nr_phys_segments(req))
1041 		nvme_unmap_data(dev, req);
1042 }
1043 
1044 static void nvme_pci_complete_rq(struct request *req)
1045 {
1046 	nvme_pci_unmap_rq(req);
1047 	nvme_complete_rq(req);
1048 }
1049 
1050 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
1051 {
1052 	nvme_complete_batch(iob, nvme_pci_unmap_rq);
1053 }
1054 
1055 /* We read the CQE phase first to check if the rest of the entry is valid */
1056 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
1057 {
1058 	struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
1059 
1060 	return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
1061 }
1062 
1063 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
1064 {
1065 	u16 head = nvmeq->cq_head;
1066 
1067 	if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1068 					      nvmeq->dbbuf_cq_ei))
1069 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1070 }
1071 
1072 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1073 {
1074 	if (!nvmeq->qid)
1075 		return nvmeq->dev->admin_tagset.tags[0];
1076 	return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1077 }
1078 
1079 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1080 				   struct io_comp_batch *iob, u16 idx)
1081 {
1082 	struct nvme_completion *cqe = &nvmeq->cqes[idx];
1083 	__u16 command_id = READ_ONCE(cqe->command_id);
1084 	struct request *req;
1085 
1086 	/*
1087 	 * AEN requests are special as they don't time out and can
1088 	 * survive any kind of queue freeze and often don't respond to
1089 	 * aborts.  We don't even bother to allocate a struct request
1090 	 * for them but rather special case them here.
1091 	 */
1092 	if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1093 		nvme_complete_async_event(&nvmeq->dev->ctrl,
1094 				cqe->status, &cqe->result);
1095 		return;
1096 	}
1097 
1098 	req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1099 	if (unlikely(!req)) {
1100 		dev_warn(nvmeq->dev->ctrl.device,
1101 			"invalid id %d completed on queue %d\n",
1102 			command_id, le16_to_cpu(cqe->sq_id));
1103 		return;
1104 	}
1105 
1106 	trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1107 	if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1108 	    !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1109 					nvme_pci_complete_batch))
1110 		nvme_pci_complete_rq(req);
1111 }
1112 
1113 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1114 {
1115 	u32 tmp = nvmeq->cq_head + 1;
1116 
1117 	if (tmp == nvmeq->q_depth) {
1118 		nvmeq->cq_head = 0;
1119 		nvmeq->cq_phase ^= 1;
1120 	} else {
1121 		nvmeq->cq_head = tmp;
1122 	}
1123 }
1124 
1125 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1126 			       struct io_comp_batch *iob)
1127 {
1128 	int found = 0;
1129 
1130 	while (nvme_cqe_pending(nvmeq)) {
1131 		found++;
1132 		/*
1133 		 * load-load control dependency between phase and the rest of
1134 		 * the cqe requires a full read memory barrier
1135 		 */
1136 		dma_rmb();
1137 		nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1138 		nvme_update_cq_head(nvmeq);
1139 	}
1140 
1141 	if (found)
1142 		nvme_ring_cq_doorbell(nvmeq);
1143 	return found;
1144 }
1145 
1146 static irqreturn_t nvme_irq(int irq, void *data)
1147 {
1148 	struct nvme_queue *nvmeq = data;
1149 	DEFINE_IO_COMP_BATCH(iob);
1150 
1151 	if (nvme_poll_cq(nvmeq, &iob)) {
1152 		if (!rq_list_empty(iob.req_list))
1153 			nvme_pci_complete_batch(&iob);
1154 		return IRQ_HANDLED;
1155 	}
1156 	return IRQ_NONE;
1157 }
1158 
1159 static irqreturn_t nvme_irq_check(int irq, void *data)
1160 {
1161 	struct nvme_queue *nvmeq = data;
1162 
1163 	if (nvme_cqe_pending(nvmeq))
1164 		return IRQ_WAKE_THREAD;
1165 	return IRQ_NONE;
1166 }
1167 
1168 /*
1169  * Poll for completions for any interrupt driven queue
1170  * Can be called from any context.
1171  */
1172 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1173 {
1174 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1175 
1176 	WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1177 
1178 	disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1179 	nvme_poll_cq(nvmeq, NULL);
1180 	enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1181 }
1182 
1183 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1184 {
1185 	struct nvme_queue *nvmeq = hctx->driver_data;
1186 	bool found;
1187 
1188 	if (!nvme_cqe_pending(nvmeq))
1189 		return 0;
1190 
1191 	spin_lock(&nvmeq->cq_poll_lock);
1192 	found = nvme_poll_cq(nvmeq, iob);
1193 	spin_unlock(&nvmeq->cq_poll_lock);
1194 
1195 	return found;
1196 }
1197 
1198 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1199 {
1200 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1201 	struct nvme_queue *nvmeq = &dev->queues[0];
1202 	struct nvme_command c = { };
1203 
1204 	c.common.opcode = nvme_admin_async_event;
1205 	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1206 
1207 	spin_lock(&nvmeq->sq_lock);
1208 	nvme_sq_copy_cmd(nvmeq, &c);
1209 	nvme_write_sq_db(nvmeq, true);
1210 	spin_unlock(&nvmeq->sq_lock);
1211 }
1212 
1213 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1214 {
1215 	struct nvme_command c = { };
1216 
1217 	c.delete_queue.opcode = opcode;
1218 	c.delete_queue.qid = cpu_to_le16(id);
1219 
1220 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1221 }
1222 
1223 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1224 		struct nvme_queue *nvmeq, s16 vector)
1225 {
1226 	struct nvme_command c = { };
1227 	int flags = NVME_QUEUE_PHYS_CONTIG;
1228 
1229 	if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1230 		flags |= NVME_CQ_IRQ_ENABLED;
1231 
1232 	/*
1233 	 * Note: we (ab)use the fact that the prp fields survive if no data
1234 	 * is attached to the request.
1235 	 */
1236 	c.create_cq.opcode = nvme_admin_create_cq;
1237 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1238 	c.create_cq.cqid = cpu_to_le16(qid);
1239 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1240 	c.create_cq.cq_flags = cpu_to_le16(flags);
1241 	c.create_cq.irq_vector = cpu_to_le16(vector);
1242 
1243 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1244 }
1245 
1246 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1247 						struct nvme_queue *nvmeq)
1248 {
1249 	struct nvme_ctrl *ctrl = &dev->ctrl;
1250 	struct nvme_command c = { };
1251 	int flags = NVME_QUEUE_PHYS_CONTIG;
1252 
1253 	/*
1254 	 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1255 	 * set. Since URGENT priority is zeroes, it makes all queues
1256 	 * URGENT.
1257 	 */
1258 	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1259 		flags |= NVME_SQ_PRIO_MEDIUM;
1260 
1261 	/*
1262 	 * Note: we (ab)use the fact that the prp fields survive if no data
1263 	 * is attached to the request.
1264 	 */
1265 	c.create_sq.opcode = nvme_admin_create_sq;
1266 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1267 	c.create_sq.sqid = cpu_to_le16(qid);
1268 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1269 	c.create_sq.sq_flags = cpu_to_le16(flags);
1270 	c.create_sq.cqid = cpu_to_le16(qid);
1271 
1272 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1273 }
1274 
1275 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1276 {
1277 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1278 }
1279 
1280 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1281 {
1282 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1283 }
1284 
1285 static void abort_endio(struct request *req, blk_status_t error)
1286 {
1287 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1288 	struct nvme_queue *nvmeq = iod->nvmeq;
1289 
1290 	dev_warn(nvmeq->dev->ctrl.device,
1291 		 "Abort status: 0x%x", nvme_req(req)->status);
1292 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1293 	blk_mq_free_request(req);
1294 }
1295 
1296 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1297 {
1298 	/* If true, indicates loss of adapter communication, possibly by a
1299 	 * NVMe Subsystem reset.
1300 	 */
1301 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1302 
1303 	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1304 	switch (dev->ctrl.state) {
1305 	case NVME_CTRL_RESETTING:
1306 	case NVME_CTRL_CONNECTING:
1307 		return false;
1308 	default:
1309 		break;
1310 	}
1311 
1312 	/* We shouldn't reset unless the controller is on fatal error state
1313 	 * _or_ if we lost the communication with it.
1314 	 */
1315 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1316 		return false;
1317 
1318 	return true;
1319 }
1320 
1321 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1322 {
1323 	/* Read a config register to help see what died. */
1324 	u16 pci_status;
1325 	int result;
1326 
1327 	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1328 				      &pci_status);
1329 	if (result == PCIBIOS_SUCCESSFUL)
1330 		dev_warn(dev->ctrl.device,
1331 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1332 			 csts, pci_status);
1333 	else
1334 		dev_warn(dev->ctrl.device,
1335 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1336 			 csts, result);
1337 }
1338 
1339 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1340 {
1341 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1342 	struct nvme_queue *nvmeq = iod->nvmeq;
1343 	struct nvme_dev *dev = nvmeq->dev;
1344 	struct request *abort_req;
1345 	struct nvme_command cmd = { };
1346 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1347 
1348 	/* If PCI error recovery process is happening, we cannot reset or
1349 	 * the recovery mechanism will surely fail.
1350 	 */
1351 	mb();
1352 	if (pci_channel_offline(to_pci_dev(dev->dev)))
1353 		return BLK_EH_RESET_TIMER;
1354 
1355 	/*
1356 	 * Reset immediately if the controller is failed
1357 	 */
1358 	if (nvme_should_reset(dev, csts)) {
1359 		nvme_warn_reset(dev, csts);
1360 		nvme_dev_disable(dev, false);
1361 		nvme_reset_ctrl(&dev->ctrl);
1362 		return BLK_EH_DONE;
1363 	}
1364 
1365 	/*
1366 	 * Did we miss an interrupt?
1367 	 */
1368 	if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1369 		nvme_poll(req->mq_hctx, NULL);
1370 	else
1371 		nvme_poll_irqdisable(nvmeq);
1372 
1373 	if (blk_mq_request_completed(req)) {
1374 		dev_warn(dev->ctrl.device,
1375 			 "I/O %d QID %d timeout, completion polled\n",
1376 			 req->tag, nvmeq->qid);
1377 		return BLK_EH_DONE;
1378 	}
1379 
1380 	/*
1381 	 * Shutdown immediately if controller times out while starting. The
1382 	 * reset work will see the pci device disabled when it gets the forced
1383 	 * cancellation error. All outstanding requests are completed on
1384 	 * shutdown, so we return BLK_EH_DONE.
1385 	 */
1386 	switch (dev->ctrl.state) {
1387 	case NVME_CTRL_CONNECTING:
1388 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1389 		fallthrough;
1390 	case NVME_CTRL_DELETING:
1391 		dev_warn_ratelimited(dev->ctrl.device,
1392 			 "I/O %d QID %d timeout, disable controller\n",
1393 			 req->tag, nvmeq->qid);
1394 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1395 		nvme_dev_disable(dev, true);
1396 		return BLK_EH_DONE;
1397 	case NVME_CTRL_RESETTING:
1398 		return BLK_EH_RESET_TIMER;
1399 	default:
1400 		break;
1401 	}
1402 
1403 	/*
1404 	 * Shutdown the controller immediately and schedule a reset if the
1405 	 * command was already aborted once before and still hasn't been
1406 	 * returned to the driver, or if this is the admin queue.
1407 	 */
1408 	if (!nvmeq->qid || iod->aborted) {
1409 		dev_warn(dev->ctrl.device,
1410 			 "I/O %d QID %d timeout, reset controller\n",
1411 			 req->tag, nvmeq->qid);
1412 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1413 		nvme_dev_disable(dev, false);
1414 		nvme_reset_ctrl(&dev->ctrl);
1415 
1416 		return BLK_EH_DONE;
1417 	}
1418 
1419 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1420 		atomic_inc(&dev->ctrl.abort_limit);
1421 		return BLK_EH_RESET_TIMER;
1422 	}
1423 	iod->aborted = 1;
1424 
1425 	cmd.abort.opcode = nvme_admin_abort_cmd;
1426 	cmd.abort.cid = nvme_cid(req);
1427 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1428 
1429 	dev_warn(nvmeq->dev->ctrl.device,
1430 		"I/O %d QID %d timeout, aborting\n",
1431 		 req->tag, nvmeq->qid);
1432 
1433 	abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1434 					 BLK_MQ_REQ_NOWAIT);
1435 	if (IS_ERR(abort_req)) {
1436 		atomic_inc(&dev->ctrl.abort_limit);
1437 		return BLK_EH_RESET_TIMER;
1438 	}
1439 	nvme_init_request(abort_req, &cmd);
1440 
1441 	abort_req->end_io_data = NULL;
1442 	abort_req->rq_flags |= RQF_QUIET;
1443 	blk_execute_rq_nowait(abort_req, false, abort_endio);
1444 
1445 	/*
1446 	 * The aborted req will be completed on receiving the abort req.
1447 	 * We enable the timer again. If hit twice, it'll cause a device reset,
1448 	 * as the device then is in a faulty state.
1449 	 */
1450 	return BLK_EH_RESET_TIMER;
1451 }
1452 
1453 static void nvme_free_queue(struct nvme_queue *nvmeq)
1454 {
1455 	dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1456 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1457 	if (!nvmeq->sq_cmds)
1458 		return;
1459 
1460 	if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1461 		pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1462 				nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1463 	} else {
1464 		dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1465 				nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1466 	}
1467 }
1468 
1469 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1470 {
1471 	int i;
1472 
1473 	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1474 		dev->ctrl.queue_count--;
1475 		nvme_free_queue(&dev->queues[i]);
1476 	}
1477 }
1478 
1479 /**
1480  * nvme_suspend_queue - put queue into suspended state
1481  * @nvmeq: queue to suspend
1482  */
1483 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1484 {
1485 	if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1486 		return 1;
1487 
1488 	/* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1489 	mb();
1490 
1491 	nvmeq->dev->online_queues--;
1492 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1493 		nvme_stop_admin_queue(&nvmeq->dev->ctrl);
1494 	if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1495 		pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1496 	return 0;
1497 }
1498 
1499 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1500 {
1501 	int i;
1502 
1503 	for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1504 		nvme_suspend_queue(&dev->queues[i]);
1505 }
1506 
1507 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1508 {
1509 	struct nvme_queue *nvmeq = &dev->queues[0];
1510 
1511 	if (shutdown)
1512 		nvme_shutdown_ctrl(&dev->ctrl);
1513 	else
1514 		nvme_disable_ctrl(&dev->ctrl);
1515 
1516 	nvme_poll_irqdisable(nvmeq);
1517 }
1518 
1519 /*
1520  * Called only on a device that has been disabled and after all other threads
1521  * that can check this device's completion queues have synced, except
1522  * nvme_poll(). This is the last chance for the driver to see a natural
1523  * completion before nvme_cancel_request() terminates all incomplete requests.
1524  */
1525 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1526 {
1527 	int i;
1528 
1529 	for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1530 		spin_lock(&dev->queues[i].cq_poll_lock);
1531 		nvme_poll_cq(&dev->queues[i], NULL);
1532 		spin_unlock(&dev->queues[i].cq_poll_lock);
1533 	}
1534 }
1535 
1536 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1537 				int entry_size)
1538 {
1539 	int q_depth = dev->q_depth;
1540 	unsigned q_size_aligned = roundup(q_depth * entry_size,
1541 					  NVME_CTRL_PAGE_SIZE);
1542 
1543 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1544 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1545 
1546 		mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1547 		q_depth = div_u64(mem_per_q, entry_size);
1548 
1549 		/*
1550 		 * Ensure the reduced q_depth is above some threshold where it
1551 		 * would be better to map queues in system memory with the
1552 		 * original depth
1553 		 */
1554 		if (q_depth < 64)
1555 			return -ENOMEM;
1556 	}
1557 
1558 	return q_depth;
1559 }
1560 
1561 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1562 				int qid)
1563 {
1564 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1565 
1566 	if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1567 		nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1568 		if (nvmeq->sq_cmds) {
1569 			nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1570 							nvmeq->sq_cmds);
1571 			if (nvmeq->sq_dma_addr) {
1572 				set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1573 				return 0;
1574 			}
1575 
1576 			pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1577 		}
1578 	}
1579 
1580 	nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1581 				&nvmeq->sq_dma_addr, GFP_KERNEL);
1582 	if (!nvmeq->sq_cmds)
1583 		return -ENOMEM;
1584 	return 0;
1585 }
1586 
1587 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1588 {
1589 	struct nvme_queue *nvmeq = &dev->queues[qid];
1590 
1591 	if (dev->ctrl.queue_count > qid)
1592 		return 0;
1593 
1594 	nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1595 	nvmeq->q_depth = depth;
1596 	nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1597 					 &nvmeq->cq_dma_addr, GFP_KERNEL);
1598 	if (!nvmeq->cqes)
1599 		goto free_nvmeq;
1600 
1601 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1602 		goto free_cqdma;
1603 
1604 	nvmeq->dev = dev;
1605 	spin_lock_init(&nvmeq->sq_lock);
1606 	spin_lock_init(&nvmeq->cq_poll_lock);
1607 	nvmeq->cq_head = 0;
1608 	nvmeq->cq_phase = 1;
1609 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1610 	nvmeq->qid = qid;
1611 	dev->ctrl.queue_count++;
1612 
1613 	return 0;
1614 
1615  free_cqdma:
1616 	dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1617 			  nvmeq->cq_dma_addr);
1618  free_nvmeq:
1619 	return -ENOMEM;
1620 }
1621 
1622 static int queue_request_irq(struct nvme_queue *nvmeq)
1623 {
1624 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1625 	int nr = nvmeq->dev->ctrl.instance;
1626 
1627 	if (use_threaded_interrupts) {
1628 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1629 				nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1630 	} else {
1631 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1632 				NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1633 	}
1634 }
1635 
1636 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1637 {
1638 	struct nvme_dev *dev = nvmeq->dev;
1639 
1640 	nvmeq->sq_tail = 0;
1641 	nvmeq->last_sq_tail = 0;
1642 	nvmeq->cq_head = 0;
1643 	nvmeq->cq_phase = 1;
1644 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1645 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1646 	nvme_dbbuf_init(dev, nvmeq, qid);
1647 	dev->online_queues++;
1648 	wmb(); /* ensure the first interrupt sees the initialization */
1649 }
1650 
1651 /*
1652  * Try getting shutdown_lock while setting up IO queues.
1653  */
1654 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1655 {
1656 	/*
1657 	 * Give up if the lock is being held by nvme_dev_disable.
1658 	 */
1659 	if (!mutex_trylock(&dev->shutdown_lock))
1660 		return -ENODEV;
1661 
1662 	/*
1663 	 * Controller is in wrong state, fail early.
1664 	 */
1665 	if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1666 		mutex_unlock(&dev->shutdown_lock);
1667 		return -ENODEV;
1668 	}
1669 
1670 	return 0;
1671 }
1672 
1673 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1674 {
1675 	struct nvme_dev *dev = nvmeq->dev;
1676 	int result;
1677 	u16 vector = 0;
1678 
1679 	clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1680 
1681 	/*
1682 	 * A queue's vector matches the queue identifier unless the controller
1683 	 * has only one vector available.
1684 	 */
1685 	if (!polled)
1686 		vector = dev->num_vecs == 1 ? 0 : qid;
1687 	else
1688 		set_bit(NVMEQ_POLLED, &nvmeq->flags);
1689 
1690 	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1691 	if (result)
1692 		return result;
1693 
1694 	result = adapter_alloc_sq(dev, qid, nvmeq);
1695 	if (result < 0)
1696 		return result;
1697 	if (result)
1698 		goto release_cq;
1699 
1700 	nvmeq->cq_vector = vector;
1701 
1702 	result = nvme_setup_io_queues_trylock(dev);
1703 	if (result)
1704 		return result;
1705 	nvme_init_queue(nvmeq, qid);
1706 	if (!polled) {
1707 		result = queue_request_irq(nvmeq);
1708 		if (result < 0)
1709 			goto release_sq;
1710 	}
1711 
1712 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1713 	mutex_unlock(&dev->shutdown_lock);
1714 	return result;
1715 
1716 release_sq:
1717 	dev->online_queues--;
1718 	mutex_unlock(&dev->shutdown_lock);
1719 	adapter_delete_sq(dev, qid);
1720 release_cq:
1721 	adapter_delete_cq(dev, qid);
1722 	return result;
1723 }
1724 
1725 static const struct blk_mq_ops nvme_mq_admin_ops = {
1726 	.queue_rq	= nvme_queue_rq,
1727 	.complete	= nvme_pci_complete_rq,
1728 	.init_hctx	= nvme_admin_init_hctx,
1729 	.init_request	= nvme_pci_init_request,
1730 	.timeout	= nvme_timeout,
1731 };
1732 
1733 static const struct blk_mq_ops nvme_mq_ops = {
1734 	.queue_rq	= nvme_queue_rq,
1735 	.queue_rqs	= nvme_queue_rqs,
1736 	.complete	= nvme_pci_complete_rq,
1737 	.commit_rqs	= nvme_commit_rqs,
1738 	.init_hctx	= nvme_init_hctx,
1739 	.init_request	= nvme_pci_init_request,
1740 	.map_queues	= nvme_pci_map_queues,
1741 	.timeout	= nvme_timeout,
1742 	.poll		= nvme_poll,
1743 };
1744 
1745 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1746 {
1747 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1748 		/*
1749 		 * If the controller was reset during removal, it's possible
1750 		 * user requests may be waiting on a stopped queue. Start the
1751 		 * queue to flush these to completion.
1752 		 */
1753 		nvme_start_admin_queue(&dev->ctrl);
1754 		blk_cleanup_queue(dev->ctrl.admin_q);
1755 		blk_mq_free_tag_set(&dev->admin_tagset);
1756 	}
1757 }
1758 
1759 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1760 {
1761 	if (!dev->ctrl.admin_q) {
1762 		dev->admin_tagset.ops = &nvme_mq_admin_ops;
1763 		dev->admin_tagset.nr_hw_queues = 1;
1764 
1765 		dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1766 		dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1767 		dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1768 		dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1769 		dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1770 		dev->admin_tagset.driver_data = dev;
1771 
1772 		if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1773 			return -ENOMEM;
1774 		dev->ctrl.admin_tagset = &dev->admin_tagset;
1775 
1776 		dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1777 		if (IS_ERR(dev->ctrl.admin_q)) {
1778 			blk_mq_free_tag_set(&dev->admin_tagset);
1779 			dev->ctrl.admin_q = NULL;
1780 			return -ENOMEM;
1781 		}
1782 		if (!blk_get_queue(dev->ctrl.admin_q)) {
1783 			nvme_dev_remove_admin(dev);
1784 			dev->ctrl.admin_q = NULL;
1785 			return -ENODEV;
1786 		}
1787 	} else
1788 		nvme_start_admin_queue(&dev->ctrl);
1789 
1790 	return 0;
1791 }
1792 
1793 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1794 {
1795 	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1796 }
1797 
1798 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1799 {
1800 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1801 
1802 	if (size <= dev->bar_mapped_size)
1803 		return 0;
1804 	if (size > pci_resource_len(pdev, 0))
1805 		return -ENOMEM;
1806 	if (dev->bar)
1807 		iounmap(dev->bar);
1808 	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1809 	if (!dev->bar) {
1810 		dev->bar_mapped_size = 0;
1811 		return -ENOMEM;
1812 	}
1813 	dev->bar_mapped_size = size;
1814 	dev->dbs = dev->bar + NVME_REG_DBS;
1815 
1816 	return 0;
1817 }
1818 
1819 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1820 {
1821 	int result;
1822 	u32 aqa;
1823 	struct nvme_queue *nvmeq;
1824 
1825 	result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1826 	if (result < 0)
1827 		return result;
1828 
1829 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1830 				NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1831 
1832 	if (dev->subsystem &&
1833 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1834 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1835 
1836 	result = nvme_disable_ctrl(&dev->ctrl);
1837 	if (result < 0)
1838 		return result;
1839 
1840 	result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1841 	if (result)
1842 		return result;
1843 
1844 	dev->ctrl.numa_node = dev_to_node(dev->dev);
1845 
1846 	nvmeq = &dev->queues[0];
1847 	aqa = nvmeq->q_depth - 1;
1848 	aqa |= aqa << 16;
1849 
1850 	writel(aqa, dev->bar + NVME_REG_AQA);
1851 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1852 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1853 
1854 	result = nvme_enable_ctrl(&dev->ctrl);
1855 	if (result)
1856 		return result;
1857 
1858 	nvmeq->cq_vector = 0;
1859 	nvme_init_queue(nvmeq, 0);
1860 	result = queue_request_irq(nvmeq);
1861 	if (result) {
1862 		dev->online_queues--;
1863 		return result;
1864 	}
1865 
1866 	set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1867 	return result;
1868 }
1869 
1870 static int nvme_create_io_queues(struct nvme_dev *dev)
1871 {
1872 	unsigned i, max, rw_queues;
1873 	int ret = 0;
1874 
1875 	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1876 		if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1877 			ret = -ENOMEM;
1878 			break;
1879 		}
1880 	}
1881 
1882 	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1883 	if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1884 		rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1885 				dev->io_queues[HCTX_TYPE_READ];
1886 	} else {
1887 		rw_queues = max;
1888 	}
1889 
1890 	for (i = dev->online_queues; i <= max; i++) {
1891 		bool polled = i > rw_queues;
1892 
1893 		ret = nvme_create_queue(&dev->queues[i], i, polled);
1894 		if (ret)
1895 			break;
1896 	}
1897 
1898 	/*
1899 	 * Ignore failing Create SQ/CQ commands, we can continue with less
1900 	 * than the desired amount of queues, and even a controller without
1901 	 * I/O queues can still be used to issue admin commands.  This might
1902 	 * be useful to upgrade a buggy firmware for example.
1903 	 */
1904 	return ret >= 0 ? 0 : ret;
1905 }
1906 
1907 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1908 {
1909 	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1910 
1911 	return 1ULL << (12 + 4 * szu);
1912 }
1913 
1914 static u32 nvme_cmb_size(struct nvme_dev *dev)
1915 {
1916 	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1917 }
1918 
1919 static void nvme_map_cmb(struct nvme_dev *dev)
1920 {
1921 	u64 size, offset;
1922 	resource_size_t bar_size;
1923 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1924 	int bar;
1925 
1926 	if (dev->cmb_size)
1927 		return;
1928 
1929 	if (NVME_CAP_CMBS(dev->ctrl.cap))
1930 		writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1931 
1932 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1933 	if (!dev->cmbsz)
1934 		return;
1935 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1936 
1937 	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1938 	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1939 	bar = NVME_CMB_BIR(dev->cmbloc);
1940 	bar_size = pci_resource_len(pdev, bar);
1941 
1942 	if (offset > bar_size)
1943 		return;
1944 
1945 	/*
1946 	 * Tell the controller about the host side address mapping the CMB,
1947 	 * and enable CMB decoding for the NVMe 1.4+ scheme:
1948 	 */
1949 	if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1950 		hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1951 			     (pci_bus_address(pdev, bar) + offset),
1952 			     dev->bar + NVME_REG_CMBMSC);
1953 	}
1954 
1955 	/*
1956 	 * Controllers may support a CMB size larger than their BAR,
1957 	 * for example, due to being behind a bridge. Reduce the CMB to
1958 	 * the reported size of the BAR
1959 	 */
1960 	if (size > bar_size - offset)
1961 		size = bar_size - offset;
1962 
1963 	if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1964 		dev_warn(dev->ctrl.device,
1965 			 "failed to register the CMB\n");
1966 		return;
1967 	}
1968 
1969 	dev->cmb_size = size;
1970 	dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1971 
1972 	if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1973 			(NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1974 		pci_p2pmem_publish(pdev, true);
1975 }
1976 
1977 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1978 {
1979 	u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1980 	u64 dma_addr = dev->host_mem_descs_dma;
1981 	struct nvme_command c = { };
1982 	int ret;
1983 
1984 	c.features.opcode	= nvme_admin_set_features;
1985 	c.features.fid		= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1986 	c.features.dword11	= cpu_to_le32(bits);
1987 	c.features.dword12	= cpu_to_le32(host_mem_size);
1988 	c.features.dword13	= cpu_to_le32(lower_32_bits(dma_addr));
1989 	c.features.dword14	= cpu_to_le32(upper_32_bits(dma_addr));
1990 	c.features.dword15	= cpu_to_le32(dev->nr_host_mem_descs);
1991 
1992 	ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1993 	if (ret) {
1994 		dev_warn(dev->ctrl.device,
1995 			 "failed to set host mem (err %d, flags %#x).\n",
1996 			 ret, bits);
1997 	} else
1998 		dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1999 
2000 	return ret;
2001 }
2002 
2003 static void nvme_free_host_mem(struct nvme_dev *dev)
2004 {
2005 	int i;
2006 
2007 	for (i = 0; i < dev->nr_host_mem_descs; i++) {
2008 		struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
2009 		size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
2010 
2011 		dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
2012 			       le64_to_cpu(desc->addr),
2013 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2014 	}
2015 
2016 	kfree(dev->host_mem_desc_bufs);
2017 	dev->host_mem_desc_bufs = NULL;
2018 	dma_free_coherent(dev->dev,
2019 			dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
2020 			dev->host_mem_descs, dev->host_mem_descs_dma);
2021 	dev->host_mem_descs = NULL;
2022 	dev->nr_host_mem_descs = 0;
2023 }
2024 
2025 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
2026 		u32 chunk_size)
2027 {
2028 	struct nvme_host_mem_buf_desc *descs;
2029 	u32 max_entries, len;
2030 	dma_addr_t descs_dma;
2031 	int i = 0;
2032 	void **bufs;
2033 	u64 size, tmp;
2034 
2035 	tmp = (preferred + chunk_size - 1);
2036 	do_div(tmp, chunk_size);
2037 	max_entries = tmp;
2038 
2039 	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
2040 		max_entries = dev->ctrl.hmmaxd;
2041 
2042 	descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
2043 				   &descs_dma, GFP_KERNEL);
2044 	if (!descs)
2045 		goto out;
2046 
2047 	bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
2048 	if (!bufs)
2049 		goto out_free_descs;
2050 
2051 	for (size = 0; size < preferred && i < max_entries; size += len) {
2052 		dma_addr_t dma_addr;
2053 
2054 		len = min_t(u64, chunk_size, preferred - size);
2055 		bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
2056 				DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2057 		if (!bufs[i])
2058 			break;
2059 
2060 		descs[i].addr = cpu_to_le64(dma_addr);
2061 		descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
2062 		i++;
2063 	}
2064 
2065 	if (!size)
2066 		goto out_free_bufs;
2067 
2068 	dev->nr_host_mem_descs = i;
2069 	dev->host_mem_size = size;
2070 	dev->host_mem_descs = descs;
2071 	dev->host_mem_descs_dma = descs_dma;
2072 	dev->host_mem_desc_bufs = bufs;
2073 	return 0;
2074 
2075 out_free_bufs:
2076 	while (--i >= 0) {
2077 		size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2078 
2079 		dma_free_attrs(dev->dev, size, bufs[i],
2080 			       le64_to_cpu(descs[i].addr),
2081 			       DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2082 	}
2083 
2084 	kfree(bufs);
2085 out_free_descs:
2086 	dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2087 			descs_dma);
2088 out:
2089 	dev->host_mem_descs = NULL;
2090 	return -ENOMEM;
2091 }
2092 
2093 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2094 {
2095 	u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2096 	u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2097 	u64 chunk_size;
2098 
2099 	/* start big and work our way down */
2100 	for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2101 		if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2102 			if (!min || dev->host_mem_size >= min)
2103 				return 0;
2104 			nvme_free_host_mem(dev);
2105 		}
2106 	}
2107 
2108 	return -ENOMEM;
2109 }
2110 
2111 static int nvme_setup_host_mem(struct nvme_dev *dev)
2112 {
2113 	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2114 	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2115 	u64 min = (u64)dev->ctrl.hmmin * 4096;
2116 	u32 enable_bits = NVME_HOST_MEM_ENABLE;
2117 	int ret;
2118 
2119 	preferred = min(preferred, max);
2120 	if (min > max) {
2121 		dev_warn(dev->ctrl.device,
2122 			"min host memory (%lld MiB) above limit (%d MiB).\n",
2123 			min >> ilog2(SZ_1M), max_host_mem_size_mb);
2124 		nvme_free_host_mem(dev);
2125 		return 0;
2126 	}
2127 
2128 	/*
2129 	 * If we already have a buffer allocated check if we can reuse it.
2130 	 */
2131 	if (dev->host_mem_descs) {
2132 		if (dev->host_mem_size >= min)
2133 			enable_bits |= NVME_HOST_MEM_RETURN;
2134 		else
2135 			nvme_free_host_mem(dev);
2136 	}
2137 
2138 	if (!dev->host_mem_descs) {
2139 		if (nvme_alloc_host_mem(dev, min, preferred)) {
2140 			dev_warn(dev->ctrl.device,
2141 				"failed to allocate host memory buffer.\n");
2142 			return 0; /* controller must work without HMB */
2143 		}
2144 
2145 		dev_info(dev->ctrl.device,
2146 			"allocated %lld MiB host memory buffer.\n",
2147 			dev->host_mem_size >> ilog2(SZ_1M));
2148 	}
2149 
2150 	ret = nvme_set_host_mem(dev, enable_bits);
2151 	if (ret)
2152 		nvme_free_host_mem(dev);
2153 	return ret;
2154 }
2155 
2156 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2157 		char *buf)
2158 {
2159 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2160 
2161 	return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz  : x%08x\n",
2162 		       ndev->cmbloc, ndev->cmbsz);
2163 }
2164 static DEVICE_ATTR_RO(cmb);
2165 
2166 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2167 		char *buf)
2168 {
2169 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2170 
2171 	return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2172 }
2173 static DEVICE_ATTR_RO(cmbloc);
2174 
2175 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2176 		char *buf)
2177 {
2178 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2179 
2180 	return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2181 }
2182 static DEVICE_ATTR_RO(cmbsz);
2183 
2184 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2185 			char *buf)
2186 {
2187 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2188 
2189 	return sysfs_emit(buf, "%d\n", ndev->hmb);
2190 }
2191 
2192 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2193 			 const char *buf, size_t count)
2194 {
2195 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2196 	bool new;
2197 	int ret;
2198 
2199 	if (strtobool(buf, &new) < 0)
2200 		return -EINVAL;
2201 
2202 	if (new == ndev->hmb)
2203 		return count;
2204 
2205 	if (new) {
2206 		ret = nvme_setup_host_mem(ndev);
2207 	} else {
2208 		ret = nvme_set_host_mem(ndev, 0);
2209 		if (!ret)
2210 			nvme_free_host_mem(ndev);
2211 	}
2212 
2213 	if (ret < 0)
2214 		return ret;
2215 
2216 	return count;
2217 }
2218 static DEVICE_ATTR_RW(hmb);
2219 
2220 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2221 		struct attribute *a, int n)
2222 {
2223 	struct nvme_ctrl *ctrl =
2224 		dev_get_drvdata(container_of(kobj, struct device, kobj));
2225 	struct nvme_dev *dev = to_nvme_dev(ctrl);
2226 
2227 	if (a == &dev_attr_cmb.attr ||
2228 	    a == &dev_attr_cmbloc.attr ||
2229 	    a == &dev_attr_cmbsz.attr) {
2230 	    	if (!dev->cmbsz)
2231 			return 0;
2232 	}
2233 	if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2234 		return 0;
2235 
2236 	return a->mode;
2237 }
2238 
2239 static struct attribute *nvme_pci_attrs[] = {
2240 	&dev_attr_cmb.attr,
2241 	&dev_attr_cmbloc.attr,
2242 	&dev_attr_cmbsz.attr,
2243 	&dev_attr_hmb.attr,
2244 	NULL,
2245 };
2246 
2247 static const struct attribute_group nvme_pci_attr_group = {
2248 	.attrs		= nvme_pci_attrs,
2249 	.is_visible	= nvme_pci_attrs_are_visible,
2250 };
2251 
2252 /*
2253  * nirqs is the number of interrupts available for write and read
2254  * queues. The core already reserved an interrupt for the admin queue.
2255  */
2256 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2257 {
2258 	struct nvme_dev *dev = affd->priv;
2259 	unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2260 
2261 	/*
2262 	 * If there is no interrupt available for queues, ensure that
2263 	 * the default queue is set to 1. The affinity set size is
2264 	 * also set to one, but the irq core ignores it for this case.
2265 	 *
2266 	 * If only one interrupt is available or 'write_queue' == 0, combine
2267 	 * write and read queues.
2268 	 *
2269 	 * If 'write_queues' > 0, ensure it leaves room for at least one read
2270 	 * queue.
2271 	 */
2272 	if (!nrirqs) {
2273 		nrirqs = 1;
2274 		nr_read_queues = 0;
2275 	} else if (nrirqs == 1 || !nr_write_queues) {
2276 		nr_read_queues = 0;
2277 	} else if (nr_write_queues >= nrirqs) {
2278 		nr_read_queues = 1;
2279 	} else {
2280 		nr_read_queues = nrirqs - nr_write_queues;
2281 	}
2282 
2283 	dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2284 	affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2285 	dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2286 	affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2287 	affd->nr_sets = nr_read_queues ? 2 : 1;
2288 }
2289 
2290 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2291 {
2292 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2293 	struct irq_affinity affd = {
2294 		.pre_vectors	= 1,
2295 		.calc_sets	= nvme_calc_irq_sets,
2296 		.priv		= dev,
2297 	};
2298 	unsigned int irq_queues, poll_queues;
2299 
2300 	/*
2301 	 * Poll queues don't need interrupts, but we need at least one I/O queue
2302 	 * left over for non-polled I/O.
2303 	 */
2304 	poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2305 	dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2306 
2307 	/*
2308 	 * Initialize for the single interrupt case, will be updated in
2309 	 * nvme_calc_irq_sets().
2310 	 */
2311 	dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2312 	dev->io_queues[HCTX_TYPE_READ] = 0;
2313 
2314 	/*
2315 	 * We need interrupts for the admin queue and each non-polled I/O queue,
2316 	 * but some Apple controllers require all queues to use the first
2317 	 * vector.
2318 	 */
2319 	irq_queues = 1;
2320 	if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2321 		irq_queues += (nr_io_queues - poll_queues);
2322 	return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2323 			      PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2324 }
2325 
2326 static void nvme_disable_io_queues(struct nvme_dev *dev)
2327 {
2328 	if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2329 		__nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2330 }
2331 
2332 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2333 {
2334 	/*
2335 	 * If tags are shared with admin queue (Apple bug), then
2336 	 * make sure we only use one IO queue.
2337 	 */
2338 	if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2339 		return 1;
2340 	return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2341 }
2342 
2343 static int nvme_setup_io_queues(struct nvme_dev *dev)
2344 {
2345 	struct nvme_queue *adminq = &dev->queues[0];
2346 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2347 	unsigned int nr_io_queues;
2348 	unsigned long size;
2349 	int result;
2350 
2351 	/*
2352 	 * Sample the module parameters once at reset time so that we have
2353 	 * stable values to work with.
2354 	 */
2355 	dev->nr_write_queues = write_queues;
2356 	dev->nr_poll_queues = poll_queues;
2357 
2358 	nr_io_queues = dev->nr_allocated_queues - 1;
2359 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2360 	if (result < 0)
2361 		return result;
2362 
2363 	if (nr_io_queues == 0)
2364 		return 0;
2365 
2366 	/*
2367 	 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2368 	 * from set to unset. If there is a window to it is truely freed,
2369 	 * pci_free_irq_vectors() jumping into this window will crash.
2370 	 * And take lock to avoid racing with pci_free_irq_vectors() in
2371 	 * nvme_dev_disable() path.
2372 	 */
2373 	result = nvme_setup_io_queues_trylock(dev);
2374 	if (result)
2375 		return result;
2376 	if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2377 		pci_free_irq(pdev, 0, adminq);
2378 
2379 	if (dev->cmb_use_sqes) {
2380 		result = nvme_cmb_qdepth(dev, nr_io_queues,
2381 				sizeof(struct nvme_command));
2382 		if (result > 0)
2383 			dev->q_depth = result;
2384 		else
2385 			dev->cmb_use_sqes = false;
2386 	}
2387 
2388 	do {
2389 		size = db_bar_size(dev, nr_io_queues);
2390 		result = nvme_remap_bar(dev, size);
2391 		if (!result)
2392 			break;
2393 		if (!--nr_io_queues) {
2394 			result = -ENOMEM;
2395 			goto out_unlock;
2396 		}
2397 	} while (1);
2398 	adminq->q_db = dev->dbs;
2399 
2400  retry:
2401 	/* Deregister the admin queue's interrupt */
2402 	if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2403 		pci_free_irq(pdev, 0, adminq);
2404 
2405 	/*
2406 	 * If we enable msix early due to not intx, disable it again before
2407 	 * setting up the full range we need.
2408 	 */
2409 	pci_free_irq_vectors(pdev);
2410 
2411 	result = nvme_setup_irqs(dev, nr_io_queues);
2412 	if (result <= 0) {
2413 		result = -EIO;
2414 		goto out_unlock;
2415 	}
2416 
2417 	dev->num_vecs = result;
2418 	result = max(result - 1, 1);
2419 	dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2420 
2421 	/*
2422 	 * Should investigate if there's a performance win from allocating
2423 	 * more queues than interrupt vectors; it might allow the submission
2424 	 * path to scale better, even if the receive path is limited by the
2425 	 * number of interrupts.
2426 	 */
2427 	result = queue_request_irq(adminq);
2428 	if (result)
2429 		goto out_unlock;
2430 	set_bit(NVMEQ_ENABLED, &adminq->flags);
2431 	mutex_unlock(&dev->shutdown_lock);
2432 
2433 	result = nvme_create_io_queues(dev);
2434 	if (result || dev->online_queues < 2)
2435 		return result;
2436 
2437 	if (dev->online_queues - 1 < dev->max_qid) {
2438 		nr_io_queues = dev->online_queues - 1;
2439 		nvme_disable_io_queues(dev);
2440 		result = nvme_setup_io_queues_trylock(dev);
2441 		if (result)
2442 			return result;
2443 		nvme_suspend_io_queues(dev);
2444 		goto retry;
2445 	}
2446 	dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2447 					dev->io_queues[HCTX_TYPE_DEFAULT],
2448 					dev->io_queues[HCTX_TYPE_READ],
2449 					dev->io_queues[HCTX_TYPE_POLL]);
2450 	return 0;
2451 out_unlock:
2452 	mutex_unlock(&dev->shutdown_lock);
2453 	return result;
2454 }
2455 
2456 static void nvme_del_queue_end(struct request *req, blk_status_t error)
2457 {
2458 	struct nvme_queue *nvmeq = req->end_io_data;
2459 
2460 	blk_mq_free_request(req);
2461 	complete(&nvmeq->delete_done);
2462 }
2463 
2464 static void nvme_del_cq_end(struct request *req, blk_status_t error)
2465 {
2466 	struct nvme_queue *nvmeq = req->end_io_data;
2467 
2468 	if (error)
2469 		set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2470 
2471 	nvme_del_queue_end(req, error);
2472 }
2473 
2474 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2475 {
2476 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2477 	struct request *req;
2478 	struct nvme_command cmd = { };
2479 
2480 	cmd.delete_queue.opcode = opcode;
2481 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2482 
2483 	req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2484 	if (IS_ERR(req))
2485 		return PTR_ERR(req);
2486 	nvme_init_request(req, &cmd);
2487 
2488 	req->end_io_data = nvmeq;
2489 
2490 	init_completion(&nvmeq->delete_done);
2491 	req->rq_flags |= RQF_QUIET;
2492 	blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ?
2493 			nvme_del_cq_end : nvme_del_queue_end);
2494 	return 0;
2495 }
2496 
2497 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2498 {
2499 	int nr_queues = dev->online_queues - 1, sent = 0;
2500 	unsigned long timeout;
2501 
2502  retry:
2503 	timeout = NVME_ADMIN_TIMEOUT;
2504 	while (nr_queues > 0) {
2505 		if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2506 			break;
2507 		nr_queues--;
2508 		sent++;
2509 	}
2510 	while (sent) {
2511 		struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2512 
2513 		timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2514 				timeout);
2515 		if (timeout == 0)
2516 			return false;
2517 
2518 		sent--;
2519 		if (nr_queues)
2520 			goto retry;
2521 	}
2522 	return true;
2523 }
2524 
2525 static void nvme_dev_add(struct nvme_dev *dev)
2526 {
2527 	int ret;
2528 
2529 	if (!dev->ctrl.tagset) {
2530 		dev->tagset.ops = &nvme_mq_ops;
2531 		dev->tagset.nr_hw_queues = dev->online_queues - 1;
2532 		dev->tagset.nr_maps = 2; /* default + read */
2533 		if (dev->io_queues[HCTX_TYPE_POLL])
2534 			dev->tagset.nr_maps++;
2535 		dev->tagset.timeout = NVME_IO_TIMEOUT;
2536 		dev->tagset.numa_node = dev->ctrl.numa_node;
2537 		dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2538 						BLK_MQ_MAX_DEPTH) - 1;
2539 		dev->tagset.cmd_size = sizeof(struct nvme_iod);
2540 		dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2541 		dev->tagset.driver_data = dev;
2542 
2543 		/*
2544 		 * Some Apple controllers requires tags to be unique
2545 		 * across admin and IO queue, so reserve the first 32
2546 		 * tags of the IO queue.
2547 		 */
2548 		if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2549 			dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2550 
2551 		ret = blk_mq_alloc_tag_set(&dev->tagset);
2552 		if (ret) {
2553 			dev_warn(dev->ctrl.device,
2554 				"IO queues tagset allocation failed %d\n", ret);
2555 			return;
2556 		}
2557 		dev->ctrl.tagset = &dev->tagset;
2558 	} else {
2559 		blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2560 
2561 		/* Free previously allocated queues that are no longer usable */
2562 		nvme_free_queues(dev, dev->online_queues);
2563 	}
2564 
2565 	nvme_dbbuf_set(dev);
2566 }
2567 
2568 static int nvme_pci_enable(struct nvme_dev *dev)
2569 {
2570 	int result = -ENOMEM;
2571 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2572 	int dma_address_bits = 64;
2573 
2574 	if (pci_enable_device_mem(pdev))
2575 		return result;
2576 
2577 	pci_set_master(pdev);
2578 
2579 	if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2580 		dma_address_bits = 48;
2581 	if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2582 		goto disable;
2583 
2584 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2585 		result = -ENODEV;
2586 		goto disable;
2587 	}
2588 
2589 	/*
2590 	 * Some devices and/or platforms don't advertise or work with INTx
2591 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2592 	 * adjust this later.
2593 	 */
2594 	result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2595 	if (result < 0)
2596 		return result;
2597 
2598 	dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2599 
2600 	dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2601 				io_queue_depth);
2602 	dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2603 	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2604 	dev->dbs = dev->bar + 4096;
2605 
2606 	/*
2607 	 * Some Apple controllers require a non-standard SQE size.
2608 	 * Interestingly they also seem to ignore the CC:IOSQES register
2609 	 * so we don't bother updating it here.
2610 	 */
2611 	if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2612 		dev->io_sqes = 7;
2613 	else
2614 		dev->io_sqes = NVME_NVM_IOSQES;
2615 
2616 	/*
2617 	 * Temporary fix for the Apple controller found in the MacBook8,1 and
2618 	 * some MacBook7,1 to avoid controller resets and data loss.
2619 	 */
2620 	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2621 		dev->q_depth = 2;
2622 		dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2623 			"set queue depth=%u to work around controller resets\n",
2624 			dev->q_depth);
2625 	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2626 		   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2627 		   NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2628 		dev->q_depth = 64;
2629 		dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2630                         "set queue depth=%u\n", dev->q_depth);
2631 	}
2632 
2633 	/*
2634 	 * Controllers with the shared tags quirk need the IO queue to be
2635 	 * big enough so that we get 32 tags for the admin queue
2636 	 */
2637 	if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2638 	    (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2639 		dev->q_depth = NVME_AQ_DEPTH + 2;
2640 		dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2641 			 dev->q_depth);
2642 	}
2643 
2644 
2645 	nvme_map_cmb(dev);
2646 
2647 	pci_enable_pcie_error_reporting(pdev);
2648 	pci_save_state(pdev);
2649 	return 0;
2650 
2651  disable:
2652 	pci_disable_device(pdev);
2653 	return result;
2654 }
2655 
2656 static void nvme_dev_unmap(struct nvme_dev *dev)
2657 {
2658 	if (dev->bar)
2659 		iounmap(dev->bar);
2660 	pci_release_mem_regions(to_pci_dev(dev->dev));
2661 }
2662 
2663 static void nvme_pci_disable(struct nvme_dev *dev)
2664 {
2665 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2666 
2667 	pci_free_irq_vectors(pdev);
2668 
2669 	if (pci_is_enabled(pdev)) {
2670 		pci_disable_pcie_error_reporting(pdev);
2671 		pci_disable_device(pdev);
2672 	}
2673 }
2674 
2675 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2676 {
2677 	bool dead = true, freeze = false;
2678 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2679 
2680 	mutex_lock(&dev->shutdown_lock);
2681 	if (pci_device_is_present(pdev) && pci_is_enabled(pdev)) {
2682 		u32 csts = readl(dev->bar + NVME_REG_CSTS);
2683 
2684 		if (dev->ctrl.state == NVME_CTRL_LIVE ||
2685 		    dev->ctrl.state == NVME_CTRL_RESETTING) {
2686 			freeze = true;
2687 			nvme_start_freeze(&dev->ctrl);
2688 		}
2689 		dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2690 			pdev->error_state  != pci_channel_io_normal);
2691 	}
2692 
2693 	/*
2694 	 * Give the controller a chance to complete all entered requests if
2695 	 * doing a safe shutdown.
2696 	 */
2697 	if (!dead && shutdown && freeze)
2698 		nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2699 
2700 	nvme_stop_queues(&dev->ctrl);
2701 
2702 	if (!dead && dev->ctrl.queue_count > 0) {
2703 		nvme_disable_io_queues(dev);
2704 		nvme_disable_admin_queue(dev, shutdown);
2705 	}
2706 	nvme_suspend_io_queues(dev);
2707 	nvme_suspend_queue(&dev->queues[0]);
2708 	nvme_pci_disable(dev);
2709 	nvme_reap_pending_cqes(dev);
2710 
2711 	blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2712 	blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2713 	blk_mq_tagset_wait_completed_request(&dev->tagset);
2714 	blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2715 
2716 	/*
2717 	 * The driver will not be starting up queues again if shutting down so
2718 	 * must flush all entered requests to their failed completion to avoid
2719 	 * deadlocking blk-mq hot-cpu notifier.
2720 	 */
2721 	if (shutdown) {
2722 		nvme_start_queues(&dev->ctrl);
2723 		if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2724 			nvme_start_admin_queue(&dev->ctrl);
2725 	}
2726 	mutex_unlock(&dev->shutdown_lock);
2727 }
2728 
2729 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2730 {
2731 	if (!nvme_wait_reset(&dev->ctrl))
2732 		return -EBUSY;
2733 	nvme_dev_disable(dev, shutdown);
2734 	return 0;
2735 }
2736 
2737 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2738 {
2739 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2740 						NVME_CTRL_PAGE_SIZE,
2741 						NVME_CTRL_PAGE_SIZE, 0);
2742 	if (!dev->prp_page_pool)
2743 		return -ENOMEM;
2744 
2745 	/* Optimisation for I/Os between 4k and 128k */
2746 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2747 						256, 256, 0);
2748 	if (!dev->prp_small_pool) {
2749 		dma_pool_destroy(dev->prp_page_pool);
2750 		return -ENOMEM;
2751 	}
2752 	return 0;
2753 }
2754 
2755 static void nvme_release_prp_pools(struct nvme_dev *dev)
2756 {
2757 	dma_pool_destroy(dev->prp_page_pool);
2758 	dma_pool_destroy(dev->prp_small_pool);
2759 }
2760 
2761 static void nvme_free_tagset(struct nvme_dev *dev)
2762 {
2763 	if (dev->tagset.tags)
2764 		blk_mq_free_tag_set(&dev->tagset);
2765 	dev->ctrl.tagset = NULL;
2766 }
2767 
2768 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2769 {
2770 	struct nvme_dev *dev = to_nvme_dev(ctrl);
2771 
2772 	nvme_dbbuf_dma_free(dev);
2773 	nvme_free_tagset(dev);
2774 	if (dev->ctrl.admin_q)
2775 		blk_put_queue(dev->ctrl.admin_q);
2776 	free_opal_dev(dev->ctrl.opal_dev);
2777 	mempool_destroy(dev->iod_mempool);
2778 	put_device(dev->dev);
2779 	kfree(dev->queues);
2780 	kfree(dev);
2781 }
2782 
2783 static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2784 {
2785 	/*
2786 	 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2787 	 * may be holding this pci_dev's device lock.
2788 	 */
2789 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2790 	nvme_get_ctrl(&dev->ctrl);
2791 	nvme_dev_disable(dev, false);
2792 	nvme_kill_queues(&dev->ctrl);
2793 	if (!queue_work(nvme_wq, &dev->remove_work))
2794 		nvme_put_ctrl(&dev->ctrl);
2795 }
2796 
2797 static void nvme_reset_work(struct work_struct *work)
2798 {
2799 	struct nvme_dev *dev =
2800 		container_of(work, struct nvme_dev, ctrl.reset_work);
2801 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2802 	int result;
2803 
2804 	if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2805 		dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2806 			 dev->ctrl.state);
2807 		result = -ENODEV;
2808 		goto out;
2809 	}
2810 
2811 	/*
2812 	 * If we're called to reset a live controller first shut it down before
2813 	 * moving on.
2814 	 */
2815 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2816 		nvme_dev_disable(dev, false);
2817 	nvme_sync_queues(&dev->ctrl);
2818 
2819 	mutex_lock(&dev->shutdown_lock);
2820 	result = nvme_pci_enable(dev);
2821 	if (result)
2822 		goto out_unlock;
2823 
2824 	result = nvme_pci_configure_admin_queue(dev);
2825 	if (result)
2826 		goto out_unlock;
2827 
2828 	result = nvme_alloc_admin_tags(dev);
2829 	if (result)
2830 		goto out_unlock;
2831 
2832 	/*
2833 	 * Limit the max command size to prevent iod->sg allocations going
2834 	 * over a single page.
2835 	 */
2836 	dev->ctrl.max_hw_sectors = min_t(u32,
2837 		NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2838 	dev->ctrl.max_segments = NVME_MAX_SEGS;
2839 
2840 	/*
2841 	 * Don't limit the IOMMU merged segment size.
2842 	 */
2843 	dma_set_max_seg_size(dev->dev, 0xffffffff);
2844 	dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2845 
2846 	mutex_unlock(&dev->shutdown_lock);
2847 
2848 	/*
2849 	 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2850 	 * initializing procedure here.
2851 	 */
2852 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2853 		dev_warn(dev->ctrl.device,
2854 			"failed to mark controller CONNECTING\n");
2855 		result = -EBUSY;
2856 		goto out;
2857 	}
2858 
2859 	/*
2860 	 * We do not support an SGL for metadata (yet), so we are limited to a
2861 	 * single integrity segment for the separate metadata pointer.
2862 	 */
2863 	dev->ctrl.max_integrity_segments = 1;
2864 
2865 	result = nvme_init_ctrl_finish(&dev->ctrl);
2866 	if (result)
2867 		goto out;
2868 
2869 	if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2870 		if (!dev->ctrl.opal_dev)
2871 			dev->ctrl.opal_dev =
2872 				init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2873 		else if (was_suspend)
2874 			opal_unlock_from_suspend(dev->ctrl.opal_dev);
2875 	} else {
2876 		free_opal_dev(dev->ctrl.opal_dev);
2877 		dev->ctrl.opal_dev = NULL;
2878 	}
2879 
2880 	if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2881 		result = nvme_dbbuf_dma_alloc(dev);
2882 		if (result)
2883 			dev_warn(dev->dev,
2884 				 "unable to allocate dma for dbbuf\n");
2885 	}
2886 
2887 	if (dev->ctrl.hmpre) {
2888 		result = nvme_setup_host_mem(dev);
2889 		if (result < 0)
2890 			goto out;
2891 	}
2892 
2893 	result = nvme_setup_io_queues(dev);
2894 	if (result)
2895 		goto out;
2896 
2897 	/*
2898 	 * Keep the controller around but remove all namespaces if we don't have
2899 	 * any working I/O queue.
2900 	 */
2901 	if (dev->online_queues < 2) {
2902 		dev_warn(dev->ctrl.device, "IO queues not created\n");
2903 		nvme_kill_queues(&dev->ctrl);
2904 		nvme_remove_namespaces(&dev->ctrl);
2905 		nvme_free_tagset(dev);
2906 	} else {
2907 		nvme_start_queues(&dev->ctrl);
2908 		nvme_wait_freeze(&dev->ctrl);
2909 		nvme_dev_add(dev);
2910 		nvme_unfreeze(&dev->ctrl);
2911 	}
2912 
2913 	/*
2914 	 * If only admin queue live, keep it to do further investigation or
2915 	 * recovery.
2916 	 */
2917 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2918 		dev_warn(dev->ctrl.device,
2919 			"failed to mark controller live state\n");
2920 		result = -ENODEV;
2921 		goto out;
2922 	}
2923 
2924 	if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj,
2925 			&nvme_pci_attr_group))
2926 		dev->attrs_added = true;
2927 
2928 	nvme_start_ctrl(&dev->ctrl);
2929 	return;
2930 
2931  out_unlock:
2932 	mutex_unlock(&dev->shutdown_lock);
2933  out:
2934 	if (result)
2935 		dev_warn(dev->ctrl.device,
2936 			 "Removing after probe failure status: %d\n", result);
2937 	nvme_remove_dead_ctrl(dev);
2938 }
2939 
2940 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2941 {
2942 	struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2943 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2944 
2945 	if (pci_get_drvdata(pdev))
2946 		device_release_driver(&pdev->dev);
2947 	nvme_put_ctrl(&dev->ctrl);
2948 }
2949 
2950 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2951 {
2952 	*val = readl(to_nvme_dev(ctrl)->bar + off);
2953 	return 0;
2954 }
2955 
2956 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2957 {
2958 	writel(val, to_nvme_dev(ctrl)->bar + off);
2959 	return 0;
2960 }
2961 
2962 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2963 {
2964 	*val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2965 	return 0;
2966 }
2967 
2968 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2969 {
2970 	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2971 
2972 	return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2973 }
2974 
2975 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2976 	.name			= "pcie",
2977 	.module			= THIS_MODULE,
2978 	.flags			= NVME_F_METADATA_SUPPORTED |
2979 				  NVME_F_PCI_P2PDMA,
2980 	.reg_read32		= nvme_pci_reg_read32,
2981 	.reg_write32		= nvme_pci_reg_write32,
2982 	.reg_read64		= nvme_pci_reg_read64,
2983 	.free_ctrl		= nvme_pci_free_ctrl,
2984 	.submit_async_event	= nvme_pci_submit_async_event,
2985 	.get_address		= nvme_pci_get_address,
2986 };
2987 
2988 static int nvme_dev_map(struct nvme_dev *dev)
2989 {
2990 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2991 
2992 	if (pci_request_mem_regions(pdev, "nvme"))
2993 		return -ENODEV;
2994 
2995 	if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2996 		goto release;
2997 
2998 	return 0;
2999   release:
3000 	pci_release_mem_regions(pdev);
3001 	return -ENODEV;
3002 }
3003 
3004 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
3005 {
3006 	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
3007 		/*
3008 		 * Several Samsung devices seem to drop off the PCIe bus
3009 		 * randomly when APST is on and uses the deepest sleep state.
3010 		 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
3011 		 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
3012 		 * 950 PRO 256GB", but it seems to be restricted to two Dell
3013 		 * laptops.
3014 		 */
3015 		if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
3016 		    (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
3017 		     dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
3018 			return NVME_QUIRK_NO_DEEPEST_PS;
3019 	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
3020 		/*
3021 		 * Samsung SSD 960 EVO drops off the PCIe bus after system
3022 		 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
3023 		 * within few minutes after bootup on a Coffee Lake board -
3024 		 * ASUS PRIME Z370-A
3025 		 */
3026 		if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
3027 		    (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
3028 		     dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
3029 			return NVME_QUIRK_NO_APST;
3030 	} else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
3031 		    pdev->device == 0xa808 || pdev->device == 0xa809)) ||
3032 		   (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
3033 		/*
3034 		 * Forcing to use host managed nvme power settings for
3035 		 * lowest idle power with quick resume latency on
3036 		 * Samsung and Toshiba SSDs based on suspend behavior
3037 		 * on Coffee Lake board for LENOVO C640
3038 		 */
3039 		if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
3040 		     dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
3041 			return NVME_QUIRK_SIMPLE_SUSPEND;
3042 	}
3043 
3044 	return 0;
3045 }
3046 
3047 static void nvme_async_probe(void *data, async_cookie_t cookie)
3048 {
3049 	struct nvme_dev *dev = data;
3050 
3051 	flush_work(&dev->ctrl.reset_work);
3052 	flush_work(&dev->ctrl.scan_work);
3053 	nvme_put_ctrl(&dev->ctrl);
3054 }
3055 
3056 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3057 {
3058 	int node, result = -ENOMEM;
3059 	struct nvme_dev *dev;
3060 	unsigned long quirks = id->driver_data;
3061 	size_t alloc_size;
3062 
3063 	node = dev_to_node(&pdev->dev);
3064 	if (node == NUMA_NO_NODE)
3065 		set_dev_node(&pdev->dev, first_memory_node);
3066 
3067 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
3068 	if (!dev)
3069 		return -ENOMEM;
3070 
3071 	dev->nr_write_queues = write_queues;
3072 	dev->nr_poll_queues = poll_queues;
3073 	dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
3074 	dev->queues = kcalloc_node(dev->nr_allocated_queues,
3075 			sizeof(struct nvme_queue), GFP_KERNEL, node);
3076 	if (!dev->queues)
3077 		goto free;
3078 
3079 	dev->dev = get_device(&pdev->dev);
3080 	pci_set_drvdata(pdev, dev);
3081 
3082 	result = nvme_dev_map(dev);
3083 	if (result)
3084 		goto put_pci;
3085 
3086 	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
3087 	INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
3088 	mutex_init(&dev->shutdown_lock);
3089 
3090 	result = nvme_setup_prp_pools(dev);
3091 	if (result)
3092 		goto unmap;
3093 
3094 	quirks |= check_vendor_combination_bug(pdev);
3095 
3096 	if (!noacpi && acpi_storage_d3(&pdev->dev)) {
3097 		/*
3098 		 * Some systems use a bios work around to ask for D3 on
3099 		 * platforms that support kernel managed suspend.
3100 		 */
3101 		dev_info(&pdev->dev,
3102 			 "platform quirk: setting simple suspend\n");
3103 		quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
3104 	}
3105 
3106 	/*
3107 	 * Double check that our mempool alloc size will cover the biggest
3108 	 * command we support.
3109 	 */
3110 	alloc_size = nvme_pci_iod_alloc_size();
3111 	WARN_ON_ONCE(alloc_size > PAGE_SIZE);
3112 
3113 	dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
3114 						mempool_kfree,
3115 						(void *) alloc_size,
3116 						GFP_KERNEL, node);
3117 	if (!dev->iod_mempool) {
3118 		result = -ENOMEM;
3119 		goto release_pools;
3120 	}
3121 
3122 	result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
3123 			quirks);
3124 	if (result)
3125 		goto release_mempool;
3126 
3127 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3128 
3129 	nvme_reset_ctrl(&dev->ctrl);
3130 	async_schedule(nvme_async_probe, dev);
3131 
3132 	return 0;
3133 
3134  release_mempool:
3135 	mempool_destroy(dev->iod_mempool);
3136  release_pools:
3137 	nvme_release_prp_pools(dev);
3138  unmap:
3139 	nvme_dev_unmap(dev);
3140  put_pci:
3141 	put_device(dev->dev);
3142  free:
3143 	kfree(dev->queues);
3144 	kfree(dev);
3145 	return result;
3146 }
3147 
3148 static void nvme_reset_prepare(struct pci_dev *pdev)
3149 {
3150 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3151 
3152 	/*
3153 	 * We don't need to check the return value from waiting for the reset
3154 	 * state as pci_dev device lock is held, making it impossible to race
3155 	 * with ->remove().
3156 	 */
3157 	nvme_disable_prepare_reset(dev, false);
3158 	nvme_sync_queues(&dev->ctrl);
3159 }
3160 
3161 static void nvme_reset_done(struct pci_dev *pdev)
3162 {
3163 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3164 
3165 	if (!nvme_try_sched_reset(&dev->ctrl))
3166 		flush_work(&dev->ctrl.reset_work);
3167 }
3168 
3169 static void nvme_shutdown(struct pci_dev *pdev)
3170 {
3171 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3172 
3173 	nvme_disable_prepare_reset(dev, true);
3174 }
3175 
3176 static void nvme_remove_attrs(struct nvme_dev *dev)
3177 {
3178 	if (dev->attrs_added)
3179 		sysfs_remove_group(&dev->ctrl.device->kobj,
3180 				   &nvme_pci_attr_group);
3181 }
3182 
3183 /*
3184  * The driver's remove may be called on a device in a partially initialized
3185  * state. This function must not have any dependencies on the device state in
3186  * order to proceed.
3187  */
3188 static void nvme_remove(struct pci_dev *pdev)
3189 {
3190 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3191 
3192 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3193 	pci_set_drvdata(pdev, NULL);
3194 
3195 	if (!pci_device_is_present(pdev)) {
3196 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3197 		nvme_dev_disable(dev, true);
3198 	}
3199 
3200 	flush_work(&dev->ctrl.reset_work);
3201 	nvme_stop_ctrl(&dev->ctrl);
3202 	nvme_remove_namespaces(&dev->ctrl);
3203 	nvme_dev_disable(dev, true);
3204 	nvme_remove_attrs(dev);
3205 	nvme_free_host_mem(dev);
3206 	nvme_dev_remove_admin(dev);
3207 	nvme_free_queues(dev, 0);
3208 	nvme_release_prp_pools(dev);
3209 	nvme_dev_unmap(dev);
3210 	nvme_uninit_ctrl(&dev->ctrl);
3211 }
3212 
3213 #ifdef CONFIG_PM_SLEEP
3214 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3215 {
3216 	return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3217 }
3218 
3219 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3220 {
3221 	return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3222 }
3223 
3224 static int nvme_resume(struct device *dev)
3225 {
3226 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3227 	struct nvme_ctrl *ctrl = &ndev->ctrl;
3228 
3229 	if (ndev->last_ps == U32_MAX ||
3230 	    nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3231 		goto reset;
3232 	if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3233 		goto reset;
3234 
3235 	return 0;
3236 reset:
3237 	return nvme_try_sched_reset(ctrl);
3238 }
3239 
3240 static int nvme_suspend(struct device *dev)
3241 {
3242 	struct pci_dev *pdev = to_pci_dev(dev);
3243 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3244 	struct nvme_ctrl *ctrl = &ndev->ctrl;
3245 	int ret = -EBUSY;
3246 
3247 	ndev->last_ps = U32_MAX;
3248 
3249 	/*
3250 	 * The platform does not remove power for a kernel managed suspend so
3251 	 * use host managed nvme power settings for lowest idle power if
3252 	 * possible. This should have quicker resume latency than a full device
3253 	 * shutdown.  But if the firmware is involved after the suspend or the
3254 	 * device does not support any non-default power states, shut down the
3255 	 * device fully.
3256 	 *
3257 	 * If ASPM is not enabled for the device, shut down the device and allow
3258 	 * the PCI bus layer to put it into D3 in order to take the PCIe link
3259 	 * down, so as to allow the platform to achieve its minimum low-power
3260 	 * state (which may not be possible if the link is up).
3261 	 */
3262 	if (pm_suspend_via_firmware() || !ctrl->npss ||
3263 	    !pcie_aspm_enabled(pdev) ||
3264 	    (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3265 		return nvme_disable_prepare_reset(ndev, true);
3266 
3267 	nvme_start_freeze(ctrl);
3268 	nvme_wait_freeze(ctrl);
3269 	nvme_sync_queues(ctrl);
3270 
3271 	if (ctrl->state != NVME_CTRL_LIVE)
3272 		goto unfreeze;
3273 
3274 	/*
3275 	 * Host memory access may not be successful in a system suspend state,
3276 	 * but the specification allows the controller to access memory in a
3277 	 * non-operational power state.
3278 	 */
3279 	if (ndev->hmb) {
3280 		ret = nvme_set_host_mem(ndev, 0);
3281 		if (ret < 0)
3282 			goto unfreeze;
3283 	}
3284 
3285 	ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3286 	if (ret < 0)
3287 		goto unfreeze;
3288 
3289 	/*
3290 	 * A saved state prevents pci pm from generically controlling the
3291 	 * device's power. If we're using protocol specific settings, we don't
3292 	 * want pci interfering.
3293 	 */
3294 	pci_save_state(pdev);
3295 
3296 	ret = nvme_set_power_state(ctrl, ctrl->npss);
3297 	if (ret < 0)
3298 		goto unfreeze;
3299 
3300 	if (ret) {
3301 		/* discard the saved state */
3302 		pci_load_saved_state(pdev, NULL);
3303 
3304 		/*
3305 		 * Clearing npss forces a controller reset on resume. The
3306 		 * correct value will be rediscovered then.
3307 		 */
3308 		ret = nvme_disable_prepare_reset(ndev, true);
3309 		ctrl->npss = 0;
3310 	}
3311 unfreeze:
3312 	nvme_unfreeze(ctrl);
3313 	return ret;
3314 }
3315 
3316 static int nvme_simple_suspend(struct device *dev)
3317 {
3318 	struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3319 
3320 	return nvme_disable_prepare_reset(ndev, true);
3321 }
3322 
3323 static int nvme_simple_resume(struct device *dev)
3324 {
3325 	struct pci_dev *pdev = to_pci_dev(dev);
3326 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
3327 
3328 	return nvme_try_sched_reset(&ndev->ctrl);
3329 }
3330 
3331 static const struct dev_pm_ops nvme_dev_pm_ops = {
3332 	.suspend	= nvme_suspend,
3333 	.resume		= nvme_resume,
3334 	.freeze		= nvme_simple_suspend,
3335 	.thaw		= nvme_simple_resume,
3336 	.poweroff	= nvme_simple_suspend,
3337 	.restore	= nvme_simple_resume,
3338 };
3339 #endif /* CONFIG_PM_SLEEP */
3340 
3341 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3342 						pci_channel_state_t state)
3343 {
3344 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3345 
3346 	/*
3347 	 * A frozen channel requires a reset. When detected, this method will
3348 	 * shutdown the controller to quiesce. The controller will be restarted
3349 	 * after the slot reset through driver's slot_reset callback.
3350 	 */
3351 	switch (state) {
3352 	case pci_channel_io_normal:
3353 		return PCI_ERS_RESULT_CAN_RECOVER;
3354 	case pci_channel_io_frozen:
3355 		dev_warn(dev->ctrl.device,
3356 			"frozen state error detected, reset controller\n");
3357 		nvme_dev_disable(dev, false);
3358 		return PCI_ERS_RESULT_NEED_RESET;
3359 	case pci_channel_io_perm_failure:
3360 		dev_warn(dev->ctrl.device,
3361 			"failure state error detected, request disconnect\n");
3362 		return PCI_ERS_RESULT_DISCONNECT;
3363 	}
3364 	return PCI_ERS_RESULT_NEED_RESET;
3365 }
3366 
3367 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3368 {
3369 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3370 
3371 	dev_info(dev->ctrl.device, "restart after slot reset\n");
3372 	pci_restore_state(pdev);
3373 	nvme_reset_ctrl(&dev->ctrl);
3374 	return PCI_ERS_RESULT_RECOVERED;
3375 }
3376 
3377 static void nvme_error_resume(struct pci_dev *pdev)
3378 {
3379 	struct nvme_dev *dev = pci_get_drvdata(pdev);
3380 
3381 	flush_work(&dev->ctrl.reset_work);
3382 }
3383 
3384 static const struct pci_error_handlers nvme_err_handler = {
3385 	.error_detected	= nvme_error_detected,
3386 	.slot_reset	= nvme_slot_reset,
3387 	.resume		= nvme_error_resume,
3388 	.reset_prepare	= nvme_reset_prepare,
3389 	.reset_done	= nvme_reset_done,
3390 };
3391 
3392 static const struct pci_device_id nvme_id_table[] = {
3393 	{ PCI_VDEVICE(INTEL, 0x0953),	/* Intel 750/P3500/P3600/P3700 */
3394 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3395 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3396 	{ PCI_VDEVICE(INTEL, 0x0a53),	/* Intel P3520 */
3397 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3398 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3399 	{ PCI_VDEVICE(INTEL, 0x0a54),	/* Intel P4500/P4600 */
3400 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3401 				NVME_QUIRK_DEALLOCATE_ZEROES |
3402 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3403 	{ PCI_VDEVICE(INTEL, 0x0a55),	/* Dell Express Flash P4600 */
3404 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
3405 				NVME_QUIRK_DEALLOCATE_ZEROES, },
3406 	{ PCI_VDEVICE(INTEL, 0xf1a5),	/* Intel 600P/P3100 */
3407 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3408 				NVME_QUIRK_MEDIUM_PRIO_SQ |
3409 				NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3410 				NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3411 	{ PCI_VDEVICE(INTEL, 0xf1a6),	/* Intel 760p/Pro 7600p */
3412 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3413 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
3414 		.driver_data = NVME_QUIRK_IDENTIFY_CNS |
3415 				NVME_QUIRK_DISABLE_WRITE_ZEROES |
3416 				NVME_QUIRK_BOGUS_NID, },
3417 	{ PCI_VDEVICE(REDHAT, 0x0010),	/* Qemu emulated controller */
3418 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3419 	{ PCI_DEVICE(0x126f, 0x2263),	/* Silicon Motion unidentified */
3420 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3421 	{ PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3422 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3423 				NVME_QUIRK_NO_NS_DESC_LIST, },
3424 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
3425 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3426 	{ PCI_DEVICE(0x1c58, 0x0023),	/* WDC SN200 adapter */
3427 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3428 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
3429 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3430 	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3431 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3432 	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3433 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3434 				NVME_QUIRK_DISABLE_WRITE_ZEROES|
3435 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3436 	{ PCI_DEVICE(0x1987, 0x5016),	/* Phison E16 */
3437 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3438 	{ PCI_DEVICE(0x1b4b, 0x1092),	/* Lexar 256 GB SSD */
3439 		.driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3440 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3441 	{ PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3442 		.driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3443 	{ PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3444 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3445 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3446 	{ PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3447 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3448 	{ PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3449 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3450 	{ PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3451 		.driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3452 	{ PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3453 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3454 	{ PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3455 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3456 	{ PCI_DEVICE(0x1e4B, 0x1002),   /* MAXIO MAP1002 */
3457 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3458 	{ PCI_DEVICE(0x1e4B, 0x1202),   /* MAXIO MAP1202 */
3459 		.driver_data = NVME_QUIRK_BOGUS_NID, },
3460 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3461 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3462 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3463 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3464 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3465 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3466 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3467 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3468 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3469 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3470 	{ PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3471 		.driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3472 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3473 		.driver_data = NVME_QUIRK_SINGLE_VECTOR },
3474 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3475 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3476 		.driver_data = NVME_QUIRK_SINGLE_VECTOR |
3477 				NVME_QUIRK_128_BYTES_SQES |
3478 				NVME_QUIRK_SHARED_TAGS |
3479 				NVME_QUIRK_SKIP_CID_GEN },
3480 	{ PCI_DEVICE(0x144d, 0xa808),   /* Samsung X5 */
3481 		.driver_data =  NVME_QUIRK_DELAY_BEFORE_CHK_RDY|
3482 				NVME_QUIRK_NO_DEEPEST_PS |
3483 				NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3484 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3485 	{ 0, }
3486 };
3487 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3488 
3489 static struct pci_driver nvme_driver = {
3490 	.name		= "nvme",
3491 	.id_table	= nvme_id_table,
3492 	.probe		= nvme_probe,
3493 	.remove		= nvme_remove,
3494 	.shutdown	= nvme_shutdown,
3495 #ifdef CONFIG_PM_SLEEP
3496 	.driver		= {
3497 		.pm	= &nvme_dev_pm_ops,
3498 	},
3499 #endif
3500 	.sriov_configure = pci_sriov_configure_simple,
3501 	.err_handler	= &nvme_err_handler,
3502 };
3503 
3504 static int __init nvme_init(void)
3505 {
3506 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3507 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3508 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3509 	BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3510 
3511 	return pci_register_driver(&nvme_driver);
3512 }
3513 
3514 static void __exit nvme_exit(void)
3515 {
3516 	pci_unregister_driver(&nvme_driver);
3517 	flush_workqueue(nvme_wq);
3518 }
3519 
3520 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3521 MODULE_LICENSE("GPL");
3522 MODULE_VERSION("1.0");
3523 module_init(nvme_init);
3524 module_exit(nvme_exit);
3525