1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/aer.h> 9 #include <linux/async.h> 10 #include <linux/blkdev.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/blk-integrity.h> 14 #include <linux/dmi.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/kstrtox.h> 19 #include <linux/memremap.h> 20 #include <linux/mm.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/once.h> 24 #include <linux/pci.h> 25 #include <linux/suspend.h> 26 #include <linux/t10-pi.h> 27 #include <linux/types.h> 28 #include <linux/io-64-nonatomic-lo-hi.h> 29 #include <linux/io-64-nonatomic-hi-lo.h> 30 #include <linux/sed-opal.h> 31 #include <linux/pci-p2pdma.h> 32 33 #include "trace.h" 34 #include "nvme.h" 35 36 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 37 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 38 39 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40 41 /* 42 * These can be higher, but we need to ensure that any command doesn't 43 * require an sg allocation that needs more than a page of data. 44 */ 45 #define NVME_MAX_KB_SZ 8192 46 #define NVME_MAX_SEGS 128 47 #define NVME_MAX_NR_ALLOCATIONS 5 48 49 static int use_threaded_interrupts; 50 module_param(use_threaded_interrupts, int, 0444); 51 52 static bool use_cmb_sqes = true; 53 module_param(use_cmb_sqes, bool, 0444); 54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 55 56 static unsigned int max_host_mem_size_mb = 128; 57 module_param(max_host_mem_size_mb, uint, 0444); 58 MODULE_PARM_DESC(max_host_mem_size_mb, 59 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 60 61 static unsigned int sgl_threshold = SZ_32K; 62 module_param(sgl_threshold, uint, 0644); 63 MODULE_PARM_DESC(sgl_threshold, 64 "Use SGLs when average request segment size is larger or equal to " 65 "this size. Use 0 to disable SGLs."); 66 67 #define NVME_PCI_MIN_QUEUE_SIZE 2 68 #define NVME_PCI_MAX_QUEUE_SIZE 4095 69 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 70 static const struct kernel_param_ops io_queue_depth_ops = { 71 .set = io_queue_depth_set, 72 .get = param_get_uint, 73 }; 74 75 static unsigned int io_queue_depth = 1024; 76 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 77 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 78 79 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 80 { 81 unsigned int n; 82 int ret; 83 84 ret = kstrtouint(val, 10, &n); 85 if (ret != 0 || n > num_possible_cpus()) 86 return -EINVAL; 87 return param_set_uint(val, kp); 88 } 89 90 static const struct kernel_param_ops io_queue_count_ops = { 91 .set = io_queue_count_set, 92 .get = param_get_uint, 93 }; 94 95 static unsigned int write_queues; 96 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 97 MODULE_PARM_DESC(write_queues, 98 "Number of queues to use for writes. If not set, reads and writes " 99 "will share a queue set."); 100 101 static unsigned int poll_queues; 102 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 103 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 104 105 static bool noacpi; 106 module_param(noacpi, bool, 0444); 107 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 108 109 struct nvme_dev; 110 struct nvme_queue; 111 112 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 113 static void nvme_delete_io_queues(struct nvme_dev *dev); 114 115 /* 116 * Represents an NVM Express device. Each nvme_dev is a PCI function. 117 */ 118 struct nvme_dev { 119 struct nvme_queue *queues; 120 struct blk_mq_tag_set tagset; 121 struct blk_mq_tag_set admin_tagset; 122 u32 __iomem *dbs; 123 struct device *dev; 124 struct dma_pool *prp_page_pool; 125 struct dma_pool *prp_small_pool; 126 unsigned online_queues; 127 unsigned max_qid; 128 unsigned io_queues[HCTX_MAX_TYPES]; 129 unsigned int num_vecs; 130 u32 q_depth; 131 int io_sqes; 132 u32 db_stride; 133 void __iomem *bar; 134 unsigned long bar_mapped_size; 135 struct mutex shutdown_lock; 136 bool subsystem; 137 u64 cmb_size; 138 bool cmb_use_sqes; 139 u32 cmbsz; 140 u32 cmbloc; 141 struct nvme_ctrl ctrl; 142 u32 last_ps; 143 bool hmb; 144 145 mempool_t *iod_mempool; 146 147 /* shadow doorbell buffer support: */ 148 __le32 *dbbuf_dbs; 149 dma_addr_t dbbuf_dbs_dma_addr; 150 __le32 *dbbuf_eis; 151 dma_addr_t dbbuf_eis_dma_addr; 152 153 /* host memory buffer support: */ 154 u64 host_mem_size; 155 u32 nr_host_mem_descs; 156 dma_addr_t host_mem_descs_dma; 157 struct nvme_host_mem_buf_desc *host_mem_descs; 158 void **host_mem_desc_bufs; 159 unsigned int nr_allocated_queues; 160 unsigned int nr_write_queues; 161 unsigned int nr_poll_queues; 162 }; 163 164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 165 { 166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 167 NVME_PCI_MAX_QUEUE_SIZE); 168 } 169 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171 { 172 return qid * 2 * stride; 173 } 174 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176 { 177 return (qid * 2 + 1) * stride; 178 } 179 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 181 { 182 return container_of(ctrl, struct nvme_dev, ctrl); 183 } 184 185 /* 186 * An NVM Express queue. Each device has at least two (one for admin 187 * commands and one for I/O commands). 188 */ 189 struct nvme_queue { 190 struct nvme_dev *dev; 191 spinlock_t sq_lock; 192 void *sq_cmds; 193 /* only used for poll queues: */ 194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 195 struct nvme_completion *cqes; 196 dma_addr_t sq_dma_addr; 197 dma_addr_t cq_dma_addr; 198 u32 __iomem *q_db; 199 u32 q_depth; 200 u16 cq_vector; 201 u16 sq_tail; 202 u16 last_sq_tail; 203 u16 cq_head; 204 u16 qid; 205 u8 cq_phase; 206 u8 sqes; 207 unsigned long flags; 208 #define NVMEQ_ENABLED 0 209 #define NVMEQ_SQ_CMB 1 210 #define NVMEQ_DELETE_ERROR 2 211 #define NVMEQ_POLLED 3 212 __le32 *dbbuf_sq_db; 213 __le32 *dbbuf_cq_db; 214 __le32 *dbbuf_sq_ei; 215 __le32 *dbbuf_cq_ei; 216 struct completion delete_done; 217 }; 218 219 union nvme_descriptor { 220 struct nvme_sgl_desc *sg_list; 221 __le64 *prp_list; 222 }; 223 224 /* 225 * The nvme_iod describes the data in an I/O. 226 * 227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 228 * to the actual struct scatterlist. 229 */ 230 struct nvme_iod { 231 struct nvme_request req; 232 struct nvme_command cmd; 233 bool aborted; 234 s8 nr_allocations; /* PRP list pool allocations. 0 means small 235 pool in use */ 236 unsigned int dma_len; /* length of single DMA segment mapping */ 237 dma_addr_t first_dma; 238 dma_addr_t meta_dma; 239 struct sg_table sgt; 240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS]; 241 }; 242 243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 244 { 245 return dev->nr_allocated_queues * 8 * dev->db_stride; 246 } 247 248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 249 { 250 unsigned int mem_size = nvme_dbbuf_size(dev); 251 252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 253 return; 254 255 if (dev->dbbuf_dbs) { 256 /* 257 * Clear the dbbuf memory so the driver doesn't observe stale 258 * values from the previous instantiation. 259 */ 260 memset(dev->dbbuf_dbs, 0, mem_size); 261 memset(dev->dbbuf_eis, 0, mem_size); 262 return; 263 } 264 265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 266 &dev->dbbuf_dbs_dma_addr, 267 GFP_KERNEL); 268 if (!dev->dbbuf_dbs) 269 goto fail; 270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 271 &dev->dbbuf_eis_dma_addr, 272 GFP_KERNEL); 273 if (!dev->dbbuf_eis) 274 goto fail_free_dbbuf_dbs; 275 return; 276 277 fail_free_dbbuf_dbs: 278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 279 dev->dbbuf_dbs_dma_addr); 280 dev->dbbuf_dbs = NULL; 281 fail: 282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 283 } 284 285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 286 { 287 unsigned int mem_size = nvme_dbbuf_size(dev); 288 289 if (dev->dbbuf_dbs) { 290 dma_free_coherent(dev->dev, mem_size, 291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 292 dev->dbbuf_dbs = NULL; 293 } 294 if (dev->dbbuf_eis) { 295 dma_free_coherent(dev->dev, mem_size, 296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 297 dev->dbbuf_eis = NULL; 298 } 299 } 300 301 static void nvme_dbbuf_init(struct nvme_dev *dev, 302 struct nvme_queue *nvmeq, int qid) 303 { 304 if (!dev->dbbuf_dbs || !qid) 305 return; 306 307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 311 } 312 313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 314 { 315 if (!nvmeq->qid) 316 return; 317 318 nvmeq->dbbuf_sq_db = NULL; 319 nvmeq->dbbuf_cq_db = NULL; 320 nvmeq->dbbuf_sq_ei = NULL; 321 nvmeq->dbbuf_cq_ei = NULL; 322 } 323 324 static void nvme_dbbuf_set(struct nvme_dev *dev) 325 { 326 struct nvme_command c = { }; 327 unsigned int i; 328 329 if (!dev->dbbuf_dbs) 330 return; 331 332 c.dbbuf.opcode = nvme_admin_dbbuf; 333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 335 336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 338 /* Free memory and continue on */ 339 nvme_dbbuf_dma_free(dev); 340 341 for (i = 1; i <= dev->online_queues; i++) 342 nvme_dbbuf_free(&dev->queues[i]); 343 } 344 } 345 346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 347 { 348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 349 } 350 351 /* Update dbbuf and return true if an MMIO is required */ 352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db, 353 volatile __le32 *dbbuf_ei) 354 { 355 if (dbbuf_db) { 356 u16 old_value, event_idx; 357 358 /* 359 * Ensure that the queue is written before updating 360 * the doorbell in memory 361 */ 362 wmb(); 363 364 old_value = le32_to_cpu(*dbbuf_db); 365 *dbbuf_db = cpu_to_le32(value); 366 367 /* 368 * Ensure that the doorbell is updated before reading the event 369 * index from memory. The controller needs to provide similar 370 * ordering to ensure the envent index is updated before reading 371 * the doorbell. 372 */ 373 mb(); 374 375 event_idx = le32_to_cpu(*dbbuf_ei); 376 if (!nvme_dbbuf_need_event(event_idx, value, old_value)) 377 return false; 378 } 379 380 return true; 381 } 382 383 /* 384 * Will slightly overestimate the number of pages needed. This is OK 385 * as it only leads to a small amount of wasted memory for the lifetime of 386 * the I/O. 387 */ 388 static int nvme_pci_npages_prp(void) 389 { 390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; 391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); 392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); 393 } 394 395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 396 unsigned int hctx_idx) 397 { 398 struct nvme_dev *dev = to_nvme_dev(data); 399 struct nvme_queue *nvmeq = &dev->queues[0]; 400 401 WARN_ON(hctx_idx != 0); 402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 403 404 hctx->driver_data = nvmeq; 405 return 0; 406 } 407 408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 409 unsigned int hctx_idx) 410 { 411 struct nvme_dev *dev = to_nvme_dev(data); 412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 413 414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 415 hctx->driver_data = nvmeq; 416 return 0; 417 } 418 419 static int nvme_pci_init_request(struct blk_mq_tag_set *set, 420 struct request *req, unsigned int hctx_idx, 421 unsigned int numa_node) 422 { 423 struct nvme_dev *dev = to_nvme_dev(set->driver_data); 424 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 425 426 nvme_req(req)->ctrl = &dev->ctrl; 427 nvme_req(req)->cmd = &iod->cmd; 428 return 0; 429 } 430 431 static int queue_irq_offset(struct nvme_dev *dev) 432 { 433 /* if we have more than 1 vec, admin queue offsets us by 1 */ 434 if (dev->num_vecs > 1) 435 return 1; 436 437 return 0; 438 } 439 440 static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 441 { 442 struct nvme_dev *dev = to_nvme_dev(set->driver_data); 443 int i, qoff, offset; 444 445 offset = queue_irq_offset(dev); 446 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 447 struct blk_mq_queue_map *map = &set->map[i]; 448 449 map->nr_queues = dev->io_queues[i]; 450 if (!map->nr_queues) { 451 BUG_ON(i == HCTX_TYPE_DEFAULT); 452 continue; 453 } 454 455 /* 456 * The poll queue(s) doesn't have an IRQ (and hence IRQ 457 * affinity), so use the regular blk-mq cpu mapping 458 */ 459 map->queue_offset = qoff; 460 if (i != HCTX_TYPE_POLL && offset) 461 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 462 else 463 blk_mq_map_queues(map); 464 qoff += map->nr_queues; 465 offset += map->nr_queues; 466 } 467 } 468 469 /* 470 * Write sq tail if we are asked to, or if the next command would wrap. 471 */ 472 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 473 { 474 if (!write_sq) { 475 u16 next_tail = nvmeq->sq_tail + 1; 476 477 if (next_tail == nvmeq->q_depth) 478 next_tail = 0; 479 if (next_tail != nvmeq->last_sq_tail) 480 return; 481 } 482 483 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 484 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 485 writel(nvmeq->sq_tail, nvmeq->q_db); 486 nvmeq->last_sq_tail = nvmeq->sq_tail; 487 } 488 489 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 490 struct nvme_command *cmd) 491 { 492 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 493 absolute_pointer(cmd), sizeof(*cmd)); 494 if (++nvmeq->sq_tail == nvmeq->q_depth) 495 nvmeq->sq_tail = 0; 496 } 497 498 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 499 { 500 struct nvme_queue *nvmeq = hctx->driver_data; 501 502 spin_lock(&nvmeq->sq_lock); 503 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 504 nvme_write_sq_db(nvmeq, true); 505 spin_unlock(&nvmeq->sq_lock); 506 } 507 508 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req, 509 int nseg) 510 { 511 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 512 unsigned int avg_seg_size; 513 514 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 515 516 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 517 return false; 518 if (!nvmeq->qid) 519 return false; 520 if (!sgl_threshold || avg_seg_size < sgl_threshold) 521 return false; 522 return true; 523 } 524 525 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 526 { 527 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 528 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 529 dma_addr_t dma_addr = iod->first_dma; 530 int i; 531 532 for (i = 0; i < iod->nr_allocations; i++) { 533 __le64 *prp_list = iod->list[i].prp_list; 534 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 535 536 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 537 dma_addr = next_dma_addr; 538 } 539 } 540 541 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 542 { 543 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 544 545 if (iod->dma_len) { 546 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 547 rq_dma_dir(req)); 548 return; 549 } 550 551 WARN_ON_ONCE(!iod->sgt.nents); 552 553 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 554 555 if (iod->nr_allocations == 0) 556 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, 557 iod->first_dma); 558 else if (iod->nr_allocations == 1) 559 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, 560 iod->first_dma); 561 else 562 nvme_free_prps(dev, req); 563 mempool_free(iod->sgt.sgl, dev->iod_mempool); 564 } 565 566 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 567 { 568 int i; 569 struct scatterlist *sg; 570 571 for_each_sg(sgl, sg, nents, i) { 572 dma_addr_t phys = sg_phys(sg); 573 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 574 "dma_address:%pad dma_length:%d\n", 575 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 576 sg_dma_len(sg)); 577 } 578 } 579 580 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 581 struct request *req, struct nvme_rw_command *cmnd) 582 { 583 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 584 struct dma_pool *pool; 585 int length = blk_rq_payload_bytes(req); 586 struct scatterlist *sg = iod->sgt.sgl; 587 int dma_len = sg_dma_len(sg); 588 u64 dma_addr = sg_dma_address(sg); 589 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 590 __le64 *prp_list; 591 dma_addr_t prp_dma; 592 int nprps, i; 593 594 length -= (NVME_CTRL_PAGE_SIZE - offset); 595 if (length <= 0) { 596 iod->first_dma = 0; 597 goto done; 598 } 599 600 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 601 if (dma_len) { 602 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 603 } else { 604 sg = sg_next(sg); 605 dma_addr = sg_dma_address(sg); 606 dma_len = sg_dma_len(sg); 607 } 608 609 if (length <= NVME_CTRL_PAGE_SIZE) { 610 iod->first_dma = dma_addr; 611 goto done; 612 } 613 614 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 615 if (nprps <= (256 / 8)) { 616 pool = dev->prp_small_pool; 617 iod->nr_allocations = 0; 618 } else { 619 pool = dev->prp_page_pool; 620 iod->nr_allocations = 1; 621 } 622 623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 624 if (!prp_list) { 625 iod->nr_allocations = -1; 626 return BLK_STS_RESOURCE; 627 } 628 iod->list[0].prp_list = prp_list; 629 iod->first_dma = prp_dma; 630 i = 0; 631 for (;;) { 632 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 633 __le64 *old_prp_list = prp_list; 634 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 635 if (!prp_list) 636 goto free_prps; 637 iod->list[iod->nr_allocations++].prp_list = prp_list; 638 prp_list[0] = old_prp_list[i - 1]; 639 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 640 i = 1; 641 } 642 prp_list[i++] = cpu_to_le64(dma_addr); 643 dma_len -= NVME_CTRL_PAGE_SIZE; 644 dma_addr += NVME_CTRL_PAGE_SIZE; 645 length -= NVME_CTRL_PAGE_SIZE; 646 if (length <= 0) 647 break; 648 if (dma_len > 0) 649 continue; 650 if (unlikely(dma_len < 0)) 651 goto bad_sgl; 652 sg = sg_next(sg); 653 dma_addr = sg_dma_address(sg); 654 dma_len = sg_dma_len(sg); 655 } 656 done: 657 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 658 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 659 return BLK_STS_OK; 660 free_prps: 661 nvme_free_prps(dev, req); 662 return BLK_STS_RESOURCE; 663 bad_sgl: 664 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 665 "Invalid SGL for payload:%d nents:%d\n", 666 blk_rq_payload_bytes(req), iod->sgt.nents); 667 return BLK_STS_IOERR; 668 } 669 670 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 671 struct scatterlist *sg) 672 { 673 sge->addr = cpu_to_le64(sg_dma_address(sg)); 674 sge->length = cpu_to_le32(sg_dma_len(sg)); 675 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 676 } 677 678 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 679 dma_addr_t dma_addr, int entries) 680 { 681 sge->addr = cpu_to_le64(dma_addr); 682 sge->length = cpu_to_le32(entries * sizeof(*sge)); 683 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 684 } 685 686 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 687 struct request *req, struct nvme_rw_command *cmd) 688 { 689 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 690 struct dma_pool *pool; 691 struct nvme_sgl_desc *sg_list; 692 struct scatterlist *sg = iod->sgt.sgl; 693 unsigned int entries = iod->sgt.nents; 694 dma_addr_t sgl_dma; 695 int i = 0; 696 697 /* setting the transfer type as SGL */ 698 cmd->flags = NVME_CMD_SGL_METABUF; 699 700 if (entries == 1) { 701 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 702 return BLK_STS_OK; 703 } 704 705 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 706 pool = dev->prp_small_pool; 707 iod->nr_allocations = 0; 708 } else { 709 pool = dev->prp_page_pool; 710 iod->nr_allocations = 1; 711 } 712 713 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 714 if (!sg_list) { 715 iod->nr_allocations = -1; 716 return BLK_STS_RESOURCE; 717 } 718 719 iod->list[0].sg_list = sg_list; 720 iod->first_dma = sgl_dma; 721 722 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 723 do { 724 nvme_pci_sgl_set_data(&sg_list[i++], sg); 725 sg = sg_next(sg); 726 } while (--entries > 0); 727 728 return BLK_STS_OK; 729 } 730 731 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 732 struct request *req, struct nvme_rw_command *cmnd, 733 struct bio_vec *bv) 734 { 735 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 736 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 737 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 738 739 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 740 if (dma_mapping_error(dev->dev, iod->first_dma)) 741 return BLK_STS_RESOURCE; 742 iod->dma_len = bv->bv_len; 743 744 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 745 if (bv->bv_len > first_prp_len) 746 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 747 else 748 cmnd->dptr.prp2 = 0; 749 return BLK_STS_OK; 750 } 751 752 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 753 struct request *req, struct nvme_rw_command *cmnd, 754 struct bio_vec *bv) 755 { 756 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 757 758 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 759 if (dma_mapping_error(dev->dev, iod->first_dma)) 760 return BLK_STS_RESOURCE; 761 iod->dma_len = bv->bv_len; 762 763 cmnd->flags = NVME_CMD_SGL_METABUF; 764 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 765 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 766 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 767 return BLK_STS_OK; 768 } 769 770 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 771 struct nvme_command *cmnd) 772 { 773 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 774 blk_status_t ret = BLK_STS_RESOURCE; 775 int rc; 776 777 if (blk_rq_nr_phys_segments(req) == 1) { 778 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 779 struct bio_vec bv = req_bvec(req); 780 781 if (!is_pci_p2pdma_page(bv.bv_page)) { 782 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 783 return nvme_setup_prp_simple(dev, req, 784 &cmnd->rw, &bv); 785 786 if (nvmeq->qid && sgl_threshold && 787 nvme_ctrl_sgl_supported(&dev->ctrl)) 788 return nvme_setup_sgl_simple(dev, req, 789 &cmnd->rw, &bv); 790 } 791 } 792 793 iod->dma_len = 0; 794 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 795 if (!iod->sgt.sgl) 796 return BLK_STS_RESOURCE; 797 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 798 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 799 if (!iod->sgt.orig_nents) 800 goto out_free_sg; 801 802 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 803 DMA_ATTR_NO_WARN); 804 if (rc) { 805 if (rc == -EREMOTEIO) 806 ret = BLK_STS_TARGET; 807 goto out_free_sg; 808 } 809 810 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents)) 811 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 812 else 813 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 814 if (ret != BLK_STS_OK) 815 goto out_unmap_sg; 816 return BLK_STS_OK; 817 818 out_unmap_sg: 819 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 820 out_free_sg: 821 mempool_free(iod->sgt.sgl, dev->iod_mempool); 822 return ret; 823 } 824 825 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 826 struct nvme_command *cmnd) 827 { 828 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 829 830 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 831 rq_dma_dir(req), 0); 832 if (dma_mapping_error(dev->dev, iod->meta_dma)) 833 return BLK_STS_IOERR; 834 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 835 return BLK_STS_OK; 836 } 837 838 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 839 { 840 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 841 blk_status_t ret; 842 843 iod->aborted = false; 844 iod->nr_allocations = -1; 845 iod->sgt.nents = 0; 846 847 ret = nvme_setup_cmd(req->q->queuedata, req); 848 if (ret) 849 return ret; 850 851 if (blk_rq_nr_phys_segments(req)) { 852 ret = nvme_map_data(dev, req, &iod->cmd); 853 if (ret) 854 goto out_free_cmd; 855 } 856 857 if (blk_integrity_rq(req)) { 858 ret = nvme_map_metadata(dev, req, &iod->cmd); 859 if (ret) 860 goto out_unmap_data; 861 } 862 863 nvme_start_request(req); 864 return BLK_STS_OK; 865 out_unmap_data: 866 nvme_unmap_data(dev, req); 867 out_free_cmd: 868 nvme_cleanup_cmd(req); 869 return ret; 870 } 871 872 /* 873 * NOTE: ns is NULL when called on the admin queue. 874 */ 875 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 876 const struct blk_mq_queue_data *bd) 877 { 878 struct nvme_queue *nvmeq = hctx->driver_data; 879 struct nvme_dev *dev = nvmeq->dev; 880 struct request *req = bd->rq; 881 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 882 blk_status_t ret; 883 884 /* 885 * We should not need to do this, but we're still using this to 886 * ensure we can drain requests on a dying queue. 887 */ 888 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 889 return BLK_STS_IOERR; 890 891 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 892 return nvme_fail_nonready_command(&dev->ctrl, req); 893 894 ret = nvme_prep_rq(dev, req); 895 if (unlikely(ret)) 896 return ret; 897 spin_lock(&nvmeq->sq_lock); 898 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 899 nvme_write_sq_db(nvmeq, bd->last); 900 spin_unlock(&nvmeq->sq_lock); 901 return BLK_STS_OK; 902 } 903 904 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 905 { 906 spin_lock(&nvmeq->sq_lock); 907 while (!rq_list_empty(*rqlist)) { 908 struct request *req = rq_list_pop(rqlist); 909 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 910 911 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 912 } 913 nvme_write_sq_db(nvmeq, true); 914 spin_unlock(&nvmeq->sq_lock); 915 } 916 917 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 918 { 919 /* 920 * We should not need to do this, but we're still using this to 921 * ensure we can drain requests on a dying queue. 922 */ 923 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 924 return false; 925 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 926 return false; 927 928 req->mq_hctx->tags->rqs[req->tag] = req; 929 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 930 } 931 932 static void nvme_queue_rqs(struct request **rqlist) 933 { 934 struct request *req, *next, *prev = NULL; 935 struct request *requeue_list = NULL; 936 937 rq_list_for_each_safe(rqlist, req, next) { 938 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 939 940 if (!nvme_prep_rq_batch(nvmeq, req)) { 941 /* detach 'req' and add to remainder list */ 942 rq_list_move(rqlist, &requeue_list, req, prev); 943 944 req = prev; 945 if (!req) 946 continue; 947 } 948 949 if (!next || req->mq_hctx != next->mq_hctx) { 950 /* detach rest of list, and submit */ 951 req->rq_next = NULL; 952 nvme_submit_cmds(nvmeq, rqlist); 953 *rqlist = next; 954 prev = NULL; 955 } else 956 prev = req; 957 } 958 959 *rqlist = requeue_list; 960 } 961 962 static __always_inline void nvme_pci_unmap_rq(struct request *req) 963 { 964 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 965 struct nvme_dev *dev = nvmeq->dev; 966 967 if (blk_integrity_rq(req)) { 968 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 969 970 dma_unmap_page(dev->dev, iod->meta_dma, 971 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 972 } 973 974 if (blk_rq_nr_phys_segments(req)) 975 nvme_unmap_data(dev, req); 976 } 977 978 static void nvme_pci_complete_rq(struct request *req) 979 { 980 nvme_pci_unmap_rq(req); 981 nvme_complete_rq(req); 982 } 983 984 static void nvme_pci_complete_batch(struct io_comp_batch *iob) 985 { 986 nvme_complete_batch(iob, nvme_pci_unmap_rq); 987 } 988 989 /* We read the CQE phase first to check if the rest of the entry is valid */ 990 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 991 { 992 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 993 994 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 995 } 996 997 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 998 { 999 u16 head = nvmeq->cq_head; 1000 1001 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1002 nvmeq->dbbuf_cq_ei)) 1003 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1004 } 1005 1006 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1007 { 1008 if (!nvmeq->qid) 1009 return nvmeq->dev->admin_tagset.tags[0]; 1010 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1011 } 1012 1013 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1014 struct io_comp_batch *iob, u16 idx) 1015 { 1016 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1017 __u16 command_id = READ_ONCE(cqe->command_id); 1018 struct request *req; 1019 1020 /* 1021 * AEN requests are special as they don't time out and can 1022 * survive any kind of queue freeze and often don't respond to 1023 * aborts. We don't even bother to allocate a struct request 1024 * for them but rather special case them here. 1025 */ 1026 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1027 nvme_complete_async_event(&nvmeq->dev->ctrl, 1028 cqe->status, &cqe->result); 1029 return; 1030 } 1031 1032 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1033 if (unlikely(!req)) { 1034 dev_warn(nvmeq->dev->ctrl.device, 1035 "invalid id %d completed on queue %d\n", 1036 command_id, le16_to_cpu(cqe->sq_id)); 1037 return; 1038 } 1039 1040 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1041 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1042 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1043 nvme_pci_complete_batch)) 1044 nvme_pci_complete_rq(req); 1045 } 1046 1047 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1048 { 1049 u32 tmp = nvmeq->cq_head + 1; 1050 1051 if (tmp == nvmeq->q_depth) { 1052 nvmeq->cq_head = 0; 1053 nvmeq->cq_phase ^= 1; 1054 } else { 1055 nvmeq->cq_head = tmp; 1056 } 1057 } 1058 1059 static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1060 struct io_comp_batch *iob) 1061 { 1062 int found = 0; 1063 1064 while (nvme_cqe_pending(nvmeq)) { 1065 found++; 1066 /* 1067 * load-load control dependency between phase and the rest of 1068 * the cqe requires a full read memory barrier 1069 */ 1070 dma_rmb(); 1071 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 1072 nvme_update_cq_head(nvmeq); 1073 } 1074 1075 if (found) 1076 nvme_ring_cq_doorbell(nvmeq); 1077 return found; 1078 } 1079 1080 static irqreturn_t nvme_irq(int irq, void *data) 1081 { 1082 struct nvme_queue *nvmeq = data; 1083 DEFINE_IO_COMP_BATCH(iob); 1084 1085 if (nvme_poll_cq(nvmeq, &iob)) { 1086 if (!rq_list_empty(iob.req_list)) 1087 nvme_pci_complete_batch(&iob); 1088 return IRQ_HANDLED; 1089 } 1090 return IRQ_NONE; 1091 } 1092 1093 static irqreturn_t nvme_irq_check(int irq, void *data) 1094 { 1095 struct nvme_queue *nvmeq = data; 1096 1097 if (nvme_cqe_pending(nvmeq)) 1098 return IRQ_WAKE_THREAD; 1099 return IRQ_NONE; 1100 } 1101 1102 /* 1103 * Poll for completions for any interrupt driven queue 1104 * Can be called from any context. 1105 */ 1106 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1107 { 1108 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1109 1110 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1111 1112 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1113 nvme_poll_cq(nvmeq, NULL); 1114 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1115 } 1116 1117 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 1118 { 1119 struct nvme_queue *nvmeq = hctx->driver_data; 1120 bool found; 1121 1122 if (!nvme_cqe_pending(nvmeq)) 1123 return 0; 1124 1125 spin_lock(&nvmeq->cq_poll_lock); 1126 found = nvme_poll_cq(nvmeq, iob); 1127 spin_unlock(&nvmeq->cq_poll_lock); 1128 1129 return found; 1130 } 1131 1132 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1133 { 1134 struct nvme_dev *dev = to_nvme_dev(ctrl); 1135 struct nvme_queue *nvmeq = &dev->queues[0]; 1136 struct nvme_command c = { }; 1137 1138 c.common.opcode = nvme_admin_async_event; 1139 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1140 1141 spin_lock(&nvmeq->sq_lock); 1142 nvme_sq_copy_cmd(nvmeq, &c); 1143 nvme_write_sq_db(nvmeq, true); 1144 spin_unlock(&nvmeq->sq_lock); 1145 } 1146 1147 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1148 { 1149 struct nvme_command c = { }; 1150 1151 c.delete_queue.opcode = opcode; 1152 c.delete_queue.qid = cpu_to_le16(id); 1153 1154 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1155 } 1156 1157 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1158 struct nvme_queue *nvmeq, s16 vector) 1159 { 1160 struct nvme_command c = { }; 1161 int flags = NVME_QUEUE_PHYS_CONTIG; 1162 1163 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1164 flags |= NVME_CQ_IRQ_ENABLED; 1165 1166 /* 1167 * Note: we (ab)use the fact that the prp fields survive if no data 1168 * is attached to the request. 1169 */ 1170 c.create_cq.opcode = nvme_admin_create_cq; 1171 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1172 c.create_cq.cqid = cpu_to_le16(qid); 1173 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1174 c.create_cq.cq_flags = cpu_to_le16(flags); 1175 c.create_cq.irq_vector = cpu_to_le16(vector); 1176 1177 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1178 } 1179 1180 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1181 struct nvme_queue *nvmeq) 1182 { 1183 struct nvme_ctrl *ctrl = &dev->ctrl; 1184 struct nvme_command c = { }; 1185 int flags = NVME_QUEUE_PHYS_CONTIG; 1186 1187 /* 1188 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1189 * set. Since URGENT priority is zeroes, it makes all queues 1190 * URGENT. 1191 */ 1192 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1193 flags |= NVME_SQ_PRIO_MEDIUM; 1194 1195 /* 1196 * Note: we (ab)use the fact that the prp fields survive if no data 1197 * is attached to the request. 1198 */ 1199 c.create_sq.opcode = nvme_admin_create_sq; 1200 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1201 c.create_sq.sqid = cpu_to_le16(qid); 1202 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1203 c.create_sq.sq_flags = cpu_to_le16(flags); 1204 c.create_sq.cqid = cpu_to_le16(qid); 1205 1206 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1207 } 1208 1209 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1210 { 1211 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1212 } 1213 1214 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1215 { 1216 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1217 } 1218 1219 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 1220 { 1221 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1222 1223 dev_warn(nvmeq->dev->ctrl.device, 1224 "Abort status: 0x%x", nvme_req(req)->status); 1225 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1226 blk_mq_free_request(req); 1227 return RQ_END_IO_NONE; 1228 } 1229 1230 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1231 { 1232 /* If true, indicates loss of adapter communication, possibly by a 1233 * NVMe Subsystem reset. 1234 */ 1235 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1236 1237 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1238 switch (dev->ctrl.state) { 1239 case NVME_CTRL_RESETTING: 1240 case NVME_CTRL_CONNECTING: 1241 return false; 1242 default: 1243 break; 1244 } 1245 1246 /* We shouldn't reset unless the controller is on fatal error state 1247 * _or_ if we lost the communication with it. 1248 */ 1249 if (!(csts & NVME_CSTS_CFS) && !nssro) 1250 return false; 1251 1252 return true; 1253 } 1254 1255 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1256 { 1257 /* Read a config register to help see what died. */ 1258 u16 pci_status; 1259 int result; 1260 1261 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1262 &pci_status); 1263 if (result == PCIBIOS_SUCCESSFUL) 1264 dev_warn(dev->ctrl.device, 1265 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1266 csts, pci_status); 1267 else 1268 dev_warn(dev->ctrl.device, 1269 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1270 csts, result); 1271 1272 if (csts != ~0) 1273 return; 1274 1275 dev_warn(dev->ctrl.device, 1276 "Does your device have a faulty power saving mode enabled?\n"); 1277 dev_warn(dev->ctrl.device, 1278 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1279 } 1280 1281 static enum blk_eh_timer_return nvme_timeout(struct request *req) 1282 { 1283 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1284 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1285 struct nvme_dev *dev = nvmeq->dev; 1286 struct request *abort_req; 1287 struct nvme_command cmd = { }; 1288 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1289 1290 /* If PCI error recovery process is happening, we cannot reset or 1291 * the recovery mechanism will surely fail. 1292 */ 1293 mb(); 1294 if (pci_channel_offline(to_pci_dev(dev->dev))) 1295 return BLK_EH_RESET_TIMER; 1296 1297 /* 1298 * Reset immediately if the controller is failed 1299 */ 1300 if (nvme_should_reset(dev, csts)) { 1301 nvme_warn_reset(dev, csts); 1302 nvme_dev_disable(dev, false); 1303 nvme_reset_ctrl(&dev->ctrl); 1304 return BLK_EH_DONE; 1305 } 1306 1307 /* 1308 * Did we miss an interrupt? 1309 */ 1310 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1311 nvme_poll(req->mq_hctx, NULL); 1312 else 1313 nvme_poll_irqdisable(nvmeq); 1314 1315 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { 1316 dev_warn(dev->ctrl.device, 1317 "I/O %d QID %d timeout, completion polled\n", 1318 req->tag, nvmeq->qid); 1319 return BLK_EH_DONE; 1320 } 1321 1322 /* 1323 * Shutdown immediately if controller times out while starting. The 1324 * reset work will see the pci device disabled when it gets the forced 1325 * cancellation error. All outstanding requests are completed on 1326 * shutdown, so we return BLK_EH_DONE. 1327 */ 1328 switch (dev->ctrl.state) { 1329 case NVME_CTRL_CONNECTING: 1330 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1331 fallthrough; 1332 case NVME_CTRL_DELETING: 1333 dev_warn_ratelimited(dev->ctrl.device, 1334 "I/O %d QID %d timeout, disable controller\n", 1335 req->tag, nvmeq->qid); 1336 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1337 nvme_dev_disable(dev, true); 1338 return BLK_EH_DONE; 1339 case NVME_CTRL_RESETTING: 1340 return BLK_EH_RESET_TIMER; 1341 default: 1342 break; 1343 } 1344 1345 /* 1346 * Shutdown the controller immediately and schedule a reset if the 1347 * command was already aborted once before and still hasn't been 1348 * returned to the driver, or if this is the admin queue. 1349 */ 1350 if (!nvmeq->qid || iod->aborted) { 1351 dev_warn(dev->ctrl.device, 1352 "I/O %d QID %d timeout, reset controller\n", 1353 req->tag, nvmeq->qid); 1354 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1355 nvme_dev_disable(dev, false); 1356 nvme_reset_ctrl(&dev->ctrl); 1357 1358 return BLK_EH_DONE; 1359 } 1360 1361 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1362 atomic_inc(&dev->ctrl.abort_limit); 1363 return BLK_EH_RESET_TIMER; 1364 } 1365 iod->aborted = true; 1366 1367 cmd.abort.opcode = nvme_admin_abort_cmd; 1368 cmd.abort.cid = nvme_cid(req); 1369 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1370 1371 dev_warn(nvmeq->dev->ctrl.device, 1372 "I/O %d (%s) QID %d timeout, aborting\n", 1373 req->tag, 1374 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 1375 nvmeq->qid); 1376 1377 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 1378 BLK_MQ_REQ_NOWAIT); 1379 if (IS_ERR(abort_req)) { 1380 atomic_inc(&dev->ctrl.abort_limit); 1381 return BLK_EH_RESET_TIMER; 1382 } 1383 nvme_init_request(abort_req, &cmd); 1384 1385 abort_req->end_io = abort_endio; 1386 abort_req->end_io_data = NULL; 1387 blk_execute_rq_nowait(abort_req, false); 1388 1389 /* 1390 * The aborted req will be completed on receiving the abort req. 1391 * We enable the timer again. If hit twice, it'll cause a device reset, 1392 * as the device then is in a faulty state. 1393 */ 1394 return BLK_EH_RESET_TIMER; 1395 } 1396 1397 static void nvme_free_queue(struct nvme_queue *nvmeq) 1398 { 1399 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1400 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1401 if (!nvmeq->sq_cmds) 1402 return; 1403 1404 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1405 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1406 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1407 } else { 1408 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1409 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1410 } 1411 } 1412 1413 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1414 { 1415 int i; 1416 1417 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1418 dev->ctrl.queue_count--; 1419 nvme_free_queue(&dev->queues[i]); 1420 } 1421 } 1422 1423 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid) 1424 { 1425 struct nvme_queue *nvmeq = &dev->queues[qid]; 1426 1427 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1428 return; 1429 1430 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1431 mb(); 1432 1433 nvmeq->dev->online_queues--; 1434 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1435 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 1436 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1437 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); 1438 } 1439 1440 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1441 { 1442 int i; 1443 1444 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1445 nvme_suspend_queue(dev, i); 1446 } 1447 1448 /* 1449 * Called only on a device that has been disabled and after all other threads 1450 * that can check this device's completion queues have synced, except 1451 * nvme_poll(). This is the last chance for the driver to see a natural 1452 * completion before nvme_cancel_request() terminates all incomplete requests. 1453 */ 1454 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1455 { 1456 int i; 1457 1458 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1459 spin_lock(&dev->queues[i].cq_poll_lock); 1460 nvme_poll_cq(&dev->queues[i], NULL); 1461 spin_unlock(&dev->queues[i].cq_poll_lock); 1462 } 1463 } 1464 1465 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1466 int entry_size) 1467 { 1468 int q_depth = dev->q_depth; 1469 unsigned q_size_aligned = roundup(q_depth * entry_size, 1470 NVME_CTRL_PAGE_SIZE); 1471 1472 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1473 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1474 1475 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1476 q_depth = div_u64(mem_per_q, entry_size); 1477 1478 /* 1479 * Ensure the reduced q_depth is above some threshold where it 1480 * would be better to map queues in system memory with the 1481 * original depth 1482 */ 1483 if (q_depth < 64) 1484 return -ENOMEM; 1485 } 1486 1487 return q_depth; 1488 } 1489 1490 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1491 int qid) 1492 { 1493 struct pci_dev *pdev = to_pci_dev(dev->dev); 1494 1495 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1496 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1497 if (nvmeq->sq_cmds) { 1498 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1499 nvmeq->sq_cmds); 1500 if (nvmeq->sq_dma_addr) { 1501 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1502 return 0; 1503 } 1504 1505 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1506 } 1507 } 1508 1509 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1510 &nvmeq->sq_dma_addr, GFP_KERNEL); 1511 if (!nvmeq->sq_cmds) 1512 return -ENOMEM; 1513 return 0; 1514 } 1515 1516 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1517 { 1518 struct nvme_queue *nvmeq = &dev->queues[qid]; 1519 1520 if (dev->ctrl.queue_count > qid) 1521 return 0; 1522 1523 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1524 nvmeq->q_depth = depth; 1525 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1526 &nvmeq->cq_dma_addr, GFP_KERNEL); 1527 if (!nvmeq->cqes) 1528 goto free_nvmeq; 1529 1530 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1531 goto free_cqdma; 1532 1533 nvmeq->dev = dev; 1534 spin_lock_init(&nvmeq->sq_lock); 1535 spin_lock_init(&nvmeq->cq_poll_lock); 1536 nvmeq->cq_head = 0; 1537 nvmeq->cq_phase = 1; 1538 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1539 nvmeq->qid = qid; 1540 dev->ctrl.queue_count++; 1541 1542 return 0; 1543 1544 free_cqdma: 1545 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1546 nvmeq->cq_dma_addr); 1547 free_nvmeq: 1548 return -ENOMEM; 1549 } 1550 1551 static int queue_request_irq(struct nvme_queue *nvmeq) 1552 { 1553 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1554 int nr = nvmeq->dev->ctrl.instance; 1555 1556 if (use_threaded_interrupts) { 1557 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1558 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1559 } else { 1560 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1561 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1562 } 1563 } 1564 1565 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1566 { 1567 struct nvme_dev *dev = nvmeq->dev; 1568 1569 nvmeq->sq_tail = 0; 1570 nvmeq->last_sq_tail = 0; 1571 nvmeq->cq_head = 0; 1572 nvmeq->cq_phase = 1; 1573 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1574 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1575 nvme_dbbuf_init(dev, nvmeq, qid); 1576 dev->online_queues++; 1577 wmb(); /* ensure the first interrupt sees the initialization */ 1578 } 1579 1580 /* 1581 * Try getting shutdown_lock while setting up IO queues. 1582 */ 1583 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1584 { 1585 /* 1586 * Give up if the lock is being held by nvme_dev_disable. 1587 */ 1588 if (!mutex_trylock(&dev->shutdown_lock)) 1589 return -ENODEV; 1590 1591 /* 1592 * Controller is in wrong state, fail early. 1593 */ 1594 if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1595 mutex_unlock(&dev->shutdown_lock); 1596 return -ENODEV; 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1603 { 1604 struct nvme_dev *dev = nvmeq->dev; 1605 int result; 1606 u16 vector = 0; 1607 1608 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1609 1610 /* 1611 * A queue's vector matches the queue identifier unless the controller 1612 * has only one vector available. 1613 */ 1614 if (!polled) 1615 vector = dev->num_vecs == 1 ? 0 : qid; 1616 else 1617 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1618 1619 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1620 if (result) 1621 return result; 1622 1623 result = adapter_alloc_sq(dev, qid, nvmeq); 1624 if (result < 0) 1625 return result; 1626 if (result) 1627 goto release_cq; 1628 1629 nvmeq->cq_vector = vector; 1630 1631 result = nvme_setup_io_queues_trylock(dev); 1632 if (result) 1633 return result; 1634 nvme_init_queue(nvmeq, qid); 1635 if (!polled) { 1636 result = queue_request_irq(nvmeq); 1637 if (result < 0) 1638 goto release_sq; 1639 } 1640 1641 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1642 mutex_unlock(&dev->shutdown_lock); 1643 return result; 1644 1645 release_sq: 1646 dev->online_queues--; 1647 mutex_unlock(&dev->shutdown_lock); 1648 adapter_delete_sq(dev, qid); 1649 release_cq: 1650 adapter_delete_cq(dev, qid); 1651 return result; 1652 } 1653 1654 static const struct blk_mq_ops nvme_mq_admin_ops = { 1655 .queue_rq = nvme_queue_rq, 1656 .complete = nvme_pci_complete_rq, 1657 .init_hctx = nvme_admin_init_hctx, 1658 .init_request = nvme_pci_init_request, 1659 .timeout = nvme_timeout, 1660 }; 1661 1662 static const struct blk_mq_ops nvme_mq_ops = { 1663 .queue_rq = nvme_queue_rq, 1664 .queue_rqs = nvme_queue_rqs, 1665 .complete = nvme_pci_complete_rq, 1666 .commit_rqs = nvme_commit_rqs, 1667 .init_hctx = nvme_init_hctx, 1668 .init_request = nvme_pci_init_request, 1669 .map_queues = nvme_pci_map_queues, 1670 .timeout = nvme_timeout, 1671 .poll = nvme_poll, 1672 }; 1673 1674 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1675 { 1676 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1677 /* 1678 * If the controller was reset during removal, it's possible 1679 * user requests may be waiting on a stopped queue. Start the 1680 * queue to flush these to completion. 1681 */ 1682 nvme_unquiesce_admin_queue(&dev->ctrl); 1683 nvme_remove_admin_tag_set(&dev->ctrl); 1684 } 1685 } 1686 1687 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1688 { 1689 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1690 } 1691 1692 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1693 { 1694 struct pci_dev *pdev = to_pci_dev(dev->dev); 1695 1696 if (size <= dev->bar_mapped_size) 1697 return 0; 1698 if (size > pci_resource_len(pdev, 0)) 1699 return -ENOMEM; 1700 if (dev->bar) 1701 iounmap(dev->bar); 1702 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1703 if (!dev->bar) { 1704 dev->bar_mapped_size = 0; 1705 return -ENOMEM; 1706 } 1707 dev->bar_mapped_size = size; 1708 dev->dbs = dev->bar + NVME_REG_DBS; 1709 1710 return 0; 1711 } 1712 1713 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1714 { 1715 int result; 1716 u32 aqa; 1717 struct nvme_queue *nvmeq; 1718 1719 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1720 if (result < 0) 1721 return result; 1722 1723 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1724 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1725 1726 if (dev->subsystem && 1727 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1728 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1729 1730 /* 1731 * If the device has been passed off to us in an enabled state, just 1732 * clear the enabled bit. The spec says we should set the 'shutdown 1733 * notification bits', but doing so may cause the device to complete 1734 * commands to the admin queue ... and we don't know what memory that 1735 * might be pointing at! 1736 */ 1737 result = nvme_disable_ctrl(&dev->ctrl, false); 1738 if (result < 0) 1739 return result; 1740 1741 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1742 if (result) 1743 return result; 1744 1745 dev->ctrl.numa_node = dev_to_node(dev->dev); 1746 1747 nvmeq = &dev->queues[0]; 1748 aqa = nvmeq->q_depth - 1; 1749 aqa |= aqa << 16; 1750 1751 writel(aqa, dev->bar + NVME_REG_AQA); 1752 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1753 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1754 1755 result = nvme_enable_ctrl(&dev->ctrl); 1756 if (result) 1757 return result; 1758 1759 nvmeq->cq_vector = 0; 1760 nvme_init_queue(nvmeq, 0); 1761 result = queue_request_irq(nvmeq); 1762 if (result) { 1763 dev->online_queues--; 1764 return result; 1765 } 1766 1767 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1768 return result; 1769 } 1770 1771 static int nvme_create_io_queues(struct nvme_dev *dev) 1772 { 1773 unsigned i, max, rw_queues; 1774 int ret = 0; 1775 1776 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1777 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1778 ret = -ENOMEM; 1779 break; 1780 } 1781 } 1782 1783 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1784 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1785 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1786 dev->io_queues[HCTX_TYPE_READ]; 1787 } else { 1788 rw_queues = max; 1789 } 1790 1791 for (i = dev->online_queues; i <= max; i++) { 1792 bool polled = i > rw_queues; 1793 1794 ret = nvme_create_queue(&dev->queues[i], i, polled); 1795 if (ret) 1796 break; 1797 } 1798 1799 /* 1800 * Ignore failing Create SQ/CQ commands, we can continue with less 1801 * than the desired amount of queues, and even a controller without 1802 * I/O queues can still be used to issue admin commands. This might 1803 * be useful to upgrade a buggy firmware for example. 1804 */ 1805 return ret >= 0 ? 0 : ret; 1806 } 1807 1808 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1809 { 1810 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1811 1812 return 1ULL << (12 + 4 * szu); 1813 } 1814 1815 static u32 nvme_cmb_size(struct nvme_dev *dev) 1816 { 1817 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1818 } 1819 1820 static void nvme_map_cmb(struct nvme_dev *dev) 1821 { 1822 u64 size, offset; 1823 resource_size_t bar_size; 1824 struct pci_dev *pdev = to_pci_dev(dev->dev); 1825 int bar; 1826 1827 if (dev->cmb_size) 1828 return; 1829 1830 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1831 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1832 1833 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1834 if (!dev->cmbsz) 1835 return; 1836 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1837 1838 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1839 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1840 bar = NVME_CMB_BIR(dev->cmbloc); 1841 bar_size = pci_resource_len(pdev, bar); 1842 1843 if (offset > bar_size) 1844 return; 1845 1846 /* 1847 * Tell the controller about the host side address mapping the CMB, 1848 * and enable CMB decoding for the NVMe 1.4+ scheme: 1849 */ 1850 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1851 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1852 (pci_bus_address(pdev, bar) + offset), 1853 dev->bar + NVME_REG_CMBMSC); 1854 } 1855 1856 /* 1857 * Controllers may support a CMB size larger than their BAR, 1858 * for example, due to being behind a bridge. Reduce the CMB to 1859 * the reported size of the BAR 1860 */ 1861 if (size > bar_size - offset) 1862 size = bar_size - offset; 1863 1864 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1865 dev_warn(dev->ctrl.device, 1866 "failed to register the CMB\n"); 1867 return; 1868 } 1869 1870 dev->cmb_size = size; 1871 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1872 1873 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1874 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1875 pci_p2pmem_publish(pdev, true); 1876 } 1877 1878 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1879 { 1880 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1881 u64 dma_addr = dev->host_mem_descs_dma; 1882 struct nvme_command c = { }; 1883 int ret; 1884 1885 c.features.opcode = nvme_admin_set_features; 1886 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1887 c.features.dword11 = cpu_to_le32(bits); 1888 c.features.dword12 = cpu_to_le32(host_mem_size); 1889 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1890 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1891 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1892 1893 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1894 if (ret) { 1895 dev_warn(dev->ctrl.device, 1896 "failed to set host mem (err %d, flags %#x).\n", 1897 ret, bits); 1898 } else 1899 dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1900 1901 return ret; 1902 } 1903 1904 static void nvme_free_host_mem(struct nvme_dev *dev) 1905 { 1906 int i; 1907 1908 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1909 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1910 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 1911 1912 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1913 le64_to_cpu(desc->addr), 1914 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1915 } 1916 1917 kfree(dev->host_mem_desc_bufs); 1918 dev->host_mem_desc_bufs = NULL; 1919 dma_free_coherent(dev->dev, 1920 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1921 dev->host_mem_descs, dev->host_mem_descs_dma); 1922 dev->host_mem_descs = NULL; 1923 dev->nr_host_mem_descs = 0; 1924 } 1925 1926 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1927 u32 chunk_size) 1928 { 1929 struct nvme_host_mem_buf_desc *descs; 1930 u32 max_entries, len; 1931 dma_addr_t descs_dma; 1932 int i = 0; 1933 void **bufs; 1934 u64 size, tmp; 1935 1936 tmp = (preferred + chunk_size - 1); 1937 do_div(tmp, chunk_size); 1938 max_entries = tmp; 1939 1940 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1941 max_entries = dev->ctrl.hmmaxd; 1942 1943 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1944 &descs_dma, GFP_KERNEL); 1945 if (!descs) 1946 goto out; 1947 1948 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1949 if (!bufs) 1950 goto out_free_descs; 1951 1952 for (size = 0; size < preferred && i < max_entries; size += len) { 1953 dma_addr_t dma_addr; 1954 1955 len = min_t(u64, chunk_size, preferred - size); 1956 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1957 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1958 if (!bufs[i]) 1959 break; 1960 1961 descs[i].addr = cpu_to_le64(dma_addr); 1962 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 1963 i++; 1964 } 1965 1966 if (!size) 1967 goto out_free_bufs; 1968 1969 dev->nr_host_mem_descs = i; 1970 dev->host_mem_size = size; 1971 dev->host_mem_descs = descs; 1972 dev->host_mem_descs_dma = descs_dma; 1973 dev->host_mem_desc_bufs = bufs; 1974 return 0; 1975 1976 out_free_bufs: 1977 while (--i >= 0) { 1978 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 1979 1980 dma_free_attrs(dev->dev, size, bufs[i], 1981 le64_to_cpu(descs[i].addr), 1982 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1983 } 1984 1985 kfree(bufs); 1986 out_free_descs: 1987 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1988 descs_dma); 1989 out: 1990 dev->host_mem_descs = NULL; 1991 return -ENOMEM; 1992 } 1993 1994 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1995 { 1996 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1997 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1998 u64 chunk_size; 1999 2000 /* start big and work our way down */ 2001 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2002 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2003 if (!min || dev->host_mem_size >= min) 2004 return 0; 2005 nvme_free_host_mem(dev); 2006 } 2007 } 2008 2009 return -ENOMEM; 2010 } 2011 2012 static int nvme_setup_host_mem(struct nvme_dev *dev) 2013 { 2014 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2015 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2016 u64 min = (u64)dev->ctrl.hmmin * 4096; 2017 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2018 int ret; 2019 2020 if (!dev->ctrl.hmpre) 2021 return 0; 2022 2023 preferred = min(preferred, max); 2024 if (min > max) { 2025 dev_warn(dev->ctrl.device, 2026 "min host memory (%lld MiB) above limit (%d MiB).\n", 2027 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2028 nvme_free_host_mem(dev); 2029 return 0; 2030 } 2031 2032 /* 2033 * If we already have a buffer allocated check if we can reuse it. 2034 */ 2035 if (dev->host_mem_descs) { 2036 if (dev->host_mem_size >= min) 2037 enable_bits |= NVME_HOST_MEM_RETURN; 2038 else 2039 nvme_free_host_mem(dev); 2040 } 2041 2042 if (!dev->host_mem_descs) { 2043 if (nvme_alloc_host_mem(dev, min, preferred)) { 2044 dev_warn(dev->ctrl.device, 2045 "failed to allocate host memory buffer.\n"); 2046 return 0; /* controller must work without HMB */ 2047 } 2048 2049 dev_info(dev->ctrl.device, 2050 "allocated %lld MiB host memory buffer.\n", 2051 dev->host_mem_size >> ilog2(SZ_1M)); 2052 } 2053 2054 ret = nvme_set_host_mem(dev, enable_bits); 2055 if (ret) 2056 nvme_free_host_mem(dev); 2057 return ret; 2058 } 2059 2060 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 2061 char *buf) 2062 { 2063 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2064 2065 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 2066 ndev->cmbloc, ndev->cmbsz); 2067 } 2068 static DEVICE_ATTR_RO(cmb); 2069 2070 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 2071 char *buf) 2072 { 2073 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2074 2075 return sysfs_emit(buf, "%u\n", ndev->cmbloc); 2076 } 2077 static DEVICE_ATTR_RO(cmbloc); 2078 2079 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 2080 char *buf) 2081 { 2082 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2083 2084 return sysfs_emit(buf, "%u\n", ndev->cmbsz); 2085 } 2086 static DEVICE_ATTR_RO(cmbsz); 2087 2088 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2089 char *buf) 2090 { 2091 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2092 2093 return sysfs_emit(buf, "%d\n", ndev->hmb); 2094 } 2095 2096 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2097 const char *buf, size_t count) 2098 { 2099 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2100 bool new; 2101 int ret; 2102 2103 if (kstrtobool(buf, &new) < 0) 2104 return -EINVAL; 2105 2106 if (new == ndev->hmb) 2107 return count; 2108 2109 if (new) { 2110 ret = nvme_setup_host_mem(ndev); 2111 } else { 2112 ret = nvme_set_host_mem(ndev, 0); 2113 if (!ret) 2114 nvme_free_host_mem(ndev); 2115 } 2116 2117 if (ret < 0) 2118 return ret; 2119 2120 return count; 2121 } 2122 static DEVICE_ATTR_RW(hmb); 2123 2124 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 2125 struct attribute *a, int n) 2126 { 2127 struct nvme_ctrl *ctrl = 2128 dev_get_drvdata(container_of(kobj, struct device, kobj)); 2129 struct nvme_dev *dev = to_nvme_dev(ctrl); 2130 2131 if (a == &dev_attr_cmb.attr || 2132 a == &dev_attr_cmbloc.attr || 2133 a == &dev_attr_cmbsz.attr) { 2134 if (!dev->cmbsz) 2135 return 0; 2136 } 2137 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2138 return 0; 2139 2140 return a->mode; 2141 } 2142 2143 static struct attribute *nvme_pci_attrs[] = { 2144 &dev_attr_cmb.attr, 2145 &dev_attr_cmbloc.attr, 2146 &dev_attr_cmbsz.attr, 2147 &dev_attr_hmb.attr, 2148 NULL, 2149 }; 2150 2151 static const struct attribute_group nvme_pci_dev_attrs_group = { 2152 .attrs = nvme_pci_attrs, 2153 .is_visible = nvme_pci_attrs_are_visible, 2154 }; 2155 2156 static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 2157 &nvme_dev_attrs_group, 2158 &nvme_pci_dev_attrs_group, 2159 NULL, 2160 }; 2161 2162 /* 2163 * nirqs is the number of interrupts available for write and read 2164 * queues. The core already reserved an interrupt for the admin queue. 2165 */ 2166 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2167 { 2168 struct nvme_dev *dev = affd->priv; 2169 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2170 2171 /* 2172 * If there is no interrupt available for queues, ensure that 2173 * the default queue is set to 1. The affinity set size is 2174 * also set to one, but the irq core ignores it for this case. 2175 * 2176 * If only one interrupt is available or 'write_queue' == 0, combine 2177 * write and read queues. 2178 * 2179 * If 'write_queues' > 0, ensure it leaves room for at least one read 2180 * queue. 2181 */ 2182 if (!nrirqs) { 2183 nrirqs = 1; 2184 nr_read_queues = 0; 2185 } else if (nrirqs == 1 || !nr_write_queues) { 2186 nr_read_queues = 0; 2187 } else if (nr_write_queues >= nrirqs) { 2188 nr_read_queues = 1; 2189 } else { 2190 nr_read_queues = nrirqs - nr_write_queues; 2191 } 2192 2193 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2194 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2195 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2196 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2197 affd->nr_sets = nr_read_queues ? 2 : 1; 2198 } 2199 2200 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2201 { 2202 struct pci_dev *pdev = to_pci_dev(dev->dev); 2203 struct irq_affinity affd = { 2204 .pre_vectors = 1, 2205 .calc_sets = nvme_calc_irq_sets, 2206 .priv = dev, 2207 }; 2208 unsigned int irq_queues, poll_queues; 2209 2210 /* 2211 * Poll queues don't need interrupts, but we need at least one I/O queue 2212 * left over for non-polled I/O. 2213 */ 2214 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2215 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2216 2217 /* 2218 * Initialize for the single interrupt case, will be updated in 2219 * nvme_calc_irq_sets(). 2220 */ 2221 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2222 dev->io_queues[HCTX_TYPE_READ] = 0; 2223 2224 /* 2225 * We need interrupts for the admin queue and each non-polled I/O queue, 2226 * but some Apple controllers require all queues to use the first 2227 * vector. 2228 */ 2229 irq_queues = 1; 2230 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2231 irq_queues += (nr_io_queues - poll_queues); 2232 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2233 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2234 } 2235 2236 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2237 { 2238 /* 2239 * If tags are shared with admin queue (Apple bug), then 2240 * make sure we only use one IO queue. 2241 */ 2242 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2243 return 1; 2244 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2245 } 2246 2247 static int nvme_setup_io_queues(struct nvme_dev *dev) 2248 { 2249 struct nvme_queue *adminq = &dev->queues[0]; 2250 struct pci_dev *pdev = to_pci_dev(dev->dev); 2251 unsigned int nr_io_queues; 2252 unsigned long size; 2253 int result; 2254 2255 /* 2256 * Sample the module parameters once at reset time so that we have 2257 * stable values to work with. 2258 */ 2259 dev->nr_write_queues = write_queues; 2260 dev->nr_poll_queues = poll_queues; 2261 2262 nr_io_queues = dev->nr_allocated_queues - 1; 2263 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2264 if (result < 0) 2265 return result; 2266 2267 if (nr_io_queues == 0) 2268 return 0; 2269 2270 /* 2271 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2272 * from set to unset. If there is a window to it is truely freed, 2273 * pci_free_irq_vectors() jumping into this window will crash. 2274 * And take lock to avoid racing with pci_free_irq_vectors() in 2275 * nvme_dev_disable() path. 2276 */ 2277 result = nvme_setup_io_queues_trylock(dev); 2278 if (result) 2279 return result; 2280 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2281 pci_free_irq(pdev, 0, adminq); 2282 2283 if (dev->cmb_use_sqes) { 2284 result = nvme_cmb_qdepth(dev, nr_io_queues, 2285 sizeof(struct nvme_command)); 2286 if (result > 0) { 2287 dev->q_depth = result; 2288 dev->ctrl.sqsize = result - 1; 2289 } else { 2290 dev->cmb_use_sqes = false; 2291 } 2292 } 2293 2294 do { 2295 size = db_bar_size(dev, nr_io_queues); 2296 result = nvme_remap_bar(dev, size); 2297 if (!result) 2298 break; 2299 if (!--nr_io_queues) { 2300 result = -ENOMEM; 2301 goto out_unlock; 2302 } 2303 } while (1); 2304 adminq->q_db = dev->dbs; 2305 2306 retry: 2307 /* Deregister the admin queue's interrupt */ 2308 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2309 pci_free_irq(pdev, 0, adminq); 2310 2311 /* 2312 * If we enable msix early due to not intx, disable it again before 2313 * setting up the full range we need. 2314 */ 2315 pci_free_irq_vectors(pdev); 2316 2317 result = nvme_setup_irqs(dev, nr_io_queues); 2318 if (result <= 0) { 2319 result = -EIO; 2320 goto out_unlock; 2321 } 2322 2323 dev->num_vecs = result; 2324 result = max(result - 1, 1); 2325 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2326 2327 /* 2328 * Should investigate if there's a performance win from allocating 2329 * more queues than interrupt vectors; it might allow the submission 2330 * path to scale better, even if the receive path is limited by the 2331 * number of interrupts. 2332 */ 2333 result = queue_request_irq(adminq); 2334 if (result) 2335 goto out_unlock; 2336 set_bit(NVMEQ_ENABLED, &adminq->flags); 2337 mutex_unlock(&dev->shutdown_lock); 2338 2339 result = nvme_create_io_queues(dev); 2340 if (result || dev->online_queues < 2) 2341 return result; 2342 2343 if (dev->online_queues - 1 < dev->max_qid) { 2344 nr_io_queues = dev->online_queues - 1; 2345 nvme_delete_io_queues(dev); 2346 result = nvme_setup_io_queues_trylock(dev); 2347 if (result) 2348 return result; 2349 nvme_suspend_io_queues(dev); 2350 goto retry; 2351 } 2352 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2353 dev->io_queues[HCTX_TYPE_DEFAULT], 2354 dev->io_queues[HCTX_TYPE_READ], 2355 dev->io_queues[HCTX_TYPE_POLL]); 2356 return 0; 2357 out_unlock: 2358 mutex_unlock(&dev->shutdown_lock); 2359 return result; 2360 } 2361 2362 static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2363 blk_status_t error) 2364 { 2365 struct nvme_queue *nvmeq = req->end_io_data; 2366 2367 blk_mq_free_request(req); 2368 complete(&nvmeq->delete_done); 2369 return RQ_END_IO_NONE; 2370 } 2371 2372 static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2373 blk_status_t error) 2374 { 2375 struct nvme_queue *nvmeq = req->end_io_data; 2376 2377 if (error) 2378 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2379 2380 return nvme_del_queue_end(req, error); 2381 } 2382 2383 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2384 { 2385 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2386 struct request *req; 2387 struct nvme_command cmd = { }; 2388 2389 cmd.delete_queue.opcode = opcode; 2390 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2391 2392 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2393 if (IS_ERR(req)) 2394 return PTR_ERR(req); 2395 nvme_init_request(req, &cmd); 2396 2397 if (opcode == nvme_admin_delete_cq) 2398 req->end_io = nvme_del_cq_end; 2399 else 2400 req->end_io = nvme_del_queue_end; 2401 req->end_io_data = nvmeq; 2402 2403 init_completion(&nvmeq->delete_done); 2404 blk_execute_rq_nowait(req, false); 2405 return 0; 2406 } 2407 2408 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode) 2409 { 2410 int nr_queues = dev->online_queues - 1, sent = 0; 2411 unsigned long timeout; 2412 2413 retry: 2414 timeout = NVME_ADMIN_TIMEOUT; 2415 while (nr_queues > 0) { 2416 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2417 break; 2418 nr_queues--; 2419 sent++; 2420 } 2421 while (sent) { 2422 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2423 2424 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2425 timeout); 2426 if (timeout == 0) 2427 return false; 2428 2429 sent--; 2430 if (nr_queues) 2431 goto retry; 2432 } 2433 return true; 2434 } 2435 2436 static void nvme_delete_io_queues(struct nvme_dev *dev) 2437 { 2438 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq)) 2439 __nvme_delete_io_queues(dev, nvme_admin_delete_cq); 2440 } 2441 2442 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev) 2443 { 2444 if (dev->io_queues[HCTX_TYPE_POLL]) 2445 return 3; 2446 if (dev->io_queues[HCTX_TYPE_READ]) 2447 return 2; 2448 return 1; 2449 } 2450 2451 static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 2452 { 2453 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2454 /* free previously allocated queues that are no longer usable */ 2455 nvme_free_queues(dev, dev->online_queues); 2456 } 2457 2458 static int nvme_pci_enable(struct nvme_dev *dev) 2459 { 2460 int result = -ENOMEM; 2461 struct pci_dev *pdev = to_pci_dev(dev->dev); 2462 int dma_address_bits = 64; 2463 2464 if (pci_enable_device_mem(pdev)) 2465 return result; 2466 2467 pci_set_master(pdev); 2468 2469 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 2470 dma_address_bits = 48; 2471 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 2472 goto disable; 2473 2474 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2475 result = -ENODEV; 2476 goto disable; 2477 } 2478 2479 /* 2480 * Some devices and/or platforms don't advertise or work with INTx 2481 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2482 * adjust this later. 2483 */ 2484 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2485 if (result < 0) 2486 goto disable; 2487 2488 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2489 2490 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2491 io_queue_depth); 2492 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2493 dev->dbs = dev->bar + 4096; 2494 2495 /* 2496 * Some Apple controllers require a non-standard SQE size. 2497 * Interestingly they also seem to ignore the CC:IOSQES register 2498 * so we don't bother updating it here. 2499 */ 2500 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2501 dev->io_sqes = 7; 2502 else 2503 dev->io_sqes = NVME_NVM_IOSQES; 2504 2505 /* 2506 * Temporary fix for the Apple controller found in the MacBook8,1 and 2507 * some MacBook7,1 to avoid controller resets and data loss. 2508 */ 2509 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2510 dev->q_depth = 2; 2511 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2512 "set queue depth=%u to work around controller resets\n", 2513 dev->q_depth); 2514 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2515 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2516 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2517 dev->q_depth = 64; 2518 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2519 "set queue depth=%u\n", dev->q_depth); 2520 } 2521 2522 /* 2523 * Controllers with the shared tags quirk need the IO queue to be 2524 * big enough so that we get 32 tags for the admin queue 2525 */ 2526 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2527 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2528 dev->q_depth = NVME_AQ_DEPTH + 2; 2529 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2530 dev->q_depth); 2531 } 2532 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2533 2534 nvme_map_cmb(dev); 2535 2536 pci_enable_pcie_error_reporting(pdev); 2537 pci_save_state(pdev); 2538 2539 result = nvme_pci_configure_admin_queue(dev); 2540 if (result) 2541 goto free_irq; 2542 return result; 2543 2544 free_irq: 2545 pci_free_irq_vectors(pdev); 2546 disable: 2547 pci_disable_device(pdev); 2548 return result; 2549 } 2550 2551 static void nvme_dev_unmap(struct nvme_dev *dev) 2552 { 2553 if (dev->bar) 2554 iounmap(dev->bar); 2555 pci_release_mem_regions(to_pci_dev(dev->dev)); 2556 } 2557 2558 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev) 2559 { 2560 struct pci_dev *pdev = to_pci_dev(dev->dev); 2561 u32 csts; 2562 2563 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev)) 2564 return true; 2565 if (pdev->error_state != pci_channel_io_normal) 2566 return true; 2567 2568 csts = readl(dev->bar + NVME_REG_CSTS); 2569 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY); 2570 } 2571 2572 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2573 { 2574 struct pci_dev *pdev = to_pci_dev(dev->dev); 2575 bool dead; 2576 2577 mutex_lock(&dev->shutdown_lock); 2578 dead = nvme_pci_ctrl_is_dead(dev); 2579 if (dev->ctrl.state == NVME_CTRL_LIVE || 2580 dev->ctrl.state == NVME_CTRL_RESETTING) { 2581 if (pci_is_enabled(pdev)) 2582 nvme_start_freeze(&dev->ctrl); 2583 /* 2584 * Give the controller a chance to complete all entered requests 2585 * if doing a safe shutdown. 2586 */ 2587 if (!dead && shutdown) 2588 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2589 } 2590 2591 nvme_quiesce_io_queues(&dev->ctrl); 2592 2593 if (!dead && dev->ctrl.queue_count > 0) { 2594 nvme_delete_io_queues(dev); 2595 nvme_disable_ctrl(&dev->ctrl, shutdown); 2596 nvme_poll_irqdisable(&dev->queues[0]); 2597 } 2598 nvme_suspend_io_queues(dev); 2599 nvme_suspend_queue(dev, 0); 2600 pci_free_irq_vectors(pdev); 2601 if (pci_is_enabled(pdev)) { 2602 pci_disable_pcie_error_reporting(pdev); 2603 pci_disable_device(pdev); 2604 } 2605 nvme_reap_pending_cqes(dev); 2606 2607 nvme_cancel_tagset(&dev->ctrl); 2608 nvme_cancel_admin_tagset(&dev->ctrl); 2609 2610 /* 2611 * The driver will not be starting up queues again if shutting down so 2612 * must flush all entered requests to their failed completion to avoid 2613 * deadlocking blk-mq hot-cpu notifier. 2614 */ 2615 if (shutdown) { 2616 nvme_unquiesce_io_queues(&dev->ctrl); 2617 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2618 nvme_unquiesce_admin_queue(&dev->ctrl); 2619 } 2620 mutex_unlock(&dev->shutdown_lock); 2621 } 2622 2623 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2624 { 2625 if (!nvme_wait_reset(&dev->ctrl)) 2626 return -EBUSY; 2627 nvme_dev_disable(dev, shutdown); 2628 return 0; 2629 } 2630 2631 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2632 { 2633 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2634 NVME_CTRL_PAGE_SIZE, 2635 NVME_CTRL_PAGE_SIZE, 0); 2636 if (!dev->prp_page_pool) 2637 return -ENOMEM; 2638 2639 /* Optimisation for I/Os between 4k and 128k */ 2640 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2641 256, 256, 0); 2642 if (!dev->prp_small_pool) { 2643 dma_pool_destroy(dev->prp_page_pool); 2644 return -ENOMEM; 2645 } 2646 return 0; 2647 } 2648 2649 static void nvme_release_prp_pools(struct nvme_dev *dev) 2650 { 2651 dma_pool_destroy(dev->prp_page_pool); 2652 dma_pool_destroy(dev->prp_small_pool); 2653 } 2654 2655 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2656 { 2657 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS; 2658 2659 dev->iod_mempool = mempool_create_node(1, 2660 mempool_kmalloc, mempool_kfree, 2661 (void *)alloc_size, GFP_KERNEL, 2662 dev_to_node(dev->dev)); 2663 if (!dev->iod_mempool) 2664 return -ENOMEM; 2665 return 0; 2666 } 2667 2668 static void nvme_free_tagset(struct nvme_dev *dev) 2669 { 2670 if (dev->tagset.tags) 2671 nvme_remove_io_tag_set(&dev->ctrl); 2672 dev->ctrl.tagset = NULL; 2673 } 2674 2675 /* pairs with nvme_pci_alloc_dev */ 2676 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2677 { 2678 struct nvme_dev *dev = to_nvme_dev(ctrl); 2679 2680 nvme_free_tagset(dev); 2681 put_device(dev->dev); 2682 kfree(dev->queues); 2683 kfree(dev); 2684 } 2685 2686 static void nvme_reset_work(struct work_struct *work) 2687 { 2688 struct nvme_dev *dev = 2689 container_of(work, struct nvme_dev, ctrl.reset_work); 2690 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2691 int result; 2692 2693 if (dev->ctrl.state != NVME_CTRL_RESETTING) { 2694 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2695 dev->ctrl.state); 2696 return; 2697 } 2698 2699 /* 2700 * If we're called to reset a live controller first shut it down before 2701 * moving on. 2702 */ 2703 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2704 nvme_dev_disable(dev, false); 2705 nvme_sync_queues(&dev->ctrl); 2706 2707 mutex_lock(&dev->shutdown_lock); 2708 result = nvme_pci_enable(dev); 2709 if (result) 2710 goto out_unlock; 2711 nvme_unquiesce_admin_queue(&dev->ctrl); 2712 mutex_unlock(&dev->shutdown_lock); 2713 2714 /* 2715 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2716 * initializing procedure here. 2717 */ 2718 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2719 dev_warn(dev->ctrl.device, 2720 "failed to mark controller CONNECTING\n"); 2721 result = -EBUSY; 2722 goto out; 2723 } 2724 2725 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2726 if (result) 2727 goto out; 2728 2729 nvme_dbbuf_dma_alloc(dev); 2730 2731 result = nvme_setup_host_mem(dev); 2732 if (result < 0) 2733 goto out; 2734 2735 result = nvme_setup_io_queues(dev); 2736 if (result) 2737 goto out; 2738 2739 /* 2740 * Freeze and update the number of I/O queues as thos might have 2741 * changed. If there are no I/O queues left after this reset, keep the 2742 * controller around but remove all namespaces. 2743 */ 2744 if (dev->online_queues > 1) { 2745 nvme_unquiesce_io_queues(&dev->ctrl); 2746 nvme_wait_freeze(&dev->ctrl); 2747 nvme_pci_update_nr_queues(dev); 2748 nvme_dbbuf_set(dev); 2749 nvme_unfreeze(&dev->ctrl); 2750 } else { 2751 dev_warn(dev->ctrl.device, "IO queues lost\n"); 2752 nvme_mark_namespaces_dead(&dev->ctrl); 2753 nvme_unquiesce_io_queues(&dev->ctrl); 2754 nvme_remove_namespaces(&dev->ctrl); 2755 nvme_free_tagset(dev); 2756 } 2757 2758 /* 2759 * If only admin queue live, keep it to do further investigation or 2760 * recovery. 2761 */ 2762 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2763 dev_warn(dev->ctrl.device, 2764 "failed to mark controller live state\n"); 2765 result = -ENODEV; 2766 goto out; 2767 } 2768 2769 nvme_start_ctrl(&dev->ctrl); 2770 return; 2771 2772 out_unlock: 2773 mutex_unlock(&dev->shutdown_lock); 2774 out: 2775 /* 2776 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2777 * may be holding this pci_dev's device lock. 2778 */ 2779 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2780 result); 2781 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2782 nvme_dev_disable(dev, true); 2783 nvme_mark_namespaces_dead(&dev->ctrl); 2784 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2785 } 2786 2787 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2788 { 2789 *val = readl(to_nvme_dev(ctrl)->bar + off); 2790 return 0; 2791 } 2792 2793 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2794 { 2795 writel(val, to_nvme_dev(ctrl)->bar + off); 2796 return 0; 2797 } 2798 2799 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2800 { 2801 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2802 return 0; 2803 } 2804 2805 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2806 { 2807 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2808 2809 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2810 } 2811 2812 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 2813 { 2814 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2815 struct nvme_subsystem *subsys = ctrl->subsys; 2816 2817 dev_err(ctrl->device, 2818 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 2819 pdev->vendor, pdev->device, 2820 nvme_strlen(subsys->model, sizeof(subsys->model)), 2821 subsys->model, nvme_strlen(subsys->firmware_rev, 2822 sizeof(subsys->firmware_rev)), 2823 subsys->firmware_rev); 2824 } 2825 2826 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 2827 { 2828 struct nvme_dev *dev = to_nvme_dev(ctrl); 2829 2830 return dma_pci_p2pdma_supported(dev->dev); 2831 } 2832 2833 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2834 .name = "pcie", 2835 .module = THIS_MODULE, 2836 .flags = NVME_F_METADATA_SUPPORTED, 2837 .dev_attr_groups = nvme_pci_dev_attr_groups, 2838 .reg_read32 = nvme_pci_reg_read32, 2839 .reg_write32 = nvme_pci_reg_write32, 2840 .reg_read64 = nvme_pci_reg_read64, 2841 .free_ctrl = nvme_pci_free_ctrl, 2842 .submit_async_event = nvme_pci_submit_async_event, 2843 .get_address = nvme_pci_get_address, 2844 .print_device_info = nvme_pci_print_device_info, 2845 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 2846 }; 2847 2848 static int nvme_dev_map(struct nvme_dev *dev) 2849 { 2850 struct pci_dev *pdev = to_pci_dev(dev->dev); 2851 2852 if (pci_request_mem_regions(pdev, "nvme")) 2853 return -ENODEV; 2854 2855 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2856 goto release; 2857 2858 return 0; 2859 release: 2860 pci_release_mem_regions(pdev); 2861 return -ENODEV; 2862 } 2863 2864 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2865 { 2866 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2867 /* 2868 * Several Samsung devices seem to drop off the PCIe bus 2869 * randomly when APST is on and uses the deepest sleep state. 2870 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2871 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2872 * 950 PRO 256GB", but it seems to be restricted to two Dell 2873 * laptops. 2874 */ 2875 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2876 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2877 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2878 return NVME_QUIRK_NO_DEEPEST_PS; 2879 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2880 /* 2881 * Samsung SSD 960 EVO drops off the PCIe bus after system 2882 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2883 * within few minutes after bootup on a Coffee Lake board - 2884 * ASUS PRIME Z370-A 2885 */ 2886 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2887 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2888 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2889 return NVME_QUIRK_NO_APST; 2890 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2891 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2892 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2893 /* 2894 * Forcing to use host managed nvme power settings for 2895 * lowest idle power with quick resume latency on 2896 * Samsung and Toshiba SSDs based on suspend behavior 2897 * on Coffee Lake board for LENOVO C640 2898 */ 2899 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2900 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2901 return NVME_QUIRK_SIMPLE_SUSPEND; 2902 } 2903 2904 return 0; 2905 } 2906 2907 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 2908 const struct pci_device_id *id) 2909 { 2910 unsigned long quirks = id->driver_data; 2911 int node = dev_to_node(&pdev->dev); 2912 struct nvme_dev *dev; 2913 int ret = -ENOMEM; 2914 2915 if (node == NUMA_NO_NODE) 2916 set_dev_node(&pdev->dev, first_memory_node); 2917 2918 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2919 if (!dev) 2920 return NULL; 2921 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2922 mutex_init(&dev->shutdown_lock); 2923 2924 dev->nr_write_queues = write_queues; 2925 dev->nr_poll_queues = poll_queues; 2926 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 2927 dev->queues = kcalloc_node(dev->nr_allocated_queues, 2928 sizeof(struct nvme_queue), GFP_KERNEL, node); 2929 if (!dev->queues) 2930 goto out_free_dev; 2931 2932 dev->dev = get_device(&pdev->dev); 2933 2934 quirks |= check_vendor_combination_bug(pdev); 2935 if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2936 /* 2937 * Some systems use a bios work around to ask for D3 on 2938 * platforms that support kernel managed suspend. 2939 */ 2940 dev_info(&pdev->dev, 2941 "platform quirk: setting simple suspend\n"); 2942 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2943 } 2944 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2945 quirks); 2946 if (ret) 2947 goto out_put_device; 2948 2949 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 2950 dma_set_max_seg_size(&pdev->dev, 0xffffffff); 2951 2952 /* 2953 * Limit the max command size to prevent iod->sg allocations going 2954 * over a single page. 2955 */ 2956 dev->ctrl.max_hw_sectors = min_t(u32, 2957 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 2958 dev->ctrl.max_segments = NVME_MAX_SEGS; 2959 2960 /* 2961 * There is no support for SGLs for metadata (yet), so we are limited to 2962 * a single integrity segment for the separate metadata pointer. 2963 */ 2964 dev->ctrl.max_integrity_segments = 1; 2965 return dev; 2966 2967 out_put_device: 2968 put_device(dev->dev); 2969 kfree(dev->queues); 2970 out_free_dev: 2971 kfree(dev); 2972 return ERR_PTR(ret); 2973 } 2974 2975 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2976 { 2977 struct nvme_dev *dev; 2978 int result = -ENOMEM; 2979 2980 dev = nvme_pci_alloc_dev(pdev, id); 2981 if (!dev) 2982 return -ENOMEM; 2983 2984 result = nvme_dev_map(dev); 2985 if (result) 2986 goto out_uninit_ctrl; 2987 2988 result = nvme_setup_prp_pools(dev); 2989 if (result) 2990 goto out_dev_unmap; 2991 2992 result = nvme_pci_alloc_iod_mempool(dev); 2993 if (result) 2994 goto out_release_prp_pools; 2995 2996 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2997 2998 result = nvme_pci_enable(dev); 2999 if (result) 3000 goto out_release_iod_mempool; 3001 3002 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset, 3003 &nvme_mq_admin_ops, sizeof(struct nvme_iod)); 3004 if (result) 3005 goto out_disable; 3006 3007 /* 3008 * Mark the controller as connecting before sending admin commands to 3009 * allow the timeout handler to do the right thing. 3010 */ 3011 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3012 dev_warn(dev->ctrl.device, 3013 "failed to mark controller CONNECTING\n"); 3014 result = -EBUSY; 3015 goto out_disable; 3016 } 3017 3018 result = nvme_init_ctrl_finish(&dev->ctrl, false); 3019 if (result) 3020 goto out_disable; 3021 3022 nvme_dbbuf_dma_alloc(dev); 3023 3024 result = nvme_setup_host_mem(dev); 3025 if (result < 0) 3026 goto out_disable; 3027 3028 result = nvme_setup_io_queues(dev); 3029 if (result) 3030 goto out_disable; 3031 3032 if (dev->online_queues > 1) { 3033 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, 3034 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod)); 3035 nvme_dbbuf_set(dev); 3036 } 3037 3038 if (!dev->ctrl.tagset) 3039 dev_warn(dev->ctrl.device, "IO queues not created\n"); 3040 3041 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3042 dev_warn(dev->ctrl.device, 3043 "failed to mark controller live state\n"); 3044 result = -ENODEV; 3045 goto out_disable; 3046 } 3047 3048 pci_set_drvdata(pdev, dev); 3049 3050 nvme_start_ctrl(&dev->ctrl); 3051 nvme_put_ctrl(&dev->ctrl); 3052 flush_work(&dev->ctrl.scan_work); 3053 return 0; 3054 3055 out_disable: 3056 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3057 nvme_dev_disable(dev, true); 3058 nvme_free_host_mem(dev); 3059 nvme_dev_remove_admin(dev); 3060 nvme_dbbuf_dma_free(dev); 3061 nvme_free_queues(dev, 0); 3062 out_release_iod_mempool: 3063 mempool_destroy(dev->iod_mempool); 3064 out_release_prp_pools: 3065 nvme_release_prp_pools(dev); 3066 out_dev_unmap: 3067 nvme_dev_unmap(dev); 3068 out_uninit_ctrl: 3069 nvme_uninit_ctrl(&dev->ctrl); 3070 return result; 3071 } 3072 3073 static void nvme_reset_prepare(struct pci_dev *pdev) 3074 { 3075 struct nvme_dev *dev = pci_get_drvdata(pdev); 3076 3077 /* 3078 * We don't need to check the return value from waiting for the reset 3079 * state as pci_dev device lock is held, making it impossible to race 3080 * with ->remove(). 3081 */ 3082 nvme_disable_prepare_reset(dev, false); 3083 nvme_sync_queues(&dev->ctrl); 3084 } 3085 3086 static void nvme_reset_done(struct pci_dev *pdev) 3087 { 3088 struct nvme_dev *dev = pci_get_drvdata(pdev); 3089 3090 if (!nvme_try_sched_reset(&dev->ctrl)) 3091 flush_work(&dev->ctrl.reset_work); 3092 } 3093 3094 static void nvme_shutdown(struct pci_dev *pdev) 3095 { 3096 struct nvme_dev *dev = pci_get_drvdata(pdev); 3097 3098 nvme_disable_prepare_reset(dev, true); 3099 } 3100 3101 /* 3102 * The driver's remove may be called on a device in a partially initialized 3103 * state. This function must not have any dependencies on the device state in 3104 * order to proceed. 3105 */ 3106 static void nvme_remove(struct pci_dev *pdev) 3107 { 3108 struct nvme_dev *dev = pci_get_drvdata(pdev); 3109 3110 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3111 pci_set_drvdata(pdev, NULL); 3112 3113 if (!pci_device_is_present(pdev)) { 3114 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 3115 nvme_dev_disable(dev, true); 3116 } 3117 3118 flush_work(&dev->ctrl.reset_work); 3119 nvme_stop_ctrl(&dev->ctrl); 3120 nvme_remove_namespaces(&dev->ctrl); 3121 nvme_dev_disable(dev, true); 3122 nvme_free_host_mem(dev); 3123 nvme_dev_remove_admin(dev); 3124 nvme_dbbuf_dma_free(dev); 3125 nvme_free_queues(dev, 0); 3126 mempool_destroy(dev->iod_mempool); 3127 nvme_release_prp_pools(dev); 3128 nvme_dev_unmap(dev); 3129 nvme_uninit_ctrl(&dev->ctrl); 3130 } 3131 3132 #ifdef CONFIG_PM_SLEEP 3133 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3134 { 3135 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3136 } 3137 3138 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3139 { 3140 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3141 } 3142 3143 static int nvme_resume(struct device *dev) 3144 { 3145 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3146 struct nvme_ctrl *ctrl = &ndev->ctrl; 3147 3148 if (ndev->last_ps == U32_MAX || 3149 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3150 goto reset; 3151 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3152 goto reset; 3153 3154 return 0; 3155 reset: 3156 return nvme_try_sched_reset(ctrl); 3157 } 3158 3159 static int nvme_suspend(struct device *dev) 3160 { 3161 struct pci_dev *pdev = to_pci_dev(dev); 3162 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3163 struct nvme_ctrl *ctrl = &ndev->ctrl; 3164 int ret = -EBUSY; 3165 3166 ndev->last_ps = U32_MAX; 3167 3168 /* 3169 * The platform does not remove power for a kernel managed suspend so 3170 * use host managed nvme power settings for lowest idle power if 3171 * possible. This should have quicker resume latency than a full device 3172 * shutdown. But if the firmware is involved after the suspend or the 3173 * device does not support any non-default power states, shut down the 3174 * device fully. 3175 * 3176 * If ASPM is not enabled for the device, shut down the device and allow 3177 * the PCI bus layer to put it into D3 in order to take the PCIe link 3178 * down, so as to allow the platform to achieve its minimum low-power 3179 * state (which may not be possible if the link is up). 3180 */ 3181 if (pm_suspend_via_firmware() || !ctrl->npss || 3182 !pcie_aspm_enabled(pdev) || 3183 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3184 return nvme_disable_prepare_reset(ndev, true); 3185 3186 nvme_start_freeze(ctrl); 3187 nvme_wait_freeze(ctrl); 3188 nvme_sync_queues(ctrl); 3189 3190 if (ctrl->state != NVME_CTRL_LIVE) 3191 goto unfreeze; 3192 3193 /* 3194 * Host memory access may not be successful in a system suspend state, 3195 * but the specification allows the controller to access memory in a 3196 * non-operational power state. 3197 */ 3198 if (ndev->hmb) { 3199 ret = nvme_set_host_mem(ndev, 0); 3200 if (ret < 0) 3201 goto unfreeze; 3202 } 3203 3204 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3205 if (ret < 0) 3206 goto unfreeze; 3207 3208 /* 3209 * A saved state prevents pci pm from generically controlling the 3210 * device's power. If we're using protocol specific settings, we don't 3211 * want pci interfering. 3212 */ 3213 pci_save_state(pdev); 3214 3215 ret = nvme_set_power_state(ctrl, ctrl->npss); 3216 if (ret < 0) 3217 goto unfreeze; 3218 3219 if (ret) { 3220 /* discard the saved state */ 3221 pci_load_saved_state(pdev, NULL); 3222 3223 /* 3224 * Clearing npss forces a controller reset on resume. The 3225 * correct value will be rediscovered then. 3226 */ 3227 ret = nvme_disable_prepare_reset(ndev, true); 3228 ctrl->npss = 0; 3229 } 3230 unfreeze: 3231 nvme_unfreeze(ctrl); 3232 return ret; 3233 } 3234 3235 static int nvme_simple_suspend(struct device *dev) 3236 { 3237 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3238 3239 return nvme_disable_prepare_reset(ndev, true); 3240 } 3241 3242 static int nvme_simple_resume(struct device *dev) 3243 { 3244 struct pci_dev *pdev = to_pci_dev(dev); 3245 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3246 3247 return nvme_try_sched_reset(&ndev->ctrl); 3248 } 3249 3250 static const struct dev_pm_ops nvme_dev_pm_ops = { 3251 .suspend = nvme_suspend, 3252 .resume = nvme_resume, 3253 .freeze = nvme_simple_suspend, 3254 .thaw = nvme_simple_resume, 3255 .poweroff = nvme_simple_suspend, 3256 .restore = nvme_simple_resume, 3257 }; 3258 #endif /* CONFIG_PM_SLEEP */ 3259 3260 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3261 pci_channel_state_t state) 3262 { 3263 struct nvme_dev *dev = pci_get_drvdata(pdev); 3264 3265 /* 3266 * A frozen channel requires a reset. When detected, this method will 3267 * shutdown the controller to quiesce. The controller will be restarted 3268 * after the slot reset through driver's slot_reset callback. 3269 */ 3270 switch (state) { 3271 case pci_channel_io_normal: 3272 return PCI_ERS_RESULT_CAN_RECOVER; 3273 case pci_channel_io_frozen: 3274 dev_warn(dev->ctrl.device, 3275 "frozen state error detected, reset controller\n"); 3276 nvme_dev_disable(dev, false); 3277 return PCI_ERS_RESULT_NEED_RESET; 3278 case pci_channel_io_perm_failure: 3279 dev_warn(dev->ctrl.device, 3280 "failure state error detected, request disconnect\n"); 3281 return PCI_ERS_RESULT_DISCONNECT; 3282 } 3283 return PCI_ERS_RESULT_NEED_RESET; 3284 } 3285 3286 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3287 { 3288 struct nvme_dev *dev = pci_get_drvdata(pdev); 3289 3290 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3291 pci_restore_state(pdev); 3292 nvme_reset_ctrl(&dev->ctrl); 3293 return PCI_ERS_RESULT_RECOVERED; 3294 } 3295 3296 static void nvme_error_resume(struct pci_dev *pdev) 3297 { 3298 struct nvme_dev *dev = pci_get_drvdata(pdev); 3299 3300 flush_work(&dev->ctrl.reset_work); 3301 } 3302 3303 static const struct pci_error_handlers nvme_err_handler = { 3304 .error_detected = nvme_error_detected, 3305 .slot_reset = nvme_slot_reset, 3306 .resume = nvme_error_resume, 3307 .reset_prepare = nvme_reset_prepare, 3308 .reset_done = nvme_reset_done, 3309 }; 3310 3311 static const struct pci_device_id nvme_id_table[] = { 3312 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3313 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3314 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3315 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3316 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3317 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3318 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3319 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3320 NVME_QUIRK_DEALLOCATE_ZEROES | 3321 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3322 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3323 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3324 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3325 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3326 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3327 NVME_QUIRK_MEDIUM_PRIO_SQ | 3328 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3329 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3330 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3331 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3332 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3333 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3334 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3335 NVME_QUIRK_BOGUS_NID, }, 3336 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3337 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3338 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3339 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3340 NVME_QUIRK_BOGUS_NID, }, 3341 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3342 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3343 NVME_QUIRK_NO_NS_DESC_LIST, }, 3344 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3345 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3346 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3347 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3348 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3349 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3350 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3351 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3352 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3353 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3354 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3355 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3356 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 3357 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3358 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3359 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3360 NVME_QUIRK_BOGUS_NID, }, 3361 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3362 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3363 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3364 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3365 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3366 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3367 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3368 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3369 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3370 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3371 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3372 NVME_QUIRK_BOGUS_NID, }, 3373 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3374 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3375 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3376 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3377 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3378 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3379 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3380 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3381 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3382 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3383 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3384 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3385 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3386 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3387 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3388 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 3389 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3390 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 3391 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3392 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 3393 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3394 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 3395 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3396 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3397 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3398 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3399 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3400 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3401 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3402 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3403 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3404 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3405 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3406 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3407 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3408 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3409 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3410 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */ 3411 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3412 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3413 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3414 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3415 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3416 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3417 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3418 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 3419 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3420 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3421 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3422 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3423 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3424 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 3425 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3426 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3427 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3428 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3429 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3430 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 3431 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3432 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3433 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3434 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3435 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3436 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3437 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3438 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3439 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3440 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3441 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3442 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3443 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3444 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3445 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3446 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3447 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3448 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3449 NVME_QUIRK_128_BYTES_SQES | 3450 NVME_QUIRK_SHARED_TAGS | 3451 NVME_QUIRK_SKIP_CID_GEN | 3452 NVME_QUIRK_IDENTIFY_CNS }, 3453 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3454 { 0, } 3455 }; 3456 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3457 3458 static struct pci_driver nvme_driver = { 3459 .name = "nvme", 3460 .id_table = nvme_id_table, 3461 .probe = nvme_probe, 3462 .remove = nvme_remove, 3463 .shutdown = nvme_shutdown, 3464 .driver = { 3465 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3466 #ifdef CONFIG_PM_SLEEP 3467 .pm = &nvme_dev_pm_ops, 3468 #endif 3469 }, 3470 .sriov_configure = pci_sriov_configure_simple, 3471 .err_handler = &nvme_err_handler, 3472 }; 3473 3474 static int __init nvme_init(void) 3475 { 3476 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3477 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3478 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3479 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3480 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE); 3481 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE); 3482 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS); 3483 3484 return pci_register_driver(&nvme_driver); 3485 } 3486 3487 static void __exit nvme_exit(void) 3488 { 3489 pci_unregister_driver(&nvme_driver); 3490 flush_workqueue(nvme_wq); 3491 } 3492 3493 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3494 MODULE_LICENSE("GPL"); 3495 MODULE_VERSION("1.0"); 3496 module_init(nvme_init); 3497 module_exit(nvme_exit); 3498