xref: /openbmc/linux/drivers/nvme/host/pci.c (revision ae3473231e77a3f1909d48cd144cebe5e1d049b3)
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14 
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/fs.h>
24 #include <linux/genhd.h>
25 #include <linux/hdreg.h>
26 #include <linux/idr.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/kdev_t.h>
31 #include <linux/kernel.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/timer.h>
43 #include <linux/types.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46 
47 #include "nvme.h"
48 
49 #define NVME_Q_DEPTH		1024
50 #define NVME_AQ_DEPTH		256
51 #define SQ_SIZE(depth)		(depth * sizeof(struct nvme_command))
52 #define CQ_SIZE(depth)		(depth * sizeof(struct nvme_completion))
53 
54 /*
55  * We handle AEN commands ourselves and don't even let the
56  * block layer know about them.
57  */
58 #define NVME_AQ_BLKMQ_DEPTH	(NVME_AQ_DEPTH - NVME_NR_AERS)
59 
60 static int use_threaded_interrupts;
61 module_param(use_threaded_interrupts, int, 0);
62 
63 static bool use_cmb_sqes = true;
64 module_param(use_cmb_sqes, bool, 0644);
65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
66 
67 static struct workqueue_struct *nvme_workq;
68 
69 struct nvme_dev;
70 struct nvme_queue;
71 
72 static int nvme_reset(struct nvme_dev *dev);
73 static void nvme_process_cq(struct nvme_queue *nvmeq);
74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
75 
76 /*
77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
78  */
79 struct nvme_dev {
80 	struct nvme_queue **queues;
81 	struct blk_mq_tag_set tagset;
82 	struct blk_mq_tag_set admin_tagset;
83 	u32 __iomem *dbs;
84 	struct device *dev;
85 	struct dma_pool *prp_page_pool;
86 	struct dma_pool *prp_small_pool;
87 	unsigned queue_count;
88 	unsigned online_queues;
89 	unsigned max_qid;
90 	int q_depth;
91 	u32 db_stride;
92 	void __iomem *bar;
93 	struct work_struct reset_work;
94 	struct work_struct remove_work;
95 	struct timer_list watchdog_timer;
96 	struct mutex shutdown_lock;
97 	bool subsystem;
98 	void __iomem *cmb;
99 	dma_addr_t cmb_dma_addr;
100 	u64 cmb_size;
101 	u32 cmbsz;
102 	u32 cmbloc;
103 	struct nvme_ctrl ctrl;
104 	struct completion ioq_wait;
105 };
106 
107 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
108 {
109 	return container_of(ctrl, struct nvme_dev, ctrl);
110 }
111 
112 /*
113  * An NVM Express queue.  Each device has at least two (one for admin
114  * commands and one for I/O commands).
115  */
116 struct nvme_queue {
117 	struct device *q_dmadev;
118 	struct nvme_dev *dev;
119 	char irqname[24];	/* nvme4294967295-65535\0 */
120 	spinlock_t q_lock;
121 	struct nvme_command *sq_cmds;
122 	struct nvme_command __iomem *sq_cmds_io;
123 	volatile struct nvme_completion *cqes;
124 	struct blk_mq_tags **tags;
125 	dma_addr_t sq_dma_addr;
126 	dma_addr_t cq_dma_addr;
127 	u32 __iomem *q_db;
128 	u16 q_depth;
129 	s16 cq_vector;
130 	u16 sq_tail;
131 	u16 cq_head;
132 	u16 qid;
133 	u8 cq_phase;
134 	u8 cqe_seen;
135 };
136 
137 /*
138  * The nvme_iod describes the data in an I/O, including the list of PRP
139  * entries.  You can't see it in this data structure because C doesn't let
140  * me express that.  Use nvme_init_iod to ensure there's enough space
141  * allocated to store the PRP list.
142  */
143 struct nvme_iod {
144 	struct nvme_request req;
145 	struct nvme_queue *nvmeq;
146 	int aborted;
147 	int npages;		/* In the PRP list. 0 means small pool in use */
148 	int nents;		/* Used in scatterlist */
149 	int length;		/* Of data, in bytes */
150 	dma_addr_t first_dma;
151 	struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
152 	struct scatterlist *sg;
153 	struct scatterlist inline_sg[0];
154 };
155 
156 /*
157  * Check we didin't inadvertently grow the command struct
158  */
159 static inline void _nvme_check_size(void)
160 {
161 	BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
162 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
163 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
164 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
165 	BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
166 	BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
167 	BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
168 	BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
169 	BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
170 	BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
171 	BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
172 	BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
173 }
174 
175 /*
176  * Max size of iod being embedded in the request payload
177  */
178 #define NVME_INT_PAGES		2
179 #define NVME_INT_BYTES(dev)	(NVME_INT_PAGES * (dev)->ctrl.page_size)
180 
181 /*
182  * Will slightly overestimate the number of pages needed.  This is OK
183  * as it only leads to a small amount of wasted memory for the lifetime of
184  * the I/O.
185  */
186 static int nvme_npages(unsigned size, struct nvme_dev *dev)
187 {
188 	unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
189 				      dev->ctrl.page_size);
190 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
191 }
192 
193 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
194 		unsigned int size, unsigned int nseg)
195 {
196 	return sizeof(__le64 *) * nvme_npages(size, dev) +
197 			sizeof(struct scatterlist) * nseg;
198 }
199 
200 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
201 {
202 	return sizeof(struct nvme_iod) +
203 		nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
204 }
205 
206 static int nvmeq_irq(struct nvme_queue *nvmeq)
207 {
208 	return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
209 }
210 
211 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
212 				unsigned int hctx_idx)
213 {
214 	struct nvme_dev *dev = data;
215 	struct nvme_queue *nvmeq = dev->queues[0];
216 
217 	WARN_ON(hctx_idx != 0);
218 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
219 	WARN_ON(nvmeq->tags);
220 
221 	hctx->driver_data = nvmeq;
222 	nvmeq->tags = &dev->admin_tagset.tags[0];
223 	return 0;
224 }
225 
226 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
227 {
228 	struct nvme_queue *nvmeq = hctx->driver_data;
229 
230 	nvmeq->tags = NULL;
231 }
232 
233 static int nvme_admin_init_request(void *data, struct request *req,
234 				unsigned int hctx_idx, unsigned int rq_idx,
235 				unsigned int numa_node)
236 {
237 	struct nvme_dev *dev = data;
238 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
239 	struct nvme_queue *nvmeq = dev->queues[0];
240 
241 	BUG_ON(!nvmeq);
242 	iod->nvmeq = nvmeq;
243 	return 0;
244 }
245 
246 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
247 			  unsigned int hctx_idx)
248 {
249 	struct nvme_dev *dev = data;
250 	struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
251 
252 	if (!nvmeq->tags)
253 		nvmeq->tags = &dev->tagset.tags[hctx_idx];
254 
255 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
256 	hctx->driver_data = nvmeq;
257 	return 0;
258 }
259 
260 static int nvme_init_request(void *data, struct request *req,
261 				unsigned int hctx_idx, unsigned int rq_idx,
262 				unsigned int numa_node)
263 {
264 	struct nvme_dev *dev = data;
265 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
266 	struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
267 
268 	BUG_ON(!nvmeq);
269 	iod->nvmeq = nvmeq;
270 	return 0;
271 }
272 
273 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
274 {
275 	struct nvme_dev *dev = set->driver_data;
276 
277 	return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
278 }
279 
280 /**
281  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
282  * @nvmeq: The queue to use
283  * @cmd: The command to send
284  *
285  * Safe to use from interrupt context
286  */
287 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
288 						struct nvme_command *cmd)
289 {
290 	u16 tail = nvmeq->sq_tail;
291 
292 	if (nvmeq->sq_cmds_io)
293 		memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
294 	else
295 		memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
296 
297 	if (++tail == nvmeq->q_depth)
298 		tail = 0;
299 	writel(tail, nvmeq->q_db);
300 	nvmeq->sq_tail = tail;
301 }
302 
303 static __le64 **iod_list(struct request *req)
304 {
305 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
306 	return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
307 }
308 
309 static int nvme_init_iod(struct request *rq, unsigned size,
310 		struct nvme_dev *dev)
311 {
312 	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
313 	int nseg = blk_rq_nr_phys_segments(rq);
314 
315 	if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
316 		iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
317 		if (!iod->sg)
318 			return BLK_MQ_RQ_QUEUE_BUSY;
319 	} else {
320 		iod->sg = iod->inline_sg;
321 	}
322 
323 	iod->aborted = 0;
324 	iod->npages = -1;
325 	iod->nents = 0;
326 	iod->length = size;
327 
328 	if (!(rq->rq_flags & RQF_DONTPREP)) {
329 		rq->retries = 0;
330 		rq->rq_flags |= RQF_DONTPREP;
331 	}
332 	return BLK_MQ_RQ_QUEUE_OK;
333 }
334 
335 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
336 {
337 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
338 	const int last_prp = dev->ctrl.page_size / 8 - 1;
339 	int i;
340 	__le64 **list = iod_list(req);
341 	dma_addr_t prp_dma = iod->first_dma;
342 
343 	if (iod->npages == 0)
344 		dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
345 	for (i = 0; i < iod->npages; i++) {
346 		__le64 *prp_list = list[i];
347 		dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
348 		dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
349 		prp_dma = next_prp_dma;
350 	}
351 
352 	if (iod->sg != iod->inline_sg)
353 		kfree(iod->sg);
354 }
355 
356 #ifdef CONFIG_BLK_DEV_INTEGRITY
357 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
358 {
359 	if (be32_to_cpu(pi->ref_tag) == v)
360 		pi->ref_tag = cpu_to_be32(p);
361 }
362 
363 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
364 {
365 	if (be32_to_cpu(pi->ref_tag) == p)
366 		pi->ref_tag = cpu_to_be32(v);
367 }
368 
369 /**
370  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
371  *
372  * The virtual start sector is the one that was originally submitted by the
373  * block layer.	Due to partitioning, MD/DM cloning, etc. the actual physical
374  * start sector may be different. Remap protection information to match the
375  * physical LBA on writes, and back to the original seed on reads.
376  *
377  * Type 0 and 3 do not have a ref tag, so no remapping required.
378  */
379 static void nvme_dif_remap(struct request *req,
380 			void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
381 {
382 	struct nvme_ns *ns = req->rq_disk->private_data;
383 	struct bio_integrity_payload *bip;
384 	struct t10_pi_tuple *pi;
385 	void *p, *pmap;
386 	u32 i, nlb, ts, phys, virt;
387 
388 	if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
389 		return;
390 
391 	bip = bio_integrity(req->bio);
392 	if (!bip)
393 		return;
394 
395 	pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
396 
397 	p = pmap;
398 	virt = bip_get_seed(bip);
399 	phys = nvme_block_nr(ns, blk_rq_pos(req));
400 	nlb = (blk_rq_bytes(req) >> ns->lba_shift);
401 	ts = ns->disk->queue->integrity.tuple_size;
402 
403 	for (i = 0; i < nlb; i++, virt++, phys++) {
404 		pi = (struct t10_pi_tuple *)p;
405 		dif_swap(phys, virt, pi);
406 		p += ts;
407 	}
408 	kunmap_atomic(pmap);
409 }
410 #else /* CONFIG_BLK_DEV_INTEGRITY */
411 static void nvme_dif_remap(struct request *req,
412 			void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
413 {
414 }
415 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
416 {
417 }
418 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
419 {
420 }
421 #endif
422 
423 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
424 		int total_len)
425 {
426 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
427 	struct dma_pool *pool;
428 	int length = total_len;
429 	struct scatterlist *sg = iod->sg;
430 	int dma_len = sg_dma_len(sg);
431 	u64 dma_addr = sg_dma_address(sg);
432 	u32 page_size = dev->ctrl.page_size;
433 	int offset = dma_addr & (page_size - 1);
434 	__le64 *prp_list;
435 	__le64 **list = iod_list(req);
436 	dma_addr_t prp_dma;
437 	int nprps, i;
438 
439 	length -= (page_size - offset);
440 	if (length <= 0)
441 		return true;
442 
443 	dma_len -= (page_size - offset);
444 	if (dma_len) {
445 		dma_addr += (page_size - offset);
446 	} else {
447 		sg = sg_next(sg);
448 		dma_addr = sg_dma_address(sg);
449 		dma_len = sg_dma_len(sg);
450 	}
451 
452 	if (length <= page_size) {
453 		iod->first_dma = dma_addr;
454 		return true;
455 	}
456 
457 	nprps = DIV_ROUND_UP(length, page_size);
458 	if (nprps <= (256 / 8)) {
459 		pool = dev->prp_small_pool;
460 		iod->npages = 0;
461 	} else {
462 		pool = dev->prp_page_pool;
463 		iod->npages = 1;
464 	}
465 
466 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
467 	if (!prp_list) {
468 		iod->first_dma = dma_addr;
469 		iod->npages = -1;
470 		return false;
471 	}
472 	list[0] = prp_list;
473 	iod->first_dma = prp_dma;
474 	i = 0;
475 	for (;;) {
476 		if (i == page_size >> 3) {
477 			__le64 *old_prp_list = prp_list;
478 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
479 			if (!prp_list)
480 				return false;
481 			list[iod->npages++] = prp_list;
482 			prp_list[0] = old_prp_list[i - 1];
483 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
484 			i = 1;
485 		}
486 		prp_list[i++] = cpu_to_le64(dma_addr);
487 		dma_len -= page_size;
488 		dma_addr += page_size;
489 		length -= page_size;
490 		if (length <= 0)
491 			break;
492 		if (dma_len > 0)
493 			continue;
494 		BUG_ON(dma_len < 0);
495 		sg = sg_next(sg);
496 		dma_addr = sg_dma_address(sg);
497 		dma_len = sg_dma_len(sg);
498 	}
499 
500 	return true;
501 }
502 
503 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
504 		unsigned size, struct nvme_command *cmnd)
505 {
506 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
507 	struct request_queue *q = req->q;
508 	enum dma_data_direction dma_dir = rq_data_dir(req) ?
509 			DMA_TO_DEVICE : DMA_FROM_DEVICE;
510 	int ret = BLK_MQ_RQ_QUEUE_ERROR;
511 
512 	sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
513 	iod->nents = blk_rq_map_sg(q, req, iod->sg);
514 	if (!iod->nents)
515 		goto out;
516 
517 	ret = BLK_MQ_RQ_QUEUE_BUSY;
518 	if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
519 				DMA_ATTR_NO_WARN))
520 		goto out;
521 
522 	if (!nvme_setup_prps(dev, req, size))
523 		goto out_unmap;
524 
525 	ret = BLK_MQ_RQ_QUEUE_ERROR;
526 	if (blk_integrity_rq(req)) {
527 		if (blk_rq_count_integrity_sg(q, req->bio) != 1)
528 			goto out_unmap;
529 
530 		sg_init_table(&iod->meta_sg, 1);
531 		if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
532 			goto out_unmap;
533 
534 		if (rq_data_dir(req))
535 			nvme_dif_remap(req, nvme_dif_prep);
536 
537 		if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
538 			goto out_unmap;
539 	}
540 
541 	cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
542 	cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
543 	if (blk_integrity_rq(req))
544 		cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
545 	return BLK_MQ_RQ_QUEUE_OK;
546 
547 out_unmap:
548 	dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
549 out:
550 	return ret;
551 }
552 
553 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
554 {
555 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
556 	enum dma_data_direction dma_dir = rq_data_dir(req) ?
557 			DMA_TO_DEVICE : DMA_FROM_DEVICE;
558 
559 	if (iod->nents) {
560 		dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
561 		if (blk_integrity_rq(req)) {
562 			if (!rq_data_dir(req))
563 				nvme_dif_remap(req, nvme_dif_complete);
564 			dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
565 		}
566 	}
567 
568 	nvme_cleanup_cmd(req);
569 	nvme_free_iod(dev, req);
570 }
571 
572 /*
573  * NOTE: ns is NULL when called on the admin queue.
574  */
575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
576 			 const struct blk_mq_queue_data *bd)
577 {
578 	struct nvme_ns *ns = hctx->queue->queuedata;
579 	struct nvme_queue *nvmeq = hctx->driver_data;
580 	struct nvme_dev *dev = nvmeq->dev;
581 	struct request *req = bd->rq;
582 	struct nvme_command cmnd;
583 	unsigned map_len;
584 	int ret = BLK_MQ_RQ_QUEUE_OK;
585 
586 	/*
587 	 * If formated with metadata, require the block layer provide a buffer
588 	 * unless this namespace is formated such that the metadata can be
589 	 * stripped/generated by the controller with PRACT=1.
590 	 */
591 	if (ns && ns->ms && !blk_integrity_rq(req)) {
592 		if (!(ns->pi_type && ns->ms == 8) &&
593 					req->cmd_type != REQ_TYPE_DRV_PRIV) {
594 			blk_mq_end_request(req, -EFAULT);
595 			return BLK_MQ_RQ_QUEUE_OK;
596 		}
597 	}
598 
599 	ret = nvme_setup_cmd(ns, req, &cmnd);
600 	if (ret != BLK_MQ_RQ_QUEUE_OK)
601 		return ret;
602 
603 	map_len = nvme_map_len(req);
604 	ret = nvme_init_iod(req, map_len, dev);
605 	if (ret != BLK_MQ_RQ_QUEUE_OK)
606 		goto out_free_cmd;
607 
608 	if (blk_rq_nr_phys_segments(req))
609 		ret = nvme_map_data(dev, req, map_len, &cmnd);
610 
611 	if (ret != BLK_MQ_RQ_QUEUE_OK)
612 		goto out_cleanup_iod;
613 
614 	blk_mq_start_request(req);
615 
616 	spin_lock_irq(&nvmeq->q_lock);
617 	if (unlikely(nvmeq->cq_vector < 0)) {
618 		if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
619 			ret = BLK_MQ_RQ_QUEUE_BUSY;
620 		else
621 			ret = BLK_MQ_RQ_QUEUE_ERROR;
622 		spin_unlock_irq(&nvmeq->q_lock);
623 		goto out_cleanup_iod;
624 	}
625 	__nvme_submit_cmd(nvmeq, &cmnd);
626 	nvme_process_cq(nvmeq);
627 	spin_unlock_irq(&nvmeq->q_lock);
628 	return BLK_MQ_RQ_QUEUE_OK;
629 out_cleanup_iod:
630 	nvme_free_iod(dev, req);
631 out_free_cmd:
632 	nvme_cleanup_cmd(req);
633 	return ret;
634 }
635 
636 static void nvme_complete_rq(struct request *req)
637 {
638 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
639 	struct nvme_dev *dev = iod->nvmeq->dev;
640 	int error = 0;
641 
642 	nvme_unmap_data(dev, req);
643 
644 	if (unlikely(req->errors)) {
645 		if (nvme_req_needs_retry(req, req->errors)) {
646 			req->retries++;
647 			nvme_requeue_req(req);
648 			return;
649 		}
650 
651 		if (req->cmd_type == REQ_TYPE_DRV_PRIV)
652 			error = req->errors;
653 		else
654 			error = nvme_error_status(req->errors);
655 	}
656 
657 	if (unlikely(iod->aborted)) {
658 		dev_warn(dev->ctrl.device,
659 			"completing aborted command with status: %04x\n",
660 			req->errors);
661 	}
662 
663 	blk_mq_end_request(req, error);
664 }
665 
666 /* We read the CQE phase first to check if the rest of the entry is valid */
667 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
668 		u16 phase)
669 {
670 	return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
671 }
672 
673 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
674 {
675 	u16 head, phase;
676 
677 	head = nvmeq->cq_head;
678 	phase = nvmeq->cq_phase;
679 
680 	while (nvme_cqe_valid(nvmeq, head, phase)) {
681 		struct nvme_completion cqe = nvmeq->cqes[head];
682 		struct request *req;
683 
684 		if (++head == nvmeq->q_depth) {
685 			head = 0;
686 			phase = !phase;
687 		}
688 
689 		if (tag && *tag == cqe.command_id)
690 			*tag = -1;
691 
692 		if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
693 			dev_warn(nvmeq->dev->ctrl.device,
694 				"invalid id %d completed on queue %d\n",
695 				cqe.command_id, le16_to_cpu(cqe.sq_id));
696 			continue;
697 		}
698 
699 		/*
700 		 * AEN requests are special as they don't time out and can
701 		 * survive any kind of queue freeze and often don't respond to
702 		 * aborts.  We don't even bother to allocate a struct request
703 		 * for them but rather special case them here.
704 		 */
705 		if (unlikely(nvmeq->qid == 0 &&
706 				cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
707 			nvme_complete_async_event(&nvmeq->dev->ctrl,
708 					cqe.status, &cqe.result);
709 			continue;
710 		}
711 
712 		req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
713 		nvme_req(req)->result = cqe.result;
714 		blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
715 
716 	}
717 
718 	/* If the controller ignores the cq head doorbell and continuously
719 	 * writes to the queue, it is theoretically possible to wrap around
720 	 * the queue twice and mistakenly return IRQ_NONE.  Linux only
721 	 * requires that 0.1% of your interrupts are handled, so this isn't
722 	 * a big problem.
723 	 */
724 	if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
725 		return;
726 
727 	if (likely(nvmeq->cq_vector >= 0))
728 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
729 	nvmeq->cq_head = head;
730 	nvmeq->cq_phase = phase;
731 
732 	nvmeq->cqe_seen = 1;
733 }
734 
735 static void nvme_process_cq(struct nvme_queue *nvmeq)
736 {
737 	__nvme_process_cq(nvmeq, NULL);
738 }
739 
740 static irqreturn_t nvme_irq(int irq, void *data)
741 {
742 	irqreturn_t result;
743 	struct nvme_queue *nvmeq = data;
744 	spin_lock(&nvmeq->q_lock);
745 	nvme_process_cq(nvmeq);
746 	result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
747 	nvmeq->cqe_seen = 0;
748 	spin_unlock(&nvmeq->q_lock);
749 	return result;
750 }
751 
752 static irqreturn_t nvme_irq_check(int irq, void *data)
753 {
754 	struct nvme_queue *nvmeq = data;
755 	if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
756 		return IRQ_WAKE_THREAD;
757 	return IRQ_NONE;
758 }
759 
760 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
761 {
762 	struct nvme_queue *nvmeq = hctx->driver_data;
763 
764 	if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
765 		spin_lock_irq(&nvmeq->q_lock);
766 		__nvme_process_cq(nvmeq, &tag);
767 		spin_unlock_irq(&nvmeq->q_lock);
768 
769 		if (tag == -1)
770 			return 1;
771 	}
772 
773 	return 0;
774 }
775 
776 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
777 {
778 	struct nvme_dev *dev = to_nvme_dev(ctrl);
779 	struct nvme_queue *nvmeq = dev->queues[0];
780 	struct nvme_command c;
781 
782 	memset(&c, 0, sizeof(c));
783 	c.common.opcode = nvme_admin_async_event;
784 	c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
785 
786 	spin_lock_irq(&nvmeq->q_lock);
787 	__nvme_submit_cmd(nvmeq, &c);
788 	spin_unlock_irq(&nvmeq->q_lock);
789 }
790 
791 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
792 {
793 	struct nvme_command c;
794 
795 	memset(&c, 0, sizeof(c));
796 	c.delete_queue.opcode = opcode;
797 	c.delete_queue.qid = cpu_to_le16(id);
798 
799 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
800 }
801 
802 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
803 						struct nvme_queue *nvmeq)
804 {
805 	struct nvme_command c;
806 	int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
807 
808 	/*
809 	 * Note: we (ab)use the fact the the prp fields survive if no data
810 	 * is attached to the request.
811 	 */
812 	memset(&c, 0, sizeof(c));
813 	c.create_cq.opcode = nvme_admin_create_cq;
814 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
815 	c.create_cq.cqid = cpu_to_le16(qid);
816 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
817 	c.create_cq.cq_flags = cpu_to_le16(flags);
818 	c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
819 
820 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
821 }
822 
823 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
824 						struct nvme_queue *nvmeq)
825 {
826 	struct nvme_command c;
827 	int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
828 
829 	/*
830 	 * Note: we (ab)use the fact the the prp fields survive if no data
831 	 * is attached to the request.
832 	 */
833 	memset(&c, 0, sizeof(c));
834 	c.create_sq.opcode = nvme_admin_create_sq;
835 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
836 	c.create_sq.sqid = cpu_to_le16(qid);
837 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
838 	c.create_sq.sq_flags = cpu_to_le16(flags);
839 	c.create_sq.cqid = cpu_to_le16(qid);
840 
841 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
842 }
843 
844 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
845 {
846 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
847 }
848 
849 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
850 {
851 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
852 }
853 
854 static void abort_endio(struct request *req, int error)
855 {
856 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
857 	struct nvme_queue *nvmeq = iod->nvmeq;
858 	u16 status = req->errors;
859 
860 	dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
861 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
862 	blk_mq_free_request(req);
863 }
864 
865 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
866 {
867 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
868 	struct nvme_queue *nvmeq = iod->nvmeq;
869 	struct nvme_dev *dev = nvmeq->dev;
870 	struct request *abort_req;
871 	struct nvme_command cmd;
872 
873 	/*
874 	 * Shutdown immediately if controller times out while starting. The
875 	 * reset work will see the pci device disabled when it gets the forced
876 	 * cancellation error. All outstanding requests are completed on
877 	 * shutdown, so we return BLK_EH_HANDLED.
878 	 */
879 	if (dev->ctrl.state == NVME_CTRL_RESETTING) {
880 		dev_warn(dev->ctrl.device,
881 			 "I/O %d QID %d timeout, disable controller\n",
882 			 req->tag, nvmeq->qid);
883 		nvme_dev_disable(dev, false);
884 		req->errors = NVME_SC_CANCELLED;
885 		return BLK_EH_HANDLED;
886 	}
887 
888 	/*
889  	 * Shutdown the controller immediately and schedule a reset if the
890  	 * command was already aborted once before and still hasn't been
891  	 * returned to the driver, or if this is the admin queue.
892 	 */
893 	if (!nvmeq->qid || iod->aborted) {
894 		dev_warn(dev->ctrl.device,
895 			 "I/O %d QID %d timeout, reset controller\n",
896 			 req->tag, nvmeq->qid);
897 		nvme_dev_disable(dev, false);
898 		nvme_reset(dev);
899 
900 		/*
901 		 * Mark the request as handled, since the inline shutdown
902 		 * forces all outstanding requests to complete.
903 		 */
904 		req->errors = NVME_SC_CANCELLED;
905 		return BLK_EH_HANDLED;
906 	}
907 
908 	iod->aborted = 1;
909 
910 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
911 		atomic_inc(&dev->ctrl.abort_limit);
912 		return BLK_EH_RESET_TIMER;
913 	}
914 
915 	memset(&cmd, 0, sizeof(cmd));
916 	cmd.abort.opcode = nvme_admin_abort_cmd;
917 	cmd.abort.cid = req->tag;
918 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
919 
920 	dev_warn(nvmeq->dev->ctrl.device,
921 		"I/O %d QID %d timeout, aborting\n",
922 		 req->tag, nvmeq->qid);
923 
924 	abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
925 			BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
926 	if (IS_ERR(abort_req)) {
927 		atomic_inc(&dev->ctrl.abort_limit);
928 		return BLK_EH_RESET_TIMER;
929 	}
930 
931 	abort_req->timeout = ADMIN_TIMEOUT;
932 	abort_req->end_io_data = NULL;
933 	blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
934 
935 	/*
936 	 * The aborted req will be completed on receiving the abort req.
937 	 * We enable the timer again. If hit twice, it'll cause a device reset,
938 	 * as the device then is in a faulty state.
939 	 */
940 	return BLK_EH_RESET_TIMER;
941 }
942 
943 static void nvme_free_queue(struct nvme_queue *nvmeq)
944 {
945 	dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
946 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
947 	if (nvmeq->sq_cmds)
948 		dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
949 					nvmeq->sq_cmds, nvmeq->sq_dma_addr);
950 	kfree(nvmeq);
951 }
952 
953 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
954 {
955 	int i;
956 
957 	for (i = dev->queue_count - 1; i >= lowest; i--) {
958 		struct nvme_queue *nvmeq = dev->queues[i];
959 		dev->queue_count--;
960 		dev->queues[i] = NULL;
961 		nvme_free_queue(nvmeq);
962 	}
963 }
964 
965 /**
966  * nvme_suspend_queue - put queue into suspended state
967  * @nvmeq - queue to suspend
968  */
969 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
970 {
971 	int vector;
972 
973 	spin_lock_irq(&nvmeq->q_lock);
974 	if (nvmeq->cq_vector == -1) {
975 		spin_unlock_irq(&nvmeq->q_lock);
976 		return 1;
977 	}
978 	vector = nvmeq_irq(nvmeq);
979 	nvmeq->dev->online_queues--;
980 	nvmeq->cq_vector = -1;
981 	spin_unlock_irq(&nvmeq->q_lock);
982 
983 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
984 		blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
985 
986 	free_irq(vector, nvmeq);
987 
988 	return 0;
989 }
990 
991 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
992 {
993 	struct nvme_queue *nvmeq = dev->queues[0];
994 
995 	if (!nvmeq)
996 		return;
997 	if (nvme_suspend_queue(nvmeq))
998 		return;
999 
1000 	if (shutdown)
1001 		nvme_shutdown_ctrl(&dev->ctrl);
1002 	else
1003 		nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1004 						dev->bar + NVME_REG_CAP));
1005 
1006 	spin_lock_irq(&nvmeq->q_lock);
1007 	nvme_process_cq(nvmeq);
1008 	spin_unlock_irq(&nvmeq->q_lock);
1009 }
1010 
1011 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1012 				int entry_size)
1013 {
1014 	int q_depth = dev->q_depth;
1015 	unsigned q_size_aligned = roundup(q_depth * entry_size,
1016 					  dev->ctrl.page_size);
1017 
1018 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1019 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1020 		mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1021 		q_depth = div_u64(mem_per_q, entry_size);
1022 
1023 		/*
1024 		 * Ensure the reduced q_depth is above some threshold where it
1025 		 * would be better to map queues in system memory with the
1026 		 * original depth
1027 		 */
1028 		if (q_depth < 64)
1029 			return -ENOMEM;
1030 	}
1031 
1032 	return q_depth;
1033 }
1034 
1035 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1036 				int qid, int depth)
1037 {
1038 	if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1039 		unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1040 						      dev->ctrl.page_size);
1041 		nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1042 		nvmeq->sq_cmds_io = dev->cmb + offset;
1043 	} else {
1044 		nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1045 					&nvmeq->sq_dma_addr, GFP_KERNEL);
1046 		if (!nvmeq->sq_cmds)
1047 			return -ENOMEM;
1048 	}
1049 
1050 	return 0;
1051 }
1052 
1053 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1054 							int depth)
1055 {
1056 	struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1057 	if (!nvmeq)
1058 		return NULL;
1059 
1060 	nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1061 					  &nvmeq->cq_dma_addr, GFP_KERNEL);
1062 	if (!nvmeq->cqes)
1063 		goto free_nvmeq;
1064 
1065 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1066 		goto free_cqdma;
1067 
1068 	nvmeq->q_dmadev = dev->dev;
1069 	nvmeq->dev = dev;
1070 	snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1071 			dev->ctrl.instance, qid);
1072 	spin_lock_init(&nvmeq->q_lock);
1073 	nvmeq->cq_head = 0;
1074 	nvmeq->cq_phase = 1;
1075 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1076 	nvmeq->q_depth = depth;
1077 	nvmeq->qid = qid;
1078 	nvmeq->cq_vector = -1;
1079 	dev->queues[qid] = nvmeq;
1080 	dev->queue_count++;
1081 
1082 	return nvmeq;
1083 
1084  free_cqdma:
1085 	dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1086 							nvmeq->cq_dma_addr);
1087  free_nvmeq:
1088 	kfree(nvmeq);
1089 	return NULL;
1090 }
1091 
1092 static int queue_request_irq(struct nvme_queue *nvmeq)
1093 {
1094 	if (use_threaded_interrupts)
1095 		return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1096 				nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1097 	else
1098 		return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1099 				nvmeq->irqname, nvmeq);
1100 }
1101 
1102 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1103 {
1104 	struct nvme_dev *dev = nvmeq->dev;
1105 
1106 	spin_lock_irq(&nvmeq->q_lock);
1107 	nvmeq->sq_tail = 0;
1108 	nvmeq->cq_head = 0;
1109 	nvmeq->cq_phase = 1;
1110 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1111 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1112 	dev->online_queues++;
1113 	spin_unlock_irq(&nvmeq->q_lock);
1114 }
1115 
1116 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1117 {
1118 	struct nvme_dev *dev = nvmeq->dev;
1119 	int result;
1120 
1121 	nvmeq->cq_vector = qid - 1;
1122 	result = adapter_alloc_cq(dev, qid, nvmeq);
1123 	if (result < 0)
1124 		return result;
1125 
1126 	result = adapter_alloc_sq(dev, qid, nvmeq);
1127 	if (result < 0)
1128 		goto release_cq;
1129 
1130 	result = queue_request_irq(nvmeq);
1131 	if (result < 0)
1132 		goto release_sq;
1133 
1134 	nvme_init_queue(nvmeq, qid);
1135 	return result;
1136 
1137  release_sq:
1138 	adapter_delete_sq(dev, qid);
1139  release_cq:
1140 	adapter_delete_cq(dev, qid);
1141 	return result;
1142 }
1143 
1144 static struct blk_mq_ops nvme_mq_admin_ops = {
1145 	.queue_rq	= nvme_queue_rq,
1146 	.complete	= nvme_complete_rq,
1147 	.init_hctx	= nvme_admin_init_hctx,
1148 	.exit_hctx      = nvme_admin_exit_hctx,
1149 	.init_request	= nvme_admin_init_request,
1150 	.timeout	= nvme_timeout,
1151 };
1152 
1153 static struct blk_mq_ops nvme_mq_ops = {
1154 	.queue_rq	= nvme_queue_rq,
1155 	.complete	= nvme_complete_rq,
1156 	.init_hctx	= nvme_init_hctx,
1157 	.init_request	= nvme_init_request,
1158 	.map_queues	= nvme_pci_map_queues,
1159 	.timeout	= nvme_timeout,
1160 	.poll		= nvme_poll,
1161 };
1162 
1163 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1164 {
1165 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1166 		/*
1167 		 * If the controller was reset during removal, it's possible
1168 		 * user requests may be waiting on a stopped queue. Start the
1169 		 * queue to flush these to completion.
1170 		 */
1171 		blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1172 		blk_cleanup_queue(dev->ctrl.admin_q);
1173 		blk_mq_free_tag_set(&dev->admin_tagset);
1174 	}
1175 }
1176 
1177 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1178 {
1179 	if (!dev->ctrl.admin_q) {
1180 		dev->admin_tagset.ops = &nvme_mq_admin_ops;
1181 		dev->admin_tagset.nr_hw_queues = 1;
1182 
1183 		/*
1184 		 * Subtract one to leave an empty queue entry for 'Full Queue'
1185 		 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1186 		 */
1187 		dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1188 		dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1189 		dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1190 		dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1191 		dev->admin_tagset.driver_data = dev;
1192 
1193 		if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1194 			return -ENOMEM;
1195 
1196 		dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1197 		if (IS_ERR(dev->ctrl.admin_q)) {
1198 			blk_mq_free_tag_set(&dev->admin_tagset);
1199 			return -ENOMEM;
1200 		}
1201 		if (!blk_get_queue(dev->ctrl.admin_q)) {
1202 			nvme_dev_remove_admin(dev);
1203 			dev->ctrl.admin_q = NULL;
1204 			return -ENODEV;
1205 		}
1206 	} else
1207 		blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1208 
1209 	return 0;
1210 }
1211 
1212 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1213 {
1214 	int result;
1215 	u32 aqa;
1216 	u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1217 	struct nvme_queue *nvmeq;
1218 
1219 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1220 						NVME_CAP_NSSRC(cap) : 0;
1221 
1222 	if (dev->subsystem &&
1223 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1224 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1225 
1226 	result = nvme_disable_ctrl(&dev->ctrl, cap);
1227 	if (result < 0)
1228 		return result;
1229 
1230 	nvmeq = dev->queues[0];
1231 	if (!nvmeq) {
1232 		nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1233 		if (!nvmeq)
1234 			return -ENOMEM;
1235 	}
1236 
1237 	aqa = nvmeq->q_depth - 1;
1238 	aqa |= aqa << 16;
1239 
1240 	writel(aqa, dev->bar + NVME_REG_AQA);
1241 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1242 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1243 
1244 	result = nvme_enable_ctrl(&dev->ctrl, cap);
1245 	if (result)
1246 		return result;
1247 
1248 	nvmeq->cq_vector = 0;
1249 	result = queue_request_irq(nvmeq);
1250 	if (result) {
1251 		nvmeq->cq_vector = -1;
1252 		return result;
1253 	}
1254 
1255 	return result;
1256 }
1257 
1258 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1259 {
1260 
1261 	/* If true, indicates loss of adapter communication, possibly by a
1262 	 * NVMe Subsystem reset.
1263 	 */
1264 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1265 
1266 	/* If there is a reset ongoing, we shouldn't reset again. */
1267 	if (work_busy(&dev->reset_work))
1268 		return false;
1269 
1270 	/* We shouldn't reset unless the controller is on fatal error state
1271 	 * _or_ if we lost the communication with it.
1272 	 */
1273 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1274 		return false;
1275 
1276 	/* If PCI error recovery process is happening, we cannot reset or
1277 	 * the recovery mechanism will surely fail.
1278 	 */
1279 	if (pci_channel_offline(to_pci_dev(dev->dev)))
1280 		return false;
1281 
1282 	return true;
1283 }
1284 
1285 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1286 {
1287 	/* Read a config register to help see what died. */
1288 	u16 pci_status;
1289 	int result;
1290 
1291 	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1292 				      &pci_status);
1293 	if (result == PCIBIOS_SUCCESSFUL)
1294 		dev_warn(dev->dev,
1295 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1296 			 csts, pci_status);
1297 	else
1298 		dev_warn(dev->dev,
1299 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1300 			 csts, result);
1301 }
1302 
1303 static void nvme_watchdog_timer(unsigned long data)
1304 {
1305 	struct nvme_dev *dev = (struct nvme_dev *)data;
1306 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1307 
1308 	/* Skip controllers under certain specific conditions. */
1309 	if (nvme_should_reset(dev, csts)) {
1310 		if (!nvme_reset(dev))
1311 			nvme_warn_reset(dev, csts);
1312 		return;
1313 	}
1314 
1315 	mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1316 }
1317 
1318 static int nvme_create_io_queues(struct nvme_dev *dev)
1319 {
1320 	unsigned i, max;
1321 	int ret = 0;
1322 
1323 	for (i = dev->queue_count; i <= dev->max_qid; i++) {
1324 		if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1325 			ret = -ENOMEM;
1326 			break;
1327 		}
1328 	}
1329 
1330 	max = min(dev->max_qid, dev->queue_count - 1);
1331 	for (i = dev->online_queues; i <= max; i++) {
1332 		ret = nvme_create_queue(dev->queues[i], i);
1333 		if (ret)
1334 			break;
1335 	}
1336 
1337 	/*
1338 	 * Ignore failing Create SQ/CQ commands, we can continue with less
1339 	 * than the desired aount of queues, and even a controller without
1340 	 * I/O queues an still be used to issue admin commands.  This might
1341 	 * be useful to upgrade a buggy firmware for example.
1342 	 */
1343 	return ret >= 0 ? 0 : ret;
1344 }
1345 
1346 static ssize_t nvme_cmb_show(struct device *dev,
1347 			     struct device_attribute *attr,
1348 			     char *buf)
1349 {
1350 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1351 
1352 	return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1353 		       ndev->cmbloc, ndev->cmbsz);
1354 }
1355 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1356 
1357 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1358 {
1359 	u64 szu, size, offset;
1360 	resource_size_t bar_size;
1361 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1362 	void __iomem *cmb;
1363 	dma_addr_t dma_addr;
1364 
1365 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1366 	if (!(NVME_CMB_SZ(dev->cmbsz)))
1367 		return NULL;
1368 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1369 
1370 	if (!use_cmb_sqes)
1371 		return NULL;
1372 
1373 	szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1374 	size = szu * NVME_CMB_SZ(dev->cmbsz);
1375 	offset = szu * NVME_CMB_OFST(dev->cmbloc);
1376 	bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1377 
1378 	if (offset > bar_size)
1379 		return NULL;
1380 
1381 	/*
1382 	 * Controllers may support a CMB size larger than their BAR,
1383 	 * for example, due to being behind a bridge. Reduce the CMB to
1384 	 * the reported size of the BAR
1385 	 */
1386 	if (size > bar_size - offset)
1387 		size = bar_size - offset;
1388 
1389 	dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1390 	cmb = ioremap_wc(dma_addr, size);
1391 	if (!cmb)
1392 		return NULL;
1393 
1394 	dev->cmb_dma_addr = dma_addr;
1395 	dev->cmb_size = size;
1396 	return cmb;
1397 }
1398 
1399 static inline void nvme_release_cmb(struct nvme_dev *dev)
1400 {
1401 	if (dev->cmb) {
1402 		iounmap(dev->cmb);
1403 		dev->cmb = NULL;
1404 	}
1405 }
1406 
1407 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1408 {
1409 	return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1410 }
1411 
1412 static int nvme_setup_io_queues(struct nvme_dev *dev)
1413 {
1414 	struct nvme_queue *adminq = dev->queues[0];
1415 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1416 	int result, nr_io_queues, size;
1417 
1418 	nr_io_queues = num_online_cpus();
1419 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1420 	if (result < 0)
1421 		return result;
1422 
1423 	if (nr_io_queues == 0)
1424 		return 0;
1425 
1426 	if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1427 		result = nvme_cmb_qdepth(dev, nr_io_queues,
1428 				sizeof(struct nvme_command));
1429 		if (result > 0)
1430 			dev->q_depth = result;
1431 		else
1432 			nvme_release_cmb(dev);
1433 	}
1434 
1435 	size = db_bar_size(dev, nr_io_queues);
1436 	if (size > 8192) {
1437 		iounmap(dev->bar);
1438 		do {
1439 			dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1440 			if (dev->bar)
1441 				break;
1442 			if (!--nr_io_queues)
1443 				return -ENOMEM;
1444 			size = db_bar_size(dev, nr_io_queues);
1445 		} while (1);
1446 		dev->dbs = dev->bar + 4096;
1447 		adminq->q_db = dev->dbs;
1448 	}
1449 
1450 	/* Deregister the admin queue's interrupt */
1451 	free_irq(pci_irq_vector(pdev, 0), adminq);
1452 
1453 	/*
1454 	 * If we enable msix early due to not intx, disable it again before
1455 	 * setting up the full range we need.
1456 	 */
1457 	pci_free_irq_vectors(pdev);
1458 	nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1459 			PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1460 	if (nr_io_queues <= 0)
1461 		return -EIO;
1462 	dev->max_qid = nr_io_queues;
1463 
1464 	/*
1465 	 * Should investigate if there's a performance win from allocating
1466 	 * more queues than interrupt vectors; it might allow the submission
1467 	 * path to scale better, even if the receive path is limited by the
1468 	 * number of interrupts.
1469 	 */
1470 
1471 	result = queue_request_irq(adminq);
1472 	if (result) {
1473 		adminq->cq_vector = -1;
1474 		return result;
1475 	}
1476 	return nvme_create_io_queues(dev);
1477 }
1478 
1479 static void nvme_del_queue_end(struct request *req, int error)
1480 {
1481 	struct nvme_queue *nvmeq = req->end_io_data;
1482 
1483 	blk_mq_free_request(req);
1484 	complete(&nvmeq->dev->ioq_wait);
1485 }
1486 
1487 static void nvme_del_cq_end(struct request *req, int error)
1488 {
1489 	struct nvme_queue *nvmeq = req->end_io_data;
1490 
1491 	if (!error) {
1492 		unsigned long flags;
1493 
1494 		/*
1495 		 * We might be called with the AQ q_lock held
1496 		 * and the I/O queue q_lock should always
1497 		 * nest inside the AQ one.
1498 		 */
1499 		spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1500 					SINGLE_DEPTH_NESTING);
1501 		nvme_process_cq(nvmeq);
1502 		spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1503 	}
1504 
1505 	nvme_del_queue_end(req, error);
1506 }
1507 
1508 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1509 {
1510 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1511 	struct request *req;
1512 	struct nvme_command cmd;
1513 
1514 	memset(&cmd, 0, sizeof(cmd));
1515 	cmd.delete_queue.opcode = opcode;
1516 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1517 
1518 	req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1519 	if (IS_ERR(req))
1520 		return PTR_ERR(req);
1521 
1522 	req->timeout = ADMIN_TIMEOUT;
1523 	req->end_io_data = nvmeq;
1524 
1525 	blk_execute_rq_nowait(q, NULL, req, false,
1526 			opcode == nvme_admin_delete_cq ?
1527 				nvme_del_cq_end : nvme_del_queue_end);
1528 	return 0;
1529 }
1530 
1531 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1532 {
1533 	int pass;
1534 	unsigned long timeout;
1535 	u8 opcode = nvme_admin_delete_sq;
1536 
1537 	for (pass = 0; pass < 2; pass++) {
1538 		int sent = 0, i = queues;
1539 
1540 		reinit_completion(&dev->ioq_wait);
1541  retry:
1542 		timeout = ADMIN_TIMEOUT;
1543 		for (; i > 0; i--, sent++)
1544 			if (nvme_delete_queue(dev->queues[i], opcode))
1545 				break;
1546 
1547 		while (sent--) {
1548 			timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1549 			if (timeout == 0)
1550 				return;
1551 			if (i)
1552 				goto retry;
1553 		}
1554 		opcode = nvme_admin_delete_cq;
1555 	}
1556 }
1557 
1558 /*
1559  * Return: error value if an error occurred setting up the queues or calling
1560  * Identify Device.  0 if these succeeded, even if adding some of the
1561  * namespaces failed.  At the moment, these failures are silent.  TBD which
1562  * failures should be reported.
1563  */
1564 static int nvme_dev_add(struct nvme_dev *dev)
1565 {
1566 	if (!dev->ctrl.tagset) {
1567 		dev->tagset.ops = &nvme_mq_ops;
1568 		dev->tagset.nr_hw_queues = dev->online_queues - 1;
1569 		dev->tagset.timeout = NVME_IO_TIMEOUT;
1570 		dev->tagset.numa_node = dev_to_node(dev->dev);
1571 		dev->tagset.queue_depth =
1572 				min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1573 		dev->tagset.cmd_size = nvme_cmd_size(dev);
1574 		dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1575 		dev->tagset.driver_data = dev;
1576 
1577 		if (blk_mq_alloc_tag_set(&dev->tagset))
1578 			return 0;
1579 		dev->ctrl.tagset = &dev->tagset;
1580 	} else {
1581 		blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1582 
1583 		/* Free previously allocated queues that are no longer usable */
1584 		nvme_free_queues(dev, dev->online_queues);
1585 	}
1586 
1587 	return 0;
1588 }
1589 
1590 static int nvme_pci_enable(struct nvme_dev *dev)
1591 {
1592 	u64 cap;
1593 	int result = -ENOMEM;
1594 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1595 
1596 	if (pci_enable_device_mem(pdev))
1597 		return result;
1598 
1599 	pci_set_master(pdev);
1600 
1601 	if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1602 	    dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1603 		goto disable;
1604 
1605 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1606 		result = -ENODEV;
1607 		goto disable;
1608 	}
1609 
1610 	/*
1611 	 * Some devices and/or platforms don't advertise or work with INTx
1612 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1613 	 * adjust this later.
1614 	 */
1615 	result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1616 	if (result < 0)
1617 		return result;
1618 
1619 	cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1620 
1621 	dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1622 	dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1623 	dev->dbs = dev->bar + 4096;
1624 
1625 	/*
1626 	 * Temporary fix for the Apple controller found in the MacBook8,1 and
1627 	 * some MacBook7,1 to avoid controller resets and data loss.
1628 	 */
1629 	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1630 		dev->q_depth = 2;
1631 		dev_warn(dev->dev, "detected Apple NVMe controller, set "
1632 			"queue depth=%u to work around controller resets\n",
1633 			dev->q_depth);
1634 	}
1635 
1636 	/*
1637 	 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1638 	 * populate sysfs if a CMB is implemented. Note that we add the
1639 	 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1640 	 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1641 	 * NULL as final argument to sysfs_add_file_to_group.
1642 	 */
1643 
1644 	if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1645 		dev->cmb = nvme_map_cmb(dev);
1646 
1647 		if (dev->cmbsz) {
1648 			if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1649 						    &dev_attr_cmb.attr, NULL))
1650 				dev_warn(dev->dev,
1651 					 "failed to add sysfs attribute for CMB\n");
1652 		}
1653 	}
1654 
1655 	pci_enable_pcie_error_reporting(pdev);
1656 	pci_save_state(pdev);
1657 	return 0;
1658 
1659  disable:
1660 	pci_disable_device(pdev);
1661 	return result;
1662 }
1663 
1664 static void nvme_dev_unmap(struct nvme_dev *dev)
1665 {
1666 	if (dev->bar)
1667 		iounmap(dev->bar);
1668 	pci_release_mem_regions(to_pci_dev(dev->dev));
1669 }
1670 
1671 static void nvme_pci_disable(struct nvme_dev *dev)
1672 {
1673 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1674 
1675 	pci_free_irq_vectors(pdev);
1676 
1677 	if (pci_is_enabled(pdev)) {
1678 		pci_disable_pcie_error_reporting(pdev);
1679 		pci_disable_device(pdev);
1680 	}
1681 }
1682 
1683 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1684 {
1685 	int i, queues;
1686 	u32 csts = -1;
1687 
1688 	del_timer_sync(&dev->watchdog_timer);
1689 
1690 	mutex_lock(&dev->shutdown_lock);
1691 	if (pci_is_enabled(to_pci_dev(dev->dev))) {
1692 		nvme_stop_queues(&dev->ctrl);
1693 		csts = readl(dev->bar + NVME_REG_CSTS);
1694 	}
1695 
1696 	queues = dev->online_queues - 1;
1697 	for (i = dev->queue_count - 1; i > 0; i--)
1698 		nvme_suspend_queue(dev->queues[i]);
1699 
1700 	if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1701 		/* A device might become IO incapable very soon during
1702 		 * probe, before the admin queue is configured. Thus,
1703 		 * queue_count can be 0 here.
1704 		 */
1705 		if (dev->queue_count)
1706 			nvme_suspend_queue(dev->queues[0]);
1707 	} else {
1708 		nvme_disable_io_queues(dev, queues);
1709 		nvme_disable_admin_queue(dev, shutdown);
1710 	}
1711 	nvme_pci_disable(dev);
1712 
1713 	blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1714 	blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1715 	mutex_unlock(&dev->shutdown_lock);
1716 }
1717 
1718 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1719 {
1720 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1721 						PAGE_SIZE, PAGE_SIZE, 0);
1722 	if (!dev->prp_page_pool)
1723 		return -ENOMEM;
1724 
1725 	/* Optimisation for I/Os between 4k and 128k */
1726 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1727 						256, 256, 0);
1728 	if (!dev->prp_small_pool) {
1729 		dma_pool_destroy(dev->prp_page_pool);
1730 		return -ENOMEM;
1731 	}
1732 	return 0;
1733 }
1734 
1735 static void nvme_release_prp_pools(struct nvme_dev *dev)
1736 {
1737 	dma_pool_destroy(dev->prp_page_pool);
1738 	dma_pool_destroy(dev->prp_small_pool);
1739 }
1740 
1741 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1742 {
1743 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1744 
1745 	put_device(dev->dev);
1746 	if (dev->tagset.tags)
1747 		blk_mq_free_tag_set(&dev->tagset);
1748 	if (dev->ctrl.admin_q)
1749 		blk_put_queue(dev->ctrl.admin_q);
1750 	kfree(dev->queues);
1751 	kfree(dev);
1752 }
1753 
1754 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1755 {
1756 	dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1757 
1758 	kref_get(&dev->ctrl.kref);
1759 	nvme_dev_disable(dev, false);
1760 	if (!schedule_work(&dev->remove_work))
1761 		nvme_put_ctrl(&dev->ctrl);
1762 }
1763 
1764 static void nvme_reset_work(struct work_struct *work)
1765 {
1766 	struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1767 	int result = -ENODEV;
1768 
1769 	if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1770 		goto out;
1771 
1772 	/*
1773 	 * If we're called to reset a live controller first shut it down before
1774 	 * moving on.
1775 	 */
1776 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1777 		nvme_dev_disable(dev, false);
1778 
1779 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1780 		goto out;
1781 
1782 	result = nvme_pci_enable(dev);
1783 	if (result)
1784 		goto out;
1785 
1786 	result = nvme_configure_admin_queue(dev);
1787 	if (result)
1788 		goto out;
1789 
1790 	nvme_init_queue(dev->queues[0], 0);
1791 	result = nvme_alloc_admin_tags(dev);
1792 	if (result)
1793 		goto out;
1794 
1795 	result = nvme_init_identify(&dev->ctrl);
1796 	if (result)
1797 		goto out;
1798 
1799 	result = nvme_setup_io_queues(dev);
1800 	if (result)
1801 		goto out;
1802 
1803 	/*
1804 	 * A controller that can not execute IO typically requires user
1805 	 * intervention to correct. For such degraded controllers, the driver
1806 	 * should not submit commands the user did not request, so skip
1807 	 * registering for asynchronous event notification on this condition.
1808 	 */
1809 	if (dev->online_queues > 1)
1810 		nvme_queue_async_events(&dev->ctrl);
1811 
1812 	mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1813 
1814 	/*
1815 	 * Keep the controller around but remove all namespaces if we don't have
1816 	 * any working I/O queue.
1817 	 */
1818 	if (dev->online_queues < 2) {
1819 		dev_warn(dev->ctrl.device, "IO queues not created\n");
1820 		nvme_kill_queues(&dev->ctrl);
1821 		nvme_remove_namespaces(&dev->ctrl);
1822 	} else {
1823 		nvme_start_queues(&dev->ctrl);
1824 		nvme_dev_add(dev);
1825 	}
1826 
1827 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1828 		dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1829 		goto out;
1830 	}
1831 
1832 	if (dev->online_queues > 1)
1833 		nvme_queue_scan(&dev->ctrl);
1834 	return;
1835 
1836  out:
1837 	nvme_remove_dead_ctrl(dev, result);
1838 }
1839 
1840 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1841 {
1842 	struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1843 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1844 
1845 	nvme_kill_queues(&dev->ctrl);
1846 	if (pci_get_drvdata(pdev))
1847 		device_release_driver(&pdev->dev);
1848 	nvme_put_ctrl(&dev->ctrl);
1849 }
1850 
1851 static int nvme_reset(struct nvme_dev *dev)
1852 {
1853 	if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1854 		return -ENODEV;
1855 	if (work_busy(&dev->reset_work))
1856 		return -ENODEV;
1857 	if (!queue_work(nvme_workq, &dev->reset_work))
1858 		return -EBUSY;
1859 	return 0;
1860 }
1861 
1862 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1863 {
1864 	*val = readl(to_nvme_dev(ctrl)->bar + off);
1865 	return 0;
1866 }
1867 
1868 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1869 {
1870 	writel(val, to_nvme_dev(ctrl)->bar + off);
1871 	return 0;
1872 }
1873 
1874 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1875 {
1876 	*val = readq(to_nvme_dev(ctrl)->bar + off);
1877 	return 0;
1878 }
1879 
1880 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1881 {
1882 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1883 	int ret = nvme_reset(dev);
1884 
1885 	if (!ret)
1886 		flush_work(&dev->reset_work);
1887 	return ret;
1888 }
1889 
1890 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1891 	.name			= "pcie",
1892 	.module			= THIS_MODULE,
1893 	.reg_read32		= nvme_pci_reg_read32,
1894 	.reg_write32		= nvme_pci_reg_write32,
1895 	.reg_read64		= nvme_pci_reg_read64,
1896 	.reset_ctrl		= nvme_pci_reset_ctrl,
1897 	.free_ctrl		= nvme_pci_free_ctrl,
1898 	.submit_async_event	= nvme_pci_submit_async_event,
1899 };
1900 
1901 static int nvme_dev_map(struct nvme_dev *dev)
1902 {
1903 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1904 
1905 	if (pci_request_mem_regions(pdev, "nvme"))
1906 		return -ENODEV;
1907 
1908 	dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1909 	if (!dev->bar)
1910 		goto release;
1911 
1912        return 0;
1913   release:
1914        pci_release_mem_regions(pdev);
1915        return -ENODEV;
1916 }
1917 
1918 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1919 {
1920 	int node, result = -ENOMEM;
1921 	struct nvme_dev *dev;
1922 
1923 	node = dev_to_node(&pdev->dev);
1924 	if (node == NUMA_NO_NODE)
1925 		set_dev_node(&pdev->dev, first_memory_node);
1926 
1927 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1928 	if (!dev)
1929 		return -ENOMEM;
1930 	dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1931 							GFP_KERNEL, node);
1932 	if (!dev->queues)
1933 		goto free;
1934 
1935 	dev->dev = get_device(&pdev->dev);
1936 	pci_set_drvdata(pdev, dev);
1937 
1938 	result = nvme_dev_map(dev);
1939 	if (result)
1940 		goto free;
1941 
1942 	INIT_WORK(&dev->reset_work, nvme_reset_work);
1943 	INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1944 	setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1945 		(unsigned long)dev);
1946 	mutex_init(&dev->shutdown_lock);
1947 	init_completion(&dev->ioq_wait);
1948 
1949 	result = nvme_setup_prp_pools(dev);
1950 	if (result)
1951 		goto put_pci;
1952 
1953 	result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1954 			id->driver_data);
1955 	if (result)
1956 		goto release_pools;
1957 
1958 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1959 
1960 	queue_work(nvme_workq, &dev->reset_work);
1961 	return 0;
1962 
1963  release_pools:
1964 	nvme_release_prp_pools(dev);
1965  put_pci:
1966 	put_device(dev->dev);
1967 	nvme_dev_unmap(dev);
1968  free:
1969 	kfree(dev->queues);
1970 	kfree(dev);
1971 	return result;
1972 }
1973 
1974 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1975 {
1976 	struct nvme_dev *dev = pci_get_drvdata(pdev);
1977 
1978 	if (prepare)
1979 		nvme_dev_disable(dev, false);
1980 	else
1981 		nvme_reset(dev);
1982 }
1983 
1984 static void nvme_shutdown(struct pci_dev *pdev)
1985 {
1986 	struct nvme_dev *dev = pci_get_drvdata(pdev);
1987 	nvme_dev_disable(dev, true);
1988 }
1989 
1990 /*
1991  * The driver's remove may be called on a device in a partially initialized
1992  * state. This function must not have any dependencies on the device state in
1993  * order to proceed.
1994  */
1995 static void nvme_remove(struct pci_dev *pdev)
1996 {
1997 	struct nvme_dev *dev = pci_get_drvdata(pdev);
1998 
1999 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2000 
2001 	pci_set_drvdata(pdev, NULL);
2002 
2003 	if (!pci_device_is_present(pdev))
2004 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2005 
2006 	flush_work(&dev->reset_work);
2007 	nvme_uninit_ctrl(&dev->ctrl);
2008 	nvme_dev_disable(dev, true);
2009 	nvme_dev_remove_admin(dev);
2010 	nvme_free_queues(dev, 0);
2011 	nvme_release_cmb(dev);
2012 	nvme_release_prp_pools(dev);
2013 	nvme_dev_unmap(dev);
2014 	nvme_put_ctrl(&dev->ctrl);
2015 }
2016 
2017 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2018 {
2019 	int ret = 0;
2020 
2021 	if (numvfs == 0) {
2022 		if (pci_vfs_assigned(pdev)) {
2023 			dev_warn(&pdev->dev,
2024 				"Cannot disable SR-IOV VFs while assigned\n");
2025 			return -EPERM;
2026 		}
2027 		pci_disable_sriov(pdev);
2028 		return 0;
2029 	}
2030 
2031 	ret = pci_enable_sriov(pdev, numvfs);
2032 	return ret ? ret : numvfs;
2033 }
2034 
2035 #ifdef CONFIG_PM_SLEEP
2036 static int nvme_suspend(struct device *dev)
2037 {
2038 	struct pci_dev *pdev = to_pci_dev(dev);
2039 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
2040 
2041 	nvme_dev_disable(ndev, true);
2042 	return 0;
2043 }
2044 
2045 static int nvme_resume(struct device *dev)
2046 {
2047 	struct pci_dev *pdev = to_pci_dev(dev);
2048 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
2049 
2050 	nvme_reset(ndev);
2051 	return 0;
2052 }
2053 #endif
2054 
2055 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2056 
2057 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2058 						pci_channel_state_t state)
2059 {
2060 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2061 
2062 	/*
2063 	 * A frozen channel requires a reset. When detected, this method will
2064 	 * shutdown the controller to quiesce. The controller will be restarted
2065 	 * after the slot reset through driver's slot_reset callback.
2066 	 */
2067 	switch (state) {
2068 	case pci_channel_io_normal:
2069 		return PCI_ERS_RESULT_CAN_RECOVER;
2070 	case pci_channel_io_frozen:
2071 		dev_warn(dev->ctrl.device,
2072 			"frozen state error detected, reset controller\n");
2073 		nvme_dev_disable(dev, false);
2074 		return PCI_ERS_RESULT_NEED_RESET;
2075 	case pci_channel_io_perm_failure:
2076 		dev_warn(dev->ctrl.device,
2077 			"failure state error detected, request disconnect\n");
2078 		return PCI_ERS_RESULT_DISCONNECT;
2079 	}
2080 	return PCI_ERS_RESULT_NEED_RESET;
2081 }
2082 
2083 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2084 {
2085 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2086 
2087 	dev_info(dev->ctrl.device, "restart after slot reset\n");
2088 	pci_restore_state(pdev);
2089 	nvme_reset(dev);
2090 	return PCI_ERS_RESULT_RECOVERED;
2091 }
2092 
2093 static void nvme_error_resume(struct pci_dev *pdev)
2094 {
2095 	pci_cleanup_aer_uncorrect_error_status(pdev);
2096 }
2097 
2098 static const struct pci_error_handlers nvme_err_handler = {
2099 	.error_detected	= nvme_error_detected,
2100 	.slot_reset	= nvme_slot_reset,
2101 	.resume		= nvme_error_resume,
2102 	.reset_notify	= nvme_reset_notify,
2103 };
2104 
2105 static const struct pci_device_id nvme_id_table[] = {
2106 	{ PCI_VDEVICE(INTEL, 0x0953),
2107 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2108 				NVME_QUIRK_DISCARD_ZEROES, },
2109 	{ PCI_VDEVICE(INTEL, 0x0a53),
2110 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2111 				NVME_QUIRK_DISCARD_ZEROES, },
2112 	{ PCI_VDEVICE(INTEL, 0x0a54),
2113 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2114 				NVME_QUIRK_DISCARD_ZEROES, },
2115 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
2116 		.driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2117 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
2118 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2119 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
2120 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2121 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2122 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2123 	{ 0, }
2124 };
2125 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2126 
2127 static struct pci_driver nvme_driver = {
2128 	.name		= "nvme",
2129 	.id_table	= nvme_id_table,
2130 	.probe		= nvme_probe,
2131 	.remove		= nvme_remove,
2132 	.shutdown	= nvme_shutdown,
2133 	.driver		= {
2134 		.pm	= &nvme_dev_pm_ops,
2135 	},
2136 	.sriov_configure = nvme_pci_sriov_configure,
2137 	.err_handler	= &nvme_err_handler,
2138 };
2139 
2140 static int __init nvme_init(void)
2141 {
2142 	int result;
2143 
2144 	nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2145 	if (!nvme_workq)
2146 		return -ENOMEM;
2147 
2148 	result = pci_register_driver(&nvme_driver);
2149 	if (result)
2150 		destroy_workqueue(nvme_workq);
2151 	return result;
2152 }
2153 
2154 static void __exit nvme_exit(void)
2155 {
2156 	pci_unregister_driver(&nvme_driver);
2157 	destroy_workqueue(nvme_workq);
2158 	_nvme_check_size();
2159 }
2160 
2161 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2162 MODULE_LICENSE("GPL");
2163 MODULE_VERSION("1.0");
2164 module_init(nvme_init);
2165 module_exit(nvme_exit);
2166