1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/aer.h> 9 #include <linux/async.h> 10 #include <linux/blkdev.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/dmi.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/mm.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/once.h> 21 #include <linux/pci.h> 22 #include <linux/suspend.h> 23 #include <linux/t10-pi.h> 24 #include <linux/types.h> 25 #include <linux/io-64-nonatomic-lo-hi.h> 26 #include <linux/io-64-nonatomic-hi-lo.h> 27 #include <linux/sed-opal.h> 28 #include <linux/pci-p2pdma.h> 29 30 #include "trace.h" 31 #include "nvme.h" 32 33 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 34 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 35 36 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 37 38 /* 39 * These can be higher, but we need to ensure that any command doesn't 40 * require an sg allocation that needs more than a page of data. 41 */ 42 #define NVME_MAX_KB_SZ 4096 43 #define NVME_MAX_SEGS 127 44 45 static int use_threaded_interrupts; 46 module_param(use_threaded_interrupts, int, 0); 47 48 static bool use_cmb_sqes = true; 49 module_param(use_cmb_sqes, bool, 0444); 50 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 51 52 static unsigned int max_host_mem_size_mb = 128; 53 module_param(max_host_mem_size_mb, uint, 0444); 54 MODULE_PARM_DESC(max_host_mem_size_mb, 55 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 56 57 static unsigned int sgl_threshold = SZ_32K; 58 module_param(sgl_threshold, uint, 0644); 59 MODULE_PARM_DESC(sgl_threshold, 60 "Use SGLs when average request segment size is larger or equal to " 61 "this size. Use 0 to disable SGLs."); 62 63 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 64 static const struct kernel_param_ops io_queue_depth_ops = { 65 .set = io_queue_depth_set, 66 .get = param_get_uint, 67 }; 68 69 static unsigned int io_queue_depth = 1024; 70 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 71 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 72 73 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 74 { 75 unsigned int n; 76 int ret; 77 78 ret = kstrtouint(val, 10, &n); 79 if (ret != 0 || n > num_possible_cpus()) 80 return -EINVAL; 81 return param_set_uint(val, kp); 82 } 83 84 static const struct kernel_param_ops io_queue_count_ops = { 85 .set = io_queue_count_set, 86 .get = param_get_uint, 87 }; 88 89 static unsigned int write_queues; 90 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 91 MODULE_PARM_DESC(write_queues, 92 "Number of queues to use for writes. If not set, reads and writes " 93 "will share a queue set."); 94 95 static unsigned int poll_queues; 96 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 97 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 98 99 static bool noacpi; 100 module_param(noacpi, bool, 0444); 101 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 102 103 struct nvme_dev; 104 struct nvme_queue; 105 106 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 107 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 108 109 /* 110 * Represents an NVM Express device. Each nvme_dev is a PCI function. 111 */ 112 struct nvme_dev { 113 struct nvme_queue *queues; 114 struct blk_mq_tag_set tagset; 115 struct blk_mq_tag_set admin_tagset; 116 u32 __iomem *dbs; 117 struct device *dev; 118 struct dma_pool *prp_page_pool; 119 struct dma_pool *prp_small_pool; 120 unsigned online_queues; 121 unsigned max_qid; 122 unsigned io_queues[HCTX_MAX_TYPES]; 123 unsigned int num_vecs; 124 u32 q_depth; 125 int io_sqes; 126 u32 db_stride; 127 void __iomem *bar; 128 unsigned long bar_mapped_size; 129 struct work_struct remove_work; 130 struct mutex shutdown_lock; 131 bool subsystem; 132 u64 cmb_size; 133 bool cmb_use_sqes; 134 u32 cmbsz; 135 u32 cmbloc; 136 struct nvme_ctrl ctrl; 137 u32 last_ps; 138 139 mempool_t *iod_mempool; 140 141 /* shadow doorbell buffer support: */ 142 u32 *dbbuf_dbs; 143 dma_addr_t dbbuf_dbs_dma_addr; 144 u32 *dbbuf_eis; 145 dma_addr_t dbbuf_eis_dma_addr; 146 147 /* host memory buffer support: */ 148 u64 host_mem_size; 149 u32 nr_host_mem_descs; 150 dma_addr_t host_mem_descs_dma; 151 struct nvme_host_mem_buf_desc *host_mem_descs; 152 void **host_mem_desc_bufs; 153 unsigned int nr_allocated_queues; 154 unsigned int nr_write_queues; 155 unsigned int nr_poll_queues; 156 }; 157 158 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 159 { 160 int ret; 161 u32 n; 162 163 ret = kstrtou32(val, 10, &n); 164 if (ret != 0 || n < 2) 165 return -EINVAL; 166 167 return param_set_uint(val, kp); 168 } 169 170 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171 { 172 return qid * 2 * stride; 173 } 174 175 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176 { 177 return (qid * 2 + 1) * stride; 178 } 179 180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 181 { 182 return container_of(ctrl, struct nvme_dev, ctrl); 183 } 184 185 /* 186 * An NVM Express queue. Each device has at least two (one for admin 187 * commands and one for I/O commands). 188 */ 189 struct nvme_queue { 190 struct nvme_dev *dev; 191 spinlock_t sq_lock; 192 void *sq_cmds; 193 /* only used for poll queues: */ 194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 195 struct nvme_completion *cqes; 196 dma_addr_t sq_dma_addr; 197 dma_addr_t cq_dma_addr; 198 u32 __iomem *q_db; 199 u32 q_depth; 200 u16 cq_vector; 201 u16 sq_tail; 202 u16 last_sq_tail; 203 u16 cq_head; 204 u16 qid; 205 u8 cq_phase; 206 u8 sqes; 207 unsigned long flags; 208 #define NVMEQ_ENABLED 0 209 #define NVMEQ_SQ_CMB 1 210 #define NVMEQ_DELETE_ERROR 2 211 #define NVMEQ_POLLED 3 212 u32 *dbbuf_sq_db; 213 u32 *dbbuf_cq_db; 214 u32 *dbbuf_sq_ei; 215 u32 *dbbuf_cq_ei; 216 struct completion delete_done; 217 }; 218 219 /* 220 * The nvme_iod describes the data in an I/O. 221 * 222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 223 * to the actual struct scatterlist. 224 */ 225 struct nvme_iod { 226 struct nvme_request req; 227 struct nvme_command cmd; 228 struct nvme_queue *nvmeq; 229 bool use_sgl; 230 int aborted; 231 int npages; /* In the PRP list. 0 means small pool in use */ 232 int nents; /* Used in scatterlist */ 233 dma_addr_t first_dma; 234 unsigned int dma_len; /* length of single DMA segment mapping */ 235 dma_addr_t meta_dma; 236 struct scatterlist *sg; 237 }; 238 239 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 240 { 241 return dev->nr_allocated_queues * 8 * dev->db_stride; 242 } 243 244 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 245 { 246 unsigned int mem_size = nvme_dbbuf_size(dev); 247 248 if (dev->dbbuf_dbs) 249 return 0; 250 251 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 252 &dev->dbbuf_dbs_dma_addr, 253 GFP_KERNEL); 254 if (!dev->dbbuf_dbs) 255 return -ENOMEM; 256 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 257 &dev->dbbuf_eis_dma_addr, 258 GFP_KERNEL); 259 if (!dev->dbbuf_eis) { 260 dma_free_coherent(dev->dev, mem_size, 261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 262 dev->dbbuf_dbs = NULL; 263 return -ENOMEM; 264 } 265 266 return 0; 267 } 268 269 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 270 { 271 unsigned int mem_size = nvme_dbbuf_size(dev); 272 273 if (dev->dbbuf_dbs) { 274 dma_free_coherent(dev->dev, mem_size, 275 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 276 dev->dbbuf_dbs = NULL; 277 } 278 if (dev->dbbuf_eis) { 279 dma_free_coherent(dev->dev, mem_size, 280 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 281 dev->dbbuf_eis = NULL; 282 } 283 } 284 285 static void nvme_dbbuf_init(struct nvme_dev *dev, 286 struct nvme_queue *nvmeq, int qid) 287 { 288 if (!dev->dbbuf_dbs || !qid) 289 return; 290 291 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 292 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 293 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 294 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 295 } 296 297 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 298 { 299 if (!nvmeq->qid) 300 return; 301 302 nvmeq->dbbuf_sq_db = NULL; 303 nvmeq->dbbuf_cq_db = NULL; 304 nvmeq->dbbuf_sq_ei = NULL; 305 nvmeq->dbbuf_cq_ei = NULL; 306 } 307 308 static void nvme_dbbuf_set(struct nvme_dev *dev) 309 { 310 struct nvme_command c = { }; 311 unsigned int i; 312 313 if (!dev->dbbuf_dbs) 314 return; 315 316 c.dbbuf.opcode = nvme_admin_dbbuf; 317 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 318 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 319 320 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 321 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 322 /* Free memory and continue on */ 323 nvme_dbbuf_dma_free(dev); 324 325 for (i = 1; i <= dev->online_queues; i++) 326 nvme_dbbuf_free(&dev->queues[i]); 327 } 328 } 329 330 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 331 { 332 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 333 } 334 335 /* Update dbbuf and return true if an MMIO is required */ 336 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 337 volatile u32 *dbbuf_ei) 338 { 339 if (dbbuf_db) { 340 u16 old_value; 341 342 /* 343 * Ensure that the queue is written before updating 344 * the doorbell in memory 345 */ 346 wmb(); 347 348 old_value = *dbbuf_db; 349 *dbbuf_db = value; 350 351 /* 352 * Ensure that the doorbell is updated before reading the event 353 * index from memory. The controller needs to provide similar 354 * ordering to ensure the envent index is updated before reading 355 * the doorbell. 356 */ 357 mb(); 358 359 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 360 return false; 361 } 362 363 return true; 364 } 365 366 /* 367 * Will slightly overestimate the number of pages needed. This is OK 368 * as it only leads to a small amount of wasted memory for the lifetime of 369 * the I/O. 370 */ 371 static int nvme_pci_npages_prp(void) 372 { 373 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 374 NVME_CTRL_PAGE_SIZE); 375 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 376 } 377 378 /* 379 * Calculates the number of pages needed for the SGL segments. For example a 4k 380 * page can accommodate 256 SGL descriptors. 381 */ 382 static int nvme_pci_npages_sgl(void) 383 { 384 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 385 PAGE_SIZE); 386 } 387 388 static size_t nvme_pci_iod_alloc_size(void) 389 { 390 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 391 392 return sizeof(__le64 *) * npages + 393 sizeof(struct scatterlist) * NVME_MAX_SEGS; 394 } 395 396 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 397 unsigned int hctx_idx) 398 { 399 struct nvme_dev *dev = data; 400 struct nvme_queue *nvmeq = &dev->queues[0]; 401 402 WARN_ON(hctx_idx != 0); 403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 404 405 hctx->driver_data = nvmeq; 406 return 0; 407 } 408 409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 410 unsigned int hctx_idx) 411 { 412 struct nvme_dev *dev = data; 413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 414 415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 416 hctx->driver_data = nvmeq; 417 return 0; 418 } 419 420 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 421 unsigned int hctx_idx, unsigned int numa_node) 422 { 423 struct nvme_dev *dev = set->driver_data; 424 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 425 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 426 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 427 428 BUG_ON(!nvmeq); 429 iod->nvmeq = nvmeq; 430 431 nvme_req(req)->ctrl = &dev->ctrl; 432 nvme_req(req)->cmd = &iod->cmd; 433 return 0; 434 } 435 436 static int queue_irq_offset(struct nvme_dev *dev) 437 { 438 /* if we have more than 1 vec, admin queue offsets us by 1 */ 439 if (dev->num_vecs > 1) 440 return 1; 441 442 return 0; 443 } 444 445 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 446 { 447 struct nvme_dev *dev = set->driver_data; 448 int i, qoff, offset; 449 450 offset = queue_irq_offset(dev); 451 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 452 struct blk_mq_queue_map *map = &set->map[i]; 453 454 map->nr_queues = dev->io_queues[i]; 455 if (!map->nr_queues) { 456 BUG_ON(i == HCTX_TYPE_DEFAULT); 457 continue; 458 } 459 460 /* 461 * The poll queue(s) doesn't have an IRQ (and hence IRQ 462 * affinity), so use the regular blk-mq cpu mapping 463 */ 464 map->queue_offset = qoff; 465 if (i != HCTX_TYPE_POLL && offset) 466 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 467 else 468 blk_mq_map_queues(map); 469 qoff += map->nr_queues; 470 offset += map->nr_queues; 471 } 472 473 return 0; 474 } 475 476 /* 477 * Write sq tail if we are asked to, or if the next command would wrap. 478 */ 479 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 480 { 481 if (!write_sq) { 482 u16 next_tail = nvmeq->sq_tail + 1; 483 484 if (next_tail == nvmeq->q_depth) 485 next_tail = 0; 486 if (next_tail != nvmeq->last_sq_tail) 487 return; 488 } 489 490 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 491 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 492 writel(nvmeq->sq_tail, nvmeq->q_db); 493 nvmeq->last_sq_tail = nvmeq->sq_tail; 494 } 495 496 /** 497 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 498 * @nvmeq: The queue to use 499 * @cmd: The command to send 500 * @write_sq: whether to write to the SQ doorbell 501 */ 502 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 503 bool write_sq) 504 { 505 spin_lock(&nvmeq->sq_lock); 506 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 507 cmd, sizeof(*cmd)); 508 if (++nvmeq->sq_tail == nvmeq->q_depth) 509 nvmeq->sq_tail = 0; 510 nvme_write_sq_db(nvmeq, write_sq); 511 spin_unlock(&nvmeq->sq_lock); 512 } 513 514 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 515 { 516 struct nvme_queue *nvmeq = hctx->driver_data; 517 518 spin_lock(&nvmeq->sq_lock); 519 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 520 nvme_write_sq_db(nvmeq, true); 521 spin_unlock(&nvmeq->sq_lock); 522 } 523 524 static void **nvme_pci_iod_list(struct request *req) 525 { 526 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 527 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 528 } 529 530 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 531 { 532 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 533 int nseg = blk_rq_nr_phys_segments(req); 534 unsigned int avg_seg_size; 535 536 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 537 538 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 539 return false; 540 if (!iod->nvmeq->qid) 541 return false; 542 if (!sgl_threshold || avg_seg_size < sgl_threshold) 543 return false; 544 return true; 545 } 546 547 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 548 { 549 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 550 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 551 dma_addr_t dma_addr = iod->first_dma; 552 int i; 553 554 for (i = 0; i < iod->npages; i++) { 555 __le64 *prp_list = nvme_pci_iod_list(req)[i]; 556 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 557 558 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 559 dma_addr = next_dma_addr; 560 } 561 } 562 563 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 564 { 565 const int last_sg = SGES_PER_PAGE - 1; 566 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 567 dma_addr_t dma_addr = iod->first_dma; 568 int i; 569 570 for (i = 0; i < iod->npages; i++) { 571 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 572 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 573 574 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 575 dma_addr = next_dma_addr; 576 } 577 } 578 579 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 580 { 581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 582 583 if (is_pci_p2pdma_page(sg_page(iod->sg))) 584 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 585 rq_dma_dir(req)); 586 else 587 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 588 } 589 590 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 591 { 592 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 593 594 if (iod->dma_len) { 595 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 596 rq_dma_dir(req)); 597 return; 598 } 599 600 WARN_ON_ONCE(!iod->nents); 601 602 nvme_unmap_sg(dev, req); 603 if (iod->npages == 0) 604 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 605 iod->first_dma); 606 else if (iod->use_sgl) 607 nvme_free_sgls(dev, req); 608 else 609 nvme_free_prps(dev, req); 610 mempool_free(iod->sg, dev->iod_mempool); 611 } 612 613 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 614 { 615 int i; 616 struct scatterlist *sg; 617 618 for_each_sg(sgl, sg, nents, i) { 619 dma_addr_t phys = sg_phys(sg); 620 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 621 "dma_address:%pad dma_length:%d\n", 622 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 623 sg_dma_len(sg)); 624 } 625 } 626 627 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 628 struct request *req, struct nvme_rw_command *cmnd) 629 { 630 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 631 struct dma_pool *pool; 632 int length = blk_rq_payload_bytes(req); 633 struct scatterlist *sg = iod->sg; 634 int dma_len = sg_dma_len(sg); 635 u64 dma_addr = sg_dma_address(sg); 636 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 637 __le64 *prp_list; 638 void **list = nvme_pci_iod_list(req); 639 dma_addr_t prp_dma; 640 int nprps, i; 641 642 length -= (NVME_CTRL_PAGE_SIZE - offset); 643 if (length <= 0) { 644 iod->first_dma = 0; 645 goto done; 646 } 647 648 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 649 if (dma_len) { 650 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 651 } else { 652 sg = sg_next(sg); 653 dma_addr = sg_dma_address(sg); 654 dma_len = sg_dma_len(sg); 655 } 656 657 if (length <= NVME_CTRL_PAGE_SIZE) { 658 iod->first_dma = dma_addr; 659 goto done; 660 } 661 662 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 663 if (nprps <= (256 / 8)) { 664 pool = dev->prp_small_pool; 665 iod->npages = 0; 666 } else { 667 pool = dev->prp_page_pool; 668 iod->npages = 1; 669 } 670 671 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 672 if (!prp_list) { 673 iod->first_dma = dma_addr; 674 iod->npages = -1; 675 return BLK_STS_RESOURCE; 676 } 677 list[0] = prp_list; 678 iod->first_dma = prp_dma; 679 i = 0; 680 for (;;) { 681 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 682 __le64 *old_prp_list = prp_list; 683 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 684 if (!prp_list) 685 goto free_prps; 686 list[iod->npages++] = prp_list; 687 prp_list[0] = old_prp_list[i - 1]; 688 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 689 i = 1; 690 } 691 prp_list[i++] = cpu_to_le64(dma_addr); 692 dma_len -= NVME_CTRL_PAGE_SIZE; 693 dma_addr += NVME_CTRL_PAGE_SIZE; 694 length -= NVME_CTRL_PAGE_SIZE; 695 if (length <= 0) 696 break; 697 if (dma_len > 0) 698 continue; 699 if (unlikely(dma_len < 0)) 700 goto bad_sgl; 701 sg = sg_next(sg); 702 dma_addr = sg_dma_address(sg); 703 dma_len = sg_dma_len(sg); 704 } 705 done: 706 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 707 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 708 return BLK_STS_OK; 709 free_prps: 710 nvme_free_prps(dev, req); 711 return BLK_STS_RESOURCE; 712 bad_sgl: 713 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 714 "Invalid SGL for payload:%d nents:%d\n", 715 blk_rq_payload_bytes(req), iod->nents); 716 return BLK_STS_IOERR; 717 } 718 719 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 720 struct scatterlist *sg) 721 { 722 sge->addr = cpu_to_le64(sg_dma_address(sg)); 723 sge->length = cpu_to_le32(sg_dma_len(sg)); 724 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 725 } 726 727 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 728 dma_addr_t dma_addr, int entries) 729 { 730 sge->addr = cpu_to_le64(dma_addr); 731 if (entries < SGES_PER_PAGE) { 732 sge->length = cpu_to_le32(entries * sizeof(*sge)); 733 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 734 } else { 735 sge->length = cpu_to_le32(PAGE_SIZE); 736 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 737 } 738 } 739 740 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 741 struct request *req, struct nvme_rw_command *cmd, int entries) 742 { 743 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 744 struct dma_pool *pool; 745 struct nvme_sgl_desc *sg_list; 746 struct scatterlist *sg = iod->sg; 747 dma_addr_t sgl_dma; 748 int i = 0; 749 750 /* setting the transfer type as SGL */ 751 cmd->flags = NVME_CMD_SGL_METABUF; 752 753 if (entries == 1) { 754 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 755 return BLK_STS_OK; 756 } 757 758 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 759 pool = dev->prp_small_pool; 760 iod->npages = 0; 761 } else { 762 pool = dev->prp_page_pool; 763 iod->npages = 1; 764 } 765 766 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 767 if (!sg_list) { 768 iod->npages = -1; 769 return BLK_STS_RESOURCE; 770 } 771 772 nvme_pci_iod_list(req)[0] = sg_list; 773 iod->first_dma = sgl_dma; 774 775 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 776 777 do { 778 if (i == SGES_PER_PAGE) { 779 struct nvme_sgl_desc *old_sg_desc = sg_list; 780 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 781 782 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 783 if (!sg_list) 784 goto free_sgls; 785 786 i = 0; 787 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 788 sg_list[i++] = *link; 789 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 790 } 791 792 nvme_pci_sgl_set_data(&sg_list[i++], sg); 793 sg = sg_next(sg); 794 } while (--entries > 0); 795 796 return BLK_STS_OK; 797 free_sgls: 798 nvme_free_sgls(dev, req); 799 return BLK_STS_RESOURCE; 800 } 801 802 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 803 struct request *req, struct nvme_rw_command *cmnd, 804 struct bio_vec *bv) 805 { 806 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 807 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 808 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 809 810 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 811 if (dma_mapping_error(dev->dev, iod->first_dma)) 812 return BLK_STS_RESOURCE; 813 iod->dma_len = bv->bv_len; 814 815 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 816 if (bv->bv_len > first_prp_len) 817 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 818 return BLK_STS_OK; 819 } 820 821 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 822 struct request *req, struct nvme_rw_command *cmnd, 823 struct bio_vec *bv) 824 { 825 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 826 827 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 828 if (dma_mapping_error(dev->dev, iod->first_dma)) 829 return BLK_STS_RESOURCE; 830 iod->dma_len = bv->bv_len; 831 832 cmnd->flags = NVME_CMD_SGL_METABUF; 833 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 834 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 835 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 836 return BLK_STS_OK; 837 } 838 839 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 840 struct nvme_command *cmnd) 841 { 842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 843 blk_status_t ret = BLK_STS_RESOURCE; 844 int nr_mapped; 845 846 if (blk_rq_nr_phys_segments(req) == 1) { 847 struct bio_vec bv = req_bvec(req); 848 849 if (!is_pci_p2pdma_page(bv.bv_page)) { 850 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 851 return nvme_setup_prp_simple(dev, req, 852 &cmnd->rw, &bv); 853 854 if (iod->nvmeq->qid && sgl_threshold && 855 nvme_ctrl_sgl_supported(&dev->ctrl)) 856 return nvme_setup_sgl_simple(dev, req, 857 &cmnd->rw, &bv); 858 } 859 } 860 861 iod->dma_len = 0; 862 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 863 if (!iod->sg) 864 return BLK_STS_RESOURCE; 865 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 866 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 867 if (!iod->nents) 868 goto out_free_sg; 869 870 if (is_pci_p2pdma_page(sg_page(iod->sg))) 871 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 872 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 873 else 874 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 875 rq_dma_dir(req), DMA_ATTR_NO_WARN); 876 if (!nr_mapped) 877 goto out_free_sg; 878 879 iod->use_sgl = nvme_pci_use_sgls(dev, req); 880 if (iod->use_sgl) 881 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 882 else 883 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 884 if (ret != BLK_STS_OK) 885 goto out_unmap_sg; 886 return BLK_STS_OK; 887 888 out_unmap_sg: 889 nvme_unmap_sg(dev, req); 890 out_free_sg: 891 mempool_free(iod->sg, dev->iod_mempool); 892 return ret; 893 } 894 895 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 896 struct nvme_command *cmnd) 897 { 898 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 899 900 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 901 rq_dma_dir(req), 0); 902 if (dma_mapping_error(dev->dev, iod->meta_dma)) 903 return BLK_STS_IOERR; 904 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 905 return BLK_STS_OK; 906 } 907 908 /* 909 * NOTE: ns is NULL when called on the admin queue. 910 */ 911 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 912 const struct blk_mq_queue_data *bd) 913 { 914 struct nvme_ns *ns = hctx->queue->queuedata; 915 struct nvme_queue *nvmeq = hctx->driver_data; 916 struct nvme_dev *dev = nvmeq->dev; 917 struct request *req = bd->rq; 918 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 919 struct nvme_command *cmnd = &iod->cmd; 920 blk_status_t ret; 921 922 iod->aborted = 0; 923 iod->npages = -1; 924 iod->nents = 0; 925 926 /* 927 * We should not need to do this, but we're still using this to 928 * ensure we can drain requests on a dying queue. 929 */ 930 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 931 return BLK_STS_IOERR; 932 933 if (!nvme_check_ready(&dev->ctrl, req, true)) 934 return nvme_fail_nonready_command(&dev->ctrl, req); 935 936 ret = nvme_setup_cmd(ns, req); 937 if (ret) 938 return ret; 939 940 if (blk_rq_nr_phys_segments(req)) { 941 ret = nvme_map_data(dev, req, cmnd); 942 if (ret) 943 goto out_free_cmd; 944 } 945 946 if (blk_integrity_rq(req)) { 947 ret = nvme_map_metadata(dev, req, cmnd); 948 if (ret) 949 goto out_unmap_data; 950 } 951 952 blk_mq_start_request(req); 953 nvme_submit_cmd(nvmeq, cmnd, bd->last); 954 return BLK_STS_OK; 955 out_unmap_data: 956 nvme_unmap_data(dev, req); 957 out_free_cmd: 958 nvme_cleanup_cmd(req); 959 return ret; 960 } 961 962 static void nvme_pci_complete_rq(struct request *req) 963 { 964 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 965 struct nvme_dev *dev = iod->nvmeq->dev; 966 967 if (blk_integrity_rq(req)) 968 dma_unmap_page(dev->dev, iod->meta_dma, 969 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 970 if (blk_rq_nr_phys_segments(req)) 971 nvme_unmap_data(dev, req); 972 nvme_complete_rq(req); 973 } 974 975 /* We read the CQE phase first to check if the rest of the entry is valid */ 976 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 977 { 978 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 979 980 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 981 } 982 983 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 984 { 985 u16 head = nvmeq->cq_head; 986 987 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 988 nvmeq->dbbuf_cq_ei)) 989 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 990 } 991 992 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 993 { 994 if (!nvmeq->qid) 995 return nvmeq->dev->admin_tagset.tags[0]; 996 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 997 } 998 999 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 1000 { 1001 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1002 __u16 command_id = READ_ONCE(cqe->command_id); 1003 struct request *req; 1004 1005 /* 1006 * AEN requests are special as they don't time out and can 1007 * survive any kind of queue freeze and often don't respond to 1008 * aborts. We don't even bother to allocate a struct request 1009 * for them but rather special case them here. 1010 */ 1011 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1012 nvme_complete_async_event(&nvmeq->dev->ctrl, 1013 cqe->status, &cqe->result); 1014 return; 1015 } 1016 1017 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id); 1018 if (unlikely(!req)) { 1019 dev_warn(nvmeq->dev->ctrl.device, 1020 "invalid id %d completed on queue %d\n", 1021 command_id, le16_to_cpu(cqe->sq_id)); 1022 return; 1023 } 1024 1025 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1026 if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 1027 nvme_pci_complete_rq(req); 1028 } 1029 1030 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1031 { 1032 u32 tmp = nvmeq->cq_head + 1; 1033 1034 if (tmp == nvmeq->q_depth) { 1035 nvmeq->cq_head = 0; 1036 nvmeq->cq_phase ^= 1; 1037 } else { 1038 nvmeq->cq_head = tmp; 1039 } 1040 } 1041 1042 static inline int nvme_process_cq(struct nvme_queue *nvmeq) 1043 { 1044 int found = 0; 1045 1046 while (nvme_cqe_pending(nvmeq)) { 1047 found++; 1048 /* 1049 * load-load control dependency between phase and the rest of 1050 * the cqe requires a full read memory barrier 1051 */ 1052 dma_rmb(); 1053 nvme_handle_cqe(nvmeq, nvmeq->cq_head); 1054 nvme_update_cq_head(nvmeq); 1055 } 1056 1057 if (found) 1058 nvme_ring_cq_doorbell(nvmeq); 1059 return found; 1060 } 1061 1062 static irqreturn_t nvme_irq(int irq, void *data) 1063 { 1064 struct nvme_queue *nvmeq = data; 1065 1066 if (nvme_process_cq(nvmeq)) 1067 return IRQ_HANDLED; 1068 return IRQ_NONE; 1069 } 1070 1071 static irqreturn_t nvme_irq_check(int irq, void *data) 1072 { 1073 struct nvme_queue *nvmeq = data; 1074 1075 if (nvme_cqe_pending(nvmeq)) 1076 return IRQ_WAKE_THREAD; 1077 return IRQ_NONE; 1078 } 1079 1080 /* 1081 * Poll for completions for any interrupt driven queue 1082 * Can be called from any context. 1083 */ 1084 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1085 { 1086 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1087 1088 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1089 1090 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1091 nvme_process_cq(nvmeq); 1092 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1093 } 1094 1095 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1096 { 1097 struct nvme_queue *nvmeq = hctx->driver_data; 1098 bool found; 1099 1100 if (!nvme_cqe_pending(nvmeq)) 1101 return 0; 1102 1103 spin_lock(&nvmeq->cq_poll_lock); 1104 found = nvme_process_cq(nvmeq); 1105 spin_unlock(&nvmeq->cq_poll_lock); 1106 1107 return found; 1108 } 1109 1110 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1111 { 1112 struct nvme_dev *dev = to_nvme_dev(ctrl); 1113 struct nvme_queue *nvmeq = &dev->queues[0]; 1114 struct nvme_command c = { }; 1115 1116 c.common.opcode = nvme_admin_async_event; 1117 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1118 nvme_submit_cmd(nvmeq, &c, true); 1119 } 1120 1121 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1122 { 1123 struct nvme_command c = { }; 1124 1125 c.delete_queue.opcode = opcode; 1126 c.delete_queue.qid = cpu_to_le16(id); 1127 1128 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1129 } 1130 1131 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1132 struct nvme_queue *nvmeq, s16 vector) 1133 { 1134 struct nvme_command c = { }; 1135 int flags = NVME_QUEUE_PHYS_CONTIG; 1136 1137 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1138 flags |= NVME_CQ_IRQ_ENABLED; 1139 1140 /* 1141 * Note: we (ab)use the fact that the prp fields survive if no data 1142 * is attached to the request. 1143 */ 1144 c.create_cq.opcode = nvme_admin_create_cq; 1145 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1146 c.create_cq.cqid = cpu_to_le16(qid); 1147 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1148 c.create_cq.cq_flags = cpu_to_le16(flags); 1149 c.create_cq.irq_vector = cpu_to_le16(vector); 1150 1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1152 } 1153 1154 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1155 struct nvme_queue *nvmeq) 1156 { 1157 struct nvme_ctrl *ctrl = &dev->ctrl; 1158 struct nvme_command c = { }; 1159 int flags = NVME_QUEUE_PHYS_CONTIG; 1160 1161 /* 1162 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1163 * set. Since URGENT priority is zeroes, it makes all queues 1164 * URGENT. 1165 */ 1166 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1167 flags |= NVME_SQ_PRIO_MEDIUM; 1168 1169 /* 1170 * Note: we (ab)use the fact that the prp fields survive if no data 1171 * is attached to the request. 1172 */ 1173 c.create_sq.opcode = nvme_admin_create_sq; 1174 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1175 c.create_sq.sqid = cpu_to_le16(qid); 1176 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1177 c.create_sq.sq_flags = cpu_to_le16(flags); 1178 c.create_sq.cqid = cpu_to_le16(qid); 1179 1180 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1181 } 1182 1183 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1184 { 1185 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1186 } 1187 1188 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1189 { 1190 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1191 } 1192 1193 static void abort_endio(struct request *req, blk_status_t error) 1194 { 1195 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1196 struct nvme_queue *nvmeq = iod->nvmeq; 1197 1198 dev_warn(nvmeq->dev->ctrl.device, 1199 "Abort status: 0x%x", nvme_req(req)->status); 1200 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1201 blk_mq_free_request(req); 1202 } 1203 1204 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1205 { 1206 /* If true, indicates loss of adapter communication, possibly by a 1207 * NVMe Subsystem reset. 1208 */ 1209 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1210 1211 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1212 switch (dev->ctrl.state) { 1213 case NVME_CTRL_RESETTING: 1214 case NVME_CTRL_CONNECTING: 1215 return false; 1216 default: 1217 break; 1218 } 1219 1220 /* We shouldn't reset unless the controller is on fatal error state 1221 * _or_ if we lost the communication with it. 1222 */ 1223 if (!(csts & NVME_CSTS_CFS) && !nssro) 1224 return false; 1225 1226 return true; 1227 } 1228 1229 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1230 { 1231 /* Read a config register to help see what died. */ 1232 u16 pci_status; 1233 int result; 1234 1235 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1236 &pci_status); 1237 if (result == PCIBIOS_SUCCESSFUL) 1238 dev_warn(dev->ctrl.device, 1239 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1240 csts, pci_status); 1241 else 1242 dev_warn(dev->ctrl.device, 1243 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1244 csts, result); 1245 } 1246 1247 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1248 { 1249 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1250 struct nvme_queue *nvmeq = iod->nvmeq; 1251 struct nvme_dev *dev = nvmeq->dev; 1252 struct request *abort_req; 1253 struct nvme_command cmd = { }; 1254 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1255 1256 /* If PCI error recovery process is happening, we cannot reset or 1257 * the recovery mechanism will surely fail. 1258 */ 1259 mb(); 1260 if (pci_channel_offline(to_pci_dev(dev->dev))) 1261 return BLK_EH_RESET_TIMER; 1262 1263 /* 1264 * Reset immediately if the controller is failed 1265 */ 1266 if (nvme_should_reset(dev, csts)) { 1267 nvme_warn_reset(dev, csts); 1268 nvme_dev_disable(dev, false); 1269 nvme_reset_ctrl(&dev->ctrl); 1270 return BLK_EH_DONE; 1271 } 1272 1273 /* 1274 * Did we miss an interrupt? 1275 */ 1276 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1277 nvme_poll(req->mq_hctx); 1278 else 1279 nvme_poll_irqdisable(nvmeq); 1280 1281 if (blk_mq_request_completed(req)) { 1282 dev_warn(dev->ctrl.device, 1283 "I/O %d QID %d timeout, completion polled\n", 1284 req->tag, nvmeq->qid); 1285 return BLK_EH_DONE; 1286 } 1287 1288 /* 1289 * Shutdown immediately if controller times out while starting. The 1290 * reset work will see the pci device disabled when it gets the forced 1291 * cancellation error. All outstanding requests are completed on 1292 * shutdown, so we return BLK_EH_DONE. 1293 */ 1294 switch (dev->ctrl.state) { 1295 case NVME_CTRL_CONNECTING: 1296 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1297 fallthrough; 1298 case NVME_CTRL_DELETING: 1299 dev_warn_ratelimited(dev->ctrl.device, 1300 "I/O %d QID %d timeout, disable controller\n", 1301 req->tag, nvmeq->qid); 1302 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1303 nvme_dev_disable(dev, true); 1304 return BLK_EH_DONE; 1305 case NVME_CTRL_RESETTING: 1306 return BLK_EH_RESET_TIMER; 1307 default: 1308 break; 1309 } 1310 1311 /* 1312 * Shutdown the controller immediately and schedule a reset if the 1313 * command was already aborted once before and still hasn't been 1314 * returned to the driver, or if this is the admin queue. 1315 */ 1316 if (!nvmeq->qid || iod->aborted) { 1317 dev_warn(dev->ctrl.device, 1318 "I/O %d QID %d timeout, reset controller\n", 1319 req->tag, nvmeq->qid); 1320 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1321 nvme_dev_disable(dev, false); 1322 nvme_reset_ctrl(&dev->ctrl); 1323 1324 return BLK_EH_DONE; 1325 } 1326 1327 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1328 atomic_inc(&dev->ctrl.abort_limit); 1329 return BLK_EH_RESET_TIMER; 1330 } 1331 iod->aborted = 1; 1332 1333 cmd.abort.opcode = nvme_admin_abort_cmd; 1334 cmd.abort.cid = req->tag; 1335 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1336 1337 dev_warn(nvmeq->dev->ctrl.device, 1338 "I/O %d QID %d timeout, aborting\n", 1339 req->tag, nvmeq->qid); 1340 1341 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1342 BLK_MQ_REQ_NOWAIT); 1343 if (IS_ERR(abort_req)) { 1344 atomic_inc(&dev->ctrl.abort_limit); 1345 return BLK_EH_RESET_TIMER; 1346 } 1347 1348 abort_req->end_io_data = NULL; 1349 blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio); 1350 1351 /* 1352 * The aborted req will be completed on receiving the abort req. 1353 * We enable the timer again. If hit twice, it'll cause a device reset, 1354 * as the device then is in a faulty state. 1355 */ 1356 return BLK_EH_RESET_TIMER; 1357 } 1358 1359 static void nvme_free_queue(struct nvme_queue *nvmeq) 1360 { 1361 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1362 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1363 if (!nvmeq->sq_cmds) 1364 return; 1365 1366 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1367 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1368 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1369 } else { 1370 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1371 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1372 } 1373 } 1374 1375 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1376 { 1377 int i; 1378 1379 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1380 dev->ctrl.queue_count--; 1381 nvme_free_queue(&dev->queues[i]); 1382 } 1383 } 1384 1385 /** 1386 * nvme_suspend_queue - put queue into suspended state 1387 * @nvmeq: queue to suspend 1388 */ 1389 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1390 { 1391 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1392 return 1; 1393 1394 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1395 mb(); 1396 1397 nvmeq->dev->online_queues--; 1398 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1399 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1400 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1401 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1402 return 0; 1403 } 1404 1405 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1406 { 1407 int i; 1408 1409 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1410 nvme_suspend_queue(&dev->queues[i]); 1411 } 1412 1413 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1414 { 1415 struct nvme_queue *nvmeq = &dev->queues[0]; 1416 1417 if (shutdown) 1418 nvme_shutdown_ctrl(&dev->ctrl); 1419 else 1420 nvme_disable_ctrl(&dev->ctrl); 1421 1422 nvme_poll_irqdisable(nvmeq); 1423 } 1424 1425 /* 1426 * Called only on a device that has been disabled and after all other threads 1427 * that can check this device's completion queues have synced, except 1428 * nvme_poll(). This is the last chance for the driver to see a natural 1429 * completion before nvme_cancel_request() terminates all incomplete requests. 1430 */ 1431 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1432 { 1433 int i; 1434 1435 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1436 spin_lock(&dev->queues[i].cq_poll_lock); 1437 nvme_process_cq(&dev->queues[i]); 1438 spin_unlock(&dev->queues[i].cq_poll_lock); 1439 } 1440 } 1441 1442 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1443 int entry_size) 1444 { 1445 int q_depth = dev->q_depth; 1446 unsigned q_size_aligned = roundup(q_depth * entry_size, 1447 NVME_CTRL_PAGE_SIZE); 1448 1449 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1450 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1451 1452 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1453 q_depth = div_u64(mem_per_q, entry_size); 1454 1455 /* 1456 * Ensure the reduced q_depth is above some threshold where it 1457 * would be better to map queues in system memory with the 1458 * original depth 1459 */ 1460 if (q_depth < 64) 1461 return -ENOMEM; 1462 } 1463 1464 return q_depth; 1465 } 1466 1467 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1468 int qid) 1469 { 1470 struct pci_dev *pdev = to_pci_dev(dev->dev); 1471 1472 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1473 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1474 if (nvmeq->sq_cmds) { 1475 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1476 nvmeq->sq_cmds); 1477 if (nvmeq->sq_dma_addr) { 1478 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1479 return 0; 1480 } 1481 1482 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1483 } 1484 } 1485 1486 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1487 &nvmeq->sq_dma_addr, GFP_KERNEL); 1488 if (!nvmeq->sq_cmds) 1489 return -ENOMEM; 1490 return 0; 1491 } 1492 1493 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1494 { 1495 struct nvme_queue *nvmeq = &dev->queues[qid]; 1496 1497 if (dev->ctrl.queue_count > qid) 1498 return 0; 1499 1500 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1501 nvmeq->q_depth = depth; 1502 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1503 &nvmeq->cq_dma_addr, GFP_KERNEL); 1504 if (!nvmeq->cqes) 1505 goto free_nvmeq; 1506 1507 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1508 goto free_cqdma; 1509 1510 nvmeq->dev = dev; 1511 spin_lock_init(&nvmeq->sq_lock); 1512 spin_lock_init(&nvmeq->cq_poll_lock); 1513 nvmeq->cq_head = 0; 1514 nvmeq->cq_phase = 1; 1515 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1516 nvmeq->qid = qid; 1517 dev->ctrl.queue_count++; 1518 1519 return 0; 1520 1521 free_cqdma: 1522 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1523 nvmeq->cq_dma_addr); 1524 free_nvmeq: 1525 return -ENOMEM; 1526 } 1527 1528 static int queue_request_irq(struct nvme_queue *nvmeq) 1529 { 1530 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1531 int nr = nvmeq->dev->ctrl.instance; 1532 1533 if (use_threaded_interrupts) { 1534 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1535 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1536 } else { 1537 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1538 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1539 } 1540 } 1541 1542 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1543 { 1544 struct nvme_dev *dev = nvmeq->dev; 1545 1546 nvmeq->sq_tail = 0; 1547 nvmeq->last_sq_tail = 0; 1548 nvmeq->cq_head = 0; 1549 nvmeq->cq_phase = 1; 1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1551 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1552 nvme_dbbuf_init(dev, nvmeq, qid); 1553 dev->online_queues++; 1554 wmb(); /* ensure the first interrupt sees the initialization */ 1555 } 1556 1557 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1558 { 1559 struct nvme_dev *dev = nvmeq->dev; 1560 int result; 1561 u16 vector = 0; 1562 1563 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1564 1565 /* 1566 * A queue's vector matches the queue identifier unless the controller 1567 * has only one vector available. 1568 */ 1569 if (!polled) 1570 vector = dev->num_vecs == 1 ? 0 : qid; 1571 else 1572 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1573 1574 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1575 if (result) 1576 return result; 1577 1578 result = adapter_alloc_sq(dev, qid, nvmeq); 1579 if (result < 0) 1580 return result; 1581 if (result) 1582 goto release_cq; 1583 1584 nvmeq->cq_vector = vector; 1585 nvme_init_queue(nvmeq, qid); 1586 1587 if (!polled) { 1588 result = queue_request_irq(nvmeq); 1589 if (result < 0) 1590 goto release_sq; 1591 } 1592 1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1594 return result; 1595 1596 release_sq: 1597 dev->online_queues--; 1598 adapter_delete_sq(dev, qid); 1599 release_cq: 1600 adapter_delete_cq(dev, qid); 1601 return result; 1602 } 1603 1604 static const struct blk_mq_ops nvme_mq_admin_ops = { 1605 .queue_rq = nvme_queue_rq, 1606 .complete = nvme_pci_complete_rq, 1607 .init_hctx = nvme_admin_init_hctx, 1608 .init_request = nvme_init_request, 1609 .timeout = nvme_timeout, 1610 }; 1611 1612 static const struct blk_mq_ops nvme_mq_ops = { 1613 .queue_rq = nvme_queue_rq, 1614 .complete = nvme_pci_complete_rq, 1615 .commit_rqs = nvme_commit_rqs, 1616 .init_hctx = nvme_init_hctx, 1617 .init_request = nvme_init_request, 1618 .map_queues = nvme_pci_map_queues, 1619 .timeout = nvme_timeout, 1620 .poll = nvme_poll, 1621 }; 1622 1623 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1624 { 1625 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1626 /* 1627 * If the controller was reset during removal, it's possible 1628 * user requests may be waiting on a stopped queue. Start the 1629 * queue to flush these to completion. 1630 */ 1631 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1632 blk_cleanup_queue(dev->ctrl.admin_q); 1633 blk_mq_free_tag_set(&dev->admin_tagset); 1634 } 1635 } 1636 1637 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1638 { 1639 if (!dev->ctrl.admin_q) { 1640 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1641 dev->admin_tagset.nr_hw_queues = 1; 1642 1643 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1644 dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1645 dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1646 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1647 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1648 dev->admin_tagset.driver_data = dev; 1649 1650 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1651 return -ENOMEM; 1652 dev->ctrl.admin_tagset = &dev->admin_tagset; 1653 1654 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1655 if (IS_ERR(dev->ctrl.admin_q)) { 1656 blk_mq_free_tag_set(&dev->admin_tagset); 1657 return -ENOMEM; 1658 } 1659 if (!blk_get_queue(dev->ctrl.admin_q)) { 1660 nvme_dev_remove_admin(dev); 1661 dev->ctrl.admin_q = NULL; 1662 return -ENODEV; 1663 } 1664 } else 1665 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1666 1667 return 0; 1668 } 1669 1670 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1671 { 1672 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1673 } 1674 1675 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1676 { 1677 struct pci_dev *pdev = to_pci_dev(dev->dev); 1678 1679 if (size <= dev->bar_mapped_size) 1680 return 0; 1681 if (size > pci_resource_len(pdev, 0)) 1682 return -ENOMEM; 1683 if (dev->bar) 1684 iounmap(dev->bar); 1685 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1686 if (!dev->bar) { 1687 dev->bar_mapped_size = 0; 1688 return -ENOMEM; 1689 } 1690 dev->bar_mapped_size = size; 1691 dev->dbs = dev->bar + NVME_REG_DBS; 1692 1693 return 0; 1694 } 1695 1696 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1697 { 1698 int result; 1699 u32 aqa; 1700 struct nvme_queue *nvmeq; 1701 1702 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1703 if (result < 0) 1704 return result; 1705 1706 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1707 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1708 1709 if (dev->subsystem && 1710 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1711 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1712 1713 result = nvme_disable_ctrl(&dev->ctrl); 1714 if (result < 0) 1715 return result; 1716 1717 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1718 if (result) 1719 return result; 1720 1721 dev->ctrl.numa_node = dev_to_node(dev->dev); 1722 1723 nvmeq = &dev->queues[0]; 1724 aqa = nvmeq->q_depth - 1; 1725 aqa |= aqa << 16; 1726 1727 writel(aqa, dev->bar + NVME_REG_AQA); 1728 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1729 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1730 1731 result = nvme_enable_ctrl(&dev->ctrl); 1732 if (result) 1733 return result; 1734 1735 nvmeq->cq_vector = 0; 1736 nvme_init_queue(nvmeq, 0); 1737 result = queue_request_irq(nvmeq); 1738 if (result) { 1739 dev->online_queues--; 1740 return result; 1741 } 1742 1743 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1744 return result; 1745 } 1746 1747 static int nvme_create_io_queues(struct nvme_dev *dev) 1748 { 1749 unsigned i, max, rw_queues; 1750 int ret = 0; 1751 1752 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1753 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1754 ret = -ENOMEM; 1755 break; 1756 } 1757 } 1758 1759 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1760 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1761 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1762 dev->io_queues[HCTX_TYPE_READ]; 1763 } else { 1764 rw_queues = max; 1765 } 1766 1767 for (i = dev->online_queues; i <= max; i++) { 1768 bool polled = i > rw_queues; 1769 1770 ret = nvme_create_queue(&dev->queues[i], i, polled); 1771 if (ret) 1772 break; 1773 } 1774 1775 /* 1776 * Ignore failing Create SQ/CQ commands, we can continue with less 1777 * than the desired amount of queues, and even a controller without 1778 * I/O queues can still be used to issue admin commands. This might 1779 * be useful to upgrade a buggy firmware for example. 1780 */ 1781 return ret >= 0 ? 0 : ret; 1782 } 1783 1784 static ssize_t nvme_cmb_show(struct device *dev, 1785 struct device_attribute *attr, 1786 char *buf) 1787 { 1788 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1789 1790 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1791 ndev->cmbloc, ndev->cmbsz); 1792 } 1793 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1794 1795 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1796 { 1797 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1798 1799 return 1ULL << (12 + 4 * szu); 1800 } 1801 1802 static u32 nvme_cmb_size(struct nvme_dev *dev) 1803 { 1804 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1805 } 1806 1807 static void nvme_map_cmb(struct nvme_dev *dev) 1808 { 1809 u64 size, offset; 1810 resource_size_t bar_size; 1811 struct pci_dev *pdev = to_pci_dev(dev->dev); 1812 int bar; 1813 1814 if (dev->cmb_size) 1815 return; 1816 1817 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1818 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1819 1820 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1821 if (!dev->cmbsz) 1822 return; 1823 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1824 1825 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1826 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1827 bar = NVME_CMB_BIR(dev->cmbloc); 1828 bar_size = pci_resource_len(pdev, bar); 1829 1830 if (offset > bar_size) 1831 return; 1832 1833 /* 1834 * Tell the controller about the host side address mapping the CMB, 1835 * and enable CMB decoding for the NVMe 1.4+ scheme: 1836 */ 1837 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1838 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1839 (pci_bus_address(pdev, bar) + offset), 1840 dev->bar + NVME_REG_CMBMSC); 1841 } 1842 1843 /* 1844 * Controllers may support a CMB size larger than their BAR, 1845 * for example, due to being behind a bridge. Reduce the CMB to 1846 * the reported size of the BAR 1847 */ 1848 if (size > bar_size - offset) 1849 size = bar_size - offset; 1850 1851 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1852 dev_warn(dev->ctrl.device, 1853 "failed to register the CMB\n"); 1854 return; 1855 } 1856 1857 dev->cmb_size = size; 1858 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1859 1860 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1861 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1862 pci_p2pmem_publish(pdev, true); 1863 1864 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1865 &dev_attr_cmb.attr, NULL)) 1866 dev_warn(dev->ctrl.device, 1867 "failed to add sysfs attribute for CMB\n"); 1868 } 1869 1870 static inline void nvme_release_cmb(struct nvme_dev *dev) 1871 { 1872 if (dev->cmb_size) { 1873 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1874 &dev_attr_cmb.attr, NULL); 1875 dev->cmb_size = 0; 1876 } 1877 } 1878 1879 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1880 { 1881 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1882 u64 dma_addr = dev->host_mem_descs_dma; 1883 struct nvme_command c = { }; 1884 int ret; 1885 1886 c.features.opcode = nvme_admin_set_features; 1887 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1888 c.features.dword11 = cpu_to_le32(bits); 1889 c.features.dword12 = cpu_to_le32(host_mem_size); 1890 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1891 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1892 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1893 1894 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1895 if (ret) { 1896 dev_warn(dev->ctrl.device, 1897 "failed to set host mem (err %d, flags %#x).\n", 1898 ret, bits); 1899 } 1900 return ret; 1901 } 1902 1903 static void nvme_free_host_mem(struct nvme_dev *dev) 1904 { 1905 int i; 1906 1907 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1908 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1909 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 1910 1911 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1912 le64_to_cpu(desc->addr), 1913 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1914 } 1915 1916 kfree(dev->host_mem_desc_bufs); 1917 dev->host_mem_desc_bufs = NULL; 1918 dma_free_coherent(dev->dev, 1919 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1920 dev->host_mem_descs, dev->host_mem_descs_dma); 1921 dev->host_mem_descs = NULL; 1922 dev->nr_host_mem_descs = 0; 1923 } 1924 1925 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1926 u32 chunk_size) 1927 { 1928 struct nvme_host_mem_buf_desc *descs; 1929 u32 max_entries, len; 1930 dma_addr_t descs_dma; 1931 int i = 0; 1932 void **bufs; 1933 u64 size, tmp; 1934 1935 tmp = (preferred + chunk_size - 1); 1936 do_div(tmp, chunk_size); 1937 max_entries = tmp; 1938 1939 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1940 max_entries = dev->ctrl.hmmaxd; 1941 1942 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1943 &descs_dma, GFP_KERNEL); 1944 if (!descs) 1945 goto out; 1946 1947 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1948 if (!bufs) 1949 goto out_free_descs; 1950 1951 for (size = 0; size < preferred && i < max_entries; size += len) { 1952 dma_addr_t dma_addr; 1953 1954 len = min_t(u64, chunk_size, preferred - size); 1955 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1956 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1957 if (!bufs[i]) 1958 break; 1959 1960 descs[i].addr = cpu_to_le64(dma_addr); 1961 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 1962 i++; 1963 } 1964 1965 if (!size) 1966 goto out_free_bufs; 1967 1968 dev->nr_host_mem_descs = i; 1969 dev->host_mem_size = size; 1970 dev->host_mem_descs = descs; 1971 dev->host_mem_descs_dma = descs_dma; 1972 dev->host_mem_desc_bufs = bufs; 1973 return 0; 1974 1975 out_free_bufs: 1976 while (--i >= 0) { 1977 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 1978 1979 dma_free_attrs(dev->dev, size, bufs[i], 1980 le64_to_cpu(descs[i].addr), 1981 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1982 } 1983 1984 kfree(bufs); 1985 out_free_descs: 1986 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1987 descs_dma); 1988 out: 1989 dev->host_mem_descs = NULL; 1990 return -ENOMEM; 1991 } 1992 1993 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1994 { 1995 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1996 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1997 u64 chunk_size; 1998 1999 /* start big and work our way down */ 2000 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2001 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2002 if (!min || dev->host_mem_size >= min) 2003 return 0; 2004 nvme_free_host_mem(dev); 2005 } 2006 } 2007 2008 return -ENOMEM; 2009 } 2010 2011 static int nvme_setup_host_mem(struct nvme_dev *dev) 2012 { 2013 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2014 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2015 u64 min = (u64)dev->ctrl.hmmin * 4096; 2016 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2017 int ret; 2018 2019 preferred = min(preferred, max); 2020 if (min > max) { 2021 dev_warn(dev->ctrl.device, 2022 "min host memory (%lld MiB) above limit (%d MiB).\n", 2023 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2024 nvme_free_host_mem(dev); 2025 return 0; 2026 } 2027 2028 /* 2029 * If we already have a buffer allocated check if we can reuse it. 2030 */ 2031 if (dev->host_mem_descs) { 2032 if (dev->host_mem_size >= min) 2033 enable_bits |= NVME_HOST_MEM_RETURN; 2034 else 2035 nvme_free_host_mem(dev); 2036 } 2037 2038 if (!dev->host_mem_descs) { 2039 if (nvme_alloc_host_mem(dev, min, preferred)) { 2040 dev_warn(dev->ctrl.device, 2041 "failed to allocate host memory buffer.\n"); 2042 return 0; /* controller must work without HMB */ 2043 } 2044 2045 dev_info(dev->ctrl.device, 2046 "allocated %lld MiB host memory buffer.\n", 2047 dev->host_mem_size >> ilog2(SZ_1M)); 2048 } 2049 2050 ret = nvme_set_host_mem(dev, enable_bits); 2051 if (ret) 2052 nvme_free_host_mem(dev); 2053 return ret; 2054 } 2055 2056 /* 2057 * nirqs is the number of interrupts available for write and read 2058 * queues. The core already reserved an interrupt for the admin queue. 2059 */ 2060 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2061 { 2062 struct nvme_dev *dev = affd->priv; 2063 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2064 2065 /* 2066 * If there is no interrupt available for queues, ensure that 2067 * the default queue is set to 1. The affinity set size is 2068 * also set to one, but the irq core ignores it for this case. 2069 * 2070 * If only one interrupt is available or 'write_queue' == 0, combine 2071 * write and read queues. 2072 * 2073 * If 'write_queues' > 0, ensure it leaves room for at least one read 2074 * queue. 2075 */ 2076 if (!nrirqs) { 2077 nrirqs = 1; 2078 nr_read_queues = 0; 2079 } else if (nrirqs == 1 || !nr_write_queues) { 2080 nr_read_queues = 0; 2081 } else if (nr_write_queues >= nrirqs) { 2082 nr_read_queues = 1; 2083 } else { 2084 nr_read_queues = nrirqs - nr_write_queues; 2085 } 2086 2087 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2088 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2089 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2090 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2091 affd->nr_sets = nr_read_queues ? 2 : 1; 2092 } 2093 2094 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2095 { 2096 struct pci_dev *pdev = to_pci_dev(dev->dev); 2097 struct irq_affinity affd = { 2098 .pre_vectors = 1, 2099 .calc_sets = nvme_calc_irq_sets, 2100 .priv = dev, 2101 }; 2102 unsigned int irq_queues, poll_queues; 2103 2104 /* 2105 * Poll queues don't need interrupts, but we need at least one I/O queue 2106 * left over for non-polled I/O. 2107 */ 2108 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2109 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2110 2111 /* 2112 * Initialize for the single interrupt case, will be updated in 2113 * nvme_calc_irq_sets(). 2114 */ 2115 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2116 dev->io_queues[HCTX_TYPE_READ] = 0; 2117 2118 /* 2119 * We need interrupts for the admin queue and each non-polled I/O queue, 2120 * but some Apple controllers require all queues to use the first 2121 * vector. 2122 */ 2123 irq_queues = 1; 2124 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2125 irq_queues += (nr_io_queues - poll_queues); 2126 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2127 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2128 } 2129 2130 static void nvme_disable_io_queues(struct nvme_dev *dev) 2131 { 2132 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2133 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2134 } 2135 2136 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2137 { 2138 /* 2139 * If tags are shared with admin queue (Apple bug), then 2140 * make sure we only use one IO queue. 2141 */ 2142 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2143 return 1; 2144 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2145 } 2146 2147 static int nvme_setup_io_queues(struct nvme_dev *dev) 2148 { 2149 struct nvme_queue *adminq = &dev->queues[0]; 2150 struct pci_dev *pdev = to_pci_dev(dev->dev); 2151 unsigned int nr_io_queues; 2152 unsigned long size; 2153 int result; 2154 2155 /* 2156 * Sample the module parameters once at reset time so that we have 2157 * stable values to work with. 2158 */ 2159 dev->nr_write_queues = write_queues; 2160 dev->nr_poll_queues = poll_queues; 2161 2162 nr_io_queues = dev->nr_allocated_queues - 1; 2163 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2164 if (result < 0) 2165 return result; 2166 2167 if (nr_io_queues == 0) 2168 return 0; 2169 2170 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2171 2172 if (dev->cmb_use_sqes) { 2173 result = nvme_cmb_qdepth(dev, nr_io_queues, 2174 sizeof(struct nvme_command)); 2175 if (result > 0) 2176 dev->q_depth = result; 2177 else 2178 dev->cmb_use_sqes = false; 2179 } 2180 2181 do { 2182 size = db_bar_size(dev, nr_io_queues); 2183 result = nvme_remap_bar(dev, size); 2184 if (!result) 2185 break; 2186 if (!--nr_io_queues) 2187 return -ENOMEM; 2188 } while (1); 2189 adminq->q_db = dev->dbs; 2190 2191 retry: 2192 /* Deregister the admin queue's interrupt */ 2193 pci_free_irq(pdev, 0, adminq); 2194 2195 /* 2196 * If we enable msix early due to not intx, disable it again before 2197 * setting up the full range we need. 2198 */ 2199 pci_free_irq_vectors(pdev); 2200 2201 result = nvme_setup_irqs(dev, nr_io_queues); 2202 if (result <= 0) 2203 return -EIO; 2204 2205 dev->num_vecs = result; 2206 result = max(result - 1, 1); 2207 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2208 2209 /* 2210 * Should investigate if there's a performance win from allocating 2211 * more queues than interrupt vectors; it might allow the submission 2212 * path to scale better, even if the receive path is limited by the 2213 * number of interrupts. 2214 */ 2215 result = queue_request_irq(adminq); 2216 if (result) 2217 return result; 2218 set_bit(NVMEQ_ENABLED, &adminq->flags); 2219 2220 result = nvme_create_io_queues(dev); 2221 if (result || dev->online_queues < 2) 2222 return result; 2223 2224 if (dev->online_queues - 1 < dev->max_qid) { 2225 nr_io_queues = dev->online_queues - 1; 2226 nvme_disable_io_queues(dev); 2227 nvme_suspend_io_queues(dev); 2228 goto retry; 2229 } 2230 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2231 dev->io_queues[HCTX_TYPE_DEFAULT], 2232 dev->io_queues[HCTX_TYPE_READ], 2233 dev->io_queues[HCTX_TYPE_POLL]); 2234 return 0; 2235 } 2236 2237 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2238 { 2239 struct nvme_queue *nvmeq = req->end_io_data; 2240 2241 blk_mq_free_request(req); 2242 complete(&nvmeq->delete_done); 2243 } 2244 2245 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2246 { 2247 struct nvme_queue *nvmeq = req->end_io_data; 2248 2249 if (error) 2250 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2251 2252 nvme_del_queue_end(req, error); 2253 } 2254 2255 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2256 { 2257 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2258 struct request *req; 2259 struct nvme_command cmd = { }; 2260 2261 cmd.delete_queue.opcode = opcode; 2262 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2263 2264 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2265 if (IS_ERR(req)) 2266 return PTR_ERR(req); 2267 2268 req->end_io_data = nvmeq; 2269 2270 init_completion(&nvmeq->delete_done); 2271 blk_execute_rq_nowait(NULL, req, false, 2272 opcode == nvme_admin_delete_cq ? 2273 nvme_del_cq_end : nvme_del_queue_end); 2274 return 0; 2275 } 2276 2277 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2278 { 2279 int nr_queues = dev->online_queues - 1, sent = 0; 2280 unsigned long timeout; 2281 2282 retry: 2283 timeout = NVME_ADMIN_TIMEOUT; 2284 while (nr_queues > 0) { 2285 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2286 break; 2287 nr_queues--; 2288 sent++; 2289 } 2290 while (sent) { 2291 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2292 2293 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2294 timeout); 2295 if (timeout == 0) 2296 return false; 2297 2298 sent--; 2299 if (nr_queues) 2300 goto retry; 2301 } 2302 return true; 2303 } 2304 2305 static void nvme_dev_add(struct nvme_dev *dev) 2306 { 2307 int ret; 2308 2309 if (!dev->ctrl.tagset) { 2310 dev->tagset.ops = &nvme_mq_ops; 2311 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2312 dev->tagset.nr_maps = 2; /* default + read */ 2313 if (dev->io_queues[HCTX_TYPE_POLL]) 2314 dev->tagset.nr_maps++; 2315 dev->tagset.timeout = NVME_IO_TIMEOUT; 2316 dev->tagset.numa_node = dev->ctrl.numa_node; 2317 dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 2318 BLK_MQ_MAX_DEPTH) - 1; 2319 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2320 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2321 dev->tagset.driver_data = dev; 2322 2323 /* 2324 * Some Apple controllers requires tags to be unique 2325 * across admin and IO queue, so reserve the first 32 2326 * tags of the IO queue. 2327 */ 2328 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2329 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2330 2331 ret = blk_mq_alloc_tag_set(&dev->tagset); 2332 if (ret) { 2333 dev_warn(dev->ctrl.device, 2334 "IO queues tagset allocation failed %d\n", ret); 2335 return; 2336 } 2337 dev->ctrl.tagset = &dev->tagset; 2338 } else { 2339 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2340 2341 /* Free previously allocated queues that are no longer usable */ 2342 nvme_free_queues(dev, dev->online_queues); 2343 } 2344 2345 nvme_dbbuf_set(dev); 2346 } 2347 2348 static int nvme_pci_enable(struct nvme_dev *dev) 2349 { 2350 int result = -ENOMEM; 2351 struct pci_dev *pdev = to_pci_dev(dev->dev); 2352 int dma_address_bits = 64; 2353 2354 if (pci_enable_device_mem(pdev)) 2355 return result; 2356 2357 pci_set_master(pdev); 2358 2359 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 2360 dma_address_bits = 48; 2361 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 2362 goto disable; 2363 2364 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2365 result = -ENODEV; 2366 goto disable; 2367 } 2368 2369 /* 2370 * Some devices and/or platforms don't advertise or work with INTx 2371 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2372 * adjust this later. 2373 */ 2374 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2375 if (result < 0) 2376 return result; 2377 2378 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2379 2380 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2381 io_queue_depth); 2382 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2383 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2384 dev->dbs = dev->bar + 4096; 2385 2386 /* 2387 * Some Apple controllers require a non-standard SQE size. 2388 * Interestingly they also seem to ignore the CC:IOSQES register 2389 * so we don't bother updating it here. 2390 */ 2391 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2392 dev->io_sqes = 7; 2393 else 2394 dev->io_sqes = NVME_NVM_IOSQES; 2395 2396 /* 2397 * Temporary fix for the Apple controller found in the MacBook8,1 and 2398 * some MacBook7,1 to avoid controller resets and data loss. 2399 */ 2400 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2401 dev->q_depth = 2; 2402 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2403 "set queue depth=%u to work around controller resets\n", 2404 dev->q_depth); 2405 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2406 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2407 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2408 dev->q_depth = 64; 2409 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2410 "set queue depth=%u\n", dev->q_depth); 2411 } 2412 2413 /* 2414 * Controllers with the shared tags quirk need the IO queue to be 2415 * big enough so that we get 32 tags for the admin queue 2416 */ 2417 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2418 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2419 dev->q_depth = NVME_AQ_DEPTH + 2; 2420 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2421 dev->q_depth); 2422 } 2423 2424 2425 nvme_map_cmb(dev); 2426 2427 pci_enable_pcie_error_reporting(pdev); 2428 pci_save_state(pdev); 2429 return 0; 2430 2431 disable: 2432 pci_disable_device(pdev); 2433 return result; 2434 } 2435 2436 static void nvme_dev_unmap(struct nvme_dev *dev) 2437 { 2438 if (dev->bar) 2439 iounmap(dev->bar); 2440 pci_release_mem_regions(to_pci_dev(dev->dev)); 2441 } 2442 2443 static void nvme_pci_disable(struct nvme_dev *dev) 2444 { 2445 struct pci_dev *pdev = to_pci_dev(dev->dev); 2446 2447 pci_free_irq_vectors(pdev); 2448 2449 if (pci_is_enabled(pdev)) { 2450 pci_disable_pcie_error_reporting(pdev); 2451 pci_disable_device(pdev); 2452 } 2453 } 2454 2455 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2456 { 2457 bool dead = true, freeze = false; 2458 struct pci_dev *pdev = to_pci_dev(dev->dev); 2459 2460 mutex_lock(&dev->shutdown_lock); 2461 if (pci_is_enabled(pdev)) { 2462 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2463 2464 if (dev->ctrl.state == NVME_CTRL_LIVE || 2465 dev->ctrl.state == NVME_CTRL_RESETTING) { 2466 freeze = true; 2467 nvme_start_freeze(&dev->ctrl); 2468 } 2469 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2470 pdev->error_state != pci_channel_io_normal); 2471 } 2472 2473 /* 2474 * Give the controller a chance to complete all entered requests if 2475 * doing a safe shutdown. 2476 */ 2477 if (!dead && shutdown && freeze) 2478 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2479 2480 nvme_stop_queues(&dev->ctrl); 2481 2482 if (!dead && dev->ctrl.queue_count > 0) { 2483 nvme_disable_io_queues(dev); 2484 nvme_disable_admin_queue(dev, shutdown); 2485 } 2486 nvme_suspend_io_queues(dev); 2487 nvme_suspend_queue(&dev->queues[0]); 2488 nvme_pci_disable(dev); 2489 nvme_reap_pending_cqes(dev); 2490 2491 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2492 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2493 blk_mq_tagset_wait_completed_request(&dev->tagset); 2494 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2495 2496 /* 2497 * The driver will not be starting up queues again if shutting down so 2498 * must flush all entered requests to their failed completion to avoid 2499 * deadlocking blk-mq hot-cpu notifier. 2500 */ 2501 if (shutdown) { 2502 nvme_start_queues(&dev->ctrl); 2503 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2504 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2505 } 2506 mutex_unlock(&dev->shutdown_lock); 2507 } 2508 2509 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2510 { 2511 if (!nvme_wait_reset(&dev->ctrl)) 2512 return -EBUSY; 2513 nvme_dev_disable(dev, shutdown); 2514 return 0; 2515 } 2516 2517 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2518 { 2519 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2520 NVME_CTRL_PAGE_SIZE, 2521 NVME_CTRL_PAGE_SIZE, 0); 2522 if (!dev->prp_page_pool) 2523 return -ENOMEM; 2524 2525 /* Optimisation for I/Os between 4k and 128k */ 2526 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2527 256, 256, 0); 2528 if (!dev->prp_small_pool) { 2529 dma_pool_destroy(dev->prp_page_pool); 2530 return -ENOMEM; 2531 } 2532 return 0; 2533 } 2534 2535 static void nvme_release_prp_pools(struct nvme_dev *dev) 2536 { 2537 dma_pool_destroy(dev->prp_page_pool); 2538 dma_pool_destroy(dev->prp_small_pool); 2539 } 2540 2541 static void nvme_free_tagset(struct nvme_dev *dev) 2542 { 2543 if (dev->tagset.tags) 2544 blk_mq_free_tag_set(&dev->tagset); 2545 dev->ctrl.tagset = NULL; 2546 } 2547 2548 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2549 { 2550 struct nvme_dev *dev = to_nvme_dev(ctrl); 2551 2552 nvme_dbbuf_dma_free(dev); 2553 nvme_free_tagset(dev); 2554 if (dev->ctrl.admin_q) 2555 blk_put_queue(dev->ctrl.admin_q); 2556 free_opal_dev(dev->ctrl.opal_dev); 2557 mempool_destroy(dev->iod_mempool); 2558 put_device(dev->dev); 2559 kfree(dev->queues); 2560 kfree(dev); 2561 } 2562 2563 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2564 { 2565 /* 2566 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2567 * may be holding this pci_dev's device lock. 2568 */ 2569 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2570 nvme_get_ctrl(&dev->ctrl); 2571 nvme_dev_disable(dev, false); 2572 nvme_kill_queues(&dev->ctrl); 2573 if (!queue_work(nvme_wq, &dev->remove_work)) 2574 nvme_put_ctrl(&dev->ctrl); 2575 } 2576 2577 static void nvme_reset_work(struct work_struct *work) 2578 { 2579 struct nvme_dev *dev = 2580 container_of(work, struct nvme_dev, ctrl.reset_work); 2581 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2582 int result; 2583 2584 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2585 result = -ENODEV; 2586 goto out; 2587 } 2588 2589 /* 2590 * If we're called to reset a live controller first shut it down before 2591 * moving on. 2592 */ 2593 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2594 nvme_dev_disable(dev, false); 2595 nvme_sync_queues(&dev->ctrl); 2596 2597 mutex_lock(&dev->shutdown_lock); 2598 result = nvme_pci_enable(dev); 2599 if (result) 2600 goto out_unlock; 2601 2602 result = nvme_pci_configure_admin_queue(dev); 2603 if (result) 2604 goto out_unlock; 2605 2606 result = nvme_alloc_admin_tags(dev); 2607 if (result) 2608 goto out_unlock; 2609 2610 /* 2611 * Limit the max command size to prevent iod->sg allocations going 2612 * over a single page. 2613 */ 2614 dev->ctrl.max_hw_sectors = min_t(u32, 2615 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2616 dev->ctrl.max_segments = NVME_MAX_SEGS; 2617 2618 /* 2619 * Don't limit the IOMMU merged segment size. 2620 */ 2621 dma_set_max_seg_size(dev->dev, 0xffffffff); 2622 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2623 2624 mutex_unlock(&dev->shutdown_lock); 2625 2626 /* 2627 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2628 * initializing procedure here. 2629 */ 2630 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2631 dev_warn(dev->ctrl.device, 2632 "failed to mark controller CONNECTING\n"); 2633 result = -EBUSY; 2634 goto out; 2635 } 2636 2637 /* 2638 * We do not support an SGL for metadata (yet), so we are limited to a 2639 * single integrity segment for the separate metadata pointer. 2640 */ 2641 dev->ctrl.max_integrity_segments = 1; 2642 2643 result = nvme_init_ctrl_finish(&dev->ctrl); 2644 if (result) 2645 goto out; 2646 2647 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2648 if (!dev->ctrl.opal_dev) 2649 dev->ctrl.opal_dev = 2650 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2651 else if (was_suspend) 2652 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2653 } else { 2654 free_opal_dev(dev->ctrl.opal_dev); 2655 dev->ctrl.opal_dev = NULL; 2656 } 2657 2658 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2659 result = nvme_dbbuf_dma_alloc(dev); 2660 if (result) 2661 dev_warn(dev->dev, 2662 "unable to allocate dma for dbbuf\n"); 2663 } 2664 2665 if (dev->ctrl.hmpre) { 2666 result = nvme_setup_host_mem(dev); 2667 if (result < 0) 2668 goto out; 2669 } 2670 2671 result = nvme_setup_io_queues(dev); 2672 if (result) 2673 goto out; 2674 2675 /* 2676 * Keep the controller around but remove all namespaces if we don't have 2677 * any working I/O queue. 2678 */ 2679 if (dev->online_queues < 2) { 2680 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2681 nvme_kill_queues(&dev->ctrl); 2682 nvme_remove_namespaces(&dev->ctrl); 2683 nvme_free_tagset(dev); 2684 } else { 2685 nvme_start_queues(&dev->ctrl); 2686 nvme_wait_freeze(&dev->ctrl); 2687 nvme_dev_add(dev); 2688 nvme_unfreeze(&dev->ctrl); 2689 } 2690 2691 /* 2692 * If only admin queue live, keep it to do further investigation or 2693 * recovery. 2694 */ 2695 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2696 dev_warn(dev->ctrl.device, 2697 "failed to mark controller live state\n"); 2698 result = -ENODEV; 2699 goto out; 2700 } 2701 2702 nvme_start_ctrl(&dev->ctrl); 2703 return; 2704 2705 out_unlock: 2706 mutex_unlock(&dev->shutdown_lock); 2707 out: 2708 if (result) 2709 dev_warn(dev->ctrl.device, 2710 "Removing after probe failure status: %d\n", result); 2711 nvme_remove_dead_ctrl(dev); 2712 } 2713 2714 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2715 { 2716 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2717 struct pci_dev *pdev = to_pci_dev(dev->dev); 2718 2719 if (pci_get_drvdata(pdev)) 2720 device_release_driver(&pdev->dev); 2721 nvme_put_ctrl(&dev->ctrl); 2722 } 2723 2724 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2725 { 2726 *val = readl(to_nvme_dev(ctrl)->bar + off); 2727 return 0; 2728 } 2729 2730 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2731 { 2732 writel(val, to_nvme_dev(ctrl)->bar + off); 2733 return 0; 2734 } 2735 2736 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2737 { 2738 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2739 return 0; 2740 } 2741 2742 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2743 { 2744 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2745 2746 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2747 } 2748 2749 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2750 .name = "pcie", 2751 .module = THIS_MODULE, 2752 .flags = NVME_F_METADATA_SUPPORTED | 2753 NVME_F_PCI_P2PDMA, 2754 .reg_read32 = nvme_pci_reg_read32, 2755 .reg_write32 = nvme_pci_reg_write32, 2756 .reg_read64 = nvme_pci_reg_read64, 2757 .free_ctrl = nvme_pci_free_ctrl, 2758 .submit_async_event = nvme_pci_submit_async_event, 2759 .get_address = nvme_pci_get_address, 2760 }; 2761 2762 static int nvme_dev_map(struct nvme_dev *dev) 2763 { 2764 struct pci_dev *pdev = to_pci_dev(dev->dev); 2765 2766 if (pci_request_mem_regions(pdev, "nvme")) 2767 return -ENODEV; 2768 2769 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2770 goto release; 2771 2772 return 0; 2773 release: 2774 pci_release_mem_regions(pdev); 2775 return -ENODEV; 2776 } 2777 2778 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2779 { 2780 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2781 /* 2782 * Several Samsung devices seem to drop off the PCIe bus 2783 * randomly when APST is on and uses the deepest sleep state. 2784 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2785 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2786 * 950 PRO 256GB", but it seems to be restricted to two Dell 2787 * laptops. 2788 */ 2789 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2790 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2791 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2792 return NVME_QUIRK_NO_DEEPEST_PS; 2793 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2794 /* 2795 * Samsung SSD 960 EVO drops off the PCIe bus after system 2796 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2797 * within few minutes after bootup on a Coffee Lake board - 2798 * ASUS PRIME Z370-A 2799 */ 2800 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2801 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2802 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2803 return NVME_QUIRK_NO_APST; 2804 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2805 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2806 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2807 /* 2808 * Forcing to use host managed nvme power settings for 2809 * lowest idle power with quick resume latency on 2810 * Samsung and Toshiba SSDs based on suspend behavior 2811 * on Coffee Lake board for LENOVO C640 2812 */ 2813 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2814 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2815 return NVME_QUIRK_SIMPLE_SUSPEND; 2816 } 2817 2818 return 0; 2819 } 2820 2821 static void nvme_async_probe(void *data, async_cookie_t cookie) 2822 { 2823 struct nvme_dev *dev = data; 2824 2825 flush_work(&dev->ctrl.reset_work); 2826 flush_work(&dev->ctrl.scan_work); 2827 nvme_put_ctrl(&dev->ctrl); 2828 } 2829 2830 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2831 { 2832 int node, result = -ENOMEM; 2833 struct nvme_dev *dev; 2834 unsigned long quirks = id->driver_data; 2835 size_t alloc_size; 2836 2837 node = dev_to_node(&pdev->dev); 2838 if (node == NUMA_NO_NODE) 2839 set_dev_node(&pdev->dev, first_memory_node); 2840 2841 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2842 if (!dev) 2843 return -ENOMEM; 2844 2845 dev->nr_write_queues = write_queues; 2846 dev->nr_poll_queues = poll_queues; 2847 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 2848 dev->queues = kcalloc_node(dev->nr_allocated_queues, 2849 sizeof(struct nvme_queue), GFP_KERNEL, node); 2850 if (!dev->queues) 2851 goto free; 2852 2853 dev->dev = get_device(&pdev->dev); 2854 pci_set_drvdata(pdev, dev); 2855 2856 result = nvme_dev_map(dev); 2857 if (result) 2858 goto put_pci; 2859 2860 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2861 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2862 mutex_init(&dev->shutdown_lock); 2863 2864 result = nvme_setup_prp_pools(dev); 2865 if (result) 2866 goto unmap; 2867 2868 quirks |= check_vendor_combination_bug(pdev); 2869 2870 if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2871 /* 2872 * Some systems use a bios work around to ask for D3 on 2873 * platforms that support kernel managed suspend. 2874 */ 2875 dev_info(&pdev->dev, 2876 "platform quirk: setting simple suspend\n"); 2877 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2878 } 2879 2880 /* 2881 * Double check that our mempool alloc size will cover the biggest 2882 * command we support. 2883 */ 2884 alloc_size = nvme_pci_iod_alloc_size(); 2885 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2886 2887 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2888 mempool_kfree, 2889 (void *) alloc_size, 2890 GFP_KERNEL, node); 2891 if (!dev->iod_mempool) { 2892 result = -ENOMEM; 2893 goto release_pools; 2894 } 2895 2896 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2897 quirks); 2898 if (result) 2899 goto release_mempool; 2900 2901 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2902 2903 nvme_reset_ctrl(&dev->ctrl); 2904 async_schedule(nvme_async_probe, dev); 2905 2906 return 0; 2907 2908 release_mempool: 2909 mempool_destroy(dev->iod_mempool); 2910 release_pools: 2911 nvme_release_prp_pools(dev); 2912 unmap: 2913 nvme_dev_unmap(dev); 2914 put_pci: 2915 put_device(dev->dev); 2916 free: 2917 kfree(dev->queues); 2918 kfree(dev); 2919 return result; 2920 } 2921 2922 static void nvme_reset_prepare(struct pci_dev *pdev) 2923 { 2924 struct nvme_dev *dev = pci_get_drvdata(pdev); 2925 2926 /* 2927 * We don't need to check the return value from waiting for the reset 2928 * state as pci_dev device lock is held, making it impossible to race 2929 * with ->remove(). 2930 */ 2931 nvme_disable_prepare_reset(dev, false); 2932 nvme_sync_queues(&dev->ctrl); 2933 } 2934 2935 static void nvme_reset_done(struct pci_dev *pdev) 2936 { 2937 struct nvme_dev *dev = pci_get_drvdata(pdev); 2938 2939 if (!nvme_try_sched_reset(&dev->ctrl)) 2940 flush_work(&dev->ctrl.reset_work); 2941 } 2942 2943 static void nvme_shutdown(struct pci_dev *pdev) 2944 { 2945 struct nvme_dev *dev = pci_get_drvdata(pdev); 2946 2947 nvme_disable_prepare_reset(dev, true); 2948 } 2949 2950 /* 2951 * The driver's remove may be called on a device in a partially initialized 2952 * state. This function must not have any dependencies on the device state in 2953 * order to proceed. 2954 */ 2955 static void nvme_remove(struct pci_dev *pdev) 2956 { 2957 struct nvme_dev *dev = pci_get_drvdata(pdev); 2958 2959 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2960 pci_set_drvdata(pdev, NULL); 2961 2962 if (!pci_device_is_present(pdev)) { 2963 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2964 nvme_dev_disable(dev, true); 2965 nvme_dev_remove_admin(dev); 2966 } 2967 2968 flush_work(&dev->ctrl.reset_work); 2969 nvme_stop_ctrl(&dev->ctrl); 2970 nvme_remove_namespaces(&dev->ctrl); 2971 nvme_dev_disable(dev, true); 2972 nvme_release_cmb(dev); 2973 nvme_free_host_mem(dev); 2974 nvme_dev_remove_admin(dev); 2975 nvme_free_queues(dev, 0); 2976 nvme_release_prp_pools(dev); 2977 nvme_dev_unmap(dev); 2978 nvme_uninit_ctrl(&dev->ctrl); 2979 } 2980 2981 #ifdef CONFIG_PM_SLEEP 2982 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2983 { 2984 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2985 } 2986 2987 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2988 { 2989 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2990 } 2991 2992 static int nvme_resume(struct device *dev) 2993 { 2994 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2995 struct nvme_ctrl *ctrl = &ndev->ctrl; 2996 2997 if (ndev->last_ps == U32_MAX || 2998 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2999 return nvme_try_sched_reset(&ndev->ctrl); 3000 return 0; 3001 } 3002 3003 static int nvme_suspend(struct device *dev) 3004 { 3005 struct pci_dev *pdev = to_pci_dev(dev); 3006 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3007 struct nvme_ctrl *ctrl = &ndev->ctrl; 3008 int ret = -EBUSY; 3009 3010 ndev->last_ps = U32_MAX; 3011 3012 /* 3013 * The platform does not remove power for a kernel managed suspend so 3014 * use host managed nvme power settings for lowest idle power if 3015 * possible. This should have quicker resume latency than a full device 3016 * shutdown. But if the firmware is involved after the suspend or the 3017 * device does not support any non-default power states, shut down the 3018 * device fully. 3019 * 3020 * If ASPM is not enabled for the device, shut down the device and allow 3021 * the PCI bus layer to put it into D3 in order to take the PCIe link 3022 * down, so as to allow the platform to achieve its minimum low-power 3023 * state (which may not be possible if the link is up). 3024 * 3025 * If a host memory buffer is enabled, shut down the device as the NVMe 3026 * specification allows the device to access the host memory buffer in 3027 * host DRAM from all power states, but hosts will fail access to DRAM 3028 * during S3. 3029 */ 3030 if (pm_suspend_via_firmware() || !ctrl->npss || 3031 !pcie_aspm_enabled(pdev) || 3032 ndev->nr_host_mem_descs || 3033 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3034 return nvme_disable_prepare_reset(ndev, true); 3035 3036 nvme_start_freeze(ctrl); 3037 nvme_wait_freeze(ctrl); 3038 nvme_sync_queues(ctrl); 3039 3040 if (ctrl->state != NVME_CTRL_LIVE) 3041 goto unfreeze; 3042 3043 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3044 if (ret < 0) 3045 goto unfreeze; 3046 3047 /* 3048 * A saved state prevents pci pm from generically controlling the 3049 * device's power. If we're using protocol specific settings, we don't 3050 * want pci interfering. 3051 */ 3052 pci_save_state(pdev); 3053 3054 ret = nvme_set_power_state(ctrl, ctrl->npss); 3055 if (ret < 0) 3056 goto unfreeze; 3057 3058 if (ret) { 3059 /* discard the saved state */ 3060 pci_load_saved_state(pdev, NULL); 3061 3062 /* 3063 * Clearing npss forces a controller reset on resume. The 3064 * correct value will be rediscovered then. 3065 */ 3066 ret = nvme_disable_prepare_reset(ndev, true); 3067 ctrl->npss = 0; 3068 } 3069 unfreeze: 3070 nvme_unfreeze(ctrl); 3071 return ret; 3072 } 3073 3074 static int nvme_simple_suspend(struct device *dev) 3075 { 3076 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3077 3078 return nvme_disable_prepare_reset(ndev, true); 3079 } 3080 3081 static int nvme_simple_resume(struct device *dev) 3082 { 3083 struct pci_dev *pdev = to_pci_dev(dev); 3084 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3085 3086 return nvme_try_sched_reset(&ndev->ctrl); 3087 } 3088 3089 static const struct dev_pm_ops nvme_dev_pm_ops = { 3090 .suspend = nvme_suspend, 3091 .resume = nvme_resume, 3092 .freeze = nvme_simple_suspend, 3093 .thaw = nvme_simple_resume, 3094 .poweroff = nvme_simple_suspend, 3095 .restore = nvme_simple_resume, 3096 }; 3097 #endif /* CONFIG_PM_SLEEP */ 3098 3099 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3100 pci_channel_state_t state) 3101 { 3102 struct nvme_dev *dev = pci_get_drvdata(pdev); 3103 3104 /* 3105 * A frozen channel requires a reset. When detected, this method will 3106 * shutdown the controller to quiesce. The controller will be restarted 3107 * after the slot reset through driver's slot_reset callback. 3108 */ 3109 switch (state) { 3110 case pci_channel_io_normal: 3111 return PCI_ERS_RESULT_CAN_RECOVER; 3112 case pci_channel_io_frozen: 3113 dev_warn(dev->ctrl.device, 3114 "frozen state error detected, reset controller\n"); 3115 nvme_dev_disable(dev, false); 3116 return PCI_ERS_RESULT_NEED_RESET; 3117 case pci_channel_io_perm_failure: 3118 dev_warn(dev->ctrl.device, 3119 "failure state error detected, request disconnect\n"); 3120 return PCI_ERS_RESULT_DISCONNECT; 3121 } 3122 return PCI_ERS_RESULT_NEED_RESET; 3123 } 3124 3125 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3126 { 3127 struct nvme_dev *dev = pci_get_drvdata(pdev); 3128 3129 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3130 pci_restore_state(pdev); 3131 nvme_reset_ctrl(&dev->ctrl); 3132 return PCI_ERS_RESULT_RECOVERED; 3133 } 3134 3135 static void nvme_error_resume(struct pci_dev *pdev) 3136 { 3137 struct nvme_dev *dev = pci_get_drvdata(pdev); 3138 3139 flush_work(&dev->ctrl.reset_work); 3140 } 3141 3142 static const struct pci_error_handlers nvme_err_handler = { 3143 .error_detected = nvme_error_detected, 3144 .slot_reset = nvme_slot_reset, 3145 .resume = nvme_error_resume, 3146 .reset_prepare = nvme_reset_prepare, 3147 .reset_done = nvme_reset_done, 3148 }; 3149 3150 static const struct pci_device_id nvme_id_table[] = { 3151 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3152 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3153 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3154 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3155 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3156 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3157 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3158 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3159 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3160 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3161 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3162 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3163 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3164 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3165 NVME_QUIRK_MEDIUM_PRIO_SQ | 3166 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3167 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3168 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3169 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3170 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3171 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3172 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3173 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3174 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 3175 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3176 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3177 NVME_QUIRK_NO_NS_DESC_LIST, }, 3178 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3179 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3180 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3181 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3182 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3183 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3184 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3185 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3186 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3187 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3188 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3189 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3190 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3191 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3192 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3193 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3194 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3195 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3196 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3197 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3198 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3199 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3200 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3201 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3202 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3203 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3204 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3205 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3206 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3207 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3208 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3209 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3210 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3211 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3212 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3213 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3214 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3215 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3216 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3217 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3218 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3219 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3220 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3221 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3222 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3223 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3224 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3225 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3226 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3227 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3228 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3229 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3230 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3231 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3232 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3233 NVME_QUIRK_128_BYTES_SQES | 3234 NVME_QUIRK_SHARED_TAGS }, 3235 3236 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3237 { 0, } 3238 }; 3239 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3240 3241 static struct pci_driver nvme_driver = { 3242 .name = "nvme", 3243 .id_table = nvme_id_table, 3244 .probe = nvme_probe, 3245 .remove = nvme_remove, 3246 .shutdown = nvme_shutdown, 3247 #ifdef CONFIG_PM_SLEEP 3248 .driver = { 3249 .pm = &nvme_dev_pm_ops, 3250 }, 3251 #endif 3252 .sriov_configure = pci_sriov_configure_simple, 3253 .err_handler = &nvme_err_handler, 3254 }; 3255 3256 static int __init nvme_init(void) 3257 { 3258 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3259 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3260 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3261 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3262 3263 return pci_register_driver(&nvme_driver); 3264 } 3265 3266 static void __exit nvme_exit(void) 3267 { 3268 pci_unregister_driver(&nvme_driver); 3269 flush_workqueue(nvme_wq); 3270 } 3271 3272 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3273 MODULE_LICENSE("GPL"); 3274 MODULE_VERSION("1.0"); 3275 module_init(nvme_init); 3276 module_exit(nvme_exit); 3277