1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/bitops.h> 17 #include <linux/blkdev.h> 18 #include <linux/blk-mq.h> 19 #include <linux/blk-mq-pci.h> 20 #include <linux/cpu.h> 21 #include <linux/delay.h> 22 #include <linux/dmi.h> 23 #include <linux/errno.h> 24 #include <linux/fs.h> 25 #include <linux/genhd.h> 26 #include <linux/hdreg.h> 27 #include <linux/idr.h> 28 #include <linux/init.h> 29 #include <linux/interrupt.h> 30 #include <linux/io.h> 31 #include <linux/kdev_t.h> 32 #include <linux/kernel.h> 33 #include <linux/mm.h> 34 #include <linux/module.h> 35 #include <linux/moduleparam.h> 36 #include <linux/mutex.h> 37 #include <linux/pci.h> 38 #include <linux/poison.h> 39 #include <linux/ptrace.h> 40 #include <linux/sched.h> 41 #include <linux/slab.h> 42 #include <linux/t10-pi.h> 43 #include <linux/timer.h> 44 #include <linux/types.h> 45 #include <linux/io-64-nonatomic-lo-hi.h> 46 #include <asm/unaligned.h> 47 #include <linux/sed-opal.h> 48 49 #include "nvme.h" 50 51 #define NVME_Q_DEPTH 1024 52 #define NVME_AQ_DEPTH 256 53 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 54 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 55 56 /* 57 * We handle AEN commands ourselves and don't even let the 58 * block layer know about them. 59 */ 60 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) 61 62 static int use_threaded_interrupts; 63 module_param(use_threaded_interrupts, int, 0); 64 65 static bool use_cmb_sqes = true; 66 module_param(use_cmb_sqes, bool, 0644); 67 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 68 69 static struct workqueue_struct *nvme_workq; 70 71 struct nvme_dev; 72 struct nvme_queue; 73 74 static int nvme_reset(struct nvme_dev *dev); 75 static void nvme_process_cq(struct nvme_queue *nvmeq); 76 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 77 78 /* 79 * Represents an NVM Express device. Each nvme_dev is a PCI function. 80 */ 81 struct nvme_dev { 82 struct nvme_queue **queues; 83 struct blk_mq_tag_set tagset; 84 struct blk_mq_tag_set admin_tagset; 85 u32 __iomem *dbs; 86 struct device *dev; 87 struct dma_pool *prp_page_pool; 88 struct dma_pool *prp_small_pool; 89 unsigned queue_count; 90 unsigned online_queues; 91 unsigned max_qid; 92 int q_depth; 93 u32 db_stride; 94 void __iomem *bar; 95 struct work_struct reset_work; 96 struct work_struct remove_work; 97 struct timer_list watchdog_timer; 98 struct mutex shutdown_lock; 99 bool subsystem; 100 void __iomem *cmb; 101 dma_addr_t cmb_dma_addr; 102 u64 cmb_size; 103 u32 cmbsz; 104 u32 cmbloc; 105 struct nvme_ctrl ctrl; 106 struct completion ioq_wait; 107 u32 *dbbuf_dbs; 108 dma_addr_t dbbuf_dbs_dma_addr; 109 u32 *dbbuf_eis; 110 dma_addr_t dbbuf_eis_dma_addr; 111 }; 112 113 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 114 { 115 return qid * 2 * stride; 116 } 117 118 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 119 { 120 return (qid * 2 + 1) * stride; 121 } 122 123 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 124 { 125 return container_of(ctrl, struct nvme_dev, ctrl); 126 } 127 128 /* 129 * An NVM Express queue. Each device has at least two (one for admin 130 * commands and one for I/O commands). 131 */ 132 struct nvme_queue { 133 struct device *q_dmadev; 134 struct nvme_dev *dev; 135 spinlock_t q_lock; 136 struct nvme_command *sq_cmds; 137 struct nvme_command __iomem *sq_cmds_io; 138 volatile struct nvme_completion *cqes; 139 struct blk_mq_tags **tags; 140 dma_addr_t sq_dma_addr; 141 dma_addr_t cq_dma_addr; 142 u32 __iomem *q_db; 143 u16 q_depth; 144 s16 cq_vector; 145 u16 sq_tail; 146 u16 cq_head; 147 u16 qid; 148 u8 cq_phase; 149 u8 cqe_seen; 150 u32 *dbbuf_sq_db; 151 u32 *dbbuf_cq_db; 152 u32 *dbbuf_sq_ei; 153 u32 *dbbuf_cq_ei; 154 }; 155 156 /* 157 * The nvme_iod describes the data in an I/O, including the list of PRP 158 * entries. You can't see it in this data structure because C doesn't let 159 * me express that. Use nvme_init_iod to ensure there's enough space 160 * allocated to store the PRP list. 161 */ 162 struct nvme_iod { 163 struct nvme_request req; 164 struct nvme_queue *nvmeq; 165 int aborted; 166 int npages; /* In the PRP list. 0 means small pool in use */ 167 int nents; /* Used in scatterlist */ 168 int length; /* Of data, in bytes */ 169 dma_addr_t first_dma; 170 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 171 struct scatterlist *sg; 172 struct scatterlist inline_sg[0]; 173 }; 174 175 /* 176 * Check we didin't inadvertently grow the command struct 177 */ 178 static inline void _nvme_check_size(void) 179 { 180 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 181 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 182 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 183 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 184 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 185 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 186 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 187 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 188 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); 189 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); 190 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 191 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 192 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 193 } 194 195 static inline unsigned int nvme_dbbuf_size(u32 stride) 196 { 197 return ((num_possible_cpus() + 1) * 8 * stride); 198 } 199 200 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 201 { 202 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 203 204 if (dev->dbbuf_dbs) 205 return 0; 206 207 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 208 &dev->dbbuf_dbs_dma_addr, 209 GFP_KERNEL); 210 if (!dev->dbbuf_dbs) 211 return -ENOMEM; 212 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 213 &dev->dbbuf_eis_dma_addr, 214 GFP_KERNEL); 215 if (!dev->dbbuf_eis) { 216 dma_free_coherent(dev->dev, mem_size, 217 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 218 dev->dbbuf_dbs = NULL; 219 return -ENOMEM; 220 } 221 222 return 0; 223 } 224 225 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 226 { 227 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 228 229 if (dev->dbbuf_dbs) { 230 dma_free_coherent(dev->dev, mem_size, 231 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 232 dev->dbbuf_dbs = NULL; 233 } 234 if (dev->dbbuf_eis) { 235 dma_free_coherent(dev->dev, mem_size, 236 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 237 dev->dbbuf_eis = NULL; 238 } 239 } 240 241 static void nvme_dbbuf_init(struct nvme_dev *dev, 242 struct nvme_queue *nvmeq, int qid) 243 { 244 if (!dev->dbbuf_dbs || !qid) 245 return; 246 247 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 248 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 249 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 250 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 251 } 252 253 static void nvme_dbbuf_set(struct nvme_dev *dev) 254 { 255 struct nvme_command c; 256 257 if (!dev->dbbuf_dbs) 258 return; 259 260 memset(&c, 0, sizeof(c)); 261 c.dbbuf.opcode = nvme_admin_dbbuf; 262 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 263 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 264 265 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 266 dev_warn(dev->dev, "unable to set dbbuf\n"); 267 /* Free memory and continue on */ 268 nvme_dbbuf_dma_free(dev); 269 } 270 } 271 272 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 273 { 274 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 275 } 276 277 /* Update dbbuf and return true if an MMIO is required */ 278 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 279 volatile u32 *dbbuf_ei) 280 { 281 if (dbbuf_db) { 282 u16 old_value; 283 284 /* 285 * Ensure that the queue is written before updating 286 * the doorbell in memory 287 */ 288 wmb(); 289 290 old_value = *dbbuf_db; 291 *dbbuf_db = value; 292 293 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 294 return false; 295 } 296 297 return true; 298 } 299 300 /* 301 * Max size of iod being embedded in the request payload 302 */ 303 #define NVME_INT_PAGES 2 304 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 305 306 /* 307 * Will slightly overestimate the number of pages needed. This is OK 308 * as it only leads to a small amount of wasted memory for the lifetime of 309 * the I/O. 310 */ 311 static int nvme_npages(unsigned size, struct nvme_dev *dev) 312 { 313 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 314 dev->ctrl.page_size); 315 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 316 } 317 318 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, 319 unsigned int size, unsigned int nseg) 320 { 321 return sizeof(__le64 *) * nvme_npages(size, dev) + 322 sizeof(struct scatterlist) * nseg; 323 } 324 325 static unsigned int nvme_cmd_size(struct nvme_dev *dev) 326 { 327 return sizeof(struct nvme_iod) + 328 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); 329 } 330 331 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 332 unsigned int hctx_idx) 333 { 334 struct nvme_dev *dev = data; 335 struct nvme_queue *nvmeq = dev->queues[0]; 336 337 WARN_ON(hctx_idx != 0); 338 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 339 WARN_ON(nvmeq->tags); 340 341 hctx->driver_data = nvmeq; 342 nvmeq->tags = &dev->admin_tagset.tags[0]; 343 return 0; 344 } 345 346 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 347 { 348 struct nvme_queue *nvmeq = hctx->driver_data; 349 350 nvmeq->tags = NULL; 351 } 352 353 static int nvme_admin_init_request(struct blk_mq_tag_set *set, 354 struct request *req, unsigned int hctx_idx, 355 unsigned int numa_node) 356 { 357 struct nvme_dev *dev = set->driver_data; 358 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 359 struct nvme_queue *nvmeq = dev->queues[0]; 360 361 BUG_ON(!nvmeq); 362 iod->nvmeq = nvmeq; 363 return 0; 364 } 365 366 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 367 unsigned int hctx_idx) 368 { 369 struct nvme_dev *dev = data; 370 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 371 372 if (!nvmeq->tags) 373 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 374 375 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 376 hctx->driver_data = nvmeq; 377 return 0; 378 } 379 380 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 381 unsigned int hctx_idx, unsigned int numa_node) 382 { 383 struct nvme_dev *dev = set->driver_data; 384 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 385 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 386 387 BUG_ON(!nvmeq); 388 iod->nvmeq = nvmeq; 389 return 0; 390 } 391 392 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 393 { 394 struct nvme_dev *dev = set->driver_data; 395 396 return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 397 } 398 399 /** 400 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 401 * @nvmeq: The queue to use 402 * @cmd: The command to send 403 * 404 * Safe to use from interrupt context 405 */ 406 static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 407 struct nvme_command *cmd) 408 { 409 u16 tail = nvmeq->sq_tail; 410 411 if (nvmeq->sq_cmds_io) 412 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 413 else 414 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 415 416 if (++tail == nvmeq->q_depth) 417 tail = 0; 418 if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 419 nvmeq->dbbuf_sq_ei)) 420 writel(tail, nvmeq->q_db); 421 nvmeq->sq_tail = tail; 422 } 423 424 static __le64 **iod_list(struct request *req) 425 { 426 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 427 return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); 428 } 429 430 static int nvme_init_iod(struct request *rq, struct nvme_dev *dev) 431 { 432 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 433 int nseg = blk_rq_nr_phys_segments(rq); 434 unsigned int size = blk_rq_payload_bytes(rq); 435 436 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 437 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); 438 if (!iod->sg) 439 return BLK_MQ_RQ_QUEUE_BUSY; 440 } else { 441 iod->sg = iod->inline_sg; 442 } 443 444 iod->aborted = 0; 445 iod->npages = -1; 446 iod->nents = 0; 447 iod->length = size; 448 449 return BLK_MQ_RQ_QUEUE_OK; 450 } 451 452 static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 453 { 454 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 455 const int last_prp = dev->ctrl.page_size / 8 - 1; 456 int i; 457 __le64 **list = iod_list(req); 458 dma_addr_t prp_dma = iod->first_dma; 459 460 if (iod->npages == 0) 461 dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 462 for (i = 0; i < iod->npages; i++) { 463 __le64 *prp_list = list[i]; 464 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 465 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 466 prp_dma = next_prp_dma; 467 } 468 469 if (iod->sg != iod->inline_sg) 470 kfree(iod->sg); 471 } 472 473 #ifdef CONFIG_BLK_DEV_INTEGRITY 474 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 475 { 476 if (be32_to_cpu(pi->ref_tag) == v) 477 pi->ref_tag = cpu_to_be32(p); 478 } 479 480 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 481 { 482 if (be32_to_cpu(pi->ref_tag) == p) 483 pi->ref_tag = cpu_to_be32(v); 484 } 485 486 /** 487 * nvme_dif_remap - remaps ref tags to bip seed and physical lba 488 * 489 * The virtual start sector is the one that was originally submitted by the 490 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 491 * start sector may be different. Remap protection information to match the 492 * physical LBA on writes, and back to the original seed on reads. 493 * 494 * Type 0 and 3 do not have a ref tag, so no remapping required. 495 */ 496 static void nvme_dif_remap(struct request *req, 497 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 498 { 499 struct nvme_ns *ns = req->rq_disk->private_data; 500 struct bio_integrity_payload *bip; 501 struct t10_pi_tuple *pi; 502 void *p, *pmap; 503 u32 i, nlb, ts, phys, virt; 504 505 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 506 return; 507 508 bip = bio_integrity(req->bio); 509 if (!bip) 510 return; 511 512 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 513 514 p = pmap; 515 virt = bip_get_seed(bip); 516 phys = nvme_block_nr(ns, blk_rq_pos(req)); 517 nlb = (blk_rq_bytes(req) >> ns->lba_shift); 518 ts = ns->disk->queue->integrity.tuple_size; 519 520 for (i = 0; i < nlb; i++, virt++, phys++) { 521 pi = (struct t10_pi_tuple *)p; 522 dif_swap(phys, virt, pi); 523 p += ts; 524 } 525 kunmap_atomic(pmap); 526 } 527 #else /* CONFIG_BLK_DEV_INTEGRITY */ 528 static void nvme_dif_remap(struct request *req, 529 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 530 { 531 } 532 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 533 { 534 } 535 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 536 { 537 } 538 #endif 539 540 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) 541 { 542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 543 struct dma_pool *pool; 544 int length = blk_rq_payload_bytes(req); 545 struct scatterlist *sg = iod->sg; 546 int dma_len = sg_dma_len(sg); 547 u64 dma_addr = sg_dma_address(sg); 548 u32 page_size = dev->ctrl.page_size; 549 int offset = dma_addr & (page_size - 1); 550 __le64 *prp_list; 551 __le64 **list = iod_list(req); 552 dma_addr_t prp_dma; 553 int nprps, i; 554 555 length -= (page_size - offset); 556 if (length <= 0) 557 return true; 558 559 dma_len -= (page_size - offset); 560 if (dma_len) { 561 dma_addr += (page_size - offset); 562 } else { 563 sg = sg_next(sg); 564 dma_addr = sg_dma_address(sg); 565 dma_len = sg_dma_len(sg); 566 } 567 568 if (length <= page_size) { 569 iod->first_dma = dma_addr; 570 return true; 571 } 572 573 nprps = DIV_ROUND_UP(length, page_size); 574 if (nprps <= (256 / 8)) { 575 pool = dev->prp_small_pool; 576 iod->npages = 0; 577 } else { 578 pool = dev->prp_page_pool; 579 iod->npages = 1; 580 } 581 582 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 583 if (!prp_list) { 584 iod->first_dma = dma_addr; 585 iod->npages = -1; 586 return false; 587 } 588 list[0] = prp_list; 589 iod->first_dma = prp_dma; 590 i = 0; 591 for (;;) { 592 if (i == page_size >> 3) { 593 __le64 *old_prp_list = prp_list; 594 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 595 if (!prp_list) 596 return false; 597 list[iod->npages++] = prp_list; 598 prp_list[0] = old_prp_list[i - 1]; 599 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 600 i = 1; 601 } 602 prp_list[i++] = cpu_to_le64(dma_addr); 603 dma_len -= page_size; 604 dma_addr += page_size; 605 length -= page_size; 606 if (length <= 0) 607 break; 608 if (dma_len > 0) 609 continue; 610 BUG_ON(dma_len < 0); 611 sg = sg_next(sg); 612 dma_addr = sg_dma_address(sg); 613 dma_len = sg_dma_len(sg); 614 } 615 616 return true; 617 } 618 619 static int nvme_map_data(struct nvme_dev *dev, struct request *req, 620 struct nvme_command *cmnd) 621 { 622 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 623 struct request_queue *q = req->q; 624 enum dma_data_direction dma_dir = rq_data_dir(req) ? 625 DMA_TO_DEVICE : DMA_FROM_DEVICE; 626 int ret = BLK_MQ_RQ_QUEUE_ERROR; 627 628 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 629 iod->nents = blk_rq_map_sg(q, req, iod->sg); 630 if (!iod->nents) 631 goto out; 632 633 ret = BLK_MQ_RQ_QUEUE_BUSY; 634 if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 635 DMA_ATTR_NO_WARN)) 636 goto out; 637 638 if (!nvme_setup_prps(dev, req)) 639 goto out_unmap; 640 641 ret = BLK_MQ_RQ_QUEUE_ERROR; 642 if (blk_integrity_rq(req)) { 643 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 644 goto out_unmap; 645 646 sg_init_table(&iod->meta_sg, 1); 647 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 648 goto out_unmap; 649 650 if (rq_data_dir(req)) 651 nvme_dif_remap(req, nvme_dif_prep); 652 653 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 654 goto out_unmap; 655 } 656 657 cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 658 cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); 659 if (blk_integrity_rq(req)) 660 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 661 return BLK_MQ_RQ_QUEUE_OK; 662 663 out_unmap: 664 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 665 out: 666 return ret; 667 } 668 669 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 670 { 671 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 672 enum dma_data_direction dma_dir = rq_data_dir(req) ? 673 DMA_TO_DEVICE : DMA_FROM_DEVICE; 674 675 if (iod->nents) { 676 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 677 if (blk_integrity_rq(req)) { 678 if (!rq_data_dir(req)) 679 nvme_dif_remap(req, nvme_dif_complete); 680 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 681 } 682 } 683 684 nvme_cleanup_cmd(req); 685 nvme_free_iod(dev, req); 686 } 687 688 /* 689 * NOTE: ns is NULL when called on the admin queue. 690 */ 691 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 692 const struct blk_mq_queue_data *bd) 693 { 694 struct nvme_ns *ns = hctx->queue->queuedata; 695 struct nvme_queue *nvmeq = hctx->driver_data; 696 struct nvme_dev *dev = nvmeq->dev; 697 struct request *req = bd->rq; 698 struct nvme_command cmnd; 699 int ret = BLK_MQ_RQ_QUEUE_OK; 700 701 /* 702 * If formated with metadata, require the block layer provide a buffer 703 * unless this namespace is formated such that the metadata can be 704 * stripped/generated by the controller with PRACT=1. 705 */ 706 if (ns && ns->ms && !blk_integrity_rq(req)) { 707 if (!(ns->pi_type && ns->ms == 8) && 708 !blk_rq_is_passthrough(req)) { 709 blk_mq_end_request(req, -EFAULT); 710 return BLK_MQ_RQ_QUEUE_OK; 711 } 712 } 713 714 ret = nvme_setup_cmd(ns, req, &cmnd); 715 if (ret != BLK_MQ_RQ_QUEUE_OK) 716 return ret; 717 718 ret = nvme_init_iod(req, dev); 719 if (ret != BLK_MQ_RQ_QUEUE_OK) 720 goto out_free_cmd; 721 722 if (blk_rq_nr_phys_segments(req)) 723 ret = nvme_map_data(dev, req, &cmnd); 724 725 if (ret != BLK_MQ_RQ_QUEUE_OK) 726 goto out_cleanup_iod; 727 728 blk_mq_start_request(req); 729 730 spin_lock_irq(&nvmeq->q_lock); 731 if (unlikely(nvmeq->cq_vector < 0)) { 732 ret = BLK_MQ_RQ_QUEUE_ERROR; 733 spin_unlock_irq(&nvmeq->q_lock); 734 goto out_cleanup_iod; 735 } 736 __nvme_submit_cmd(nvmeq, &cmnd); 737 nvme_process_cq(nvmeq); 738 spin_unlock_irq(&nvmeq->q_lock); 739 return BLK_MQ_RQ_QUEUE_OK; 740 out_cleanup_iod: 741 nvme_free_iod(dev, req); 742 out_free_cmd: 743 nvme_cleanup_cmd(req); 744 return ret; 745 } 746 747 static void nvme_pci_complete_rq(struct request *req) 748 { 749 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 750 751 nvme_unmap_data(iod->nvmeq->dev, req); 752 nvme_complete_rq(req); 753 } 754 755 /* We read the CQE phase first to check if the rest of the entry is valid */ 756 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 757 u16 phase) 758 { 759 return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 760 } 761 762 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) 763 { 764 u16 head, phase; 765 766 head = nvmeq->cq_head; 767 phase = nvmeq->cq_phase; 768 769 while (nvme_cqe_valid(nvmeq, head, phase)) { 770 struct nvme_completion cqe = nvmeq->cqes[head]; 771 struct request *req; 772 773 if (++head == nvmeq->q_depth) { 774 head = 0; 775 phase = !phase; 776 } 777 778 if (tag && *tag == cqe.command_id) 779 *tag = -1; 780 781 if (unlikely(cqe.command_id >= nvmeq->q_depth)) { 782 dev_warn(nvmeq->dev->ctrl.device, 783 "invalid id %d completed on queue %d\n", 784 cqe.command_id, le16_to_cpu(cqe.sq_id)); 785 continue; 786 } 787 788 /* 789 * AEN requests are special as they don't time out and can 790 * survive any kind of queue freeze and often don't respond to 791 * aborts. We don't even bother to allocate a struct request 792 * for them but rather special case them here. 793 */ 794 if (unlikely(nvmeq->qid == 0 && 795 cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { 796 nvme_complete_async_event(&nvmeq->dev->ctrl, 797 cqe.status, &cqe.result); 798 continue; 799 } 800 801 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); 802 nvme_end_request(req, cqe.status, cqe.result); 803 } 804 805 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) 806 return; 807 808 if (likely(nvmeq->cq_vector >= 0)) 809 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 810 nvmeq->dbbuf_cq_ei)) 811 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 812 nvmeq->cq_head = head; 813 nvmeq->cq_phase = phase; 814 815 nvmeq->cqe_seen = 1; 816 } 817 818 static void nvme_process_cq(struct nvme_queue *nvmeq) 819 { 820 __nvme_process_cq(nvmeq, NULL); 821 } 822 823 static irqreturn_t nvme_irq(int irq, void *data) 824 { 825 irqreturn_t result; 826 struct nvme_queue *nvmeq = data; 827 spin_lock(&nvmeq->q_lock); 828 nvme_process_cq(nvmeq); 829 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 830 nvmeq->cqe_seen = 0; 831 spin_unlock(&nvmeq->q_lock); 832 return result; 833 } 834 835 static irqreturn_t nvme_irq_check(int irq, void *data) 836 { 837 struct nvme_queue *nvmeq = data; 838 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 839 return IRQ_WAKE_THREAD; 840 return IRQ_NONE; 841 } 842 843 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 844 { 845 if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 846 spin_lock_irq(&nvmeq->q_lock); 847 __nvme_process_cq(nvmeq, &tag); 848 spin_unlock_irq(&nvmeq->q_lock); 849 850 if (tag == -1) 851 return 1; 852 } 853 854 return 0; 855 } 856 857 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 858 { 859 struct nvme_queue *nvmeq = hctx->driver_data; 860 861 return __nvme_poll(nvmeq, tag); 862 } 863 864 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) 865 { 866 struct nvme_dev *dev = to_nvme_dev(ctrl); 867 struct nvme_queue *nvmeq = dev->queues[0]; 868 struct nvme_command c; 869 870 memset(&c, 0, sizeof(c)); 871 c.common.opcode = nvme_admin_async_event; 872 c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; 873 874 spin_lock_irq(&nvmeq->q_lock); 875 __nvme_submit_cmd(nvmeq, &c); 876 spin_unlock_irq(&nvmeq->q_lock); 877 } 878 879 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 880 { 881 struct nvme_command c; 882 883 memset(&c, 0, sizeof(c)); 884 c.delete_queue.opcode = opcode; 885 c.delete_queue.qid = cpu_to_le16(id); 886 887 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 888 } 889 890 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 891 struct nvme_queue *nvmeq) 892 { 893 struct nvme_command c; 894 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 895 896 /* 897 * Note: we (ab)use the fact the the prp fields survive if no data 898 * is attached to the request. 899 */ 900 memset(&c, 0, sizeof(c)); 901 c.create_cq.opcode = nvme_admin_create_cq; 902 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 903 c.create_cq.cqid = cpu_to_le16(qid); 904 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 905 c.create_cq.cq_flags = cpu_to_le16(flags); 906 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 907 908 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 909 } 910 911 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 912 struct nvme_queue *nvmeq) 913 { 914 struct nvme_command c; 915 int flags = NVME_QUEUE_PHYS_CONTIG; 916 917 /* 918 * Note: we (ab)use the fact the the prp fields survive if no data 919 * is attached to the request. 920 */ 921 memset(&c, 0, sizeof(c)); 922 c.create_sq.opcode = nvme_admin_create_sq; 923 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 924 c.create_sq.sqid = cpu_to_le16(qid); 925 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 926 c.create_sq.sq_flags = cpu_to_le16(flags); 927 c.create_sq.cqid = cpu_to_le16(qid); 928 929 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 930 } 931 932 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 933 { 934 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 935 } 936 937 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 938 { 939 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 940 } 941 942 static void abort_endio(struct request *req, int error) 943 { 944 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 945 struct nvme_queue *nvmeq = iod->nvmeq; 946 947 dev_warn(nvmeq->dev->ctrl.device, 948 "Abort status: 0x%x", nvme_req(req)->status); 949 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 950 blk_mq_free_request(req); 951 } 952 953 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 954 { 955 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 956 struct nvme_queue *nvmeq = iod->nvmeq; 957 struct nvme_dev *dev = nvmeq->dev; 958 struct request *abort_req; 959 struct nvme_command cmd; 960 961 /* 962 * Did we miss an interrupt? 963 */ 964 if (__nvme_poll(nvmeq, req->tag)) { 965 dev_warn(dev->ctrl.device, 966 "I/O %d QID %d timeout, completion polled\n", 967 req->tag, nvmeq->qid); 968 return BLK_EH_HANDLED; 969 } 970 971 /* 972 * Shutdown immediately if controller times out while starting. The 973 * reset work will see the pci device disabled when it gets the forced 974 * cancellation error. All outstanding requests are completed on 975 * shutdown, so we return BLK_EH_HANDLED. 976 */ 977 if (dev->ctrl.state == NVME_CTRL_RESETTING) { 978 dev_warn(dev->ctrl.device, 979 "I/O %d QID %d timeout, disable controller\n", 980 req->tag, nvmeq->qid); 981 nvme_dev_disable(dev, false); 982 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 983 return BLK_EH_HANDLED; 984 } 985 986 /* 987 * Shutdown the controller immediately and schedule a reset if the 988 * command was already aborted once before and still hasn't been 989 * returned to the driver, or if this is the admin queue. 990 */ 991 if (!nvmeq->qid || iod->aborted) { 992 dev_warn(dev->ctrl.device, 993 "I/O %d QID %d timeout, reset controller\n", 994 req->tag, nvmeq->qid); 995 nvme_dev_disable(dev, false); 996 nvme_reset(dev); 997 998 /* 999 * Mark the request as handled, since the inline shutdown 1000 * forces all outstanding requests to complete. 1001 */ 1002 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1003 return BLK_EH_HANDLED; 1004 } 1005 1006 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1007 atomic_inc(&dev->ctrl.abort_limit); 1008 return BLK_EH_RESET_TIMER; 1009 } 1010 iod->aborted = 1; 1011 1012 memset(&cmd, 0, sizeof(cmd)); 1013 cmd.abort.opcode = nvme_admin_abort_cmd; 1014 cmd.abort.cid = req->tag; 1015 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1016 1017 dev_warn(nvmeq->dev->ctrl.device, 1018 "I/O %d QID %d timeout, aborting\n", 1019 req->tag, nvmeq->qid); 1020 1021 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1022 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1023 if (IS_ERR(abort_req)) { 1024 atomic_inc(&dev->ctrl.abort_limit); 1025 return BLK_EH_RESET_TIMER; 1026 } 1027 1028 abort_req->timeout = ADMIN_TIMEOUT; 1029 abort_req->end_io_data = NULL; 1030 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1031 1032 /* 1033 * The aborted req will be completed on receiving the abort req. 1034 * We enable the timer again. If hit twice, it'll cause a device reset, 1035 * as the device then is in a faulty state. 1036 */ 1037 return BLK_EH_RESET_TIMER; 1038 } 1039 1040 static void nvme_free_queue(struct nvme_queue *nvmeq) 1041 { 1042 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1043 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1044 if (nvmeq->sq_cmds) 1045 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1046 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1047 kfree(nvmeq); 1048 } 1049 1050 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1051 { 1052 int i; 1053 1054 for (i = dev->queue_count - 1; i >= lowest; i--) { 1055 struct nvme_queue *nvmeq = dev->queues[i]; 1056 dev->queue_count--; 1057 dev->queues[i] = NULL; 1058 nvme_free_queue(nvmeq); 1059 } 1060 } 1061 1062 /** 1063 * nvme_suspend_queue - put queue into suspended state 1064 * @nvmeq - queue to suspend 1065 */ 1066 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1067 { 1068 int vector; 1069 1070 spin_lock_irq(&nvmeq->q_lock); 1071 if (nvmeq->cq_vector == -1) { 1072 spin_unlock_irq(&nvmeq->q_lock); 1073 return 1; 1074 } 1075 vector = nvmeq->cq_vector; 1076 nvmeq->dev->online_queues--; 1077 nvmeq->cq_vector = -1; 1078 spin_unlock_irq(&nvmeq->q_lock); 1079 1080 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1081 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); 1082 1083 pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 1084 1085 return 0; 1086 } 1087 1088 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1089 { 1090 struct nvme_queue *nvmeq = dev->queues[0]; 1091 1092 if (!nvmeq) 1093 return; 1094 if (nvme_suspend_queue(nvmeq)) 1095 return; 1096 1097 if (shutdown) 1098 nvme_shutdown_ctrl(&dev->ctrl); 1099 else 1100 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( 1101 dev->bar + NVME_REG_CAP)); 1102 1103 spin_lock_irq(&nvmeq->q_lock); 1104 nvme_process_cq(nvmeq); 1105 spin_unlock_irq(&nvmeq->q_lock); 1106 } 1107 1108 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1109 int entry_size) 1110 { 1111 int q_depth = dev->q_depth; 1112 unsigned q_size_aligned = roundup(q_depth * entry_size, 1113 dev->ctrl.page_size); 1114 1115 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1116 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1117 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1118 q_depth = div_u64(mem_per_q, entry_size); 1119 1120 /* 1121 * Ensure the reduced q_depth is above some threshold where it 1122 * would be better to map queues in system memory with the 1123 * original depth 1124 */ 1125 if (q_depth < 64) 1126 return -ENOMEM; 1127 } 1128 1129 return q_depth; 1130 } 1131 1132 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1133 int qid, int depth) 1134 { 1135 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 1136 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 1137 dev->ctrl.page_size); 1138 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 1139 nvmeq->sq_cmds_io = dev->cmb + offset; 1140 } else { 1141 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1142 &nvmeq->sq_dma_addr, GFP_KERNEL); 1143 if (!nvmeq->sq_cmds) 1144 return -ENOMEM; 1145 } 1146 1147 return 0; 1148 } 1149 1150 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1151 int depth, int node) 1152 { 1153 struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, 1154 node); 1155 if (!nvmeq) 1156 return NULL; 1157 1158 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 1159 &nvmeq->cq_dma_addr, GFP_KERNEL); 1160 if (!nvmeq->cqes) 1161 goto free_nvmeq; 1162 1163 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1164 goto free_cqdma; 1165 1166 nvmeq->q_dmadev = dev->dev; 1167 nvmeq->dev = dev; 1168 spin_lock_init(&nvmeq->q_lock); 1169 nvmeq->cq_head = 0; 1170 nvmeq->cq_phase = 1; 1171 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1172 nvmeq->q_depth = depth; 1173 nvmeq->qid = qid; 1174 nvmeq->cq_vector = -1; 1175 dev->queues[qid] = nvmeq; 1176 dev->queue_count++; 1177 1178 return nvmeq; 1179 1180 free_cqdma: 1181 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1182 nvmeq->cq_dma_addr); 1183 free_nvmeq: 1184 kfree(nvmeq); 1185 return NULL; 1186 } 1187 1188 static int queue_request_irq(struct nvme_queue *nvmeq) 1189 { 1190 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1191 int nr = nvmeq->dev->ctrl.instance; 1192 1193 if (use_threaded_interrupts) { 1194 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1195 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1196 } else { 1197 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1198 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1199 } 1200 } 1201 1202 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1203 { 1204 struct nvme_dev *dev = nvmeq->dev; 1205 1206 spin_lock_irq(&nvmeq->q_lock); 1207 nvmeq->sq_tail = 0; 1208 nvmeq->cq_head = 0; 1209 nvmeq->cq_phase = 1; 1210 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1211 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1212 nvme_dbbuf_init(dev, nvmeq, qid); 1213 dev->online_queues++; 1214 spin_unlock_irq(&nvmeq->q_lock); 1215 } 1216 1217 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 1218 { 1219 struct nvme_dev *dev = nvmeq->dev; 1220 int result; 1221 1222 nvmeq->cq_vector = qid - 1; 1223 result = adapter_alloc_cq(dev, qid, nvmeq); 1224 if (result < 0) 1225 return result; 1226 1227 result = adapter_alloc_sq(dev, qid, nvmeq); 1228 if (result < 0) 1229 goto release_cq; 1230 1231 result = queue_request_irq(nvmeq); 1232 if (result < 0) 1233 goto release_sq; 1234 1235 nvme_init_queue(nvmeq, qid); 1236 return result; 1237 1238 release_sq: 1239 adapter_delete_sq(dev, qid); 1240 release_cq: 1241 adapter_delete_cq(dev, qid); 1242 return result; 1243 } 1244 1245 static const struct blk_mq_ops nvme_mq_admin_ops = { 1246 .queue_rq = nvme_queue_rq, 1247 .complete = nvme_pci_complete_rq, 1248 .init_hctx = nvme_admin_init_hctx, 1249 .exit_hctx = nvme_admin_exit_hctx, 1250 .init_request = nvme_admin_init_request, 1251 .timeout = nvme_timeout, 1252 }; 1253 1254 static const struct blk_mq_ops nvme_mq_ops = { 1255 .queue_rq = nvme_queue_rq, 1256 .complete = nvme_pci_complete_rq, 1257 .init_hctx = nvme_init_hctx, 1258 .init_request = nvme_init_request, 1259 .map_queues = nvme_pci_map_queues, 1260 .timeout = nvme_timeout, 1261 .poll = nvme_poll, 1262 }; 1263 1264 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1265 { 1266 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1267 /* 1268 * If the controller was reset during removal, it's possible 1269 * user requests may be waiting on a stopped queue. Start the 1270 * queue to flush these to completion. 1271 */ 1272 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); 1273 blk_cleanup_queue(dev->ctrl.admin_q); 1274 blk_mq_free_tag_set(&dev->admin_tagset); 1275 } 1276 } 1277 1278 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1279 { 1280 if (!dev->ctrl.admin_q) { 1281 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1282 dev->admin_tagset.nr_hw_queues = 1; 1283 1284 /* 1285 * Subtract one to leave an empty queue entry for 'Full Queue' 1286 * condition. See NVM-Express 1.2 specification, section 4.1.2. 1287 */ 1288 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; 1289 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1290 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1291 dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1292 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1293 dev->admin_tagset.driver_data = dev; 1294 1295 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1296 return -ENOMEM; 1297 1298 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1299 if (IS_ERR(dev->ctrl.admin_q)) { 1300 blk_mq_free_tag_set(&dev->admin_tagset); 1301 return -ENOMEM; 1302 } 1303 if (!blk_get_queue(dev->ctrl.admin_q)) { 1304 nvme_dev_remove_admin(dev); 1305 dev->ctrl.admin_q = NULL; 1306 return -ENODEV; 1307 } 1308 } else 1309 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); 1310 1311 return 0; 1312 } 1313 1314 static int nvme_configure_admin_queue(struct nvme_dev *dev) 1315 { 1316 int result; 1317 u32 aqa; 1318 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1319 struct nvme_queue *nvmeq; 1320 1321 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1322 NVME_CAP_NSSRC(cap) : 0; 1323 1324 if (dev->subsystem && 1325 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1326 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1327 1328 result = nvme_disable_ctrl(&dev->ctrl, cap); 1329 if (result < 0) 1330 return result; 1331 1332 nvmeq = dev->queues[0]; 1333 if (!nvmeq) { 1334 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1335 dev_to_node(dev->dev)); 1336 if (!nvmeq) 1337 return -ENOMEM; 1338 } 1339 1340 aqa = nvmeq->q_depth - 1; 1341 aqa |= aqa << 16; 1342 1343 writel(aqa, dev->bar + NVME_REG_AQA); 1344 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1345 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1346 1347 result = nvme_enable_ctrl(&dev->ctrl, cap); 1348 if (result) 1349 return result; 1350 1351 nvmeq->cq_vector = 0; 1352 result = queue_request_irq(nvmeq); 1353 if (result) { 1354 nvmeq->cq_vector = -1; 1355 return result; 1356 } 1357 1358 return result; 1359 } 1360 1361 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1362 { 1363 1364 /* If true, indicates loss of adapter communication, possibly by a 1365 * NVMe Subsystem reset. 1366 */ 1367 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1368 1369 /* If there is a reset ongoing, we shouldn't reset again. */ 1370 if (work_busy(&dev->reset_work)) 1371 return false; 1372 1373 /* We shouldn't reset unless the controller is on fatal error state 1374 * _or_ if we lost the communication with it. 1375 */ 1376 if (!(csts & NVME_CSTS_CFS) && !nssro) 1377 return false; 1378 1379 /* If PCI error recovery process is happening, we cannot reset or 1380 * the recovery mechanism will surely fail. 1381 */ 1382 if (pci_channel_offline(to_pci_dev(dev->dev))) 1383 return false; 1384 1385 return true; 1386 } 1387 1388 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1389 { 1390 /* Read a config register to help see what died. */ 1391 u16 pci_status; 1392 int result; 1393 1394 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1395 &pci_status); 1396 if (result == PCIBIOS_SUCCESSFUL) 1397 dev_warn(dev->dev, 1398 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1399 csts, pci_status); 1400 else 1401 dev_warn(dev->dev, 1402 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1403 csts, result); 1404 } 1405 1406 static void nvme_watchdog_timer(unsigned long data) 1407 { 1408 struct nvme_dev *dev = (struct nvme_dev *)data; 1409 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1410 1411 /* Skip controllers under certain specific conditions. */ 1412 if (nvme_should_reset(dev, csts)) { 1413 if (!nvme_reset(dev)) 1414 nvme_warn_reset(dev, csts); 1415 return; 1416 } 1417 1418 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); 1419 } 1420 1421 static int nvme_create_io_queues(struct nvme_dev *dev) 1422 { 1423 unsigned i, max; 1424 int ret = 0; 1425 1426 for (i = dev->queue_count; i <= dev->max_qid; i++) { 1427 /* vector == qid - 1, match nvme_create_queue */ 1428 if (!nvme_alloc_queue(dev, i, dev->q_depth, 1429 pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1430 ret = -ENOMEM; 1431 break; 1432 } 1433 } 1434 1435 max = min(dev->max_qid, dev->queue_count - 1); 1436 for (i = dev->online_queues; i <= max; i++) { 1437 ret = nvme_create_queue(dev->queues[i], i); 1438 if (ret) 1439 break; 1440 } 1441 1442 /* 1443 * Ignore failing Create SQ/CQ commands, we can continue with less 1444 * than the desired aount of queues, and even a controller without 1445 * I/O queues an still be used to issue admin commands. This might 1446 * be useful to upgrade a buggy firmware for example. 1447 */ 1448 return ret >= 0 ? 0 : ret; 1449 } 1450 1451 static ssize_t nvme_cmb_show(struct device *dev, 1452 struct device_attribute *attr, 1453 char *buf) 1454 { 1455 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1456 1457 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1458 ndev->cmbloc, ndev->cmbsz); 1459 } 1460 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1461 1462 static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 1463 { 1464 u64 szu, size, offset; 1465 resource_size_t bar_size; 1466 struct pci_dev *pdev = to_pci_dev(dev->dev); 1467 void __iomem *cmb; 1468 dma_addr_t dma_addr; 1469 1470 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1471 if (!(NVME_CMB_SZ(dev->cmbsz))) 1472 return NULL; 1473 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1474 1475 if (!use_cmb_sqes) 1476 return NULL; 1477 1478 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 1479 size = szu * NVME_CMB_SZ(dev->cmbsz); 1480 offset = szu * NVME_CMB_OFST(dev->cmbloc); 1481 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 1482 1483 if (offset > bar_size) 1484 return NULL; 1485 1486 /* 1487 * Controllers may support a CMB size larger than their BAR, 1488 * for example, due to being behind a bridge. Reduce the CMB to 1489 * the reported size of the BAR 1490 */ 1491 if (size > bar_size - offset) 1492 size = bar_size - offset; 1493 1494 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 1495 cmb = ioremap_wc(dma_addr, size); 1496 if (!cmb) 1497 return NULL; 1498 1499 dev->cmb_dma_addr = dma_addr; 1500 dev->cmb_size = size; 1501 return cmb; 1502 } 1503 1504 static inline void nvme_release_cmb(struct nvme_dev *dev) 1505 { 1506 if (dev->cmb) { 1507 iounmap(dev->cmb); 1508 dev->cmb = NULL; 1509 if (dev->cmbsz) { 1510 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1511 &dev_attr_cmb.attr, NULL); 1512 dev->cmbsz = 0; 1513 } 1514 } 1515 } 1516 1517 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1518 { 1519 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); 1520 } 1521 1522 static int nvme_setup_io_queues(struct nvme_dev *dev) 1523 { 1524 struct nvme_queue *adminq = dev->queues[0]; 1525 struct pci_dev *pdev = to_pci_dev(dev->dev); 1526 int result, nr_io_queues, size; 1527 1528 nr_io_queues = num_online_cpus(); 1529 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 1530 if (result < 0) 1531 return result; 1532 1533 if (nr_io_queues == 0) 1534 return 0; 1535 1536 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 1537 result = nvme_cmb_qdepth(dev, nr_io_queues, 1538 sizeof(struct nvme_command)); 1539 if (result > 0) 1540 dev->q_depth = result; 1541 else 1542 nvme_release_cmb(dev); 1543 } 1544 1545 size = db_bar_size(dev, nr_io_queues); 1546 if (size > 8192) { 1547 iounmap(dev->bar); 1548 do { 1549 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1550 if (dev->bar) 1551 break; 1552 if (!--nr_io_queues) 1553 return -ENOMEM; 1554 size = db_bar_size(dev, nr_io_queues); 1555 } while (1); 1556 dev->dbs = dev->bar + 4096; 1557 adminq->q_db = dev->dbs; 1558 } 1559 1560 /* Deregister the admin queue's interrupt */ 1561 pci_free_irq(pdev, 0, adminq); 1562 1563 /* 1564 * If we enable msix early due to not intx, disable it again before 1565 * setting up the full range we need. 1566 */ 1567 pci_free_irq_vectors(pdev); 1568 nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1569 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1570 if (nr_io_queues <= 0) 1571 return -EIO; 1572 dev->max_qid = nr_io_queues; 1573 1574 /* 1575 * Should investigate if there's a performance win from allocating 1576 * more queues than interrupt vectors; it might allow the submission 1577 * path to scale better, even if the receive path is limited by the 1578 * number of interrupts. 1579 */ 1580 1581 result = queue_request_irq(adminq); 1582 if (result) { 1583 adminq->cq_vector = -1; 1584 return result; 1585 } 1586 return nvme_create_io_queues(dev); 1587 } 1588 1589 static void nvme_del_queue_end(struct request *req, int error) 1590 { 1591 struct nvme_queue *nvmeq = req->end_io_data; 1592 1593 blk_mq_free_request(req); 1594 complete(&nvmeq->dev->ioq_wait); 1595 } 1596 1597 static void nvme_del_cq_end(struct request *req, int error) 1598 { 1599 struct nvme_queue *nvmeq = req->end_io_data; 1600 1601 if (!error) { 1602 unsigned long flags; 1603 1604 /* 1605 * We might be called with the AQ q_lock held 1606 * and the I/O queue q_lock should always 1607 * nest inside the AQ one. 1608 */ 1609 spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 1610 SINGLE_DEPTH_NESTING); 1611 nvme_process_cq(nvmeq); 1612 spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1613 } 1614 1615 nvme_del_queue_end(req, error); 1616 } 1617 1618 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1619 { 1620 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1621 struct request *req; 1622 struct nvme_command cmd; 1623 1624 memset(&cmd, 0, sizeof(cmd)); 1625 cmd.delete_queue.opcode = opcode; 1626 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1627 1628 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1629 if (IS_ERR(req)) 1630 return PTR_ERR(req); 1631 1632 req->timeout = ADMIN_TIMEOUT; 1633 req->end_io_data = nvmeq; 1634 1635 blk_execute_rq_nowait(q, NULL, req, false, 1636 opcode == nvme_admin_delete_cq ? 1637 nvme_del_cq_end : nvme_del_queue_end); 1638 return 0; 1639 } 1640 1641 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1642 { 1643 int pass; 1644 unsigned long timeout; 1645 u8 opcode = nvme_admin_delete_sq; 1646 1647 for (pass = 0; pass < 2; pass++) { 1648 int sent = 0, i = queues; 1649 1650 reinit_completion(&dev->ioq_wait); 1651 retry: 1652 timeout = ADMIN_TIMEOUT; 1653 for (; i > 0; i--, sent++) 1654 if (nvme_delete_queue(dev->queues[i], opcode)) 1655 break; 1656 1657 while (sent--) { 1658 timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 1659 if (timeout == 0) 1660 return; 1661 if (i) 1662 goto retry; 1663 } 1664 opcode = nvme_admin_delete_cq; 1665 } 1666 } 1667 1668 /* 1669 * Return: error value if an error occurred setting up the queues or calling 1670 * Identify Device. 0 if these succeeded, even if adding some of the 1671 * namespaces failed. At the moment, these failures are silent. TBD which 1672 * failures should be reported. 1673 */ 1674 static int nvme_dev_add(struct nvme_dev *dev) 1675 { 1676 if (!dev->ctrl.tagset) { 1677 dev->tagset.ops = &nvme_mq_ops; 1678 dev->tagset.nr_hw_queues = dev->online_queues - 1; 1679 dev->tagset.timeout = NVME_IO_TIMEOUT; 1680 dev->tagset.numa_node = dev_to_node(dev->dev); 1681 dev->tagset.queue_depth = 1682 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 1683 dev->tagset.cmd_size = nvme_cmd_size(dev); 1684 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 1685 dev->tagset.driver_data = dev; 1686 1687 if (blk_mq_alloc_tag_set(&dev->tagset)) 1688 return 0; 1689 dev->ctrl.tagset = &dev->tagset; 1690 1691 nvme_dbbuf_set(dev); 1692 } else { 1693 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 1694 1695 /* Free previously allocated queues that are no longer usable */ 1696 nvme_free_queues(dev, dev->online_queues); 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int nvme_pci_enable(struct nvme_dev *dev) 1703 { 1704 u64 cap; 1705 int result = -ENOMEM; 1706 struct pci_dev *pdev = to_pci_dev(dev->dev); 1707 1708 if (pci_enable_device_mem(pdev)) 1709 return result; 1710 1711 pci_set_master(pdev); 1712 1713 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 1714 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 1715 goto disable; 1716 1717 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 1718 result = -ENODEV; 1719 goto disable; 1720 } 1721 1722 /* 1723 * Some devices and/or platforms don't advertise or work with INTx 1724 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 1725 * adjust this later. 1726 */ 1727 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1728 if (result < 0) 1729 return result; 1730 1731 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1732 1733 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); 1734 dev->db_stride = 1 << NVME_CAP_STRIDE(cap); 1735 dev->dbs = dev->bar + 4096; 1736 1737 /* 1738 * Temporary fix for the Apple controller found in the MacBook8,1 and 1739 * some MacBook7,1 to avoid controller resets and data loss. 1740 */ 1741 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 1742 dev->q_depth = 2; 1743 dev_warn(dev->dev, "detected Apple NVMe controller, set " 1744 "queue depth=%u to work around controller resets\n", 1745 dev->q_depth); 1746 } 1747 1748 /* 1749 * CMBs can currently only exist on >=1.2 PCIe devices. We only 1750 * populate sysfs if a CMB is implemented. Note that we add the 1751 * CMB attribute to the nvme_ctrl kobj which removes the need to remove 1752 * it on exit. Since nvme_dev_attrs_group has no name we can pass 1753 * NULL as final argument to sysfs_add_file_to_group. 1754 */ 1755 1756 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 1757 dev->cmb = nvme_map_cmb(dev); 1758 1759 if (dev->cmbsz) { 1760 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1761 &dev_attr_cmb.attr, NULL)) 1762 dev_warn(dev->dev, 1763 "failed to add sysfs attribute for CMB\n"); 1764 } 1765 } 1766 1767 pci_enable_pcie_error_reporting(pdev); 1768 pci_save_state(pdev); 1769 return 0; 1770 1771 disable: 1772 pci_disable_device(pdev); 1773 return result; 1774 } 1775 1776 static void nvme_dev_unmap(struct nvme_dev *dev) 1777 { 1778 if (dev->bar) 1779 iounmap(dev->bar); 1780 pci_release_mem_regions(to_pci_dev(dev->dev)); 1781 } 1782 1783 static void nvme_pci_disable(struct nvme_dev *dev) 1784 { 1785 struct pci_dev *pdev = to_pci_dev(dev->dev); 1786 1787 nvme_release_cmb(dev); 1788 pci_free_irq_vectors(pdev); 1789 1790 if (pci_is_enabled(pdev)) { 1791 pci_disable_pcie_error_reporting(pdev); 1792 pci_disable_device(pdev); 1793 } 1794 } 1795 1796 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 1797 { 1798 int i, queues; 1799 bool dead = true; 1800 struct pci_dev *pdev = to_pci_dev(dev->dev); 1801 1802 del_timer_sync(&dev->watchdog_timer); 1803 1804 mutex_lock(&dev->shutdown_lock); 1805 if (pci_is_enabled(pdev)) { 1806 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1807 1808 if (dev->ctrl.state == NVME_CTRL_LIVE) 1809 nvme_start_freeze(&dev->ctrl); 1810 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 1811 pdev->error_state != pci_channel_io_normal); 1812 } 1813 1814 /* 1815 * Give the controller a chance to complete all entered requests if 1816 * doing a safe shutdown. 1817 */ 1818 if (!dead && shutdown) 1819 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 1820 nvme_stop_queues(&dev->ctrl); 1821 1822 queues = dev->online_queues - 1; 1823 for (i = dev->queue_count - 1; i > 0; i--) 1824 nvme_suspend_queue(dev->queues[i]); 1825 1826 if (dead) { 1827 /* A device might become IO incapable very soon during 1828 * probe, before the admin queue is configured. Thus, 1829 * queue_count can be 0 here. 1830 */ 1831 if (dev->queue_count) 1832 nvme_suspend_queue(dev->queues[0]); 1833 } else { 1834 nvme_disable_io_queues(dev, queues); 1835 nvme_disable_admin_queue(dev, shutdown); 1836 } 1837 nvme_pci_disable(dev); 1838 1839 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 1840 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 1841 1842 /* 1843 * The driver will not be starting up queues again if shutting down so 1844 * must flush all entered requests to their failed completion to avoid 1845 * deadlocking blk-mq hot-cpu notifier. 1846 */ 1847 if (shutdown) 1848 nvme_start_queues(&dev->ctrl); 1849 mutex_unlock(&dev->shutdown_lock); 1850 } 1851 1852 static int nvme_setup_prp_pools(struct nvme_dev *dev) 1853 { 1854 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 1855 PAGE_SIZE, PAGE_SIZE, 0); 1856 if (!dev->prp_page_pool) 1857 return -ENOMEM; 1858 1859 /* Optimisation for I/Os between 4k and 128k */ 1860 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 1861 256, 256, 0); 1862 if (!dev->prp_small_pool) { 1863 dma_pool_destroy(dev->prp_page_pool); 1864 return -ENOMEM; 1865 } 1866 return 0; 1867 } 1868 1869 static void nvme_release_prp_pools(struct nvme_dev *dev) 1870 { 1871 dma_pool_destroy(dev->prp_page_pool); 1872 dma_pool_destroy(dev->prp_small_pool); 1873 } 1874 1875 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 1876 { 1877 struct nvme_dev *dev = to_nvme_dev(ctrl); 1878 1879 nvme_dbbuf_dma_free(dev); 1880 put_device(dev->dev); 1881 if (dev->tagset.tags) 1882 blk_mq_free_tag_set(&dev->tagset); 1883 if (dev->ctrl.admin_q) 1884 blk_put_queue(dev->ctrl.admin_q); 1885 kfree(dev->queues); 1886 free_opal_dev(dev->ctrl.opal_dev); 1887 kfree(dev); 1888 } 1889 1890 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 1891 { 1892 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 1893 1894 kref_get(&dev->ctrl.kref); 1895 nvme_dev_disable(dev, false); 1896 if (!schedule_work(&dev->remove_work)) 1897 nvme_put_ctrl(&dev->ctrl); 1898 } 1899 1900 static void nvme_reset_work(struct work_struct *work) 1901 { 1902 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); 1903 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 1904 int result = -ENODEV; 1905 1906 if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING)) 1907 goto out; 1908 1909 /* 1910 * If we're called to reset a live controller first shut it down before 1911 * moving on. 1912 */ 1913 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 1914 nvme_dev_disable(dev, false); 1915 1916 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) 1917 goto out; 1918 1919 result = nvme_pci_enable(dev); 1920 if (result) 1921 goto out; 1922 1923 result = nvme_configure_admin_queue(dev); 1924 if (result) 1925 goto out; 1926 1927 nvme_init_queue(dev->queues[0], 0); 1928 result = nvme_alloc_admin_tags(dev); 1929 if (result) 1930 goto out; 1931 1932 result = nvme_init_identify(&dev->ctrl); 1933 if (result) 1934 goto out; 1935 1936 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 1937 if (!dev->ctrl.opal_dev) 1938 dev->ctrl.opal_dev = 1939 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 1940 else if (was_suspend) 1941 opal_unlock_from_suspend(dev->ctrl.opal_dev); 1942 } else { 1943 free_opal_dev(dev->ctrl.opal_dev); 1944 dev->ctrl.opal_dev = NULL; 1945 } 1946 1947 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 1948 result = nvme_dbbuf_dma_alloc(dev); 1949 if (result) 1950 dev_warn(dev->dev, 1951 "unable to allocate dma for dbbuf\n"); 1952 } 1953 1954 result = nvme_setup_io_queues(dev); 1955 if (result) 1956 goto out; 1957 1958 /* 1959 * A controller that can not execute IO typically requires user 1960 * intervention to correct. For such degraded controllers, the driver 1961 * should not submit commands the user did not request, so skip 1962 * registering for asynchronous event notification on this condition. 1963 */ 1964 if (dev->online_queues > 1) 1965 nvme_queue_async_events(&dev->ctrl); 1966 1967 mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); 1968 1969 /* 1970 * Keep the controller around but remove all namespaces if we don't have 1971 * any working I/O queue. 1972 */ 1973 if (dev->online_queues < 2) { 1974 dev_warn(dev->ctrl.device, "IO queues not created\n"); 1975 nvme_kill_queues(&dev->ctrl); 1976 nvme_remove_namespaces(&dev->ctrl); 1977 } else { 1978 nvme_start_queues(&dev->ctrl); 1979 nvme_wait_freeze(&dev->ctrl); 1980 nvme_dev_add(dev); 1981 nvme_unfreeze(&dev->ctrl); 1982 } 1983 1984 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 1985 dev_warn(dev->ctrl.device, "failed to mark controller live\n"); 1986 goto out; 1987 } 1988 1989 if (dev->online_queues > 1) 1990 nvme_queue_scan(&dev->ctrl); 1991 return; 1992 1993 out: 1994 nvme_remove_dead_ctrl(dev, result); 1995 } 1996 1997 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 1998 { 1999 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2000 struct pci_dev *pdev = to_pci_dev(dev->dev); 2001 2002 nvme_kill_queues(&dev->ctrl); 2003 if (pci_get_drvdata(pdev)) 2004 device_release_driver(&pdev->dev); 2005 nvme_put_ctrl(&dev->ctrl); 2006 } 2007 2008 static int nvme_reset(struct nvme_dev *dev) 2009 { 2010 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 2011 return -ENODEV; 2012 if (work_busy(&dev->reset_work)) 2013 return -ENODEV; 2014 if (!queue_work(nvme_workq, &dev->reset_work)) 2015 return -EBUSY; 2016 return 0; 2017 } 2018 2019 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2020 { 2021 *val = readl(to_nvme_dev(ctrl)->bar + off); 2022 return 0; 2023 } 2024 2025 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2026 { 2027 writel(val, to_nvme_dev(ctrl)->bar + off); 2028 return 0; 2029 } 2030 2031 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2032 { 2033 *val = readq(to_nvme_dev(ctrl)->bar + off); 2034 return 0; 2035 } 2036 2037 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 2038 { 2039 struct nvme_dev *dev = to_nvme_dev(ctrl); 2040 int ret = nvme_reset(dev); 2041 2042 if (!ret) 2043 flush_work(&dev->reset_work); 2044 return ret; 2045 } 2046 2047 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2048 .name = "pcie", 2049 .module = THIS_MODULE, 2050 .reg_read32 = nvme_pci_reg_read32, 2051 .reg_write32 = nvme_pci_reg_write32, 2052 .reg_read64 = nvme_pci_reg_read64, 2053 .reset_ctrl = nvme_pci_reset_ctrl, 2054 .free_ctrl = nvme_pci_free_ctrl, 2055 .submit_async_event = nvme_pci_submit_async_event, 2056 }; 2057 2058 static int nvme_dev_map(struct nvme_dev *dev) 2059 { 2060 struct pci_dev *pdev = to_pci_dev(dev->dev); 2061 2062 if (pci_request_mem_regions(pdev, "nvme")) 2063 return -ENODEV; 2064 2065 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); 2066 if (!dev->bar) 2067 goto release; 2068 2069 return 0; 2070 release: 2071 pci_release_mem_regions(pdev); 2072 return -ENODEV; 2073 } 2074 2075 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) 2076 { 2077 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2078 /* 2079 * Several Samsung devices seem to drop off the PCIe bus 2080 * randomly when APST is on and uses the deepest sleep state. 2081 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2082 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2083 * 950 PRO 256GB", but it seems to be restricted to two Dell 2084 * laptops. 2085 */ 2086 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2087 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2088 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2089 return NVME_QUIRK_NO_DEEPEST_PS; 2090 } 2091 2092 return 0; 2093 } 2094 2095 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2096 { 2097 int node, result = -ENOMEM; 2098 struct nvme_dev *dev; 2099 unsigned long quirks = id->driver_data; 2100 2101 node = dev_to_node(&pdev->dev); 2102 if (node == NUMA_NO_NODE) 2103 set_dev_node(&pdev->dev, first_memory_node); 2104 2105 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2106 if (!dev) 2107 return -ENOMEM; 2108 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 2109 GFP_KERNEL, node); 2110 if (!dev->queues) 2111 goto free; 2112 2113 dev->dev = get_device(&pdev->dev); 2114 pci_set_drvdata(pdev, dev); 2115 2116 result = nvme_dev_map(dev); 2117 if (result) 2118 goto free; 2119 2120 INIT_WORK(&dev->reset_work, nvme_reset_work); 2121 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2122 setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, 2123 (unsigned long)dev); 2124 mutex_init(&dev->shutdown_lock); 2125 init_completion(&dev->ioq_wait); 2126 2127 result = nvme_setup_prp_pools(dev); 2128 if (result) 2129 goto put_pci; 2130 2131 quirks |= check_dell_samsung_bug(pdev); 2132 2133 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2134 quirks); 2135 if (result) 2136 goto release_pools; 2137 2138 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2139 2140 queue_work(nvme_workq, &dev->reset_work); 2141 return 0; 2142 2143 release_pools: 2144 nvme_release_prp_pools(dev); 2145 put_pci: 2146 put_device(dev->dev); 2147 nvme_dev_unmap(dev); 2148 free: 2149 kfree(dev->queues); 2150 kfree(dev); 2151 return result; 2152 } 2153 2154 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) 2155 { 2156 struct nvme_dev *dev = pci_get_drvdata(pdev); 2157 2158 if (prepare) 2159 nvme_dev_disable(dev, false); 2160 else 2161 nvme_reset(dev); 2162 } 2163 2164 static void nvme_shutdown(struct pci_dev *pdev) 2165 { 2166 struct nvme_dev *dev = pci_get_drvdata(pdev); 2167 nvme_dev_disable(dev, true); 2168 } 2169 2170 /* 2171 * The driver's remove may be called on a device in a partially initialized 2172 * state. This function must not have any dependencies on the device state in 2173 * order to proceed. 2174 */ 2175 static void nvme_remove(struct pci_dev *pdev) 2176 { 2177 struct nvme_dev *dev = pci_get_drvdata(pdev); 2178 2179 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2180 2181 pci_set_drvdata(pdev, NULL); 2182 2183 if (!pci_device_is_present(pdev)) { 2184 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2185 nvme_dev_disable(dev, false); 2186 } 2187 2188 flush_work(&dev->reset_work); 2189 nvme_uninit_ctrl(&dev->ctrl); 2190 nvme_dev_disable(dev, true); 2191 nvme_dev_remove_admin(dev); 2192 nvme_free_queues(dev, 0); 2193 nvme_release_prp_pools(dev); 2194 nvme_dev_unmap(dev); 2195 nvme_put_ctrl(&dev->ctrl); 2196 } 2197 2198 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 2199 { 2200 int ret = 0; 2201 2202 if (numvfs == 0) { 2203 if (pci_vfs_assigned(pdev)) { 2204 dev_warn(&pdev->dev, 2205 "Cannot disable SR-IOV VFs while assigned\n"); 2206 return -EPERM; 2207 } 2208 pci_disable_sriov(pdev); 2209 return 0; 2210 } 2211 2212 ret = pci_enable_sriov(pdev, numvfs); 2213 return ret ? ret : numvfs; 2214 } 2215 2216 #ifdef CONFIG_PM_SLEEP 2217 static int nvme_suspend(struct device *dev) 2218 { 2219 struct pci_dev *pdev = to_pci_dev(dev); 2220 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2221 2222 nvme_dev_disable(ndev, true); 2223 return 0; 2224 } 2225 2226 static int nvme_resume(struct device *dev) 2227 { 2228 struct pci_dev *pdev = to_pci_dev(dev); 2229 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2230 2231 nvme_reset(ndev); 2232 return 0; 2233 } 2234 #endif 2235 2236 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2237 2238 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2239 pci_channel_state_t state) 2240 { 2241 struct nvme_dev *dev = pci_get_drvdata(pdev); 2242 2243 /* 2244 * A frozen channel requires a reset. When detected, this method will 2245 * shutdown the controller to quiesce. The controller will be restarted 2246 * after the slot reset through driver's slot_reset callback. 2247 */ 2248 switch (state) { 2249 case pci_channel_io_normal: 2250 return PCI_ERS_RESULT_CAN_RECOVER; 2251 case pci_channel_io_frozen: 2252 dev_warn(dev->ctrl.device, 2253 "frozen state error detected, reset controller\n"); 2254 nvme_dev_disable(dev, false); 2255 return PCI_ERS_RESULT_NEED_RESET; 2256 case pci_channel_io_perm_failure: 2257 dev_warn(dev->ctrl.device, 2258 "failure state error detected, request disconnect\n"); 2259 return PCI_ERS_RESULT_DISCONNECT; 2260 } 2261 return PCI_ERS_RESULT_NEED_RESET; 2262 } 2263 2264 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2265 { 2266 struct nvme_dev *dev = pci_get_drvdata(pdev); 2267 2268 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2269 pci_restore_state(pdev); 2270 nvme_reset(dev); 2271 return PCI_ERS_RESULT_RECOVERED; 2272 } 2273 2274 static void nvme_error_resume(struct pci_dev *pdev) 2275 { 2276 pci_cleanup_aer_uncorrect_error_status(pdev); 2277 } 2278 2279 static const struct pci_error_handlers nvme_err_handler = { 2280 .error_detected = nvme_error_detected, 2281 .slot_reset = nvme_slot_reset, 2282 .resume = nvme_error_resume, 2283 .reset_notify = nvme_reset_notify, 2284 }; 2285 2286 static const struct pci_device_id nvme_id_table[] = { 2287 { PCI_VDEVICE(INTEL, 0x0953), 2288 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2289 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2290 { PCI_VDEVICE(INTEL, 0x0a53), 2291 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2292 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2293 { PCI_VDEVICE(INTEL, 0x0a54), 2294 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2295 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2296 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2297 .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 2298 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 2299 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2300 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2301 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2302 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2303 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2304 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 2305 { 0, } 2306 }; 2307 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2308 2309 static struct pci_driver nvme_driver = { 2310 .name = "nvme", 2311 .id_table = nvme_id_table, 2312 .probe = nvme_probe, 2313 .remove = nvme_remove, 2314 .shutdown = nvme_shutdown, 2315 .driver = { 2316 .pm = &nvme_dev_pm_ops, 2317 }, 2318 .sriov_configure = nvme_pci_sriov_configure, 2319 .err_handler = &nvme_err_handler, 2320 }; 2321 2322 static int __init nvme_init(void) 2323 { 2324 int result; 2325 2326 nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); 2327 if (!nvme_workq) 2328 return -ENOMEM; 2329 2330 result = pci_register_driver(&nvme_driver); 2331 if (result) 2332 destroy_workqueue(nvme_workq); 2333 return result; 2334 } 2335 2336 static void __exit nvme_exit(void) 2337 { 2338 pci_unregister_driver(&nvme_driver); 2339 destroy_workqueue(nvme_workq); 2340 _nvme_check_size(); 2341 } 2342 2343 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2344 MODULE_LICENSE("GPL"); 2345 MODULE_VERSION("1.0"); 2346 module_init(nvme_init); 2347 module_exit(nvme_exit); 2348