xref: /openbmc/linux/drivers/nvme/host/pci.c (revision 82003e04)
1 /*
2  * NVM Express device driver
3  * Copyright (c) 2011-2014, Intel Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms and conditions of the GNU General Public License,
7  * version 2, as published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  */
14 
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/errno.h>
23 #include <linux/fs.h>
24 #include <linux/genhd.h>
25 #include <linux/hdreg.h>
26 #include <linux/idr.h>
27 #include <linux/init.h>
28 #include <linux/interrupt.h>
29 #include <linux/io.h>
30 #include <linux/kdev_t.h>
31 #include <linux/kernel.h>
32 #include <linux/mm.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/mutex.h>
36 #include <linux/pci.h>
37 #include <linux/poison.h>
38 #include <linux/ptrace.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/t10-pi.h>
42 #include <linux/timer.h>
43 #include <linux/types.h>
44 #include <linux/io-64-nonatomic-lo-hi.h>
45 #include <asm/unaligned.h>
46 
47 #include "nvme.h"
48 
49 #define NVME_Q_DEPTH		1024
50 #define NVME_AQ_DEPTH		256
51 #define SQ_SIZE(depth)		(depth * sizeof(struct nvme_command))
52 #define CQ_SIZE(depth)		(depth * sizeof(struct nvme_completion))
53 
54 /*
55  * We handle AEN commands ourselves and don't even let the
56  * block layer know about them.
57  */
58 #define NVME_AQ_BLKMQ_DEPTH	(NVME_AQ_DEPTH - NVME_NR_AERS)
59 
60 static int use_threaded_interrupts;
61 module_param(use_threaded_interrupts, int, 0);
62 
63 static bool use_cmb_sqes = true;
64 module_param(use_cmb_sqes, bool, 0644);
65 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
66 
67 static struct workqueue_struct *nvme_workq;
68 
69 struct nvme_dev;
70 struct nvme_queue;
71 
72 static int nvme_reset(struct nvme_dev *dev);
73 static void nvme_process_cq(struct nvme_queue *nvmeq);
74 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
75 
76 /*
77  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
78  */
79 struct nvme_dev {
80 	struct nvme_queue **queues;
81 	struct blk_mq_tag_set tagset;
82 	struct blk_mq_tag_set admin_tagset;
83 	u32 __iomem *dbs;
84 	struct device *dev;
85 	struct dma_pool *prp_page_pool;
86 	struct dma_pool *prp_small_pool;
87 	unsigned queue_count;
88 	unsigned online_queues;
89 	unsigned max_qid;
90 	int q_depth;
91 	u32 db_stride;
92 	void __iomem *bar;
93 	struct work_struct reset_work;
94 	struct work_struct remove_work;
95 	struct timer_list watchdog_timer;
96 	struct mutex shutdown_lock;
97 	bool subsystem;
98 	void __iomem *cmb;
99 	dma_addr_t cmb_dma_addr;
100 	u64 cmb_size;
101 	u32 cmbsz;
102 	u32 cmbloc;
103 	struct nvme_ctrl ctrl;
104 	struct completion ioq_wait;
105 };
106 
107 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
108 {
109 	return container_of(ctrl, struct nvme_dev, ctrl);
110 }
111 
112 /*
113  * An NVM Express queue.  Each device has at least two (one for admin
114  * commands and one for I/O commands).
115  */
116 struct nvme_queue {
117 	struct device *q_dmadev;
118 	struct nvme_dev *dev;
119 	char irqname[24];	/* nvme4294967295-65535\0 */
120 	spinlock_t q_lock;
121 	struct nvme_command *sq_cmds;
122 	struct nvme_command __iomem *sq_cmds_io;
123 	volatile struct nvme_completion *cqes;
124 	struct blk_mq_tags **tags;
125 	dma_addr_t sq_dma_addr;
126 	dma_addr_t cq_dma_addr;
127 	u32 __iomem *q_db;
128 	u16 q_depth;
129 	s16 cq_vector;
130 	u16 sq_tail;
131 	u16 cq_head;
132 	u16 qid;
133 	u8 cq_phase;
134 	u8 cqe_seen;
135 };
136 
137 /*
138  * The nvme_iod describes the data in an I/O, including the list of PRP
139  * entries.  You can't see it in this data structure because C doesn't let
140  * me express that.  Use nvme_init_iod to ensure there's enough space
141  * allocated to store the PRP list.
142  */
143 struct nvme_iod {
144 	struct nvme_queue *nvmeq;
145 	int aborted;
146 	int npages;		/* In the PRP list. 0 means small pool in use */
147 	int nents;		/* Used in scatterlist */
148 	int length;		/* Of data, in bytes */
149 	dma_addr_t first_dma;
150 	struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
151 	struct scatterlist *sg;
152 	struct scatterlist inline_sg[0];
153 };
154 
155 /*
156  * Check we didin't inadvertently grow the command struct
157  */
158 static inline void _nvme_check_size(void)
159 {
160 	BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
161 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
162 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
163 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
164 	BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
165 	BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
166 	BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
167 	BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
168 	BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
169 	BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
170 	BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
171 	BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
172 }
173 
174 /*
175  * Max size of iod being embedded in the request payload
176  */
177 #define NVME_INT_PAGES		2
178 #define NVME_INT_BYTES(dev)	(NVME_INT_PAGES * (dev)->ctrl.page_size)
179 
180 /*
181  * Will slightly overestimate the number of pages needed.  This is OK
182  * as it only leads to a small amount of wasted memory for the lifetime of
183  * the I/O.
184  */
185 static int nvme_npages(unsigned size, struct nvme_dev *dev)
186 {
187 	unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
188 				      dev->ctrl.page_size);
189 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
190 }
191 
192 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
193 		unsigned int size, unsigned int nseg)
194 {
195 	return sizeof(__le64 *) * nvme_npages(size, dev) +
196 			sizeof(struct scatterlist) * nseg;
197 }
198 
199 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
200 {
201 	return sizeof(struct nvme_iod) +
202 		nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
203 }
204 
205 static int nvmeq_irq(struct nvme_queue *nvmeq)
206 {
207 	return pci_irq_vector(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector);
208 }
209 
210 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
211 				unsigned int hctx_idx)
212 {
213 	struct nvme_dev *dev = data;
214 	struct nvme_queue *nvmeq = dev->queues[0];
215 
216 	WARN_ON(hctx_idx != 0);
217 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
218 	WARN_ON(nvmeq->tags);
219 
220 	hctx->driver_data = nvmeq;
221 	nvmeq->tags = &dev->admin_tagset.tags[0];
222 	return 0;
223 }
224 
225 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
226 {
227 	struct nvme_queue *nvmeq = hctx->driver_data;
228 
229 	nvmeq->tags = NULL;
230 }
231 
232 static int nvme_admin_init_request(void *data, struct request *req,
233 				unsigned int hctx_idx, unsigned int rq_idx,
234 				unsigned int numa_node)
235 {
236 	struct nvme_dev *dev = data;
237 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
238 	struct nvme_queue *nvmeq = dev->queues[0];
239 
240 	BUG_ON(!nvmeq);
241 	iod->nvmeq = nvmeq;
242 	return 0;
243 }
244 
245 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
246 			  unsigned int hctx_idx)
247 {
248 	struct nvme_dev *dev = data;
249 	struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
250 
251 	if (!nvmeq->tags)
252 		nvmeq->tags = &dev->tagset.tags[hctx_idx];
253 
254 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
255 	hctx->driver_data = nvmeq;
256 	return 0;
257 }
258 
259 static int nvme_init_request(void *data, struct request *req,
260 				unsigned int hctx_idx, unsigned int rq_idx,
261 				unsigned int numa_node)
262 {
263 	struct nvme_dev *dev = data;
264 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
265 	struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
266 
267 	BUG_ON(!nvmeq);
268 	iod->nvmeq = nvmeq;
269 	return 0;
270 }
271 
272 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
273 {
274 	struct nvme_dev *dev = set->driver_data;
275 
276 	return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
277 }
278 
279 /**
280  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
281  * @nvmeq: The queue to use
282  * @cmd: The command to send
283  *
284  * Safe to use from interrupt context
285  */
286 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
287 						struct nvme_command *cmd)
288 {
289 	u16 tail = nvmeq->sq_tail;
290 
291 	if (nvmeq->sq_cmds_io)
292 		memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
293 	else
294 		memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
295 
296 	if (++tail == nvmeq->q_depth)
297 		tail = 0;
298 	writel(tail, nvmeq->q_db);
299 	nvmeq->sq_tail = tail;
300 }
301 
302 static __le64 **iod_list(struct request *req)
303 {
304 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
305 	return (__le64 **)(iod->sg + req->nr_phys_segments);
306 }
307 
308 static int nvme_init_iod(struct request *rq, unsigned size,
309 		struct nvme_dev *dev)
310 {
311 	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
312 	int nseg = rq->nr_phys_segments;
313 
314 	if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
315 		iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
316 		if (!iod->sg)
317 			return BLK_MQ_RQ_QUEUE_BUSY;
318 	} else {
319 		iod->sg = iod->inline_sg;
320 	}
321 
322 	iod->aborted = 0;
323 	iod->npages = -1;
324 	iod->nents = 0;
325 	iod->length = size;
326 
327 	if (!(rq->cmd_flags & REQ_DONTPREP)) {
328 		rq->retries = 0;
329 		rq->cmd_flags |= REQ_DONTPREP;
330 	}
331 	return 0;
332 }
333 
334 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
335 {
336 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
337 	const int last_prp = dev->ctrl.page_size / 8 - 1;
338 	int i;
339 	__le64 **list = iod_list(req);
340 	dma_addr_t prp_dma = iod->first_dma;
341 
342 	nvme_cleanup_cmd(req);
343 
344 	if (iod->npages == 0)
345 		dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
346 	for (i = 0; i < iod->npages; i++) {
347 		__le64 *prp_list = list[i];
348 		dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
349 		dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
350 		prp_dma = next_prp_dma;
351 	}
352 
353 	if (iod->sg != iod->inline_sg)
354 		kfree(iod->sg);
355 }
356 
357 #ifdef CONFIG_BLK_DEV_INTEGRITY
358 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
359 {
360 	if (be32_to_cpu(pi->ref_tag) == v)
361 		pi->ref_tag = cpu_to_be32(p);
362 }
363 
364 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
365 {
366 	if (be32_to_cpu(pi->ref_tag) == p)
367 		pi->ref_tag = cpu_to_be32(v);
368 }
369 
370 /**
371  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
372  *
373  * The virtual start sector is the one that was originally submitted by the
374  * block layer.	Due to partitioning, MD/DM cloning, etc. the actual physical
375  * start sector may be different. Remap protection information to match the
376  * physical LBA on writes, and back to the original seed on reads.
377  *
378  * Type 0 and 3 do not have a ref tag, so no remapping required.
379  */
380 static void nvme_dif_remap(struct request *req,
381 			void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
382 {
383 	struct nvme_ns *ns = req->rq_disk->private_data;
384 	struct bio_integrity_payload *bip;
385 	struct t10_pi_tuple *pi;
386 	void *p, *pmap;
387 	u32 i, nlb, ts, phys, virt;
388 
389 	if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
390 		return;
391 
392 	bip = bio_integrity(req->bio);
393 	if (!bip)
394 		return;
395 
396 	pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
397 
398 	p = pmap;
399 	virt = bip_get_seed(bip);
400 	phys = nvme_block_nr(ns, blk_rq_pos(req));
401 	nlb = (blk_rq_bytes(req) >> ns->lba_shift);
402 	ts = ns->disk->queue->integrity.tuple_size;
403 
404 	for (i = 0; i < nlb; i++, virt++, phys++) {
405 		pi = (struct t10_pi_tuple *)p;
406 		dif_swap(phys, virt, pi);
407 		p += ts;
408 	}
409 	kunmap_atomic(pmap);
410 }
411 #else /* CONFIG_BLK_DEV_INTEGRITY */
412 static void nvme_dif_remap(struct request *req,
413 			void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
414 {
415 }
416 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
417 {
418 }
419 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
420 {
421 }
422 #endif
423 
424 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req,
425 		int total_len)
426 {
427 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
428 	struct dma_pool *pool;
429 	int length = total_len;
430 	struct scatterlist *sg = iod->sg;
431 	int dma_len = sg_dma_len(sg);
432 	u64 dma_addr = sg_dma_address(sg);
433 	u32 page_size = dev->ctrl.page_size;
434 	int offset = dma_addr & (page_size - 1);
435 	__le64 *prp_list;
436 	__le64 **list = iod_list(req);
437 	dma_addr_t prp_dma;
438 	int nprps, i;
439 
440 	length -= (page_size - offset);
441 	if (length <= 0)
442 		return true;
443 
444 	dma_len -= (page_size - offset);
445 	if (dma_len) {
446 		dma_addr += (page_size - offset);
447 	} else {
448 		sg = sg_next(sg);
449 		dma_addr = sg_dma_address(sg);
450 		dma_len = sg_dma_len(sg);
451 	}
452 
453 	if (length <= page_size) {
454 		iod->first_dma = dma_addr;
455 		return true;
456 	}
457 
458 	nprps = DIV_ROUND_UP(length, page_size);
459 	if (nprps <= (256 / 8)) {
460 		pool = dev->prp_small_pool;
461 		iod->npages = 0;
462 	} else {
463 		pool = dev->prp_page_pool;
464 		iod->npages = 1;
465 	}
466 
467 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
468 	if (!prp_list) {
469 		iod->first_dma = dma_addr;
470 		iod->npages = -1;
471 		return false;
472 	}
473 	list[0] = prp_list;
474 	iod->first_dma = prp_dma;
475 	i = 0;
476 	for (;;) {
477 		if (i == page_size >> 3) {
478 			__le64 *old_prp_list = prp_list;
479 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
480 			if (!prp_list)
481 				return false;
482 			list[iod->npages++] = prp_list;
483 			prp_list[0] = old_prp_list[i - 1];
484 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
485 			i = 1;
486 		}
487 		prp_list[i++] = cpu_to_le64(dma_addr);
488 		dma_len -= page_size;
489 		dma_addr += page_size;
490 		length -= page_size;
491 		if (length <= 0)
492 			break;
493 		if (dma_len > 0)
494 			continue;
495 		BUG_ON(dma_len < 0);
496 		sg = sg_next(sg);
497 		dma_addr = sg_dma_address(sg);
498 		dma_len = sg_dma_len(sg);
499 	}
500 
501 	return true;
502 }
503 
504 static int nvme_map_data(struct nvme_dev *dev, struct request *req,
505 		unsigned size, struct nvme_command *cmnd)
506 {
507 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
508 	struct request_queue *q = req->q;
509 	enum dma_data_direction dma_dir = rq_data_dir(req) ?
510 			DMA_TO_DEVICE : DMA_FROM_DEVICE;
511 	int ret = BLK_MQ_RQ_QUEUE_ERROR;
512 
513 	sg_init_table(iod->sg, req->nr_phys_segments);
514 	iod->nents = blk_rq_map_sg(q, req, iod->sg);
515 	if (!iod->nents)
516 		goto out;
517 
518 	ret = BLK_MQ_RQ_QUEUE_BUSY;
519 	if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
520 				DMA_ATTR_NO_WARN))
521 		goto out;
522 
523 	if (!nvme_setup_prps(dev, req, size))
524 		goto out_unmap;
525 
526 	ret = BLK_MQ_RQ_QUEUE_ERROR;
527 	if (blk_integrity_rq(req)) {
528 		if (blk_rq_count_integrity_sg(q, req->bio) != 1)
529 			goto out_unmap;
530 
531 		sg_init_table(&iod->meta_sg, 1);
532 		if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
533 			goto out_unmap;
534 
535 		if (rq_data_dir(req))
536 			nvme_dif_remap(req, nvme_dif_prep);
537 
538 		if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
539 			goto out_unmap;
540 	}
541 
542 	cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
543 	cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
544 	if (blk_integrity_rq(req))
545 		cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
546 	return BLK_MQ_RQ_QUEUE_OK;
547 
548 out_unmap:
549 	dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
550 out:
551 	return ret;
552 }
553 
554 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
555 {
556 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
557 	enum dma_data_direction dma_dir = rq_data_dir(req) ?
558 			DMA_TO_DEVICE : DMA_FROM_DEVICE;
559 
560 	if (iod->nents) {
561 		dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
562 		if (blk_integrity_rq(req)) {
563 			if (!rq_data_dir(req))
564 				nvme_dif_remap(req, nvme_dif_complete);
565 			dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
566 		}
567 	}
568 
569 	nvme_free_iod(dev, req);
570 }
571 
572 /*
573  * NOTE: ns is NULL when called on the admin queue.
574  */
575 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
576 			 const struct blk_mq_queue_data *bd)
577 {
578 	struct nvme_ns *ns = hctx->queue->queuedata;
579 	struct nvme_queue *nvmeq = hctx->driver_data;
580 	struct nvme_dev *dev = nvmeq->dev;
581 	struct request *req = bd->rq;
582 	struct nvme_command cmnd;
583 	unsigned map_len;
584 	int ret = BLK_MQ_RQ_QUEUE_OK;
585 
586 	/*
587 	 * If formated with metadata, require the block layer provide a buffer
588 	 * unless this namespace is formated such that the metadata can be
589 	 * stripped/generated by the controller with PRACT=1.
590 	 */
591 	if (ns && ns->ms && !blk_integrity_rq(req)) {
592 		if (!(ns->pi_type && ns->ms == 8) &&
593 					req->cmd_type != REQ_TYPE_DRV_PRIV) {
594 			blk_mq_end_request(req, -EFAULT);
595 			return BLK_MQ_RQ_QUEUE_OK;
596 		}
597 	}
598 
599 	map_len = nvme_map_len(req);
600 	ret = nvme_init_iod(req, map_len, dev);
601 	if (ret)
602 		return ret;
603 
604 	ret = nvme_setup_cmd(ns, req, &cmnd);
605 	if (ret)
606 		goto out;
607 
608 	if (req->nr_phys_segments)
609 		ret = nvme_map_data(dev, req, map_len, &cmnd);
610 
611 	if (ret)
612 		goto out;
613 
614 	cmnd.common.command_id = req->tag;
615 	blk_mq_start_request(req);
616 
617 	spin_lock_irq(&nvmeq->q_lock);
618 	if (unlikely(nvmeq->cq_vector < 0)) {
619 		if (ns && !test_bit(NVME_NS_DEAD, &ns->flags))
620 			ret = BLK_MQ_RQ_QUEUE_BUSY;
621 		else
622 			ret = BLK_MQ_RQ_QUEUE_ERROR;
623 		spin_unlock_irq(&nvmeq->q_lock);
624 		goto out;
625 	}
626 	__nvme_submit_cmd(nvmeq, &cmnd);
627 	nvme_process_cq(nvmeq);
628 	spin_unlock_irq(&nvmeq->q_lock);
629 	return BLK_MQ_RQ_QUEUE_OK;
630 out:
631 	nvme_free_iod(dev, req);
632 	return ret;
633 }
634 
635 static void nvme_complete_rq(struct request *req)
636 {
637 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
638 	struct nvme_dev *dev = iod->nvmeq->dev;
639 	int error = 0;
640 
641 	nvme_unmap_data(dev, req);
642 
643 	if (unlikely(req->errors)) {
644 		if (nvme_req_needs_retry(req, req->errors)) {
645 			req->retries++;
646 			nvme_requeue_req(req);
647 			return;
648 		}
649 
650 		if (req->cmd_type == REQ_TYPE_DRV_PRIV)
651 			error = req->errors;
652 		else
653 			error = nvme_error_status(req->errors);
654 	}
655 
656 	if (unlikely(iod->aborted)) {
657 		dev_warn(dev->ctrl.device,
658 			"completing aborted command with status: %04x\n",
659 			req->errors);
660 	}
661 
662 	blk_mq_end_request(req, error);
663 }
664 
665 /* We read the CQE phase first to check if the rest of the entry is valid */
666 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
667 		u16 phase)
668 {
669 	return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
670 }
671 
672 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag)
673 {
674 	u16 head, phase;
675 
676 	head = nvmeq->cq_head;
677 	phase = nvmeq->cq_phase;
678 
679 	while (nvme_cqe_valid(nvmeq, head, phase)) {
680 		struct nvme_completion cqe = nvmeq->cqes[head];
681 		struct request *req;
682 
683 		if (++head == nvmeq->q_depth) {
684 			head = 0;
685 			phase = !phase;
686 		}
687 
688 		if (tag && *tag == cqe.command_id)
689 			*tag = -1;
690 
691 		if (unlikely(cqe.command_id >= nvmeq->q_depth)) {
692 			dev_warn(nvmeq->dev->ctrl.device,
693 				"invalid id %d completed on queue %d\n",
694 				cqe.command_id, le16_to_cpu(cqe.sq_id));
695 			continue;
696 		}
697 
698 		/*
699 		 * AEN requests are special as they don't time out and can
700 		 * survive any kind of queue freeze and often don't respond to
701 		 * aborts.  We don't even bother to allocate a struct request
702 		 * for them but rather special case them here.
703 		 */
704 		if (unlikely(nvmeq->qid == 0 &&
705 				cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) {
706 			nvme_complete_async_event(&nvmeq->dev->ctrl, &cqe);
707 			continue;
708 		}
709 
710 		req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id);
711 		if (req->cmd_type == REQ_TYPE_DRV_PRIV && req->special)
712 			memcpy(req->special, &cqe, sizeof(cqe));
713 		blk_mq_complete_request(req, le16_to_cpu(cqe.status) >> 1);
714 
715 	}
716 
717 	/* If the controller ignores the cq head doorbell and continuously
718 	 * writes to the queue, it is theoretically possible to wrap around
719 	 * the queue twice and mistakenly return IRQ_NONE.  Linux only
720 	 * requires that 0.1% of your interrupts are handled, so this isn't
721 	 * a big problem.
722 	 */
723 	if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
724 		return;
725 
726 	if (likely(nvmeq->cq_vector >= 0))
727 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
728 	nvmeq->cq_head = head;
729 	nvmeq->cq_phase = phase;
730 
731 	nvmeq->cqe_seen = 1;
732 }
733 
734 static void nvme_process_cq(struct nvme_queue *nvmeq)
735 {
736 	__nvme_process_cq(nvmeq, NULL);
737 }
738 
739 static irqreturn_t nvme_irq(int irq, void *data)
740 {
741 	irqreturn_t result;
742 	struct nvme_queue *nvmeq = data;
743 	spin_lock(&nvmeq->q_lock);
744 	nvme_process_cq(nvmeq);
745 	result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
746 	nvmeq->cqe_seen = 0;
747 	spin_unlock(&nvmeq->q_lock);
748 	return result;
749 }
750 
751 static irqreturn_t nvme_irq_check(int irq, void *data)
752 {
753 	struct nvme_queue *nvmeq = data;
754 	if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
755 		return IRQ_WAKE_THREAD;
756 	return IRQ_NONE;
757 }
758 
759 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
760 {
761 	struct nvme_queue *nvmeq = hctx->driver_data;
762 
763 	if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
764 		spin_lock_irq(&nvmeq->q_lock);
765 		__nvme_process_cq(nvmeq, &tag);
766 		spin_unlock_irq(&nvmeq->q_lock);
767 
768 		if (tag == -1)
769 			return 1;
770 	}
771 
772 	return 0;
773 }
774 
775 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
776 {
777 	struct nvme_dev *dev = to_nvme_dev(ctrl);
778 	struct nvme_queue *nvmeq = dev->queues[0];
779 	struct nvme_command c;
780 
781 	memset(&c, 0, sizeof(c));
782 	c.common.opcode = nvme_admin_async_event;
783 	c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
784 
785 	spin_lock_irq(&nvmeq->q_lock);
786 	__nvme_submit_cmd(nvmeq, &c);
787 	spin_unlock_irq(&nvmeq->q_lock);
788 }
789 
790 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
791 {
792 	struct nvme_command c;
793 
794 	memset(&c, 0, sizeof(c));
795 	c.delete_queue.opcode = opcode;
796 	c.delete_queue.qid = cpu_to_le16(id);
797 
798 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
799 }
800 
801 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
802 						struct nvme_queue *nvmeq)
803 {
804 	struct nvme_command c;
805 	int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
806 
807 	/*
808 	 * Note: we (ab)use the fact the the prp fields survive if no data
809 	 * is attached to the request.
810 	 */
811 	memset(&c, 0, sizeof(c));
812 	c.create_cq.opcode = nvme_admin_create_cq;
813 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
814 	c.create_cq.cqid = cpu_to_le16(qid);
815 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
816 	c.create_cq.cq_flags = cpu_to_le16(flags);
817 	c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
818 
819 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
820 }
821 
822 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
823 						struct nvme_queue *nvmeq)
824 {
825 	struct nvme_command c;
826 	int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
827 
828 	/*
829 	 * Note: we (ab)use the fact the the prp fields survive if no data
830 	 * is attached to the request.
831 	 */
832 	memset(&c, 0, sizeof(c));
833 	c.create_sq.opcode = nvme_admin_create_sq;
834 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
835 	c.create_sq.sqid = cpu_to_le16(qid);
836 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
837 	c.create_sq.sq_flags = cpu_to_le16(flags);
838 	c.create_sq.cqid = cpu_to_le16(qid);
839 
840 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
841 }
842 
843 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
844 {
845 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
846 }
847 
848 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
849 {
850 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
851 }
852 
853 static void abort_endio(struct request *req, int error)
854 {
855 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
856 	struct nvme_queue *nvmeq = iod->nvmeq;
857 	u16 status = req->errors;
858 
859 	dev_warn(nvmeq->dev->ctrl.device, "Abort status: 0x%x", status);
860 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
861 	blk_mq_free_request(req);
862 }
863 
864 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
865 {
866 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
867 	struct nvme_queue *nvmeq = iod->nvmeq;
868 	struct nvme_dev *dev = nvmeq->dev;
869 	struct request *abort_req;
870 	struct nvme_command cmd;
871 
872 	/*
873 	 * Shutdown immediately if controller times out while starting. The
874 	 * reset work will see the pci device disabled when it gets the forced
875 	 * cancellation error. All outstanding requests are completed on
876 	 * shutdown, so we return BLK_EH_HANDLED.
877 	 */
878 	if (dev->ctrl.state == NVME_CTRL_RESETTING) {
879 		dev_warn(dev->ctrl.device,
880 			 "I/O %d QID %d timeout, disable controller\n",
881 			 req->tag, nvmeq->qid);
882 		nvme_dev_disable(dev, false);
883 		req->errors = NVME_SC_CANCELLED;
884 		return BLK_EH_HANDLED;
885 	}
886 
887 	/*
888  	 * Shutdown the controller immediately and schedule a reset if the
889  	 * command was already aborted once before and still hasn't been
890  	 * returned to the driver, or if this is the admin queue.
891 	 */
892 	if (!nvmeq->qid || iod->aborted) {
893 		dev_warn(dev->ctrl.device,
894 			 "I/O %d QID %d timeout, reset controller\n",
895 			 req->tag, nvmeq->qid);
896 		nvme_dev_disable(dev, false);
897 		nvme_reset(dev);
898 
899 		/*
900 		 * Mark the request as handled, since the inline shutdown
901 		 * forces all outstanding requests to complete.
902 		 */
903 		req->errors = NVME_SC_CANCELLED;
904 		return BLK_EH_HANDLED;
905 	}
906 
907 	iod->aborted = 1;
908 
909 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
910 		atomic_inc(&dev->ctrl.abort_limit);
911 		return BLK_EH_RESET_TIMER;
912 	}
913 
914 	memset(&cmd, 0, sizeof(cmd));
915 	cmd.abort.opcode = nvme_admin_abort_cmd;
916 	cmd.abort.cid = req->tag;
917 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
918 
919 	dev_warn(nvmeq->dev->ctrl.device,
920 		"I/O %d QID %d timeout, aborting\n",
921 		 req->tag, nvmeq->qid);
922 
923 	abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
924 			BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
925 	if (IS_ERR(abort_req)) {
926 		atomic_inc(&dev->ctrl.abort_limit);
927 		return BLK_EH_RESET_TIMER;
928 	}
929 
930 	abort_req->timeout = ADMIN_TIMEOUT;
931 	abort_req->end_io_data = NULL;
932 	blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
933 
934 	/*
935 	 * The aborted req will be completed on receiving the abort req.
936 	 * We enable the timer again. If hit twice, it'll cause a device reset,
937 	 * as the device then is in a faulty state.
938 	 */
939 	return BLK_EH_RESET_TIMER;
940 }
941 
942 static void nvme_free_queue(struct nvme_queue *nvmeq)
943 {
944 	dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
945 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
946 	if (nvmeq->sq_cmds)
947 		dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
948 					nvmeq->sq_cmds, nvmeq->sq_dma_addr);
949 	kfree(nvmeq);
950 }
951 
952 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
953 {
954 	int i;
955 
956 	for (i = dev->queue_count - 1; i >= lowest; i--) {
957 		struct nvme_queue *nvmeq = dev->queues[i];
958 		dev->queue_count--;
959 		dev->queues[i] = NULL;
960 		nvme_free_queue(nvmeq);
961 	}
962 }
963 
964 /**
965  * nvme_suspend_queue - put queue into suspended state
966  * @nvmeq - queue to suspend
967  */
968 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
969 {
970 	int vector;
971 
972 	spin_lock_irq(&nvmeq->q_lock);
973 	if (nvmeq->cq_vector == -1) {
974 		spin_unlock_irq(&nvmeq->q_lock);
975 		return 1;
976 	}
977 	vector = nvmeq_irq(nvmeq);
978 	nvmeq->dev->online_queues--;
979 	nvmeq->cq_vector = -1;
980 	spin_unlock_irq(&nvmeq->q_lock);
981 
982 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
983 		blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
984 
985 	free_irq(vector, nvmeq);
986 
987 	return 0;
988 }
989 
990 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
991 {
992 	struct nvme_queue *nvmeq = dev->queues[0];
993 
994 	if (!nvmeq)
995 		return;
996 	if (nvme_suspend_queue(nvmeq))
997 		return;
998 
999 	if (shutdown)
1000 		nvme_shutdown_ctrl(&dev->ctrl);
1001 	else
1002 		nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1003 						dev->bar + NVME_REG_CAP));
1004 
1005 	spin_lock_irq(&nvmeq->q_lock);
1006 	nvme_process_cq(nvmeq);
1007 	spin_unlock_irq(&nvmeq->q_lock);
1008 }
1009 
1010 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1011 				int entry_size)
1012 {
1013 	int q_depth = dev->q_depth;
1014 	unsigned q_size_aligned = roundup(q_depth * entry_size,
1015 					  dev->ctrl.page_size);
1016 
1017 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1018 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1019 		mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1020 		q_depth = div_u64(mem_per_q, entry_size);
1021 
1022 		/*
1023 		 * Ensure the reduced q_depth is above some threshold where it
1024 		 * would be better to map queues in system memory with the
1025 		 * original depth
1026 		 */
1027 		if (q_depth < 64)
1028 			return -ENOMEM;
1029 	}
1030 
1031 	return q_depth;
1032 }
1033 
1034 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1035 				int qid, int depth)
1036 {
1037 	if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1038 		unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1039 						      dev->ctrl.page_size);
1040 		nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1041 		nvmeq->sq_cmds_io = dev->cmb + offset;
1042 	} else {
1043 		nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1044 					&nvmeq->sq_dma_addr, GFP_KERNEL);
1045 		if (!nvmeq->sq_cmds)
1046 			return -ENOMEM;
1047 	}
1048 
1049 	return 0;
1050 }
1051 
1052 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1053 							int depth)
1054 {
1055 	struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL);
1056 	if (!nvmeq)
1057 		return NULL;
1058 
1059 	nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1060 					  &nvmeq->cq_dma_addr, GFP_KERNEL);
1061 	if (!nvmeq->cqes)
1062 		goto free_nvmeq;
1063 
1064 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1065 		goto free_cqdma;
1066 
1067 	nvmeq->q_dmadev = dev->dev;
1068 	nvmeq->dev = dev;
1069 	snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1070 			dev->ctrl.instance, qid);
1071 	spin_lock_init(&nvmeq->q_lock);
1072 	nvmeq->cq_head = 0;
1073 	nvmeq->cq_phase = 1;
1074 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1075 	nvmeq->q_depth = depth;
1076 	nvmeq->qid = qid;
1077 	nvmeq->cq_vector = -1;
1078 	dev->queues[qid] = nvmeq;
1079 	dev->queue_count++;
1080 
1081 	return nvmeq;
1082 
1083  free_cqdma:
1084 	dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1085 							nvmeq->cq_dma_addr);
1086  free_nvmeq:
1087 	kfree(nvmeq);
1088 	return NULL;
1089 }
1090 
1091 static int queue_request_irq(struct nvme_queue *nvmeq)
1092 {
1093 	if (use_threaded_interrupts)
1094 		return request_threaded_irq(nvmeq_irq(nvmeq), nvme_irq_check,
1095 				nvme_irq, IRQF_SHARED, nvmeq->irqname, nvmeq);
1096 	else
1097 		return request_irq(nvmeq_irq(nvmeq), nvme_irq, IRQF_SHARED,
1098 				nvmeq->irqname, nvmeq);
1099 }
1100 
1101 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1102 {
1103 	struct nvme_dev *dev = nvmeq->dev;
1104 
1105 	spin_lock_irq(&nvmeq->q_lock);
1106 	nvmeq->sq_tail = 0;
1107 	nvmeq->cq_head = 0;
1108 	nvmeq->cq_phase = 1;
1109 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1110 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1111 	dev->online_queues++;
1112 	spin_unlock_irq(&nvmeq->q_lock);
1113 }
1114 
1115 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1116 {
1117 	struct nvme_dev *dev = nvmeq->dev;
1118 	int result;
1119 
1120 	nvmeq->cq_vector = qid - 1;
1121 	result = adapter_alloc_cq(dev, qid, nvmeq);
1122 	if (result < 0)
1123 		return result;
1124 
1125 	result = adapter_alloc_sq(dev, qid, nvmeq);
1126 	if (result < 0)
1127 		goto release_cq;
1128 
1129 	result = queue_request_irq(nvmeq);
1130 	if (result < 0)
1131 		goto release_sq;
1132 
1133 	nvme_init_queue(nvmeq, qid);
1134 	return result;
1135 
1136  release_sq:
1137 	adapter_delete_sq(dev, qid);
1138  release_cq:
1139 	adapter_delete_cq(dev, qid);
1140 	return result;
1141 }
1142 
1143 static struct blk_mq_ops nvme_mq_admin_ops = {
1144 	.queue_rq	= nvme_queue_rq,
1145 	.complete	= nvme_complete_rq,
1146 	.init_hctx	= nvme_admin_init_hctx,
1147 	.exit_hctx      = nvme_admin_exit_hctx,
1148 	.init_request	= nvme_admin_init_request,
1149 	.timeout	= nvme_timeout,
1150 };
1151 
1152 static struct blk_mq_ops nvme_mq_ops = {
1153 	.queue_rq	= nvme_queue_rq,
1154 	.complete	= nvme_complete_rq,
1155 	.init_hctx	= nvme_init_hctx,
1156 	.init_request	= nvme_init_request,
1157 	.map_queues	= nvme_pci_map_queues,
1158 	.timeout	= nvme_timeout,
1159 	.poll		= nvme_poll,
1160 };
1161 
1162 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1163 {
1164 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1165 		/*
1166 		 * If the controller was reset during removal, it's possible
1167 		 * user requests may be waiting on a stopped queue. Start the
1168 		 * queue to flush these to completion.
1169 		 */
1170 		blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1171 		blk_cleanup_queue(dev->ctrl.admin_q);
1172 		blk_mq_free_tag_set(&dev->admin_tagset);
1173 	}
1174 }
1175 
1176 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1177 {
1178 	if (!dev->ctrl.admin_q) {
1179 		dev->admin_tagset.ops = &nvme_mq_admin_ops;
1180 		dev->admin_tagset.nr_hw_queues = 1;
1181 
1182 		/*
1183 		 * Subtract one to leave an empty queue entry for 'Full Queue'
1184 		 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1185 		 */
1186 		dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1187 		dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1188 		dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1189 		dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1190 		dev->admin_tagset.driver_data = dev;
1191 
1192 		if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1193 			return -ENOMEM;
1194 
1195 		dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1196 		if (IS_ERR(dev->ctrl.admin_q)) {
1197 			blk_mq_free_tag_set(&dev->admin_tagset);
1198 			return -ENOMEM;
1199 		}
1200 		if (!blk_get_queue(dev->ctrl.admin_q)) {
1201 			nvme_dev_remove_admin(dev);
1202 			dev->ctrl.admin_q = NULL;
1203 			return -ENODEV;
1204 		}
1205 	} else
1206 		blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1207 
1208 	return 0;
1209 }
1210 
1211 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1212 {
1213 	int result;
1214 	u32 aqa;
1215 	u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1216 	struct nvme_queue *nvmeq;
1217 
1218 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1219 						NVME_CAP_NSSRC(cap) : 0;
1220 
1221 	if (dev->subsystem &&
1222 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1223 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1224 
1225 	result = nvme_disable_ctrl(&dev->ctrl, cap);
1226 	if (result < 0)
1227 		return result;
1228 
1229 	nvmeq = dev->queues[0];
1230 	if (!nvmeq) {
1231 		nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1232 		if (!nvmeq)
1233 			return -ENOMEM;
1234 	}
1235 
1236 	aqa = nvmeq->q_depth - 1;
1237 	aqa |= aqa << 16;
1238 
1239 	writel(aqa, dev->bar + NVME_REG_AQA);
1240 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1241 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1242 
1243 	result = nvme_enable_ctrl(&dev->ctrl, cap);
1244 	if (result)
1245 		goto free_nvmeq;
1246 
1247 	nvmeq->cq_vector = 0;
1248 	result = queue_request_irq(nvmeq);
1249 	if (result) {
1250 		nvmeq->cq_vector = -1;
1251 		goto free_nvmeq;
1252 	}
1253 
1254 	return result;
1255 
1256  free_nvmeq:
1257 	nvme_free_queues(dev, 0);
1258 	return result;
1259 }
1260 
1261 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1262 {
1263 
1264 	/* If true, indicates loss of adapter communication, possibly by a
1265 	 * NVMe Subsystem reset.
1266 	 */
1267 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1268 
1269 	/* If there is a reset ongoing, we shouldn't reset again. */
1270 	if (work_busy(&dev->reset_work))
1271 		return false;
1272 
1273 	/* We shouldn't reset unless the controller is on fatal error state
1274 	 * _or_ if we lost the communication with it.
1275 	 */
1276 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1277 		return false;
1278 
1279 	/* If PCI error recovery process is happening, we cannot reset or
1280 	 * the recovery mechanism will surely fail.
1281 	 */
1282 	if (pci_channel_offline(to_pci_dev(dev->dev)))
1283 		return false;
1284 
1285 	return true;
1286 }
1287 
1288 static void nvme_watchdog_timer(unsigned long data)
1289 {
1290 	struct nvme_dev *dev = (struct nvme_dev *)data;
1291 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1292 
1293 	/* Skip controllers under certain specific conditions. */
1294 	if (nvme_should_reset(dev, csts)) {
1295 		if (!nvme_reset(dev))
1296 			dev_warn(dev->dev,
1297 				"Failed status: 0x%x, reset controller.\n",
1298 				csts);
1299 		return;
1300 	}
1301 
1302 	mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1303 }
1304 
1305 static int nvme_create_io_queues(struct nvme_dev *dev)
1306 {
1307 	unsigned i, max;
1308 	int ret = 0;
1309 
1310 	for (i = dev->queue_count; i <= dev->max_qid; i++) {
1311 		if (!nvme_alloc_queue(dev, i, dev->q_depth)) {
1312 			ret = -ENOMEM;
1313 			break;
1314 		}
1315 	}
1316 
1317 	max = min(dev->max_qid, dev->queue_count - 1);
1318 	for (i = dev->online_queues; i <= max; i++) {
1319 		ret = nvme_create_queue(dev->queues[i], i);
1320 		if (ret) {
1321 			nvme_free_queues(dev, i);
1322 			break;
1323 		}
1324 	}
1325 
1326 	/*
1327 	 * Ignore failing Create SQ/CQ commands, we can continue with less
1328 	 * than the desired aount of queues, and even a controller without
1329 	 * I/O queues an still be used to issue admin commands.  This might
1330 	 * be useful to upgrade a buggy firmware for example.
1331 	 */
1332 	return ret >= 0 ? 0 : ret;
1333 }
1334 
1335 static ssize_t nvme_cmb_show(struct device *dev,
1336 			     struct device_attribute *attr,
1337 			     char *buf)
1338 {
1339 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1340 
1341 	return snprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1342 		       ndev->cmbloc, ndev->cmbsz);
1343 }
1344 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1345 
1346 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1347 {
1348 	u64 szu, size, offset;
1349 	resource_size_t bar_size;
1350 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1351 	void __iomem *cmb;
1352 	dma_addr_t dma_addr;
1353 
1354 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1355 	if (!(NVME_CMB_SZ(dev->cmbsz)))
1356 		return NULL;
1357 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1358 
1359 	if (!use_cmb_sqes)
1360 		return NULL;
1361 
1362 	szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1363 	size = szu * NVME_CMB_SZ(dev->cmbsz);
1364 	offset = szu * NVME_CMB_OFST(dev->cmbloc);
1365 	bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1366 
1367 	if (offset > bar_size)
1368 		return NULL;
1369 
1370 	/*
1371 	 * Controllers may support a CMB size larger than their BAR,
1372 	 * for example, due to being behind a bridge. Reduce the CMB to
1373 	 * the reported size of the BAR
1374 	 */
1375 	if (size > bar_size - offset)
1376 		size = bar_size - offset;
1377 
1378 	dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1379 	cmb = ioremap_wc(dma_addr, size);
1380 	if (!cmb)
1381 		return NULL;
1382 
1383 	dev->cmb_dma_addr = dma_addr;
1384 	dev->cmb_size = size;
1385 	return cmb;
1386 }
1387 
1388 static inline void nvme_release_cmb(struct nvme_dev *dev)
1389 {
1390 	if (dev->cmb) {
1391 		iounmap(dev->cmb);
1392 		dev->cmb = NULL;
1393 	}
1394 }
1395 
1396 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1397 {
1398 	return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
1399 }
1400 
1401 static int nvme_setup_io_queues(struct nvme_dev *dev)
1402 {
1403 	struct nvme_queue *adminq = dev->queues[0];
1404 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1405 	int result, nr_io_queues, size;
1406 
1407 	nr_io_queues = num_online_cpus();
1408 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1409 	if (result < 0)
1410 		return result;
1411 
1412 	if (nr_io_queues == 0)
1413 		return 0;
1414 
1415 	if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1416 		result = nvme_cmb_qdepth(dev, nr_io_queues,
1417 				sizeof(struct nvme_command));
1418 		if (result > 0)
1419 			dev->q_depth = result;
1420 		else
1421 			nvme_release_cmb(dev);
1422 	}
1423 
1424 	size = db_bar_size(dev, nr_io_queues);
1425 	if (size > 8192) {
1426 		iounmap(dev->bar);
1427 		do {
1428 			dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1429 			if (dev->bar)
1430 				break;
1431 			if (!--nr_io_queues)
1432 				return -ENOMEM;
1433 			size = db_bar_size(dev, nr_io_queues);
1434 		} while (1);
1435 		dev->dbs = dev->bar + 4096;
1436 		adminq->q_db = dev->dbs;
1437 	}
1438 
1439 	/* Deregister the admin queue's interrupt */
1440 	free_irq(pci_irq_vector(pdev, 0), adminq);
1441 
1442 	/*
1443 	 * If we enable msix early due to not intx, disable it again before
1444 	 * setting up the full range we need.
1445 	 */
1446 	pci_free_irq_vectors(pdev);
1447 	nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1448 			PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1449 	if (nr_io_queues <= 0)
1450 		return -EIO;
1451 	dev->max_qid = nr_io_queues;
1452 
1453 	/*
1454 	 * Should investigate if there's a performance win from allocating
1455 	 * more queues than interrupt vectors; it might allow the submission
1456 	 * path to scale better, even if the receive path is limited by the
1457 	 * number of interrupts.
1458 	 */
1459 
1460 	result = queue_request_irq(adminq);
1461 	if (result) {
1462 		adminq->cq_vector = -1;
1463 		goto free_queues;
1464 	}
1465 	return nvme_create_io_queues(dev);
1466 
1467  free_queues:
1468 	nvme_free_queues(dev, 1);
1469 	return result;
1470 }
1471 
1472 static void nvme_del_queue_end(struct request *req, int error)
1473 {
1474 	struct nvme_queue *nvmeq = req->end_io_data;
1475 
1476 	blk_mq_free_request(req);
1477 	complete(&nvmeq->dev->ioq_wait);
1478 }
1479 
1480 static void nvme_del_cq_end(struct request *req, int error)
1481 {
1482 	struct nvme_queue *nvmeq = req->end_io_data;
1483 
1484 	if (!error) {
1485 		unsigned long flags;
1486 
1487 		/*
1488 		 * We might be called with the AQ q_lock held
1489 		 * and the I/O queue q_lock should always
1490 		 * nest inside the AQ one.
1491 		 */
1492 		spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1493 					SINGLE_DEPTH_NESTING);
1494 		nvme_process_cq(nvmeq);
1495 		spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1496 	}
1497 
1498 	nvme_del_queue_end(req, error);
1499 }
1500 
1501 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1502 {
1503 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1504 	struct request *req;
1505 	struct nvme_command cmd;
1506 
1507 	memset(&cmd, 0, sizeof(cmd));
1508 	cmd.delete_queue.opcode = opcode;
1509 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1510 
1511 	req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1512 	if (IS_ERR(req))
1513 		return PTR_ERR(req);
1514 
1515 	req->timeout = ADMIN_TIMEOUT;
1516 	req->end_io_data = nvmeq;
1517 
1518 	blk_execute_rq_nowait(q, NULL, req, false,
1519 			opcode == nvme_admin_delete_cq ?
1520 				nvme_del_cq_end : nvme_del_queue_end);
1521 	return 0;
1522 }
1523 
1524 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1525 {
1526 	int pass;
1527 	unsigned long timeout;
1528 	u8 opcode = nvme_admin_delete_sq;
1529 
1530 	for (pass = 0; pass < 2; pass++) {
1531 		int sent = 0, i = queues;
1532 
1533 		reinit_completion(&dev->ioq_wait);
1534  retry:
1535 		timeout = ADMIN_TIMEOUT;
1536 		for (; i > 0; i--, sent++)
1537 			if (nvme_delete_queue(dev->queues[i], opcode))
1538 				break;
1539 
1540 		while (sent--) {
1541 			timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1542 			if (timeout == 0)
1543 				return;
1544 			if (i)
1545 				goto retry;
1546 		}
1547 		opcode = nvme_admin_delete_cq;
1548 	}
1549 }
1550 
1551 /*
1552  * Return: error value if an error occurred setting up the queues or calling
1553  * Identify Device.  0 if these succeeded, even if adding some of the
1554  * namespaces failed.  At the moment, these failures are silent.  TBD which
1555  * failures should be reported.
1556  */
1557 static int nvme_dev_add(struct nvme_dev *dev)
1558 {
1559 	if (!dev->ctrl.tagset) {
1560 		dev->tagset.ops = &nvme_mq_ops;
1561 		dev->tagset.nr_hw_queues = dev->online_queues - 1;
1562 		dev->tagset.timeout = NVME_IO_TIMEOUT;
1563 		dev->tagset.numa_node = dev_to_node(dev->dev);
1564 		dev->tagset.queue_depth =
1565 				min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1566 		dev->tagset.cmd_size = nvme_cmd_size(dev);
1567 		dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1568 		dev->tagset.driver_data = dev;
1569 
1570 		if (blk_mq_alloc_tag_set(&dev->tagset))
1571 			return 0;
1572 		dev->ctrl.tagset = &dev->tagset;
1573 	} else {
1574 		blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1575 
1576 		/* Free previously allocated queues that are no longer usable */
1577 		nvme_free_queues(dev, dev->online_queues);
1578 	}
1579 
1580 	return 0;
1581 }
1582 
1583 static int nvme_pci_enable(struct nvme_dev *dev)
1584 {
1585 	u64 cap;
1586 	int result = -ENOMEM;
1587 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1588 
1589 	if (pci_enable_device_mem(pdev))
1590 		return result;
1591 
1592 	pci_set_master(pdev);
1593 
1594 	if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1595 	    dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1596 		goto disable;
1597 
1598 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1599 		result = -ENODEV;
1600 		goto disable;
1601 	}
1602 
1603 	/*
1604 	 * Some devices and/or platforms don't advertise or work with INTx
1605 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1606 	 * adjust this later.
1607 	 */
1608 	result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1609 	if (result < 0)
1610 		return result;
1611 
1612 	cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1613 
1614 	dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1615 	dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1616 	dev->dbs = dev->bar + 4096;
1617 
1618 	/*
1619 	 * Temporary fix for the Apple controller found in the MacBook8,1 and
1620 	 * some MacBook7,1 to avoid controller resets and data loss.
1621 	 */
1622 	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1623 		dev->q_depth = 2;
1624 		dev_warn(dev->dev, "detected Apple NVMe controller, set "
1625 			"queue depth=%u to work around controller resets\n",
1626 			dev->q_depth);
1627 	}
1628 
1629 	/*
1630 	 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1631 	 * populate sysfs if a CMB is implemented. Note that we add the
1632 	 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1633 	 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1634 	 * NULL as final argument to sysfs_add_file_to_group.
1635 	 */
1636 
1637 	if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1638 		dev->cmb = nvme_map_cmb(dev);
1639 
1640 		if (dev->cmbsz) {
1641 			if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1642 						    &dev_attr_cmb.attr, NULL))
1643 				dev_warn(dev->dev,
1644 					 "failed to add sysfs attribute for CMB\n");
1645 		}
1646 	}
1647 
1648 	pci_enable_pcie_error_reporting(pdev);
1649 	pci_save_state(pdev);
1650 	return 0;
1651 
1652  disable:
1653 	pci_disable_device(pdev);
1654 	return result;
1655 }
1656 
1657 static void nvme_dev_unmap(struct nvme_dev *dev)
1658 {
1659 	if (dev->bar)
1660 		iounmap(dev->bar);
1661 	pci_release_mem_regions(to_pci_dev(dev->dev));
1662 }
1663 
1664 static void nvme_pci_disable(struct nvme_dev *dev)
1665 {
1666 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1667 
1668 	pci_free_irq_vectors(pdev);
1669 
1670 	if (pci_is_enabled(pdev)) {
1671 		pci_disable_pcie_error_reporting(pdev);
1672 		pci_disable_device(pdev);
1673 	}
1674 }
1675 
1676 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1677 {
1678 	int i, queues;
1679 	u32 csts = -1;
1680 
1681 	del_timer_sync(&dev->watchdog_timer);
1682 
1683 	mutex_lock(&dev->shutdown_lock);
1684 	if (pci_is_enabled(to_pci_dev(dev->dev))) {
1685 		nvme_stop_queues(&dev->ctrl);
1686 		csts = readl(dev->bar + NVME_REG_CSTS);
1687 	}
1688 
1689 	queues = dev->online_queues - 1;
1690 	for (i = dev->queue_count - 1; i > 0; i--)
1691 		nvme_suspend_queue(dev->queues[i]);
1692 
1693 	if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) {
1694 		/* A device might become IO incapable very soon during
1695 		 * probe, before the admin queue is configured. Thus,
1696 		 * queue_count can be 0 here.
1697 		 */
1698 		if (dev->queue_count)
1699 			nvme_suspend_queue(dev->queues[0]);
1700 	} else {
1701 		nvme_disable_io_queues(dev, queues);
1702 		nvme_disable_admin_queue(dev, shutdown);
1703 	}
1704 	nvme_pci_disable(dev);
1705 
1706 	blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
1707 	blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
1708 	mutex_unlock(&dev->shutdown_lock);
1709 }
1710 
1711 static int nvme_setup_prp_pools(struct nvme_dev *dev)
1712 {
1713 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
1714 						PAGE_SIZE, PAGE_SIZE, 0);
1715 	if (!dev->prp_page_pool)
1716 		return -ENOMEM;
1717 
1718 	/* Optimisation for I/Os between 4k and 128k */
1719 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
1720 						256, 256, 0);
1721 	if (!dev->prp_small_pool) {
1722 		dma_pool_destroy(dev->prp_page_pool);
1723 		return -ENOMEM;
1724 	}
1725 	return 0;
1726 }
1727 
1728 static void nvme_release_prp_pools(struct nvme_dev *dev)
1729 {
1730 	dma_pool_destroy(dev->prp_page_pool);
1731 	dma_pool_destroy(dev->prp_small_pool);
1732 }
1733 
1734 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
1735 {
1736 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1737 
1738 	put_device(dev->dev);
1739 	if (dev->tagset.tags)
1740 		blk_mq_free_tag_set(&dev->tagset);
1741 	if (dev->ctrl.admin_q)
1742 		blk_put_queue(dev->ctrl.admin_q);
1743 	kfree(dev->queues);
1744 	kfree(dev);
1745 }
1746 
1747 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
1748 {
1749 	dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
1750 
1751 	kref_get(&dev->ctrl.kref);
1752 	nvme_dev_disable(dev, false);
1753 	if (!schedule_work(&dev->remove_work))
1754 		nvme_put_ctrl(&dev->ctrl);
1755 }
1756 
1757 static void nvme_reset_work(struct work_struct *work)
1758 {
1759 	struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
1760 	int result = -ENODEV;
1761 
1762 	if (WARN_ON(dev->ctrl.state == NVME_CTRL_RESETTING))
1763 		goto out;
1764 
1765 	/*
1766 	 * If we're called to reset a live controller first shut it down before
1767 	 * moving on.
1768 	 */
1769 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
1770 		nvme_dev_disable(dev, false);
1771 
1772 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING))
1773 		goto out;
1774 
1775 	result = nvme_pci_enable(dev);
1776 	if (result)
1777 		goto out;
1778 
1779 	result = nvme_configure_admin_queue(dev);
1780 	if (result)
1781 		goto out;
1782 
1783 	nvme_init_queue(dev->queues[0], 0);
1784 	result = nvme_alloc_admin_tags(dev);
1785 	if (result)
1786 		goto out;
1787 
1788 	result = nvme_init_identify(&dev->ctrl);
1789 	if (result)
1790 		goto out;
1791 
1792 	result = nvme_setup_io_queues(dev);
1793 	if (result)
1794 		goto out;
1795 
1796 	/*
1797 	 * A controller that can not execute IO typically requires user
1798 	 * intervention to correct. For such degraded controllers, the driver
1799 	 * should not submit commands the user did not request, so skip
1800 	 * registering for asynchronous event notification on this condition.
1801 	 */
1802 	if (dev->online_queues > 1)
1803 		nvme_queue_async_events(&dev->ctrl);
1804 
1805 	mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ));
1806 
1807 	/*
1808 	 * Keep the controller around but remove all namespaces if we don't have
1809 	 * any working I/O queue.
1810 	 */
1811 	if (dev->online_queues < 2) {
1812 		dev_warn(dev->ctrl.device, "IO queues not created\n");
1813 		nvme_kill_queues(&dev->ctrl);
1814 		nvme_remove_namespaces(&dev->ctrl);
1815 	} else {
1816 		nvme_start_queues(&dev->ctrl);
1817 		nvme_dev_add(dev);
1818 	}
1819 
1820 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
1821 		dev_warn(dev->ctrl.device, "failed to mark controller live\n");
1822 		goto out;
1823 	}
1824 
1825 	if (dev->online_queues > 1)
1826 		nvme_queue_scan(&dev->ctrl);
1827 	return;
1828 
1829  out:
1830 	nvme_remove_dead_ctrl(dev, result);
1831 }
1832 
1833 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
1834 {
1835 	struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
1836 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1837 
1838 	nvme_kill_queues(&dev->ctrl);
1839 	if (pci_get_drvdata(pdev))
1840 		device_release_driver(&pdev->dev);
1841 	nvme_put_ctrl(&dev->ctrl);
1842 }
1843 
1844 static int nvme_reset(struct nvme_dev *dev)
1845 {
1846 	if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q))
1847 		return -ENODEV;
1848 	if (work_busy(&dev->reset_work))
1849 		return -ENODEV;
1850 	if (!queue_work(nvme_workq, &dev->reset_work))
1851 		return -EBUSY;
1852 	return 0;
1853 }
1854 
1855 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
1856 {
1857 	*val = readl(to_nvme_dev(ctrl)->bar + off);
1858 	return 0;
1859 }
1860 
1861 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
1862 {
1863 	writel(val, to_nvme_dev(ctrl)->bar + off);
1864 	return 0;
1865 }
1866 
1867 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
1868 {
1869 	*val = readq(to_nvme_dev(ctrl)->bar + off);
1870 	return 0;
1871 }
1872 
1873 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl)
1874 {
1875 	struct nvme_dev *dev = to_nvme_dev(ctrl);
1876 	int ret = nvme_reset(dev);
1877 
1878 	if (!ret)
1879 		flush_work(&dev->reset_work);
1880 	return ret;
1881 }
1882 
1883 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
1884 	.name			= "pcie",
1885 	.module			= THIS_MODULE,
1886 	.reg_read32		= nvme_pci_reg_read32,
1887 	.reg_write32		= nvme_pci_reg_write32,
1888 	.reg_read64		= nvme_pci_reg_read64,
1889 	.reset_ctrl		= nvme_pci_reset_ctrl,
1890 	.free_ctrl		= nvme_pci_free_ctrl,
1891 	.submit_async_event	= nvme_pci_submit_async_event,
1892 };
1893 
1894 static int nvme_dev_map(struct nvme_dev *dev)
1895 {
1896 	struct pci_dev *pdev = to_pci_dev(dev->dev);
1897 
1898 	if (pci_request_mem_regions(pdev, "nvme"))
1899 		return -ENODEV;
1900 
1901 	dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
1902 	if (!dev->bar)
1903 		goto release;
1904 
1905        return 0;
1906   release:
1907        pci_release_mem_regions(pdev);
1908        return -ENODEV;
1909 }
1910 
1911 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1912 {
1913 	int node, result = -ENOMEM;
1914 	struct nvme_dev *dev;
1915 
1916 	node = dev_to_node(&pdev->dev);
1917 	if (node == NUMA_NO_NODE)
1918 		set_dev_node(&pdev->dev, first_memory_node);
1919 
1920 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
1921 	if (!dev)
1922 		return -ENOMEM;
1923 	dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
1924 							GFP_KERNEL, node);
1925 	if (!dev->queues)
1926 		goto free;
1927 
1928 	dev->dev = get_device(&pdev->dev);
1929 	pci_set_drvdata(pdev, dev);
1930 
1931 	result = nvme_dev_map(dev);
1932 	if (result)
1933 		goto free;
1934 
1935 	INIT_WORK(&dev->reset_work, nvme_reset_work);
1936 	INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
1937 	setup_timer(&dev->watchdog_timer, nvme_watchdog_timer,
1938 		(unsigned long)dev);
1939 	mutex_init(&dev->shutdown_lock);
1940 	init_completion(&dev->ioq_wait);
1941 
1942 	result = nvme_setup_prp_pools(dev);
1943 	if (result)
1944 		goto put_pci;
1945 
1946 	result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
1947 			id->driver_data);
1948 	if (result)
1949 		goto release_pools;
1950 
1951 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
1952 
1953 	queue_work(nvme_workq, &dev->reset_work);
1954 	return 0;
1955 
1956  release_pools:
1957 	nvme_release_prp_pools(dev);
1958  put_pci:
1959 	put_device(dev->dev);
1960 	nvme_dev_unmap(dev);
1961  free:
1962 	kfree(dev->queues);
1963 	kfree(dev);
1964 	return result;
1965 }
1966 
1967 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
1968 {
1969 	struct nvme_dev *dev = pci_get_drvdata(pdev);
1970 
1971 	if (prepare)
1972 		nvme_dev_disable(dev, false);
1973 	else
1974 		nvme_reset(dev);
1975 }
1976 
1977 static void nvme_shutdown(struct pci_dev *pdev)
1978 {
1979 	struct nvme_dev *dev = pci_get_drvdata(pdev);
1980 	nvme_dev_disable(dev, true);
1981 }
1982 
1983 /*
1984  * The driver's remove may be called on a device in a partially initialized
1985  * state. This function must not have any dependencies on the device state in
1986  * order to proceed.
1987  */
1988 static void nvme_remove(struct pci_dev *pdev)
1989 {
1990 	struct nvme_dev *dev = pci_get_drvdata(pdev);
1991 
1992 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1993 
1994 	pci_set_drvdata(pdev, NULL);
1995 
1996 	if (!pci_device_is_present(pdev))
1997 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
1998 
1999 	flush_work(&dev->reset_work);
2000 	nvme_uninit_ctrl(&dev->ctrl);
2001 	nvme_dev_disable(dev, true);
2002 	nvme_dev_remove_admin(dev);
2003 	nvme_free_queues(dev, 0);
2004 	nvme_release_cmb(dev);
2005 	nvme_release_prp_pools(dev);
2006 	nvme_dev_unmap(dev);
2007 	nvme_put_ctrl(&dev->ctrl);
2008 }
2009 
2010 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2011 {
2012 	int ret = 0;
2013 
2014 	if (numvfs == 0) {
2015 		if (pci_vfs_assigned(pdev)) {
2016 			dev_warn(&pdev->dev,
2017 				"Cannot disable SR-IOV VFs while assigned\n");
2018 			return -EPERM;
2019 		}
2020 		pci_disable_sriov(pdev);
2021 		return 0;
2022 	}
2023 
2024 	ret = pci_enable_sriov(pdev, numvfs);
2025 	return ret ? ret : numvfs;
2026 }
2027 
2028 #ifdef CONFIG_PM_SLEEP
2029 static int nvme_suspend(struct device *dev)
2030 {
2031 	struct pci_dev *pdev = to_pci_dev(dev);
2032 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
2033 
2034 	nvme_dev_disable(ndev, true);
2035 	return 0;
2036 }
2037 
2038 static int nvme_resume(struct device *dev)
2039 {
2040 	struct pci_dev *pdev = to_pci_dev(dev);
2041 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
2042 
2043 	nvme_reset(ndev);
2044 	return 0;
2045 }
2046 #endif
2047 
2048 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2049 
2050 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2051 						pci_channel_state_t state)
2052 {
2053 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2054 
2055 	/*
2056 	 * A frozen channel requires a reset. When detected, this method will
2057 	 * shutdown the controller to quiesce. The controller will be restarted
2058 	 * after the slot reset through driver's slot_reset callback.
2059 	 */
2060 	switch (state) {
2061 	case pci_channel_io_normal:
2062 		return PCI_ERS_RESULT_CAN_RECOVER;
2063 	case pci_channel_io_frozen:
2064 		dev_warn(dev->ctrl.device,
2065 			"frozen state error detected, reset controller\n");
2066 		nvme_dev_disable(dev, false);
2067 		return PCI_ERS_RESULT_NEED_RESET;
2068 	case pci_channel_io_perm_failure:
2069 		dev_warn(dev->ctrl.device,
2070 			"failure state error detected, request disconnect\n");
2071 		return PCI_ERS_RESULT_DISCONNECT;
2072 	}
2073 	return PCI_ERS_RESULT_NEED_RESET;
2074 }
2075 
2076 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2077 {
2078 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2079 
2080 	dev_info(dev->ctrl.device, "restart after slot reset\n");
2081 	pci_restore_state(pdev);
2082 	nvme_reset(dev);
2083 	return PCI_ERS_RESULT_RECOVERED;
2084 }
2085 
2086 static void nvme_error_resume(struct pci_dev *pdev)
2087 {
2088 	pci_cleanup_aer_uncorrect_error_status(pdev);
2089 }
2090 
2091 static const struct pci_error_handlers nvme_err_handler = {
2092 	.error_detected	= nvme_error_detected,
2093 	.slot_reset	= nvme_slot_reset,
2094 	.resume		= nvme_error_resume,
2095 	.reset_notify	= nvme_reset_notify,
2096 };
2097 
2098 /* Move to pci_ids.h later */
2099 #define PCI_CLASS_STORAGE_EXPRESS	0x010802
2100 
2101 static const struct pci_device_id nvme_id_table[] = {
2102 	{ PCI_VDEVICE(INTEL, 0x0953),
2103 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2104 				NVME_QUIRK_DISCARD_ZEROES, },
2105 	{ PCI_VDEVICE(INTEL, 0x0a53),
2106 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2107 				NVME_QUIRK_DISCARD_ZEROES, },
2108 	{ PCI_VDEVICE(INTEL, 0x0a54),
2109 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2110 				NVME_QUIRK_DISCARD_ZEROES, },
2111 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
2112 		.driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2113 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
2114 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2115 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
2116 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2117 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2118 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2119 	{ 0, }
2120 };
2121 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2122 
2123 static struct pci_driver nvme_driver = {
2124 	.name		= "nvme",
2125 	.id_table	= nvme_id_table,
2126 	.probe		= nvme_probe,
2127 	.remove		= nvme_remove,
2128 	.shutdown	= nvme_shutdown,
2129 	.driver		= {
2130 		.pm	= &nvme_dev_pm_ops,
2131 	},
2132 	.sriov_configure = nvme_pci_sriov_configure,
2133 	.err_handler	= &nvme_err_handler,
2134 };
2135 
2136 static int __init nvme_init(void)
2137 {
2138 	int result;
2139 
2140 	nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0);
2141 	if (!nvme_workq)
2142 		return -ENOMEM;
2143 
2144 	result = pci_register_driver(&nvme_driver);
2145 	if (result)
2146 		destroy_workqueue(nvme_workq);
2147 	return result;
2148 }
2149 
2150 static void __exit nvme_exit(void)
2151 {
2152 	pci_unregister_driver(&nvme_driver);
2153 	destroy_workqueue(nvme_workq);
2154 	_nvme_check_size();
2155 }
2156 
2157 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2158 MODULE_LICENSE("GPL");
2159 MODULE_VERSION("1.0");
2160 module_init(nvme_init);
2161 module_exit(nvme_exit);
2162