1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 32 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static int write_queues; 72 module_param(write_queues, int, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static int poll_queues; 78 module_param(poll_queues, int, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 u32 db_stride; 104 void __iomem *bar; 105 unsigned long bar_mapped_size; 106 struct work_struct remove_work; 107 struct mutex shutdown_lock; 108 bool subsystem; 109 u64 cmb_size; 110 bool cmb_use_sqes; 111 u32 cmbsz; 112 u32 cmbloc; 113 struct nvme_ctrl ctrl; 114 u32 last_ps; 115 116 mempool_t *iod_mempool; 117 118 /* shadow doorbell buffer support: */ 119 u32 *dbbuf_dbs; 120 dma_addr_t dbbuf_dbs_dma_addr; 121 u32 *dbbuf_eis; 122 dma_addr_t dbbuf_eis_dma_addr; 123 124 /* host memory buffer support: */ 125 u64 host_mem_size; 126 u32 nr_host_mem_descs; 127 dma_addr_t host_mem_descs_dma; 128 struct nvme_host_mem_buf_desc *host_mem_descs; 129 void **host_mem_desc_bufs; 130 }; 131 132 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 133 { 134 int n = 0, ret; 135 136 ret = kstrtoint(val, 10, &n); 137 if (ret != 0 || n < 2) 138 return -EINVAL; 139 140 return param_set_int(val, kp); 141 } 142 143 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 144 { 145 return qid * 2 * stride; 146 } 147 148 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 149 { 150 return (qid * 2 + 1) * stride; 151 } 152 153 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 154 { 155 return container_of(ctrl, struct nvme_dev, ctrl); 156 } 157 158 /* 159 * An NVM Express queue. Each device has at least two (one for admin 160 * commands and one for I/O commands). 161 */ 162 struct nvme_queue { 163 struct nvme_dev *dev; 164 spinlock_t sq_lock; 165 struct nvme_command *sq_cmds; 166 /* only used for poll queues: */ 167 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 168 volatile struct nvme_completion *cqes; 169 struct blk_mq_tags **tags; 170 dma_addr_t sq_dma_addr; 171 dma_addr_t cq_dma_addr; 172 u32 __iomem *q_db; 173 u16 q_depth; 174 u16 cq_vector; 175 u16 sq_tail; 176 u16 last_sq_tail; 177 u16 cq_head; 178 u16 last_cq_head; 179 u16 qid; 180 u8 cq_phase; 181 unsigned long flags; 182 #define NVMEQ_ENABLED 0 183 #define NVMEQ_SQ_CMB 1 184 #define NVMEQ_DELETE_ERROR 2 185 #define NVMEQ_POLLED 3 186 u32 *dbbuf_sq_db; 187 u32 *dbbuf_cq_db; 188 u32 *dbbuf_sq_ei; 189 u32 *dbbuf_cq_ei; 190 struct completion delete_done; 191 }; 192 193 /* 194 * The nvme_iod describes the data in an I/O. 195 * 196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 197 * to the actual struct scatterlist. 198 */ 199 struct nvme_iod { 200 struct nvme_request req; 201 struct nvme_queue *nvmeq; 202 bool use_sgl; 203 int aborted; 204 int npages; /* In the PRP list. 0 means small pool in use */ 205 int nents; /* Used in scatterlist */ 206 dma_addr_t first_dma; 207 unsigned int dma_len; /* length of single DMA segment mapping */ 208 dma_addr_t meta_dma; 209 struct scatterlist *sg; 210 }; 211 212 static unsigned int max_io_queues(void) 213 { 214 return num_possible_cpus() + write_queues + poll_queues; 215 } 216 217 static unsigned int max_queue_count(void) 218 { 219 /* IO queues + admin queue */ 220 return 1 + max_io_queues(); 221 } 222 223 static inline unsigned int nvme_dbbuf_size(u32 stride) 224 { 225 return (max_queue_count() * 8 * stride); 226 } 227 228 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229 { 230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231 232 if (dev->dbbuf_dbs) 233 return 0; 234 235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236 &dev->dbbuf_dbs_dma_addr, 237 GFP_KERNEL); 238 if (!dev->dbbuf_dbs) 239 return -ENOMEM; 240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241 &dev->dbbuf_eis_dma_addr, 242 GFP_KERNEL); 243 if (!dev->dbbuf_eis) { 244 dma_free_coherent(dev->dev, mem_size, 245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246 dev->dbbuf_dbs = NULL; 247 return -ENOMEM; 248 } 249 250 return 0; 251 } 252 253 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254 { 255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256 257 if (dev->dbbuf_dbs) { 258 dma_free_coherent(dev->dev, mem_size, 259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260 dev->dbbuf_dbs = NULL; 261 } 262 if (dev->dbbuf_eis) { 263 dma_free_coherent(dev->dev, mem_size, 264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265 dev->dbbuf_eis = NULL; 266 } 267 } 268 269 static void nvme_dbbuf_init(struct nvme_dev *dev, 270 struct nvme_queue *nvmeq, int qid) 271 { 272 if (!dev->dbbuf_dbs || !qid) 273 return; 274 275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279 } 280 281 static void nvme_dbbuf_set(struct nvme_dev *dev) 282 { 283 struct nvme_command c; 284 285 if (!dev->dbbuf_dbs) 286 return; 287 288 memset(&c, 0, sizeof(c)); 289 c.dbbuf.opcode = nvme_admin_dbbuf; 290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292 293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295 /* Free memory and continue on */ 296 nvme_dbbuf_dma_free(dev); 297 } 298 } 299 300 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301 { 302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303 } 304 305 /* Update dbbuf and return true if an MMIO is required */ 306 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307 volatile u32 *dbbuf_ei) 308 { 309 if (dbbuf_db) { 310 u16 old_value; 311 312 /* 313 * Ensure that the queue is written before updating 314 * the doorbell in memory 315 */ 316 wmb(); 317 318 old_value = *dbbuf_db; 319 *dbbuf_db = value; 320 321 /* 322 * Ensure that the doorbell is updated before reading the event 323 * index from memory. The controller needs to provide similar 324 * ordering to ensure the envent index is updated before reading 325 * the doorbell. 326 */ 327 mb(); 328 329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330 return false; 331 } 332 333 return true; 334 } 335 336 /* 337 * Will slightly overestimate the number of pages needed. This is OK 338 * as it only leads to a small amount of wasted memory for the lifetime of 339 * the I/O. 340 */ 341 static int nvme_npages(unsigned size, struct nvme_dev *dev) 342 { 343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 344 dev->ctrl.page_size); 345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 346 } 347 348 /* 349 * Calculates the number of pages needed for the SGL segments. For example a 4k 350 * page can accommodate 256 SGL descriptors. 351 */ 352 static int nvme_pci_npages_sgl(unsigned int num_seg) 353 { 354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355 } 356 357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358 unsigned int size, unsigned int nseg, bool use_sgl) 359 { 360 size_t alloc_size; 361 362 if (use_sgl) 363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364 else 365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366 367 return alloc_size + sizeof(struct scatterlist) * nseg; 368 } 369 370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 371 unsigned int hctx_idx) 372 { 373 struct nvme_dev *dev = data; 374 struct nvme_queue *nvmeq = &dev->queues[0]; 375 376 WARN_ON(hctx_idx != 0); 377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 378 WARN_ON(nvmeq->tags); 379 380 hctx->driver_data = nvmeq; 381 nvmeq->tags = &dev->admin_tagset.tags[0]; 382 return 0; 383 } 384 385 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 386 { 387 struct nvme_queue *nvmeq = hctx->driver_data; 388 389 nvmeq->tags = NULL; 390 } 391 392 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 393 unsigned int hctx_idx) 394 { 395 struct nvme_dev *dev = data; 396 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 397 398 if (!nvmeq->tags) 399 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 400 401 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 402 hctx->driver_data = nvmeq; 403 return 0; 404 } 405 406 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 407 unsigned int hctx_idx, unsigned int numa_node) 408 { 409 struct nvme_dev *dev = set->driver_data; 410 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 411 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 412 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 413 414 BUG_ON(!nvmeq); 415 iod->nvmeq = nvmeq; 416 417 nvme_req(req)->ctrl = &dev->ctrl; 418 return 0; 419 } 420 421 static int queue_irq_offset(struct nvme_dev *dev) 422 { 423 /* if we have more than 1 vec, admin queue offsets us by 1 */ 424 if (dev->num_vecs > 1) 425 return 1; 426 427 return 0; 428 } 429 430 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 431 { 432 struct nvme_dev *dev = set->driver_data; 433 int i, qoff, offset; 434 435 offset = queue_irq_offset(dev); 436 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 437 struct blk_mq_queue_map *map = &set->map[i]; 438 439 map->nr_queues = dev->io_queues[i]; 440 if (!map->nr_queues) { 441 BUG_ON(i == HCTX_TYPE_DEFAULT); 442 continue; 443 } 444 445 /* 446 * The poll queue(s) doesn't have an IRQ (and hence IRQ 447 * affinity), so use the regular blk-mq cpu mapping 448 */ 449 map->queue_offset = qoff; 450 if (i != HCTX_TYPE_POLL && offset) 451 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 452 else 453 blk_mq_map_queues(map); 454 qoff += map->nr_queues; 455 offset += map->nr_queues; 456 } 457 458 return 0; 459 } 460 461 /* 462 * Write sq tail if we are asked to, or if the next command would wrap. 463 */ 464 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 465 { 466 if (!write_sq) { 467 u16 next_tail = nvmeq->sq_tail + 1; 468 469 if (next_tail == nvmeq->q_depth) 470 next_tail = 0; 471 if (next_tail != nvmeq->last_sq_tail) 472 return; 473 } 474 475 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 476 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 477 writel(nvmeq->sq_tail, nvmeq->q_db); 478 nvmeq->last_sq_tail = nvmeq->sq_tail; 479 } 480 481 /** 482 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 483 * @nvmeq: The queue to use 484 * @cmd: The command to send 485 * @write_sq: whether to write to the SQ doorbell 486 */ 487 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 488 bool write_sq) 489 { 490 spin_lock(&nvmeq->sq_lock); 491 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 492 if (++nvmeq->sq_tail == nvmeq->q_depth) 493 nvmeq->sq_tail = 0; 494 nvme_write_sq_db(nvmeq, write_sq); 495 spin_unlock(&nvmeq->sq_lock); 496 } 497 498 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 499 { 500 struct nvme_queue *nvmeq = hctx->driver_data; 501 502 spin_lock(&nvmeq->sq_lock); 503 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 504 nvme_write_sq_db(nvmeq, true); 505 spin_unlock(&nvmeq->sq_lock); 506 } 507 508 static void **nvme_pci_iod_list(struct request *req) 509 { 510 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 511 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 512 } 513 514 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 515 { 516 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 517 int nseg = blk_rq_nr_phys_segments(req); 518 unsigned int avg_seg_size; 519 520 if (nseg == 0) 521 return false; 522 523 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 524 525 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 526 return false; 527 if (!iod->nvmeq->qid) 528 return false; 529 if (!sgl_threshold || avg_seg_size < sgl_threshold) 530 return false; 531 return true; 532 } 533 534 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 535 { 536 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 537 enum dma_data_direction dma_dir = rq_data_dir(req) ? 538 DMA_TO_DEVICE : DMA_FROM_DEVICE; 539 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 540 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 541 int i; 542 543 if (iod->dma_len) { 544 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); 545 return; 546 } 547 548 WARN_ON_ONCE(!iod->nents); 549 550 if (is_pci_p2pdma_page(sg_page(iod->sg))) 551 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 552 rq_dma_dir(req)); 553 else 554 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 555 556 557 if (iod->npages == 0) 558 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 559 dma_addr); 560 561 for (i = 0; i < iod->npages; i++) { 562 void *addr = nvme_pci_iod_list(req)[i]; 563 564 if (iod->use_sgl) { 565 struct nvme_sgl_desc *sg_list = addr; 566 567 next_dma_addr = 568 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 569 } else { 570 __le64 *prp_list = addr; 571 572 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 573 } 574 575 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 576 dma_addr = next_dma_addr; 577 } 578 579 mempool_free(iod->sg, dev->iod_mempool); 580 } 581 582 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 583 { 584 int i; 585 struct scatterlist *sg; 586 587 for_each_sg(sgl, sg, nents, i) { 588 dma_addr_t phys = sg_phys(sg); 589 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 590 "dma_address:%pad dma_length:%d\n", 591 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 592 sg_dma_len(sg)); 593 } 594 } 595 596 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 597 struct request *req, struct nvme_rw_command *cmnd) 598 { 599 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 600 struct dma_pool *pool; 601 int length = blk_rq_payload_bytes(req); 602 struct scatterlist *sg = iod->sg; 603 int dma_len = sg_dma_len(sg); 604 u64 dma_addr = sg_dma_address(sg); 605 u32 page_size = dev->ctrl.page_size; 606 int offset = dma_addr & (page_size - 1); 607 __le64 *prp_list; 608 void **list = nvme_pci_iod_list(req); 609 dma_addr_t prp_dma; 610 int nprps, i; 611 612 length -= (page_size - offset); 613 if (length <= 0) { 614 iod->first_dma = 0; 615 goto done; 616 } 617 618 dma_len -= (page_size - offset); 619 if (dma_len) { 620 dma_addr += (page_size - offset); 621 } else { 622 sg = sg_next(sg); 623 dma_addr = sg_dma_address(sg); 624 dma_len = sg_dma_len(sg); 625 } 626 627 if (length <= page_size) { 628 iod->first_dma = dma_addr; 629 goto done; 630 } 631 632 nprps = DIV_ROUND_UP(length, page_size); 633 if (nprps <= (256 / 8)) { 634 pool = dev->prp_small_pool; 635 iod->npages = 0; 636 } else { 637 pool = dev->prp_page_pool; 638 iod->npages = 1; 639 } 640 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 642 if (!prp_list) { 643 iod->first_dma = dma_addr; 644 iod->npages = -1; 645 return BLK_STS_RESOURCE; 646 } 647 list[0] = prp_list; 648 iod->first_dma = prp_dma; 649 i = 0; 650 for (;;) { 651 if (i == page_size >> 3) { 652 __le64 *old_prp_list = prp_list; 653 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 654 if (!prp_list) 655 return BLK_STS_RESOURCE; 656 list[iod->npages++] = prp_list; 657 prp_list[0] = old_prp_list[i - 1]; 658 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 659 i = 1; 660 } 661 prp_list[i++] = cpu_to_le64(dma_addr); 662 dma_len -= page_size; 663 dma_addr += page_size; 664 length -= page_size; 665 if (length <= 0) 666 break; 667 if (dma_len > 0) 668 continue; 669 if (unlikely(dma_len < 0)) 670 goto bad_sgl; 671 sg = sg_next(sg); 672 dma_addr = sg_dma_address(sg); 673 dma_len = sg_dma_len(sg); 674 } 675 676 done: 677 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 678 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 679 680 return BLK_STS_OK; 681 682 bad_sgl: 683 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 684 "Invalid SGL for payload:%d nents:%d\n", 685 blk_rq_payload_bytes(req), iod->nents); 686 return BLK_STS_IOERR; 687 } 688 689 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 690 struct scatterlist *sg) 691 { 692 sge->addr = cpu_to_le64(sg_dma_address(sg)); 693 sge->length = cpu_to_le32(sg_dma_len(sg)); 694 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 695 } 696 697 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 698 dma_addr_t dma_addr, int entries) 699 { 700 sge->addr = cpu_to_le64(dma_addr); 701 if (entries < SGES_PER_PAGE) { 702 sge->length = cpu_to_le32(entries * sizeof(*sge)); 703 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 704 } else { 705 sge->length = cpu_to_le32(PAGE_SIZE); 706 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 707 } 708 } 709 710 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 711 struct request *req, struct nvme_rw_command *cmd, int entries) 712 { 713 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 714 struct dma_pool *pool; 715 struct nvme_sgl_desc *sg_list; 716 struct scatterlist *sg = iod->sg; 717 dma_addr_t sgl_dma; 718 int i = 0; 719 720 /* setting the transfer type as SGL */ 721 cmd->flags = NVME_CMD_SGL_METABUF; 722 723 if (entries == 1) { 724 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 725 return BLK_STS_OK; 726 } 727 728 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 729 pool = dev->prp_small_pool; 730 iod->npages = 0; 731 } else { 732 pool = dev->prp_page_pool; 733 iod->npages = 1; 734 } 735 736 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 737 if (!sg_list) { 738 iod->npages = -1; 739 return BLK_STS_RESOURCE; 740 } 741 742 nvme_pci_iod_list(req)[0] = sg_list; 743 iod->first_dma = sgl_dma; 744 745 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 746 747 do { 748 if (i == SGES_PER_PAGE) { 749 struct nvme_sgl_desc *old_sg_desc = sg_list; 750 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 751 752 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 753 if (!sg_list) 754 return BLK_STS_RESOURCE; 755 756 i = 0; 757 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 758 sg_list[i++] = *link; 759 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 760 } 761 762 nvme_pci_sgl_set_data(&sg_list[i++], sg); 763 sg = sg_next(sg); 764 } while (--entries > 0); 765 766 return BLK_STS_OK; 767 } 768 769 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 770 struct request *req, struct nvme_rw_command *cmnd, 771 struct bio_vec *bv) 772 { 773 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 774 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 775 776 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 777 if (dma_mapping_error(dev->dev, iod->first_dma)) 778 return BLK_STS_RESOURCE; 779 iod->dma_len = bv->bv_len; 780 781 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 782 if (bv->bv_len > first_prp_len) 783 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 784 return 0; 785 } 786 787 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 788 struct request *req, struct nvme_rw_command *cmnd, 789 struct bio_vec *bv) 790 { 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 792 793 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 794 if (dma_mapping_error(dev->dev, iod->first_dma)) 795 return BLK_STS_RESOURCE; 796 iod->dma_len = bv->bv_len; 797 798 cmnd->flags = NVME_CMD_SGL_METABUF; 799 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 800 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 801 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 802 return 0; 803 } 804 805 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 806 struct nvme_command *cmnd) 807 { 808 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 809 blk_status_t ret = BLK_STS_RESOURCE; 810 int nr_mapped; 811 812 if (blk_rq_nr_phys_segments(req) == 1) { 813 struct bio_vec bv = req_bvec(req); 814 815 if (!is_pci_p2pdma_page(bv.bv_page)) { 816 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 817 return nvme_setup_prp_simple(dev, req, 818 &cmnd->rw, &bv); 819 820 if (iod->nvmeq->qid && 821 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 822 return nvme_setup_sgl_simple(dev, req, 823 &cmnd->rw, &bv); 824 } 825 } 826 827 iod->dma_len = 0; 828 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 829 if (!iod->sg) 830 return BLK_STS_RESOURCE; 831 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 832 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 833 if (!iod->nents) 834 goto out; 835 836 if (is_pci_p2pdma_page(sg_page(iod->sg))) 837 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 838 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 839 else 840 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 841 rq_dma_dir(req), DMA_ATTR_NO_WARN); 842 if (!nr_mapped) 843 goto out; 844 845 iod->use_sgl = nvme_pci_use_sgls(dev, req); 846 if (iod->use_sgl) 847 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 848 else 849 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 850 out: 851 if (ret != BLK_STS_OK) 852 nvme_unmap_data(dev, req); 853 return ret; 854 } 855 856 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 857 struct nvme_command *cmnd) 858 { 859 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 860 861 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 862 rq_dma_dir(req), 0); 863 if (dma_mapping_error(dev->dev, iod->meta_dma)) 864 return BLK_STS_IOERR; 865 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 866 return 0; 867 } 868 869 /* 870 * NOTE: ns is NULL when called on the admin queue. 871 */ 872 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 873 const struct blk_mq_queue_data *bd) 874 { 875 struct nvme_ns *ns = hctx->queue->queuedata; 876 struct nvme_queue *nvmeq = hctx->driver_data; 877 struct nvme_dev *dev = nvmeq->dev; 878 struct request *req = bd->rq; 879 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 880 struct nvme_command cmnd; 881 blk_status_t ret; 882 883 iod->aborted = 0; 884 iod->npages = -1; 885 iod->nents = 0; 886 887 /* 888 * We should not need to do this, but we're still using this to 889 * ensure we can drain requests on a dying queue. 890 */ 891 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 892 return BLK_STS_IOERR; 893 894 ret = nvme_setup_cmd(ns, req, &cmnd); 895 if (ret) 896 return ret; 897 898 if (blk_rq_nr_phys_segments(req)) { 899 ret = nvme_map_data(dev, req, &cmnd); 900 if (ret) 901 goto out_free_cmd; 902 } 903 904 if (blk_integrity_rq(req)) { 905 ret = nvme_map_metadata(dev, req, &cmnd); 906 if (ret) 907 goto out_unmap_data; 908 } 909 910 blk_mq_start_request(req); 911 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 912 return BLK_STS_OK; 913 out_unmap_data: 914 nvme_unmap_data(dev, req); 915 out_free_cmd: 916 nvme_cleanup_cmd(req); 917 return ret; 918 } 919 920 static void nvme_pci_complete_rq(struct request *req) 921 { 922 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 923 struct nvme_dev *dev = iod->nvmeq->dev; 924 925 nvme_cleanup_cmd(req); 926 if (blk_integrity_rq(req)) 927 dma_unmap_page(dev->dev, iod->meta_dma, 928 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 929 if (blk_rq_nr_phys_segments(req)) 930 nvme_unmap_data(dev, req); 931 nvme_complete_rq(req); 932 } 933 934 /* We read the CQE phase first to check if the rest of the entry is valid */ 935 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 936 { 937 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 938 nvmeq->cq_phase; 939 } 940 941 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 942 { 943 u16 head = nvmeq->cq_head; 944 945 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 946 nvmeq->dbbuf_cq_ei)) 947 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 948 } 949 950 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 951 { 952 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 953 struct request *req; 954 955 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 956 dev_warn(nvmeq->dev->ctrl.device, 957 "invalid id %d completed on queue %d\n", 958 cqe->command_id, le16_to_cpu(cqe->sq_id)); 959 return; 960 } 961 962 /* 963 * AEN requests are special as they don't time out and can 964 * survive any kind of queue freeze and often don't respond to 965 * aborts. We don't even bother to allocate a struct request 966 * for them but rather special case them here. 967 */ 968 if (unlikely(nvmeq->qid == 0 && 969 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 970 nvme_complete_async_event(&nvmeq->dev->ctrl, 971 cqe->status, &cqe->result); 972 return; 973 } 974 975 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 976 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 977 nvme_end_request(req, cqe->status, cqe->result); 978 } 979 980 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 981 { 982 while (start != end) { 983 nvme_handle_cqe(nvmeq, start); 984 if (++start == nvmeq->q_depth) 985 start = 0; 986 } 987 } 988 989 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 990 { 991 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 992 nvmeq->cq_head = 0; 993 nvmeq->cq_phase = !nvmeq->cq_phase; 994 } else { 995 nvmeq->cq_head++; 996 } 997 } 998 999 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 1000 u16 *end, unsigned int tag) 1001 { 1002 int found = 0; 1003 1004 *start = nvmeq->cq_head; 1005 while (nvme_cqe_pending(nvmeq)) { 1006 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1007 found++; 1008 nvme_update_cq_head(nvmeq); 1009 } 1010 *end = nvmeq->cq_head; 1011 1012 if (*start != *end) 1013 nvme_ring_cq_doorbell(nvmeq); 1014 return found; 1015 } 1016 1017 static irqreturn_t nvme_irq(int irq, void *data) 1018 { 1019 struct nvme_queue *nvmeq = data; 1020 irqreturn_t ret = IRQ_NONE; 1021 u16 start, end; 1022 1023 /* 1024 * The rmb/wmb pair ensures we see all updates from a previous run of 1025 * the irq handler, even if that was on another CPU. 1026 */ 1027 rmb(); 1028 if (nvmeq->cq_head != nvmeq->last_cq_head) 1029 ret = IRQ_HANDLED; 1030 nvme_process_cq(nvmeq, &start, &end, -1); 1031 nvmeq->last_cq_head = nvmeq->cq_head; 1032 wmb(); 1033 1034 if (start != end) { 1035 nvme_complete_cqes(nvmeq, start, end); 1036 return IRQ_HANDLED; 1037 } 1038 1039 return ret; 1040 } 1041 1042 static irqreturn_t nvme_irq_check(int irq, void *data) 1043 { 1044 struct nvme_queue *nvmeq = data; 1045 if (nvme_cqe_pending(nvmeq)) 1046 return IRQ_WAKE_THREAD; 1047 return IRQ_NONE; 1048 } 1049 1050 /* 1051 * Poll for completions any queue, including those not dedicated to polling. 1052 * Can be called from any context. 1053 */ 1054 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1055 { 1056 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1057 u16 start, end; 1058 int found; 1059 1060 /* 1061 * For a poll queue we need to protect against the polling thread 1062 * using the CQ lock. For normal interrupt driven threads we have 1063 * to disable the interrupt to avoid racing with it. 1064 */ 1065 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1066 spin_lock(&nvmeq->cq_poll_lock); 1067 found = nvme_process_cq(nvmeq, &start, &end, tag); 1068 spin_unlock(&nvmeq->cq_poll_lock); 1069 } else { 1070 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1071 found = nvme_process_cq(nvmeq, &start, &end, tag); 1072 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1073 } 1074 1075 nvme_complete_cqes(nvmeq, start, end); 1076 return found; 1077 } 1078 1079 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1080 { 1081 struct nvme_queue *nvmeq = hctx->driver_data; 1082 u16 start, end; 1083 bool found; 1084 1085 if (!nvme_cqe_pending(nvmeq)) 1086 return 0; 1087 1088 spin_lock(&nvmeq->cq_poll_lock); 1089 found = nvme_process_cq(nvmeq, &start, &end, -1); 1090 spin_unlock(&nvmeq->cq_poll_lock); 1091 1092 nvme_complete_cqes(nvmeq, start, end); 1093 return found; 1094 } 1095 1096 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1097 { 1098 struct nvme_dev *dev = to_nvme_dev(ctrl); 1099 struct nvme_queue *nvmeq = &dev->queues[0]; 1100 struct nvme_command c; 1101 1102 memset(&c, 0, sizeof(c)); 1103 c.common.opcode = nvme_admin_async_event; 1104 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1105 nvme_submit_cmd(nvmeq, &c, true); 1106 } 1107 1108 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1109 { 1110 struct nvme_command c; 1111 1112 memset(&c, 0, sizeof(c)); 1113 c.delete_queue.opcode = opcode; 1114 c.delete_queue.qid = cpu_to_le16(id); 1115 1116 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1117 } 1118 1119 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1120 struct nvme_queue *nvmeq, s16 vector) 1121 { 1122 struct nvme_command c; 1123 int flags = NVME_QUEUE_PHYS_CONTIG; 1124 1125 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1126 flags |= NVME_CQ_IRQ_ENABLED; 1127 1128 /* 1129 * Note: we (ab)use the fact that the prp fields survive if no data 1130 * is attached to the request. 1131 */ 1132 memset(&c, 0, sizeof(c)); 1133 c.create_cq.opcode = nvme_admin_create_cq; 1134 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1135 c.create_cq.cqid = cpu_to_le16(qid); 1136 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1137 c.create_cq.cq_flags = cpu_to_le16(flags); 1138 c.create_cq.irq_vector = cpu_to_le16(vector); 1139 1140 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1141 } 1142 1143 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1144 struct nvme_queue *nvmeq) 1145 { 1146 struct nvme_ctrl *ctrl = &dev->ctrl; 1147 struct nvme_command c; 1148 int flags = NVME_QUEUE_PHYS_CONTIG; 1149 1150 /* 1151 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1152 * set. Since URGENT priority is zeroes, it makes all queues 1153 * URGENT. 1154 */ 1155 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1156 flags |= NVME_SQ_PRIO_MEDIUM; 1157 1158 /* 1159 * Note: we (ab)use the fact that the prp fields survive if no data 1160 * is attached to the request. 1161 */ 1162 memset(&c, 0, sizeof(c)); 1163 c.create_sq.opcode = nvme_admin_create_sq; 1164 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1165 c.create_sq.sqid = cpu_to_le16(qid); 1166 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1167 c.create_sq.sq_flags = cpu_to_le16(flags); 1168 c.create_sq.cqid = cpu_to_le16(qid); 1169 1170 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1171 } 1172 1173 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1174 { 1175 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1176 } 1177 1178 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1179 { 1180 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1181 } 1182 1183 static void abort_endio(struct request *req, blk_status_t error) 1184 { 1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1186 struct nvme_queue *nvmeq = iod->nvmeq; 1187 1188 dev_warn(nvmeq->dev->ctrl.device, 1189 "Abort status: 0x%x", nvme_req(req)->status); 1190 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1191 blk_mq_free_request(req); 1192 } 1193 1194 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1195 { 1196 1197 /* If true, indicates loss of adapter communication, possibly by a 1198 * NVMe Subsystem reset. 1199 */ 1200 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1201 1202 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1203 switch (dev->ctrl.state) { 1204 case NVME_CTRL_RESETTING: 1205 case NVME_CTRL_CONNECTING: 1206 return false; 1207 default: 1208 break; 1209 } 1210 1211 /* We shouldn't reset unless the controller is on fatal error state 1212 * _or_ if we lost the communication with it. 1213 */ 1214 if (!(csts & NVME_CSTS_CFS) && !nssro) 1215 return false; 1216 1217 return true; 1218 } 1219 1220 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1221 { 1222 /* Read a config register to help see what died. */ 1223 u16 pci_status; 1224 int result; 1225 1226 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1227 &pci_status); 1228 if (result == PCIBIOS_SUCCESSFUL) 1229 dev_warn(dev->ctrl.device, 1230 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1231 csts, pci_status); 1232 else 1233 dev_warn(dev->ctrl.device, 1234 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1235 csts, result); 1236 } 1237 1238 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1239 { 1240 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1241 struct nvme_queue *nvmeq = iod->nvmeq; 1242 struct nvme_dev *dev = nvmeq->dev; 1243 struct request *abort_req; 1244 struct nvme_command cmd; 1245 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1246 1247 /* If PCI error recovery process is happening, we cannot reset or 1248 * the recovery mechanism will surely fail. 1249 */ 1250 mb(); 1251 if (pci_channel_offline(to_pci_dev(dev->dev))) 1252 return BLK_EH_RESET_TIMER; 1253 1254 /* 1255 * Reset immediately if the controller is failed 1256 */ 1257 if (nvme_should_reset(dev, csts)) { 1258 nvme_warn_reset(dev, csts); 1259 nvme_dev_disable(dev, false); 1260 nvme_reset_ctrl(&dev->ctrl); 1261 return BLK_EH_DONE; 1262 } 1263 1264 /* 1265 * Did we miss an interrupt? 1266 */ 1267 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1268 dev_warn(dev->ctrl.device, 1269 "I/O %d QID %d timeout, completion polled\n", 1270 req->tag, nvmeq->qid); 1271 return BLK_EH_DONE; 1272 } 1273 1274 /* 1275 * Shutdown immediately if controller times out while starting. The 1276 * reset work will see the pci device disabled when it gets the forced 1277 * cancellation error. All outstanding requests are completed on 1278 * shutdown, so we return BLK_EH_DONE. 1279 */ 1280 switch (dev->ctrl.state) { 1281 case NVME_CTRL_CONNECTING: 1282 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1283 /* fall through */ 1284 case NVME_CTRL_DELETING: 1285 dev_warn_ratelimited(dev->ctrl.device, 1286 "I/O %d QID %d timeout, disable controller\n", 1287 req->tag, nvmeq->qid); 1288 nvme_dev_disable(dev, true); 1289 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1290 return BLK_EH_DONE; 1291 case NVME_CTRL_RESETTING: 1292 return BLK_EH_RESET_TIMER; 1293 default: 1294 break; 1295 } 1296 1297 /* 1298 * Shutdown the controller immediately and schedule a reset if the 1299 * command was already aborted once before and still hasn't been 1300 * returned to the driver, or if this is the admin queue. 1301 */ 1302 if (!nvmeq->qid || iod->aborted) { 1303 dev_warn(dev->ctrl.device, 1304 "I/O %d QID %d timeout, reset controller\n", 1305 req->tag, nvmeq->qid); 1306 nvme_dev_disable(dev, false); 1307 nvme_reset_ctrl(&dev->ctrl); 1308 1309 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1310 return BLK_EH_DONE; 1311 } 1312 1313 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1314 atomic_inc(&dev->ctrl.abort_limit); 1315 return BLK_EH_RESET_TIMER; 1316 } 1317 iod->aborted = 1; 1318 1319 memset(&cmd, 0, sizeof(cmd)); 1320 cmd.abort.opcode = nvme_admin_abort_cmd; 1321 cmd.abort.cid = req->tag; 1322 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1323 1324 dev_warn(nvmeq->dev->ctrl.device, 1325 "I/O %d QID %d timeout, aborting\n", 1326 req->tag, nvmeq->qid); 1327 1328 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1329 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1330 if (IS_ERR(abort_req)) { 1331 atomic_inc(&dev->ctrl.abort_limit); 1332 return BLK_EH_RESET_TIMER; 1333 } 1334 1335 abort_req->timeout = ADMIN_TIMEOUT; 1336 abort_req->end_io_data = NULL; 1337 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1338 1339 /* 1340 * The aborted req will be completed on receiving the abort req. 1341 * We enable the timer again. If hit twice, it'll cause a device reset, 1342 * as the device then is in a faulty state. 1343 */ 1344 return BLK_EH_RESET_TIMER; 1345 } 1346 1347 static void nvme_free_queue(struct nvme_queue *nvmeq) 1348 { 1349 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 1350 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1351 if (!nvmeq->sq_cmds) 1352 return; 1353 1354 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1355 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1356 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 1357 } else { 1358 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 1359 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1360 } 1361 } 1362 1363 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1364 { 1365 int i; 1366 1367 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1368 dev->ctrl.queue_count--; 1369 nvme_free_queue(&dev->queues[i]); 1370 } 1371 } 1372 1373 /** 1374 * nvme_suspend_queue - put queue into suspended state 1375 * @nvmeq: queue to suspend 1376 */ 1377 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1378 { 1379 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1380 return 1; 1381 1382 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1383 mb(); 1384 1385 nvmeq->dev->online_queues--; 1386 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1387 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1388 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1389 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1390 return 0; 1391 } 1392 1393 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1394 { 1395 int i; 1396 1397 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1398 nvme_suspend_queue(&dev->queues[i]); 1399 } 1400 1401 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1402 { 1403 struct nvme_queue *nvmeq = &dev->queues[0]; 1404 1405 if (shutdown) 1406 nvme_shutdown_ctrl(&dev->ctrl); 1407 else 1408 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1409 1410 nvme_poll_irqdisable(nvmeq, -1); 1411 } 1412 1413 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1414 int entry_size) 1415 { 1416 int q_depth = dev->q_depth; 1417 unsigned q_size_aligned = roundup(q_depth * entry_size, 1418 dev->ctrl.page_size); 1419 1420 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1421 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1422 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1423 q_depth = div_u64(mem_per_q, entry_size); 1424 1425 /* 1426 * Ensure the reduced q_depth is above some threshold where it 1427 * would be better to map queues in system memory with the 1428 * original depth 1429 */ 1430 if (q_depth < 64) 1431 return -ENOMEM; 1432 } 1433 1434 return q_depth; 1435 } 1436 1437 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1438 int qid, int depth) 1439 { 1440 struct pci_dev *pdev = to_pci_dev(dev->dev); 1441 1442 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1443 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 1444 if (nvmeq->sq_cmds) { 1445 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1446 nvmeq->sq_cmds); 1447 if (nvmeq->sq_dma_addr) { 1448 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1449 return 0; 1450 } 1451 1452 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(depth)); 1453 } 1454 } 1455 1456 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1457 &nvmeq->sq_dma_addr, GFP_KERNEL); 1458 if (!nvmeq->sq_cmds) 1459 return -ENOMEM; 1460 return 0; 1461 } 1462 1463 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1464 { 1465 struct nvme_queue *nvmeq = &dev->queues[qid]; 1466 1467 if (dev->ctrl.queue_count > qid) 1468 return 0; 1469 1470 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 1471 &nvmeq->cq_dma_addr, GFP_KERNEL); 1472 if (!nvmeq->cqes) 1473 goto free_nvmeq; 1474 1475 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1476 goto free_cqdma; 1477 1478 nvmeq->dev = dev; 1479 spin_lock_init(&nvmeq->sq_lock); 1480 spin_lock_init(&nvmeq->cq_poll_lock); 1481 nvmeq->cq_head = 0; 1482 nvmeq->cq_phase = 1; 1483 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1484 nvmeq->q_depth = depth; 1485 nvmeq->qid = qid; 1486 dev->ctrl.queue_count++; 1487 1488 return 0; 1489 1490 free_cqdma: 1491 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1492 nvmeq->cq_dma_addr); 1493 free_nvmeq: 1494 return -ENOMEM; 1495 } 1496 1497 static int queue_request_irq(struct nvme_queue *nvmeq) 1498 { 1499 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1500 int nr = nvmeq->dev->ctrl.instance; 1501 1502 if (use_threaded_interrupts) { 1503 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1504 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1505 } else { 1506 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1507 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1508 } 1509 } 1510 1511 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1512 { 1513 struct nvme_dev *dev = nvmeq->dev; 1514 1515 nvmeq->sq_tail = 0; 1516 nvmeq->last_sq_tail = 0; 1517 nvmeq->cq_head = 0; 1518 nvmeq->cq_phase = 1; 1519 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1520 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1521 nvme_dbbuf_init(dev, nvmeq, qid); 1522 dev->online_queues++; 1523 wmb(); /* ensure the first interrupt sees the initialization */ 1524 } 1525 1526 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1527 { 1528 struct nvme_dev *dev = nvmeq->dev; 1529 int result; 1530 u16 vector = 0; 1531 1532 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1533 1534 /* 1535 * A queue's vector matches the queue identifier unless the controller 1536 * has only one vector available. 1537 */ 1538 if (!polled) 1539 vector = dev->num_vecs == 1 ? 0 : qid; 1540 else 1541 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1542 1543 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1544 if (result) 1545 return result; 1546 1547 result = adapter_alloc_sq(dev, qid, nvmeq); 1548 if (result < 0) 1549 return result; 1550 else if (result) 1551 goto release_cq; 1552 1553 nvmeq->cq_vector = vector; 1554 nvme_init_queue(nvmeq, qid); 1555 1556 if (!polled) { 1557 nvmeq->cq_vector = vector; 1558 result = queue_request_irq(nvmeq); 1559 if (result < 0) 1560 goto release_sq; 1561 } 1562 1563 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1564 return result; 1565 1566 release_sq: 1567 dev->online_queues--; 1568 adapter_delete_sq(dev, qid); 1569 release_cq: 1570 adapter_delete_cq(dev, qid); 1571 return result; 1572 } 1573 1574 static const struct blk_mq_ops nvme_mq_admin_ops = { 1575 .queue_rq = nvme_queue_rq, 1576 .complete = nvme_pci_complete_rq, 1577 .init_hctx = nvme_admin_init_hctx, 1578 .exit_hctx = nvme_admin_exit_hctx, 1579 .init_request = nvme_init_request, 1580 .timeout = nvme_timeout, 1581 }; 1582 1583 static const struct blk_mq_ops nvme_mq_ops = { 1584 .queue_rq = nvme_queue_rq, 1585 .complete = nvme_pci_complete_rq, 1586 .commit_rqs = nvme_commit_rqs, 1587 .init_hctx = nvme_init_hctx, 1588 .init_request = nvme_init_request, 1589 .map_queues = nvme_pci_map_queues, 1590 .timeout = nvme_timeout, 1591 .poll = nvme_poll, 1592 }; 1593 1594 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1595 { 1596 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1597 /* 1598 * If the controller was reset during removal, it's possible 1599 * user requests may be waiting on a stopped queue. Start the 1600 * queue to flush these to completion. 1601 */ 1602 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1603 blk_cleanup_queue(dev->ctrl.admin_q); 1604 blk_mq_free_tag_set(&dev->admin_tagset); 1605 } 1606 } 1607 1608 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1609 { 1610 if (!dev->ctrl.admin_q) { 1611 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1612 dev->admin_tagset.nr_hw_queues = 1; 1613 1614 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1615 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1616 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1617 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1618 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1619 dev->admin_tagset.driver_data = dev; 1620 1621 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1622 return -ENOMEM; 1623 dev->ctrl.admin_tagset = &dev->admin_tagset; 1624 1625 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1626 if (IS_ERR(dev->ctrl.admin_q)) { 1627 blk_mq_free_tag_set(&dev->admin_tagset); 1628 return -ENOMEM; 1629 } 1630 if (!blk_get_queue(dev->ctrl.admin_q)) { 1631 nvme_dev_remove_admin(dev); 1632 dev->ctrl.admin_q = NULL; 1633 return -ENODEV; 1634 } 1635 } else 1636 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1637 1638 return 0; 1639 } 1640 1641 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1642 { 1643 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1644 } 1645 1646 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1647 { 1648 struct pci_dev *pdev = to_pci_dev(dev->dev); 1649 1650 if (size <= dev->bar_mapped_size) 1651 return 0; 1652 if (size > pci_resource_len(pdev, 0)) 1653 return -ENOMEM; 1654 if (dev->bar) 1655 iounmap(dev->bar); 1656 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1657 if (!dev->bar) { 1658 dev->bar_mapped_size = 0; 1659 return -ENOMEM; 1660 } 1661 dev->bar_mapped_size = size; 1662 dev->dbs = dev->bar + NVME_REG_DBS; 1663 1664 return 0; 1665 } 1666 1667 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1668 { 1669 int result; 1670 u32 aqa; 1671 struct nvme_queue *nvmeq; 1672 1673 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1674 if (result < 0) 1675 return result; 1676 1677 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1678 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1679 1680 if (dev->subsystem && 1681 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1682 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1683 1684 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1685 if (result < 0) 1686 return result; 1687 1688 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1689 if (result) 1690 return result; 1691 1692 nvmeq = &dev->queues[0]; 1693 aqa = nvmeq->q_depth - 1; 1694 aqa |= aqa << 16; 1695 1696 writel(aqa, dev->bar + NVME_REG_AQA); 1697 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1698 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1699 1700 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 1701 if (result) 1702 return result; 1703 1704 nvmeq->cq_vector = 0; 1705 nvme_init_queue(nvmeq, 0); 1706 result = queue_request_irq(nvmeq); 1707 if (result) { 1708 dev->online_queues--; 1709 return result; 1710 } 1711 1712 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1713 return result; 1714 } 1715 1716 static int nvme_create_io_queues(struct nvme_dev *dev) 1717 { 1718 unsigned i, max, rw_queues; 1719 int ret = 0; 1720 1721 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1722 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1723 ret = -ENOMEM; 1724 break; 1725 } 1726 } 1727 1728 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1729 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1730 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1731 dev->io_queues[HCTX_TYPE_READ]; 1732 } else { 1733 rw_queues = max; 1734 } 1735 1736 for (i = dev->online_queues; i <= max; i++) { 1737 bool polled = i > rw_queues; 1738 1739 ret = nvme_create_queue(&dev->queues[i], i, polled); 1740 if (ret) 1741 break; 1742 } 1743 1744 /* 1745 * Ignore failing Create SQ/CQ commands, we can continue with less 1746 * than the desired amount of queues, and even a controller without 1747 * I/O queues can still be used to issue admin commands. This might 1748 * be useful to upgrade a buggy firmware for example. 1749 */ 1750 return ret >= 0 ? 0 : ret; 1751 } 1752 1753 static ssize_t nvme_cmb_show(struct device *dev, 1754 struct device_attribute *attr, 1755 char *buf) 1756 { 1757 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1758 1759 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1760 ndev->cmbloc, ndev->cmbsz); 1761 } 1762 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1763 1764 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1765 { 1766 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1767 1768 return 1ULL << (12 + 4 * szu); 1769 } 1770 1771 static u32 nvme_cmb_size(struct nvme_dev *dev) 1772 { 1773 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1774 } 1775 1776 static void nvme_map_cmb(struct nvme_dev *dev) 1777 { 1778 u64 size, offset; 1779 resource_size_t bar_size; 1780 struct pci_dev *pdev = to_pci_dev(dev->dev); 1781 int bar; 1782 1783 if (dev->cmb_size) 1784 return; 1785 1786 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1787 if (!dev->cmbsz) 1788 return; 1789 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1790 1791 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1792 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1793 bar = NVME_CMB_BIR(dev->cmbloc); 1794 bar_size = pci_resource_len(pdev, bar); 1795 1796 if (offset > bar_size) 1797 return; 1798 1799 /* 1800 * Controllers may support a CMB size larger than their BAR, 1801 * for example, due to being behind a bridge. Reduce the CMB to 1802 * the reported size of the BAR 1803 */ 1804 if (size > bar_size - offset) 1805 size = bar_size - offset; 1806 1807 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1808 dev_warn(dev->ctrl.device, 1809 "failed to register the CMB\n"); 1810 return; 1811 } 1812 1813 dev->cmb_size = size; 1814 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1815 1816 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1817 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1818 pci_p2pmem_publish(pdev, true); 1819 1820 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1821 &dev_attr_cmb.attr, NULL)) 1822 dev_warn(dev->ctrl.device, 1823 "failed to add sysfs attribute for CMB\n"); 1824 } 1825 1826 static inline void nvme_release_cmb(struct nvme_dev *dev) 1827 { 1828 if (dev->cmb_size) { 1829 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1830 &dev_attr_cmb.attr, NULL); 1831 dev->cmb_size = 0; 1832 } 1833 } 1834 1835 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1836 { 1837 u64 dma_addr = dev->host_mem_descs_dma; 1838 struct nvme_command c; 1839 int ret; 1840 1841 memset(&c, 0, sizeof(c)); 1842 c.features.opcode = nvme_admin_set_features; 1843 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1844 c.features.dword11 = cpu_to_le32(bits); 1845 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1846 ilog2(dev->ctrl.page_size)); 1847 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1848 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1849 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1850 1851 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1852 if (ret) { 1853 dev_warn(dev->ctrl.device, 1854 "failed to set host mem (err %d, flags %#x).\n", 1855 ret, bits); 1856 } 1857 return ret; 1858 } 1859 1860 static void nvme_free_host_mem(struct nvme_dev *dev) 1861 { 1862 int i; 1863 1864 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1865 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1866 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1867 1868 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1869 le64_to_cpu(desc->addr), 1870 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1871 } 1872 1873 kfree(dev->host_mem_desc_bufs); 1874 dev->host_mem_desc_bufs = NULL; 1875 dma_free_coherent(dev->dev, 1876 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1877 dev->host_mem_descs, dev->host_mem_descs_dma); 1878 dev->host_mem_descs = NULL; 1879 dev->nr_host_mem_descs = 0; 1880 } 1881 1882 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1883 u32 chunk_size) 1884 { 1885 struct nvme_host_mem_buf_desc *descs; 1886 u32 max_entries, len; 1887 dma_addr_t descs_dma; 1888 int i = 0; 1889 void **bufs; 1890 u64 size, tmp; 1891 1892 tmp = (preferred + chunk_size - 1); 1893 do_div(tmp, chunk_size); 1894 max_entries = tmp; 1895 1896 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1897 max_entries = dev->ctrl.hmmaxd; 1898 1899 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1900 &descs_dma, GFP_KERNEL); 1901 if (!descs) 1902 goto out; 1903 1904 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1905 if (!bufs) 1906 goto out_free_descs; 1907 1908 for (size = 0; size < preferred && i < max_entries; size += len) { 1909 dma_addr_t dma_addr; 1910 1911 len = min_t(u64, chunk_size, preferred - size); 1912 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1913 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1914 if (!bufs[i]) 1915 break; 1916 1917 descs[i].addr = cpu_to_le64(dma_addr); 1918 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1919 i++; 1920 } 1921 1922 if (!size) 1923 goto out_free_bufs; 1924 1925 dev->nr_host_mem_descs = i; 1926 dev->host_mem_size = size; 1927 dev->host_mem_descs = descs; 1928 dev->host_mem_descs_dma = descs_dma; 1929 dev->host_mem_desc_bufs = bufs; 1930 return 0; 1931 1932 out_free_bufs: 1933 while (--i >= 0) { 1934 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1935 1936 dma_free_attrs(dev->dev, size, bufs[i], 1937 le64_to_cpu(descs[i].addr), 1938 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1939 } 1940 1941 kfree(bufs); 1942 out_free_descs: 1943 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1944 descs_dma); 1945 out: 1946 dev->host_mem_descs = NULL; 1947 return -ENOMEM; 1948 } 1949 1950 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1951 { 1952 u32 chunk_size; 1953 1954 /* start big and work our way down */ 1955 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1956 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1957 chunk_size /= 2) { 1958 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1959 if (!min || dev->host_mem_size >= min) 1960 return 0; 1961 nvme_free_host_mem(dev); 1962 } 1963 } 1964 1965 return -ENOMEM; 1966 } 1967 1968 static int nvme_setup_host_mem(struct nvme_dev *dev) 1969 { 1970 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1971 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1972 u64 min = (u64)dev->ctrl.hmmin * 4096; 1973 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1974 int ret; 1975 1976 preferred = min(preferred, max); 1977 if (min > max) { 1978 dev_warn(dev->ctrl.device, 1979 "min host memory (%lld MiB) above limit (%d MiB).\n", 1980 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1981 nvme_free_host_mem(dev); 1982 return 0; 1983 } 1984 1985 /* 1986 * If we already have a buffer allocated check if we can reuse it. 1987 */ 1988 if (dev->host_mem_descs) { 1989 if (dev->host_mem_size >= min) 1990 enable_bits |= NVME_HOST_MEM_RETURN; 1991 else 1992 nvme_free_host_mem(dev); 1993 } 1994 1995 if (!dev->host_mem_descs) { 1996 if (nvme_alloc_host_mem(dev, min, preferred)) { 1997 dev_warn(dev->ctrl.device, 1998 "failed to allocate host memory buffer.\n"); 1999 return 0; /* controller must work without HMB */ 2000 } 2001 2002 dev_info(dev->ctrl.device, 2003 "allocated %lld MiB host memory buffer.\n", 2004 dev->host_mem_size >> ilog2(SZ_1M)); 2005 } 2006 2007 ret = nvme_set_host_mem(dev, enable_bits); 2008 if (ret) 2009 nvme_free_host_mem(dev); 2010 return ret; 2011 } 2012 2013 /* 2014 * nirqs is the number of interrupts available for write and read 2015 * queues. The core already reserved an interrupt for the admin queue. 2016 */ 2017 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2018 { 2019 struct nvme_dev *dev = affd->priv; 2020 unsigned int nr_read_queues; 2021 2022 /* 2023 * If there is no interupt available for queues, ensure that 2024 * the default queue is set to 1. The affinity set size is 2025 * also set to one, but the irq core ignores it for this case. 2026 * 2027 * If only one interrupt is available or 'write_queue' == 0, combine 2028 * write and read queues. 2029 * 2030 * If 'write_queues' > 0, ensure it leaves room for at least one read 2031 * queue. 2032 */ 2033 if (!nrirqs) { 2034 nrirqs = 1; 2035 nr_read_queues = 0; 2036 } else if (nrirqs == 1 || !write_queues) { 2037 nr_read_queues = 0; 2038 } else if (write_queues >= nrirqs) { 2039 nr_read_queues = 1; 2040 } else { 2041 nr_read_queues = nrirqs - write_queues; 2042 } 2043 2044 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2045 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2046 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2047 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2048 affd->nr_sets = nr_read_queues ? 2 : 1; 2049 } 2050 2051 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2052 { 2053 struct pci_dev *pdev = to_pci_dev(dev->dev); 2054 struct irq_affinity affd = { 2055 .pre_vectors = 1, 2056 .calc_sets = nvme_calc_irq_sets, 2057 .priv = dev, 2058 }; 2059 unsigned int irq_queues, this_p_queues; 2060 unsigned int nr_cpus = num_possible_cpus(); 2061 2062 /* 2063 * Poll queues don't need interrupts, but we need at least one IO 2064 * queue left over for non-polled IO. 2065 */ 2066 this_p_queues = poll_queues; 2067 if (this_p_queues >= nr_io_queues) { 2068 this_p_queues = nr_io_queues - 1; 2069 irq_queues = 1; 2070 } else { 2071 if (nr_cpus < nr_io_queues - this_p_queues) 2072 irq_queues = nr_cpus + 1; 2073 else 2074 irq_queues = nr_io_queues - this_p_queues + 1; 2075 } 2076 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2077 2078 /* Initialize for the single interrupt case */ 2079 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2080 dev->io_queues[HCTX_TYPE_READ] = 0; 2081 2082 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2083 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2084 } 2085 2086 static void nvme_disable_io_queues(struct nvme_dev *dev) 2087 { 2088 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2089 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2090 } 2091 2092 static int nvme_setup_io_queues(struct nvme_dev *dev) 2093 { 2094 struct nvme_queue *adminq = &dev->queues[0]; 2095 struct pci_dev *pdev = to_pci_dev(dev->dev); 2096 int result, nr_io_queues; 2097 unsigned long size; 2098 2099 nr_io_queues = max_io_queues(); 2100 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2101 if (result < 0) 2102 return result; 2103 2104 if (nr_io_queues == 0) 2105 return 0; 2106 2107 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2108 2109 if (dev->cmb_use_sqes) { 2110 result = nvme_cmb_qdepth(dev, nr_io_queues, 2111 sizeof(struct nvme_command)); 2112 if (result > 0) 2113 dev->q_depth = result; 2114 else 2115 dev->cmb_use_sqes = false; 2116 } 2117 2118 do { 2119 size = db_bar_size(dev, nr_io_queues); 2120 result = nvme_remap_bar(dev, size); 2121 if (!result) 2122 break; 2123 if (!--nr_io_queues) 2124 return -ENOMEM; 2125 } while (1); 2126 adminq->q_db = dev->dbs; 2127 2128 retry: 2129 /* Deregister the admin queue's interrupt */ 2130 pci_free_irq(pdev, 0, adminq); 2131 2132 /* 2133 * If we enable msix early due to not intx, disable it again before 2134 * setting up the full range we need. 2135 */ 2136 pci_free_irq_vectors(pdev); 2137 2138 result = nvme_setup_irqs(dev, nr_io_queues); 2139 if (result <= 0) 2140 return -EIO; 2141 2142 dev->num_vecs = result; 2143 result = max(result - 1, 1); 2144 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2145 2146 /* 2147 * Should investigate if there's a performance win from allocating 2148 * more queues than interrupt vectors; it might allow the submission 2149 * path to scale better, even if the receive path is limited by the 2150 * number of interrupts. 2151 */ 2152 result = queue_request_irq(adminq); 2153 if (result) 2154 return result; 2155 set_bit(NVMEQ_ENABLED, &adminq->flags); 2156 2157 result = nvme_create_io_queues(dev); 2158 if (result || dev->online_queues < 2) 2159 return result; 2160 2161 if (dev->online_queues - 1 < dev->max_qid) { 2162 nr_io_queues = dev->online_queues - 1; 2163 nvme_disable_io_queues(dev); 2164 nvme_suspend_io_queues(dev); 2165 goto retry; 2166 } 2167 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2168 dev->io_queues[HCTX_TYPE_DEFAULT], 2169 dev->io_queues[HCTX_TYPE_READ], 2170 dev->io_queues[HCTX_TYPE_POLL]); 2171 return 0; 2172 } 2173 2174 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2175 { 2176 struct nvme_queue *nvmeq = req->end_io_data; 2177 2178 blk_mq_free_request(req); 2179 complete(&nvmeq->delete_done); 2180 } 2181 2182 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2183 { 2184 struct nvme_queue *nvmeq = req->end_io_data; 2185 2186 if (error) 2187 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2188 2189 nvme_del_queue_end(req, error); 2190 } 2191 2192 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2193 { 2194 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2195 struct request *req; 2196 struct nvme_command cmd; 2197 2198 memset(&cmd, 0, sizeof(cmd)); 2199 cmd.delete_queue.opcode = opcode; 2200 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2201 2202 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2203 if (IS_ERR(req)) 2204 return PTR_ERR(req); 2205 2206 req->timeout = ADMIN_TIMEOUT; 2207 req->end_io_data = nvmeq; 2208 2209 init_completion(&nvmeq->delete_done); 2210 blk_execute_rq_nowait(q, NULL, req, false, 2211 opcode == nvme_admin_delete_cq ? 2212 nvme_del_cq_end : nvme_del_queue_end); 2213 return 0; 2214 } 2215 2216 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2217 { 2218 int nr_queues = dev->online_queues - 1, sent = 0; 2219 unsigned long timeout; 2220 2221 retry: 2222 timeout = ADMIN_TIMEOUT; 2223 while (nr_queues > 0) { 2224 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2225 break; 2226 nr_queues--; 2227 sent++; 2228 } 2229 while (sent) { 2230 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2231 2232 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2233 timeout); 2234 if (timeout == 0) 2235 return false; 2236 2237 /* handle any remaining CQEs */ 2238 if (opcode == nvme_admin_delete_cq && 2239 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2240 nvme_poll_irqdisable(nvmeq, -1); 2241 2242 sent--; 2243 if (nr_queues) 2244 goto retry; 2245 } 2246 return true; 2247 } 2248 2249 /* 2250 * return error value only when tagset allocation failed 2251 */ 2252 static int nvme_dev_add(struct nvme_dev *dev) 2253 { 2254 int ret; 2255 2256 if (!dev->ctrl.tagset) { 2257 dev->tagset.ops = &nvme_mq_ops; 2258 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2259 dev->tagset.nr_maps = 1; /* default */ 2260 if (dev->io_queues[HCTX_TYPE_READ]) 2261 dev->tagset.nr_maps++; 2262 if (dev->io_queues[HCTX_TYPE_POLL]) 2263 dev->tagset.nr_maps++; 2264 dev->tagset.timeout = NVME_IO_TIMEOUT; 2265 dev->tagset.numa_node = dev_to_node(dev->dev); 2266 dev->tagset.queue_depth = 2267 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2268 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2269 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2270 dev->tagset.driver_data = dev; 2271 2272 ret = blk_mq_alloc_tag_set(&dev->tagset); 2273 if (ret) { 2274 dev_warn(dev->ctrl.device, 2275 "IO queues tagset allocation failed %d\n", ret); 2276 return ret; 2277 } 2278 dev->ctrl.tagset = &dev->tagset; 2279 } else { 2280 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2281 2282 /* Free previously allocated queues that are no longer usable */ 2283 nvme_free_queues(dev, dev->online_queues); 2284 } 2285 2286 nvme_dbbuf_set(dev); 2287 return 0; 2288 } 2289 2290 static int nvme_pci_enable(struct nvme_dev *dev) 2291 { 2292 int result = -ENOMEM; 2293 struct pci_dev *pdev = to_pci_dev(dev->dev); 2294 2295 if (pci_enable_device_mem(pdev)) 2296 return result; 2297 2298 pci_set_master(pdev); 2299 2300 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2301 goto disable; 2302 2303 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2304 result = -ENODEV; 2305 goto disable; 2306 } 2307 2308 /* 2309 * Some devices and/or platforms don't advertise or work with INTx 2310 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2311 * adjust this later. 2312 */ 2313 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2314 if (result < 0) 2315 return result; 2316 2317 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2318 2319 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2320 io_queue_depth); 2321 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2322 dev->dbs = dev->bar + 4096; 2323 2324 /* 2325 * Temporary fix for the Apple controller found in the MacBook8,1 and 2326 * some MacBook7,1 to avoid controller resets and data loss. 2327 */ 2328 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2329 dev->q_depth = 2; 2330 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2331 "set queue depth=%u to work around controller resets\n", 2332 dev->q_depth); 2333 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2334 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2335 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2336 dev->q_depth = 64; 2337 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2338 "set queue depth=%u\n", dev->q_depth); 2339 } 2340 2341 nvme_map_cmb(dev); 2342 2343 pci_enable_pcie_error_reporting(pdev); 2344 pci_save_state(pdev); 2345 return 0; 2346 2347 disable: 2348 pci_disable_device(pdev); 2349 return result; 2350 } 2351 2352 static void nvme_dev_unmap(struct nvme_dev *dev) 2353 { 2354 if (dev->bar) 2355 iounmap(dev->bar); 2356 pci_release_mem_regions(to_pci_dev(dev->dev)); 2357 } 2358 2359 static void nvme_pci_disable(struct nvme_dev *dev) 2360 { 2361 struct pci_dev *pdev = to_pci_dev(dev->dev); 2362 2363 pci_free_irq_vectors(pdev); 2364 2365 if (pci_is_enabled(pdev)) { 2366 pci_disable_pcie_error_reporting(pdev); 2367 pci_disable_device(pdev); 2368 } 2369 } 2370 2371 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2372 { 2373 bool dead = true, freeze = false; 2374 struct pci_dev *pdev = to_pci_dev(dev->dev); 2375 2376 mutex_lock(&dev->shutdown_lock); 2377 if (pci_is_enabled(pdev)) { 2378 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2379 2380 if (dev->ctrl.state == NVME_CTRL_LIVE || 2381 dev->ctrl.state == NVME_CTRL_RESETTING) { 2382 freeze = true; 2383 nvme_start_freeze(&dev->ctrl); 2384 } 2385 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2386 pdev->error_state != pci_channel_io_normal); 2387 } 2388 2389 /* 2390 * Give the controller a chance to complete all entered requests if 2391 * doing a safe shutdown. 2392 */ 2393 if (!dead && shutdown && freeze) 2394 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2395 2396 nvme_stop_queues(&dev->ctrl); 2397 2398 if (!dead && dev->ctrl.queue_count > 0) { 2399 nvme_disable_io_queues(dev); 2400 nvme_disable_admin_queue(dev, shutdown); 2401 } 2402 nvme_suspend_io_queues(dev); 2403 nvme_suspend_queue(&dev->queues[0]); 2404 nvme_pci_disable(dev); 2405 2406 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2407 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2408 2409 /* 2410 * The driver will not be starting up queues again if shutting down so 2411 * must flush all entered requests to their failed completion to avoid 2412 * deadlocking blk-mq hot-cpu notifier. 2413 */ 2414 if (shutdown) { 2415 nvme_start_queues(&dev->ctrl); 2416 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2417 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2418 } 2419 mutex_unlock(&dev->shutdown_lock); 2420 } 2421 2422 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2423 { 2424 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2425 PAGE_SIZE, PAGE_SIZE, 0); 2426 if (!dev->prp_page_pool) 2427 return -ENOMEM; 2428 2429 /* Optimisation for I/Os between 4k and 128k */ 2430 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2431 256, 256, 0); 2432 if (!dev->prp_small_pool) { 2433 dma_pool_destroy(dev->prp_page_pool); 2434 return -ENOMEM; 2435 } 2436 return 0; 2437 } 2438 2439 static void nvme_release_prp_pools(struct nvme_dev *dev) 2440 { 2441 dma_pool_destroy(dev->prp_page_pool); 2442 dma_pool_destroy(dev->prp_small_pool); 2443 } 2444 2445 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2446 { 2447 struct nvme_dev *dev = to_nvme_dev(ctrl); 2448 2449 nvme_dbbuf_dma_free(dev); 2450 put_device(dev->dev); 2451 if (dev->tagset.tags) 2452 blk_mq_free_tag_set(&dev->tagset); 2453 if (dev->ctrl.admin_q) 2454 blk_put_queue(dev->ctrl.admin_q); 2455 kfree(dev->queues); 2456 free_opal_dev(dev->ctrl.opal_dev); 2457 mempool_destroy(dev->iod_mempool); 2458 kfree(dev); 2459 } 2460 2461 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2462 { 2463 nvme_get_ctrl(&dev->ctrl); 2464 nvme_dev_disable(dev, false); 2465 nvme_kill_queues(&dev->ctrl); 2466 if (!queue_work(nvme_wq, &dev->remove_work)) 2467 nvme_put_ctrl(&dev->ctrl); 2468 } 2469 2470 static void nvme_reset_work(struct work_struct *work) 2471 { 2472 struct nvme_dev *dev = 2473 container_of(work, struct nvme_dev, ctrl.reset_work); 2474 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2475 int result; 2476 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2477 2478 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2479 result = -ENODEV; 2480 goto out; 2481 } 2482 2483 /* 2484 * If we're called to reset a live controller first shut it down before 2485 * moving on. 2486 */ 2487 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2488 nvme_dev_disable(dev, false); 2489 nvme_sync_queues(&dev->ctrl); 2490 2491 mutex_lock(&dev->shutdown_lock); 2492 result = nvme_pci_enable(dev); 2493 if (result) 2494 goto out_unlock; 2495 2496 result = nvme_pci_configure_admin_queue(dev); 2497 if (result) 2498 goto out_unlock; 2499 2500 result = nvme_alloc_admin_tags(dev); 2501 if (result) 2502 goto out_unlock; 2503 2504 /* 2505 * Limit the max command size to prevent iod->sg allocations going 2506 * over a single page. 2507 */ 2508 dev->ctrl.max_hw_sectors = min_t(u32, 2509 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2510 dev->ctrl.max_segments = NVME_MAX_SEGS; 2511 2512 /* 2513 * Don't limit the IOMMU merged segment size. 2514 */ 2515 dma_set_max_seg_size(dev->dev, 0xffffffff); 2516 2517 mutex_unlock(&dev->shutdown_lock); 2518 2519 /* 2520 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2521 * initializing procedure here. 2522 */ 2523 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2524 dev_warn(dev->ctrl.device, 2525 "failed to mark controller CONNECTING\n"); 2526 result = -EBUSY; 2527 goto out; 2528 } 2529 2530 result = nvme_init_identify(&dev->ctrl); 2531 if (result) 2532 goto out; 2533 2534 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2535 if (!dev->ctrl.opal_dev) 2536 dev->ctrl.opal_dev = 2537 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2538 else if (was_suspend) 2539 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2540 } else { 2541 free_opal_dev(dev->ctrl.opal_dev); 2542 dev->ctrl.opal_dev = NULL; 2543 } 2544 2545 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2546 result = nvme_dbbuf_dma_alloc(dev); 2547 if (result) 2548 dev_warn(dev->dev, 2549 "unable to allocate dma for dbbuf\n"); 2550 } 2551 2552 if (dev->ctrl.hmpre) { 2553 result = nvme_setup_host_mem(dev); 2554 if (result < 0) 2555 goto out; 2556 } 2557 2558 result = nvme_setup_io_queues(dev); 2559 if (result) 2560 goto out; 2561 2562 /* 2563 * Keep the controller around but remove all namespaces if we don't have 2564 * any working I/O queue. 2565 */ 2566 if (dev->online_queues < 2) { 2567 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2568 nvme_kill_queues(&dev->ctrl); 2569 nvme_remove_namespaces(&dev->ctrl); 2570 new_state = NVME_CTRL_ADMIN_ONLY; 2571 } else { 2572 nvme_start_queues(&dev->ctrl); 2573 nvme_wait_freeze(&dev->ctrl); 2574 /* hit this only when allocate tagset fails */ 2575 if (nvme_dev_add(dev)) 2576 new_state = NVME_CTRL_ADMIN_ONLY; 2577 nvme_unfreeze(&dev->ctrl); 2578 } 2579 2580 /* 2581 * If only admin queue live, keep it to do further investigation or 2582 * recovery. 2583 */ 2584 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2585 dev_warn(dev->ctrl.device, 2586 "failed to mark controller state %d\n", new_state); 2587 result = -ENODEV; 2588 goto out; 2589 } 2590 2591 nvme_start_ctrl(&dev->ctrl); 2592 return; 2593 2594 out_unlock: 2595 mutex_unlock(&dev->shutdown_lock); 2596 out: 2597 if (result) 2598 dev_warn(dev->ctrl.device, 2599 "Removing after probe failure status: %d\n", result); 2600 nvme_remove_dead_ctrl(dev); 2601 } 2602 2603 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2604 { 2605 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2606 struct pci_dev *pdev = to_pci_dev(dev->dev); 2607 2608 if (pci_get_drvdata(pdev)) 2609 device_release_driver(&pdev->dev); 2610 nvme_put_ctrl(&dev->ctrl); 2611 } 2612 2613 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2614 { 2615 *val = readl(to_nvme_dev(ctrl)->bar + off); 2616 return 0; 2617 } 2618 2619 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2620 { 2621 writel(val, to_nvme_dev(ctrl)->bar + off); 2622 return 0; 2623 } 2624 2625 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2626 { 2627 *val = readq(to_nvme_dev(ctrl)->bar + off); 2628 return 0; 2629 } 2630 2631 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2632 { 2633 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2634 2635 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2636 } 2637 2638 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2639 .name = "pcie", 2640 .module = THIS_MODULE, 2641 .flags = NVME_F_METADATA_SUPPORTED | 2642 NVME_F_PCI_P2PDMA, 2643 .reg_read32 = nvme_pci_reg_read32, 2644 .reg_write32 = nvme_pci_reg_write32, 2645 .reg_read64 = nvme_pci_reg_read64, 2646 .free_ctrl = nvme_pci_free_ctrl, 2647 .submit_async_event = nvme_pci_submit_async_event, 2648 .get_address = nvme_pci_get_address, 2649 }; 2650 2651 static int nvme_dev_map(struct nvme_dev *dev) 2652 { 2653 struct pci_dev *pdev = to_pci_dev(dev->dev); 2654 2655 if (pci_request_mem_regions(pdev, "nvme")) 2656 return -ENODEV; 2657 2658 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2659 goto release; 2660 2661 return 0; 2662 release: 2663 pci_release_mem_regions(pdev); 2664 return -ENODEV; 2665 } 2666 2667 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2668 { 2669 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2670 /* 2671 * Several Samsung devices seem to drop off the PCIe bus 2672 * randomly when APST is on and uses the deepest sleep state. 2673 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2674 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2675 * 950 PRO 256GB", but it seems to be restricted to two Dell 2676 * laptops. 2677 */ 2678 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2679 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2680 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2681 return NVME_QUIRK_NO_DEEPEST_PS; 2682 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2683 /* 2684 * Samsung SSD 960 EVO drops off the PCIe bus after system 2685 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2686 * within few minutes after bootup on a Coffee Lake board - 2687 * ASUS PRIME Z370-A 2688 */ 2689 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2690 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2691 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2692 return NVME_QUIRK_NO_APST; 2693 } 2694 2695 return 0; 2696 } 2697 2698 static void nvme_async_probe(void *data, async_cookie_t cookie) 2699 { 2700 struct nvme_dev *dev = data; 2701 2702 nvme_reset_ctrl_sync(&dev->ctrl); 2703 flush_work(&dev->ctrl.scan_work); 2704 nvme_put_ctrl(&dev->ctrl); 2705 } 2706 2707 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2708 { 2709 int node, result = -ENOMEM; 2710 struct nvme_dev *dev; 2711 unsigned long quirks = id->driver_data; 2712 size_t alloc_size; 2713 2714 node = dev_to_node(&pdev->dev); 2715 if (node == NUMA_NO_NODE) 2716 set_dev_node(&pdev->dev, first_memory_node); 2717 2718 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2719 if (!dev) 2720 return -ENOMEM; 2721 2722 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2723 GFP_KERNEL, node); 2724 if (!dev->queues) 2725 goto free; 2726 2727 dev->dev = get_device(&pdev->dev); 2728 pci_set_drvdata(pdev, dev); 2729 2730 result = nvme_dev_map(dev); 2731 if (result) 2732 goto put_pci; 2733 2734 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2735 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2736 mutex_init(&dev->shutdown_lock); 2737 2738 result = nvme_setup_prp_pools(dev); 2739 if (result) 2740 goto unmap; 2741 2742 quirks |= check_vendor_combination_bug(pdev); 2743 2744 /* 2745 * Double check that our mempool alloc size will cover the biggest 2746 * command we support. 2747 */ 2748 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2749 NVME_MAX_SEGS, true); 2750 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2751 2752 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2753 mempool_kfree, 2754 (void *) alloc_size, 2755 GFP_KERNEL, node); 2756 if (!dev->iod_mempool) { 2757 result = -ENOMEM; 2758 goto release_pools; 2759 } 2760 2761 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2762 quirks); 2763 if (result) 2764 goto release_mempool; 2765 2766 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2767 2768 nvme_get_ctrl(&dev->ctrl); 2769 async_schedule(nvme_async_probe, dev); 2770 2771 return 0; 2772 2773 release_mempool: 2774 mempool_destroy(dev->iod_mempool); 2775 release_pools: 2776 nvme_release_prp_pools(dev); 2777 unmap: 2778 nvme_dev_unmap(dev); 2779 put_pci: 2780 put_device(dev->dev); 2781 free: 2782 kfree(dev->queues); 2783 kfree(dev); 2784 return result; 2785 } 2786 2787 static void nvme_reset_prepare(struct pci_dev *pdev) 2788 { 2789 struct nvme_dev *dev = pci_get_drvdata(pdev); 2790 nvme_dev_disable(dev, false); 2791 } 2792 2793 static void nvme_reset_done(struct pci_dev *pdev) 2794 { 2795 struct nvme_dev *dev = pci_get_drvdata(pdev); 2796 nvme_reset_ctrl_sync(&dev->ctrl); 2797 } 2798 2799 static void nvme_shutdown(struct pci_dev *pdev) 2800 { 2801 struct nvme_dev *dev = pci_get_drvdata(pdev); 2802 nvme_dev_disable(dev, true); 2803 } 2804 2805 /* 2806 * The driver's remove may be called on a device in a partially initialized 2807 * state. This function must not have any dependencies on the device state in 2808 * order to proceed. 2809 */ 2810 static void nvme_remove(struct pci_dev *pdev) 2811 { 2812 struct nvme_dev *dev = pci_get_drvdata(pdev); 2813 2814 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2815 pci_set_drvdata(pdev, NULL); 2816 2817 if (!pci_device_is_present(pdev)) { 2818 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2819 nvme_dev_disable(dev, true); 2820 nvme_dev_remove_admin(dev); 2821 } 2822 2823 flush_work(&dev->ctrl.reset_work); 2824 nvme_stop_ctrl(&dev->ctrl); 2825 nvme_remove_namespaces(&dev->ctrl); 2826 nvme_dev_disable(dev, true); 2827 nvme_release_cmb(dev); 2828 nvme_free_host_mem(dev); 2829 nvme_dev_remove_admin(dev); 2830 nvme_free_queues(dev, 0); 2831 nvme_uninit_ctrl(&dev->ctrl); 2832 nvme_release_prp_pools(dev); 2833 nvme_dev_unmap(dev); 2834 nvme_put_ctrl(&dev->ctrl); 2835 } 2836 2837 #ifdef CONFIG_PM_SLEEP 2838 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2839 { 2840 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2841 } 2842 2843 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2844 { 2845 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2846 } 2847 2848 static int nvme_resume(struct device *dev) 2849 { 2850 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2851 struct nvme_ctrl *ctrl = &ndev->ctrl; 2852 2853 if (pm_resume_via_firmware() || !ctrl->npss || 2854 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2855 nvme_reset_ctrl(ctrl); 2856 return 0; 2857 } 2858 2859 static int nvme_suspend(struct device *dev) 2860 { 2861 struct pci_dev *pdev = to_pci_dev(dev); 2862 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2863 struct nvme_ctrl *ctrl = &ndev->ctrl; 2864 int ret = -EBUSY; 2865 2866 /* 2867 * The platform does not remove power for a kernel managed suspend so 2868 * use host managed nvme power settings for lowest idle power if 2869 * possible. This should have quicker resume latency than a full device 2870 * shutdown. But if the firmware is involved after the suspend or the 2871 * device does not support any non-default power states, shut down the 2872 * device fully. 2873 */ 2874 if (pm_suspend_via_firmware() || !ctrl->npss) { 2875 nvme_dev_disable(ndev, true); 2876 return 0; 2877 } 2878 2879 nvme_start_freeze(ctrl); 2880 nvme_wait_freeze(ctrl); 2881 nvme_sync_queues(ctrl); 2882 2883 if (ctrl->state != NVME_CTRL_LIVE && 2884 ctrl->state != NVME_CTRL_ADMIN_ONLY) 2885 goto unfreeze; 2886 2887 ndev->last_ps = 0; 2888 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2889 if (ret < 0) 2890 goto unfreeze; 2891 2892 ret = nvme_set_power_state(ctrl, ctrl->npss); 2893 if (ret < 0) 2894 goto unfreeze; 2895 2896 if (ret) { 2897 /* 2898 * Clearing npss forces a controller reset on resume. The 2899 * correct value will be resdicovered then. 2900 */ 2901 nvme_dev_disable(ndev, true); 2902 ctrl->npss = 0; 2903 ret = 0; 2904 goto unfreeze; 2905 } 2906 /* 2907 * A saved state prevents pci pm from generically controlling the 2908 * device's power. If we're using protocol specific settings, we don't 2909 * want pci interfering. 2910 */ 2911 pci_save_state(pdev); 2912 unfreeze: 2913 nvme_unfreeze(ctrl); 2914 return ret; 2915 } 2916 2917 static int nvme_simple_suspend(struct device *dev) 2918 { 2919 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2920 2921 nvme_dev_disable(ndev, true); 2922 return 0; 2923 } 2924 2925 static int nvme_simple_resume(struct device *dev) 2926 { 2927 struct pci_dev *pdev = to_pci_dev(dev); 2928 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2929 2930 nvme_reset_ctrl(&ndev->ctrl); 2931 return 0; 2932 } 2933 2934 static const struct dev_pm_ops nvme_dev_pm_ops = { 2935 .suspend = nvme_suspend, 2936 .resume = nvme_resume, 2937 .freeze = nvme_simple_suspend, 2938 .thaw = nvme_simple_resume, 2939 .poweroff = nvme_simple_suspend, 2940 .restore = nvme_simple_resume, 2941 }; 2942 #endif /* CONFIG_PM_SLEEP */ 2943 2944 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2945 pci_channel_state_t state) 2946 { 2947 struct nvme_dev *dev = pci_get_drvdata(pdev); 2948 2949 /* 2950 * A frozen channel requires a reset. When detected, this method will 2951 * shutdown the controller to quiesce. The controller will be restarted 2952 * after the slot reset through driver's slot_reset callback. 2953 */ 2954 switch (state) { 2955 case pci_channel_io_normal: 2956 return PCI_ERS_RESULT_CAN_RECOVER; 2957 case pci_channel_io_frozen: 2958 dev_warn(dev->ctrl.device, 2959 "frozen state error detected, reset controller\n"); 2960 nvme_dev_disable(dev, false); 2961 return PCI_ERS_RESULT_NEED_RESET; 2962 case pci_channel_io_perm_failure: 2963 dev_warn(dev->ctrl.device, 2964 "failure state error detected, request disconnect\n"); 2965 return PCI_ERS_RESULT_DISCONNECT; 2966 } 2967 return PCI_ERS_RESULT_NEED_RESET; 2968 } 2969 2970 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2971 { 2972 struct nvme_dev *dev = pci_get_drvdata(pdev); 2973 2974 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2975 pci_restore_state(pdev); 2976 nvme_reset_ctrl(&dev->ctrl); 2977 return PCI_ERS_RESULT_RECOVERED; 2978 } 2979 2980 static void nvme_error_resume(struct pci_dev *pdev) 2981 { 2982 struct nvme_dev *dev = pci_get_drvdata(pdev); 2983 2984 flush_work(&dev->ctrl.reset_work); 2985 } 2986 2987 static const struct pci_error_handlers nvme_err_handler = { 2988 .error_detected = nvme_error_detected, 2989 .slot_reset = nvme_slot_reset, 2990 .resume = nvme_error_resume, 2991 .reset_prepare = nvme_reset_prepare, 2992 .reset_done = nvme_reset_done, 2993 }; 2994 2995 static const struct pci_device_id nvme_id_table[] = { 2996 { PCI_VDEVICE(INTEL, 0x0953), 2997 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2998 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2999 { PCI_VDEVICE(INTEL, 0x0a53), 3000 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3001 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3002 { PCI_VDEVICE(INTEL, 0x0a54), 3003 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3004 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3005 { PCI_VDEVICE(INTEL, 0x0a55), 3006 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3007 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3008 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3009 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3010 NVME_QUIRK_MEDIUM_PRIO_SQ }, 3011 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3012 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3013 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3014 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3015 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3016 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3017 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3018 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3019 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3020 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3021 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3022 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3023 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3024 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3025 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3026 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3027 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3028 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3029 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3030 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3031 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3032 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3033 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3034 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3035 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3036 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3037 { 0, } 3038 }; 3039 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3040 3041 static struct pci_driver nvme_driver = { 3042 .name = "nvme", 3043 .id_table = nvme_id_table, 3044 .probe = nvme_probe, 3045 .remove = nvme_remove, 3046 .shutdown = nvme_shutdown, 3047 #ifdef CONFIG_PM_SLEEP 3048 .driver = { 3049 .pm = &nvme_dev_pm_ops, 3050 }, 3051 #endif 3052 .sriov_configure = pci_sriov_configure_simple, 3053 .err_handler = &nvme_err_handler, 3054 }; 3055 3056 static int __init nvme_init(void) 3057 { 3058 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3059 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3060 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3061 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3062 return pci_register_driver(&nvme_driver); 3063 } 3064 3065 static void __exit nvme_exit(void) 3066 { 3067 pci_unregister_driver(&nvme_driver); 3068 flush_workqueue(nvme_wq); 3069 } 3070 3071 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3072 MODULE_LICENSE("GPL"); 3073 MODULE_VERSION("1.0"); 3074 module_init(nvme_init); 3075 module_exit(nvme_exit); 3076