1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static int write_queues; 72 module_param(write_queues, int, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static int poll_queues; 78 module_param(poll_queues, int, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 int io_sqes; 104 u32 db_stride; 105 void __iomem *bar; 106 unsigned long bar_mapped_size; 107 struct work_struct remove_work; 108 struct mutex shutdown_lock; 109 bool subsystem; 110 u64 cmb_size; 111 bool cmb_use_sqes; 112 u32 cmbsz; 113 u32 cmbloc; 114 struct nvme_ctrl ctrl; 115 u32 last_ps; 116 117 mempool_t *iod_mempool; 118 119 /* shadow doorbell buffer support: */ 120 u32 *dbbuf_dbs; 121 dma_addr_t dbbuf_dbs_dma_addr; 122 u32 *dbbuf_eis; 123 dma_addr_t dbbuf_eis_dma_addr; 124 125 /* host memory buffer support: */ 126 u64 host_mem_size; 127 u32 nr_host_mem_descs; 128 dma_addr_t host_mem_descs_dma; 129 struct nvme_host_mem_buf_desc *host_mem_descs; 130 void **host_mem_desc_bufs; 131 }; 132 133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134 { 135 int n = 0, ret; 136 137 ret = kstrtoint(val, 10, &n); 138 if (ret != 0 || n < 2) 139 return -EINVAL; 140 141 return param_set_int(val, kp); 142 } 143 144 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145 { 146 return qid * 2 * stride; 147 } 148 149 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150 { 151 return (qid * 2 + 1) * stride; 152 } 153 154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 155 { 156 return container_of(ctrl, struct nvme_dev, ctrl); 157 } 158 159 /* 160 * An NVM Express queue. Each device has at least two (one for admin 161 * commands and one for I/O commands). 162 */ 163 struct nvme_queue { 164 struct nvme_dev *dev; 165 spinlock_t sq_lock; 166 void *sq_cmds; 167 /* only used for poll queues: */ 168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 169 volatile struct nvme_completion *cqes; 170 struct blk_mq_tags **tags; 171 dma_addr_t sq_dma_addr; 172 dma_addr_t cq_dma_addr; 173 u32 __iomem *q_db; 174 u16 q_depth; 175 u16 cq_vector; 176 u16 sq_tail; 177 u16 last_sq_tail; 178 u16 cq_head; 179 u16 last_cq_head; 180 u16 qid; 181 u8 cq_phase; 182 u8 sqes; 183 unsigned long flags; 184 #define NVMEQ_ENABLED 0 185 #define NVMEQ_SQ_CMB 1 186 #define NVMEQ_DELETE_ERROR 2 187 #define NVMEQ_POLLED 3 188 u32 *dbbuf_sq_db; 189 u32 *dbbuf_cq_db; 190 u32 *dbbuf_sq_ei; 191 u32 *dbbuf_cq_ei; 192 struct completion delete_done; 193 }; 194 195 /* 196 * The nvme_iod describes the data in an I/O. 197 * 198 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 199 * to the actual struct scatterlist. 200 */ 201 struct nvme_iod { 202 struct nvme_request req; 203 struct nvme_queue *nvmeq; 204 bool use_sgl; 205 int aborted; 206 int npages; /* In the PRP list. 0 means small pool in use */ 207 int nents; /* Used in scatterlist */ 208 dma_addr_t first_dma; 209 unsigned int dma_len; /* length of single DMA segment mapping */ 210 dma_addr_t meta_dma; 211 struct scatterlist *sg; 212 }; 213 214 static unsigned int max_io_queues(void) 215 { 216 return num_possible_cpus() + write_queues + poll_queues; 217 } 218 219 static unsigned int max_queue_count(void) 220 { 221 /* IO queues + admin queue */ 222 return 1 + max_io_queues(); 223 } 224 225 static inline unsigned int nvme_dbbuf_size(u32 stride) 226 { 227 return (max_queue_count() * 8 * stride); 228 } 229 230 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 231 { 232 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 233 234 if (dev->dbbuf_dbs) 235 return 0; 236 237 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 238 &dev->dbbuf_dbs_dma_addr, 239 GFP_KERNEL); 240 if (!dev->dbbuf_dbs) 241 return -ENOMEM; 242 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 243 &dev->dbbuf_eis_dma_addr, 244 GFP_KERNEL); 245 if (!dev->dbbuf_eis) { 246 dma_free_coherent(dev->dev, mem_size, 247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 248 dev->dbbuf_dbs = NULL; 249 return -ENOMEM; 250 } 251 252 return 0; 253 } 254 255 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 256 { 257 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 258 259 if (dev->dbbuf_dbs) { 260 dma_free_coherent(dev->dev, mem_size, 261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 262 dev->dbbuf_dbs = NULL; 263 } 264 if (dev->dbbuf_eis) { 265 dma_free_coherent(dev->dev, mem_size, 266 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 267 dev->dbbuf_eis = NULL; 268 } 269 } 270 271 static void nvme_dbbuf_init(struct nvme_dev *dev, 272 struct nvme_queue *nvmeq, int qid) 273 { 274 if (!dev->dbbuf_dbs || !qid) 275 return; 276 277 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 279 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 280 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 281 } 282 283 static void nvme_dbbuf_set(struct nvme_dev *dev) 284 { 285 struct nvme_command c; 286 287 if (!dev->dbbuf_dbs) 288 return; 289 290 memset(&c, 0, sizeof(c)); 291 c.dbbuf.opcode = nvme_admin_dbbuf; 292 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 293 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 294 295 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 296 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 297 /* Free memory and continue on */ 298 nvme_dbbuf_dma_free(dev); 299 } 300 } 301 302 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 303 { 304 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 305 } 306 307 /* Update dbbuf and return true if an MMIO is required */ 308 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 309 volatile u32 *dbbuf_ei) 310 { 311 if (dbbuf_db) { 312 u16 old_value; 313 314 /* 315 * Ensure that the queue is written before updating 316 * the doorbell in memory 317 */ 318 wmb(); 319 320 old_value = *dbbuf_db; 321 *dbbuf_db = value; 322 323 /* 324 * Ensure that the doorbell is updated before reading the event 325 * index from memory. The controller needs to provide similar 326 * ordering to ensure the envent index is updated before reading 327 * the doorbell. 328 */ 329 mb(); 330 331 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 332 return false; 333 } 334 335 return true; 336 } 337 338 /* 339 * Will slightly overestimate the number of pages needed. This is OK 340 * as it only leads to a small amount of wasted memory for the lifetime of 341 * the I/O. 342 */ 343 static int nvme_npages(unsigned size, struct nvme_dev *dev) 344 { 345 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 346 dev->ctrl.page_size); 347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 348 } 349 350 /* 351 * Calculates the number of pages needed for the SGL segments. For example a 4k 352 * page can accommodate 256 SGL descriptors. 353 */ 354 static int nvme_pci_npages_sgl(unsigned int num_seg) 355 { 356 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 357 } 358 359 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 360 unsigned int size, unsigned int nseg, bool use_sgl) 361 { 362 size_t alloc_size; 363 364 if (use_sgl) 365 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 366 else 367 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 368 369 return alloc_size + sizeof(struct scatterlist) * nseg; 370 } 371 372 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 373 unsigned int hctx_idx) 374 { 375 struct nvme_dev *dev = data; 376 struct nvme_queue *nvmeq = &dev->queues[0]; 377 378 WARN_ON(hctx_idx != 0); 379 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 380 WARN_ON(nvmeq->tags); 381 382 hctx->driver_data = nvmeq; 383 nvmeq->tags = &dev->admin_tagset.tags[0]; 384 return 0; 385 } 386 387 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 388 { 389 struct nvme_queue *nvmeq = hctx->driver_data; 390 391 nvmeq->tags = NULL; 392 } 393 394 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 395 unsigned int hctx_idx) 396 { 397 struct nvme_dev *dev = data; 398 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 399 400 if (!nvmeq->tags) 401 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 402 403 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 404 hctx->driver_data = nvmeq; 405 return 0; 406 } 407 408 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 409 unsigned int hctx_idx, unsigned int numa_node) 410 { 411 struct nvme_dev *dev = set->driver_data; 412 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 413 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 414 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 415 416 BUG_ON(!nvmeq); 417 iod->nvmeq = nvmeq; 418 419 nvme_req(req)->ctrl = &dev->ctrl; 420 return 0; 421 } 422 423 static int queue_irq_offset(struct nvme_dev *dev) 424 { 425 /* if we have more than 1 vec, admin queue offsets us by 1 */ 426 if (dev->num_vecs > 1) 427 return 1; 428 429 return 0; 430 } 431 432 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 433 { 434 struct nvme_dev *dev = set->driver_data; 435 int i, qoff, offset; 436 437 offset = queue_irq_offset(dev); 438 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 439 struct blk_mq_queue_map *map = &set->map[i]; 440 441 map->nr_queues = dev->io_queues[i]; 442 if (!map->nr_queues) { 443 BUG_ON(i == HCTX_TYPE_DEFAULT); 444 continue; 445 } 446 447 /* 448 * The poll queue(s) doesn't have an IRQ (and hence IRQ 449 * affinity), so use the regular blk-mq cpu mapping 450 */ 451 map->queue_offset = qoff; 452 if (i != HCTX_TYPE_POLL && offset) 453 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 454 else 455 blk_mq_map_queues(map); 456 qoff += map->nr_queues; 457 offset += map->nr_queues; 458 } 459 460 return 0; 461 } 462 463 /* 464 * Write sq tail if we are asked to, or if the next command would wrap. 465 */ 466 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 467 { 468 if (!write_sq) { 469 u16 next_tail = nvmeq->sq_tail + 1; 470 471 if (next_tail == nvmeq->q_depth) 472 next_tail = 0; 473 if (next_tail != nvmeq->last_sq_tail) 474 return; 475 } 476 477 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 478 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 479 writel(nvmeq->sq_tail, nvmeq->q_db); 480 nvmeq->last_sq_tail = nvmeq->sq_tail; 481 } 482 483 /** 484 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 485 * @nvmeq: The queue to use 486 * @cmd: The command to send 487 * @write_sq: whether to write to the SQ doorbell 488 */ 489 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 490 bool write_sq) 491 { 492 spin_lock(&nvmeq->sq_lock); 493 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 494 cmd, sizeof(*cmd)); 495 if (++nvmeq->sq_tail == nvmeq->q_depth) 496 nvmeq->sq_tail = 0; 497 nvme_write_sq_db(nvmeq, write_sq); 498 spin_unlock(&nvmeq->sq_lock); 499 } 500 501 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 502 { 503 struct nvme_queue *nvmeq = hctx->driver_data; 504 505 spin_lock(&nvmeq->sq_lock); 506 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 507 nvme_write_sq_db(nvmeq, true); 508 spin_unlock(&nvmeq->sq_lock); 509 } 510 511 static void **nvme_pci_iod_list(struct request *req) 512 { 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 515 } 516 517 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518 { 519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 520 int nseg = blk_rq_nr_phys_segments(req); 521 unsigned int avg_seg_size; 522 523 if (nseg == 0) 524 return false; 525 526 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 527 528 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 529 return false; 530 if (!iod->nvmeq->qid) 531 return false; 532 if (!sgl_threshold || avg_seg_size < sgl_threshold) 533 return false; 534 return true; 535 } 536 537 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 538 { 539 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 540 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 541 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 542 int i; 543 544 if (iod->dma_len) { 545 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 546 rq_dma_dir(req)); 547 return; 548 } 549 550 WARN_ON_ONCE(!iod->nents); 551 552 /* P2PDMA requests do not need to be unmapped */ 553 if (!is_pci_p2pdma_page(sg_page(iod->sg))) 554 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 555 556 557 if (iod->npages == 0) 558 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 559 dma_addr); 560 561 for (i = 0; i < iod->npages; i++) { 562 void *addr = nvme_pci_iod_list(req)[i]; 563 564 if (iod->use_sgl) { 565 struct nvme_sgl_desc *sg_list = addr; 566 567 next_dma_addr = 568 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 569 } else { 570 __le64 *prp_list = addr; 571 572 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 573 } 574 575 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 576 dma_addr = next_dma_addr; 577 } 578 579 mempool_free(iod->sg, dev->iod_mempool); 580 } 581 582 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 583 { 584 int i; 585 struct scatterlist *sg; 586 587 for_each_sg(sgl, sg, nents, i) { 588 dma_addr_t phys = sg_phys(sg); 589 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 590 "dma_address:%pad dma_length:%d\n", 591 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 592 sg_dma_len(sg)); 593 } 594 } 595 596 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 597 struct request *req, struct nvme_rw_command *cmnd) 598 { 599 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 600 struct dma_pool *pool; 601 int length = blk_rq_payload_bytes(req); 602 struct scatterlist *sg = iod->sg; 603 int dma_len = sg_dma_len(sg); 604 u64 dma_addr = sg_dma_address(sg); 605 u32 page_size = dev->ctrl.page_size; 606 int offset = dma_addr & (page_size - 1); 607 __le64 *prp_list; 608 void **list = nvme_pci_iod_list(req); 609 dma_addr_t prp_dma; 610 int nprps, i; 611 612 length -= (page_size - offset); 613 if (length <= 0) { 614 iod->first_dma = 0; 615 goto done; 616 } 617 618 dma_len -= (page_size - offset); 619 if (dma_len) { 620 dma_addr += (page_size - offset); 621 } else { 622 sg = sg_next(sg); 623 dma_addr = sg_dma_address(sg); 624 dma_len = sg_dma_len(sg); 625 } 626 627 if (length <= page_size) { 628 iod->first_dma = dma_addr; 629 goto done; 630 } 631 632 nprps = DIV_ROUND_UP(length, page_size); 633 if (nprps <= (256 / 8)) { 634 pool = dev->prp_small_pool; 635 iod->npages = 0; 636 } else { 637 pool = dev->prp_page_pool; 638 iod->npages = 1; 639 } 640 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 642 if (!prp_list) { 643 iod->first_dma = dma_addr; 644 iod->npages = -1; 645 return BLK_STS_RESOURCE; 646 } 647 list[0] = prp_list; 648 iod->first_dma = prp_dma; 649 i = 0; 650 for (;;) { 651 if (i == page_size >> 3) { 652 __le64 *old_prp_list = prp_list; 653 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 654 if (!prp_list) 655 return BLK_STS_RESOURCE; 656 list[iod->npages++] = prp_list; 657 prp_list[0] = old_prp_list[i - 1]; 658 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 659 i = 1; 660 } 661 prp_list[i++] = cpu_to_le64(dma_addr); 662 dma_len -= page_size; 663 dma_addr += page_size; 664 length -= page_size; 665 if (length <= 0) 666 break; 667 if (dma_len > 0) 668 continue; 669 if (unlikely(dma_len < 0)) 670 goto bad_sgl; 671 sg = sg_next(sg); 672 dma_addr = sg_dma_address(sg); 673 dma_len = sg_dma_len(sg); 674 } 675 676 done: 677 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 678 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 679 680 return BLK_STS_OK; 681 682 bad_sgl: 683 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 684 "Invalid SGL for payload:%d nents:%d\n", 685 blk_rq_payload_bytes(req), iod->nents); 686 return BLK_STS_IOERR; 687 } 688 689 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 690 struct scatterlist *sg) 691 { 692 sge->addr = cpu_to_le64(sg_dma_address(sg)); 693 sge->length = cpu_to_le32(sg_dma_len(sg)); 694 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 695 } 696 697 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 698 dma_addr_t dma_addr, int entries) 699 { 700 sge->addr = cpu_to_le64(dma_addr); 701 if (entries < SGES_PER_PAGE) { 702 sge->length = cpu_to_le32(entries * sizeof(*sge)); 703 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 704 } else { 705 sge->length = cpu_to_le32(PAGE_SIZE); 706 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 707 } 708 } 709 710 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 711 struct request *req, struct nvme_rw_command *cmd, int entries) 712 { 713 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 714 struct dma_pool *pool; 715 struct nvme_sgl_desc *sg_list; 716 struct scatterlist *sg = iod->sg; 717 dma_addr_t sgl_dma; 718 int i = 0; 719 720 /* setting the transfer type as SGL */ 721 cmd->flags = NVME_CMD_SGL_METABUF; 722 723 if (entries == 1) { 724 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 725 return BLK_STS_OK; 726 } 727 728 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 729 pool = dev->prp_small_pool; 730 iod->npages = 0; 731 } else { 732 pool = dev->prp_page_pool; 733 iod->npages = 1; 734 } 735 736 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 737 if (!sg_list) { 738 iod->npages = -1; 739 return BLK_STS_RESOURCE; 740 } 741 742 nvme_pci_iod_list(req)[0] = sg_list; 743 iod->first_dma = sgl_dma; 744 745 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 746 747 do { 748 if (i == SGES_PER_PAGE) { 749 struct nvme_sgl_desc *old_sg_desc = sg_list; 750 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 751 752 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 753 if (!sg_list) 754 return BLK_STS_RESOURCE; 755 756 i = 0; 757 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 758 sg_list[i++] = *link; 759 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 760 } 761 762 nvme_pci_sgl_set_data(&sg_list[i++], sg); 763 sg = sg_next(sg); 764 } while (--entries > 0); 765 766 return BLK_STS_OK; 767 } 768 769 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 770 struct request *req, struct nvme_rw_command *cmnd, 771 struct bio_vec *bv) 772 { 773 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 774 unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 775 776 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 777 if (dma_mapping_error(dev->dev, iod->first_dma)) 778 return BLK_STS_RESOURCE; 779 iod->dma_len = bv->bv_len; 780 781 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 782 if (bv->bv_len > first_prp_len) 783 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 784 return 0; 785 } 786 787 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 788 struct request *req, struct nvme_rw_command *cmnd, 789 struct bio_vec *bv) 790 { 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 792 793 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 794 if (dma_mapping_error(dev->dev, iod->first_dma)) 795 return BLK_STS_RESOURCE; 796 iod->dma_len = bv->bv_len; 797 798 cmnd->flags = NVME_CMD_SGL_METABUF; 799 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 800 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 801 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 802 return 0; 803 } 804 805 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 806 struct nvme_command *cmnd) 807 { 808 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 809 blk_status_t ret = BLK_STS_RESOURCE; 810 int nr_mapped; 811 812 if (blk_rq_nr_phys_segments(req) == 1) { 813 struct bio_vec bv = req_bvec(req); 814 815 if (!is_pci_p2pdma_page(bv.bv_page)) { 816 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 817 return nvme_setup_prp_simple(dev, req, 818 &cmnd->rw, &bv); 819 820 if (iod->nvmeq->qid && 821 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 822 return nvme_setup_sgl_simple(dev, req, 823 &cmnd->rw, &bv); 824 } 825 } 826 827 iod->dma_len = 0; 828 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 829 if (!iod->sg) 830 return BLK_STS_RESOURCE; 831 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 832 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 833 if (!iod->nents) 834 goto out; 835 836 if (is_pci_p2pdma_page(sg_page(iod->sg))) 837 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 838 rq_dma_dir(req)); 839 else 840 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 841 rq_dma_dir(req), DMA_ATTR_NO_WARN); 842 if (!nr_mapped) 843 goto out; 844 845 iod->use_sgl = nvme_pci_use_sgls(dev, req); 846 if (iod->use_sgl) 847 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 848 else 849 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 850 out: 851 if (ret != BLK_STS_OK) 852 nvme_unmap_data(dev, req); 853 return ret; 854 } 855 856 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 857 struct nvme_command *cmnd) 858 { 859 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 860 861 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 862 rq_dma_dir(req), 0); 863 if (dma_mapping_error(dev->dev, iod->meta_dma)) 864 return BLK_STS_IOERR; 865 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 866 return 0; 867 } 868 869 /* 870 * NOTE: ns is NULL when called on the admin queue. 871 */ 872 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 873 const struct blk_mq_queue_data *bd) 874 { 875 struct nvme_ns *ns = hctx->queue->queuedata; 876 struct nvme_queue *nvmeq = hctx->driver_data; 877 struct nvme_dev *dev = nvmeq->dev; 878 struct request *req = bd->rq; 879 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 880 struct nvme_command cmnd; 881 blk_status_t ret; 882 883 iod->aborted = 0; 884 iod->npages = -1; 885 iod->nents = 0; 886 887 /* 888 * We should not need to do this, but we're still using this to 889 * ensure we can drain requests on a dying queue. 890 */ 891 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 892 return BLK_STS_IOERR; 893 894 ret = nvme_setup_cmd(ns, req, &cmnd); 895 if (ret) 896 return ret; 897 898 if (blk_rq_nr_phys_segments(req)) { 899 ret = nvme_map_data(dev, req, &cmnd); 900 if (ret) 901 goto out_free_cmd; 902 } 903 904 if (blk_integrity_rq(req)) { 905 ret = nvme_map_metadata(dev, req, &cmnd); 906 if (ret) 907 goto out_unmap_data; 908 } 909 910 blk_mq_start_request(req); 911 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 912 return BLK_STS_OK; 913 out_unmap_data: 914 nvme_unmap_data(dev, req); 915 out_free_cmd: 916 nvme_cleanup_cmd(req); 917 return ret; 918 } 919 920 static void nvme_pci_complete_rq(struct request *req) 921 { 922 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 923 struct nvme_dev *dev = iod->nvmeq->dev; 924 925 nvme_cleanup_cmd(req); 926 if (blk_integrity_rq(req)) 927 dma_unmap_page(dev->dev, iod->meta_dma, 928 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 929 if (blk_rq_nr_phys_segments(req)) 930 nvme_unmap_data(dev, req); 931 nvme_complete_rq(req); 932 } 933 934 /* We read the CQE phase first to check if the rest of the entry is valid */ 935 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 936 { 937 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 938 nvmeq->cq_phase; 939 } 940 941 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 942 { 943 u16 head = nvmeq->cq_head; 944 945 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 946 nvmeq->dbbuf_cq_ei)) 947 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 948 } 949 950 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 951 { 952 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 953 struct request *req; 954 955 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 956 dev_warn(nvmeq->dev->ctrl.device, 957 "invalid id %d completed on queue %d\n", 958 cqe->command_id, le16_to_cpu(cqe->sq_id)); 959 return; 960 } 961 962 /* 963 * AEN requests are special as they don't time out and can 964 * survive any kind of queue freeze and often don't respond to 965 * aborts. We don't even bother to allocate a struct request 966 * for them but rather special case them here. 967 */ 968 if (unlikely(nvmeq->qid == 0 && 969 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 970 nvme_complete_async_event(&nvmeq->dev->ctrl, 971 cqe->status, &cqe->result); 972 return; 973 } 974 975 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 976 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 977 nvme_end_request(req, cqe->status, cqe->result); 978 } 979 980 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 981 { 982 while (start != end) { 983 nvme_handle_cqe(nvmeq, start); 984 if (++start == nvmeq->q_depth) 985 start = 0; 986 } 987 } 988 989 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 990 { 991 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 992 nvmeq->cq_head = 0; 993 nvmeq->cq_phase = !nvmeq->cq_phase; 994 } else { 995 nvmeq->cq_head++; 996 } 997 } 998 999 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 1000 u16 *end, unsigned int tag) 1001 { 1002 int found = 0; 1003 1004 *start = nvmeq->cq_head; 1005 while (nvme_cqe_pending(nvmeq)) { 1006 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1007 found++; 1008 nvme_update_cq_head(nvmeq); 1009 } 1010 *end = nvmeq->cq_head; 1011 1012 if (*start != *end) 1013 nvme_ring_cq_doorbell(nvmeq); 1014 return found; 1015 } 1016 1017 static irqreturn_t nvme_irq(int irq, void *data) 1018 { 1019 struct nvme_queue *nvmeq = data; 1020 irqreturn_t ret = IRQ_NONE; 1021 u16 start, end; 1022 1023 /* 1024 * The rmb/wmb pair ensures we see all updates from a previous run of 1025 * the irq handler, even if that was on another CPU. 1026 */ 1027 rmb(); 1028 if (nvmeq->cq_head != nvmeq->last_cq_head) 1029 ret = IRQ_HANDLED; 1030 nvme_process_cq(nvmeq, &start, &end, -1); 1031 nvmeq->last_cq_head = nvmeq->cq_head; 1032 wmb(); 1033 1034 if (start != end) { 1035 nvme_complete_cqes(nvmeq, start, end); 1036 return IRQ_HANDLED; 1037 } 1038 1039 return ret; 1040 } 1041 1042 static irqreturn_t nvme_irq_check(int irq, void *data) 1043 { 1044 struct nvme_queue *nvmeq = data; 1045 if (nvme_cqe_pending(nvmeq)) 1046 return IRQ_WAKE_THREAD; 1047 return IRQ_NONE; 1048 } 1049 1050 /* 1051 * Poll for completions any queue, including those not dedicated to polling. 1052 * Can be called from any context. 1053 */ 1054 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1055 { 1056 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1057 u16 start, end; 1058 int found; 1059 1060 /* 1061 * For a poll queue we need to protect against the polling thread 1062 * using the CQ lock. For normal interrupt driven threads we have 1063 * to disable the interrupt to avoid racing with it. 1064 */ 1065 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1066 spin_lock(&nvmeq->cq_poll_lock); 1067 found = nvme_process_cq(nvmeq, &start, &end, tag); 1068 spin_unlock(&nvmeq->cq_poll_lock); 1069 } else { 1070 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1071 found = nvme_process_cq(nvmeq, &start, &end, tag); 1072 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1073 } 1074 1075 nvme_complete_cqes(nvmeq, start, end); 1076 return found; 1077 } 1078 1079 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1080 { 1081 struct nvme_queue *nvmeq = hctx->driver_data; 1082 u16 start, end; 1083 bool found; 1084 1085 if (!nvme_cqe_pending(nvmeq)) 1086 return 0; 1087 1088 spin_lock(&nvmeq->cq_poll_lock); 1089 found = nvme_process_cq(nvmeq, &start, &end, -1); 1090 spin_unlock(&nvmeq->cq_poll_lock); 1091 1092 nvme_complete_cqes(nvmeq, start, end); 1093 return found; 1094 } 1095 1096 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1097 { 1098 struct nvme_dev *dev = to_nvme_dev(ctrl); 1099 struct nvme_queue *nvmeq = &dev->queues[0]; 1100 struct nvme_command c; 1101 1102 memset(&c, 0, sizeof(c)); 1103 c.common.opcode = nvme_admin_async_event; 1104 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1105 nvme_submit_cmd(nvmeq, &c, true); 1106 } 1107 1108 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1109 { 1110 struct nvme_command c; 1111 1112 memset(&c, 0, sizeof(c)); 1113 c.delete_queue.opcode = opcode; 1114 c.delete_queue.qid = cpu_to_le16(id); 1115 1116 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1117 } 1118 1119 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1120 struct nvme_queue *nvmeq, s16 vector) 1121 { 1122 struct nvme_command c; 1123 int flags = NVME_QUEUE_PHYS_CONTIG; 1124 1125 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1126 flags |= NVME_CQ_IRQ_ENABLED; 1127 1128 /* 1129 * Note: we (ab)use the fact that the prp fields survive if no data 1130 * is attached to the request. 1131 */ 1132 memset(&c, 0, sizeof(c)); 1133 c.create_cq.opcode = nvme_admin_create_cq; 1134 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1135 c.create_cq.cqid = cpu_to_le16(qid); 1136 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1137 c.create_cq.cq_flags = cpu_to_le16(flags); 1138 c.create_cq.irq_vector = cpu_to_le16(vector); 1139 1140 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1141 } 1142 1143 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1144 struct nvme_queue *nvmeq) 1145 { 1146 struct nvme_ctrl *ctrl = &dev->ctrl; 1147 struct nvme_command c; 1148 int flags = NVME_QUEUE_PHYS_CONTIG; 1149 1150 /* 1151 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1152 * set. Since URGENT priority is zeroes, it makes all queues 1153 * URGENT. 1154 */ 1155 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1156 flags |= NVME_SQ_PRIO_MEDIUM; 1157 1158 /* 1159 * Note: we (ab)use the fact that the prp fields survive if no data 1160 * is attached to the request. 1161 */ 1162 memset(&c, 0, sizeof(c)); 1163 c.create_sq.opcode = nvme_admin_create_sq; 1164 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1165 c.create_sq.sqid = cpu_to_le16(qid); 1166 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1167 c.create_sq.sq_flags = cpu_to_le16(flags); 1168 c.create_sq.cqid = cpu_to_le16(qid); 1169 1170 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1171 } 1172 1173 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1174 { 1175 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1176 } 1177 1178 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1179 { 1180 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1181 } 1182 1183 static void abort_endio(struct request *req, blk_status_t error) 1184 { 1185 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1186 struct nvme_queue *nvmeq = iod->nvmeq; 1187 1188 dev_warn(nvmeq->dev->ctrl.device, 1189 "Abort status: 0x%x", nvme_req(req)->status); 1190 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1191 blk_mq_free_request(req); 1192 } 1193 1194 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1195 { 1196 1197 /* If true, indicates loss of adapter communication, possibly by a 1198 * NVMe Subsystem reset. 1199 */ 1200 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1201 1202 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1203 switch (dev->ctrl.state) { 1204 case NVME_CTRL_RESETTING: 1205 case NVME_CTRL_CONNECTING: 1206 return false; 1207 default: 1208 break; 1209 } 1210 1211 /* We shouldn't reset unless the controller is on fatal error state 1212 * _or_ if we lost the communication with it. 1213 */ 1214 if (!(csts & NVME_CSTS_CFS) && !nssro) 1215 return false; 1216 1217 return true; 1218 } 1219 1220 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1221 { 1222 /* Read a config register to help see what died. */ 1223 u16 pci_status; 1224 int result; 1225 1226 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1227 &pci_status); 1228 if (result == PCIBIOS_SUCCESSFUL) 1229 dev_warn(dev->ctrl.device, 1230 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1231 csts, pci_status); 1232 else 1233 dev_warn(dev->ctrl.device, 1234 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1235 csts, result); 1236 } 1237 1238 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1239 { 1240 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1241 struct nvme_queue *nvmeq = iod->nvmeq; 1242 struct nvme_dev *dev = nvmeq->dev; 1243 struct request *abort_req; 1244 struct nvme_command cmd; 1245 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1246 1247 /* If PCI error recovery process is happening, we cannot reset or 1248 * the recovery mechanism will surely fail. 1249 */ 1250 mb(); 1251 if (pci_channel_offline(to_pci_dev(dev->dev))) 1252 return BLK_EH_RESET_TIMER; 1253 1254 /* 1255 * Reset immediately if the controller is failed 1256 */ 1257 if (nvme_should_reset(dev, csts)) { 1258 nvme_warn_reset(dev, csts); 1259 nvme_dev_disable(dev, false); 1260 nvme_reset_ctrl(&dev->ctrl); 1261 return BLK_EH_DONE; 1262 } 1263 1264 /* 1265 * Did we miss an interrupt? 1266 */ 1267 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1268 dev_warn(dev->ctrl.device, 1269 "I/O %d QID %d timeout, completion polled\n", 1270 req->tag, nvmeq->qid); 1271 return BLK_EH_DONE; 1272 } 1273 1274 /* 1275 * Shutdown immediately if controller times out while starting. The 1276 * reset work will see the pci device disabled when it gets the forced 1277 * cancellation error. All outstanding requests are completed on 1278 * shutdown, so we return BLK_EH_DONE. 1279 */ 1280 switch (dev->ctrl.state) { 1281 case NVME_CTRL_CONNECTING: 1282 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1283 /* fall through */ 1284 case NVME_CTRL_DELETING: 1285 dev_warn_ratelimited(dev->ctrl.device, 1286 "I/O %d QID %d timeout, disable controller\n", 1287 req->tag, nvmeq->qid); 1288 nvme_dev_disable(dev, true); 1289 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1290 return BLK_EH_DONE; 1291 case NVME_CTRL_RESETTING: 1292 return BLK_EH_RESET_TIMER; 1293 default: 1294 break; 1295 } 1296 1297 /* 1298 * Shutdown the controller immediately and schedule a reset if the 1299 * command was already aborted once before and still hasn't been 1300 * returned to the driver, or if this is the admin queue. 1301 */ 1302 if (!nvmeq->qid || iod->aborted) { 1303 dev_warn(dev->ctrl.device, 1304 "I/O %d QID %d timeout, reset controller\n", 1305 req->tag, nvmeq->qid); 1306 nvme_dev_disable(dev, false); 1307 nvme_reset_ctrl(&dev->ctrl); 1308 1309 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1310 return BLK_EH_DONE; 1311 } 1312 1313 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1314 atomic_inc(&dev->ctrl.abort_limit); 1315 return BLK_EH_RESET_TIMER; 1316 } 1317 iod->aborted = 1; 1318 1319 memset(&cmd, 0, sizeof(cmd)); 1320 cmd.abort.opcode = nvme_admin_abort_cmd; 1321 cmd.abort.cid = req->tag; 1322 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1323 1324 dev_warn(nvmeq->dev->ctrl.device, 1325 "I/O %d QID %d timeout, aborting\n", 1326 req->tag, nvmeq->qid); 1327 1328 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1329 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1330 if (IS_ERR(abort_req)) { 1331 atomic_inc(&dev->ctrl.abort_limit); 1332 return BLK_EH_RESET_TIMER; 1333 } 1334 1335 abort_req->timeout = ADMIN_TIMEOUT; 1336 abort_req->end_io_data = NULL; 1337 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1338 1339 /* 1340 * The aborted req will be completed on receiving the abort req. 1341 * We enable the timer again. If hit twice, it'll cause a device reset, 1342 * as the device then is in a faulty state. 1343 */ 1344 return BLK_EH_RESET_TIMER; 1345 } 1346 1347 static void nvme_free_queue(struct nvme_queue *nvmeq) 1348 { 1349 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1350 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1351 if (!nvmeq->sq_cmds) 1352 return; 1353 1354 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1355 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1356 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1357 } else { 1358 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1359 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1360 } 1361 } 1362 1363 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1364 { 1365 int i; 1366 1367 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1368 dev->ctrl.queue_count--; 1369 nvme_free_queue(&dev->queues[i]); 1370 } 1371 } 1372 1373 /** 1374 * nvme_suspend_queue - put queue into suspended state 1375 * @nvmeq: queue to suspend 1376 */ 1377 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1378 { 1379 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1380 return 1; 1381 1382 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1383 mb(); 1384 1385 nvmeq->dev->online_queues--; 1386 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1387 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1388 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1389 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1390 return 0; 1391 } 1392 1393 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1394 { 1395 int i; 1396 1397 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1398 nvme_suspend_queue(&dev->queues[i]); 1399 } 1400 1401 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1402 { 1403 struct nvme_queue *nvmeq = &dev->queues[0]; 1404 1405 if (shutdown) 1406 nvme_shutdown_ctrl(&dev->ctrl); 1407 else 1408 nvme_disable_ctrl(&dev->ctrl); 1409 1410 nvme_poll_irqdisable(nvmeq, -1); 1411 } 1412 1413 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1414 int entry_size) 1415 { 1416 int q_depth = dev->q_depth; 1417 unsigned q_size_aligned = roundup(q_depth * entry_size, 1418 dev->ctrl.page_size); 1419 1420 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1421 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1422 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1423 q_depth = div_u64(mem_per_q, entry_size); 1424 1425 /* 1426 * Ensure the reduced q_depth is above some threshold where it 1427 * would be better to map queues in system memory with the 1428 * original depth 1429 */ 1430 if (q_depth < 64) 1431 return -ENOMEM; 1432 } 1433 1434 return q_depth; 1435 } 1436 1437 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1438 int qid) 1439 { 1440 struct pci_dev *pdev = to_pci_dev(dev->dev); 1441 1442 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1443 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1444 if (nvmeq->sq_cmds) { 1445 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1446 nvmeq->sq_cmds); 1447 if (nvmeq->sq_dma_addr) { 1448 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1449 return 0; 1450 } 1451 1452 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1453 } 1454 } 1455 1456 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1457 &nvmeq->sq_dma_addr, GFP_KERNEL); 1458 if (!nvmeq->sq_cmds) 1459 return -ENOMEM; 1460 return 0; 1461 } 1462 1463 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1464 { 1465 struct nvme_queue *nvmeq = &dev->queues[qid]; 1466 1467 if (dev->ctrl.queue_count > qid) 1468 return 0; 1469 1470 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1471 nvmeq->q_depth = depth; 1472 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1473 &nvmeq->cq_dma_addr, GFP_KERNEL); 1474 if (!nvmeq->cqes) 1475 goto free_nvmeq; 1476 1477 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1478 goto free_cqdma; 1479 1480 nvmeq->dev = dev; 1481 spin_lock_init(&nvmeq->sq_lock); 1482 spin_lock_init(&nvmeq->cq_poll_lock); 1483 nvmeq->cq_head = 0; 1484 nvmeq->cq_phase = 1; 1485 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1486 nvmeq->qid = qid; 1487 dev->ctrl.queue_count++; 1488 1489 return 0; 1490 1491 free_cqdma: 1492 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1493 nvmeq->cq_dma_addr); 1494 free_nvmeq: 1495 return -ENOMEM; 1496 } 1497 1498 static int queue_request_irq(struct nvme_queue *nvmeq) 1499 { 1500 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1501 int nr = nvmeq->dev->ctrl.instance; 1502 1503 if (use_threaded_interrupts) { 1504 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1505 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1506 } else { 1507 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1508 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1509 } 1510 } 1511 1512 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1513 { 1514 struct nvme_dev *dev = nvmeq->dev; 1515 1516 nvmeq->sq_tail = 0; 1517 nvmeq->last_sq_tail = 0; 1518 nvmeq->cq_head = 0; 1519 nvmeq->cq_phase = 1; 1520 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1521 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1522 nvme_dbbuf_init(dev, nvmeq, qid); 1523 dev->online_queues++; 1524 wmb(); /* ensure the first interrupt sees the initialization */ 1525 } 1526 1527 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1528 { 1529 struct nvme_dev *dev = nvmeq->dev; 1530 int result; 1531 u16 vector = 0; 1532 1533 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1534 1535 /* 1536 * A queue's vector matches the queue identifier unless the controller 1537 * has only one vector available. 1538 */ 1539 if (!polled) 1540 vector = dev->num_vecs == 1 ? 0 : qid; 1541 else 1542 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1543 1544 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1545 if (result) 1546 return result; 1547 1548 result = adapter_alloc_sq(dev, qid, nvmeq); 1549 if (result < 0) 1550 return result; 1551 else if (result) 1552 goto release_cq; 1553 1554 nvmeq->cq_vector = vector; 1555 nvme_init_queue(nvmeq, qid); 1556 1557 if (!polled) { 1558 result = queue_request_irq(nvmeq); 1559 if (result < 0) 1560 goto release_sq; 1561 } 1562 1563 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1564 return result; 1565 1566 release_sq: 1567 dev->online_queues--; 1568 adapter_delete_sq(dev, qid); 1569 release_cq: 1570 adapter_delete_cq(dev, qid); 1571 return result; 1572 } 1573 1574 static const struct blk_mq_ops nvme_mq_admin_ops = { 1575 .queue_rq = nvme_queue_rq, 1576 .complete = nvme_pci_complete_rq, 1577 .init_hctx = nvme_admin_init_hctx, 1578 .exit_hctx = nvme_admin_exit_hctx, 1579 .init_request = nvme_init_request, 1580 .timeout = nvme_timeout, 1581 }; 1582 1583 static const struct blk_mq_ops nvme_mq_ops = { 1584 .queue_rq = nvme_queue_rq, 1585 .complete = nvme_pci_complete_rq, 1586 .commit_rqs = nvme_commit_rqs, 1587 .init_hctx = nvme_init_hctx, 1588 .init_request = nvme_init_request, 1589 .map_queues = nvme_pci_map_queues, 1590 .timeout = nvme_timeout, 1591 .poll = nvme_poll, 1592 }; 1593 1594 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1595 { 1596 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1597 /* 1598 * If the controller was reset during removal, it's possible 1599 * user requests may be waiting on a stopped queue. Start the 1600 * queue to flush these to completion. 1601 */ 1602 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1603 blk_cleanup_queue(dev->ctrl.admin_q); 1604 blk_mq_free_tag_set(&dev->admin_tagset); 1605 } 1606 } 1607 1608 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1609 { 1610 if (!dev->ctrl.admin_q) { 1611 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1612 dev->admin_tagset.nr_hw_queues = 1; 1613 1614 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1615 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1616 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1617 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1618 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1619 dev->admin_tagset.driver_data = dev; 1620 1621 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1622 return -ENOMEM; 1623 dev->ctrl.admin_tagset = &dev->admin_tagset; 1624 1625 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1626 if (IS_ERR(dev->ctrl.admin_q)) { 1627 blk_mq_free_tag_set(&dev->admin_tagset); 1628 return -ENOMEM; 1629 } 1630 if (!blk_get_queue(dev->ctrl.admin_q)) { 1631 nvme_dev_remove_admin(dev); 1632 dev->ctrl.admin_q = NULL; 1633 return -ENODEV; 1634 } 1635 } else 1636 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1637 1638 return 0; 1639 } 1640 1641 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1642 { 1643 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1644 } 1645 1646 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1647 { 1648 struct pci_dev *pdev = to_pci_dev(dev->dev); 1649 1650 if (size <= dev->bar_mapped_size) 1651 return 0; 1652 if (size > pci_resource_len(pdev, 0)) 1653 return -ENOMEM; 1654 if (dev->bar) 1655 iounmap(dev->bar); 1656 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1657 if (!dev->bar) { 1658 dev->bar_mapped_size = 0; 1659 return -ENOMEM; 1660 } 1661 dev->bar_mapped_size = size; 1662 dev->dbs = dev->bar + NVME_REG_DBS; 1663 1664 return 0; 1665 } 1666 1667 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1668 { 1669 int result; 1670 u32 aqa; 1671 struct nvme_queue *nvmeq; 1672 1673 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1674 if (result < 0) 1675 return result; 1676 1677 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1678 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1679 1680 if (dev->subsystem && 1681 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1682 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1683 1684 result = nvme_disable_ctrl(&dev->ctrl); 1685 if (result < 0) 1686 return result; 1687 1688 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1689 if (result) 1690 return result; 1691 1692 nvmeq = &dev->queues[0]; 1693 aqa = nvmeq->q_depth - 1; 1694 aqa |= aqa << 16; 1695 1696 writel(aqa, dev->bar + NVME_REG_AQA); 1697 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1698 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1699 1700 result = nvme_enable_ctrl(&dev->ctrl); 1701 if (result) 1702 return result; 1703 1704 nvmeq->cq_vector = 0; 1705 nvme_init_queue(nvmeq, 0); 1706 result = queue_request_irq(nvmeq); 1707 if (result) { 1708 dev->online_queues--; 1709 return result; 1710 } 1711 1712 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1713 return result; 1714 } 1715 1716 static int nvme_create_io_queues(struct nvme_dev *dev) 1717 { 1718 unsigned i, max, rw_queues; 1719 int ret = 0; 1720 1721 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1722 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1723 ret = -ENOMEM; 1724 break; 1725 } 1726 } 1727 1728 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1729 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1730 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1731 dev->io_queues[HCTX_TYPE_READ]; 1732 } else { 1733 rw_queues = max; 1734 } 1735 1736 for (i = dev->online_queues; i <= max; i++) { 1737 bool polled = i > rw_queues; 1738 1739 ret = nvme_create_queue(&dev->queues[i], i, polled); 1740 if (ret) 1741 break; 1742 } 1743 1744 /* 1745 * Ignore failing Create SQ/CQ commands, we can continue with less 1746 * than the desired amount of queues, and even a controller without 1747 * I/O queues can still be used to issue admin commands. This might 1748 * be useful to upgrade a buggy firmware for example. 1749 */ 1750 return ret >= 0 ? 0 : ret; 1751 } 1752 1753 static ssize_t nvme_cmb_show(struct device *dev, 1754 struct device_attribute *attr, 1755 char *buf) 1756 { 1757 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1758 1759 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1760 ndev->cmbloc, ndev->cmbsz); 1761 } 1762 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1763 1764 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1765 { 1766 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1767 1768 return 1ULL << (12 + 4 * szu); 1769 } 1770 1771 static u32 nvme_cmb_size(struct nvme_dev *dev) 1772 { 1773 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1774 } 1775 1776 static void nvme_map_cmb(struct nvme_dev *dev) 1777 { 1778 u64 size, offset; 1779 resource_size_t bar_size; 1780 struct pci_dev *pdev = to_pci_dev(dev->dev); 1781 int bar; 1782 1783 if (dev->cmb_size) 1784 return; 1785 1786 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1787 if (!dev->cmbsz) 1788 return; 1789 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1790 1791 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1792 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1793 bar = NVME_CMB_BIR(dev->cmbloc); 1794 bar_size = pci_resource_len(pdev, bar); 1795 1796 if (offset > bar_size) 1797 return; 1798 1799 /* 1800 * Controllers may support a CMB size larger than their BAR, 1801 * for example, due to being behind a bridge. Reduce the CMB to 1802 * the reported size of the BAR 1803 */ 1804 if (size > bar_size - offset) 1805 size = bar_size - offset; 1806 1807 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1808 dev_warn(dev->ctrl.device, 1809 "failed to register the CMB\n"); 1810 return; 1811 } 1812 1813 dev->cmb_size = size; 1814 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1815 1816 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1817 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1818 pci_p2pmem_publish(pdev, true); 1819 1820 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1821 &dev_attr_cmb.attr, NULL)) 1822 dev_warn(dev->ctrl.device, 1823 "failed to add sysfs attribute for CMB\n"); 1824 } 1825 1826 static inline void nvme_release_cmb(struct nvme_dev *dev) 1827 { 1828 if (dev->cmb_size) { 1829 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1830 &dev_attr_cmb.attr, NULL); 1831 dev->cmb_size = 0; 1832 } 1833 } 1834 1835 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1836 { 1837 u64 dma_addr = dev->host_mem_descs_dma; 1838 struct nvme_command c; 1839 int ret; 1840 1841 memset(&c, 0, sizeof(c)); 1842 c.features.opcode = nvme_admin_set_features; 1843 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1844 c.features.dword11 = cpu_to_le32(bits); 1845 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1846 ilog2(dev->ctrl.page_size)); 1847 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1848 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1849 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1850 1851 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1852 if (ret) { 1853 dev_warn(dev->ctrl.device, 1854 "failed to set host mem (err %d, flags %#x).\n", 1855 ret, bits); 1856 } 1857 return ret; 1858 } 1859 1860 static void nvme_free_host_mem(struct nvme_dev *dev) 1861 { 1862 int i; 1863 1864 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1865 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1866 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1867 1868 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1869 le64_to_cpu(desc->addr), 1870 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1871 } 1872 1873 kfree(dev->host_mem_desc_bufs); 1874 dev->host_mem_desc_bufs = NULL; 1875 dma_free_coherent(dev->dev, 1876 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1877 dev->host_mem_descs, dev->host_mem_descs_dma); 1878 dev->host_mem_descs = NULL; 1879 dev->nr_host_mem_descs = 0; 1880 } 1881 1882 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1883 u32 chunk_size) 1884 { 1885 struct nvme_host_mem_buf_desc *descs; 1886 u32 max_entries, len; 1887 dma_addr_t descs_dma; 1888 int i = 0; 1889 void **bufs; 1890 u64 size, tmp; 1891 1892 tmp = (preferred + chunk_size - 1); 1893 do_div(tmp, chunk_size); 1894 max_entries = tmp; 1895 1896 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1897 max_entries = dev->ctrl.hmmaxd; 1898 1899 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1900 &descs_dma, GFP_KERNEL); 1901 if (!descs) 1902 goto out; 1903 1904 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1905 if (!bufs) 1906 goto out_free_descs; 1907 1908 for (size = 0; size < preferred && i < max_entries; size += len) { 1909 dma_addr_t dma_addr; 1910 1911 len = min_t(u64, chunk_size, preferred - size); 1912 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1913 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1914 if (!bufs[i]) 1915 break; 1916 1917 descs[i].addr = cpu_to_le64(dma_addr); 1918 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1919 i++; 1920 } 1921 1922 if (!size) 1923 goto out_free_bufs; 1924 1925 dev->nr_host_mem_descs = i; 1926 dev->host_mem_size = size; 1927 dev->host_mem_descs = descs; 1928 dev->host_mem_descs_dma = descs_dma; 1929 dev->host_mem_desc_bufs = bufs; 1930 return 0; 1931 1932 out_free_bufs: 1933 while (--i >= 0) { 1934 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1935 1936 dma_free_attrs(dev->dev, size, bufs[i], 1937 le64_to_cpu(descs[i].addr), 1938 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1939 } 1940 1941 kfree(bufs); 1942 out_free_descs: 1943 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1944 descs_dma); 1945 out: 1946 dev->host_mem_descs = NULL; 1947 return -ENOMEM; 1948 } 1949 1950 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1951 { 1952 u32 chunk_size; 1953 1954 /* start big and work our way down */ 1955 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1956 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1957 chunk_size /= 2) { 1958 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1959 if (!min || dev->host_mem_size >= min) 1960 return 0; 1961 nvme_free_host_mem(dev); 1962 } 1963 } 1964 1965 return -ENOMEM; 1966 } 1967 1968 static int nvme_setup_host_mem(struct nvme_dev *dev) 1969 { 1970 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1971 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1972 u64 min = (u64)dev->ctrl.hmmin * 4096; 1973 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1974 int ret; 1975 1976 preferred = min(preferred, max); 1977 if (min > max) { 1978 dev_warn(dev->ctrl.device, 1979 "min host memory (%lld MiB) above limit (%d MiB).\n", 1980 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1981 nvme_free_host_mem(dev); 1982 return 0; 1983 } 1984 1985 /* 1986 * If we already have a buffer allocated check if we can reuse it. 1987 */ 1988 if (dev->host_mem_descs) { 1989 if (dev->host_mem_size >= min) 1990 enable_bits |= NVME_HOST_MEM_RETURN; 1991 else 1992 nvme_free_host_mem(dev); 1993 } 1994 1995 if (!dev->host_mem_descs) { 1996 if (nvme_alloc_host_mem(dev, min, preferred)) { 1997 dev_warn(dev->ctrl.device, 1998 "failed to allocate host memory buffer.\n"); 1999 return 0; /* controller must work without HMB */ 2000 } 2001 2002 dev_info(dev->ctrl.device, 2003 "allocated %lld MiB host memory buffer.\n", 2004 dev->host_mem_size >> ilog2(SZ_1M)); 2005 } 2006 2007 ret = nvme_set_host_mem(dev, enable_bits); 2008 if (ret) 2009 nvme_free_host_mem(dev); 2010 return ret; 2011 } 2012 2013 /* 2014 * nirqs is the number of interrupts available for write and read 2015 * queues. The core already reserved an interrupt for the admin queue. 2016 */ 2017 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2018 { 2019 struct nvme_dev *dev = affd->priv; 2020 unsigned int nr_read_queues; 2021 2022 /* 2023 * If there is no interupt available for queues, ensure that 2024 * the default queue is set to 1. The affinity set size is 2025 * also set to one, but the irq core ignores it for this case. 2026 * 2027 * If only one interrupt is available or 'write_queue' == 0, combine 2028 * write and read queues. 2029 * 2030 * If 'write_queues' > 0, ensure it leaves room for at least one read 2031 * queue. 2032 */ 2033 if (!nrirqs) { 2034 nrirqs = 1; 2035 nr_read_queues = 0; 2036 } else if (nrirqs == 1 || !write_queues) { 2037 nr_read_queues = 0; 2038 } else if (write_queues >= nrirqs) { 2039 nr_read_queues = 1; 2040 } else { 2041 nr_read_queues = nrirqs - write_queues; 2042 } 2043 2044 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2045 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2046 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2047 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2048 affd->nr_sets = nr_read_queues ? 2 : 1; 2049 } 2050 2051 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2052 { 2053 struct pci_dev *pdev = to_pci_dev(dev->dev); 2054 struct irq_affinity affd = { 2055 .pre_vectors = 1, 2056 .calc_sets = nvme_calc_irq_sets, 2057 .priv = dev, 2058 }; 2059 unsigned int irq_queues, this_p_queues; 2060 unsigned int nr_cpus = num_possible_cpus(); 2061 2062 /* 2063 * Poll queues don't need interrupts, but we need at least one IO 2064 * queue left over for non-polled IO. 2065 */ 2066 this_p_queues = poll_queues; 2067 if (this_p_queues >= nr_io_queues) { 2068 this_p_queues = nr_io_queues - 1; 2069 irq_queues = 1; 2070 } else { 2071 if (nr_cpus < nr_io_queues - this_p_queues) 2072 irq_queues = nr_cpus + 1; 2073 else 2074 irq_queues = nr_io_queues - this_p_queues + 1; 2075 } 2076 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2077 2078 /* Initialize for the single interrupt case */ 2079 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2080 dev->io_queues[HCTX_TYPE_READ] = 0; 2081 2082 /* 2083 * Some Apple controllers require all queues to use the 2084 * first vector. 2085 */ 2086 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2087 irq_queues = 1; 2088 2089 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2090 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2091 } 2092 2093 static void nvme_disable_io_queues(struct nvme_dev *dev) 2094 { 2095 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2096 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2097 } 2098 2099 static int nvme_setup_io_queues(struct nvme_dev *dev) 2100 { 2101 struct nvme_queue *adminq = &dev->queues[0]; 2102 struct pci_dev *pdev = to_pci_dev(dev->dev); 2103 int result, nr_io_queues; 2104 unsigned long size; 2105 2106 nr_io_queues = max_io_queues(); 2107 2108 /* 2109 * If tags are shared with admin queue (Apple bug), then 2110 * make sure we only use one IO queue. 2111 */ 2112 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2113 nr_io_queues = 1; 2114 2115 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2116 if (result < 0) 2117 return result; 2118 2119 if (nr_io_queues == 0) 2120 return 0; 2121 2122 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2123 2124 if (dev->cmb_use_sqes) { 2125 result = nvme_cmb_qdepth(dev, nr_io_queues, 2126 sizeof(struct nvme_command)); 2127 if (result > 0) 2128 dev->q_depth = result; 2129 else 2130 dev->cmb_use_sqes = false; 2131 } 2132 2133 do { 2134 size = db_bar_size(dev, nr_io_queues); 2135 result = nvme_remap_bar(dev, size); 2136 if (!result) 2137 break; 2138 if (!--nr_io_queues) 2139 return -ENOMEM; 2140 } while (1); 2141 adminq->q_db = dev->dbs; 2142 2143 retry: 2144 /* Deregister the admin queue's interrupt */ 2145 pci_free_irq(pdev, 0, adminq); 2146 2147 /* 2148 * If we enable msix early due to not intx, disable it again before 2149 * setting up the full range we need. 2150 */ 2151 pci_free_irq_vectors(pdev); 2152 2153 result = nvme_setup_irqs(dev, nr_io_queues); 2154 if (result <= 0) 2155 return -EIO; 2156 2157 dev->num_vecs = result; 2158 result = max(result - 1, 1); 2159 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2160 2161 /* 2162 * Should investigate if there's a performance win from allocating 2163 * more queues than interrupt vectors; it might allow the submission 2164 * path to scale better, even if the receive path is limited by the 2165 * number of interrupts. 2166 */ 2167 result = queue_request_irq(adminq); 2168 if (result) 2169 return result; 2170 set_bit(NVMEQ_ENABLED, &adminq->flags); 2171 2172 result = nvme_create_io_queues(dev); 2173 if (result || dev->online_queues < 2) 2174 return result; 2175 2176 if (dev->online_queues - 1 < dev->max_qid) { 2177 nr_io_queues = dev->online_queues - 1; 2178 nvme_disable_io_queues(dev); 2179 nvme_suspend_io_queues(dev); 2180 goto retry; 2181 } 2182 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2183 dev->io_queues[HCTX_TYPE_DEFAULT], 2184 dev->io_queues[HCTX_TYPE_READ], 2185 dev->io_queues[HCTX_TYPE_POLL]); 2186 return 0; 2187 } 2188 2189 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2190 { 2191 struct nvme_queue *nvmeq = req->end_io_data; 2192 2193 blk_mq_free_request(req); 2194 complete(&nvmeq->delete_done); 2195 } 2196 2197 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2198 { 2199 struct nvme_queue *nvmeq = req->end_io_data; 2200 2201 if (error) 2202 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2203 2204 nvme_del_queue_end(req, error); 2205 } 2206 2207 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2208 { 2209 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2210 struct request *req; 2211 struct nvme_command cmd; 2212 2213 memset(&cmd, 0, sizeof(cmd)); 2214 cmd.delete_queue.opcode = opcode; 2215 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2216 2217 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2218 if (IS_ERR(req)) 2219 return PTR_ERR(req); 2220 2221 req->timeout = ADMIN_TIMEOUT; 2222 req->end_io_data = nvmeq; 2223 2224 init_completion(&nvmeq->delete_done); 2225 blk_execute_rq_nowait(q, NULL, req, false, 2226 opcode == nvme_admin_delete_cq ? 2227 nvme_del_cq_end : nvme_del_queue_end); 2228 return 0; 2229 } 2230 2231 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2232 { 2233 int nr_queues = dev->online_queues - 1, sent = 0; 2234 unsigned long timeout; 2235 2236 retry: 2237 timeout = ADMIN_TIMEOUT; 2238 while (nr_queues > 0) { 2239 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2240 break; 2241 nr_queues--; 2242 sent++; 2243 } 2244 while (sent) { 2245 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2246 2247 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2248 timeout); 2249 if (timeout == 0) 2250 return false; 2251 2252 /* handle any remaining CQEs */ 2253 if (opcode == nvme_admin_delete_cq && 2254 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2255 nvme_poll_irqdisable(nvmeq, -1); 2256 2257 sent--; 2258 if (nr_queues) 2259 goto retry; 2260 } 2261 return true; 2262 } 2263 2264 /* 2265 * return error value only when tagset allocation failed 2266 */ 2267 static int nvme_dev_add(struct nvme_dev *dev) 2268 { 2269 int ret; 2270 2271 if (!dev->ctrl.tagset) { 2272 dev->tagset.ops = &nvme_mq_ops; 2273 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2274 dev->tagset.nr_maps = 2; /* default + read */ 2275 if (dev->io_queues[HCTX_TYPE_POLL]) 2276 dev->tagset.nr_maps++; 2277 dev->tagset.timeout = NVME_IO_TIMEOUT; 2278 dev->tagset.numa_node = dev_to_node(dev->dev); 2279 dev->tagset.queue_depth = 2280 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2281 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2282 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2283 dev->tagset.driver_data = dev; 2284 2285 /* 2286 * Some Apple controllers requires tags to be unique 2287 * across admin and IO queue, so reserve the first 32 2288 * tags of the IO queue. 2289 */ 2290 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2291 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2292 2293 ret = blk_mq_alloc_tag_set(&dev->tagset); 2294 if (ret) { 2295 dev_warn(dev->ctrl.device, 2296 "IO queues tagset allocation failed %d\n", ret); 2297 return ret; 2298 } 2299 dev->ctrl.tagset = &dev->tagset; 2300 } else { 2301 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2302 2303 /* Free previously allocated queues that are no longer usable */ 2304 nvme_free_queues(dev, dev->online_queues); 2305 } 2306 2307 nvme_dbbuf_set(dev); 2308 return 0; 2309 } 2310 2311 static int nvme_pci_enable(struct nvme_dev *dev) 2312 { 2313 int result = -ENOMEM; 2314 struct pci_dev *pdev = to_pci_dev(dev->dev); 2315 2316 if (pci_enable_device_mem(pdev)) 2317 return result; 2318 2319 pci_set_master(pdev); 2320 2321 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2322 goto disable; 2323 2324 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2325 result = -ENODEV; 2326 goto disable; 2327 } 2328 2329 /* 2330 * Some devices and/or platforms don't advertise or work with INTx 2331 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2332 * adjust this later. 2333 */ 2334 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2335 if (result < 0) 2336 return result; 2337 2338 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2339 2340 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2341 io_queue_depth); 2342 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2343 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2344 dev->dbs = dev->bar + 4096; 2345 2346 /* 2347 * Some Apple controllers require a non-standard SQE size. 2348 * Interestingly they also seem to ignore the CC:IOSQES register 2349 * so we don't bother updating it here. 2350 */ 2351 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2352 dev->io_sqes = 7; 2353 else 2354 dev->io_sqes = NVME_NVM_IOSQES; 2355 2356 /* 2357 * Temporary fix for the Apple controller found in the MacBook8,1 and 2358 * some MacBook7,1 to avoid controller resets and data loss. 2359 */ 2360 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2361 dev->q_depth = 2; 2362 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2363 "set queue depth=%u to work around controller resets\n", 2364 dev->q_depth); 2365 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2366 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2367 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2368 dev->q_depth = 64; 2369 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2370 "set queue depth=%u\n", dev->q_depth); 2371 } 2372 2373 /* 2374 * Controllers with the shared tags quirk need the IO queue to be 2375 * big enough so that we get 32 tags for the admin queue 2376 */ 2377 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2378 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2379 dev->q_depth = NVME_AQ_DEPTH + 2; 2380 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2381 dev->q_depth); 2382 } 2383 2384 2385 nvme_map_cmb(dev); 2386 2387 pci_enable_pcie_error_reporting(pdev); 2388 pci_save_state(pdev); 2389 return 0; 2390 2391 disable: 2392 pci_disable_device(pdev); 2393 return result; 2394 } 2395 2396 static void nvme_dev_unmap(struct nvme_dev *dev) 2397 { 2398 if (dev->bar) 2399 iounmap(dev->bar); 2400 pci_release_mem_regions(to_pci_dev(dev->dev)); 2401 } 2402 2403 static void nvme_pci_disable(struct nvme_dev *dev) 2404 { 2405 struct pci_dev *pdev = to_pci_dev(dev->dev); 2406 2407 pci_free_irq_vectors(pdev); 2408 2409 if (pci_is_enabled(pdev)) { 2410 pci_disable_pcie_error_reporting(pdev); 2411 pci_disable_device(pdev); 2412 } 2413 } 2414 2415 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2416 { 2417 bool dead = true, freeze = false; 2418 struct pci_dev *pdev = to_pci_dev(dev->dev); 2419 2420 mutex_lock(&dev->shutdown_lock); 2421 if (pci_is_enabled(pdev)) { 2422 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2423 2424 if (dev->ctrl.state == NVME_CTRL_LIVE || 2425 dev->ctrl.state == NVME_CTRL_RESETTING) { 2426 freeze = true; 2427 nvme_start_freeze(&dev->ctrl); 2428 } 2429 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2430 pdev->error_state != pci_channel_io_normal); 2431 } 2432 2433 /* 2434 * Give the controller a chance to complete all entered requests if 2435 * doing a safe shutdown. 2436 */ 2437 if (!dead && shutdown && freeze) 2438 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2439 2440 nvme_stop_queues(&dev->ctrl); 2441 2442 if (!dead && dev->ctrl.queue_count > 0) { 2443 nvme_disable_io_queues(dev); 2444 nvme_disable_admin_queue(dev, shutdown); 2445 } 2446 nvme_suspend_io_queues(dev); 2447 nvme_suspend_queue(&dev->queues[0]); 2448 nvme_pci_disable(dev); 2449 2450 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2451 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2452 blk_mq_tagset_wait_completed_request(&dev->tagset); 2453 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2454 2455 /* 2456 * The driver will not be starting up queues again if shutting down so 2457 * must flush all entered requests to their failed completion to avoid 2458 * deadlocking blk-mq hot-cpu notifier. 2459 */ 2460 if (shutdown) { 2461 nvme_start_queues(&dev->ctrl); 2462 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2463 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2464 } 2465 mutex_unlock(&dev->shutdown_lock); 2466 } 2467 2468 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2469 { 2470 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2471 PAGE_SIZE, PAGE_SIZE, 0); 2472 if (!dev->prp_page_pool) 2473 return -ENOMEM; 2474 2475 /* Optimisation for I/Os between 4k and 128k */ 2476 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2477 256, 256, 0); 2478 if (!dev->prp_small_pool) { 2479 dma_pool_destroy(dev->prp_page_pool); 2480 return -ENOMEM; 2481 } 2482 return 0; 2483 } 2484 2485 static void nvme_release_prp_pools(struct nvme_dev *dev) 2486 { 2487 dma_pool_destroy(dev->prp_page_pool); 2488 dma_pool_destroy(dev->prp_small_pool); 2489 } 2490 2491 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2492 { 2493 struct nvme_dev *dev = to_nvme_dev(ctrl); 2494 2495 nvme_dbbuf_dma_free(dev); 2496 put_device(dev->dev); 2497 if (dev->tagset.tags) 2498 blk_mq_free_tag_set(&dev->tagset); 2499 if (dev->ctrl.admin_q) 2500 blk_put_queue(dev->ctrl.admin_q); 2501 kfree(dev->queues); 2502 free_opal_dev(dev->ctrl.opal_dev); 2503 mempool_destroy(dev->iod_mempool); 2504 kfree(dev); 2505 } 2506 2507 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2508 { 2509 nvme_get_ctrl(&dev->ctrl); 2510 nvme_dev_disable(dev, false); 2511 nvme_kill_queues(&dev->ctrl); 2512 if (!queue_work(nvme_wq, &dev->remove_work)) 2513 nvme_put_ctrl(&dev->ctrl); 2514 } 2515 2516 static void nvme_reset_work(struct work_struct *work) 2517 { 2518 struct nvme_dev *dev = 2519 container_of(work, struct nvme_dev, ctrl.reset_work); 2520 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2521 int result; 2522 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2523 2524 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2525 result = -ENODEV; 2526 goto out; 2527 } 2528 2529 /* 2530 * If we're called to reset a live controller first shut it down before 2531 * moving on. 2532 */ 2533 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2534 nvme_dev_disable(dev, false); 2535 nvme_sync_queues(&dev->ctrl); 2536 2537 mutex_lock(&dev->shutdown_lock); 2538 result = nvme_pci_enable(dev); 2539 if (result) 2540 goto out_unlock; 2541 2542 result = nvme_pci_configure_admin_queue(dev); 2543 if (result) 2544 goto out_unlock; 2545 2546 result = nvme_alloc_admin_tags(dev); 2547 if (result) 2548 goto out_unlock; 2549 2550 /* 2551 * Limit the max command size to prevent iod->sg allocations going 2552 * over a single page. 2553 */ 2554 dev->ctrl.max_hw_sectors = min_t(u32, 2555 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2556 dev->ctrl.max_segments = NVME_MAX_SEGS; 2557 2558 /* 2559 * Don't limit the IOMMU merged segment size. 2560 */ 2561 dma_set_max_seg_size(dev->dev, 0xffffffff); 2562 2563 mutex_unlock(&dev->shutdown_lock); 2564 2565 /* 2566 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2567 * initializing procedure here. 2568 */ 2569 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2570 dev_warn(dev->ctrl.device, 2571 "failed to mark controller CONNECTING\n"); 2572 result = -EBUSY; 2573 goto out; 2574 } 2575 2576 result = nvme_init_identify(&dev->ctrl); 2577 if (result) 2578 goto out; 2579 2580 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2581 if (!dev->ctrl.opal_dev) 2582 dev->ctrl.opal_dev = 2583 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2584 else if (was_suspend) 2585 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2586 } else { 2587 free_opal_dev(dev->ctrl.opal_dev); 2588 dev->ctrl.opal_dev = NULL; 2589 } 2590 2591 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2592 result = nvme_dbbuf_dma_alloc(dev); 2593 if (result) 2594 dev_warn(dev->dev, 2595 "unable to allocate dma for dbbuf\n"); 2596 } 2597 2598 if (dev->ctrl.hmpre) { 2599 result = nvme_setup_host_mem(dev); 2600 if (result < 0) 2601 goto out; 2602 } 2603 2604 result = nvme_setup_io_queues(dev); 2605 if (result) 2606 goto out; 2607 2608 /* 2609 * Keep the controller around but remove all namespaces if we don't have 2610 * any working I/O queue. 2611 */ 2612 if (dev->online_queues < 2) { 2613 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2614 nvme_kill_queues(&dev->ctrl); 2615 nvme_remove_namespaces(&dev->ctrl); 2616 new_state = NVME_CTRL_ADMIN_ONLY; 2617 } else { 2618 nvme_start_queues(&dev->ctrl); 2619 nvme_wait_freeze(&dev->ctrl); 2620 /* hit this only when allocate tagset fails */ 2621 if (nvme_dev_add(dev)) 2622 new_state = NVME_CTRL_ADMIN_ONLY; 2623 nvme_unfreeze(&dev->ctrl); 2624 } 2625 2626 /* 2627 * If only admin queue live, keep it to do further investigation or 2628 * recovery. 2629 */ 2630 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2631 dev_warn(dev->ctrl.device, 2632 "failed to mark controller state %d\n", new_state); 2633 result = -ENODEV; 2634 goto out; 2635 } 2636 2637 nvme_start_ctrl(&dev->ctrl); 2638 return; 2639 2640 out_unlock: 2641 mutex_unlock(&dev->shutdown_lock); 2642 out: 2643 if (result) 2644 dev_warn(dev->ctrl.device, 2645 "Removing after probe failure status: %d\n", result); 2646 nvme_remove_dead_ctrl(dev); 2647 } 2648 2649 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2650 { 2651 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2652 struct pci_dev *pdev = to_pci_dev(dev->dev); 2653 2654 if (pci_get_drvdata(pdev)) 2655 device_release_driver(&pdev->dev); 2656 nvme_put_ctrl(&dev->ctrl); 2657 } 2658 2659 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2660 { 2661 *val = readl(to_nvme_dev(ctrl)->bar + off); 2662 return 0; 2663 } 2664 2665 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2666 { 2667 writel(val, to_nvme_dev(ctrl)->bar + off); 2668 return 0; 2669 } 2670 2671 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2672 { 2673 *val = readq(to_nvme_dev(ctrl)->bar + off); 2674 return 0; 2675 } 2676 2677 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2678 { 2679 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2680 2681 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2682 } 2683 2684 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2685 .name = "pcie", 2686 .module = THIS_MODULE, 2687 .flags = NVME_F_METADATA_SUPPORTED | 2688 NVME_F_PCI_P2PDMA, 2689 .reg_read32 = nvme_pci_reg_read32, 2690 .reg_write32 = nvme_pci_reg_write32, 2691 .reg_read64 = nvme_pci_reg_read64, 2692 .free_ctrl = nvme_pci_free_ctrl, 2693 .submit_async_event = nvme_pci_submit_async_event, 2694 .get_address = nvme_pci_get_address, 2695 }; 2696 2697 static int nvme_dev_map(struct nvme_dev *dev) 2698 { 2699 struct pci_dev *pdev = to_pci_dev(dev->dev); 2700 2701 if (pci_request_mem_regions(pdev, "nvme")) 2702 return -ENODEV; 2703 2704 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2705 goto release; 2706 2707 return 0; 2708 release: 2709 pci_release_mem_regions(pdev); 2710 return -ENODEV; 2711 } 2712 2713 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2714 { 2715 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2716 /* 2717 * Several Samsung devices seem to drop off the PCIe bus 2718 * randomly when APST is on and uses the deepest sleep state. 2719 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2720 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2721 * 950 PRO 256GB", but it seems to be restricted to two Dell 2722 * laptops. 2723 */ 2724 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2725 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2726 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2727 return NVME_QUIRK_NO_DEEPEST_PS; 2728 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2729 /* 2730 * Samsung SSD 960 EVO drops off the PCIe bus after system 2731 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2732 * within few minutes after bootup on a Coffee Lake board - 2733 * ASUS PRIME Z370-A 2734 */ 2735 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2736 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2737 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2738 return NVME_QUIRK_NO_APST; 2739 } 2740 2741 return 0; 2742 } 2743 2744 static void nvme_async_probe(void *data, async_cookie_t cookie) 2745 { 2746 struct nvme_dev *dev = data; 2747 2748 flush_work(&dev->ctrl.reset_work); 2749 flush_work(&dev->ctrl.scan_work); 2750 nvme_put_ctrl(&dev->ctrl); 2751 } 2752 2753 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2754 { 2755 int node, result = -ENOMEM; 2756 struct nvme_dev *dev; 2757 unsigned long quirks = id->driver_data; 2758 size_t alloc_size; 2759 2760 node = dev_to_node(&pdev->dev); 2761 if (node == NUMA_NO_NODE) 2762 set_dev_node(&pdev->dev, first_memory_node); 2763 2764 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2765 if (!dev) 2766 return -ENOMEM; 2767 2768 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2769 GFP_KERNEL, node); 2770 if (!dev->queues) 2771 goto free; 2772 2773 dev->dev = get_device(&pdev->dev); 2774 pci_set_drvdata(pdev, dev); 2775 2776 result = nvme_dev_map(dev); 2777 if (result) 2778 goto put_pci; 2779 2780 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2781 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2782 mutex_init(&dev->shutdown_lock); 2783 2784 result = nvme_setup_prp_pools(dev); 2785 if (result) 2786 goto unmap; 2787 2788 quirks |= check_vendor_combination_bug(pdev); 2789 2790 /* 2791 * Double check that our mempool alloc size will cover the biggest 2792 * command we support. 2793 */ 2794 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2795 NVME_MAX_SEGS, true); 2796 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2797 2798 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2799 mempool_kfree, 2800 (void *) alloc_size, 2801 GFP_KERNEL, node); 2802 if (!dev->iod_mempool) { 2803 result = -ENOMEM; 2804 goto release_pools; 2805 } 2806 2807 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2808 quirks); 2809 if (result) 2810 goto release_mempool; 2811 2812 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2813 2814 nvme_reset_ctrl(&dev->ctrl); 2815 nvme_get_ctrl(&dev->ctrl); 2816 async_schedule(nvme_async_probe, dev); 2817 2818 return 0; 2819 2820 release_mempool: 2821 mempool_destroy(dev->iod_mempool); 2822 release_pools: 2823 nvme_release_prp_pools(dev); 2824 unmap: 2825 nvme_dev_unmap(dev); 2826 put_pci: 2827 put_device(dev->dev); 2828 free: 2829 kfree(dev->queues); 2830 kfree(dev); 2831 return result; 2832 } 2833 2834 static void nvme_reset_prepare(struct pci_dev *pdev) 2835 { 2836 struct nvme_dev *dev = pci_get_drvdata(pdev); 2837 nvme_dev_disable(dev, false); 2838 } 2839 2840 static void nvme_reset_done(struct pci_dev *pdev) 2841 { 2842 struct nvme_dev *dev = pci_get_drvdata(pdev); 2843 nvme_reset_ctrl_sync(&dev->ctrl); 2844 } 2845 2846 static void nvme_shutdown(struct pci_dev *pdev) 2847 { 2848 struct nvme_dev *dev = pci_get_drvdata(pdev); 2849 nvme_dev_disable(dev, true); 2850 } 2851 2852 /* 2853 * The driver's remove may be called on a device in a partially initialized 2854 * state. This function must not have any dependencies on the device state in 2855 * order to proceed. 2856 */ 2857 static void nvme_remove(struct pci_dev *pdev) 2858 { 2859 struct nvme_dev *dev = pci_get_drvdata(pdev); 2860 2861 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2862 pci_set_drvdata(pdev, NULL); 2863 2864 if (!pci_device_is_present(pdev)) { 2865 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2866 nvme_dev_disable(dev, true); 2867 nvme_dev_remove_admin(dev); 2868 } 2869 2870 flush_work(&dev->ctrl.reset_work); 2871 nvme_stop_ctrl(&dev->ctrl); 2872 nvme_remove_namespaces(&dev->ctrl); 2873 nvme_dev_disable(dev, true); 2874 nvme_release_cmb(dev); 2875 nvme_free_host_mem(dev); 2876 nvme_dev_remove_admin(dev); 2877 nvme_free_queues(dev, 0); 2878 nvme_uninit_ctrl(&dev->ctrl); 2879 nvme_release_prp_pools(dev); 2880 nvme_dev_unmap(dev); 2881 nvme_put_ctrl(&dev->ctrl); 2882 } 2883 2884 #ifdef CONFIG_PM_SLEEP 2885 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2886 { 2887 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2888 } 2889 2890 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2891 { 2892 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2893 } 2894 2895 static int nvme_resume(struct device *dev) 2896 { 2897 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2898 struct nvme_ctrl *ctrl = &ndev->ctrl; 2899 2900 if (ndev->last_ps == U32_MAX || 2901 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2902 nvme_reset_ctrl(ctrl); 2903 return 0; 2904 } 2905 2906 static int nvme_suspend(struct device *dev) 2907 { 2908 struct pci_dev *pdev = to_pci_dev(dev); 2909 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2910 struct nvme_ctrl *ctrl = &ndev->ctrl; 2911 int ret = -EBUSY; 2912 2913 ndev->last_ps = U32_MAX; 2914 2915 /* 2916 * The platform does not remove power for a kernel managed suspend so 2917 * use host managed nvme power settings for lowest idle power if 2918 * possible. This should have quicker resume latency than a full device 2919 * shutdown. But if the firmware is involved after the suspend or the 2920 * device does not support any non-default power states, shut down the 2921 * device fully. 2922 * 2923 * If ASPM is not enabled for the device, shut down the device and allow 2924 * the PCI bus layer to put it into D3 in order to take the PCIe link 2925 * down, so as to allow the platform to achieve its minimum low-power 2926 * state (which may not be possible if the link is up). 2927 */ 2928 if (pm_suspend_via_firmware() || !ctrl->npss || 2929 !pcie_aspm_enabled(pdev) || 2930 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) { 2931 nvme_dev_disable(ndev, true); 2932 return 0; 2933 } 2934 2935 nvme_start_freeze(ctrl); 2936 nvme_wait_freeze(ctrl); 2937 nvme_sync_queues(ctrl); 2938 2939 if (ctrl->state != NVME_CTRL_LIVE && 2940 ctrl->state != NVME_CTRL_ADMIN_ONLY) 2941 goto unfreeze; 2942 2943 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2944 if (ret < 0) 2945 goto unfreeze; 2946 2947 /* 2948 * A saved state prevents pci pm from generically controlling the 2949 * device's power. If we're using protocol specific settings, we don't 2950 * want pci interfering. 2951 */ 2952 pci_save_state(pdev); 2953 2954 ret = nvme_set_power_state(ctrl, ctrl->npss); 2955 if (ret < 0) 2956 goto unfreeze; 2957 2958 if (ret) { 2959 /* discard the saved state */ 2960 pci_load_saved_state(pdev, NULL); 2961 2962 /* 2963 * Clearing npss forces a controller reset on resume. The 2964 * correct value will be resdicovered then. 2965 */ 2966 nvme_dev_disable(ndev, true); 2967 ctrl->npss = 0; 2968 ret = 0; 2969 } 2970 unfreeze: 2971 nvme_unfreeze(ctrl); 2972 return ret; 2973 } 2974 2975 static int nvme_simple_suspend(struct device *dev) 2976 { 2977 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2978 2979 nvme_dev_disable(ndev, true); 2980 return 0; 2981 } 2982 2983 static int nvme_simple_resume(struct device *dev) 2984 { 2985 struct pci_dev *pdev = to_pci_dev(dev); 2986 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2987 2988 nvme_reset_ctrl(&ndev->ctrl); 2989 return 0; 2990 } 2991 2992 static const struct dev_pm_ops nvme_dev_pm_ops = { 2993 .suspend = nvme_suspend, 2994 .resume = nvme_resume, 2995 .freeze = nvme_simple_suspend, 2996 .thaw = nvme_simple_resume, 2997 .poweroff = nvme_simple_suspend, 2998 .restore = nvme_simple_resume, 2999 }; 3000 #endif /* CONFIG_PM_SLEEP */ 3001 3002 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3003 pci_channel_state_t state) 3004 { 3005 struct nvme_dev *dev = pci_get_drvdata(pdev); 3006 3007 /* 3008 * A frozen channel requires a reset. When detected, this method will 3009 * shutdown the controller to quiesce. The controller will be restarted 3010 * after the slot reset through driver's slot_reset callback. 3011 */ 3012 switch (state) { 3013 case pci_channel_io_normal: 3014 return PCI_ERS_RESULT_CAN_RECOVER; 3015 case pci_channel_io_frozen: 3016 dev_warn(dev->ctrl.device, 3017 "frozen state error detected, reset controller\n"); 3018 nvme_dev_disable(dev, false); 3019 return PCI_ERS_RESULT_NEED_RESET; 3020 case pci_channel_io_perm_failure: 3021 dev_warn(dev->ctrl.device, 3022 "failure state error detected, request disconnect\n"); 3023 return PCI_ERS_RESULT_DISCONNECT; 3024 } 3025 return PCI_ERS_RESULT_NEED_RESET; 3026 } 3027 3028 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3029 { 3030 struct nvme_dev *dev = pci_get_drvdata(pdev); 3031 3032 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3033 pci_restore_state(pdev); 3034 nvme_reset_ctrl(&dev->ctrl); 3035 return PCI_ERS_RESULT_RECOVERED; 3036 } 3037 3038 static void nvme_error_resume(struct pci_dev *pdev) 3039 { 3040 struct nvme_dev *dev = pci_get_drvdata(pdev); 3041 3042 flush_work(&dev->ctrl.reset_work); 3043 } 3044 3045 static const struct pci_error_handlers nvme_err_handler = { 3046 .error_detected = nvme_error_detected, 3047 .slot_reset = nvme_slot_reset, 3048 .resume = nvme_error_resume, 3049 .reset_prepare = nvme_reset_prepare, 3050 .reset_done = nvme_reset_done, 3051 }; 3052 3053 static const struct pci_device_id nvme_id_table[] = { 3054 { PCI_VDEVICE(INTEL, 0x0953), 3055 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3056 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3057 { PCI_VDEVICE(INTEL, 0x0a53), 3058 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3059 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3060 { PCI_VDEVICE(INTEL, 0x0a54), 3061 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3062 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3063 { PCI_VDEVICE(INTEL, 0x0a55), 3064 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3065 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3066 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3067 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3068 NVME_QUIRK_MEDIUM_PRIO_SQ }, 3069 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3070 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3071 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3072 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3073 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3074 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3075 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3076 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3077 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3078 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3079 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3080 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3081 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3082 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3083 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3084 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3085 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3086 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3087 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3088 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3089 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3090 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3091 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3092 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3093 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3094 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3095 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3096 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3097 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3098 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3099 NVME_QUIRK_128_BYTES_SQES | 3100 NVME_QUIRK_SHARED_TAGS }, 3101 { 0, } 3102 }; 3103 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3104 3105 static struct pci_driver nvme_driver = { 3106 .name = "nvme", 3107 .id_table = nvme_id_table, 3108 .probe = nvme_probe, 3109 .remove = nvme_remove, 3110 .shutdown = nvme_shutdown, 3111 #ifdef CONFIG_PM_SLEEP 3112 .driver = { 3113 .pm = &nvme_dev_pm_ops, 3114 }, 3115 #endif 3116 .sriov_configure = pci_sriov_configure_simple, 3117 .err_handler = &nvme_err_handler, 3118 }; 3119 3120 static int __init nvme_init(void) 3121 { 3122 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3123 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3124 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3125 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3126 return pci_register_driver(&nvme_driver); 3127 } 3128 3129 static void __exit nvme_exit(void) 3130 { 3131 pci_unregister_driver(&nvme_driver); 3132 flush_workqueue(nvme_wq); 3133 } 3134 3135 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3136 MODULE_LICENSE("GPL"); 3137 MODULE_VERSION("1.0"); 3138 module_init(nvme_init); 3139 module_exit(nvme_exit); 3140