1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static unsigned int write_queues; 72 module_param(write_queues, uint, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static unsigned int poll_queues; 78 module_param(poll_queues, uint, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 int io_sqes; 104 u32 db_stride; 105 void __iomem *bar; 106 unsigned long bar_mapped_size; 107 struct work_struct remove_work; 108 struct mutex shutdown_lock; 109 bool subsystem; 110 u64 cmb_size; 111 bool cmb_use_sqes; 112 u32 cmbsz; 113 u32 cmbloc; 114 struct nvme_ctrl ctrl; 115 u32 last_ps; 116 117 mempool_t *iod_mempool; 118 119 /* shadow doorbell buffer support: */ 120 u32 *dbbuf_dbs; 121 dma_addr_t dbbuf_dbs_dma_addr; 122 u32 *dbbuf_eis; 123 dma_addr_t dbbuf_eis_dma_addr; 124 125 /* host memory buffer support: */ 126 u64 host_mem_size; 127 u32 nr_host_mem_descs; 128 dma_addr_t host_mem_descs_dma; 129 struct nvme_host_mem_buf_desc *host_mem_descs; 130 void **host_mem_desc_bufs; 131 }; 132 133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134 { 135 int n = 0, ret; 136 137 ret = kstrtoint(val, 10, &n); 138 if (ret != 0 || n < 2) 139 return -EINVAL; 140 141 return param_set_int(val, kp); 142 } 143 144 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145 { 146 return qid * 2 * stride; 147 } 148 149 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150 { 151 return (qid * 2 + 1) * stride; 152 } 153 154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 155 { 156 return container_of(ctrl, struct nvme_dev, ctrl); 157 } 158 159 /* 160 * An NVM Express queue. Each device has at least two (one for admin 161 * commands and one for I/O commands). 162 */ 163 struct nvme_queue { 164 struct nvme_dev *dev; 165 spinlock_t sq_lock; 166 void *sq_cmds; 167 /* only used for poll queues: */ 168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 169 volatile struct nvme_completion *cqes; 170 dma_addr_t sq_dma_addr; 171 dma_addr_t cq_dma_addr; 172 u32 __iomem *q_db; 173 u16 q_depth; 174 u16 cq_vector; 175 u16 sq_tail; 176 u16 last_sq_tail; 177 u16 cq_head; 178 u16 qid; 179 u8 cq_phase; 180 u8 sqes; 181 unsigned long flags; 182 #define NVMEQ_ENABLED 0 183 #define NVMEQ_SQ_CMB 1 184 #define NVMEQ_DELETE_ERROR 2 185 #define NVMEQ_POLLED 3 186 u32 *dbbuf_sq_db; 187 u32 *dbbuf_cq_db; 188 u32 *dbbuf_sq_ei; 189 u32 *dbbuf_cq_ei; 190 struct completion delete_done; 191 }; 192 193 /* 194 * The nvme_iod describes the data in an I/O. 195 * 196 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 197 * to the actual struct scatterlist. 198 */ 199 struct nvme_iod { 200 struct nvme_request req; 201 struct nvme_queue *nvmeq; 202 bool use_sgl; 203 int aborted; 204 int npages; /* In the PRP list. 0 means small pool in use */ 205 int nents; /* Used in scatterlist */ 206 dma_addr_t first_dma; 207 unsigned int dma_len; /* length of single DMA segment mapping */ 208 dma_addr_t meta_dma; 209 struct scatterlist *sg; 210 }; 211 212 static unsigned int max_io_queues(void) 213 { 214 return num_possible_cpus() + write_queues + poll_queues; 215 } 216 217 static unsigned int max_queue_count(void) 218 { 219 /* IO queues + admin queue */ 220 return 1 + max_io_queues(); 221 } 222 223 static inline unsigned int nvme_dbbuf_size(u32 stride) 224 { 225 return (max_queue_count() * 8 * stride); 226 } 227 228 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229 { 230 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231 232 if (dev->dbbuf_dbs) 233 return 0; 234 235 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236 &dev->dbbuf_dbs_dma_addr, 237 GFP_KERNEL); 238 if (!dev->dbbuf_dbs) 239 return -ENOMEM; 240 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241 &dev->dbbuf_eis_dma_addr, 242 GFP_KERNEL); 243 if (!dev->dbbuf_eis) { 244 dma_free_coherent(dev->dev, mem_size, 245 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246 dev->dbbuf_dbs = NULL; 247 return -ENOMEM; 248 } 249 250 return 0; 251 } 252 253 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254 { 255 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256 257 if (dev->dbbuf_dbs) { 258 dma_free_coherent(dev->dev, mem_size, 259 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260 dev->dbbuf_dbs = NULL; 261 } 262 if (dev->dbbuf_eis) { 263 dma_free_coherent(dev->dev, mem_size, 264 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265 dev->dbbuf_eis = NULL; 266 } 267 } 268 269 static void nvme_dbbuf_init(struct nvme_dev *dev, 270 struct nvme_queue *nvmeq, int qid) 271 { 272 if (!dev->dbbuf_dbs || !qid) 273 return; 274 275 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279 } 280 281 static void nvme_dbbuf_set(struct nvme_dev *dev) 282 { 283 struct nvme_command c; 284 285 if (!dev->dbbuf_dbs) 286 return; 287 288 memset(&c, 0, sizeof(c)); 289 c.dbbuf.opcode = nvme_admin_dbbuf; 290 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292 293 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 294 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295 /* Free memory and continue on */ 296 nvme_dbbuf_dma_free(dev); 297 } 298 } 299 300 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301 { 302 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303 } 304 305 /* Update dbbuf and return true if an MMIO is required */ 306 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307 volatile u32 *dbbuf_ei) 308 { 309 if (dbbuf_db) { 310 u16 old_value; 311 312 /* 313 * Ensure that the queue is written before updating 314 * the doorbell in memory 315 */ 316 wmb(); 317 318 old_value = *dbbuf_db; 319 *dbbuf_db = value; 320 321 /* 322 * Ensure that the doorbell is updated before reading the event 323 * index from memory. The controller needs to provide similar 324 * ordering to ensure the envent index is updated before reading 325 * the doorbell. 326 */ 327 mb(); 328 329 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330 return false; 331 } 332 333 return true; 334 } 335 336 /* 337 * Will slightly overestimate the number of pages needed. This is OK 338 * as it only leads to a small amount of wasted memory for the lifetime of 339 * the I/O. 340 */ 341 static int nvme_npages(unsigned size, struct nvme_dev *dev) 342 { 343 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 344 dev->ctrl.page_size); 345 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 346 } 347 348 /* 349 * Calculates the number of pages needed for the SGL segments. For example a 4k 350 * page can accommodate 256 SGL descriptors. 351 */ 352 static int nvme_pci_npages_sgl(unsigned int num_seg) 353 { 354 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355 } 356 357 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358 unsigned int size, unsigned int nseg, bool use_sgl) 359 { 360 size_t alloc_size; 361 362 if (use_sgl) 363 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364 else 365 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366 367 return alloc_size + sizeof(struct scatterlist) * nseg; 368 } 369 370 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 371 unsigned int hctx_idx) 372 { 373 struct nvme_dev *dev = data; 374 struct nvme_queue *nvmeq = &dev->queues[0]; 375 376 WARN_ON(hctx_idx != 0); 377 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 378 379 hctx->driver_data = nvmeq; 380 return 0; 381 } 382 383 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 384 unsigned int hctx_idx) 385 { 386 struct nvme_dev *dev = data; 387 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 388 389 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 390 hctx->driver_data = nvmeq; 391 return 0; 392 } 393 394 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 395 unsigned int hctx_idx, unsigned int numa_node) 396 { 397 struct nvme_dev *dev = set->driver_data; 398 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 399 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 400 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 401 402 BUG_ON(!nvmeq); 403 iod->nvmeq = nvmeq; 404 405 nvme_req(req)->ctrl = &dev->ctrl; 406 return 0; 407 } 408 409 static int queue_irq_offset(struct nvme_dev *dev) 410 { 411 /* if we have more than 1 vec, admin queue offsets us by 1 */ 412 if (dev->num_vecs > 1) 413 return 1; 414 415 return 0; 416 } 417 418 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 419 { 420 struct nvme_dev *dev = set->driver_data; 421 int i, qoff, offset; 422 423 offset = queue_irq_offset(dev); 424 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 425 struct blk_mq_queue_map *map = &set->map[i]; 426 427 map->nr_queues = dev->io_queues[i]; 428 if (!map->nr_queues) { 429 BUG_ON(i == HCTX_TYPE_DEFAULT); 430 continue; 431 } 432 433 /* 434 * The poll queue(s) doesn't have an IRQ (and hence IRQ 435 * affinity), so use the regular blk-mq cpu mapping 436 */ 437 map->queue_offset = qoff; 438 if (i != HCTX_TYPE_POLL && offset) 439 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 440 else 441 blk_mq_map_queues(map); 442 qoff += map->nr_queues; 443 offset += map->nr_queues; 444 } 445 446 return 0; 447 } 448 449 /* 450 * Write sq tail if we are asked to, or if the next command would wrap. 451 */ 452 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 453 { 454 if (!write_sq) { 455 u16 next_tail = nvmeq->sq_tail + 1; 456 457 if (next_tail == nvmeq->q_depth) 458 next_tail = 0; 459 if (next_tail != nvmeq->last_sq_tail) 460 return; 461 } 462 463 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 464 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 465 writel(nvmeq->sq_tail, nvmeq->q_db); 466 nvmeq->last_sq_tail = nvmeq->sq_tail; 467 } 468 469 /** 470 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 471 * @nvmeq: The queue to use 472 * @cmd: The command to send 473 * @write_sq: whether to write to the SQ doorbell 474 */ 475 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 476 bool write_sq) 477 { 478 spin_lock(&nvmeq->sq_lock); 479 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 480 cmd, sizeof(*cmd)); 481 if (++nvmeq->sq_tail == nvmeq->q_depth) 482 nvmeq->sq_tail = 0; 483 nvme_write_sq_db(nvmeq, write_sq); 484 spin_unlock(&nvmeq->sq_lock); 485 } 486 487 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 488 { 489 struct nvme_queue *nvmeq = hctx->driver_data; 490 491 spin_lock(&nvmeq->sq_lock); 492 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 493 nvme_write_sq_db(nvmeq, true); 494 spin_unlock(&nvmeq->sq_lock); 495 } 496 497 static void **nvme_pci_iod_list(struct request *req) 498 { 499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 500 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 501 } 502 503 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 504 { 505 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 506 int nseg = blk_rq_nr_phys_segments(req); 507 unsigned int avg_seg_size; 508 509 if (nseg == 0) 510 return false; 511 512 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 513 514 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 515 return false; 516 if (!iod->nvmeq->qid) 517 return false; 518 if (!sgl_threshold || avg_seg_size < sgl_threshold) 519 return false; 520 return true; 521 } 522 523 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 524 { 525 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 527 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 528 int i; 529 530 if (iod->dma_len) { 531 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 532 rq_dma_dir(req)); 533 return; 534 } 535 536 WARN_ON_ONCE(!iod->nents); 537 538 if (is_pci_p2pdma_page(sg_page(iod->sg))) 539 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 540 rq_dma_dir(req)); 541 else 542 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 543 544 545 if (iod->npages == 0) 546 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 547 dma_addr); 548 549 for (i = 0; i < iod->npages; i++) { 550 void *addr = nvme_pci_iod_list(req)[i]; 551 552 if (iod->use_sgl) { 553 struct nvme_sgl_desc *sg_list = addr; 554 555 next_dma_addr = 556 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 557 } else { 558 __le64 *prp_list = addr; 559 560 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 561 } 562 563 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 564 dma_addr = next_dma_addr; 565 } 566 567 mempool_free(iod->sg, dev->iod_mempool); 568 } 569 570 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 571 { 572 int i; 573 struct scatterlist *sg; 574 575 for_each_sg(sgl, sg, nents, i) { 576 dma_addr_t phys = sg_phys(sg); 577 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 578 "dma_address:%pad dma_length:%d\n", 579 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 580 sg_dma_len(sg)); 581 } 582 } 583 584 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 585 struct request *req, struct nvme_rw_command *cmnd) 586 { 587 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 588 struct dma_pool *pool; 589 int length = blk_rq_payload_bytes(req); 590 struct scatterlist *sg = iod->sg; 591 int dma_len = sg_dma_len(sg); 592 u64 dma_addr = sg_dma_address(sg); 593 u32 page_size = dev->ctrl.page_size; 594 int offset = dma_addr & (page_size - 1); 595 __le64 *prp_list; 596 void **list = nvme_pci_iod_list(req); 597 dma_addr_t prp_dma; 598 int nprps, i; 599 600 length -= (page_size - offset); 601 if (length <= 0) { 602 iod->first_dma = 0; 603 goto done; 604 } 605 606 dma_len -= (page_size - offset); 607 if (dma_len) { 608 dma_addr += (page_size - offset); 609 } else { 610 sg = sg_next(sg); 611 dma_addr = sg_dma_address(sg); 612 dma_len = sg_dma_len(sg); 613 } 614 615 if (length <= page_size) { 616 iod->first_dma = dma_addr; 617 goto done; 618 } 619 620 nprps = DIV_ROUND_UP(length, page_size); 621 if (nprps <= (256 / 8)) { 622 pool = dev->prp_small_pool; 623 iod->npages = 0; 624 } else { 625 pool = dev->prp_page_pool; 626 iod->npages = 1; 627 } 628 629 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 630 if (!prp_list) { 631 iod->first_dma = dma_addr; 632 iod->npages = -1; 633 return BLK_STS_RESOURCE; 634 } 635 list[0] = prp_list; 636 iod->first_dma = prp_dma; 637 i = 0; 638 for (;;) { 639 if (i == page_size >> 3) { 640 __le64 *old_prp_list = prp_list; 641 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 642 if (!prp_list) 643 return BLK_STS_RESOURCE; 644 list[iod->npages++] = prp_list; 645 prp_list[0] = old_prp_list[i - 1]; 646 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 647 i = 1; 648 } 649 prp_list[i++] = cpu_to_le64(dma_addr); 650 dma_len -= page_size; 651 dma_addr += page_size; 652 length -= page_size; 653 if (length <= 0) 654 break; 655 if (dma_len > 0) 656 continue; 657 if (unlikely(dma_len < 0)) 658 goto bad_sgl; 659 sg = sg_next(sg); 660 dma_addr = sg_dma_address(sg); 661 dma_len = sg_dma_len(sg); 662 } 663 664 done: 665 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 666 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 667 668 return BLK_STS_OK; 669 670 bad_sgl: 671 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 672 "Invalid SGL for payload:%d nents:%d\n", 673 blk_rq_payload_bytes(req), iod->nents); 674 return BLK_STS_IOERR; 675 } 676 677 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 678 struct scatterlist *sg) 679 { 680 sge->addr = cpu_to_le64(sg_dma_address(sg)); 681 sge->length = cpu_to_le32(sg_dma_len(sg)); 682 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 683 } 684 685 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 686 dma_addr_t dma_addr, int entries) 687 { 688 sge->addr = cpu_to_le64(dma_addr); 689 if (entries < SGES_PER_PAGE) { 690 sge->length = cpu_to_le32(entries * sizeof(*sge)); 691 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 692 } else { 693 sge->length = cpu_to_le32(PAGE_SIZE); 694 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 695 } 696 } 697 698 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 699 struct request *req, struct nvme_rw_command *cmd, int entries) 700 { 701 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 702 struct dma_pool *pool; 703 struct nvme_sgl_desc *sg_list; 704 struct scatterlist *sg = iod->sg; 705 dma_addr_t sgl_dma; 706 int i = 0; 707 708 /* setting the transfer type as SGL */ 709 cmd->flags = NVME_CMD_SGL_METABUF; 710 711 if (entries == 1) { 712 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 713 return BLK_STS_OK; 714 } 715 716 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 717 pool = dev->prp_small_pool; 718 iod->npages = 0; 719 } else { 720 pool = dev->prp_page_pool; 721 iod->npages = 1; 722 } 723 724 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 725 if (!sg_list) { 726 iod->npages = -1; 727 return BLK_STS_RESOURCE; 728 } 729 730 nvme_pci_iod_list(req)[0] = sg_list; 731 iod->first_dma = sgl_dma; 732 733 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 734 735 do { 736 if (i == SGES_PER_PAGE) { 737 struct nvme_sgl_desc *old_sg_desc = sg_list; 738 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 739 740 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 741 if (!sg_list) 742 return BLK_STS_RESOURCE; 743 744 i = 0; 745 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 746 sg_list[i++] = *link; 747 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 748 } 749 750 nvme_pci_sgl_set_data(&sg_list[i++], sg); 751 sg = sg_next(sg); 752 } while (--entries > 0); 753 754 return BLK_STS_OK; 755 } 756 757 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 758 struct request *req, struct nvme_rw_command *cmnd, 759 struct bio_vec *bv) 760 { 761 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 762 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 763 unsigned int first_prp_len = dev->ctrl.page_size - offset; 764 765 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 766 if (dma_mapping_error(dev->dev, iod->first_dma)) 767 return BLK_STS_RESOURCE; 768 iod->dma_len = bv->bv_len; 769 770 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 771 if (bv->bv_len > first_prp_len) 772 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 773 return 0; 774 } 775 776 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 777 struct request *req, struct nvme_rw_command *cmnd, 778 struct bio_vec *bv) 779 { 780 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 781 782 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 783 if (dma_mapping_error(dev->dev, iod->first_dma)) 784 return BLK_STS_RESOURCE; 785 iod->dma_len = bv->bv_len; 786 787 cmnd->flags = NVME_CMD_SGL_METABUF; 788 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 789 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 790 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 791 return 0; 792 } 793 794 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 795 struct nvme_command *cmnd) 796 { 797 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 798 blk_status_t ret = BLK_STS_RESOURCE; 799 int nr_mapped; 800 801 if (blk_rq_nr_phys_segments(req) == 1) { 802 struct bio_vec bv = req_bvec(req); 803 804 if (!is_pci_p2pdma_page(bv.bv_page)) { 805 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 806 return nvme_setup_prp_simple(dev, req, 807 &cmnd->rw, &bv); 808 809 if (iod->nvmeq->qid && 810 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 811 return nvme_setup_sgl_simple(dev, req, 812 &cmnd->rw, &bv); 813 } 814 } 815 816 iod->dma_len = 0; 817 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 818 if (!iod->sg) 819 return BLK_STS_RESOURCE; 820 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 821 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 822 if (!iod->nents) 823 goto out; 824 825 if (is_pci_p2pdma_page(sg_page(iod->sg))) 826 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 827 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 828 else 829 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 830 rq_dma_dir(req), DMA_ATTR_NO_WARN); 831 if (!nr_mapped) 832 goto out; 833 834 iod->use_sgl = nvme_pci_use_sgls(dev, req); 835 if (iod->use_sgl) 836 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 837 else 838 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 839 out: 840 if (ret != BLK_STS_OK) 841 nvme_unmap_data(dev, req); 842 return ret; 843 } 844 845 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 846 struct nvme_command *cmnd) 847 { 848 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 849 850 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 851 rq_dma_dir(req), 0); 852 if (dma_mapping_error(dev->dev, iod->meta_dma)) 853 return BLK_STS_IOERR; 854 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 855 return 0; 856 } 857 858 /* 859 * NOTE: ns is NULL when called on the admin queue. 860 */ 861 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 862 const struct blk_mq_queue_data *bd) 863 { 864 struct nvme_ns *ns = hctx->queue->queuedata; 865 struct nvme_queue *nvmeq = hctx->driver_data; 866 struct nvme_dev *dev = nvmeq->dev; 867 struct request *req = bd->rq; 868 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 869 struct nvme_command cmnd; 870 blk_status_t ret; 871 872 iod->aborted = 0; 873 iod->npages = -1; 874 iod->nents = 0; 875 876 /* 877 * We should not need to do this, but we're still using this to 878 * ensure we can drain requests on a dying queue. 879 */ 880 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 881 return BLK_STS_IOERR; 882 883 ret = nvme_setup_cmd(ns, req, &cmnd); 884 if (ret) 885 return ret; 886 887 if (blk_rq_nr_phys_segments(req)) { 888 ret = nvme_map_data(dev, req, &cmnd); 889 if (ret) 890 goto out_free_cmd; 891 } 892 893 if (blk_integrity_rq(req)) { 894 ret = nvme_map_metadata(dev, req, &cmnd); 895 if (ret) 896 goto out_unmap_data; 897 } 898 899 blk_mq_start_request(req); 900 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 901 return BLK_STS_OK; 902 out_unmap_data: 903 nvme_unmap_data(dev, req); 904 out_free_cmd: 905 nvme_cleanup_cmd(req); 906 return ret; 907 } 908 909 static void nvme_pci_complete_rq(struct request *req) 910 { 911 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 912 struct nvme_dev *dev = iod->nvmeq->dev; 913 914 if (blk_integrity_rq(req)) 915 dma_unmap_page(dev->dev, iod->meta_dma, 916 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 917 if (blk_rq_nr_phys_segments(req)) 918 nvme_unmap_data(dev, req); 919 nvme_complete_rq(req); 920 } 921 922 /* We read the CQE phase first to check if the rest of the entry is valid */ 923 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 924 { 925 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 926 nvmeq->cq_phase; 927 } 928 929 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 930 { 931 u16 head = nvmeq->cq_head; 932 933 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 934 nvmeq->dbbuf_cq_ei)) 935 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 936 } 937 938 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 939 { 940 if (!nvmeq->qid) 941 return nvmeq->dev->admin_tagset.tags[0]; 942 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 943 } 944 945 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 946 { 947 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 948 struct request *req; 949 950 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 951 dev_warn(nvmeq->dev->ctrl.device, 952 "invalid id %d completed on queue %d\n", 953 cqe->command_id, le16_to_cpu(cqe->sq_id)); 954 return; 955 } 956 957 /* 958 * AEN requests are special as they don't time out and can 959 * survive any kind of queue freeze and often don't respond to 960 * aborts. We don't even bother to allocate a struct request 961 * for them but rather special case them here. 962 */ 963 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 964 nvme_complete_async_event(&nvmeq->dev->ctrl, 965 cqe->status, &cqe->result); 966 return; 967 } 968 969 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 970 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 971 nvme_end_request(req, cqe->status, cqe->result); 972 } 973 974 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 975 { 976 while (start != end) { 977 nvme_handle_cqe(nvmeq, start); 978 if (++start == nvmeq->q_depth) 979 start = 0; 980 } 981 } 982 983 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 984 { 985 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 986 nvmeq->cq_head = 0; 987 nvmeq->cq_phase = !nvmeq->cq_phase; 988 } else { 989 nvmeq->cq_head++; 990 } 991 } 992 993 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 994 u16 *end, unsigned int tag) 995 { 996 int found = 0; 997 998 *start = nvmeq->cq_head; 999 while (nvme_cqe_pending(nvmeq)) { 1000 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1001 found++; 1002 nvme_update_cq_head(nvmeq); 1003 } 1004 *end = nvmeq->cq_head; 1005 1006 if (*start != *end) 1007 nvme_ring_cq_doorbell(nvmeq); 1008 return found; 1009 } 1010 1011 static irqreturn_t nvme_irq(int irq, void *data) 1012 { 1013 struct nvme_queue *nvmeq = data; 1014 irqreturn_t ret = IRQ_NONE; 1015 u16 start, end; 1016 1017 /* 1018 * The rmb/wmb pair ensures we see all updates from a previous run of 1019 * the irq handler, even if that was on another CPU. 1020 */ 1021 rmb(); 1022 nvme_process_cq(nvmeq, &start, &end, -1); 1023 wmb(); 1024 1025 if (start != end) { 1026 nvme_complete_cqes(nvmeq, start, end); 1027 return IRQ_HANDLED; 1028 } 1029 1030 return ret; 1031 } 1032 1033 static irqreturn_t nvme_irq_check(int irq, void *data) 1034 { 1035 struct nvme_queue *nvmeq = data; 1036 if (nvme_cqe_pending(nvmeq)) 1037 return IRQ_WAKE_THREAD; 1038 return IRQ_NONE; 1039 } 1040 1041 /* 1042 * Poll for completions any queue, including those not dedicated to polling. 1043 * Can be called from any context. 1044 */ 1045 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1046 { 1047 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1048 u16 start, end; 1049 int found; 1050 1051 /* 1052 * For a poll queue we need to protect against the polling thread 1053 * using the CQ lock. For normal interrupt driven threads we have 1054 * to disable the interrupt to avoid racing with it. 1055 */ 1056 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1057 spin_lock(&nvmeq->cq_poll_lock); 1058 found = nvme_process_cq(nvmeq, &start, &end, tag); 1059 spin_unlock(&nvmeq->cq_poll_lock); 1060 } else { 1061 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1062 found = nvme_process_cq(nvmeq, &start, &end, tag); 1063 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1064 } 1065 1066 nvme_complete_cqes(nvmeq, start, end); 1067 return found; 1068 } 1069 1070 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1071 { 1072 struct nvme_queue *nvmeq = hctx->driver_data; 1073 u16 start, end; 1074 bool found; 1075 1076 if (!nvme_cqe_pending(nvmeq)) 1077 return 0; 1078 1079 spin_lock(&nvmeq->cq_poll_lock); 1080 found = nvme_process_cq(nvmeq, &start, &end, -1); 1081 spin_unlock(&nvmeq->cq_poll_lock); 1082 1083 nvme_complete_cqes(nvmeq, start, end); 1084 return found; 1085 } 1086 1087 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1088 { 1089 struct nvme_dev *dev = to_nvme_dev(ctrl); 1090 struct nvme_queue *nvmeq = &dev->queues[0]; 1091 struct nvme_command c; 1092 1093 memset(&c, 0, sizeof(c)); 1094 c.common.opcode = nvme_admin_async_event; 1095 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1096 nvme_submit_cmd(nvmeq, &c, true); 1097 } 1098 1099 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1100 { 1101 struct nvme_command c; 1102 1103 memset(&c, 0, sizeof(c)); 1104 c.delete_queue.opcode = opcode; 1105 c.delete_queue.qid = cpu_to_le16(id); 1106 1107 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1108 } 1109 1110 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1111 struct nvme_queue *nvmeq, s16 vector) 1112 { 1113 struct nvme_command c; 1114 int flags = NVME_QUEUE_PHYS_CONTIG; 1115 1116 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1117 flags |= NVME_CQ_IRQ_ENABLED; 1118 1119 /* 1120 * Note: we (ab)use the fact that the prp fields survive if no data 1121 * is attached to the request. 1122 */ 1123 memset(&c, 0, sizeof(c)); 1124 c.create_cq.opcode = nvme_admin_create_cq; 1125 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1126 c.create_cq.cqid = cpu_to_le16(qid); 1127 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1128 c.create_cq.cq_flags = cpu_to_le16(flags); 1129 c.create_cq.irq_vector = cpu_to_le16(vector); 1130 1131 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1132 } 1133 1134 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1135 struct nvme_queue *nvmeq) 1136 { 1137 struct nvme_ctrl *ctrl = &dev->ctrl; 1138 struct nvme_command c; 1139 int flags = NVME_QUEUE_PHYS_CONTIG; 1140 1141 /* 1142 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1143 * set. Since URGENT priority is zeroes, it makes all queues 1144 * URGENT. 1145 */ 1146 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1147 flags |= NVME_SQ_PRIO_MEDIUM; 1148 1149 /* 1150 * Note: we (ab)use the fact that the prp fields survive if no data 1151 * is attached to the request. 1152 */ 1153 memset(&c, 0, sizeof(c)); 1154 c.create_sq.opcode = nvme_admin_create_sq; 1155 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1156 c.create_sq.sqid = cpu_to_le16(qid); 1157 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1158 c.create_sq.sq_flags = cpu_to_le16(flags); 1159 c.create_sq.cqid = cpu_to_le16(qid); 1160 1161 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1162 } 1163 1164 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1165 { 1166 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1167 } 1168 1169 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1170 { 1171 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1172 } 1173 1174 static void abort_endio(struct request *req, blk_status_t error) 1175 { 1176 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1177 struct nvme_queue *nvmeq = iod->nvmeq; 1178 1179 dev_warn(nvmeq->dev->ctrl.device, 1180 "Abort status: 0x%x", nvme_req(req)->status); 1181 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1182 blk_mq_free_request(req); 1183 } 1184 1185 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1186 { 1187 1188 /* If true, indicates loss of adapter communication, possibly by a 1189 * NVMe Subsystem reset. 1190 */ 1191 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1192 1193 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1194 switch (dev->ctrl.state) { 1195 case NVME_CTRL_RESETTING: 1196 case NVME_CTRL_CONNECTING: 1197 return false; 1198 default: 1199 break; 1200 } 1201 1202 /* We shouldn't reset unless the controller is on fatal error state 1203 * _or_ if we lost the communication with it. 1204 */ 1205 if (!(csts & NVME_CSTS_CFS) && !nssro) 1206 return false; 1207 1208 return true; 1209 } 1210 1211 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1212 { 1213 /* Read a config register to help see what died. */ 1214 u16 pci_status; 1215 int result; 1216 1217 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1218 &pci_status); 1219 if (result == PCIBIOS_SUCCESSFUL) 1220 dev_warn(dev->ctrl.device, 1221 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1222 csts, pci_status); 1223 else 1224 dev_warn(dev->ctrl.device, 1225 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1226 csts, result); 1227 } 1228 1229 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1230 { 1231 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1232 struct nvme_queue *nvmeq = iod->nvmeq; 1233 struct nvme_dev *dev = nvmeq->dev; 1234 struct request *abort_req; 1235 struct nvme_command cmd; 1236 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1237 1238 /* If PCI error recovery process is happening, we cannot reset or 1239 * the recovery mechanism will surely fail. 1240 */ 1241 mb(); 1242 if (pci_channel_offline(to_pci_dev(dev->dev))) 1243 return BLK_EH_RESET_TIMER; 1244 1245 /* 1246 * Reset immediately if the controller is failed 1247 */ 1248 if (nvme_should_reset(dev, csts)) { 1249 nvme_warn_reset(dev, csts); 1250 nvme_dev_disable(dev, false); 1251 nvme_reset_ctrl(&dev->ctrl); 1252 return BLK_EH_DONE; 1253 } 1254 1255 /* 1256 * Did we miss an interrupt? 1257 */ 1258 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1259 dev_warn(dev->ctrl.device, 1260 "I/O %d QID %d timeout, completion polled\n", 1261 req->tag, nvmeq->qid); 1262 return BLK_EH_DONE; 1263 } 1264 1265 /* 1266 * Shutdown immediately if controller times out while starting. The 1267 * reset work will see the pci device disabled when it gets the forced 1268 * cancellation error. All outstanding requests are completed on 1269 * shutdown, so we return BLK_EH_DONE. 1270 */ 1271 switch (dev->ctrl.state) { 1272 case NVME_CTRL_CONNECTING: 1273 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1274 /* fall through */ 1275 case NVME_CTRL_DELETING: 1276 dev_warn_ratelimited(dev->ctrl.device, 1277 "I/O %d QID %d timeout, disable controller\n", 1278 req->tag, nvmeq->qid); 1279 nvme_dev_disable(dev, true); 1280 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1281 return BLK_EH_DONE; 1282 case NVME_CTRL_RESETTING: 1283 return BLK_EH_RESET_TIMER; 1284 default: 1285 break; 1286 } 1287 1288 /* 1289 * Shutdown the controller immediately and schedule a reset if the 1290 * command was already aborted once before and still hasn't been 1291 * returned to the driver, or if this is the admin queue. 1292 */ 1293 if (!nvmeq->qid || iod->aborted) { 1294 dev_warn(dev->ctrl.device, 1295 "I/O %d QID %d timeout, reset controller\n", 1296 req->tag, nvmeq->qid); 1297 nvme_dev_disable(dev, false); 1298 nvme_reset_ctrl(&dev->ctrl); 1299 1300 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1301 return BLK_EH_DONE; 1302 } 1303 1304 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1305 atomic_inc(&dev->ctrl.abort_limit); 1306 return BLK_EH_RESET_TIMER; 1307 } 1308 iod->aborted = 1; 1309 1310 memset(&cmd, 0, sizeof(cmd)); 1311 cmd.abort.opcode = nvme_admin_abort_cmd; 1312 cmd.abort.cid = req->tag; 1313 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1314 1315 dev_warn(nvmeq->dev->ctrl.device, 1316 "I/O %d QID %d timeout, aborting\n", 1317 req->tag, nvmeq->qid); 1318 1319 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1320 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1321 if (IS_ERR(abort_req)) { 1322 atomic_inc(&dev->ctrl.abort_limit); 1323 return BLK_EH_RESET_TIMER; 1324 } 1325 1326 abort_req->timeout = ADMIN_TIMEOUT; 1327 abort_req->end_io_data = NULL; 1328 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1329 1330 /* 1331 * The aborted req will be completed on receiving the abort req. 1332 * We enable the timer again. If hit twice, it'll cause a device reset, 1333 * as the device then is in a faulty state. 1334 */ 1335 return BLK_EH_RESET_TIMER; 1336 } 1337 1338 static void nvme_free_queue(struct nvme_queue *nvmeq) 1339 { 1340 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1341 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1342 if (!nvmeq->sq_cmds) 1343 return; 1344 1345 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1346 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1347 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1348 } else { 1349 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1350 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1351 } 1352 } 1353 1354 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1355 { 1356 int i; 1357 1358 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1359 dev->ctrl.queue_count--; 1360 nvme_free_queue(&dev->queues[i]); 1361 } 1362 } 1363 1364 /** 1365 * nvme_suspend_queue - put queue into suspended state 1366 * @nvmeq: queue to suspend 1367 */ 1368 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1369 { 1370 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1371 return 1; 1372 1373 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1374 mb(); 1375 1376 nvmeq->dev->online_queues--; 1377 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1378 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1379 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1380 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1381 return 0; 1382 } 1383 1384 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1385 { 1386 int i; 1387 1388 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1389 nvme_suspend_queue(&dev->queues[i]); 1390 } 1391 1392 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1393 { 1394 struct nvme_queue *nvmeq = &dev->queues[0]; 1395 1396 if (shutdown) 1397 nvme_shutdown_ctrl(&dev->ctrl); 1398 else 1399 nvme_disable_ctrl(&dev->ctrl); 1400 1401 nvme_poll_irqdisable(nvmeq, -1); 1402 } 1403 1404 /* 1405 * Called only on a device that has been disabled and after all other threads 1406 * that can check this device's completion queues have synced. This is the 1407 * last chance for the driver to see a natural completion before 1408 * nvme_cancel_request() terminates all incomplete requests. 1409 */ 1410 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1411 { 1412 u16 start, end; 1413 int i; 1414 1415 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1416 nvme_process_cq(&dev->queues[i], &start, &end, -1); 1417 nvme_complete_cqes(&dev->queues[i], start, end); 1418 } 1419 } 1420 1421 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1422 int entry_size) 1423 { 1424 int q_depth = dev->q_depth; 1425 unsigned q_size_aligned = roundup(q_depth * entry_size, 1426 dev->ctrl.page_size); 1427 1428 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1429 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1430 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1431 q_depth = div_u64(mem_per_q, entry_size); 1432 1433 /* 1434 * Ensure the reduced q_depth is above some threshold where it 1435 * would be better to map queues in system memory with the 1436 * original depth 1437 */ 1438 if (q_depth < 64) 1439 return -ENOMEM; 1440 } 1441 1442 return q_depth; 1443 } 1444 1445 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1446 int qid) 1447 { 1448 struct pci_dev *pdev = to_pci_dev(dev->dev); 1449 1450 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1451 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1452 if (nvmeq->sq_cmds) { 1453 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1454 nvmeq->sq_cmds); 1455 if (nvmeq->sq_dma_addr) { 1456 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1457 return 0; 1458 } 1459 1460 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1461 } 1462 } 1463 1464 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1465 &nvmeq->sq_dma_addr, GFP_KERNEL); 1466 if (!nvmeq->sq_cmds) 1467 return -ENOMEM; 1468 return 0; 1469 } 1470 1471 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1472 { 1473 struct nvme_queue *nvmeq = &dev->queues[qid]; 1474 1475 if (dev->ctrl.queue_count > qid) 1476 return 0; 1477 1478 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1479 nvmeq->q_depth = depth; 1480 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1481 &nvmeq->cq_dma_addr, GFP_KERNEL); 1482 if (!nvmeq->cqes) 1483 goto free_nvmeq; 1484 1485 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1486 goto free_cqdma; 1487 1488 nvmeq->dev = dev; 1489 spin_lock_init(&nvmeq->sq_lock); 1490 spin_lock_init(&nvmeq->cq_poll_lock); 1491 nvmeq->cq_head = 0; 1492 nvmeq->cq_phase = 1; 1493 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1494 nvmeq->qid = qid; 1495 dev->ctrl.queue_count++; 1496 1497 return 0; 1498 1499 free_cqdma: 1500 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1501 nvmeq->cq_dma_addr); 1502 free_nvmeq: 1503 return -ENOMEM; 1504 } 1505 1506 static int queue_request_irq(struct nvme_queue *nvmeq) 1507 { 1508 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1509 int nr = nvmeq->dev->ctrl.instance; 1510 1511 if (use_threaded_interrupts) { 1512 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1513 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1514 } else { 1515 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1516 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1517 } 1518 } 1519 1520 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1521 { 1522 struct nvme_dev *dev = nvmeq->dev; 1523 1524 nvmeq->sq_tail = 0; 1525 nvmeq->last_sq_tail = 0; 1526 nvmeq->cq_head = 0; 1527 nvmeq->cq_phase = 1; 1528 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1529 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1530 nvme_dbbuf_init(dev, nvmeq, qid); 1531 dev->online_queues++; 1532 wmb(); /* ensure the first interrupt sees the initialization */ 1533 } 1534 1535 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1536 { 1537 struct nvme_dev *dev = nvmeq->dev; 1538 int result; 1539 u16 vector = 0; 1540 1541 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1542 1543 /* 1544 * A queue's vector matches the queue identifier unless the controller 1545 * has only one vector available. 1546 */ 1547 if (!polled) 1548 vector = dev->num_vecs == 1 ? 0 : qid; 1549 else 1550 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1551 1552 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1553 if (result) 1554 return result; 1555 1556 result = adapter_alloc_sq(dev, qid, nvmeq); 1557 if (result < 0) 1558 return result; 1559 if (result) 1560 goto release_cq; 1561 1562 nvmeq->cq_vector = vector; 1563 nvme_init_queue(nvmeq, qid); 1564 1565 if (!polled) { 1566 result = queue_request_irq(nvmeq); 1567 if (result < 0) 1568 goto release_sq; 1569 } 1570 1571 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1572 return result; 1573 1574 release_sq: 1575 dev->online_queues--; 1576 adapter_delete_sq(dev, qid); 1577 release_cq: 1578 adapter_delete_cq(dev, qid); 1579 return result; 1580 } 1581 1582 static const struct blk_mq_ops nvme_mq_admin_ops = { 1583 .queue_rq = nvme_queue_rq, 1584 .complete = nvme_pci_complete_rq, 1585 .init_hctx = nvme_admin_init_hctx, 1586 .init_request = nvme_init_request, 1587 .timeout = nvme_timeout, 1588 }; 1589 1590 static const struct blk_mq_ops nvme_mq_ops = { 1591 .queue_rq = nvme_queue_rq, 1592 .complete = nvme_pci_complete_rq, 1593 .commit_rqs = nvme_commit_rqs, 1594 .init_hctx = nvme_init_hctx, 1595 .init_request = nvme_init_request, 1596 .map_queues = nvme_pci_map_queues, 1597 .timeout = nvme_timeout, 1598 .poll = nvme_poll, 1599 }; 1600 1601 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1602 { 1603 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1604 /* 1605 * If the controller was reset during removal, it's possible 1606 * user requests may be waiting on a stopped queue. Start the 1607 * queue to flush these to completion. 1608 */ 1609 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1610 blk_cleanup_queue(dev->ctrl.admin_q); 1611 blk_mq_free_tag_set(&dev->admin_tagset); 1612 } 1613 } 1614 1615 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1616 { 1617 if (!dev->ctrl.admin_q) { 1618 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1619 dev->admin_tagset.nr_hw_queues = 1; 1620 1621 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1622 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1623 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1624 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1625 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1626 dev->admin_tagset.driver_data = dev; 1627 1628 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1629 return -ENOMEM; 1630 dev->ctrl.admin_tagset = &dev->admin_tagset; 1631 1632 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1633 if (IS_ERR(dev->ctrl.admin_q)) { 1634 blk_mq_free_tag_set(&dev->admin_tagset); 1635 return -ENOMEM; 1636 } 1637 if (!blk_get_queue(dev->ctrl.admin_q)) { 1638 nvme_dev_remove_admin(dev); 1639 dev->ctrl.admin_q = NULL; 1640 return -ENODEV; 1641 } 1642 } else 1643 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1644 1645 return 0; 1646 } 1647 1648 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1649 { 1650 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1651 } 1652 1653 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1654 { 1655 struct pci_dev *pdev = to_pci_dev(dev->dev); 1656 1657 if (size <= dev->bar_mapped_size) 1658 return 0; 1659 if (size > pci_resource_len(pdev, 0)) 1660 return -ENOMEM; 1661 if (dev->bar) 1662 iounmap(dev->bar); 1663 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1664 if (!dev->bar) { 1665 dev->bar_mapped_size = 0; 1666 return -ENOMEM; 1667 } 1668 dev->bar_mapped_size = size; 1669 dev->dbs = dev->bar + NVME_REG_DBS; 1670 1671 return 0; 1672 } 1673 1674 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1675 { 1676 int result; 1677 u32 aqa; 1678 struct nvme_queue *nvmeq; 1679 1680 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1681 if (result < 0) 1682 return result; 1683 1684 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1685 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1686 1687 if (dev->subsystem && 1688 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1689 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1690 1691 result = nvme_disable_ctrl(&dev->ctrl); 1692 if (result < 0) 1693 return result; 1694 1695 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1696 if (result) 1697 return result; 1698 1699 nvmeq = &dev->queues[0]; 1700 aqa = nvmeq->q_depth - 1; 1701 aqa |= aqa << 16; 1702 1703 writel(aqa, dev->bar + NVME_REG_AQA); 1704 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1705 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1706 1707 result = nvme_enable_ctrl(&dev->ctrl); 1708 if (result) 1709 return result; 1710 1711 nvmeq->cq_vector = 0; 1712 nvme_init_queue(nvmeq, 0); 1713 result = queue_request_irq(nvmeq); 1714 if (result) { 1715 dev->online_queues--; 1716 return result; 1717 } 1718 1719 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1720 return result; 1721 } 1722 1723 static int nvme_create_io_queues(struct nvme_dev *dev) 1724 { 1725 unsigned i, max, rw_queues; 1726 int ret = 0; 1727 1728 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1729 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1730 ret = -ENOMEM; 1731 break; 1732 } 1733 } 1734 1735 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1736 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1737 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1738 dev->io_queues[HCTX_TYPE_READ]; 1739 } else { 1740 rw_queues = max; 1741 } 1742 1743 for (i = dev->online_queues; i <= max; i++) { 1744 bool polled = i > rw_queues; 1745 1746 ret = nvme_create_queue(&dev->queues[i], i, polled); 1747 if (ret) 1748 break; 1749 } 1750 1751 /* 1752 * Ignore failing Create SQ/CQ commands, we can continue with less 1753 * than the desired amount of queues, and even a controller without 1754 * I/O queues can still be used to issue admin commands. This might 1755 * be useful to upgrade a buggy firmware for example. 1756 */ 1757 return ret >= 0 ? 0 : ret; 1758 } 1759 1760 static ssize_t nvme_cmb_show(struct device *dev, 1761 struct device_attribute *attr, 1762 char *buf) 1763 { 1764 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1765 1766 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1767 ndev->cmbloc, ndev->cmbsz); 1768 } 1769 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1770 1771 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1772 { 1773 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1774 1775 return 1ULL << (12 + 4 * szu); 1776 } 1777 1778 static u32 nvme_cmb_size(struct nvme_dev *dev) 1779 { 1780 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1781 } 1782 1783 static void nvme_map_cmb(struct nvme_dev *dev) 1784 { 1785 u64 size, offset; 1786 resource_size_t bar_size; 1787 struct pci_dev *pdev = to_pci_dev(dev->dev); 1788 int bar; 1789 1790 if (dev->cmb_size) 1791 return; 1792 1793 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1794 if (!dev->cmbsz) 1795 return; 1796 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1797 1798 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1799 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1800 bar = NVME_CMB_BIR(dev->cmbloc); 1801 bar_size = pci_resource_len(pdev, bar); 1802 1803 if (offset > bar_size) 1804 return; 1805 1806 /* 1807 * Controllers may support a CMB size larger than their BAR, 1808 * for example, due to being behind a bridge. Reduce the CMB to 1809 * the reported size of the BAR 1810 */ 1811 if (size > bar_size - offset) 1812 size = bar_size - offset; 1813 1814 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1815 dev_warn(dev->ctrl.device, 1816 "failed to register the CMB\n"); 1817 return; 1818 } 1819 1820 dev->cmb_size = size; 1821 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1822 1823 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1824 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1825 pci_p2pmem_publish(pdev, true); 1826 1827 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1828 &dev_attr_cmb.attr, NULL)) 1829 dev_warn(dev->ctrl.device, 1830 "failed to add sysfs attribute for CMB\n"); 1831 } 1832 1833 static inline void nvme_release_cmb(struct nvme_dev *dev) 1834 { 1835 if (dev->cmb_size) { 1836 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1837 &dev_attr_cmb.attr, NULL); 1838 dev->cmb_size = 0; 1839 } 1840 } 1841 1842 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1843 { 1844 u64 dma_addr = dev->host_mem_descs_dma; 1845 struct nvme_command c; 1846 int ret; 1847 1848 memset(&c, 0, sizeof(c)); 1849 c.features.opcode = nvme_admin_set_features; 1850 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1851 c.features.dword11 = cpu_to_le32(bits); 1852 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1853 ilog2(dev->ctrl.page_size)); 1854 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1855 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1856 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1857 1858 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1859 if (ret) { 1860 dev_warn(dev->ctrl.device, 1861 "failed to set host mem (err %d, flags %#x).\n", 1862 ret, bits); 1863 } 1864 return ret; 1865 } 1866 1867 static void nvme_free_host_mem(struct nvme_dev *dev) 1868 { 1869 int i; 1870 1871 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1872 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1873 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1874 1875 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1876 le64_to_cpu(desc->addr), 1877 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1878 } 1879 1880 kfree(dev->host_mem_desc_bufs); 1881 dev->host_mem_desc_bufs = NULL; 1882 dma_free_coherent(dev->dev, 1883 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1884 dev->host_mem_descs, dev->host_mem_descs_dma); 1885 dev->host_mem_descs = NULL; 1886 dev->nr_host_mem_descs = 0; 1887 } 1888 1889 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1890 u32 chunk_size) 1891 { 1892 struct nvme_host_mem_buf_desc *descs; 1893 u32 max_entries, len; 1894 dma_addr_t descs_dma; 1895 int i = 0; 1896 void **bufs; 1897 u64 size, tmp; 1898 1899 tmp = (preferred + chunk_size - 1); 1900 do_div(tmp, chunk_size); 1901 max_entries = tmp; 1902 1903 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1904 max_entries = dev->ctrl.hmmaxd; 1905 1906 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1907 &descs_dma, GFP_KERNEL); 1908 if (!descs) 1909 goto out; 1910 1911 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1912 if (!bufs) 1913 goto out_free_descs; 1914 1915 for (size = 0; size < preferred && i < max_entries; size += len) { 1916 dma_addr_t dma_addr; 1917 1918 len = min_t(u64, chunk_size, preferred - size); 1919 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1920 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1921 if (!bufs[i]) 1922 break; 1923 1924 descs[i].addr = cpu_to_le64(dma_addr); 1925 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1926 i++; 1927 } 1928 1929 if (!size) 1930 goto out_free_bufs; 1931 1932 dev->nr_host_mem_descs = i; 1933 dev->host_mem_size = size; 1934 dev->host_mem_descs = descs; 1935 dev->host_mem_descs_dma = descs_dma; 1936 dev->host_mem_desc_bufs = bufs; 1937 return 0; 1938 1939 out_free_bufs: 1940 while (--i >= 0) { 1941 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1942 1943 dma_free_attrs(dev->dev, size, bufs[i], 1944 le64_to_cpu(descs[i].addr), 1945 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1946 } 1947 1948 kfree(bufs); 1949 out_free_descs: 1950 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1951 descs_dma); 1952 out: 1953 dev->host_mem_descs = NULL; 1954 return -ENOMEM; 1955 } 1956 1957 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1958 { 1959 u32 chunk_size; 1960 1961 /* start big and work our way down */ 1962 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1963 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1964 chunk_size /= 2) { 1965 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1966 if (!min || dev->host_mem_size >= min) 1967 return 0; 1968 nvme_free_host_mem(dev); 1969 } 1970 } 1971 1972 return -ENOMEM; 1973 } 1974 1975 static int nvme_setup_host_mem(struct nvme_dev *dev) 1976 { 1977 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1978 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1979 u64 min = (u64)dev->ctrl.hmmin * 4096; 1980 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1981 int ret; 1982 1983 preferred = min(preferred, max); 1984 if (min > max) { 1985 dev_warn(dev->ctrl.device, 1986 "min host memory (%lld MiB) above limit (%d MiB).\n", 1987 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1988 nvme_free_host_mem(dev); 1989 return 0; 1990 } 1991 1992 /* 1993 * If we already have a buffer allocated check if we can reuse it. 1994 */ 1995 if (dev->host_mem_descs) { 1996 if (dev->host_mem_size >= min) 1997 enable_bits |= NVME_HOST_MEM_RETURN; 1998 else 1999 nvme_free_host_mem(dev); 2000 } 2001 2002 if (!dev->host_mem_descs) { 2003 if (nvme_alloc_host_mem(dev, min, preferred)) { 2004 dev_warn(dev->ctrl.device, 2005 "failed to allocate host memory buffer.\n"); 2006 return 0; /* controller must work without HMB */ 2007 } 2008 2009 dev_info(dev->ctrl.device, 2010 "allocated %lld MiB host memory buffer.\n", 2011 dev->host_mem_size >> ilog2(SZ_1M)); 2012 } 2013 2014 ret = nvme_set_host_mem(dev, enable_bits); 2015 if (ret) 2016 nvme_free_host_mem(dev); 2017 return ret; 2018 } 2019 2020 /* 2021 * nirqs is the number of interrupts available for write and read 2022 * queues. The core already reserved an interrupt for the admin queue. 2023 */ 2024 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2025 { 2026 struct nvme_dev *dev = affd->priv; 2027 unsigned int nr_read_queues; 2028 2029 /* 2030 * If there is no interupt available for queues, ensure that 2031 * the default queue is set to 1. The affinity set size is 2032 * also set to one, but the irq core ignores it for this case. 2033 * 2034 * If only one interrupt is available or 'write_queue' == 0, combine 2035 * write and read queues. 2036 * 2037 * If 'write_queues' > 0, ensure it leaves room for at least one read 2038 * queue. 2039 */ 2040 if (!nrirqs) { 2041 nrirqs = 1; 2042 nr_read_queues = 0; 2043 } else if (nrirqs == 1 || !write_queues) { 2044 nr_read_queues = 0; 2045 } else if (write_queues >= nrirqs) { 2046 nr_read_queues = 1; 2047 } else { 2048 nr_read_queues = nrirqs - write_queues; 2049 } 2050 2051 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2052 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2053 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2054 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2055 affd->nr_sets = nr_read_queues ? 2 : 1; 2056 } 2057 2058 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2059 { 2060 struct pci_dev *pdev = to_pci_dev(dev->dev); 2061 struct irq_affinity affd = { 2062 .pre_vectors = 1, 2063 .calc_sets = nvme_calc_irq_sets, 2064 .priv = dev, 2065 }; 2066 unsigned int irq_queues, this_p_queues; 2067 2068 /* 2069 * Poll queues don't need interrupts, but we need at least one IO 2070 * queue left over for non-polled IO. 2071 */ 2072 this_p_queues = poll_queues; 2073 if (this_p_queues >= nr_io_queues) { 2074 this_p_queues = nr_io_queues - 1; 2075 irq_queues = 1; 2076 } else { 2077 irq_queues = nr_io_queues - this_p_queues + 1; 2078 } 2079 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2080 2081 /* Initialize for the single interrupt case */ 2082 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2083 dev->io_queues[HCTX_TYPE_READ] = 0; 2084 2085 /* 2086 * Some Apple controllers require all queues to use the 2087 * first vector. 2088 */ 2089 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2090 irq_queues = 1; 2091 2092 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2093 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2094 } 2095 2096 static void nvme_disable_io_queues(struct nvme_dev *dev) 2097 { 2098 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2099 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2100 } 2101 2102 static int nvme_setup_io_queues(struct nvme_dev *dev) 2103 { 2104 struct nvme_queue *adminq = &dev->queues[0]; 2105 struct pci_dev *pdev = to_pci_dev(dev->dev); 2106 int result, nr_io_queues; 2107 unsigned long size; 2108 2109 nr_io_queues = max_io_queues(); 2110 2111 /* 2112 * If tags are shared with admin queue (Apple bug), then 2113 * make sure we only use one IO queue. 2114 */ 2115 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2116 nr_io_queues = 1; 2117 2118 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2119 if (result < 0) 2120 return result; 2121 2122 if (nr_io_queues == 0) 2123 return 0; 2124 2125 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2126 2127 if (dev->cmb_use_sqes) { 2128 result = nvme_cmb_qdepth(dev, nr_io_queues, 2129 sizeof(struct nvme_command)); 2130 if (result > 0) 2131 dev->q_depth = result; 2132 else 2133 dev->cmb_use_sqes = false; 2134 } 2135 2136 do { 2137 size = db_bar_size(dev, nr_io_queues); 2138 result = nvme_remap_bar(dev, size); 2139 if (!result) 2140 break; 2141 if (!--nr_io_queues) 2142 return -ENOMEM; 2143 } while (1); 2144 adminq->q_db = dev->dbs; 2145 2146 retry: 2147 /* Deregister the admin queue's interrupt */ 2148 pci_free_irq(pdev, 0, adminq); 2149 2150 /* 2151 * If we enable msix early due to not intx, disable it again before 2152 * setting up the full range we need. 2153 */ 2154 pci_free_irq_vectors(pdev); 2155 2156 result = nvme_setup_irqs(dev, nr_io_queues); 2157 if (result <= 0) 2158 return -EIO; 2159 2160 dev->num_vecs = result; 2161 result = max(result - 1, 1); 2162 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2163 2164 /* 2165 * Should investigate if there's a performance win from allocating 2166 * more queues than interrupt vectors; it might allow the submission 2167 * path to scale better, even if the receive path is limited by the 2168 * number of interrupts. 2169 */ 2170 result = queue_request_irq(adminq); 2171 if (result) 2172 return result; 2173 set_bit(NVMEQ_ENABLED, &adminq->flags); 2174 2175 result = nvme_create_io_queues(dev); 2176 if (result || dev->online_queues < 2) 2177 return result; 2178 2179 if (dev->online_queues - 1 < dev->max_qid) { 2180 nr_io_queues = dev->online_queues - 1; 2181 nvme_disable_io_queues(dev); 2182 nvme_suspend_io_queues(dev); 2183 goto retry; 2184 } 2185 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2186 dev->io_queues[HCTX_TYPE_DEFAULT], 2187 dev->io_queues[HCTX_TYPE_READ], 2188 dev->io_queues[HCTX_TYPE_POLL]); 2189 return 0; 2190 } 2191 2192 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2193 { 2194 struct nvme_queue *nvmeq = req->end_io_data; 2195 2196 blk_mq_free_request(req); 2197 complete(&nvmeq->delete_done); 2198 } 2199 2200 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2201 { 2202 struct nvme_queue *nvmeq = req->end_io_data; 2203 2204 if (error) 2205 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2206 2207 nvme_del_queue_end(req, error); 2208 } 2209 2210 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2211 { 2212 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2213 struct request *req; 2214 struct nvme_command cmd; 2215 2216 memset(&cmd, 0, sizeof(cmd)); 2217 cmd.delete_queue.opcode = opcode; 2218 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2219 2220 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2221 if (IS_ERR(req)) 2222 return PTR_ERR(req); 2223 2224 req->timeout = ADMIN_TIMEOUT; 2225 req->end_io_data = nvmeq; 2226 2227 init_completion(&nvmeq->delete_done); 2228 blk_execute_rq_nowait(q, NULL, req, false, 2229 opcode == nvme_admin_delete_cq ? 2230 nvme_del_cq_end : nvme_del_queue_end); 2231 return 0; 2232 } 2233 2234 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2235 { 2236 int nr_queues = dev->online_queues - 1, sent = 0; 2237 unsigned long timeout; 2238 2239 retry: 2240 timeout = ADMIN_TIMEOUT; 2241 while (nr_queues > 0) { 2242 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2243 break; 2244 nr_queues--; 2245 sent++; 2246 } 2247 while (sent) { 2248 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2249 2250 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2251 timeout); 2252 if (timeout == 0) 2253 return false; 2254 2255 sent--; 2256 if (nr_queues) 2257 goto retry; 2258 } 2259 return true; 2260 } 2261 2262 static void nvme_dev_add(struct nvme_dev *dev) 2263 { 2264 int ret; 2265 2266 if (!dev->ctrl.tagset) { 2267 dev->tagset.ops = &nvme_mq_ops; 2268 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2269 dev->tagset.nr_maps = 2; /* default + read */ 2270 if (dev->io_queues[HCTX_TYPE_POLL]) 2271 dev->tagset.nr_maps++; 2272 dev->tagset.timeout = NVME_IO_TIMEOUT; 2273 dev->tagset.numa_node = dev_to_node(dev->dev); 2274 dev->tagset.queue_depth = 2275 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2276 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2277 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2278 dev->tagset.driver_data = dev; 2279 2280 /* 2281 * Some Apple controllers requires tags to be unique 2282 * across admin and IO queue, so reserve the first 32 2283 * tags of the IO queue. 2284 */ 2285 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2286 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2287 2288 ret = blk_mq_alloc_tag_set(&dev->tagset); 2289 if (ret) { 2290 dev_warn(dev->ctrl.device, 2291 "IO queues tagset allocation failed %d\n", ret); 2292 return; 2293 } 2294 dev->ctrl.tagset = &dev->tagset; 2295 } else { 2296 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2297 2298 /* Free previously allocated queues that are no longer usable */ 2299 nvme_free_queues(dev, dev->online_queues); 2300 } 2301 2302 nvme_dbbuf_set(dev); 2303 } 2304 2305 static int nvme_pci_enable(struct nvme_dev *dev) 2306 { 2307 int result = -ENOMEM; 2308 struct pci_dev *pdev = to_pci_dev(dev->dev); 2309 2310 if (pci_enable_device_mem(pdev)) 2311 return result; 2312 2313 pci_set_master(pdev); 2314 2315 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2316 goto disable; 2317 2318 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2319 result = -ENODEV; 2320 goto disable; 2321 } 2322 2323 /* 2324 * Some devices and/or platforms don't advertise or work with INTx 2325 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2326 * adjust this later. 2327 */ 2328 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2329 if (result < 0) 2330 return result; 2331 2332 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2333 2334 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2335 io_queue_depth); 2336 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2337 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2338 dev->dbs = dev->bar + 4096; 2339 2340 /* 2341 * Some Apple controllers require a non-standard SQE size. 2342 * Interestingly they also seem to ignore the CC:IOSQES register 2343 * so we don't bother updating it here. 2344 */ 2345 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2346 dev->io_sqes = 7; 2347 else 2348 dev->io_sqes = NVME_NVM_IOSQES; 2349 2350 /* 2351 * Temporary fix for the Apple controller found in the MacBook8,1 and 2352 * some MacBook7,1 to avoid controller resets and data loss. 2353 */ 2354 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2355 dev->q_depth = 2; 2356 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2357 "set queue depth=%u to work around controller resets\n", 2358 dev->q_depth); 2359 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2360 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2361 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2362 dev->q_depth = 64; 2363 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2364 "set queue depth=%u\n", dev->q_depth); 2365 } 2366 2367 /* 2368 * Controllers with the shared tags quirk need the IO queue to be 2369 * big enough so that we get 32 tags for the admin queue 2370 */ 2371 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2372 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2373 dev->q_depth = NVME_AQ_DEPTH + 2; 2374 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2375 dev->q_depth); 2376 } 2377 2378 2379 nvme_map_cmb(dev); 2380 2381 pci_enable_pcie_error_reporting(pdev); 2382 pci_save_state(pdev); 2383 return 0; 2384 2385 disable: 2386 pci_disable_device(pdev); 2387 return result; 2388 } 2389 2390 static void nvme_dev_unmap(struct nvme_dev *dev) 2391 { 2392 if (dev->bar) 2393 iounmap(dev->bar); 2394 pci_release_mem_regions(to_pci_dev(dev->dev)); 2395 } 2396 2397 static void nvme_pci_disable(struct nvme_dev *dev) 2398 { 2399 struct pci_dev *pdev = to_pci_dev(dev->dev); 2400 2401 pci_free_irq_vectors(pdev); 2402 2403 if (pci_is_enabled(pdev)) { 2404 pci_disable_pcie_error_reporting(pdev); 2405 pci_disable_device(pdev); 2406 } 2407 } 2408 2409 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2410 { 2411 bool dead = true, freeze = false; 2412 struct pci_dev *pdev = to_pci_dev(dev->dev); 2413 2414 mutex_lock(&dev->shutdown_lock); 2415 if (pci_is_enabled(pdev)) { 2416 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2417 2418 if (dev->ctrl.state == NVME_CTRL_LIVE || 2419 dev->ctrl.state == NVME_CTRL_RESETTING) { 2420 freeze = true; 2421 nvme_start_freeze(&dev->ctrl); 2422 } 2423 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2424 pdev->error_state != pci_channel_io_normal); 2425 } 2426 2427 /* 2428 * Give the controller a chance to complete all entered requests if 2429 * doing a safe shutdown. 2430 */ 2431 if (!dead && shutdown && freeze) 2432 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2433 2434 nvme_stop_queues(&dev->ctrl); 2435 2436 if (!dead && dev->ctrl.queue_count > 0) { 2437 nvme_disable_io_queues(dev); 2438 nvme_disable_admin_queue(dev, shutdown); 2439 } 2440 nvme_suspend_io_queues(dev); 2441 nvme_suspend_queue(&dev->queues[0]); 2442 nvme_pci_disable(dev); 2443 nvme_reap_pending_cqes(dev); 2444 2445 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2446 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2447 blk_mq_tagset_wait_completed_request(&dev->tagset); 2448 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2449 2450 /* 2451 * The driver will not be starting up queues again if shutting down so 2452 * must flush all entered requests to their failed completion to avoid 2453 * deadlocking blk-mq hot-cpu notifier. 2454 */ 2455 if (shutdown) { 2456 nvme_start_queues(&dev->ctrl); 2457 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2458 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2459 } 2460 mutex_unlock(&dev->shutdown_lock); 2461 } 2462 2463 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2464 { 2465 if (!nvme_wait_reset(&dev->ctrl)) 2466 return -EBUSY; 2467 nvme_dev_disable(dev, shutdown); 2468 return 0; 2469 } 2470 2471 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2472 { 2473 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2474 PAGE_SIZE, PAGE_SIZE, 0); 2475 if (!dev->prp_page_pool) 2476 return -ENOMEM; 2477 2478 /* Optimisation for I/Os between 4k and 128k */ 2479 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2480 256, 256, 0); 2481 if (!dev->prp_small_pool) { 2482 dma_pool_destroy(dev->prp_page_pool); 2483 return -ENOMEM; 2484 } 2485 return 0; 2486 } 2487 2488 static void nvme_release_prp_pools(struct nvme_dev *dev) 2489 { 2490 dma_pool_destroy(dev->prp_page_pool); 2491 dma_pool_destroy(dev->prp_small_pool); 2492 } 2493 2494 static void nvme_free_tagset(struct nvme_dev *dev) 2495 { 2496 if (dev->tagset.tags) 2497 blk_mq_free_tag_set(&dev->tagset); 2498 dev->ctrl.tagset = NULL; 2499 } 2500 2501 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2502 { 2503 struct nvme_dev *dev = to_nvme_dev(ctrl); 2504 2505 nvme_dbbuf_dma_free(dev); 2506 put_device(dev->dev); 2507 nvme_free_tagset(dev); 2508 if (dev->ctrl.admin_q) 2509 blk_put_queue(dev->ctrl.admin_q); 2510 kfree(dev->queues); 2511 free_opal_dev(dev->ctrl.opal_dev); 2512 mempool_destroy(dev->iod_mempool); 2513 kfree(dev); 2514 } 2515 2516 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2517 { 2518 /* 2519 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2520 * may be holding this pci_dev's device lock. 2521 */ 2522 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2523 nvme_get_ctrl(&dev->ctrl); 2524 nvme_dev_disable(dev, false); 2525 nvme_kill_queues(&dev->ctrl); 2526 if (!queue_work(nvme_wq, &dev->remove_work)) 2527 nvme_put_ctrl(&dev->ctrl); 2528 } 2529 2530 static void nvme_reset_work(struct work_struct *work) 2531 { 2532 struct nvme_dev *dev = 2533 container_of(work, struct nvme_dev, ctrl.reset_work); 2534 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2535 int result; 2536 2537 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2538 result = -ENODEV; 2539 goto out; 2540 } 2541 2542 /* 2543 * If we're called to reset a live controller first shut it down before 2544 * moving on. 2545 */ 2546 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2547 nvme_dev_disable(dev, false); 2548 nvme_sync_queues(&dev->ctrl); 2549 2550 mutex_lock(&dev->shutdown_lock); 2551 result = nvme_pci_enable(dev); 2552 if (result) 2553 goto out_unlock; 2554 2555 result = nvme_pci_configure_admin_queue(dev); 2556 if (result) 2557 goto out_unlock; 2558 2559 result = nvme_alloc_admin_tags(dev); 2560 if (result) 2561 goto out_unlock; 2562 2563 /* 2564 * Limit the max command size to prevent iod->sg allocations going 2565 * over a single page. 2566 */ 2567 dev->ctrl.max_hw_sectors = min_t(u32, 2568 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2569 dev->ctrl.max_segments = NVME_MAX_SEGS; 2570 2571 /* 2572 * Don't limit the IOMMU merged segment size. 2573 */ 2574 dma_set_max_seg_size(dev->dev, 0xffffffff); 2575 2576 mutex_unlock(&dev->shutdown_lock); 2577 2578 /* 2579 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2580 * initializing procedure here. 2581 */ 2582 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2583 dev_warn(dev->ctrl.device, 2584 "failed to mark controller CONNECTING\n"); 2585 result = -EBUSY; 2586 goto out; 2587 } 2588 2589 result = nvme_init_identify(&dev->ctrl); 2590 if (result) 2591 goto out; 2592 2593 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2594 if (!dev->ctrl.opal_dev) 2595 dev->ctrl.opal_dev = 2596 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2597 else if (was_suspend) 2598 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2599 } else { 2600 free_opal_dev(dev->ctrl.opal_dev); 2601 dev->ctrl.opal_dev = NULL; 2602 } 2603 2604 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2605 result = nvme_dbbuf_dma_alloc(dev); 2606 if (result) 2607 dev_warn(dev->dev, 2608 "unable to allocate dma for dbbuf\n"); 2609 } 2610 2611 if (dev->ctrl.hmpre) { 2612 result = nvme_setup_host_mem(dev); 2613 if (result < 0) 2614 goto out; 2615 } 2616 2617 result = nvme_setup_io_queues(dev); 2618 if (result) 2619 goto out; 2620 2621 /* 2622 * Keep the controller around but remove all namespaces if we don't have 2623 * any working I/O queue. 2624 */ 2625 if (dev->online_queues < 2) { 2626 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2627 nvme_kill_queues(&dev->ctrl); 2628 nvme_remove_namespaces(&dev->ctrl); 2629 nvme_free_tagset(dev); 2630 } else { 2631 nvme_start_queues(&dev->ctrl); 2632 nvme_wait_freeze(&dev->ctrl); 2633 nvme_dev_add(dev); 2634 nvme_unfreeze(&dev->ctrl); 2635 } 2636 2637 /* 2638 * If only admin queue live, keep it to do further investigation or 2639 * recovery. 2640 */ 2641 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2642 dev_warn(dev->ctrl.device, 2643 "failed to mark controller live state\n"); 2644 result = -ENODEV; 2645 goto out; 2646 } 2647 2648 nvme_start_ctrl(&dev->ctrl); 2649 return; 2650 2651 out_unlock: 2652 mutex_unlock(&dev->shutdown_lock); 2653 out: 2654 if (result) 2655 dev_warn(dev->ctrl.device, 2656 "Removing after probe failure status: %d\n", result); 2657 nvme_remove_dead_ctrl(dev); 2658 } 2659 2660 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2661 { 2662 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2663 struct pci_dev *pdev = to_pci_dev(dev->dev); 2664 2665 if (pci_get_drvdata(pdev)) 2666 device_release_driver(&pdev->dev); 2667 nvme_put_ctrl(&dev->ctrl); 2668 } 2669 2670 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2671 { 2672 *val = readl(to_nvme_dev(ctrl)->bar + off); 2673 return 0; 2674 } 2675 2676 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2677 { 2678 writel(val, to_nvme_dev(ctrl)->bar + off); 2679 return 0; 2680 } 2681 2682 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2683 { 2684 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2685 return 0; 2686 } 2687 2688 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2689 { 2690 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2691 2692 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2693 } 2694 2695 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2696 .name = "pcie", 2697 .module = THIS_MODULE, 2698 .flags = NVME_F_METADATA_SUPPORTED | 2699 NVME_F_PCI_P2PDMA, 2700 .reg_read32 = nvme_pci_reg_read32, 2701 .reg_write32 = nvme_pci_reg_write32, 2702 .reg_read64 = nvme_pci_reg_read64, 2703 .free_ctrl = nvme_pci_free_ctrl, 2704 .submit_async_event = nvme_pci_submit_async_event, 2705 .get_address = nvme_pci_get_address, 2706 }; 2707 2708 static int nvme_dev_map(struct nvme_dev *dev) 2709 { 2710 struct pci_dev *pdev = to_pci_dev(dev->dev); 2711 2712 if (pci_request_mem_regions(pdev, "nvme")) 2713 return -ENODEV; 2714 2715 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2716 goto release; 2717 2718 return 0; 2719 release: 2720 pci_release_mem_regions(pdev); 2721 return -ENODEV; 2722 } 2723 2724 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2725 { 2726 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2727 /* 2728 * Several Samsung devices seem to drop off the PCIe bus 2729 * randomly when APST is on and uses the deepest sleep state. 2730 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2731 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2732 * 950 PRO 256GB", but it seems to be restricted to two Dell 2733 * laptops. 2734 */ 2735 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2736 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2737 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2738 return NVME_QUIRK_NO_DEEPEST_PS; 2739 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2740 /* 2741 * Samsung SSD 960 EVO drops off the PCIe bus after system 2742 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2743 * within few minutes after bootup on a Coffee Lake board - 2744 * ASUS PRIME Z370-A 2745 */ 2746 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2747 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2748 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2749 return NVME_QUIRK_NO_APST; 2750 } 2751 2752 return 0; 2753 } 2754 2755 static void nvme_async_probe(void *data, async_cookie_t cookie) 2756 { 2757 struct nvme_dev *dev = data; 2758 2759 flush_work(&dev->ctrl.reset_work); 2760 flush_work(&dev->ctrl.scan_work); 2761 nvme_put_ctrl(&dev->ctrl); 2762 } 2763 2764 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2765 { 2766 int node, result = -ENOMEM; 2767 struct nvme_dev *dev; 2768 unsigned long quirks = id->driver_data; 2769 size_t alloc_size; 2770 2771 node = dev_to_node(&pdev->dev); 2772 if (node == NUMA_NO_NODE) 2773 set_dev_node(&pdev->dev, first_memory_node); 2774 2775 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2776 if (!dev) 2777 return -ENOMEM; 2778 2779 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2780 GFP_KERNEL, node); 2781 if (!dev->queues) 2782 goto free; 2783 2784 dev->dev = get_device(&pdev->dev); 2785 pci_set_drvdata(pdev, dev); 2786 2787 result = nvme_dev_map(dev); 2788 if (result) 2789 goto put_pci; 2790 2791 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2792 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2793 mutex_init(&dev->shutdown_lock); 2794 2795 result = nvme_setup_prp_pools(dev); 2796 if (result) 2797 goto unmap; 2798 2799 quirks |= check_vendor_combination_bug(pdev); 2800 2801 /* 2802 * Double check that our mempool alloc size will cover the biggest 2803 * command we support. 2804 */ 2805 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2806 NVME_MAX_SEGS, true); 2807 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2808 2809 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2810 mempool_kfree, 2811 (void *) alloc_size, 2812 GFP_KERNEL, node); 2813 if (!dev->iod_mempool) { 2814 result = -ENOMEM; 2815 goto release_pools; 2816 } 2817 2818 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2819 quirks); 2820 if (result) 2821 goto release_mempool; 2822 2823 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2824 2825 nvme_reset_ctrl(&dev->ctrl); 2826 nvme_get_ctrl(&dev->ctrl); 2827 async_schedule(nvme_async_probe, dev); 2828 2829 return 0; 2830 2831 release_mempool: 2832 mempool_destroy(dev->iod_mempool); 2833 release_pools: 2834 nvme_release_prp_pools(dev); 2835 unmap: 2836 nvme_dev_unmap(dev); 2837 put_pci: 2838 put_device(dev->dev); 2839 free: 2840 kfree(dev->queues); 2841 kfree(dev); 2842 return result; 2843 } 2844 2845 static void nvme_reset_prepare(struct pci_dev *pdev) 2846 { 2847 struct nvme_dev *dev = pci_get_drvdata(pdev); 2848 2849 /* 2850 * We don't need to check the return value from waiting for the reset 2851 * state as pci_dev device lock is held, making it impossible to race 2852 * with ->remove(). 2853 */ 2854 nvme_disable_prepare_reset(dev, false); 2855 nvme_sync_queues(&dev->ctrl); 2856 } 2857 2858 static void nvme_reset_done(struct pci_dev *pdev) 2859 { 2860 struct nvme_dev *dev = pci_get_drvdata(pdev); 2861 2862 if (!nvme_try_sched_reset(&dev->ctrl)) 2863 flush_work(&dev->ctrl.reset_work); 2864 } 2865 2866 static void nvme_shutdown(struct pci_dev *pdev) 2867 { 2868 struct nvme_dev *dev = pci_get_drvdata(pdev); 2869 nvme_disable_prepare_reset(dev, true); 2870 } 2871 2872 /* 2873 * The driver's remove may be called on a device in a partially initialized 2874 * state. This function must not have any dependencies on the device state in 2875 * order to proceed. 2876 */ 2877 static void nvme_remove(struct pci_dev *pdev) 2878 { 2879 struct nvme_dev *dev = pci_get_drvdata(pdev); 2880 2881 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2882 pci_set_drvdata(pdev, NULL); 2883 2884 if (!pci_device_is_present(pdev)) { 2885 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2886 nvme_dev_disable(dev, true); 2887 nvme_dev_remove_admin(dev); 2888 } 2889 2890 flush_work(&dev->ctrl.reset_work); 2891 nvme_stop_ctrl(&dev->ctrl); 2892 nvme_remove_namespaces(&dev->ctrl); 2893 nvme_dev_disable(dev, true); 2894 nvme_release_cmb(dev); 2895 nvme_free_host_mem(dev); 2896 nvme_dev_remove_admin(dev); 2897 nvme_free_queues(dev, 0); 2898 nvme_uninit_ctrl(&dev->ctrl); 2899 nvme_release_prp_pools(dev); 2900 nvme_dev_unmap(dev); 2901 nvme_put_ctrl(&dev->ctrl); 2902 } 2903 2904 #ifdef CONFIG_PM_SLEEP 2905 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2906 { 2907 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2908 } 2909 2910 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2911 { 2912 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2913 } 2914 2915 static int nvme_resume(struct device *dev) 2916 { 2917 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2918 struct nvme_ctrl *ctrl = &ndev->ctrl; 2919 2920 if (ndev->last_ps == U32_MAX || 2921 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2922 return nvme_try_sched_reset(&ndev->ctrl); 2923 return 0; 2924 } 2925 2926 static int nvme_suspend(struct device *dev) 2927 { 2928 struct pci_dev *pdev = to_pci_dev(dev); 2929 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2930 struct nvme_ctrl *ctrl = &ndev->ctrl; 2931 int ret = -EBUSY; 2932 2933 ndev->last_ps = U32_MAX; 2934 2935 /* 2936 * The platform does not remove power for a kernel managed suspend so 2937 * use host managed nvme power settings for lowest idle power if 2938 * possible. This should have quicker resume latency than a full device 2939 * shutdown. But if the firmware is involved after the suspend or the 2940 * device does not support any non-default power states, shut down the 2941 * device fully. 2942 * 2943 * If ASPM is not enabled for the device, shut down the device and allow 2944 * the PCI bus layer to put it into D3 in order to take the PCIe link 2945 * down, so as to allow the platform to achieve its minimum low-power 2946 * state (which may not be possible if the link is up). 2947 */ 2948 if (pm_suspend_via_firmware() || !ctrl->npss || 2949 !pcie_aspm_enabled(pdev) || 2950 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2951 return nvme_disable_prepare_reset(ndev, true); 2952 2953 nvme_start_freeze(ctrl); 2954 nvme_wait_freeze(ctrl); 2955 nvme_sync_queues(ctrl); 2956 2957 if (ctrl->state != NVME_CTRL_LIVE) 2958 goto unfreeze; 2959 2960 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2961 if (ret < 0) 2962 goto unfreeze; 2963 2964 /* 2965 * A saved state prevents pci pm from generically controlling the 2966 * device's power. If we're using protocol specific settings, we don't 2967 * want pci interfering. 2968 */ 2969 pci_save_state(pdev); 2970 2971 ret = nvme_set_power_state(ctrl, ctrl->npss); 2972 if (ret < 0) 2973 goto unfreeze; 2974 2975 if (ret) { 2976 /* discard the saved state */ 2977 pci_load_saved_state(pdev, NULL); 2978 2979 /* 2980 * Clearing npss forces a controller reset on resume. The 2981 * correct value will be rediscovered then. 2982 */ 2983 ret = nvme_disable_prepare_reset(ndev, true); 2984 ctrl->npss = 0; 2985 } 2986 unfreeze: 2987 nvme_unfreeze(ctrl); 2988 return ret; 2989 } 2990 2991 static int nvme_simple_suspend(struct device *dev) 2992 { 2993 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2994 return nvme_disable_prepare_reset(ndev, true); 2995 } 2996 2997 static int nvme_simple_resume(struct device *dev) 2998 { 2999 struct pci_dev *pdev = to_pci_dev(dev); 3000 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3001 3002 return nvme_try_sched_reset(&ndev->ctrl); 3003 } 3004 3005 static const struct dev_pm_ops nvme_dev_pm_ops = { 3006 .suspend = nvme_suspend, 3007 .resume = nvme_resume, 3008 .freeze = nvme_simple_suspend, 3009 .thaw = nvme_simple_resume, 3010 .poweroff = nvme_simple_suspend, 3011 .restore = nvme_simple_resume, 3012 }; 3013 #endif /* CONFIG_PM_SLEEP */ 3014 3015 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3016 pci_channel_state_t state) 3017 { 3018 struct nvme_dev *dev = pci_get_drvdata(pdev); 3019 3020 /* 3021 * A frozen channel requires a reset. When detected, this method will 3022 * shutdown the controller to quiesce. The controller will be restarted 3023 * after the slot reset through driver's slot_reset callback. 3024 */ 3025 switch (state) { 3026 case pci_channel_io_normal: 3027 return PCI_ERS_RESULT_CAN_RECOVER; 3028 case pci_channel_io_frozen: 3029 dev_warn(dev->ctrl.device, 3030 "frozen state error detected, reset controller\n"); 3031 nvme_dev_disable(dev, false); 3032 return PCI_ERS_RESULT_NEED_RESET; 3033 case pci_channel_io_perm_failure: 3034 dev_warn(dev->ctrl.device, 3035 "failure state error detected, request disconnect\n"); 3036 return PCI_ERS_RESULT_DISCONNECT; 3037 } 3038 return PCI_ERS_RESULT_NEED_RESET; 3039 } 3040 3041 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3042 { 3043 struct nvme_dev *dev = pci_get_drvdata(pdev); 3044 3045 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3046 pci_restore_state(pdev); 3047 nvme_reset_ctrl(&dev->ctrl); 3048 return PCI_ERS_RESULT_RECOVERED; 3049 } 3050 3051 static void nvme_error_resume(struct pci_dev *pdev) 3052 { 3053 struct nvme_dev *dev = pci_get_drvdata(pdev); 3054 3055 flush_work(&dev->ctrl.reset_work); 3056 } 3057 3058 static const struct pci_error_handlers nvme_err_handler = { 3059 .error_detected = nvme_error_detected, 3060 .slot_reset = nvme_slot_reset, 3061 .resume = nvme_error_resume, 3062 .reset_prepare = nvme_reset_prepare, 3063 .reset_done = nvme_reset_done, 3064 }; 3065 3066 static const struct pci_device_id nvme_id_table[] = { 3067 { PCI_VDEVICE(INTEL, 0x0953), 3068 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3069 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3070 { PCI_VDEVICE(INTEL, 0x0a53), 3071 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3072 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3073 { PCI_VDEVICE(INTEL, 0x0a54), 3074 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3075 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3076 { PCI_VDEVICE(INTEL, 0x0a55), 3077 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3078 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3079 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3080 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3081 NVME_QUIRK_MEDIUM_PRIO_SQ | 3082 NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 3083 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3084 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3085 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3086 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3087 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3088 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3089 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3090 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3091 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3092 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3093 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3094 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3095 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3096 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3097 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3098 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3099 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3100 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3101 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3102 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3103 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3104 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3105 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3106 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3107 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3108 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3109 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3110 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3111 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3112 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3113 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3114 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3115 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3116 NVME_QUIRK_128_BYTES_SQES | 3117 NVME_QUIRK_SHARED_TAGS }, 3118 { 0, } 3119 }; 3120 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3121 3122 static struct pci_driver nvme_driver = { 3123 .name = "nvme", 3124 .id_table = nvme_id_table, 3125 .probe = nvme_probe, 3126 .remove = nvme_remove, 3127 .shutdown = nvme_shutdown, 3128 #ifdef CONFIG_PM_SLEEP 3129 .driver = { 3130 .pm = &nvme_dev_pm_ops, 3131 }, 3132 #endif 3133 .sriov_configure = pci_sriov_configure_simple, 3134 .err_handler = &nvme_err_handler, 3135 }; 3136 3137 static int __init nvme_init(void) 3138 { 3139 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3140 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3141 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3142 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3143 3144 write_queues = min(write_queues, num_possible_cpus()); 3145 poll_queues = min(poll_queues, num_possible_cpus()); 3146 return pci_register_driver(&nvme_driver); 3147 } 3148 3149 static void __exit nvme_exit(void) 3150 { 3151 pci_unregister_driver(&nvme_driver); 3152 flush_workqueue(nvme_wq); 3153 } 3154 3155 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3156 MODULE_LICENSE("GPL"); 3157 MODULE_VERSION("1.0"); 3158 module_init(nvme_init); 3159 module_exit(nvme_exit); 3160