1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/blkdev.h> 17 #include <linux/blk-mq.h> 18 #include <linux/cpu.h> 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/fs.h> 22 #include <linux/genhd.h> 23 #include <linux/hdreg.h> 24 #include <linux/idr.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kdev_t.h> 29 #include <linux/kthread.h> 30 #include <linux/kernel.h> 31 #include <linux/mm.h> 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/pci.h> 35 #include <linux/poison.h> 36 #include <linux/ptrace.h> 37 #include <linux/sched.h> 38 #include <linux/slab.h> 39 #include <linux/t10-pi.h> 40 #include <linux/types.h> 41 #include <linux/io-64-nonatomic-lo-hi.h> 42 #include <asm/unaligned.h> 43 44 #include "nvme.h" 45 46 #define NVME_Q_DEPTH 1024 47 #define NVME_AQ_DEPTH 256 48 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 49 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 50 51 unsigned char admin_timeout = 60; 52 module_param(admin_timeout, byte, 0644); 53 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); 54 55 unsigned char nvme_io_timeout = 30; 56 module_param_named(io_timeout, nvme_io_timeout, byte, 0644); 57 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); 58 59 unsigned char shutdown_timeout = 5; 60 module_param(shutdown_timeout, byte, 0644); 61 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); 62 63 static int use_threaded_interrupts; 64 module_param(use_threaded_interrupts, int, 0); 65 66 static bool use_cmb_sqes = true; 67 module_param(use_cmb_sqes, bool, 0644); 68 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 69 70 static LIST_HEAD(dev_list); 71 static struct task_struct *nvme_thread; 72 static struct workqueue_struct *nvme_workq; 73 static wait_queue_head_t nvme_kthread_wait; 74 75 struct nvme_dev; 76 struct nvme_queue; 77 struct nvme_iod; 78 79 static int __nvme_reset(struct nvme_dev *dev); 80 static int nvme_reset(struct nvme_dev *dev); 81 static void nvme_process_cq(struct nvme_queue *nvmeq); 82 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); 83 static void nvme_dead_ctrl(struct nvme_dev *dev); 84 85 struct async_cmd_info { 86 struct kthread_work work; 87 struct kthread_worker *worker; 88 struct request *req; 89 u32 result; 90 int status; 91 void *ctx; 92 }; 93 94 /* 95 * Represents an NVM Express device. Each nvme_dev is a PCI function. 96 */ 97 struct nvme_dev { 98 struct list_head node; 99 struct nvme_queue **queues; 100 struct blk_mq_tag_set tagset; 101 struct blk_mq_tag_set admin_tagset; 102 u32 __iomem *dbs; 103 struct device *dev; 104 struct dma_pool *prp_page_pool; 105 struct dma_pool *prp_small_pool; 106 unsigned queue_count; 107 unsigned online_queues; 108 unsigned max_qid; 109 int q_depth; 110 u32 db_stride; 111 struct msix_entry *entry; 112 void __iomem *bar; 113 struct work_struct reset_work; 114 struct work_struct probe_work; 115 struct work_struct scan_work; 116 bool subsystem; 117 void __iomem *cmb; 118 dma_addr_t cmb_dma_addr; 119 u64 cmb_size; 120 u32 cmbsz; 121 122 struct nvme_ctrl ctrl; 123 }; 124 125 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 126 { 127 return container_of(ctrl, struct nvme_dev, ctrl); 128 } 129 130 /* 131 * An NVM Express queue. Each device has at least two (one for admin 132 * commands and one for I/O commands). 133 */ 134 struct nvme_queue { 135 struct device *q_dmadev; 136 struct nvme_dev *dev; 137 char irqname[24]; /* nvme4294967295-65535\0 */ 138 spinlock_t q_lock; 139 struct nvme_command *sq_cmds; 140 struct nvme_command __iomem *sq_cmds_io; 141 volatile struct nvme_completion *cqes; 142 struct blk_mq_tags **tags; 143 dma_addr_t sq_dma_addr; 144 dma_addr_t cq_dma_addr; 145 u32 __iomem *q_db; 146 u16 q_depth; 147 s16 cq_vector; 148 u16 sq_head; 149 u16 sq_tail; 150 u16 cq_head; 151 u16 qid; 152 u8 cq_phase; 153 u8 cqe_seen; 154 struct async_cmd_info cmdinfo; 155 }; 156 157 /* 158 * The nvme_iod describes the data in an I/O, including the list of PRP 159 * entries. You can't see it in this data structure because C doesn't let 160 * me express that. Use nvme_alloc_iod to ensure there's enough space 161 * allocated to store the PRP list. 162 */ 163 struct nvme_iod { 164 unsigned long private; /* For the use of the submitter of the I/O */ 165 int npages; /* In the PRP list. 0 means small pool in use */ 166 int offset; /* Of PRP list */ 167 int nents; /* Used in scatterlist */ 168 int length; /* Of data, in bytes */ 169 dma_addr_t first_dma; 170 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ 171 struct scatterlist sg[0]; 172 }; 173 174 /* 175 * Check we didin't inadvertently grow the command struct 176 */ 177 static inline void _nvme_check_size(void) 178 { 179 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 180 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 181 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 182 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 183 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 184 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 185 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 186 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 187 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); 188 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); 189 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 190 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 191 } 192 193 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, 194 struct nvme_completion *); 195 196 struct nvme_cmd_info { 197 nvme_completion_fn fn; 198 void *ctx; 199 int aborted; 200 struct nvme_queue *nvmeq; 201 struct nvme_iod iod[0]; 202 }; 203 204 /* 205 * Max size of iod being embedded in the request payload 206 */ 207 #define NVME_INT_PAGES 2 208 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 209 #define NVME_INT_MASK 0x01 210 211 /* 212 * Will slightly overestimate the number of pages needed. This is OK 213 * as it only leads to a small amount of wasted memory for the lifetime of 214 * the I/O. 215 */ 216 static int nvme_npages(unsigned size, struct nvme_dev *dev) 217 { 218 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 219 dev->ctrl.page_size); 220 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 221 } 222 223 static unsigned int nvme_cmd_size(struct nvme_dev *dev) 224 { 225 unsigned int ret = sizeof(struct nvme_cmd_info); 226 227 ret += sizeof(struct nvme_iod); 228 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); 229 ret += sizeof(struct scatterlist) * NVME_INT_PAGES; 230 231 return ret; 232 } 233 234 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 235 unsigned int hctx_idx) 236 { 237 struct nvme_dev *dev = data; 238 struct nvme_queue *nvmeq = dev->queues[0]; 239 240 WARN_ON(hctx_idx != 0); 241 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 242 WARN_ON(nvmeq->tags); 243 244 hctx->driver_data = nvmeq; 245 nvmeq->tags = &dev->admin_tagset.tags[0]; 246 return 0; 247 } 248 249 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 250 { 251 struct nvme_queue *nvmeq = hctx->driver_data; 252 253 nvmeq->tags = NULL; 254 } 255 256 static int nvme_admin_init_request(void *data, struct request *req, 257 unsigned int hctx_idx, unsigned int rq_idx, 258 unsigned int numa_node) 259 { 260 struct nvme_dev *dev = data; 261 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 262 struct nvme_queue *nvmeq = dev->queues[0]; 263 264 BUG_ON(!nvmeq); 265 cmd->nvmeq = nvmeq; 266 return 0; 267 } 268 269 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 270 unsigned int hctx_idx) 271 { 272 struct nvme_dev *dev = data; 273 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 274 275 if (!nvmeq->tags) 276 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 277 278 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 279 hctx->driver_data = nvmeq; 280 return 0; 281 } 282 283 static int nvme_init_request(void *data, struct request *req, 284 unsigned int hctx_idx, unsigned int rq_idx, 285 unsigned int numa_node) 286 { 287 struct nvme_dev *dev = data; 288 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 289 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 290 291 BUG_ON(!nvmeq); 292 cmd->nvmeq = nvmeq; 293 return 0; 294 } 295 296 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, 297 nvme_completion_fn handler) 298 { 299 cmd->fn = handler; 300 cmd->ctx = ctx; 301 cmd->aborted = 0; 302 blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); 303 } 304 305 static void *iod_get_private(struct nvme_iod *iod) 306 { 307 return (void *) (iod->private & ~0x1UL); 308 } 309 310 /* 311 * If bit 0 is set, the iod is embedded in the request payload. 312 */ 313 static bool iod_should_kfree(struct nvme_iod *iod) 314 { 315 return (iod->private & NVME_INT_MASK) == 0; 316 } 317 318 /* Special values must be less than 0x1000 */ 319 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) 320 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) 321 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) 322 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) 323 324 static void special_completion(struct nvme_queue *nvmeq, void *ctx, 325 struct nvme_completion *cqe) 326 { 327 if (ctx == CMD_CTX_CANCELLED) 328 return; 329 if (ctx == CMD_CTX_COMPLETED) { 330 dev_warn(nvmeq->q_dmadev, 331 "completed id %d twice on queue %d\n", 332 cqe->command_id, le16_to_cpup(&cqe->sq_id)); 333 return; 334 } 335 if (ctx == CMD_CTX_INVALID) { 336 dev_warn(nvmeq->q_dmadev, 337 "invalid id %d completed on queue %d\n", 338 cqe->command_id, le16_to_cpup(&cqe->sq_id)); 339 return; 340 } 341 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); 342 } 343 344 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) 345 { 346 void *ctx; 347 348 if (fn) 349 *fn = cmd->fn; 350 ctx = cmd->ctx; 351 cmd->fn = special_completion; 352 cmd->ctx = CMD_CTX_CANCELLED; 353 return ctx; 354 } 355 356 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, 357 struct nvme_completion *cqe) 358 { 359 u32 result = le32_to_cpup(&cqe->result); 360 u16 status = le16_to_cpup(&cqe->status) >> 1; 361 362 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) 363 ++nvmeq->dev->ctrl.event_limit; 364 if (status != NVME_SC_SUCCESS) 365 return; 366 367 switch (result & 0xff07) { 368 case NVME_AER_NOTICE_NS_CHANGED: 369 dev_info(nvmeq->q_dmadev, "rescanning\n"); 370 schedule_work(&nvmeq->dev->scan_work); 371 default: 372 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); 373 } 374 } 375 376 static void abort_completion(struct nvme_queue *nvmeq, void *ctx, 377 struct nvme_completion *cqe) 378 { 379 struct request *req = ctx; 380 381 u16 status = le16_to_cpup(&cqe->status) >> 1; 382 u32 result = le32_to_cpup(&cqe->result); 383 384 blk_mq_free_request(req); 385 386 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); 387 ++nvmeq->dev->ctrl.abort_limit; 388 } 389 390 static void async_completion(struct nvme_queue *nvmeq, void *ctx, 391 struct nvme_completion *cqe) 392 { 393 struct async_cmd_info *cmdinfo = ctx; 394 cmdinfo->result = le32_to_cpup(&cqe->result); 395 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; 396 queue_kthread_work(cmdinfo->worker, &cmdinfo->work); 397 blk_mq_free_request(cmdinfo->req); 398 } 399 400 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, 401 unsigned int tag) 402 { 403 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); 404 405 return blk_mq_rq_to_pdu(req); 406 } 407 408 /* 409 * Called with local interrupts disabled and the q_lock held. May not sleep. 410 */ 411 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, 412 nvme_completion_fn *fn) 413 { 414 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); 415 void *ctx; 416 if (tag >= nvmeq->q_depth) { 417 *fn = special_completion; 418 return CMD_CTX_INVALID; 419 } 420 if (fn) 421 *fn = cmd->fn; 422 ctx = cmd->ctx; 423 cmd->fn = special_completion; 424 cmd->ctx = CMD_CTX_COMPLETED; 425 return ctx; 426 } 427 428 /** 429 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 430 * @nvmeq: The queue to use 431 * @cmd: The command to send 432 * 433 * Safe to use from interrupt context 434 */ 435 static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 436 struct nvme_command *cmd) 437 { 438 u16 tail = nvmeq->sq_tail; 439 440 if (nvmeq->sq_cmds_io) 441 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 442 else 443 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 444 445 if (++tail == nvmeq->q_depth) 446 tail = 0; 447 writel(tail, nvmeq->q_db); 448 nvmeq->sq_tail = tail; 449 } 450 451 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 452 { 453 unsigned long flags; 454 spin_lock_irqsave(&nvmeq->q_lock, flags); 455 __nvme_submit_cmd(nvmeq, cmd); 456 spin_unlock_irqrestore(&nvmeq->q_lock, flags); 457 } 458 459 static __le64 **iod_list(struct nvme_iod *iod) 460 { 461 return ((void *)iod) + iod->offset; 462 } 463 464 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, 465 unsigned nseg, unsigned long private) 466 { 467 iod->private = private; 468 iod->offset = offsetof(struct nvme_iod, sg[nseg]); 469 iod->npages = -1; 470 iod->length = nbytes; 471 iod->nents = 0; 472 } 473 474 static struct nvme_iod * 475 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, 476 unsigned long priv, gfp_t gfp) 477 { 478 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + 479 sizeof(__le64 *) * nvme_npages(bytes, dev) + 480 sizeof(struct scatterlist) * nseg, gfp); 481 482 if (iod) 483 iod_init(iod, bytes, nseg, priv); 484 485 return iod; 486 } 487 488 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, 489 gfp_t gfp) 490 { 491 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : 492 sizeof(struct nvme_dsm_range); 493 struct nvme_iod *iod; 494 495 if (rq->nr_phys_segments <= NVME_INT_PAGES && 496 size <= NVME_INT_BYTES(dev)) { 497 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); 498 499 iod = cmd->iod; 500 iod_init(iod, size, rq->nr_phys_segments, 501 (unsigned long) rq | NVME_INT_MASK); 502 return iod; 503 } 504 505 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, 506 (unsigned long) rq, gfp); 507 } 508 509 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) 510 { 511 const int last_prp = dev->ctrl.page_size / 8 - 1; 512 int i; 513 __le64 **list = iod_list(iod); 514 dma_addr_t prp_dma = iod->first_dma; 515 516 if (iod->npages == 0) 517 dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 518 for (i = 0; i < iod->npages; i++) { 519 __le64 *prp_list = list[i]; 520 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 521 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 522 prp_dma = next_prp_dma; 523 } 524 525 if (iod_should_kfree(iod)) 526 kfree(iod); 527 } 528 529 #ifdef CONFIG_BLK_DEV_INTEGRITY 530 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 531 { 532 if (be32_to_cpu(pi->ref_tag) == v) 533 pi->ref_tag = cpu_to_be32(p); 534 } 535 536 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 537 { 538 if (be32_to_cpu(pi->ref_tag) == p) 539 pi->ref_tag = cpu_to_be32(v); 540 } 541 542 /** 543 * nvme_dif_remap - remaps ref tags to bip seed and physical lba 544 * 545 * The virtual start sector is the one that was originally submitted by the 546 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 547 * start sector may be different. Remap protection information to match the 548 * physical LBA on writes, and back to the original seed on reads. 549 * 550 * Type 0 and 3 do not have a ref tag, so no remapping required. 551 */ 552 static void nvme_dif_remap(struct request *req, 553 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 554 { 555 struct nvme_ns *ns = req->rq_disk->private_data; 556 struct bio_integrity_payload *bip; 557 struct t10_pi_tuple *pi; 558 void *p, *pmap; 559 u32 i, nlb, ts, phys, virt; 560 561 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 562 return; 563 564 bip = bio_integrity(req->bio); 565 if (!bip) 566 return; 567 568 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 569 570 p = pmap; 571 virt = bip_get_seed(bip); 572 phys = nvme_block_nr(ns, blk_rq_pos(req)); 573 nlb = (blk_rq_bytes(req) >> ns->lba_shift); 574 ts = ns->disk->queue->integrity.tuple_size; 575 576 for (i = 0; i < nlb; i++, virt++, phys++) { 577 pi = (struct t10_pi_tuple *)p; 578 dif_swap(phys, virt, pi); 579 p += ts; 580 } 581 kunmap_atomic(pmap); 582 } 583 #else /* CONFIG_BLK_DEV_INTEGRITY */ 584 static void nvme_dif_remap(struct request *req, 585 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 586 { 587 } 588 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 589 { 590 } 591 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 592 { 593 } 594 #endif 595 596 static void req_completion(struct nvme_queue *nvmeq, void *ctx, 597 struct nvme_completion *cqe) 598 { 599 struct nvme_iod *iod = ctx; 600 struct request *req = iod_get_private(iod); 601 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); 602 u16 status = le16_to_cpup(&cqe->status) >> 1; 603 int error = 0; 604 605 if (unlikely(status)) { 606 if (!(status & NVME_SC_DNR || blk_noretry_request(req)) 607 && (jiffies - req->start_time) < req->timeout) { 608 unsigned long flags; 609 610 nvme_unmap_data(nvmeq->dev, iod); 611 612 blk_mq_requeue_request(req); 613 spin_lock_irqsave(req->q->queue_lock, flags); 614 if (!blk_queue_stopped(req->q)) 615 blk_mq_kick_requeue_list(req->q); 616 spin_unlock_irqrestore(req->q->queue_lock, flags); 617 return; 618 } 619 620 if (req->cmd_type == REQ_TYPE_DRV_PRIV) { 621 if (cmd_rq->ctx == CMD_CTX_CANCELLED) 622 error = -EINTR; 623 else 624 error = status; 625 } else { 626 error = nvme_error_status(status); 627 } 628 } 629 630 if (req->cmd_type == REQ_TYPE_DRV_PRIV) { 631 u32 result = le32_to_cpup(&cqe->result); 632 req->special = (void *)(uintptr_t)result; 633 } 634 635 if (cmd_rq->aborted) 636 dev_warn(nvmeq->dev->dev, 637 "completing aborted command with status:%04x\n", 638 error); 639 640 nvme_unmap_data(nvmeq->dev, iod); 641 blk_mq_complete_request(req, error); 642 } 643 644 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, 645 int total_len) 646 { 647 struct dma_pool *pool; 648 int length = total_len; 649 struct scatterlist *sg = iod->sg; 650 int dma_len = sg_dma_len(sg); 651 u64 dma_addr = sg_dma_address(sg); 652 u32 page_size = dev->ctrl.page_size; 653 int offset = dma_addr & (page_size - 1); 654 __le64 *prp_list; 655 __le64 **list = iod_list(iod); 656 dma_addr_t prp_dma; 657 int nprps, i; 658 659 length -= (page_size - offset); 660 if (length <= 0) 661 return true; 662 663 dma_len -= (page_size - offset); 664 if (dma_len) { 665 dma_addr += (page_size - offset); 666 } else { 667 sg = sg_next(sg); 668 dma_addr = sg_dma_address(sg); 669 dma_len = sg_dma_len(sg); 670 } 671 672 if (length <= page_size) { 673 iod->first_dma = dma_addr; 674 return true; 675 } 676 677 nprps = DIV_ROUND_UP(length, page_size); 678 if (nprps <= (256 / 8)) { 679 pool = dev->prp_small_pool; 680 iod->npages = 0; 681 } else { 682 pool = dev->prp_page_pool; 683 iod->npages = 1; 684 } 685 686 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 687 if (!prp_list) { 688 iod->first_dma = dma_addr; 689 iod->npages = -1; 690 return false; 691 } 692 list[0] = prp_list; 693 iod->first_dma = prp_dma; 694 i = 0; 695 for (;;) { 696 if (i == page_size >> 3) { 697 __le64 *old_prp_list = prp_list; 698 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 699 if (!prp_list) 700 return false; 701 list[iod->npages++] = prp_list; 702 prp_list[0] = old_prp_list[i - 1]; 703 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 704 i = 1; 705 } 706 prp_list[i++] = cpu_to_le64(dma_addr); 707 dma_len -= page_size; 708 dma_addr += page_size; 709 length -= page_size; 710 if (length <= 0) 711 break; 712 if (dma_len > 0) 713 continue; 714 BUG_ON(dma_len < 0); 715 sg = sg_next(sg); 716 dma_addr = sg_dma_address(sg); 717 dma_len = sg_dma_len(sg); 718 } 719 720 return true; 721 } 722 723 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, 724 struct nvme_command *cmnd) 725 { 726 struct request *req = iod_get_private(iod); 727 struct request_queue *q = req->q; 728 enum dma_data_direction dma_dir = rq_data_dir(req) ? 729 DMA_TO_DEVICE : DMA_FROM_DEVICE; 730 int ret = BLK_MQ_RQ_QUEUE_ERROR; 731 732 sg_init_table(iod->sg, req->nr_phys_segments); 733 iod->nents = blk_rq_map_sg(q, req, iod->sg); 734 if (!iod->nents) 735 goto out; 736 737 ret = BLK_MQ_RQ_QUEUE_BUSY; 738 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) 739 goto out; 740 741 if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) 742 goto out_unmap; 743 744 ret = BLK_MQ_RQ_QUEUE_ERROR; 745 if (blk_integrity_rq(req)) { 746 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 747 goto out_unmap; 748 749 sg_init_table(iod->meta_sg, 1); 750 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) 751 goto out_unmap; 752 753 if (rq_data_dir(req)) 754 nvme_dif_remap(req, nvme_dif_prep); 755 756 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) 757 goto out_unmap; 758 } 759 760 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 761 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); 762 if (blk_integrity_rq(req)) 763 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); 764 return BLK_MQ_RQ_QUEUE_OK; 765 766 out_unmap: 767 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 768 out: 769 return ret; 770 } 771 772 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) 773 { 774 struct request *req = iod_get_private(iod); 775 enum dma_data_direction dma_dir = rq_data_dir(req) ? 776 DMA_TO_DEVICE : DMA_FROM_DEVICE; 777 778 if (iod->nents) { 779 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 780 if (blk_integrity_rq(req)) { 781 if (!rq_data_dir(req)) 782 nvme_dif_remap(req, nvme_dif_complete); 783 dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); 784 } 785 } 786 787 nvme_free_iod(dev, iod); 788 } 789 790 /* 791 * We reuse the small pool to allocate the 16-byte range here as it is not 792 * worth having a special pool for these or additional cases to handle freeing 793 * the iod. 794 */ 795 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, 796 struct nvme_iod *iod, struct nvme_command *cmnd) 797 { 798 struct request *req = iod_get_private(iod); 799 struct nvme_dsm_range *range; 800 801 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, 802 &iod->first_dma); 803 if (!range) 804 return BLK_MQ_RQ_QUEUE_BUSY; 805 iod_list(iod)[0] = (__le64 *)range; 806 iod->npages = 0; 807 808 range->cattr = cpu_to_le32(0); 809 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); 810 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); 811 812 memset(cmnd, 0, sizeof(*cmnd)); 813 cmnd->dsm.opcode = nvme_cmd_dsm; 814 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); 815 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); 816 cmnd->dsm.nr = 0; 817 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); 818 return BLK_MQ_RQ_QUEUE_OK; 819 } 820 821 /* 822 * NOTE: ns is NULL when called on the admin queue. 823 */ 824 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 825 const struct blk_mq_queue_data *bd) 826 { 827 struct nvme_ns *ns = hctx->queue->queuedata; 828 struct nvme_queue *nvmeq = hctx->driver_data; 829 struct nvme_dev *dev = nvmeq->dev; 830 struct request *req = bd->rq; 831 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 832 struct nvme_iod *iod; 833 struct nvme_command cmnd; 834 int ret = BLK_MQ_RQ_QUEUE_OK; 835 836 /* 837 * If formated with metadata, require the block layer provide a buffer 838 * unless this namespace is formated such that the metadata can be 839 * stripped/generated by the controller with PRACT=1. 840 */ 841 if (ns && ns->ms && !blk_integrity_rq(req)) { 842 if (!(ns->pi_type && ns->ms == 8) && 843 req->cmd_type != REQ_TYPE_DRV_PRIV) { 844 blk_mq_complete_request(req, -EFAULT); 845 return BLK_MQ_RQ_QUEUE_OK; 846 } 847 } 848 849 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); 850 if (!iod) 851 return BLK_MQ_RQ_QUEUE_BUSY; 852 853 if (req->cmd_flags & REQ_DISCARD) { 854 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); 855 } else { 856 if (req->cmd_type == REQ_TYPE_DRV_PRIV) 857 memcpy(&cmnd, req->cmd, sizeof(cmnd)); 858 else if (req->cmd_flags & REQ_FLUSH) 859 nvme_setup_flush(ns, &cmnd); 860 else 861 nvme_setup_rw(ns, req, &cmnd); 862 863 if (req->nr_phys_segments) 864 ret = nvme_map_data(dev, iod, &cmnd); 865 } 866 867 if (ret) 868 goto out; 869 870 cmnd.common.command_id = req->tag; 871 nvme_set_info(cmd, iod, req_completion); 872 873 spin_lock_irq(&nvmeq->q_lock); 874 __nvme_submit_cmd(nvmeq, &cmnd); 875 nvme_process_cq(nvmeq); 876 spin_unlock_irq(&nvmeq->q_lock); 877 return BLK_MQ_RQ_QUEUE_OK; 878 out: 879 nvme_free_iod(dev, iod); 880 return ret; 881 } 882 883 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) 884 { 885 u16 head, phase; 886 887 head = nvmeq->cq_head; 888 phase = nvmeq->cq_phase; 889 890 for (;;) { 891 void *ctx; 892 nvme_completion_fn fn; 893 struct nvme_completion cqe = nvmeq->cqes[head]; 894 if ((le16_to_cpu(cqe.status) & 1) != phase) 895 break; 896 nvmeq->sq_head = le16_to_cpu(cqe.sq_head); 897 if (++head == nvmeq->q_depth) { 898 head = 0; 899 phase = !phase; 900 } 901 if (tag && *tag == cqe.command_id) 902 *tag = -1; 903 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); 904 fn(nvmeq, ctx, &cqe); 905 } 906 907 /* If the controller ignores the cq head doorbell and continuously 908 * writes to the queue, it is theoretically possible to wrap around 909 * the queue twice and mistakenly return IRQ_NONE. Linux only 910 * requires that 0.1% of your interrupts are handled, so this isn't 911 * a big problem. 912 */ 913 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) 914 return; 915 916 if (likely(nvmeq->cq_vector >= 0)) 917 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 918 nvmeq->cq_head = head; 919 nvmeq->cq_phase = phase; 920 921 nvmeq->cqe_seen = 1; 922 } 923 924 static void nvme_process_cq(struct nvme_queue *nvmeq) 925 { 926 __nvme_process_cq(nvmeq, NULL); 927 } 928 929 static irqreturn_t nvme_irq(int irq, void *data) 930 { 931 irqreturn_t result; 932 struct nvme_queue *nvmeq = data; 933 spin_lock(&nvmeq->q_lock); 934 nvme_process_cq(nvmeq); 935 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 936 nvmeq->cqe_seen = 0; 937 spin_unlock(&nvmeq->q_lock); 938 return result; 939 } 940 941 static irqreturn_t nvme_irq_check(int irq, void *data) 942 { 943 struct nvme_queue *nvmeq = data; 944 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; 945 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) 946 return IRQ_NONE; 947 return IRQ_WAKE_THREAD; 948 } 949 950 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 951 { 952 struct nvme_queue *nvmeq = hctx->driver_data; 953 954 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 955 nvmeq->cq_phase) { 956 spin_lock_irq(&nvmeq->q_lock); 957 __nvme_process_cq(nvmeq, &tag); 958 spin_unlock_irq(&nvmeq->q_lock); 959 960 if (tag == -1) 961 return 1; 962 } 963 964 return 0; 965 } 966 967 static int nvme_submit_async_admin_req(struct nvme_dev *dev) 968 { 969 struct nvme_queue *nvmeq = dev->queues[0]; 970 struct nvme_command c; 971 struct nvme_cmd_info *cmd_info; 972 struct request *req; 973 974 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 975 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); 976 if (IS_ERR(req)) 977 return PTR_ERR(req); 978 979 req->cmd_flags |= REQ_NO_TIMEOUT; 980 cmd_info = blk_mq_rq_to_pdu(req); 981 nvme_set_info(cmd_info, NULL, async_req_completion); 982 983 memset(&c, 0, sizeof(c)); 984 c.common.opcode = nvme_admin_async_event; 985 c.common.command_id = req->tag; 986 987 blk_mq_free_request(req); 988 __nvme_submit_cmd(nvmeq, &c); 989 return 0; 990 } 991 992 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, 993 struct nvme_command *cmd, 994 struct async_cmd_info *cmdinfo, unsigned timeout) 995 { 996 struct nvme_queue *nvmeq = dev->queues[0]; 997 struct request *req; 998 struct nvme_cmd_info *cmd_rq; 999 1000 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); 1001 if (IS_ERR(req)) 1002 return PTR_ERR(req); 1003 1004 req->timeout = timeout; 1005 cmd_rq = blk_mq_rq_to_pdu(req); 1006 cmdinfo->req = req; 1007 nvme_set_info(cmd_rq, cmdinfo, async_completion); 1008 cmdinfo->status = -EINTR; 1009 1010 cmd->common.command_id = req->tag; 1011 1012 nvme_submit_cmd(nvmeq, cmd); 1013 return 0; 1014 } 1015 1016 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1017 { 1018 struct nvme_command c; 1019 1020 memset(&c, 0, sizeof(c)); 1021 c.delete_queue.opcode = opcode; 1022 c.delete_queue.qid = cpu_to_le16(id); 1023 1024 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1025 } 1026 1027 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1028 struct nvme_queue *nvmeq) 1029 { 1030 struct nvme_command c; 1031 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 1032 1033 /* 1034 * Note: we (ab)use the fact the the prp fields survive if no data 1035 * is attached to the request. 1036 */ 1037 memset(&c, 0, sizeof(c)); 1038 c.create_cq.opcode = nvme_admin_create_cq; 1039 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1040 c.create_cq.cqid = cpu_to_le16(qid); 1041 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1042 c.create_cq.cq_flags = cpu_to_le16(flags); 1043 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 1044 1045 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1046 } 1047 1048 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1049 struct nvme_queue *nvmeq) 1050 { 1051 struct nvme_command c; 1052 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; 1053 1054 /* 1055 * Note: we (ab)use the fact the the prp fields survive if no data 1056 * is attached to the request. 1057 */ 1058 memset(&c, 0, sizeof(c)); 1059 c.create_sq.opcode = nvme_admin_create_sq; 1060 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1061 c.create_sq.sqid = cpu_to_le16(qid); 1062 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1063 c.create_sq.sq_flags = cpu_to_le16(flags); 1064 c.create_sq.cqid = cpu_to_le16(qid); 1065 1066 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1067 } 1068 1069 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1070 { 1071 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1072 } 1073 1074 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1075 { 1076 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1077 } 1078 1079 /** 1080 * nvme_abort_req - Attempt aborting a request 1081 * 1082 * Schedule controller reset if the command was already aborted once before and 1083 * still hasn't been returned to the driver, or if this is the admin queue. 1084 */ 1085 static void nvme_abort_req(struct request *req) 1086 { 1087 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); 1088 struct nvme_queue *nvmeq = cmd_rq->nvmeq; 1089 struct nvme_dev *dev = nvmeq->dev; 1090 struct request *abort_req; 1091 struct nvme_cmd_info *abort_cmd; 1092 struct nvme_command cmd; 1093 1094 if (!nvmeq->qid || cmd_rq->aborted) { 1095 spin_lock(&dev_list_lock); 1096 if (!__nvme_reset(dev)) { 1097 dev_warn(dev->dev, 1098 "I/O %d QID %d timeout, reset controller\n", 1099 req->tag, nvmeq->qid); 1100 } 1101 spin_unlock(&dev_list_lock); 1102 return; 1103 } 1104 1105 if (!dev->ctrl.abort_limit) 1106 return; 1107 1108 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 1109 BLK_MQ_REQ_NOWAIT); 1110 if (IS_ERR(abort_req)) 1111 return; 1112 1113 abort_cmd = blk_mq_rq_to_pdu(abort_req); 1114 nvme_set_info(abort_cmd, abort_req, abort_completion); 1115 1116 memset(&cmd, 0, sizeof(cmd)); 1117 cmd.abort.opcode = nvme_admin_abort_cmd; 1118 cmd.abort.cid = req->tag; 1119 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1120 cmd.abort.command_id = abort_req->tag; 1121 1122 --dev->ctrl.abort_limit; 1123 cmd_rq->aborted = 1; 1124 1125 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, 1126 nvmeq->qid); 1127 nvme_submit_cmd(dev->queues[0], &cmd); 1128 } 1129 1130 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) 1131 { 1132 struct nvme_queue *nvmeq = data; 1133 void *ctx; 1134 nvme_completion_fn fn; 1135 struct nvme_cmd_info *cmd; 1136 struct nvme_completion cqe; 1137 1138 if (!blk_mq_request_started(req)) 1139 return; 1140 1141 cmd = blk_mq_rq_to_pdu(req); 1142 1143 if (cmd->ctx == CMD_CTX_CANCELLED) 1144 return; 1145 1146 if (blk_queue_dying(req->q)) 1147 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); 1148 else 1149 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); 1150 1151 1152 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", 1153 req->tag, nvmeq->qid); 1154 ctx = cancel_cmd_info(cmd, &fn); 1155 fn(nvmeq, ctx, &cqe); 1156 } 1157 1158 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1159 { 1160 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 1161 struct nvme_queue *nvmeq = cmd->nvmeq; 1162 1163 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, 1164 nvmeq->qid); 1165 spin_lock_irq(&nvmeq->q_lock); 1166 nvme_abort_req(req); 1167 spin_unlock_irq(&nvmeq->q_lock); 1168 1169 /* 1170 * The aborted req will be completed on receiving the abort req. 1171 * We enable the timer again. If hit twice, it'll cause a device reset, 1172 * as the device then is in a faulty state. 1173 */ 1174 return BLK_EH_RESET_TIMER; 1175 } 1176 1177 static void nvme_free_queue(struct nvme_queue *nvmeq) 1178 { 1179 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1180 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1181 if (nvmeq->sq_cmds) 1182 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1183 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1184 kfree(nvmeq); 1185 } 1186 1187 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1188 { 1189 int i; 1190 1191 for (i = dev->queue_count - 1; i >= lowest; i--) { 1192 struct nvme_queue *nvmeq = dev->queues[i]; 1193 dev->queue_count--; 1194 dev->queues[i] = NULL; 1195 nvme_free_queue(nvmeq); 1196 } 1197 } 1198 1199 /** 1200 * nvme_suspend_queue - put queue into suspended state 1201 * @nvmeq - queue to suspend 1202 */ 1203 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1204 { 1205 int vector; 1206 1207 spin_lock_irq(&nvmeq->q_lock); 1208 if (nvmeq->cq_vector == -1) { 1209 spin_unlock_irq(&nvmeq->q_lock); 1210 return 1; 1211 } 1212 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; 1213 nvmeq->dev->online_queues--; 1214 nvmeq->cq_vector = -1; 1215 spin_unlock_irq(&nvmeq->q_lock); 1216 1217 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1218 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); 1219 1220 irq_set_affinity_hint(vector, NULL); 1221 free_irq(vector, nvmeq); 1222 1223 return 0; 1224 } 1225 1226 static void nvme_clear_queue(struct nvme_queue *nvmeq) 1227 { 1228 spin_lock_irq(&nvmeq->q_lock); 1229 if (nvmeq->tags && *nvmeq->tags) 1230 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); 1231 spin_unlock_irq(&nvmeq->q_lock); 1232 } 1233 1234 static void nvme_disable_queue(struct nvme_dev *dev, int qid) 1235 { 1236 struct nvme_queue *nvmeq = dev->queues[qid]; 1237 1238 if (!nvmeq) 1239 return; 1240 if (nvme_suspend_queue(nvmeq)) 1241 return; 1242 1243 /* Don't tell the adapter to delete the admin queue. 1244 * Don't tell a removed adapter to delete IO queues. */ 1245 if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { 1246 adapter_delete_sq(dev, qid); 1247 adapter_delete_cq(dev, qid); 1248 } 1249 1250 spin_lock_irq(&nvmeq->q_lock); 1251 nvme_process_cq(nvmeq); 1252 spin_unlock_irq(&nvmeq->q_lock); 1253 } 1254 1255 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1256 int entry_size) 1257 { 1258 int q_depth = dev->q_depth; 1259 unsigned q_size_aligned = roundup(q_depth * entry_size, 1260 dev->ctrl.page_size); 1261 1262 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1263 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1264 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1265 q_depth = div_u64(mem_per_q, entry_size); 1266 1267 /* 1268 * Ensure the reduced q_depth is above some threshold where it 1269 * would be better to map queues in system memory with the 1270 * original depth 1271 */ 1272 if (q_depth < 64) 1273 return -ENOMEM; 1274 } 1275 1276 return q_depth; 1277 } 1278 1279 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1280 int qid, int depth) 1281 { 1282 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 1283 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 1284 dev->ctrl.page_size); 1285 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 1286 nvmeq->sq_cmds_io = dev->cmb + offset; 1287 } else { 1288 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1289 &nvmeq->sq_dma_addr, GFP_KERNEL); 1290 if (!nvmeq->sq_cmds) 1291 return -ENOMEM; 1292 } 1293 1294 return 0; 1295 } 1296 1297 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1298 int depth) 1299 { 1300 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); 1301 if (!nvmeq) 1302 return NULL; 1303 1304 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 1305 &nvmeq->cq_dma_addr, GFP_KERNEL); 1306 if (!nvmeq->cqes) 1307 goto free_nvmeq; 1308 1309 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1310 goto free_cqdma; 1311 1312 nvmeq->q_dmadev = dev->dev; 1313 nvmeq->dev = dev; 1314 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", 1315 dev->ctrl.instance, qid); 1316 spin_lock_init(&nvmeq->q_lock); 1317 nvmeq->cq_head = 0; 1318 nvmeq->cq_phase = 1; 1319 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1320 nvmeq->q_depth = depth; 1321 nvmeq->qid = qid; 1322 nvmeq->cq_vector = -1; 1323 dev->queues[qid] = nvmeq; 1324 1325 /* make sure queue descriptor is set before queue count, for kthread */ 1326 mb(); 1327 dev->queue_count++; 1328 1329 return nvmeq; 1330 1331 free_cqdma: 1332 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1333 nvmeq->cq_dma_addr); 1334 free_nvmeq: 1335 kfree(nvmeq); 1336 return NULL; 1337 } 1338 1339 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1340 const char *name) 1341 { 1342 if (use_threaded_interrupts) 1343 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, 1344 nvme_irq_check, nvme_irq, IRQF_SHARED, 1345 name, nvmeq); 1346 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, 1347 IRQF_SHARED, name, nvmeq); 1348 } 1349 1350 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1351 { 1352 struct nvme_dev *dev = nvmeq->dev; 1353 1354 spin_lock_irq(&nvmeq->q_lock); 1355 nvmeq->sq_tail = 0; 1356 nvmeq->cq_head = 0; 1357 nvmeq->cq_phase = 1; 1358 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1359 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1360 dev->online_queues++; 1361 spin_unlock_irq(&nvmeq->q_lock); 1362 } 1363 1364 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 1365 { 1366 struct nvme_dev *dev = nvmeq->dev; 1367 int result; 1368 1369 nvmeq->cq_vector = qid - 1; 1370 result = adapter_alloc_cq(dev, qid, nvmeq); 1371 if (result < 0) 1372 return result; 1373 1374 result = adapter_alloc_sq(dev, qid, nvmeq); 1375 if (result < 0) 1376 goto release_cq; 1377 1378 result = queue_request_irq(dev, nvmeq, nvmeq->irqname); 1379 if (result < 0) 1380 goto release_sq; 1381 1382 nvme_init_queue(nvmeq, qid); 1383 return result; 1384 1385 release_sq: 1386 adapter_delete_sq(dev, qid); 1387 release_cq: 1388 adapter_delete_cq(dev, qid); 1389 return result; 1390 } 1391 1392 static struct blk_mq_ops nvme_mq_admin_ops = { 1393 .queue_rq = nvme_queue_rq, 1394 .map_queue = blk_mq_map_queue, 1395 .init_hctx = nvme_admin_init_hctx, 1396 .exit_hctx = nvme_admin_exit_hctx, 1397 .init_request = nvme_admin_init_request, 1398 .timeout = nvme_timeout, 1399 }; 1400 1401 static struct blk_mq_ops nvme_mq_ops = { 1402 .queue_rq = nvme_queue_rq, 1403 .map_queue = blk_mq_map_queue, 1404 .init_hctx = nvme_init_hctx, 1405 .init_request = nvme_init_request, 1406 .timeout = nvme_timeout, 1407 .poll = nvme_poll, 1408 }; 1409 1410 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1411 { 1412 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1413 blk_cleanup_queue(dev->ctrl.admin_q); 1414 blk_mq_free_tag_set(&dev->admin_tagset); 1415 } 1416 } 1417 1418 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1419 { 1420 if (!dev->ctrl.admin_q) { 1421 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1422 dev->admin_tagset.nr_hw_queues = 1; 1423 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; 1424 dev->admin_tagset.reserved_tags = 1; 1425 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1426 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1427 dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1428 dev->admin_tagset.driver_data = dev; 1429 1430 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1431 return -ENOMEM; 1432 1433 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1434 if (IS_ERR(dev->ctrl.admin_q)) { 1435 blk_mq_free_tag_set(&dev->admin_tagset); 1436 return -ENOMEM; 1437 } 1438 if (!blk_get_queue(dev->ctrl.admin_q)) { 1439 nvme_dev_remove_admin(dev); 1440 dev->ctrl.admin_q = NULL; 1441 return -ENODEV; 1442 } 1443 } else 1444 blk_mq_unfreeze_queue(dev->ctrl.admin_q); 1445 1446 return 0; 1447 } 1448 1449 static int nvme_configure_admin_queue(struct nvme_dev *dev) 1450 { 1451 int result; 1452 u32 aqa; 1453 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1454 struct nvme_queue *nvmeq; 1455 1456 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? 1457 NVME_CAP_NSSRC(cap) : 0; 1458 1459 if (dev->subsystem && 1460 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1461 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1462 1463 result = nvme_disable_ctrl(&dev->ctrl, cap); 1464 if (result < 0) 1465 return result; 1466 1467 nvmeq = dev->queues[0]; 1468 if (!nvmeq) { 1469 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1470 if (!nvmeq) 1471 return -ENOMEM; 1472 } 1473 1474 aqa = nvmeq->q_depth - 1; 1475 aqa |= aqa << 16; 1476 1477 writel(aqa, dev->bar + NVME_REG_AQA); 1478 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1479 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1480 1481 result = nvme_enable_ctrl(&dev->ctrl, cap); 1482 if (result) 1483 goto free_nvmeq; 1484 1485 nvmeq->cq_vector = 0; 1486 result = queue_request_irq(dev, nvmeq, nvmeq->irqname); 1487 if (result) { 1488 nvmeq->cq_vector = -1; 1489 goto free_nvmeq; 1490 } 1491 1492 return result; 1493 1494 free_nvmeq: 1495 nvme_free_queues(dev, 0); 1496 return result; 1497 } 1498 1499 static int nvme_kthread(void *data) 1500 { 1501 struct nvme_dev *dev, *next; 1502 1503 while (!kthread_should_stop()) { 1504 set_current_state(TASK_INTERRUPTIBLE); 1505 spin_lock(&dev_list_lock); 1506 list_for_each_entry_safe(dev, next, &dev_list, node) { 1507 int i; 1508 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1509 1510 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || 1511 csts & NVME_CSTS_CFS) { 1512 if (!__nvme_reset(dev)) { 1513 dev_warn(dev->dev, 1514 "Failed status: %x, reset controller\n", 1515 readl(dev->bar + NVME_REG_CSTS)); 1516 } 1517 continue; 1518 } 1519 for (i = 0; i < dev->queue_count; i++) { 1520 struct nvme_queue *nvmeq = dev->queues[i]; 1521 if (!nvmeq) 1522 continue; 1523 spin_lock_irq(&nvmeq->q_lock); 1524 nvme_process_cq(nvmeq); 1525 1526 while (i == 0 && dev->ctrl.event_limit > 0) { 1527 if (nvme_submit_async_admin_req(dev)) 1528 break; 1529 dev->ctrl.event_limit--; 1530 } 1531 spin_unlock_irq(&nvmeq->q_lock); 1532 } 1533 } 1534 spin_unlock(&dev_list_lock); 1535 schedule_timeout(round_jiffies_relative(HZ)); 1536 } 1537 return 0; 1538 } 1539 1540 static int nvme_create_io_queues(struct nvme_dev *dev) 1541 { 1542 unsigned i; 1543 int ret = 0; 1544 1545 for (i = dev->queue_count; i <= dev->max_qid; i++) { 1546 if (!nvme_alloc_queue(dev, i, dev->q_depth)) { 1547 ret = -ENOMEM; 1548 break; 1549 } 1550 } 1551 1552 for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { 1553 ret = nvme_create_queue(dev->queues[i], i); 1554 if (ret) { 1555 nvme_free_queues(dev, i); 1556 break; 1557 } 1558 } 1559 1560 /* 1561 * Ignore failing Create SQ/CQ commands, we can continue with less 1562 * than the desired aount of queues, and even a controller without 1563 * I/O queues an still be used to issue admin commands. This might 1564 * be useful to upgrade a buggy firmware for example. 1565 */ 1566 return ret >= 0 ? 0 : ret; 1567 } 1568 1569 static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 1570 { 1571 u64 szu, size, offset; 1572 u32 cmbloc; 1573 resource_size_t bar_size; 1574 struct pci_dev *pdev = to_pci_dev(dev->dev); 1575 void __iomem *cmb; 1576 dma_addr_t dma_addr; 1577 1578 if (!use_cmb_sqes) 1579 return NULL; 1580 1581 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1582 if (!(NVME_CMB_SZ(dev->cmbsz))) 1583 return NULL; 1584 1585 cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1586 1587 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 1588 size = szu * NVME_CMB_SZ(dev->cmbsz); 1589 offset = szu * NVME_CMB_OFST(cmbloc); 1590 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); 1591 1592 if (offset > bar_size) 1593 return NULL; 1594 1595 /* 1596 * Controllers may support a CMB size larger than their BAR, 1597 * for example, due to being behind a bridge. Reduce the CMB to 1598 * the reported size of the BAR 1599 */ 1600 if (size > bar_size - offset) 1601 size = bar_size - offset; 1602 1603 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; 1604 cmb = ioremap_wc(dma_addr, size); 1605 if (!cmb) 1606 return NULL; 1607 1608 dev->cmb_dma_addr = dma_addr; 1609 dev->cmb_size = size; 1610 return cmb; 1611 } 1612 1613 static inline void nvme_release_cmb(struct nvme_dev *dev) 1614 { 1615 if (dev->cmb) { 1616 iounmap(dev->cmb); 1617 dev->cmb = NULL; 1618 } 1619 } 1620 1621 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1622 { 1623 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); 1624 } 1625 1626 static int nvme_setup_io_queues(struct nvme_dev *dev) 1627 { 1628 struct nvme_queue *adminq = dev->queues[0]; 1629 struct pci_dev *pdev = to_pci_dev(dev->dev); 1630 int result, i, vecs, nr_io_queues, size; 1631 1632 nr_io_queues = num_possible_cpus(); 1633 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 1634 if (result < 0) 1635 return result; 1636 1637 /* 1638 * Degraded controllers might return an error when setting the queue 1639 * count. We still want to be able to bring them online and offer 1640 * access to the admin queue, as that might be only way to fix them up. 1641 */ 1642 if (result > 0) { 1643 dev_err(dev->dev, "Could not set queue count (%d)\n", result); 1644 nr_io_queues = 0; 1645 result = 0; 1646 } 1647 1648 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 1649 result = nvme_cmb_qdepth(dev, nr_io_queues, 1650 sizeof(struct nvme_command)); 1651 if (result > 0) 1652 dev->q_depth = result; 1653 else 1654 nvme_release_cmb(dev); 1655 } 1656 1657 size = db_bar_size(dev, nr_io_queues); 1658 if (size > 8192) { 1659 iounmap(dev->bar); 1660 do { 1661 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1662 if (dev->bar) 1663 break; 1664 if (!--nr_io_queues) 1665 return -ENOMEM; 1666 size = db_bar_size(dev, nr_io_queues); 1667 } while (1); 1668 dev->dbs = dev->bar + 4096; 1669 adminq->q_db = dev->dbs; 1670 } 1671 1672 /* Deregister the admin queue's interrupt */ 1673 free_irq(dev->entry[0].vector, adminq); 1674 1675 /* 1676 * If we enable msix early due to not intx, disable it again before 1677 * setting up the full range we need. 1678 */ 1679 if (!pdev->irq) 1680 pci_disable_msix(pdev); 1681 1682 for (i = 0; i < nr_io_queues; i++) 1683 dev->entry[i].entry = i; 1684 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); 1685 if (vecs < 0) { 1686 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); 1687 if (vecs < 0) { 1688 vecs = 1; 1689 } else { 1690 for (i = 0; i < vecs; i++) 1691 dev->entry[i].vector = i + pdev->irq; 1692 } 1693 } 1694 1695 /* 1696 * Should investigate if there's a performance win from allocating 1697 * more queues than interrupt vectors; it might allow the submission 1698 * path to scale better, even if the receive path is limited by the 1699 * number of interrupts. 1700 */ 1701 nr_io_queues = vecs; 1702 dev->max_qid = nr_io_queues; 1703 1704 result = queue_request_irq(dev, adminq, adminq->irqname); 1705 if (result) { 1706 adminq->cq_vector = -1; 1707 goto free_queues; 1708 } 1709 1710 /* Free previously allocated queues that are no longer usable */ 1711 nvme_free_queues(dev, nr_io_queues + 1); 1712 return nvme_create_io_queues(dev); 1713 1714 free_queues: 1715 nvme_free_queues(dev, 1); 1716 return result; 1717 } 1718 1719 static void nvme_set_irq_hints(struct nvme_dev *dev) 1720 { 1721 struct nvme_queue *nvmeq; 1722 int i; 1723 1724 for (i = 0; i < dev->online_queues; i++) { 1725 nvmeq = dev->queues[i]; 1726 1727 if (!nvmeq->tags || !(*nvmeq->tags)) 1728 continue; 1729 1730 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, 1731 blk_mq_tags_cpumask(*nvmeq->tags)); 1732 } 1733 } 1734 1735 static void nvme_dev_scan(struct work_struct *work) 1736 { 1737 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); 1738 1739 if (!dev->tagset.tags) 1740 return; 1741 nvme_scan_namespaces(&dev->ctrl); 1742 nvme_set_irq_hints(dev); 1743 } 1744 1745 /* 1746 * Return: error value if an error occurred setting up the queues or calling 1747 * Identify Device. 0 if these succeeded, even if adding some of the 1748 * namespaces failed. At the moment, these failures are silent. TBD which 1749 * failures should be reported. 1750 */ 1751 static int nvme_dev_add(struct nvme_dev *dev) 1752 { 1753 if (!dev->ctrl.tagset) { 1754 dev->tagset.ops = &nvme_mq_ops; 1755 dev->tagset.nr_hw_queues = dev->online_queues - 1; 1756 dev->tagset.timeout = NVME_IO_TIMEOUT; 1757 dev->tagset.numa_node = dev_to_node(dev->dev); 1758 dev->tagset.queue_depth = 1759 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 1760 dev->tagset.cmd_size = nvme_cmd_size(dev); 1761 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 1762 dev->tagset.driver_data = dev; 1763 1764 if (blk_mq_alloc_tag_set(&dev->tagset)) 1765 return 0; 1766 dev->ctrl.tagset = &dev->tagset; 1767 } 1768 schedule_work(&dev->scan_work); 1769 return 0; 1770 } 1771 1772 static int nvme_dev_map(struct nvme_dev *dev) 1773 { 1774 u64 cap; 1775 int bars, result = -ENOMEM; 1776 struct pci_dev *pdev = to_pci_dev(dev->dev); 1777 1778 if (pci_enable_device_mem(pdev)) 1779 return result; 1780 1781 dev->entry[0].vector = pdev->irq; 1782 pci_set_master(pdev); 1783 bars = pci_select_bars(pdev, IORESOURCE_MEM); 1784 if (!bars) 1785 goto disable_pci; 1786 1787 if (pci_request_selected_regions(pdev, bars, "nvme")) 1788 goto disable_pci; 1789 1790 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 1791 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 1792 goto disable; 1793 1794 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); 1795 if (!dev->bar) 1796 goto disable; 1797 1798 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 1799 result = -ENODEV; 1800 goto unmap; 1801 } 1802 1803 /* 1804 * Some devices don't advertse INTx interrupts, pre-enable a single 1805 * MSIX vec for setup. We'll adjust this later. 1806 */ 1807 if (!pdev->irq) { 1808 result = pci_enable_msix(pdev, dev->entry, 1); 1809 if (result < 0) 1810 goto unmap; 1811 } 1812 1813 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1814 1815 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); 1816 dev->db_stride = 1 << NVME_CAP_STRIDE(cap); 1817 dev->dbs = dev->bar + 4096; 1818 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) 1819 dev->cmb = nvme_map_cmb(dev); 1820 1821 return 0; 1822 1823 unmap: 1824 iounmap(dev->bar); 1825 dev->bar = NULL; 1826 disable: 1827 pci_release_regions(pdev); 1828 disable_pci: 1829 pci_disable_device(pdev); 1830 return result; 1831 } 1832 1833 static void nvme_dev_unmap(struct nvme_dev *dev) 1834 { 1835 struct pci_dev *pdev = to_pci_dev(dev->dev); 1836 1837 if (pdev->msi_enabled) 1838 pci_disable_msi(pdev); 1839 else if (pdev->msix_enabled) 1840 pci_disable_msix(pdev); 1841 1842 if (dev->bar) { 1843 iounmap(dev->bar); 1844 dev->bar = NULL; 1845 pci_release_regions(pdev); 1846 } 1847 1848 if (pci_is_enabled(pdev)) 1849 pci_disable_device(pdev); 1850 } 1851 1852 struct nvme_delq_ctx { 1853 struct task_struct *waiter; 1854 struct kthread_worker *worker; 1855 atomic_t refcount; 1856 }; 1857 1858 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) 1859 { 1860 dq->waiter = current; 1861 mb(); 1862 1863 for (;;) { 1864 set_current_state(TASK_KILLABLE); 1865 if (!atomic_read(&dq->refcount)) 1866 break; 1867 if (!schedule_timeout(ADMIN_TIMEOUT) || 1868 fatal_signal_pending(current)) { 1869 /* 1870 * Disable the controller first since we can't trust it 1871 * at this point, but leave the admin queue enabled 1872 * until all queue deletion requests are flushed. 1873 * FIXME: This may take a while if there are more h/w 1874 * queues than admin tags. 1875 */ 1876 set_current_state(TASK_RUNNING); 1877 nvme_disable_ctrl(&dev->ctrl, 1878 lo_hi_readq(dev->bar + NVME_REG_CAP)); 1879 nvme_clear_queue(dev->queues[0]); 1880 flush_kthread_worker(dq->worker); 1881 nvme_disable_queue(dev, 0); 1882 return; 1883 } 1884 } 1885 set_current_state(TASK_RUNNING); 1886 } 1887 1888 static void nvme_put_dq(struct nvme_delq_ctx *dq) 1889 { 1890 atomic_dec(&dq->refcount); 1891 if (dq->waiter) 1892 wake_up_process(dq->waiter); 1893 } 1894 1895 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) 1896 { 1897 atomic_inc(&dq->refcount); 1898 return dq; 1899 } 1900 1901 static void nvme_del_queue_end(struct nvme_queue *nvmeq) 1902 { 1903 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; 1904 nvme_put_dq(dq); 1905 1906 spin_lock_irq(&nvmeq->q_lock); 1907 nvme_process_cq(nvmeq); 1908 spin_unlock_irq(&nvmeq->q_lock); 1909 } 1910 1911 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, 1912 kthread_work_func_t fn) 1913 { 1914 struct nvme_command c; 1915 1916 memset(&c, 0, sizeof(c)); 1917 c.delete_queue.opcode = opcode; 1918 c.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1919 1920 init_kthread_work(&nvmeq->cmdinfo.work, fn); 1921 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, 1922 ADMIN_TIMEOUT); 1923 } 1924 1925 static void nvme_del_cq_work_handler(struct kthread_work *work) 1926 { 1927 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1928 cmdinfo.work); 1929 nvme_del_queue_end(nvmeq); 1930 } 1931 1932 static int nvme_delete_cq(struct nvme_queue *nvmeq) 1933 { 1934 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, 1935 nvme_del_cq_work_handler); 1936 } 1937 1938 static void nvme_del_sq_work_handler(struct kthread_work *work) 1939 { 1940 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1941 cmdinfo.work); 1942 int status = nvmeq->cmdinfo.status; 1943 1944 if (!status) 1945 status = nvme_delete_cq(nvmeq); 1946 if (status) 1947 nvme_del_queue_end(nvmeq); 1948 } 1949 1950 static int nvme_delete_sq(struct nvme_queue *nvmeq) 1951 { 1952 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, 1953 nvme_del_sq_work_handler); 1954 } 1955 1956 static void nvme_del_queue_start(struct kthread_work *work) 1957 { 1958 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1959 cmdinfo.work); 1960 if (nvme_delete_sq(nvmeq)) 1961 nvme_del_queue_end(nvmeq); 1962 } 1963 1964 static void nvme_disable_io_queues(struct nvme_dev *dev) 1965 { 1966 int i; 1967 DEFINE_KTHREAD_WORKER_ONSTACK(worker); 1968 struct nvme_delq_ctx dq; 1969 struct task_struct *kworker_task = kthread_run(kthread_worker_fn, 1970 &worker, "nvme%d", dev->ctrl.instance); 1971 1972 if (IS_ERR(kworker_task)) { 1973 dev_err(dev->dev, 1974 "Failed to create queue del task\n"); 1975 for (i = dev->queue_count - 1; i > 0; i--) 1976 nvme_disable_queue(dev, i); 1977 return; 1978 } 1979 1980 dq.waiter = NULL; 1981 atomic_set(&dq.refcount, 0); 1982 dq.worker = &worker; 1983 for (i = dev->queue_count - 1; i > 0; i--) { 1984 struct nvme_queue *nvmeq = dev->queues[i]; 1985 1986 if (nvme_suspend_queue(nvmeq)) 1987 continue; 1988 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); 1989 nvmeq->cmdinfo.worker = dq.worker; 1990 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); 1991 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); 1992 } 1993 nvme_wait_dq(&dq, dev); 1994 kthread_stop(kworker_task); 1995 } 1996 1997 /* 1998 * Remove the node from the device list and check 1999 * for whether or not we need to stop the nvme_thread. 2000 */ 2001 static void nvme_dev_list_remove(struct nvme_dev *dev) 2002 { 2003 struct task_struct *tmp = NULL; 2004 2005 spin_lock(&dev_list_lock); 2006 list_del_init(&dev->node); 2007 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { 2008 tmp = nvme_thread; 2009 nvme_thread = NULL; 2010 } 2011 spin_unlock(&dev_list_lock); 2012 2013 if (tmp) 2014 kthread_stop(tmp); 2015 } 2016 2017 static void nvme_freeze_queues(struct nvme_dev *dev) 2018 { 2019 struct nvme_ns *ns; 2020 2021 list_for_each_entry(ns, &dev->ctrl.namespaces, list) { 2022 blk_mq_freeze_queue_start(ns->queue); 2023 2024 spin_lock_irq(ns->queue->queue_lock); 2025 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); 2026 spin_unlock_irq(ns->queue->queue_lock); 2027 2028 blk_mq_cancel_requeue_work(ns->queue); 2029 blk_mq_stop_hw_queues(ns->queue); 2030 } 2031 } 2032 2033 static void nvme_unfreeze_queues(struct nvme_dev *dev) 2034 { 2035 struct nvme_ns *ns; 2036 2037 list_for_each_entry(ns, &dev->ctrl.namespaces, list) { 2038 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); 2039 blk_mq_unfreeze_queue(ns->queue); 2040 blk_mq_start_stopped_hw_queues(ns->queue, true); 2041 blk_mq_kick_requeue_list(ns->queue); 2042 } 2043 } 2044 2045 static void nvme_dev_shutdown(struct nvme_dev *dev) 2046 { 2047 int i; 2048 u32 csts = -1; 2049 2050 nvme_dev_list_remove(dev); 2051 2052 if (dev->bar) { 2053 nvme_freeze_queues(dev); 2054 csts = readl(dev->bar + NVME_REG_CSTS); 2055 } 2056 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { 2057 for (i = dev->queue_count - 1; i >= 0; i--) { 2058 struct nvme_queue *nvmeq = dev->queues[i]; 2059 nvme_suspend_queue(nvmeq); 2060 } 2061 } else { 2062 nvme_disable_io_queues(dev); 2063 nvme_shutdown_ctrl(&dev->ctrl); 2064 nvme_disable_queue(dev, 0); 2065 } 2066 nvme_dev_unmap(dev); 2067 2068 for (i = dev->queue_count - 1; i >= 0; i--) 2069 nvme_clear_queue(dev->queues[i]); 2070 } 2071 2072 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2073 { 2074 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2075 PAGE_SIZE, PAGE_SIZE, 0); 2076 if (!dev->prp_page_pool) 2077 return -ENOMEM; 2078 2079 /* Optimisation for I/Os between 4k and 128k */ 2080 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2081 256, 256, 0); 2082 if (!dev->prp_small_pool) { 2083 dma_pool_destroy(dev->prp_page_pool); 2084 return -ENOMEM; 2085 } 2086 return 0; 2087 } 2088 2089 static void nvme_release_prp_pools(struct nvme_dev *dev) 2090 { 2091 dma_pool_destroy(dev->prp_page_pool); 2092 dma_pool_destroy(dev->prp_small_pool); 2093 } 2094 2095 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2096 { 2097 struct nvme_dev *dev = to_nvme_dev(ctrl); 2098 2099 put_device(dev->dev); 2100 if (dev->tagset.tags) 2101 blk_mq_free_tag_set(&dev->tagset); 2102 if (dev->ctrl.admin_q) 2103 blk_put_queue(dev->ctrl.admin_q); 2104 kfree(dev->queues); 2105 kfree(dev->entry); 2106 kfree(dev); 2107 } 2108 2109 static void nvme_probe_work(struct work_struct *work) 2110 { 2111 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); 2112 bool start_thread = false; 2113 int result; 2114 2115 result = nvme_dev_map(dev); 2116 if (result) 2117 goto out; 2118 2119 result = nvme_configure_admin_queue(dev); 2120 if (result) 2121 goto unmap; 2122 2123 spin_lock(&dev_list_lock); 2124 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { 2125 start_thread = true; 2126 nvme_thread = NULL; 2127 } 2128 list_add(&dev->node, &dev_list); 2129 spin_unlock(&dev_list_lock); 2130 2131 if (start_thread) { 2132 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); 2133 wake_up_all(&nvme_kthread_wait); 2134 } else 2135 wait_event_killable(nvme_kthread_wait, nvme_thread); 2136 2137 if (IS_ERR_OR_NULL(nvme_thread)) { 2138 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; 2139 goto disable; 2140 } 2141 2142 nvme_init_queue(dev->queues[0], 0); 2143 result = nvme_alloc_admin_tags(dev); 2144 if (result) 2145 goto disable; 2146 2147 result = nvme_init_identify(&dev->ctrl); 2148 if (result) 2149 goto free_tags; 2150 2151 result = nvme_setup_io_queues(dev); 2152 if (result) 2153 goto free_tags; 2154 2155 dev->ctrl.event_limit = 1; 2156 2157 /* 2158 * Keep the controller around but remove all namespaces if we don't have 2159 * any working I/O queue. 2160 */ 2161 if (dev->online_queues < 2) { 2162 dev_warn(dev->dev, "IO queues not created\n"); 2163 nvme_remove_namespaces(&dev->ctrl); 2164 } else { 2165 nvme_unfreeze_queues(dev); 2166 nvme_dev_add(dev); 2167 } 2168 2169 return; 2170 2171 free_tags: 2172 nvme_dev_remove_admin(dev); 2173 blk_put_queue(dev->ctrl.admin_q); 2174 dev->ctrl.admin_q = NULL; 2175 dev->queues[0]->tags = NULL; 2176 disable: 2177 nvme_disable_queue(dev, 0); 2178 nvme_dev_list_remove(dev); 2179 unmap: 2180 nvme_dev_unmap(dev); 2181 out: 2182 if (!work_busy(&dev->reset_work)) 2183 nvme_dead_ctrl(dev); 2184 } 2185 2186 static int nvme_remove_dead_ctrl(void *arg) 2187 { 2188 struct nvme_dev *dev = (struct nvme_dev *)arg; 2189 struct pci_dev *pdev = to_pci_dev(dev->dev); 2190 2191 if (pci_get_drvdata(pdev)) 2192 pci_stop_and_remove_bus_device_locked(pdev); 2193 nvme_put_ctrl(&dev->ctrl); 2194 return 0; 2195 } 2196 2197 static void nvme_dead_ctrl(struct nvme_dev *dev) 2198 { 2199 dev_warn(dev->dev, "Device failed to resume\n"); 2200 kref_get(&dev->ctrl.kref); 2201 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", 2202 dev->ctrl.instance))) { 2203 dev_err(dev->dev, 2204 "Failed to start controller remove task\n"); 2205 nvme_put_ctrl(&dev->ctrl); 2206 } 2207 } 2208 2209 static void nvme_reset_work(struct work_struct *ws) 2210 { 2211 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); 2212 bool in_probe = work_busy(&dev->probe_work); 2213 2214 nvme_dev_shutdown(dev); 2215 2216 /* Synchronize with device probe so that work will see failure status 2217 * and exit gracefully without trying to schedule another reset */ 2218 flush_work(&dev->probe_work); 2219 2220 /* Fail this device if reset occured during probe to avoid 2221 * infinite initialization loops. */ 2222 if (in_probe) { 2223 nvme_dead_ctrl(dev); 2224 return; 2225 } 2226 /* Schedule device resume asynchronously so the reset work is available 2227 * to cleanup errors that may occur during reinitialization */ 2228 schedule_work(&dev->probe_work); 2229 } 2230 2231 static int __nvme_reset(struct nvme_dev *dev) 2232 { 2233 if (work_pending(&dev->reset_work)) 2234 return -EBUSY; 2235 list_del_init(&dev->node); 2236 queue_work(nvme_workq, &dev->reset_work); 2237 return 0; 2238 } 2239 2240 static int nvme_reset(struct nvme_dev *dev) 2241 { 2242 int ret; 2243 2244 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 2245 return -ENODEV; 2246 2247 spin_lock(&dev_list_lock); 2248 ret = __nvme_reset(dev); 2249 spin_unlock(&dev_list_lock); 2250 2251 if (!ret) { 2252 flush_work(&dev->reset_work); 2253 flush_work(&dev->probe_work); 2254 return 0; 2255 } 2256 2257 return ret; 2258 } 2259 2260 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2261 { 2262 *val = readl(to_nvme_dev(ctrl)->bar + off); 2263 return 0; 2264 } 2265 2266 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2267 { 2268 writel(val, to_nvme_dev(ctrl)->bar + off); 2269 return 0; 2270 } 2271 2272 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2273 { 2274 *val = readq(to_nvme_dev(ctrl)->bar + off); 2275 return 0; 2276 } 2277 2278 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) 2279 { 2280 struct nvme_dev *dev = to_nvme_dev(ctrl); 2281 2282 return !dev->bar || dev->online_queues < 2; 2283 } 2284 2285 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 2286 { 2287 return nvme_reset(to_nvme_dev(ctrl)); 2288 } 2289 2290 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2291 .reg_read32 = nvme_pci_reg_read32, 2292 .reg_write32 = nvme_pci_reg_write32, 2293 .reg_read64 = nvme_pci_reg_read64, 2294 .io_incapable = nvme_pci_io_incapable, 2295 .reset_ctrl = nvme_pci_reset_ctrl, 2296 .free_ctrl = nvme_pci_free_ctrl, 2297 }; 2298 2299 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2300 { 2301 int node, result = -ENOMEM; 2302 struct nvme_dev *dev; 2303 2304 node = dev_to_node(&pdev->dev); 2305 if (node == NUMA_NO_NODE) 2306 set_dev_node(&pdev->dev, 0); 2307 2308 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2309 if (!dev) 2310 return -ENOMEM; 2311 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), 2312 GFP_KERNEL, node); 2313 if (!dev->entry) 2314 goto free; 2315 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 2316 GFP_KERNEL, node); 2317 if (!dev->queues) 2318 goto free; 2319 2320 dev->dev = get_device(&pdev->dev); 2321 pci_set_drvdata(pdev, dev); 2322 2323 INIT_LIST_HEAD(&dev->node); 2324 INIT_WORK(&dev->scan_work, nvme_dev_scan); 2325 INIT_WORK(&dev->probe_work, nvme_probe_work); 2326 INIT_WORK(&dev->reset_work, nvme_reset_work); 2327 2328 result = nvme_setup_prp_pools(dev); 2329 if (result) 2330 goto put_pci; 2331 2332 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2333 id->driver_data); 2334 if (result) 2335 goto release_pools; 2336 2337 schedule_work(&dev->probe_work); 2338 return 0; 2339 2340 release_pools: 2341 nvme_release_prp_pools(dev); 2342 put_pci: 2343 put_device(dev->dev); 2344 free: 2345 kfree(dev->queues); 2346 kfree(dev->entry); 2347 kfree(dev); 2348 return result; 2349 } 2350 2351 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) 2352 { 2353 struct nvme_dev *dev = pci_get_drvdata(pdev); 2354 2355 if (prepare) 2356 nvme_dev_shutdown(dev); 2357 else 2358 schedule_work(&dev->probe_work); 2359 } 2360 2361 static void nvme_shutdown(struct pci_dev *pdev) 2362 { 2363 struct nvme_dev *dev = pci_get_drvdata(pdev); 2364 nvme_dev_shutdown(dev); 2365 } 2366 2367 static void nvme_remove(struct pci_dev *pdev) 2368 { 2369 struct nvme_dev *dev = pci_get_drvdata(pdev); 2370 2371 spin_lock(&dev_list_lock); 2372 list_del_init(&dev->node); 2373 spin_unlock(&dev_list_lock); 2374 2375 pci_set_drvdata(pdev, NULL); 2376 flush_work(&dev->probe_work); 2377 flush_work(&dev->reset_work); 2378 flush_work(&dev->scan_work); 2379 nvme_remove_namespaces(&dev->ctrl); 2380 nvme_dev_shutdown(dev); 2381 nvme_dev_remove_admin(dev); 2382 nvme_free_queues(dev, 0); 2383 nvme_release_cmb(dev); 2384 nvme_release_prp_pools(dev); 2385 nvme_put_ctrl(&dev->ctrl); 2386 } 2387 2388 /* These functions are yet to be implemented */ 2389 #define nvme_error_detected NULL 2390 #define nvme_dump_registers NULL 2391 #define nvme_link_reset NULL 2392 #define nvme_slot_reset NULL 2393 #define nvme_error_resume NULL 2394 2395 #ifdef CONFIG_PM_SLEEP 2396 static int nvme_suspend(struct device *dev) 2397 { 2398 struct pci_dev *pdev = to_pci_dev(dev); 2399 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2400 2401 nvme_dev_shutdown(ndev); 2402 return 0; 2403 } 2404 2405 static int nvme_resume(struct device *dev) 2406 { 2407 struct pci_dev *pdev = to_pci_dev(dev); 2408 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2409 2410 schedule_work(&ndev->probe_work); 2411 return 0; 2412 } 2413 #endif 2414 2415 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2416 2417 static const struct pci_error_handlers nvme_err_handler = { 2418 .error_detected = nvme_error_detected, 2419 .mmio_enabled = nvme_dump_registers, 2420 .link_reset = nvme_link_reset, 2421 .slot_reset = nvme_slot_reset, 2422 .resume = nvme_error_resume, 2423 .reset_notify = nvme_reset_notify, 2424 }; 2425 2426 /* Move to pci_ids.h later */ 2427 #define PCI_CLASS_STORAGE_EXPRESS 0x010802 2428 2429 static const struct pci_device_id nvme_id_table[] = { 2430 { PCI_VDEVICE(INTEL, 0x0953), 2431 .driver_data = NVME_QUIRK_STRIPE_SIZE, }, 2432 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2433 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2434 { 0, } 2435 }; 2436 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2437 2438 static struct pci_driver nvme_driver = { 2439 .name = "nvme", 2440 .id_table = nvme_id_table, 2441 .probe = nvme_probe, 2442 .remove = nvme_remove, 2443 .shutdown = nvme_shutdown, 2444 .driver = { 2445 .pm = &nvme_dev_pm_ops, 2446 }, 2447 .err_handler = &nvme_err_handler, 2448 }; 2449 2450 static int __init nvme_init(void) 2451 { 2452 int result; 2453 2454 init_waitqueue_head(&nvme_kthread_wait); 2455 2456 nvme_workq = create_singlethread_workqueue("nvme"); 2457 if (!nvme_workq) 2458 return -ENOMEM; 2459 2460 result = nvme_core_init(); 2461 if (result < 0) 2462 goto kill_workq; 2463 2464 result = pci_register_driver(&nvme_driver); 2465 if (result) 2466 goto core_exit; 2467 return 0; 2468 2469 core_exit: 2470 nvme_core_exit(); 2471 kill_workq: 2472 destroy_workqueue(nvme_workq); 2473 return result; 2474 } 2475 2476 static void __exit nvme_exit(void) 2477 { 2478 pci_unregister_driver(&nvme_driver); 2479 nvme_core_exit(); 2480 destroy_workqueue(nvme_workq); 2481 BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); 2482 _nvme_check_size(); 2483 } 2484 2485 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2486 MODULE_LICENSE("GPL"); 2487 MODULE_VERSION("1.0"); 2488 module_init(nvme_init); 2489 module_exit(nvme_exit); 2490