1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/aer.h> 9 #include <linux/async.h> 10 #include <linux/blkdev.h> 11 #include <linux/blk-mq.h> 12 #include <linux/blk-mq-pci.h> 13 #include <linux/blk-integrity.h> 14 #include <linux/dmi.h> 15 #include <linux/init.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/memremap.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/once.h> 23 #include <linux/pci.h> 24 #include <linux/suspend.h> 25 #include <linux/t10-pi.h> 26 #include <linux/types.h> 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #include <linux/io-64-nonatomic-hi-lo.h> 29 #include <linux/sed-opal.h> 30 #include <linux/pci-p2pdma.h> 31 32 #include "trace.h" 33 #include "nvme.h" 34 35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 37 38 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39 40 /* 41 * These can be higher, but we need to ensure that any command doesn't 42 * require an sg allocation that needs more than a page of data. 43 */ 44 #define NVME_MAX_KB_SZ 4096 45 #define NVME_MAX_SEGS 127 46 47 static int use_threaded_interrupts; 48 module_param(use_threaded_interrupts, int, 0444); 49 50 static bool use_cmb_sqes = true; 51 module_param(use_cmb_sqes, bool, 0444); 52 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 53 54 static unsigned int max_host_mem_size_mb = 128; 55 module_param(max_host_mem_size_mb, uint, 0444); 56 MODULE_PARM_DESC(max_host_mem_size_mb, 57 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 58 59 static unsigned int sgl_threshold = SZ_32K; 60 module_param(sgl_threshold, uint, 0644); 61 MODULE_PARM_DESC(sgl_threshold, 62 "Use SGLs when average request segment size is larger or equal to " 63 "this size. Use 0 to disable SGLs."); 64 65 #define NVME_PCI_MIN_QUEUE_SIZE 2 66 #define NVME_PCI_MAX_QUEUE_SIZE 4095 67 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68 static const struct kernel_param_ops io_queue_depth_ops = { 69 .set = io_queue_depth_set, 70 .get = param_get_uint, 71 }; 72 73 static unsigned int io_queue_depth = 1024; 74 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76 77 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 78 { 79 unsigned int n; 80 int ret; 81 82 ret = kstrtouint(val, 10, &n); 83 if (ret != 0 || n > num_possible_cpus()) 84 return -EINVAL; 85 return param_set_uint(val, kp); 86 } 87 88 static const struct kernel_param_ops io_queue_count_ops = { 89 .set = io_queue_count_set, 90 .get = param_get_uint, 91 }; 92 93 static unsigned int write_queues; 94 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 95 MODULE_PARM_DESC(write_queues, 96 "Number of queues to use for writes. If not set, reads and writes " 97 "will share a queue set."); 98 99 static unsigned int poll_queues; 100 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 101 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 102 103 static bool noacpi; 104 module_param(noacpi, bool, 0444); 105 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106 107 struct nvme_dev; 108 struct nvme_queue; 109 110 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 111 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 112 113 /* 114 * Represents an NVM Express device. Each nvme_dev is a PCI function. 115 */ 116 struct nvme_dev { 117 struct nvme_queue *queues; 118 struct blk_mq_tag_set tagset; 119 struct blk_mq_tag_set admin_tagset; 120 u32 __iomem *dbs; 121 struct device *dev; 122 struct dma_pool *prp_page_pool; 123 struct dma_pool *prp_small_pool; 124 unsigned online_queues; 125 unsigned max_qid; 126 unsigned io_queues[HCTX_MAX_TYPES]; 127 unsigned int num_vecs; 128 u32 q_depth; 129 int io_sqes; 130 u32 db_stride; 131 void __iomem *bar; 132 unsigned long bar_mapped_size; 133 struct work_struct remove_work; 134 struct mutex shutdown_lock; 135 bool subsystem; 136 u64 cmb_size; 137 bool cmb_use_sqes; 138 u32 cmbsz; 139 u32 cmbloc; 140 struct nvme_ctrl ctrl; 141 u32 last_ps; 142 bool hmb; 143 144 mempool_t *iod_mempool; 145 146 /* shadow doorbell buffer support: */ 147 u32 *dbbuf_dbs; 148 dma_addr_t dbbuf_dbs_dma_addr; 149 u32 *dbbuf_eis; 150 dma_addr_t dbbuf_eis_dma_addr; 151 152 /* host memory buffer support: */ 153 u64 host_mem_size; 154 u32 nr_host_mem_descs; 155 dma_addr_t host_mem_descs_dma; 156 struct nvme_host_mem_buf_desc *host_mem_descs; 157 void **host_mem_desc_bufs; 158 unsigned int nr_allocated_queues; 159 unsigned int nr_write_queues; 160 unsigned int nr_poll_queues; 161 162 bool attrs_added; 163 }; 164 165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 166 { 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 168 NVME_PCI_MAX_QUEUE_SIZE); 169 } 170 171 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 172 { 173 return qid * 2 * stride; 174 } 175 176 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 177 { 178 return (qid * 2 + 1) * stride; 179 } 180 181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 182 { 183 return container_of(ctrl, struct nvme_dev, ctrl); 184 } 185 186 /* 187 * An NVM Express queue. Each device has at least two (one for admin 188 * commands and one for I/O commands). 189 */ 190 struct nvme_queue { 191 struct nvme_dev *dev; 192 spinlock_t sq_lock; 193 void *sq_cmds; 194 /* only used for poll queues: */ 195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 196 struct nvme_completion *cqes; 197 dma_addr_t sq_dma_addr; 198 dma_addr_t cq_dma_addr; 199 u32 __iomem *q_db; 200 u32 q_depth; 201 u16 cq_vector; 202 u16 sq_tail; 203 u16 last_sq_tail; 204 u16 cq_head; 205 u16 qid; 206 u8 cq_phase; 207 u8 sqes; 208 unsigned long flags; 209 #define NVMEQ_ENABLED 0 210 #define NVMEQ_SQ_CMB 1 211 #define NVMEQ_DELETE_ERROR 2 212 #define NVMEQ_POLLED 3 213 u32 *dbbuf_sq_db; 214 u32 *dbbuf_cq_db; 215 u32 *dbbuf_sq_ei; 216 u32 *dbbuf_cq_ei; 217 struct completion delete_done; 218 }; 219 220 /* 221 * The nvme_iod describes the data in an I/O. 222 * 223 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 224 * to the actual struct scatterlist. 225 */ 226 struct nvme_iod { 227 struct nvme_request req; 228 struct nvme_command cmd; 229 struct nvme_queue *nvmeq; 230 bool use_sgl; 231 int aborted; 232 int npages; /* In the PRP list. 0 means small pool in use */ 233 int nents; /* Used in scatterlist */ 234 dma_addr_t first_dma; 235 unsigned int dma_len; /* length of single DMA segment mapping */ 236 dma_addr_t meta_dma; 237 struct scatterlist *sg; 238 }; 239 240 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 241 { 242 return dev->nr_allocated_queues * 8 * dev->db_stride; 243 } 244 245 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 246 { 247 unsigned int mem_size = nvme_dbbuf_size(dev); 248 249 if (dev->dbbuf_dbs) { 250 /* 251 * Clear the dbbuf memory so the driver doesn't observe stale 252 * values from the previous instantiation. 253 */ 254 memset(dev->dbbuf_dbs, 0, mem_size); 255 memset(dev->dbbuf_eis, 0, mem_size); 256 return 0; 257 } 258 259 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 260 &dev->dbbuf_dbs_dma_addr, 261 GFP_KERNEL); 262 if (!dev->dbbuf_dbs) 263 return -ENOMEM; 264 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 265 &dev->dbbuf_eis_dma_addr, 266 GFP_KERNEL); 267 if (!dev->dbbuf_eis) { 268 dma_free_coherent(dev->dev, mem_size, 269 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 270 dev->dbbuf_dbs = NULL; 271 return -ENOMEM; 272 } 273 274 return 0; 275 } 276 277 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 278 { 279 unsigned int mem_size = nvme_dbbuf_size(dev); 280 281 if (dev->dbbuf_dbs) { 282 dma_free_coherent(dev->dev, mem_size, 283 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 284 dev->dbbuf_dbs = NULL; 285 } 286 if (dev->dbbuf_eis) { 287 dma_free_coherent(dev->dev, mem_size, 288 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 289 dev->dbbuf_eis = NULL; 290 } 291 } 292 293 static void nvme_dbbuf_init(struct nvme_dev *dev, 294 struct nvme_queue *nvmeq, int qid) 295 { 296 if (!dev->dbbuf_dbs || !qid) 297 return; 298 299 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 300 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 301 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 302 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 303 } 304 305 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 306 { 307 if (!nvmeq->qid) 308 return; 309 310 nvmeq->dbbuf_sq_db = NULL; 311 nvmeq->dbbuf_cq_db = NULL; 312 nvmeq->dbbuf_sq_ei = NULL; 313 nvmeq->dbbuf_cq_ei = NULL; 314 } 315 316 static void nvme_dbbuf_set(struct nvme_dev *dev) 317 { 318 struct nvme_command c = { }; 319 unsigned int i; 320 321 if (!dev->dbbuf_dbs) 322 return; 323 324 c.dbbuf.opcode = nvme_admin_dbbuf; 325 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 326 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 327 328 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 329 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 330 /* Free memory and continue on */ 331 nvme_dbbuf_dma_free(dev); 332 333 for (i = 1; i <= dev->online_queues; i++) 334 nvme_dbbuf_free(&dev->queues[i]); 335 } 336 } 337 338 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 339 { 340 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 341 } 342 343 /* Update dbbuf and return true if an MMIO is required */ 344 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 345 volatile u32 *dbbuf_ei) 346 { 347 if (dbbuf_db) { 348 u16 old_value; 349 350 /* 351 * Ensure that the queue is written before updating 352 * the doorbell in memory 353 */ 354 wmb(); 355 356 old_value = *dbbuf_db; 357 *dbbuf_db = value; 358 359 /* 360 * Ensure that the doorbell is updated before reading the event 361 * index from memory. The controller needs to provide similar 362 * ordering to ensure the envent index is updated before reading 363 * the doorbell. 364 */ 365 mb(); 366 367 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 368 return false; 369 } 370 371 return true; 372 } 373 374 /* 375 * Will slightly overestimate the number of pages needed. This is OK 376 * as it only leads to a small amount of wasted memory for the lifetime of 377 * the I/O. 378 */ 379 static int nvme_pci_npages_prp(void) 380 { 381 unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 382 NVME_CTRL_PAGE_SIZE); 383 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 384 } 385 386 /* 387 * Calculates the number of pages needed for the SGL segments. For example a 4k 388 * page can accommodate 256 SGL descriptors. 389 */ 390 static int nvme_pci_npages_sgl(void) 391 { 392 return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 393 PAGE_SIZE); 394 } 395 396 static size_t nvme_pci_iod_alloc_size(void) 397 { 398 size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 399 400 return sizeof(__le64 *) * npages + 401 sizeof(struct scatterlist) * NVME_MAX_SEGS; 402 } 403 404 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 405 unsigned int hctx_idx) 406 { 407 struct nvme_dev *dev = data; 408 struct nvme_queue *nvmeq = &dev->queues[0]; 409 410 WARN_ON(hctx_idx != 0); 411 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 412 413 hctx->driver_data = nvmeq; 414 return 0; 415 } 416 417 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 418 unsigned int hctx_idx) 419 { 420 struct nvme_dev *dev = data; 421 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 422 423 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 424 hctx->driver_data = nvmeq; 425 return 0; 426 } 427 428 static int nvme_pci_init_request(struct blk_mq_tag_set *set, 429 struct request *req, unsigned int hctx_idx, 430 unsigned int numa_node) 431 { 432 struct nvme_dev *dev = set->driver_data; 433 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 434 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 435 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 436 437 BUG_ON(!nvmeq); 438 iod->nvmeq = nvmeq; 439 440 nvme_req(req)->ctrl = &dev->ctrl; 441 nvme_req(req)->cmd = &iod->cmd; 442 return 0; 443 } 444 445 static int queue_irq_offset(struct nvme_dev *dev) 446 { 447 /* if we have more than 1 vec, admin queue offsets us by 1 */ 448 if (dev->num_vecs > 1) 449 return 1; 450 451 return 0; 452 } 453 454 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 455 { 456 struct nvme_dev *dev = set->driver_data; 457 int i, qoff, offset; 458 459 offset = queue_irq_offset(dev); 460 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 461 struct blk_mq_queue_map *map = &set->map[i]; 462 463 map->nr_queues = dev->io_queues[i]; 464 if (!map->nr_queues) { 465 BUG_ON(i == HCTX_TYPE_DEFAULT); 466 continue; 467 } 468 469 /* 470 * The poll queue(s) doesn't have an IRQ (and hence IRQ 471 * affinity), so use the regular blk-mq cpu mapping 472 */ 473 map->queue_offset = qoff; 474 if (i != HCTX_TYPE_POLL && offset) 475 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 476 else 477 blk_mq_map_queues(map); 478 qoff += map->nr_queues; 479 offset += map->nr_queues; 480 } 481 482 return 0; 483 } 484 485 /* 486 * Write sq tail if we are asked to, or if the next command would wrap. 487 */ 488 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 489 { 490 if (!write_sq) { 491 u16 next_tail = nvmeq->sq_tail + 1; 492 493 if (next_tail == nvmeq->q_depth) 494 next_tail = 0; 495 if (next_tail != nvmeq->last_sq_tail) 496 return; 497 } 498 499 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 500 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 501 writel(nvmeq->sq_tail, nvmeq->q_db); 502 nvmeq->last_sq_tail = nvmeq->sq_tail; 503 } 504 505 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 506 struct nvme_command *cmd) 507 { 508 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 509 absolute_pointer(cmd), sizeof(*cmd)); 510 if (++nvmeq->sq_tail == nvmeq->q_depth) 511 nvmeq->sq_tail = 0; 512 } 513 514 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 515 { 516 struct nvme_queue *nvmeq = hctx->driver_data; 517 518 spin_lock(&nvmeq->sq_lock); 519 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 520 nvme_write_sq_db(nvmeq, true); 521 spin_unlock(&nvmeq->sq_lock); 522 } 523 524 static void **nvme_pci_iod_list(struct request *req) 525 { 526 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 527 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 528 } 529 530 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 531 { 532 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 533 int nseg = blk_rq_nr_phys_segments(req); 534 unsigned int avg_seg_size; 535 536 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 537 538 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 539 return false; 540 if (!iod->nvmeq->qid) 541 return false; 542 if (!sgl_threshold || avg_seg_size < sgl_threshold) 543 return false; 544 return true; 545 } 546 547 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 548 { 549 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 550 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 551 dma_addr_t dma_addr = iod->first_dma; 552 int i; 553 554 for (i = 0; i < iod->npages; i++) { 555 __le64 *prp_list = nvme_pci_iod_list(req)[i]; 556 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 557 558 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 559 dma_addr = next_dma_addr; 560 } 561 } 562 563 static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 564 { 565 const int last_sg = SGES_PER_PAGE - 1; 566 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 567 dma_addr_t dma_addr = iod->first_dma; 568 int i; 569 570 for (i = 0; i < iod->npages; i++) { 571 struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 572 dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 573 574 dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 575 dma_addr = next_dma_addr; 576 } 577 } 578 579 static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 580 { 581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 582 583 if (is_pci_p2pdma_page(sg_page(iod->sg))) 584 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 585 rq_dma_dir(req)); 586 else 587 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 588 } 589 590 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 591 { 592 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 593 594 if (iod->dma_len) { 595 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 596 rq_dma_dir(req)); 597 return; 598 } 599 600 WARN_ON_ONCE(!iod->nents); 601 602 nvme_unmap_sg(dev, req); 603 if (iod->npages == 0) 604 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 605 iod->first_dma); 606 else if (iod->use_sgl) 607 nvme_free_sgls(dev, req); 608 else 609 nvme_free_prps(dev, req); 610 mempool_free(iod->sg, dev->iod_mempool); 611 } 612 613 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 614 { 615 int i; 616 struct scatterlist *sg; 617 618 for_each_sg(sgl, sg, nents, i) { 619 dma_addr_t phys = sg_phys(sg); 620 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 621 "dma_address:%pad dma_length:%d\n", 622 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 623 sg_dma_len(sg)); 624 } 625 } 626 627 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 628 struct request *req, struct nvme_rw_command *cmnd) 629 { 630 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 631 struct dma_pool *pool; 632 int length = blk_rq_payload_bytes(req); 633 struct scatterlist *sg = iod->sg; 634 int dma_len = sg_dma_len(sg); 635 u64 dma_addr = sg_dma_address(sg); 636 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 637 __le64 *prp_list; 638 void **list = nvme_pci_iod_list(req); 639 dma_addr_t prp_dma; 640 int nprps, i; 641 642 length -= (NVME_CTRL_PAGE_SIZE - offset); 643 if (length <= 0) { 644 iod->first_dma = 0; 645 goto done; 646 } 647 648 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 649 if (dma_len) { 650 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 651 } else { 652 sg = sg_next(sg); 653 dma_addr = sg_dma_address(sg); 654 dma_len = sg_dma_len(sg); 655 } 656 657 if (length <= NVME_CTRL_PAGE_SIZE) { 658 iod->first_dma = dma_addr; 659 goto done; 660 } 661 662 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 663 if (nprps <= (256 / 8)) { 664 pool = dev->prp_small_pool; 665 iod->npages = 0; 666 } else { 667 pool = dev->prp_page_pool; 668 iod->npages = 1; 669 } 670 671 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 672 if (!prp_list) { 673 iod->npages = -1; 674 return BLK_STS_RESOURCE; 675 } 676 list[0] = prp_list; 677 iod->first_dma = prp_dma; 678 i = 0; 679 for (;;) { 680 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 681 __le64 *old_prp_list = prp_list; 682 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 683 if (!prp_list) 684 goto free_prps; 685 list[iod->npages++] = prp_list; 686 prp_list[0] = old_prp_list[i - 1]; 687 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 688 i = 1; 689 } 690 prp_list[i++] = cpu_to_le64(dma_addr); 691 dma_len -= NVME_CTRL_PAGE_SIZE; 692 dma_addr += NVME_CTRL_PAGE_SIZE; 693 length -= NVME_CTRL_PAGE_SIZE; 694 if (length <= 0) 695 break; 696 if (dma_len > 0) 697 continue; 698 if (unlikely(dma_len < 0)) 699 goto bad_sgl; 700 sg = sg_next(sg); 701 dma_addr = sg_dma_address(sg); 702 dma_len = sg_dma_len(sg); 703 } 704 done: 705 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 706 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 707 return BLK_STS_OK; 708 free_prps: 709 nvme_free_prps(dev, req); 710 return BLK_STS_RESOURCE; 711 bad_sgl: 712 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 713 "Invalid SGL for payload:%d nents:%d\n", 714 blk_rq_payload_bytes(req), iod->nents); 715 return BLK_STS_IOERR; 716 } 717 718 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 719 struct scatterlist *sg) 720 { 721 sge->addr = cpu_to_le64(sg_dma_address(sg)); 722 sge->length = cpu_to_le32(sg_dma_len(sg)); 723 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 724 } 725 726 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 727 dma_addr_t dma_addr, int entries) 728 { 729 sge->addr = cpu_to_le64(dma_addr); 730 if (entries < SGES_PER_PAGE) { 731 sge->length = cpu_to_le32(entries * sizeof(*sge)); 732 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 733 } else { 734 sge->length = cpu_to_le32(PAGE_SIZE); 735 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 736 } 737 } 738 739 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 740 struct request *req, struct nvme_rw_command *cmd, int entries) 741 { 742 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 743 struct dma_pool *pool; 744 struct nvme_sgl_desc *sg_list; 745 struct scatterlist *sg = iod->sg; 746 dma_addr_t sgl_dma; 747 int i = 0; 748 749 /* setting the transfer type as SGL */ 750 cmd->flags = NVME_CMD_SGL_METABUF; 751 752 if (entries == 1) { 753 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 754 return BLK_STS_OK; 755 } 756 757 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 758 pool = dev->prp_small_pool; 759 iod->npages = 0; 760 } else { 761 pool = dev->prp_page_pool; 762 iod->npages = 1; 763 } 764 765 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 766 if (!sg_list) { 767 iod->npages = -1; 768 return BLK_STS_RESOURCE; 769 } 770 771 nvme_pci_iod_list(req)[0] = sg_list; 772 iod->first_dma = sgl_dma; 773 774 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 775 776 do { 777 if (i == SGES_PER_PAGE) { 778 struct nvme_sgl_desc *old_sg_desc = sg_list; 779 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 780 781 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 782 if (!sg_list) 783 goto free_sgls; 784 785 i = 0; 786 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 787 sg_list[i++] = *link; 788 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 789 } 790 791 nvme_pci_sgl_set_data(&sg_list[i++], sg); 792 sg = sg_next(sg); 793 } while (--entries > 0); 794 795 return BLK_STS_OK; 796 free_sgls: 797 nvme_free_sgls(dev, req); 798 return BLK_STS_RESOURCE; 799 } 800 801 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 802 struct request *req, struct nvme_rw_command *cmnd, 803 struct bio_vec *bv) 804 { 805 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 806 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 807 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 808 809 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 810 if (dma_mapping_error(dev->dev, iod->first_dma)) 811 return BLK_STS_RESOURCE; 812 iod->dma_len = bv->bv_len; 813 814 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 815 if (bv->bv_len > first_prp_len) 816 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 817 return BLK_STS_OK; 818 } 819 820 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 821 struct request *req, struct nvme_rw_command *cmnd, 822 struct bio_vec *bv) 823 { 824 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 825 826 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 827 if (dma_mapping_error(dev->dev, iod->first_dma)) 828 return BLK_STS_RESOURCE; 829 iod->dma_len = bv->bv_len; 830 831 cmnd->flags = NVME_CMD_SGL_METABUF; 832 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 833 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 834 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 835 return BLK_STS_OK; 836 } 837 838 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 839 struct nvme_command *cmnd) 840 { 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 842 blk_status_t ret = BLK_STS_RESOURCE; 843 int nr_mapped; 844 845 if (blk_rq_nr_phys_segments(req) == 1) { 846 struct bio_vec bv = req_bvec(req); 847 848 if (!is_pci_p2pdma_page(bv.bv_page)) { 849 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 850 return nvme_setup_prp_simple(dev, req, 851 &cmnd->rw, &bv); 852 853 if (iod->nvmeq->qid && sgl_threshold && 854 nvme_ctrl_sgl_supported(&dev->ctrl)) 855 return nvme_setup_sgl_simple(dev, req, 856 &cmnd->rw, &bv); 857 } 858 } 859 860 iod->dma_len = 0; 861 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 862 if (!iod->sg) 863 return BLK_STS_RESOURCE; 864 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 865 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 866 if (!iod->nents) 867 goto out_free_sg; 868 869 if (is_pci_p2pdma_page(sg_page(iod->sg))) 870 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 871 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 872 else 873 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 874 rq_dma_dir(req), DMA_ATTR_NO_WARN); 875 if (!nr_mapped) 876 goto out_free_sg; 877 878 iod->use_sgl = nvme_pci_use_sgls(dev, req); 879 if (iod->use_sgl) 880 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 881 else 882 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 883 if (ret != BLK_STS_OK) 884 goto out_unmap_sg; 885 return BLK_STS_OK; 886 887 out_unmap_sg: 888 nvme_unmap_sg(dev, req); 889 out_free_sg: 890 mempool_free(iod->sg, dev->iod_mempool); 891 return ret; 892 } 893 894 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 895 struct nvme_command *cmnd) 896 { 897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 898 899 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 900 rq_dma_dir(req), 0); 901 if (dma_mapping_error(dev->dev, iod->meta_dma)) 902 return BLK_STS_IOERR; 903 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 904 return BLK_STS_OK; 905 } 906 907 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 908 { 909 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 910 blk_status_t ret; 911 912 iod->aborted = 0; 913 iod->npages = -1; 914 iod->nents = 0; 915 916 ret = nvme_setup_cmd(req->q->queuedata, req); 917 if (ret) 918 return ret; 919 920 if (blk_rq_nr_phys_segments(req)) { 921 ret = nvme_map_data(dev, req, &iod->cmd); 922 if (ret) 923 goto out_free_cmd; 924 } 925 926 if (blk_integrity_rq(req)) { 927 ret = nvme_map_metadata(dev, req, &iod->cmd); 928 if (ret) 929 goto out_unmap_data; 930 } 931 932 blk_mq_start_request(req); 933 return BLK_STS_OK; 934 out_unmap_data: 935 nvme_unmap_data(dev, req); 936 out_free_cmd: 937 nvme_cleanup_cmd(req); 938 return ret; 939 } 940 941 /* 942 * NOTE: ns is NULL when called on the admin queue. 943 */ 944 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 945 const struct blk_mq_queue_data *bd) 946 { 947 struct nvme_queue *nvmeq = hctx->driver_data; 948 struct nvme_dev *dev = nvmeq->dev; 949 struct request *req = bd->rq; 950 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 951 blk_status_t ret; 952 953 /* 954 * We should not need to do this, but we're still using this to 955 * ensure we can drain requests on a dying queue. 956 */ 957 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 958 return BLK_STS_IOERR; 959 960 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 961 return nvme_fail_nonready_command(&dev->ctrl, req); 962 963 ret = nvme_prep_rq(dev, req); 964 if (unlikely(ret)) 965 return ret; 966 spin_lock(&nvmeq->sq_lock); 967 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 968 nvme_write_sq_db(nvmeq, bd->last); 969 spin_unlock(&nvmeq->sq_lock); 970 return BLK_STS_OK; 971 } 972 973 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 974 { 975 spin_lock(&nvmeq->sq_lock); 976 while (!rq_list_empty(*rqlist)) { 977 struct request *req = rq_list_pop(rqlist); 978 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 979 980 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 981 } 982 nvme_write_sq_db(nvmeq, true); 983 spin_unlock(&nvmeq->sq_lock); 984 } 985 986 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 987 { 988 /* 989 * We should not need to do this, but we're still using this to 990 * ensure we can drain requests on a dying queue. 991 */ 992 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 993 return false; 994 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 995 return false; 996 997 req->mq_hctx->tags->rqs[req->tag] = req; 998 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 999 } 1000 1001 static void nvme_queue_rqs(struct request **rqlist) 1002 { 1003 struct request *req, *next, *prev = NULL; 1004 struct request *requeue_list = NULL; 1005 1006 rq_list_for_each_safe(rqlist, req, next) { 1007 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1008 1009 if (!nvme_prep_rq_batch(nvmeq, req)) { 1010 /* detach 'req' and add to remainder list */ 1011 rq_list_move(rqlist, &requeue_list, req, prev); 1012 1013 req = prev; 1014 if (!req) 1015 continue; 1016 } 1017 1018 if (!next || req->mq_hctx != next->mq_hctx) { 1019 /* detach rest of list, and submit */ 1020 req->rq_next = NULL; 1021 nvme_submit_cmds(nvmeq, rqlist); 1022 *rqlist = next; 1023 prev = NULL; 1024 } else 1025 prev = req; 1026 } 1027 1028 *rqlist = requeue_list; 1029 } 1030 1031 static __always_inline void nvme_pci_unmap_rq(struct request *req) 1032 { 1033 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1034 struct nvme_dev *dev = iod->nvmeq->dev; 1035 1036 if (blk_integrity_rq(req)) 1037 dma_unmap_page(dev->dev, iod->meta_dma, 1038 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1039 if (blk_rq_nr_phys_segments(req)) 1040 nvme_unmap_data(dev, req); 1041 } 1042 1043 static void nvme_pci_complete_rq(struct request *req) 1044 { 1045 nvme_pci_unmap_rq(req); 1046 nvme_complete_rq(req); 1047 } 1048 1049 static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1050 { 1051 nvme_complete_batch(iob, nvme_pci_unmap_rq); 1052 } 1053 1054 /* We read the CQE phase first to check if the rest of the entry is valid */ 1055 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1056 { 1057 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 1058 1059 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1060 } 1061 1062 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 1063 { 1064 u16 head = nvmeq->cq_head; 1065 1066 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1067 nvmeq->dbbuf_cq_ei)) 1068 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1069 } 1070 1071 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1072 { 1073 if (!nvmeq->qid) 1074 return nvmeq->dev->admin_tagset.tags[0]; 1075 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1076 } 1077 1078 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1079 struct io_comp_batch *iob, u16 idx) 1080 { 1081 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1082 __u16 command_id = READ_ONCE(cqe->command_id); 1083 struct request *req; 1084 1085 /* 1086 * AEN requests are special as they don't time out and can 1087 * survive any kind of queue freeze and often don't respond to 1088 * aborts. We don't even bother to allocate a struct request 1089 * for them but rather special case them here. 1090 */ 1091 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1092 nvme_complete_async_event(&nvmeq->dev->ctrl, 1093 cqe->status, &cqe->result); 1094 return; 1095 } 1096 1097 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1098 if (unlikely(!req)) { 1099 dev_warn(nvmeq->dev->ctrl.device, 1100 "invalid id %d completed on queue %d\n", 1101 command_id, le16_to_cpu(cqe->sq_id)); 1102 return; 1103 } 1104 1105 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1106 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1107 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1108 nvme_pci_complete_batch)) 1109 nvme_pci_complete_rq(req); 1110 } 1111 1112 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1113 { 1114 u32 tmp = nvmeq->cq_head + 1; 1115 1116 if (tmp == nvmeq->q_depth) { 1117 nvmeq->cq_head = 0; 1118 nvmeq->cq_phase ^= 1; 1119 } else { 1120 nvmeq->cq_head = tmp; 1121 } 1122 } 1123 1124 static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1125 struct io_comp_batch *iob) 1126 { 1127 int found = 0; 1128 1129 while (nvme_cqe_pending(nvmeq)) { 1130 found++; 1131 /* 1132 * load-load control dependency between phase and the rest of 1133 * the cqe requires a full read memory barrier 1134 */ 1135 dma_rmb(); 1136 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 1137 nvme_update_cq_head(nvmeq); 1138 } 1139 1140 if (found) 1141 nvme_ring_cq_doorbell(nvmeq); 1142 return found; 1143 } 1144 1145 static irqreturn_t nvme_irq(int irq, void *data) 1146 { 1147 struct nvme_queue *nvmeq = data; 1148 DEFINE_IO_COMP_BATCH(iob); 1149 1150 if (nvme_poll_cq(nvmeq, &iob)) { 1151 if (!rq_list_empty(iob.req_list)) 1152 nvme_pci_complete_batch(&iob); 1153 return IRQ_HANDLED; 1154 } 1155 return IRQ_NONE; 1156 } 1157 1158 static irqreturn_t nvme_irq_check(int irq, void *data) 1159 { 1160 struct nvme_queue *nvmeq = data; 1161 1162 if (nvme_cqe_pending(nvmeq)) 1163 return IRQ_WAKE_THREAD; 1164 return IRQ_NONE; 1165 } 1166 1167 /* 1168 * Poll for completions for any interrupt driven queue 1169 * Can be called from any context. 1170 */ 1171 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1172 { 1173 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1174 1175 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1176 1177 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1178 nvme_poll_cq(nvmeq, NULL); 1179 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1180 } 1181 1182 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 1183 { 1184 struct nvme_queue *nvmeq = hctx->driver_data; 1185 bool found; 1186 1187 if (!nvme_cqe_pending(nvmeq)) 1188 return 0; 1189 1190 spin_lock(&nvmeq->cq_poll_lock); 1191 found = nvme_poll_cq(nvmeq, iob); 1192 spin_unlock(&nvmeq->cq_poll_lock); 1193 1194 return found; 1195 } 1196 1197 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1198 { 1199 struct nvme_dev *dev = to_nvme_dev(ctrl); 1200 struct nvme_queue *nvmeq = &dev->queues[0]; 1201 struct nvme_command c = { }; 1202 1203 c.common.opcode = nvme_admin_async_event; 1204 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1205 1206 spin_lock(&nvmeq->sq_lock); 1207 nvme_sq_copy_cmd(nvmeq, &c); 1208 nvme_write_sq_db(nvmeq, true); 1209 spin_unlock(&nvmeq->sq_lock); 1210 } 1211 1212 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1213 { 1214 struct nvme_command c = { }; 1215 1216 c.delete_queue.opcode = opcode; 1217 c.delete_queue.qid = cpu_to_le16(id); 1218 1219 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1220 } 1221 1222 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1223 struct nvme_queue *nvmeq, s16 vector) 1224 { 1225 struct nvme_command c = { }; 1226 int flags = NVME_QUEUE_PHYS_CONTIG; 1227 1228 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1229 flags |= NVME_CQ_IRQ_ENABLED; 1230 1231 /* 1232 * Note: we (ab)use the fact that the prp fields survive if no data 1233 * is attached to the request. 1234 */ 1235 c.create_cq.opcode = nvme_admin_create_cq; 1236 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1237 c.create_cq.cqid = cpu_to_le16(qid); 1238 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1239 c.create_cq.cq_flags = cpu_to_le16(flags); 1240 c.create_cq.irq_vector = cpu_to_le16(vector); 1241 1242 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1243 } 1244 1245 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1246 struct nvme_queue *nvmeq) 1247 { 1248 struct nvme_ctrl *ctrl = &dev->ctrl; 1249 struct nvme_command c = { }; 1250 int flags = NVME_QUEUE_PHYS_CONTIG; 1251 1252 /* 1253 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1254 * set. Since URGENT priority is zeroes, it makes all queues 1255 * URGENT. 1256 */ 1257 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1258 flags |= NVME_SQ_PRIO_MEDIUM; 1259 1260 /* 1261 * Note: we (ab)use the fact that the prp fields survive if no data 1262 * is attached to the request. 1263 */ 1264 c.create_sq.opcode = nvme_admin_create_sq; 1265 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1266 c.create_sq.sqid = cpu_to_le16(qid); 1267 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1268 c.create_sq.sq_flags = cpu_to_le16(flags); 1269 c.create_sq.cqid = cpu_to_le16(qid); 1270 1271 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1272 } 1273 1274 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1275 { 1276 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1277 } 1278 1279 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1280 { 1281 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1282 } 1283 1284 static void abort_endio(struct request *req, blk_status_t error) 1285 { 1286 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1287 struct nvme_queue *nvmeq = iod->nvmeq; 1288 1289 dev_warn(nvmeq->dev->ctrl.device, 1290 "Abort status: 0x%x", nvme_req(req)->status); 1291 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1292 blk_mq_free_request(req); 1293 } 1294 1295 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1296 { 1297 /* If true, indicates loss of adapter communication, possibly by a 1298 * NVMe Subsystem reset. 1299 */ 1300 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1301 1302 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1303 switch (dev->ctrl.state) { 1304 case NVME_CTRL_RESETTING: 1305 case NVME_CTRL_CONNECTING: 1306 return false; 1307 default: 1308 break; 1309 } 1310 1311 /* We shouldn't reset unless the controller is on fatal error state 1312 * _or_ if we lost the communication with it. 1313 */ 1314 if (!(csts & NVME_CSTS_CFS) && !nssro) 1315 return false; 1316 1317 return true; 1318 } 1319 1320 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1321 { 1322 /* Read a config register to help see what died. */ 1323 u16 pci_status; 1324 int result; 1325 1326 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1327 &pci_status); 1328 if (result == PCIBIOS_SUCCESSFUL) 1329 dev_warn(dev->ctrl.device, 1330 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1331 csts, pci_status); 1332 else 1333 dev_warn(dev->ctrl.device, 1334 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1335 csts, result); 1336 1337 if (csts != ~0) 1338 return; 1339 1340 dev_warn(dev->ctrl.device, 1341 "Does your device have a faulty power saving mode enabled?\n"); 1342 dev_warn(dev->ctrl.device, 1343 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1344 } 1345 1346 static enum blk_eh_timer_return nvme_timeout(struct request *req) 1347 { 1348 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1349 struct nvme_queue *nvmeq = iod->nvmeq; 1350 struct nvme_dev *dev = nvmeq->dev; 1351 struct request *abort_req; 1352 struct nvme_command cmd = { }; 1353 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1354 1355 /* If PCI error recovery process is happening, we cannot reset or 1356 * the recovery mechanism will surely fail. 1357 */ 1358 mb(); 1359 if (pci_channel_offline(to_pci_dev(dev->dev))) 1360 return BLK_EH_RESET_TIMER; 1361 1362 /* 1363 * Reset immediately if the controller is failed 1364 */ 1365 if (nvme_should_reset(dev, csts)) { 1366 nvme_warn_reset(dev, csts); 1367 nvme_dev_disable(dev, false); 1368 nvme_reset_ctrl(&dev->ctrl); 1369 return BLK_EH_DONE; 1370 } 1371 1372 /* 1373 * Did we miss an interrupt? 1374 */ 1375 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1376 nvme_poll(req->mq_hctx, NULL); 1377 else 1378 nvme_poll_irqdisable(nvmeq); 1379 1380 if (blk_mq_request_completed(req)) { 1381 dev_warn(dev->ctrl.device, 1382 "I/O %d QID %d timeout, completion polled\n", 1383 req->tag, nvmeq->qid); 1384 return BLK_EH_DONE; 1385 } 1386 1387 /* 1388 * Shutdown immediately if controller times out while starting. The 1389 * reset work will see the pci device disabled when it gets the forced 1390 * cancellation error. All outstanding requests are completed on 1391 * shutdown, so we return BLK_EH_DONE. 1392 */ 1393 switch (dev->ctrl.state) { 1394 case NVME_CTRL_CONNECTING: 1395 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1396 fallthrough; 1397 case NVME_CTRL_DELETING: 1398 dev_warn_ratelimited(dev->ctrl.device, 1399 "I/O %d QID %d timeout, disable controller\n", 1400 req->tag, nvmeq->qid); 1401 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1402 nvme_dev_disable(dev, true); 1403 return BLK_EH_DONE; 1404 case NVME_CTRL_RESETTING: 1405 return BLK_EH_RESET_TIMER; 1406 default: 1407 break; 1408 } 1409 1410 /* 1411 * Shutdown the controller immediately and schedule a reset if the 1412 * command was already aborted once before and still hasn't been 1413 * returned to the driver, or if this is the admin queue. 1414 */ 1415 if (!nvmeq->qid || iod->aborted) { 1416 dev_warn(dev->ctrl.device, 1417 "I/O %d QID %d timeout, reset controller\n", 1418 req->tag, nvmeq->qid); 1419 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1420 nvme_dev_disable(dev, false); 1421 nvme_reset_ctrl(&dev->ctrl); 1422 1423 return BLK_EH_DONE; 1424 } 1425 1426 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1427 atomic_inc(&dev->ctrl.abort_limit); 1428 return BLK_EH_RESET_TIMER; 1429 } 1430 iod->aborted = 1; 1431 1432 cmd.abort.opcode = nvme_admin_abort_cmd; 1433 cmd.abort.cid = nvme_cid(req); 1434 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1435 1436 dev_warn(nvmeq->dev->ctrl.device, 1437 "I/O %d (%s) QID %d timeout, aborting\n", 1438 req->tag, 1439 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 1440 nvmeq->qid); 1441 1442 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 1443 BLK_MQ_REQ_NOWAIT); 1444 if (IS_ERR(abort_req)) { 1445 atomic_inc(&dev->ctrl.abort_limit); 1446 return BLK_EH_RESET_TIMER; 1447 } 1448 nvme_init_request(abort_req, &cmd); 1449 1450 abort_req->end_io = abort_endio; 1451 abort_req->end_io_data = NULL; 1452 abort_req->rq_flags |= RQF_QUIET; 1453 blk_execute_rq_nowait(abort_req, false); 1454 1455 /* 1456 * The aborted req will be completed on receiving the abort req. 1457 * We enable the timer again. If hit twice, it'll cause a device reset, 1458 * as the device then is in a faulty state. 1459 */ 1460 return BLK_EH_RESET_TIMER; 1461 } 1462 1463 static void nvme_free_queue(struct nvme_queue *nvmeq) 1464 { 1465 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1466 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1467 if (!nvmeq->sq_cmds) 1468 return; 1469 1470 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1471 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1472 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1473 } else { 1474 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1475 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1476 } 1477 } 1478 1479 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1480 { 1481 int i; 1482 1483 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1484 dev->ctrl.queue_count--; 1485 nvme_free_queue(&dev->queues[i]); 1486 } 1487 } 1488 1489 /** 1490 * nvme_suspend_queue - put queue into suspended state 1491 * @nvmeq: queue to suspend 1492 */ 1493 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1494 { 1495 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1496 return 1; 1497 1498 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1499 mb(); 1500 1501 nvmeq->dev->online_queues--; 1502 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1503 nvme_stop_admin_queue(&nvmeq->dev->ctrl); 1504 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1505 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1506 return 0; 1507 } 1508 1509 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1510 { 1511 int i; 1512 1513 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1514 nvme_suspend_queue(&dev->queues[i]); 1515 } 1516 1517 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1518 { 1519 struct nvme_queue *nvmeq = &dev->queues[0]; 1520 1521 if (shutdown) 1522 nvme_shutdown_ctrl(&dev->ctrl); 1523 else 1524 nvme_disable_ctrl(&dev->ctrl); 1525 1526 nvme_poll_irqdisable(nvmeq); 1527 } 1528 1529 /* 1530 * Called only on a device that has been disabled and after all other threads 1531 * that can check this device's completion queues have synced, except 1532 * nvme_poll(). This is the last chance for the driver to see a natural 1533 * completion before nvme_cancel_request() terminates all incomplete requests. 1534 */ 1535 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1536 { 1537 int i; 1538 1539 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1540 spin_lock(&dev->queues[i].cq_poll_lock); 1541 nvme_poll_cq(&dev->queues[i], NULL); 1542 spin_unlock(&dev->queues[i].cq_poll_lock); 1543 } 1544 } 1545 1546 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1547 int entry_size) 1548 { 1549 int q_depth = dev->q_depth; 1550 unsigned q_size_aligned = roundup(q_depth * entry_size, 1551 NVME_CTRL_PAGE_SIZE); 1552 1553 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1554 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1555 1556 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1557 q_depth = div_u64(mem_per_q, entry_size); 1558 1559 /* 1560 * Ensure the reduced q_depth is above some threshold where it 1561 * would be better to map queues in system memory with the 1562 * original depth 1563 */ 1564 if (q_depth < 64) 1565 return -ENOMEM; 1566 } 1567 1568 return q_depth; 1569 } 1570 1571 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1572 int qid) 1573 { 1574 struct pci_dev *pdev = to_pci_dev(dev->dev); 1575 1576 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1577 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1578 if (nvmeq->sq_cmds) { 1579 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1580 nvmeq->sq_cmds); 1581 if (nvmeq->sq_dma_addr) { 1582 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1583 return 0; 1584 } 1585 1586 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1587 } 1588 } 1589 1590 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1591 &nvmeq->sq_dma_addr, GFP_KERNEL); 1592 if (!nvmeq->sq_cmds) 1593 return -ENOMEM; 1594 return 0; 1595 } 1596 1597 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1598 { 1599 struct nvme_queue *nvmeq = &dev->queues[qid]; 1600 1601 if (dev->ctrl.queue_count > qid) 1602 return 0; 1603 1604 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1605 nvmeq->q_depth = depth; 1606 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1607 &nvmeq->cq_dma_addr, GFP_KERNEL); 1608 if (!nvmeq->cqes) 1609 goto free_nvmeq; 1610 1611 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1612 goto free_cqdma; 1613 1614 nvmeq->dev = dev; 1615 spin_lock_init(&nvmeq->sq_lock); 1616 spin_lock_init(&nvmeq->cq_poll_lock); 1617 nvmeq->cq_head = 0; 1618 nvmeq->cq_phase = 1; 1619 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1620 nvmeq->qid = qid; 1621 dev->ctrl.queue_count++; 1622 1623 return 0; 1624 1625 free_cqdma: 1626 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1627 nvmeq->cq_dma_addr); 1628 free_nvmeq: 1629 return -ENOMEM; 1630 } 1631 1632 static int queue_request_irq(struct nvme_queue *nvmeq) 1633 { 1634 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1635 int nr = nvmeq->dev->ctrl.instance; 1636 1637 if (use_threaded_interrupts) { 1638 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1639 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1640 } else { 1641 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1642 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1643 } 1644 } 1645 1646 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1647 { 1648 struct nvme_dev *dev = nvmeq->dev; 1649 1650 nvmeq->sq_tail = 0; 1651 nvmeq->last_sq_tail = 0; 1652 nvmeq->cq_head = 0; 1653 nvmeq->cq_phase = 1; 1654 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1655 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1656 nvme_dbbuf_init(dev, nvmeq, qid); 1657 dev->online_queues++; 1658 wmb(); /* ensure the first interrupt sees the initialization */ 1659 } 1660 1661 /* 1662 * Try getting shutdown_lock while setting up IO queues. 1663 */ 1664 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1665 { 1666 /* 1667 * Give up if the lock is being held by nvme_dev_disable. 1668 */ 1669 if (!mutex_trylock(&dev->shutdown_lock)) 1670 return -ENODEV; 1671 1672 /* 1673 * Controller is in wrong state, fail early. 1674 */ 1675 if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1676 mutex_unlock(&dev->shutdown_lock); 1677 return -ENODEV; 1678 } 1679 1680 return 0; 1681 } 1682 1683 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1684 { 1685 struct nvme_dev *dev = nvmeq->dev; 1686 int result; 1687 u16 vector = 0; 1688 1689 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1690 1691 /* 1692 * A queue's vector matches the queue identifier unless the controller 1693 * has only one vector available. 1694 */ 1695 if (!polled) 1696 vector = dev->num_vecs == 1 ? 0 : qid; 1697 else 1698 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1699 1700 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1701 if (result) 1702 return result; 1703 1704 result = adapter_alloc_sq(dev, qid, nvmeq); 1705 if (result < 0) 1706 return result; 1707 if (result) 1708 goto release_cq; 1709 1710 nvmeq->cq_vector = vector; 1711 1712 result = nvme_setup_io_queues_trylock(dev); 1713 if (result) 1714 return result; 1715 nvme_init_queue(nvmeq, qid); 1716 if (!polled) { 1717 result = queue_request_irq(nvmeq); 1718 if (result < 0) 1719 goto release_sq; 1720 } 1721 1722 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1723 mutex_unlock(&dev->shutdown_lock); 1724 return result; 1725 1726 release_sq: 1727 dev->online_queues--; 1728 mutex_unlock(&dev->shutdown_lock); 1729 adapter_delete_sq(dev, qid); 1730 release_cq: 1731 adapter_delete_cq(dev, qid); 1732 return result; 1733 } 1734 1735 static const struct blk_mq_ops nvme_mq_admin_ops = { 1736 .queue_rq = nvme_queue_rq, 1737 .complete = nvme_pci_complete_rq, 1738 .init_hctx = nvme_admin_init_hctx, 1739 .init_request = nvme_pci_init_request, 1740 .timeout = nvme_timeout, 1741 }; 1742 1743 static const struct blk_mq_ops nvme_mq_ops = { 1744 .queue_rq = nvme_queue_rq, 1745 .queue_rqs = nvme_queue_rqs, 1746 .complete = nvme_pci_complete_rq, 1747 .commit_rqs = nvme_commit_rqs, 1748 .init_hctx = nvme_init_hctx, 1749 .init_request = nvme_pci_init_request, 1750 .map_queues = nvme_pci_map_queues, 1751 .timeout = nvme_timeout, 1752 .poll = nvme_poll, 1753 }; 1754 1755 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1756 { 1757 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1758 /* 1759 * If the controller was reset during removal, it's possible 1760 * user requests may be waiting on a stopped queue. Start the 1761 * queue to flush these to completion. 1762 */ 1763 nvme_start_admin_queue(&dev->ctrl); 1764 blk_mq_destroy_queue(dev->ctrl.admin_q); 1765 blk_mq_free_tag_set(&dev->admin_tagset); 1766 } 1767 } 1768 1769 static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 1770 { 1771 struct blk_mq_tag_set *set = &dev->admin_tagset; 1772 1773 set->ops = &nvme_mq_admin_ops; 1774 set->nr_hw_queues = 1; 1775 1776 set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1777 set->timeout = NVME_ADMIN_TIMEOUT; 1778 set->numa_node = dev->ctrl.numa_node; 1779 set->cmd_size = sizeof(struct nvme_iod); 1780 set->flags = BLK_MQ_F_NO_SCHED; 1781 set->driver_data = dev; 1782 1783 if (blk_mq_alloc_tag_set(set)) 1784 return -ENOMEM; 1785 dev->ctrl.admin_tagset = set; 1786 1787 dev->ctrl.admin_q = blk_mq_init_queue(set); 1788 if (IS_ERR(dev->ctrl.admin_q)) { 1789 blk_mq_free_tag_set(set); 1790 dev->ctrl.admin_q = NULL; 1791 return -ENOMEM; 1792 } 1793 if (!blk_get_queue(dev->ctrl.admin_q)) { 1794 nvme_dev_remove_admin(dev); 1795 dev->ctrl.admin_q = NULL; 1796 return -ENODEV; 1797 } 1798 return 0; 1799 } 1800 1801 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1802 { 1803 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1804 } 1805 1806 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1807 { 1808 struct pci_dev *pdev = to_pci_dev(dev->dev); 1809 1810 if (size <= dev->bar_mapped_size) 1811 return 0; 1812 if (size > pci_resource_len(pdev, 0)) 1813 return -ENOMEM; 1814 if (dev->bar) 1815 iounmap(dev->bar); 1816 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1817 if (!dev->bar) { 1818 dev->bar_mapped_size = 0; 1819 return -ENOMEM; 1820 } 1821 dev->bar_mapped_size = size; 1822 dev->dbs = dev->bar + NVME_REG_DBS; 1823 1824 return 0; 1825 } 1826 1827 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1828 { 1829 int result; 1830 u32 aqa; 1831 struct nvme_queue *nvmeq; 1832 1833 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1834 if (result < 0) 1835 return result; 1836 1837 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1838 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1839 1840 if (dev->subsystem && 1841 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1842 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1843 1844 result = nvme_disable_ctrl(&dev->ctrl); 1845 if (result < 0) 1846 return result; 1847 1848 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1849 if (result) 1850 return result; 1851 1852 dev->ctrl.numa_node = dev_to_node(dev->dev); 1853 1854 nvmeq = &dev->queues[0]; 1855 aqa = nvmeq->q_depth - 1; 1856 aqa |= aqa << 16; 1857 1858 writel(aqa, dev->bar + NVME_REG_AQA); 1859 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1860 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1861 1862 result = nvme_enable_ctrl(&dev->ctrl); 1863 if (result) 1864 return result; 1865 1866 nvmeq->cq_vector = 0; 1867 nvme_init_queue(nvmeq, 0); 1868 result = queue_request_irq(nvmeq); 1869 if (result) { 1870 dev->online_queues--; 1871 return result; 1872 } 1873 1874 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1875 return result; 1876 } 1877 1878 static int nvme_create_io_queues(struct nvme_dev *dev) 1879 { 1880 unsigned i, max, rw_queues; 1881 int ret = 0; 1882 1883 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1884 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1885 ret = -ENOMEM; 1886 break; 1887 } 1888 } 1889 1890 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1891 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1892 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1893 dev->io_queues[HCTX_TYPE_READ]; 1894 } else { 1895 rw_queues = max; 1896 } 1897 1898 for (i = dev->online_queues; i <= max; i++) { 1899 bool polled = i > rw_queues; 1900 1901 ret = nvme_create_queue(&dev->queues[i], i, polled); 1902 if (ret) 1903 break; 1904 } 1905 1906 /* 1907 * Ignore failing Create SQ/CQ commands, we can continue with less 1908 * than the desired amount of queues, and even a controller without 1909 * I/O queues can still be used to issue admin commands. This might 1910 * be useful to upgrade a buggy firmware for example. 1911 */ 1912 return ret >= 0 ? 0 : ret; 1913 } 1914 1915 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1916 { 1917 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1918 1919 return 1ULL << (12 + 4 * szu); 1920 } 1921 1922 static u32 nvme_cmb_size(struct nvme_dev *dev) 1923 { 1924 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1925 } 1926 1927 static void nvme_map_cmb(struct nvme_dev *dev) 1928 { 1929 u64 size, offset; 1930 resource_size_t bar_size; 1931 struct pci_dev *pdev = to_pci_dev(dev->dev); 1932 int bar; 1933 1934 if (dev->cmb_size) 1935 return; 1936 1937 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1938 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1939 1940 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1941 if (!dev->cmbsz) 1942 return; 1943 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1944 1945 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1946 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1947 bar = NVME_CMB_BIR(dev->cmbloc); 1948 bar_size = pci_resource_len(pdev, bar); 1949 1950 if (offset > bar_size) 1951 return; 1952 1953 /* 1954 * Tell the controller about the host side address mapping the CMB, 1955 * and enable CMB decoding for the NVMe 1.4+ scheme: 1956 */ 1957 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1958 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1959 (pci_bus_address(pdev, bar) + offset), 1960 dev->bar + NVME_REG_CMBMSC); 1961 } 1962 1963 /* 1964 * Controllers may support a CMB size larger than their BAR, 1965 * for example, due to being behind a bridge. Reduce the CMB to 1966 * the reported size of the BAR 1967 */ 1968 if (size > bar_size - offset) 1969 size = bar_size - offset; 1970 1971 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1972 dev_warn(dev->ctrl.device, 1973 "failed to register the CMB\n"); 1974 return; 1975 } 1976 1977 dev->cmb_size = size; 1978 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1979 1980 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1981 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1982 pci_p2pmem_publish(pdev, true); 1983 } 1984 1985 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1986 { 1987 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1988 u64 dma_addr = dev->host_mem_descs_dma; 1989 struct nvme_command c = { }; 1990 int ret; 1991 1992 c.features.opcode = nvme_admin_set_features; 1993 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1994 c.features.dword11 = cpu_to_le32(bits); 1995 c.features.dword12 = cpu_to_le32(host_mem_size); 1996 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1997 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1998 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1999 2000 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 2001 if (ret) { 2002 dev_warn(dev->ctrl.device, 2003 "failed to set host mem (err %d, flags %#x).\n", 2004 ret, bits); 2005 } else 2006 dev->hmb = bits & NVME_HOST_MEM_ENABLE; 2007 2008 return ret; 2009 } 2010 2011 static void nvme_free_host_mem(struct nvme_dev *dev) 2012 { 2013 int i; 2014 2015 for (i = 0; i < dev->nr_host_mem_descs; i++) { 2016 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 2017 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 2018 2019 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 2020 le64_to_cpu(desc->addr), 2021 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2022 } 2023 2024 kfree(dev->host_mem_desc_bufs); 2025 dev->host_mem_desc_bufs = NULL; 2026 dma_free_coherent(dev->dev, 2027 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 2028 dev->host_mem_descs, dev->host_mem_descs_dma); 2029 dev->host_mem_descs = NULL; 2030 dev->nr_host_mem_descs = 0; 2031 } 2032 2033 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 2034 u32 chunk_size) 2035 { 2036 struct nvme_host_mem_buf_desc *descs; 2037 u32 max_entries, len; 2038 dma_addr_t descs_dma; 2039 int i = 0; 2040 void **bufs; 2041 u64 size, tmp; 2042 2043 tmp = (preferred + chunk_size - 1); 2044 do_div(tmp, chunk_size); 2045 max_entries = tmp; 2046 2047 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2048 max_entries = dev->ctrl.hmmaxd; 2049 2050 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 2051 &descs_dma, GFP_KERNEL); 2052 if (!descs) 2053 goto out; 2054 2055 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 2056 if (!bufs) 2057 goto out_free_descs; 2058 2059 for (size = 0; size < preferred && i < max_entries; size += len) { 2060 dma_addr_t dma_addr; 2061 2062 len = min_t(u64, chunk_size, preferred - size); 2063 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 2064 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2065 if (!bufs[i]) 2066 break; 2067 2068 descs[i].addr = cpu_to_le64(dma_addr); 2069 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 2070 i++; 2071 } 2072 2073 if (!size) 2074 goto out_free_bufs; 2075 2076 dev->nr_host_mem_descs = i; 2077 dev->host_mem_size = size; 2078 dev->host_mem_descs = descs; 2079 dev->host_mem_descs_dma = descs_dma; 2080 dev->host_mem_desc_bufs = bufs; 2081 return 0; 2082 2083 out_free_bufs: 2084 while (--i >= 0) { 2085 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 2086 2087 dma_free_attrs(dev->dev, size, bufs[i], 2088 le64_to_cpu(descs[i].addr), 2089 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2090 } 2091 2092 kfree(bufs); 2093 out_free_descs: 2094 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 2095 descs_dma); 2096 out: 2097 dev->host_mem_descs = NULL; 2098 return -ENOMEM; 2099 } 2100 2101 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 2102 { 2103 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 2104 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 2105 u64 chunk_size; 2106 2107 /* start big and work our way down */ 2108 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2109 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2110 if (!min || dev->host_mem_size >= min) 2111 return 0; 2112 nvme_free_host_mem(dev); 2113 } 2114 } 2115 2116 return -ENOMEM; 2117 } 2118 2119 static int nvme_setup_host_mem(struct nvme_dev *dev) 2120 { 2121 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2122 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2123 u64 min = (u64)dev->ctrl.hmmin * 4096; 2124 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2125 int ret; 2126 2127 preferred = min(preferred, max); 2128 if (min > max) { 2129 dev_warn(dev->ctrl.device, 2130 "min host memory (%lld MiB) above limit (%d MiB).\n", 2131 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2132 nvme_free_host_mem(dev); 2133 return 0; 2134 } 2135 2136 /* 2137 * If we already have a buffer allocated check if we can reuse it. 2138 */ 2139 if (dev->host_mem_descs) { 2140 if (dev->host_mem_size >= min) 2141 enable_bits |= NVME_HOST_MEM_RETURN; 2142 else 2143 nvme_free_host_mem(dev); 2144 } 2145 2146 if (!dev->host_mem_descs) { 2147 if (nvme_alloc_host_mem(dev, min, preferred)) { 2148 dev_warn(dev->ctrl.device, 2149 "failed to allocate host memory buffer.\n"); 2150 return 0; /* controller must work without HMB */ 2151 } 2152 2153 dev_info(dev->ctrl.device, 2154 "allocated %lld MiB host memory buffer.\n", 2155 dev->host_mem_size >> ilog2(SZ_1M)); 2156 } 2157 2158 ret = nvme_set_host_mem(dev, enable_bits); 2159 if (ret) 2160 nvme_free_host_mem(dev); 2161 return ret; 2162 } 2163 2164 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 2165 char *buf) 2166 { 2167 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2168 2169 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 2170 ndev->cmbloc, ndev->cmbsz); 2171 } 2172 static DEVICE_ATTR_RO(cmb); 2173 2174 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 2175 char *buf) 2176 { 2177 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2178 2179 return sysfs_emit(buf, "%u\n", ndev->cmbloc); 2180 } 2181 static DEVICE_ATTR_RO(cmbloc); 2182 2183 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 2184 char *buf) 2185 { 2186 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2187 2188 return sysfs_emit(buf, "%u\n", ndev->cmbsz); 2189 } 2190 static DEVICE_ATTR_RO(cmbsz); 2191 2192 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2193 char *buf) 2194 { 2195 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2196 2197 return sysfs_emit(buf, "%d\n", ndev->hmb); 2198 } 2199 2200 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2201 const char *buf, size_t count) 2202 { 2203 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2204 bool new; 2205 int ret; 2206 2207 if (strtobool(buf, &new) < 0) 2208 return -EINVAL; 2209 2210 if (new == ndev->hmb) 2211 return count; 2212 2213 if (new) { 2214 ret = nvme_setup_host_mem(ndev); 2215 } else { 2216 ret = nvme_set_host_mem(ndev, 0); 2217 if (!ret) 2218 nvme_free_host_mem(ndev); 2219 } 2220 2221 if (ret < 0) 2222 return ret; 2223 2224 return count; 2225 } 2226 static DEVICE_ATTR_RW(hmb); 2227 2228 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 2229 struct attribute *a, int n) 2230 { 2231 struct nvme_ctrl *ctrl = 2232 dev_get_drvdata(container_of(kobj, struct device, kobj)); 2233 struct nvme_dev *dev = to_nvme_dev(ctrl); 2234 2235 if (a == &dev_attr_cmb.attr || 2236 a == &dev_attr_cmbloc.attr || 2237 a == &dev_attr_cmbsz.attr) { 2238 if (!dev->cmbsz) 2239 return 0; 2240 } 2241 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2242 return 0; 2243 2244 return a->mode; 2245 } 2246 2247 static struct attribute *nvme_pci_attrs[] = { 2248 &dev_attr_cmb.attr, 2249 &dev_attr_cmbloc.attr, 2250 &dev_attr_cmbsz.attr, 2251 &dev_attr_hmb.attr, 2252 NULL, 2253 }; 2254 2255 static const struct attribute_group nvme_pci_attr_group = { 2256 .attrs = nvme_pci_attrs, 2257 .is_visible = nvme_pci_attrs_are_visible, 2258 }; 2259 2260 /* 2261 * nirqs is the number of interrupts available for write and read 2262 * queues. The core already reserved an interrupt for the admin queue. 2263 */ 2264 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2265 { 2266 struct nvme_dev *dev = affd->priv; 2267 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2268 2269 /* 2270 * If there is no interrupt available for queues, ensure that 2271 * the default queue is set to 1. The affinity set size is 2272 * also set to one, but the irq core ignores it for this case. 2273 * 2274 * If only one interrupt is available or 'write_queue' == 0, combine 2275 * write and read queues. 2276 * 2277 * If 'write_queues' > 0, ensure it leaves room for at least one read 2278 * queue. 2279 */ 2280 if (!nrirqs) { 2281 nrirqs = 1; 2282 nr_read_queues = 0; 2283 } else if (nrirqs == 1 || !nr_write_queues) { 2284 nr_read_queues = 0; 2285 } else if (nr_write_queues >= nrirqs) { 2286 nr_read_queues = 1; 2287 } else { 2288 nr_read_queues = nrirqs - nr_write_queues; 2289 } 2290 2291 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2292 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2293 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2294 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2295 affd->nr_sets = nr_read_queues ? 2 : 1; 2296 } 2297 2298 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2299 { 2300 struct pci_dev *pdev = to_pci_dev(dev->dev); 2301 struct irq_affinity affd = { 2302 .pre_vectors = 1, 2303 .calc_sets = nvme_calc_irq_sets, 2304 .priv = dev, 2305 }; 2306 unsigned int irq_queues, poll_queues; 2307 2308 /* 2309 * Poll queues don't need interrupts, but we need at least one I/O queue 2310 * left over for non-polled I/O. 2311 */ 2312 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2313 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2314 2315 /* 2316 * Initialize for the single interrupt case, will be updated in 2317 * nvme_calc_irq_sets(). 2318 */ 2319 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2320 dev->io_queues[HCTX_TYPE_READ] = 0; 2321 2322 /* 2323 * We need interrupts for the admin queue and each non-polled I/O queue, 2324 * but some Apple controllers require all queues to use the first 2325 * vector. 2326 */ 2327 irq_queues = 1; 2328 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2329 irq_queues += (nr_io_queues - poll_queues); 2330 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2331 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2332 } 2333 2334 static void nvme_disable_io_queues(struct nvme_dev *dev) 2335 { 2336 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2337 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2338 } 2339 2340 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2341 { 2342 /* 2343 * If tags are shared with admin queue (Apple bug), then 2344 * make sure we only use one IO queue. 2345 */ 2346 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2347 return 1; 2348 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2349 } 2350 2351 static int nvme_setup_io_queues(struct nvme_dev *dev) 2352 { 2353 struct nvme_queue *adminq = &dev->queues[0]; 2354 struct pci_dev *pdev = to_pci_dev(dev->dev); 2355 unsigned int nr_io_queues; 2356 unsigned long size; 2357 int result; 2358 2359 /* 2360 * Sample the module parameters once at reset time so that we have 2361 * stable values to work with. 2362 */ 2363 dev->nr_write_queues = write_queues; 2364 dev->nr_poll_queues = poll_queues; 2365 2366 nr_io_queues = dev->nr_allocated_queues - 1; 2367 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2368 if (result < 0) 2369 return result; 2370 2371 if (nr_io_queues == 0) 2372 return 0; 2373 2374 /* 2375 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2376 * from set to unset. If there is a window to it is truely freed, 2377 * pci_free_irq_vectors() jumping into this window will crash. 2378 * And take lock to avoid racing with pci_free_irq_vectors() in 2379 * nvme_dev_disable() path. 2380 */ 2381 result = nvme_setup_io_queues_trylock(dev); 2382 if (result) 2383 return result; 2384 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2385 pci_free_irq(pdev, 0, adminq); 2386 2387 if (dev->cmb_use_sqes) { 2388 result = nvme_cmb_qdepth(dev, nr_io_queues, 2389 sizeof(struct nvme_command)); 2390 if (result > 0) 2391 dev->q_depth = result; 2392 else 2393 dev->cmb_use_sqes = false; 2394 } 2395 2396 do { 2397 size = db_bar_size(dev, nr_io_queues); 2398 result = nvme_remap_bar(dev, size); 2399 if (!result) 2400 break; 2401 if (!--nr_io_queues) { 2402 result = -ENOMEM; 2403 goto out_unlock; 2404 } 2405 } while (1); 2406 adminq->q_db = dev->dbs; 2407 2408 retry: 2409 /* Deregister the admin queue's interrupt */ 2410 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2411 pci_free_irq(pdev, 0, adminq); 2412 2413 /* 2414 * If we enable msix early due to not intx, disable it again before 2415 * setting up the full range we need. 2416 */ 2417 pci_free_irq_vectors(pdev); 2418 2419 result = nvme_setup_irqs(dev, nr_io_queues); 2420 if (result <= 0) { 2421 result = -EIO; 2422 goto out_unlock; 2423 } 2424 2425 dev->num_vecs = result; 2426 result = max(result - 1, 1); 2427 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2428 2429 /* 2430 * Should investigate if there's a performance win from allocating 2431 * more queues than interrupt vectors; it might allow the submission 2432 * path to scale better, even if the receive path is limited by the 2433 * number of interrupts. 2434 */ 2435 result = queue_request_irq(adminq); 2436 if (result) 2437 goto out_unlock; 2438 set_bit(NVMEQ_ENABLED, &adminq->flags); 2439 mutex_unlock(&dev->shutdown_lock); 2440 2441 result = nvme_create_io_queues(dev); 2442 if (result || dev->online_queues < 2) 2443 return result; 2444 2445 if (dev->online_queues - 1 < dev->max_qid) { 2446 nr_io_queues = dev->online_queues - 1; 2447 nvme_disable_io_queues(dev); 2448 result = nvme_setup_io_queues_trylock(dev); 2449 if (result) 2450 return result; 2451 nvme_suspend_io_queues(dev); 2452 goto retry; 2453 } 2454 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2455 dev->io_queues[HCTX_TYPE_DEFAULT], 2456 dev->io_queues[HCTX_TYPE_READ], 2457 dev->io_queues[HCTX_TYPE_POLL]); 2458 return 0; 2459 out_unlock: 2460 mutex_unlock(&dev->shutdown_lock); 2461 return result; 2462 } 2463 2464 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2465 { 2466 struct nvme_queue *nvmeq = req->end_io_data; 2467 2468 blk_mq_free_request(req); 2469 complete(&nvmeq->delete_done); 2470 } 2471 2472 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2473 { 2474 struct nvme_queue *nvmeq = req->end_io_data; 2475 2476 if (error) 2477 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2478 2479 nvme_del_queue_end(req, error); 2480 } 2481 2482 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2483 { 2484 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2485 struct request *req; 2486 struct nvme_command cmd = { }; 2487 2488 cmd.delete_queue.opcode = opcode; 2489 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2490 2491 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2492 if (IS_ERR(req)) 2493 return PTR_ERR(req); 2494 nvme_init_request(req, &cmd); 2495 2496 if (opcode == nvme_admin_delete_cq) 2497 req->end_io = nvme_del_cq_end; 2498 else 2499 req->end_io = nvme_del_queue_end; 2500 req->end_io_data = nvmeq; 2501 2502 init_completion(&nvmeq->delete_done); 2503 req->rq_flags |= RQF_QUIET; 2504 blk_execute_rq_nowait(req, false); 2505 return 0; 2506 } 2507 2508 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2509 { 2510 int nr_queues = dev->online_queues - 1, sent = 0; 2511 unsigned long timeout; 2512 2513 retry: 2514 timeout = NVME_ADMIN_TIMEOUT; 2515 while (nr_queues > 0) { 2516 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2517 break; 2518 nr_queues--; 2519 sent++; 2520 } 2521 while (sent) { 2522 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2523 2524 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2525 timeout); 2526 if (timeout == 0) 2527 return false; 2528 2529 sent--; 2530 if (nr_queues) 2531 goto retry; 2532 } 2533 return true; 2534 } 2535 2536 static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 2537 { 2538 struct blk_mq_tag_set * set = &dev->tagset; 2539 int ret; 2540 2541 set->ops = &nvme_mq_ops; 2542 set->nr_hw_queues = dev->online_queues - 1; 2543 set->nr_maps = 2; /* default + read */ 2544 if (dev->io_queues[HCTX_TYPE_POLL]) 2545 set->nr_maps++; 2546 set->timeout = NVME_IO_TIMEOUT; 2547 set->numa_node = dev->ctrl.numa_node; 2548 set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2549 set->cmd_size = sizeof(struct nvme_iod); 2550 set->flags = BLK_MQ_F_SHOULD_MERGE; 2551 set->driver_data = dev; 2552 2553 /* 2554 * Some Apple controllers requires tags to be unique 2555 * across admin and IO queue, so reserve the first 32 2556 * tags of the IO queue. 2557 */ 2558 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2559 set->reserved_tags = NVME_AQ_DEPTH; 2560 2561 ret = blk_mq_alloc_tag_set(set); 2562 if (ret) { 2563 dev_warn(dev->ctrl.device, 2564 "IO queues tagset allocation failed %d\n", ret); 2565 return; 2566 } 2567 dev->ctrl.tagset = set; 2568 } 2569 2570 static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 2571 { 2572 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2573 /* free previously allocated queues that are no longer usable */ 2574 nvme_free_queues(dev, dev->online_queues); 2575 } 2576 2577 static int nvme_pci_enable(struct nvme_dev *dev) 2578 { 2579 int result = -ENOMEM; 2580 struct pci_dev *pdev = to_pci_dev(dev->dev); 2581 int dma_address_bits = 64; 2582 2583 if (pci_enable_device_mem(pdev)) 2584 return result; 2585 2586 pci_set_master(pdev); 2587 2588 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 2589 dma_address_bits = 48; 2590 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 2591 goto disable; 2592 2593 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2594 result = -ENODEV; 2595 goto disable; 2596 } 2597 2598 /* 2599 * Some devices and/or platforms don't advertise or work with INTx 2600 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2601 * adjust this later. 2602 */ 2603 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2604 if (result < 0) 2605 return result; 2606 2607 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2608 2609 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2610 io_queue_depth); 2611 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2612 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2613 dev->dbs = dev->bar + 4096; 2614 2615 /* 2616 * Some Apple controllers require a non-standard SQE size. 2617 * Interestingly they also seem to ignore the CC:IOSQES register 2618 * so we don't bother updating it here. 2619 */ 2620 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2621 dev->io_sqes = 7; 2622 else 2623 dev->io_sqes = NVME_NVM_IOSQES; 2624 2625 /* 2626 * Temporary fix for the Apple controller found in the MacBook8,1 and 2627 * some MacBook7,1 to avoid controller resets and data loss. 2628 */ 2629 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2630 dev->q_depth = 2; 2631 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2632 "set queue depth=%u to work around controller resets\n", 2633 dev->q_depth); 2634 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2635 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2636 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2637 dev->q_depth = 64; 2638 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2639 "set queue depth=%u\n", dev->q_depth); 2640 } 2641 2642 /* 2643 * Controllers with the shared tags quirk need the IO queue to be 2644 * big enough so that we get 32 tags for the admin queue 2645 */ 2646 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2647 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2648 dev->q_depth = NVME_AQ_DEPTH + 2; 2649 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2650 dev->q_depth); 2651 } 2652 2653 2654 nvme_map_cmb(dev); 2655 2656 pci_enable_pcie_error_reporting(pdev); 2657 pci_save_state(pdev); 2658 return 0; 2659 2660 disable: 2661 pci_disable_device(pdev); 2662 return result; 2663 } 2664 2665 static void nvme_dev_unmap(struct nvme_dev *dev) 2666 { 2667 if (dev->bar) 2668 iounmap(dev->bar); 2669 pci_release_mem_regions(to_pci_dev(dev->dev)); 2670 } 2671 2672 static void nvme_pci_disable(struct nvme_dev *dev) 2673 { 2674 struct pci_dev *pdev = to_pci_dev(dev->dev); 2675 2676 pci_free_irq_vectors(pdev); 2677 2678 if (pci_is_enabled(pdev)) { 2679 pci_disable_pcie_error_reporting(pdev); 2680 pci_disable_device(pdev); 2681 } 2682 } 2683 2684 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2685 { 2686 bool dead = true, freeze = false; 2687 struct pci_dev *pdev = to_pci_dev(dev->dev); 2688 2689 mutex_lock(&dev->shutdown_lock); 2690 if (pci_is_enabled(pdev)) { 2691 u32 csts; 2692 2693 if (pci_device_is_present(pdev)) 2694 csts = readl(dev->bar + NVME_REG_CSTS); 2695 else 2696 csts = ~0; 2697 2698 if (dev->ctrl.state == NVME_CTRL_LIVE || 2699 dev->ctrl.state == NVME_CTRL_RESETTING) { 2700 freeze = true; 2701 nvme_start_freeze(&dev->ctrl); 2702 } 2703 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2704 pdev->error_state != pci_channel_io_normal); 2705 } 2706 2707 /* 2708 * Give the controller a chance to complete all entered requests if 2709 * doing a safe shutdown. 2710 */ 2711 if (!dead && shutdown && freeze) 2712 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2713 2714 nvme_stop_queues(&dev->ctrl); 2715 2716 if (!dead && dev->ctrl.queue_count > 0) { 2717 nvme_disable_io_queues(dev); 2718 nvme_disable_admin_queue(dev, shutdown); 2719 } 2720 nvme_suspend_io_queues(dev); 2721 nvme_suspend_queue(&dev->queues[0]); 2722 nvme_pci_disable(dev); 2723 nvme_reap_pending_cqes(dev); 2724 2725 nvme_cancel_tagset(&dev->ctrl); 2726 nvme_cancel_admin_tagset(&dev->ctrl); 2727 2728 /* 2729 * The driver will not be starting up queues again if shutting down so 2730 * must flush all entered requests to their failed completion to avoid 2731 * deadlocking blk-mq hot-cpu notifier. 2732 */ 2733 if (shutdown) { 2734 nvme_start_queues(&dev->ctrl); 2735 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2736 nvme_start_admin_queue(&dev->ctrl); 2737 } 2738 mutex_unlock(&dev->shutdown_lock); 2739 } 2740 2741 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2742 { 2743 if (!nvme_wait_reset(&dev->ctrl)) 2744 return -EBUSY; 2745 nvme_dev_disable(dev, shutdown); 2746 return 0; 2747 } 2748 2749 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2750 { 2751 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2752 NVME_CTRL_PAGE_SIZE, 2753 NVME_CTRL_PAGE_SIZE, 0); 2754 if (!dev->prp_page_pool) 2755 return -ENOMEM; 2756 2757 /* Optimisation for I/Os between 4k and 128k */ 2758 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2759 256, 256, 0); 2760 if (!dev->prp_small_pool) { 2761 dma_pool_destroy(dev->prp_page_pool); 2762 return -ENOMEM; 2763 } 2764 return 0; 2765 } 2766 2767 static void nvme_release_prp_pools(struct nvme_dev *dev) 2768 { 2769 dma_pool_destroy(dev->prp_page_pool); 2770 dma_pool_destroy(dev->prp_small_pool); 2771 } 2772 2773 static void nvme_free_tagset(struct nvme_dev *dev) 2774 { 2775 if (dev->tagset.tags) 2776 blk_mq_free_tag_set(&dev->tagset); 2777 dev->ctrl.tagset = NULL; 2778 } 2779 2780 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2781 { 2782 struct nvme_dev *dev = to_nvme_dev(ctrl); 2783 2784 nvme_dbbuf_dma_free(dev); 2785 nvme_free_tagset(dev); 2786 if (dev->ctrl.admin_q) 2787 blk_put_queue(dev->ctrl.admin_q); 2788 free_opal_dev(dev->ctrl.opal_dev); 2789 mempool_destroy(dev->iod_mempool); 2790 put_device(dev->dev); 2791 kfree(dev->queues); 2792 kfree(dev); 2793 } 2794 2795 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2796 { 2797 /* 2798 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2799 * may be holding this pci_dev's device lock. 2800 */ 2801 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2802 nvme_get_ctrl(&dev->ctrl); 2803 nvme_dev_disable(dev, false); 2804 nvme_kill_queues(&dev->ctrl); 2805 if (!queue_work(nvme_wq, &dev->remove_work)) 2806 nvme_put_ctrl(&dev->ctrl); 2807 } 2808 2809 static void nvme_reset_work(struct work_struct *work) 2810 { 2811 struct nvme_dev *dev = 2812 container_of(work, struct nvme_dev, ctrl.reset_work); 2813 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2814 int result; 2815 2816 if (dev->ctrl.state != NVME_CTRL_RESETTING) { 2817 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2818 dev->ctrl.state); 2819 result = -ENODEV; 2820 goto out; 2821 } 2822 2823 /* 2824 * If we're called to reset a live controller first shut it down before 2825 * moving on. 2826 */ 2827 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2828 nvme_dev_disable(dev, false); 2829 nvme_sync_queues(&dev->ctrl); 2830 2831 mutex_lock(&dev->shutdown_lock); 2832 result = nvme_pci_enable(dev); 2833 if (result) 2834 goto out_unlock; 2835 2836 result = nvme_pci_configure_admin_queue(dev); 2837 if (result) 2838 goto out_unlock; 2839 2840 if (!dev->ctrl.admin_q) { 2841 result = nvme_pci_alloc_admin_tag_set(dev); 2842 if (result) 2843 goto out_unlock; 2844 } else { 2845 nvme_start_admin_queue(&dev->ctrl); 2846 } 2847 2848 /* 2849 * Limit the max command size to prevent iod->sg allocations going 2850 * over a single page. 2851 */ 2852 dev->ctrl.max_hw_sectors = min_t(u32, 2853 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2854 dev->ctrl.max_segments = NVME_MAX_SEGS; 2855 2856 /* 2857 * Don't limit the IOMMU merged segment size. 2858 */ 2859 dma_set_max_seg_size(dev->dev, 0xffffffff); 2860 dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2861 2862 mutex_unlock(&dev->shutdown_lock); 2863 2864 /* 2865 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2866 * initializing procedure here. 2867 */ 2868 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2869 dev_warn(dev->ctrl.device, 2870 "failed to mark controller CONNECTING\n"); 2871 result = -EBUSY; 2872 goto out; 2873 } 2874 2875 /* 2876 * We do not support an SGL for metadata (yet), so we are limited to a 2877 * single integrity segment for the separate metadata pointer. 2878 */ 2879 dev->ctrl.max_integrity_segments = 1; 2880 2881 result = nvme_init_ctrl_finish(&dev->ctrl); 2882 if (result) 2883 goto out; 2884 2885 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2886 if (!dev->ctrl.opal_dev) 2887 dev->ctrl.opal_dev = 2888 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2889 else if (was_suspend) 2890 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2891 } else { 2892 free_opal_dev(dev->ctrl.opal_dev); 2893 dev->ctrl.opal_dev = NULL; 2894 } 2895 2896 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2897 result = nvme_dbbuf_dma_alloc(dev); 2898 if (result) 2899 dev_warn(dev->dev, 2900 "unable to allocate dma for dbbuf\n"); 2901 } 2902 2903 if (dev->ctrl.hmpre) { 2904 result = nvme_setup_host_mem(dev); 2905 if (result < 0) 2906 goto out; 2907 } 2908 2909 result = nvme_setup_io_queues(dev); 2910 if (result) 2911 goto out; 2912 2913 /* 2914 * Keep the controller around but remove all namespaces if we don't have 2915 * any working I/O queue. 2916 */ 2917 if (dev->online_queues < 2) { 2918 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2919 nvme_kill_queues(&dev->ctrl); 2920 nvme_remove_namespaces(&dev->ctrl); 2921 nvme_free_tagset(dev); 2922 } else { 2923 nvme_start_queues(&dev->ctrl); 2924 nvme_wait_freeze(&dev->ctrl); 2925 if (!dev->ctrl.tagset) 2926 nvme_pci_alloc_tag_set(dev); 2927 else 2928 nvme_pci_update_nr_queues(dev); 2929 nvme_dbbuf_set(dev); 2930 nvme_unfreeze(&dev->ctrl); 2931 } 2932 2933 /* 2934 * If only admin queue live, keep it to do further investigation or 2935 * recovery. 2936 */ 2937 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2938 dev_warn(dev->ctrl.device, 2939 "failed to mark controller live state\n"); 2940 result = -ENODEV; 2941 goto out; 2942 } 2943 2944 if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 2945 &nvme_pci_attr_group)) 2946 dev->attrs_added = true; 2947 2948 nvme_start_ctrl(&dev->ctrl); 2949 return; 2950 2951 out_unlock: 2952 mutex_unlock(&dev->shutdown_lock); 2953 out: 2954 if (result) 2955 dev_warn(dev->ctrl.device, 2956 "Removing after probe failure status: %d\n", result); 2957 nvme_remove_dead_ctrl(dev); 2958 } 2959 2960 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2961 { 2962 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2963 struct pci_dev *pdev = to_pci_dev(dev->dev); 2964 2965 if (pci_get_drvdata(pdev)) 2966 device_release_driver(&pdev->dev); 2967 nvme_put_ctrl(&dev->ctrl); 2968 } 2969 2970 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2971 { 2972 *val = readl(to_nvme_dev(ctrl)->bar + off); 2973 return 0; 2974 } 2975 2976 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2977 { 2978 writel(val, to_nvme_dev(ctrl)->bar + off); 2979 return 0; 2980 } 2981 2982 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2983 { 2984 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2985 return 0; 2986 } 2987 2988 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2989 { 2990 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2991 2992 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2993 } 2994 2995 2996 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 2997 { 2998 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2999 struct nvme_subsystem *subsys = ctrl->subsys; 3000 3001 dev_err(ctrl->device, 3002 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 3003 pdev->vendor, pdev->device, 3004 nvme_strlen(subsys->model, sizeof(subsys->model)), 3005 subsys->model, nvme_strlen(subsys->firmware_rev, 3006 sizeof(subsys->firmware_rev)), 3007 subsys->firmware_rev); 3008 } 3009 3010 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 3011 .name = "pcie", 3012 .module = THIS_MODULE, 3013 .flags = NVME_F_METADATA_SUPPORTED | 3014 NVME_F_PCI_P2PDMA, 3015 .reg_read32 = nvme_pci_reg_read32, 3016 .reg_write32 = nvme_pci_reg_write32, 3017 .reg_read64 = nvme_pci_reg_read64, 3018 .free_ctrl = nvme_pci_free_ctrl, 3019 .submit_async_event = nvme_pci_submit_async_event, 3020 .get_address = nvme_pci_get_address, 3021 .print_device_info = nvme_pci_print_device_info, 3022 }; 3023 3024 static int nvme_dev_map(struct nvme_dev *dev) 3025 { 3026 struct pci_dev *pdev = to_pci_dev(dev->dev); 3027 3028 if (pci_request_mem_regions(pdev, "nvme")) 3029 return -ENODEV; 3030 3031 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 3032 goto release; 3033 3034 return 0; 3035 release: 3036 pci_release_mem_regions(pdev); 3037 return -ENODEV; 3038 } 3039 3040 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 3041 { 3042 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3043 /* 3044 * Several Samsung devices seem to drop off the PCIe bus 3045 * randomly when APST is on and uses the deepest sleep state. 3046 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3047 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3048 * 950 PRO 256GB", but it seems to be restricted to two Dell 3049 * laptops. 3050 */ 3051 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3052 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3053 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3054 return NVME_QUIRK_NO_DEEPEST_PS; 3055 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 3056 /* 3057 * Samsung SSD 960 EVO drops off the PCIe bus after system 3058 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3059 * within few minutes after bootup on a Coffee Lake board - 3060 * ASUS PRIME Z370-A 3061 */ 3062 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3063 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3064 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 3065 return NVME_QUIRK_NO_APST; 3066 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 3067 pdev->device == 0xa808 || pdev->device == 0xa809)) || 3068 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 3069 /* 3070 * Forcing to use host managed nvme power settings for 3071 * lowest idle power with quick resume latency on 3072 * Samsung and Toshiba SSDs based on suspend behavior 3073 * on Coffee Lake board for LENOVO C640 3074 */ 3075 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 3076 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 3077 return NVME_QUIRK_SIMPLE_SUSPEND; 3078 } 3079 3080 return 0; 3081 } 3082 3083 static void nvme_async_probe(void *data, async_cookie_t cookie) 3084 { 3085 struct nvme_dev *dev = data; 3086 3087 flush_work(&dev->ctrl.reset_work); 3088 flush_work(&dev->ctrl.scan_work); 3089 nvme_put_ctrl(&dev->ctrl); 3090 } 3091 3092 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3093 { 3094 int node, result = -ENOMEM; 3095 struct nvme_dev *dev; 3096 unsigned long quirks = id->driver_data; 3097 size_t alloc_size; 3098 3099 node = dev_to_node(&pdev->dev); 3100 if (node == NUMA_NO_NODE) 3101 set_dev_node(&pdev->dev, first_memory_node); 3102 3103 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 3104 if (!dev) 3105 return -ENOMEM; 3106 3107 dev->nr_write_queues = write_queues; 3108 dev->nr_poll_queues = poll_queues; 3109 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 3110 dev->queues = kcalloc_node(dev->nr_allocated_queues, 3111 sizeof(struct nvme_queue), GFP_KERNEL, node); 3112 if (!dev->queues) 3113 goto free; 3114 3115 dev->dev = get_device(&pdev->dev); 3116 pci_set_drvdata(pdev, dev); 3117 3118 result = nvme_dev_map(dev); 3119 if (result) 3120 goto put_pci; 3121 3122 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 3123 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 3124 mutex_init(&dev->shutdown_lock); 3125 3126 result = nvme_setup_prp_pools(dev); 3127 if (result) 3128 goto unmap; 3129 3130 quirks |= check_vendor_combination_bug(pdev); 3131 3132 if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3133 /* 3134 * Some systems use a bios work around to ask for D3 on 3135 * platforms that support kernel managed suspend. 3136 */ 3137 dev_info(&pdev->dev, 3138 "platform quirk: setting simple suspend\n"); 3139 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3140 } 3141 3142 /* 3143 * Double check that our mempool alloc size will cover the biggest 3144 * command we support. 3145 */ 3146 alloc_size = nvme_pci_iod_alloc_size(); 3147 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3148 3149 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3150 mempool_kfree, 3151 (void *) alloc_size, 3152 GFP_KERNEL, node); 3153 if (!dev->iod_mempool) { 3154 result = -ENOMEM; 3155 goto release_pools; 3156 } 3157 3158 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3159 quirks); 3160 if (result) 3161 goto release_mempool; 3162 3163 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3164 3165 nvme_reset_ctrl(&dev->ctrl); 3166 async_schedule(nvme_async_probe, dev); 3167 3168 return 0; 3169 3170 release_mempool: 3171 mempool_destroy(dev->iod_mempool); 3172 release_pools: 3173 nvme_release_prp_pools(dev); 3174 unmap: 3175 nvme_dev_unmap(dev); 3176 put_pci: 3177 put_device(dev->dev); 3178 free: 3179 kfree(dev->queues); 3180 kfree(dev); 3181 return result; 3182 } 3183 3184 static void nvme_reset_prepare(struct pci_dev *pdev) 3185 { 3186 struct nvme_dev *dev = pci_get_drvdata(pdev); 3187 3188 /* 3189 * We don't need to check the return value from waiting for the reset 3190 * state as pci_dev device lock is held, making it impossible to race 3191 * with ->remove(). 3192 */ 3193 nvme_disable_prepare_reset(dev, false); 3194 nvme_sync_queues(&dev->ctrl); 3195 } 3196 3197 static void nvme_reset_done(struct pci_dev *pdev) 3198 { 3199 struct nvme_dev *dev = pci_get_drvdata(pdev); 3200 3201 if (!nvme_try_sched_reset(&dev->ctrl)) 3202 flush_work(&dev->ctrl.reset_work); 3203 } 3204 3205 static void nvme_shutdown(struct pci_dev *pdev) 3206 { 3207 struct nvme_dev *dev = pci_get_drvdata(pdev); 3208 3209 nvme_disable_prepare_reset(dev, true); 3210 } 3211 3212 static void nvme_remove_attrs(struct nvme_dev *dev) 3213 { 3214 if (dev->attrs_added) 3215 sysfs_remove_group(&dev->ctrl.device->kobj, 3216 &nvme_pci_attr_group); 3217 } 3218 3219 /* 3220 * The driver's remove may be called on a device in a partially initialized 3221 * state. This function must not have any dependencies on the device state in 3222 * order to proceed. 3223 */ 3224 static void nvme_remove(struct pci_dev *pdev) 3225 { 3226 struct nvme_dev *dev = pci_get_drvdata(pdev); 3227 3228 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3229 pci_set_drvdata(pdev, NULL); 3230 3231 if (!pci_device_is_present(pdev)) { 3232 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 3233 nvme_dev_disable(dev, true); 3234 } 3235 3236 flush_work(&dev->ctrl.reset_work); 3237 nvme_stop_ctrl(&dev->ctrl); 3238 nvme_remove_namespaces(&dev->ctrl); 3239 nvme_dev_disable(dev, true); 3240 nvme_remove_attrs(dev); 3241 nvme_free_host_mem(dev); 3242 nvme_dev_remove_admin(dev); 3243 nvme_free_queues(dev, 0); 3244 nvme_release_prp_pools(dev); 3245 nvme_dev_unmap(dev); 3246 nvme_uninit_ctrl(&dev->ctrl); 3247 } 3248 3249 #ifdef CONFIG_PM_SLEEP 3250 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3251 { 3252 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3253 } 3254 3255 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3256 { 3257 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3258 } 3259 3260 static int nvme_resume(struct device *dev) 3261 { 3262 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3263 struct nvme_ctrl *ctrl = &ndev->ctrl; 3264 3265 if (ndev->last_ps == U32_MAX || 3266 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3267 goto reset; 3268 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3269 goto reset; 3270 3271 return 0; 3272 reset: 3273 return nvme_try_sched_reset(ctrl); 3274 } 3275 3276 static int nvme_suspend(struct device *dev) 3277 { 3278 struct pci_dev *pdev = to_pci_dev(dev); 3279 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3280 struct nvme_ctrl *ctrl = &ndev->ctrl; 3281 int ret = -EBUSY; 3282 3283 ndev->last_ps = U32_MAX; 3284 3285 /* 3286 * The platform does not remove power for a kernel managed suspend so 3287 * use host managed nvme power settings for lowest idle power if 3288 * possible. This should have quicker resume latency than a full device 3289 * shutdown. But if the firmware is involved after the suspend or the 3290 * device does not support any non-default power states, shut down the 3291 * device fully. 3292 * 3293 * If ASPM is not enabled for the device, shut down the device and allow 3294 * the PCI bus layer to put it into D3 in order to take the PCIe link 3295 * down, so as to allow the platform to achieve its minimum low-power 3296 * state (which may not be possible if the link is up). 3297 */ 3298 if (pm_suspend_via_firmware() || !ctrl->npss || 3299 !pcie_aspm_enabled(pdev) || 3300 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3301 return nvme_disable_prepare_reset(ndev, true); 3302 3303 nvme_start_freeze(ctrl); 3304 nvme_wait_freeze(ctrl); 3305 nvme_sync_queues(ctrl); 3306 3307 if (ctrl->state != NVME_CTRL_LIVE) 3308 goto unfreeze; 3309 3310 /* 3311 * Host memory access may not be successful in a system suspend state, 3312 * but the specification allows the controller to access memory in a 3313 * non-operational power state. 3314 */ 3315 if (ndev->hmb) { 3316 ret = nvme_set_host_mem(ndev, 0); 3317 if (ret < 0) 3318 goto unfreeze; 3319 } 3320 3321 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3322 if (ret < 0) 3323 goto unfreeze; 3324 3325 /* 3326 * A saved state prevents pci pm from generically controlling the 3327 * device's power. If we're using protocol specific settings, we don't 3328 * want pci interfering. 3329 */ 3330 pci_save_state(pdev); 3331 3332 ret = nvme_set_power_state(ctrl, ctrl->npss); 3333 if (ret < 0) 3334 goto unfreeze; 3335 3336 if (ret) { 3337 /* discard the saved state */ 3338 pci_load_saved_state(pdev, NULL); 3339 3340 /* 3341 * Clearing npss forces a controller reset on resume. The 3342 * correct value will be rediscovered then. 3343 */ 3344 ret = nvme_disable_prepare_reset(ndev, true); 3345 ctrl->npss = 0; 3346 } 3347 unfreeze: 3348 nvme_unfreeze(ctrl); 3349 return ret; 3350 } 3351 3352 static int nvme_simple_suspend(struct device *dev) 3353 { 3354 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3355 3356 return nvme_disable_prepare_reset(ndev, true); 3357 } 3358 3359 static int nvme_simple_resume(struct device *dev) 3360 { 3361 struct pci_dev *pdev = to_pci_dev(dev); 3362 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3363 3364 return nvme_try_sched_reset(&ndev->ctrl); 3365 } 3366 3367 static const struct dev_pm_ops nvme_dev_pm_ops = { 3368 .suspend = nvme_suspend, 3369 .resume = nvme_resume, 3370 .freeze = nvme_simple_suspend, 3371 .thaw = nvme_simple_resume, 3372 .poweroff = nvme_simple_suspend, 3373 .restore = nvme_simple_resume, 3374 }; 3375 #endif /* CONFIG_PM_SLEEP */ 3376 3377 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3378 pci_channel_state_t state) 3379 { 3380 struct nvme_dev *dev = pci_get_drvdata(pdev); 3381 3382 /* 3383 * A frozen channel requires a reset. When detected, this method will 3384 * shutdown the controller to quiesce. The controller will be restarted 3385 * after the slot reset through driver's slot_reset callback. 3386 */ 3387 switch (state) { 3388 case pci_channel_io_normal: 3389 return PCI_ERS_RESULT_CAN_RECOVER; 3390 case pci_channel_io_frozen: 3391 dev_warn(dev->ctrl.device, 3392 "frozen state error detected, reset controller\n"); 3393 nvme_dev_disable(dev, false); 3394 return PCI_ERS_RESULT_NEED_RESET; 3395 case pci_channel_io_perm_failure: 3396 dev_warn(dev->ctrl.device, 3397 "failure state error detected, request disconnect\n"); 3398 return PCI_ERS_RESULT_DISCONNECT; 3399 } 3400 return PCI_ERS_RESULT_NEED_RESET; 3401 } 3402 3403 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3404 { 3405 struct nvme_dev *dev = pci_get_drvdata(pdev); 3406 3407 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3408 pci_restore_state(pdev); 3409 nvme_reset_ctrl(&dev->ctrl); 3410 return PCI_ERS_RESULT_RECOVERED; 3411 } 3412 3413 static void nvme_error_resume(struct pci_dev *pdev) 3414 { 3415 struct nvme_dev *dev = pci_get_drvdata(pdev); 3416 3417 flush_work(&dev->ctrl.reset_work); 3418 } 3419 3420 static const struct pci_error_handlers nvme_err_handler = { 3421 .error_detected = nvme_error_detected, 3422 .slot_reset = nvme_slot_reset, 3423 .resume = nvme_error_resume, 3424 .reset_prepare = nvme_reset_prepare, 3425 .reset_done = nvme_reset_done, 3426 }; 3427 3428 static const struct pci_device_id nvme_id_table[] = { 3429 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3430 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3431 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3432 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3433 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3434 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3435 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3436 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3437 NVME_QUIRK_DEALLOCATE_ZEROES | 3438 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3439 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3440 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3441 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3442 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3443 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3444 NVME_QUIRK_MEDIUM_PRIO_SQ | 3445 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3446 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3447 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3448 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3449 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3450 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3451 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3452 NVME_QUIRK_BOGUS_NID, }, 3453 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3454 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3455 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3456 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3457 NVME_QUIRK_BOGUS_NID, }, 3458 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3459 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3460 NVME_QUIRK_NO_NS_DESC_LIST, }, 3461 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3462 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3463 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3464 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3465 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3466 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3467 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3468 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3469 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3470 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3471 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3472 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3473 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 3474 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3475 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3476 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3477 NVME_QUIRK_BOGUS_NID, }, 3478 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3479 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3480 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3481 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3482 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3483 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3484 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3485 NVME_QUIRK_BOGUS_NID, }, 3486 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3487 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3488 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3489 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3490 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3491 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3492 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3493 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3494 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3495 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3496 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3497 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3498 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3499 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 3500 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3501 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 3502 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3503 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 3504 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3505 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 3506 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3507 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3508 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3509 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3510 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3511 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3512 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3513 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3514 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3515 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3516 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3517 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 3518 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3519 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 3520 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3521 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3522 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3523 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3524 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3525 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3526 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3527 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3528 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3529 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3530 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3531 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3532 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3533 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3534 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3535 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3536 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3537 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3538 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3539 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3540 NVME_QUIRK_128_BYTES_SQES | 3541 NVME_QUIRK_SHARED_TAGS | 3542 NVME_QUIRK_SKIP_CID_GEN }, 3543 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3544 { 0, } 3545 }; 3546 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3547 3548 static struct pci_driver nvme_driver = { 3549 .name = "nvme", 3550 .id_table = nvme_id_table, 3551 .probe = nvme_probe, 3552 .remove = nvme_remove, 3553 .shutdown = nvme_shutdown, 3554 #ifdef CONFIG_PM_SLEEP 3555 .driver = { 3556 .pm = &nvme_dev_pm_ops, 3557 }, 3558 #endif 3559 .sriov_configure = pci_sriov_configure_simple, 3560 .err_handler = &nvme_err_handler, 3561 }; 3562 3563 static int __init nvme_init(void) 3564 { 3565 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3566 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3567 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3568 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3569 3570 return pci_register_driver(&nvme_driver); 3571 } 3572 3573 static void __exit nvme_exit(void) 3574 { 3575 pci_unregister_driver(&nvme_driver); 3576 flush_workqueue(nvme_wq); 3577 } 3578 3579 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3580 MODULE_LICENSE("GPL"); 3581 MODULE_VERSION("1.0"); 3582 module_init(nvme_init); 3583 module_exit(nvme_exit); 3584