1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/blkdev.h> 17 #include <linux/blk-mq.h> 18 #include <linux/cpu.h> 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/fs.h> 22 #include <linux/genhd.h> 23 #include <linux/hdreg.h> 24 #include <linux/idr.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kdev_t.h> 29 #include <linux/kthread.h> 30 #include <linux/kernel.h> 31 #include <linux/mm.h> 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/mutex.h> 35 #include <linux/pci.h> 36 #include <linux/poison.h> 37 #include <linux/ptrace.h> 38 #include <linux/sched.h> 39 #include <linux/slab.h> 40 #include <linux/t10-pi.h> 41 #include <linux/types.h> 42 #include <linux/io-64-nonatomic-lo-hi.h> 43 #include <asm/unaligned.h> 44 45 #include "nvme.h" 46 47 #define NVME_Q_DEPTH 1024 48 #define NVME_AQ_DEPTH 256 49 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 50 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 51 52 unsigned char admin_timeout = 60; 53 module_param(admin_timeout, byte, 0644); 54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); 55 56 unsigned char nvme_io_timeout = 30; 57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644); 58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); 59 60 unsigned char shutdown_timeout = 5; 61 module_param(shutdown_timeout, byte, 0644); 62 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); 63 64 static int use_threaded_interrupts; 65 module_param(use_threaded_interrupts, int, 0); 66 67 static bool use_cmb_sqes = true; 68 module_param(use_cmb_sqes, bool, 0644); 69 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 70 71 static LIST_HEAD(dev_list); 72 static struct task_struct *nvme_thread; 73 static struct workqueue_struct *nvme_workq; 74 static wait_queue_head_t nvme_kthread_wait; 75 76 struct nvme_dev; 77 struct nvme_queue; 78 struct nvme_iod; 79 80 static int __nvme_reset(struct nvme_dev *dev); 81 static int nvme_reset(struct nvme_dev *dev); 82 static void nvme_process_cq(struct nvme_queue *nvmeq); 83 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); 84 static void nvme_dead_ctrl(struct nvme_dev *dev); 85 86 struct async_cmd_info { 87 struct kthread_work work; 88 struct kthread_worker *worker; 89 struct request *req; 90 u32 result; 91 int status; 92 void *ctx; 93 }; 94 95 /* 96 * Represents an NVM Express device. Each nvme_dev is a PCI function. 97 */ 98 struct nvme_dev { 99 struct list_head node; 100 struct nvme_queue **queues; 101 struct blk_mq_tag_set tagset; 102 struct blk_mq_tag_set admin_tagset; 103 u32 __iomem *dbs; 104 struct device *dev; 105 struct dma_pool *prp_page_pool; 106 struct dma_pool *prp_small_pool; 107 unsigned queue_count; 108 unsigned online_queues; 109 unsigned max_qid; 110 int q_depth; 111 u32 db_stride; 112 struct msix_entry *entry; 113 void __iomem *bar; 114 struct work_struct reset_work; 115 struct work_struct probe_work; 116 struct work_struct scan_work; 117 struct mutex shutdown_lock; 118 bool subsystem; 119 void __iomem *cmb; 120 dma_addr_t cmb_dma_addr; 121 u64 cmb_size; 122 u32 cmbsz; 123 124 struct nvme_ctrl ctrl; 125 }; 126 127 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 128 { 129 return container_of(ctrl, struct nvme_dev, ctrl); 130 } 131 132 /* 133 * An NVM Express queue. Each device has at least two (one for admin 134 * commands and one for I/O commands). 135 */ 136 struct nvme_queue { 137 struct device *q_dmadev; 138 struct nvme_dev *dev; 139 char irqname[24]; /* nvme4294967295-65535\0 */ 140 spinlock_t q_lock; 141 struct nvme_command *sq_cmds; 142 struct nvme_command __iomem *sq_cmds_io; 143 volatile struct nvme_completion *cqes; 144 struct blk_mq_tags **tags; 145 dma_addr_t sq_dma_addr; 146 dma_addr_t cq_dma_addr; 147 u32 __iomem *q_db; 148 u16 q_depth; 149 s16 cq_vector; 150 u16 sq_head; 151 u16 sq_tail; 152 u16 cq_head; 153 u16 qid; 154 u8 cq_phase; 155 u8 cqe_seen; 156 struct async_cmd_info cmdinfo; 157 }; 158 159 /* 160 * The nvme_iod describes the data in an I/O, including the list of PRP 161 * entries. You can't see it in this data structure because C doesn't let 162 * me express that. Use nvme_alloc_iod to ensure there's enough space 163 * allocated to store the PRP list. 164 */ 165 struct nvme_iod { 166 unsigned long private; /* For the use of the submitter of the I/O */ 167 int npages; /* In the PRP list. 0 means small pool in use */ 168 int offset; /* Of PRP list */ 169 int nents; /* Used in scatterlist */ 170 int length; /* Of data, in bytes */ 171 dma_addr_t first_dma; 172 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ 173 struct scatterlist sg[0]; 174 }; 175 176 /* 177 * Check we didin't inadvertently grow the command struct 178 */ 179 static inline void _nvme_check_size(void) 180 { 181 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 182 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 183 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 184 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 185 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 186 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 187 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 188 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 189 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); 190 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); 191 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 192 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 193 } 194 195 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, 196 struct nvme_completion *); 197 198 struct nvme_cmd_info { 199 nvme_completion_fn fn; 200 void *ctx; 201 int aborted; 202 struct nvme_queue *nvmeq; 203 struct nvme_iod iod[0]; 204 }; 205 206 /* 207 * Max size of iod being embedded in the request payload 208 */ 209 #define NVME_INT_PAGES 2 210 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 211 #define NVME_INT_MASK 0x01 212 213 /* 214 * Will slightly overestimate the number of pages needed. This is OK 215 * as it only leads to a small amount of wasted memory for the lifetime of 216 * the I/O. 217 */ 218 static int nvme_npages(unsigned size, struct nvme_dev *dev) 219 { 220 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 221 dev->ctrl.page_size); 222 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 223 } 224 225 static unsigned int nvme_cmd_size(struct nvme_dev *dev) 226 { 227 unsigned int ret = sizeof(struct nvme_cmd_info); 228 229 ret += sizeof(struct nvme_iod); 230 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); 231 ret += sizeof(struct scatterlist) * NVME_INT_PAGES; 232 233 return ret; 234 } 235 236 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 237 unsigned int hctx_idx) 238 { 239 struct nvme_dev *dev = data; 240 struct nvme_queue *nvmeq = dev->queues[0]; 241 242 WARN_ON(hctx_idx != 0); 243 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 244 WARN_ON(nvmeq->tags); 245 246 hctx->driver_data = nvmeq; 247 nvmeq->tags = &dev->admin_tagset.tags[0]; 248 return 0; 249 } 250 251 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 252 { 253 struct nvme_queue *nvmeq = hctx->driver_data; 254 255 nvmeq->tags = NULL; 256 } 257 258 static int nvme_admin_init_request(void *data, struct request *req, 259 unsigned int hctx_idx, unsigned int rq_idx, 260 unsigned int numa_node) 261 { 262 struct nvme_dev *dev = data; 263 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 264 struct nvme_queue *nvmeq = dev->queues[0]; 265 266 BUG_ON(!nvmeq); 267 cmd->nvmeq = nvmeq; 268 return 0; 269 } 270 271 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 272 unsigned int hctx_idx) 273 { 274 struct nvme_dev *dev = data; 275 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 276 277 if (!nvmeq->tags) 278 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 279 280 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 281 hctx->driver_data = nvmeq; 282 return 0; 283 } 284 285 static int nvme_init_request(void *data, struct request *req, 286 unsigned int hctx_idx, unsigned int rq_idx, 287 unsigned int numa_node) 288 { 289 struct nvme_dev *dev = data; 290 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 291 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 292 293 BUG_ON(!nvmeq); 294 cmd->nvmeq = nvmeq; 295 return 0; 296 } 297 298 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, 299 nvme_completion_fn handler) 300 { 301 cmd->fn = handler; 302 cmd->ctx = ctx; 303 cmd->aborted = 0; 304 blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); 305 } 306 307 static void *iod_get_private(struct nvme_iod *iod) 308 { 309 return (void *) (iod->private & ~0x1UL); 310 } 311 312 /* 313 * If bit 0 is set, the iod is embedded in the request payload. 314 */ 315 static bool iod_should_kfree(struct nvme_iod *iod) 316 { 317 return (iod->private & NVME_INT_MASK) == 0; 318 } 319 320 /* Special values must be less than 0x1000 */ 321 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) 322 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) 323 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) 324 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) 325 326 static void special_completion(struct nvme_queue *nvmeq, void *ctx, 327 struct nvme_completion *cqe) 328 { 329 if (ctx == CMD_CTX_CANCELLED) 330 return; 331 if (ctx == CMD_CTX_COMPLETED) { 332 dev_warn(nvmeq->q_dmadev, 333 "completed id %d twice on queue %d\n", 334 cqe->command_id, le16_to_cpup(&cqe->sq_id)); 335 return; 336 } 337 if (ctx == CMD_CTX_INVALID) { 338 dev_warn(nvmeq->q_dmadev, 339 "invalid id %d completed on queue %d\n", 340 cqe->command_id, le16_to_cpup(&cqe->sq_id)); 341 return; 342 } 343 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); 344 } 345 346 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) 347 { 348 void *ctx; 349 350 if (fn) 351 *fn = cmd->fn; 352 ctx = cmd->ctx; 353 cmd->fn = special_completion; 354 cmd->ctx = CMD_CTX_CANCELLED; 355 return ctx; 356 } 357 358 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, 359 struct nvme_completion *cqe) 360 { 361 u32 result = le32_to_cpup(&cqe->result); 362 u16 status = le16_to_cpup(&cqe->status) >> 1; 363 364 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) 365 ++nvmeq->dev->ctrl.event_limit; 366 if (status != NVME_SC_SUCCESS) 367 return; 368 369 switch (result & 0xff07) { 370 case NVME_AER_NOTICE_NS_CHANGED: 371 dev_info(nvmeq->q_dmadev, "rescanning\n"); 372 schedule_work(&nvmeq->dev->scan_work); 373 default: 374 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); 375 } 376 } 377 378 static void abort_completion(struct nvme_queue *nvmeq, void *ctx, 379 struct nvme_completion *cqe) 380 { 381 struct request *req = ctx; 382 383 u16 status = le16_to_cpup(&cqe->status) >> 1; 384 u32 result = le32_to_cpup(&cqe->result); 385 386 blk_mq_free_request(req); 387 388 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); 389 ++nvmeq->dev->ctrl.abort_limit; 390 } 391 392 static void async_completion(struct nvme_queue *nvmeq, void *ctx, 393 struct nvme_completion *cqe) 394 { 395 struct async_cmd_info *cmdinfo = ctx; 396 cmdinfo->result = le32_to_cpup(&cqe->result); 397 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; 398 queue_kthread_work(cmdinfo->worker, &cmdinfo->work); 399 blk_mq_free_request(cmdinfo->req); 400 } 401 402 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, 403 unsigned int tag) 404 { 405 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); 406 407 return blk_mq_rq_to_pdu(req); 408 } 409 410 /* 411 * Called with local interrupts disabled and the q_lock held. May not sleep. 412 */ 413 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, 414 nvme_completion_fn *fn) 415 { 416 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); 417 void *ctx; 418 if (tag >= nvmeq->q_depth) { 419 *fn = special_completion; 420 return CMD_CTX_INVALID; 421 } 422 if (fn) 423 *fn = cmd->fn; 424 ctx = cmd->ctx; 425 cmd->fn = special_completion; 426 cmd->ctx = CMD_CTX_COMPLETED; 427 return ctx; 428 } 429 430 /** 431 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 432 * @nvmeq: The queue to use 433 * @cmd: The command to send 434 * 435 * Safe to use from interrupt context 436 */ 437 static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 438 struct nvme_command *cmd) 439 { 440 u16 tail = nvmeq->sq_tail; 441 442 if (nvmeq->sq_cmds_io) 443 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 444 else 445 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 446 447 if (++tail == nvmeq->q_depth) 448 tail = 0; 449 writel(tail, nvmeq->q_db); 450 nvmeq->sq_tail = tail; 451 } 452 453 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 454 { 455 unsigned long flags; 456 spin_lock_irqsave(&nvmeq->q_lock, flags); 457 __nvme_submit_cmd(nvmeq, cmd); 458 spin_unlock_irqrestore(&nvmeq->q_lock, flags); 459 } 460 461 static __le64 **iod_list(struct nvme_iod *iod) 462 { 463 return ((void *)iod) + iod->offset; 464 } 465 466 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, 467 unsigned nseg, unsigned long private) 468 { 469 iod->private = private; 470 iod->offset = offsetof(struct nvme_iod, sg[nseg]); 471 iod->npages = -1; 472 iod->length = nbytes; 473 iod->nents = 0; 474 } 475 476 static struct nvme_iod * 477 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, 478 unsigned long priv, gfp_t gfp) 479 { 480 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + 481 sizeof(__le64 *) * nvme_npages(bytes, dev) + 482 sizeof(struct scatterlist) * nseg, gfp); 483 484 if (iod) 485 iod_init(iod, bytes, nseg, priv); 486 487 return iod; 488 } 489 490 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, 491 gfp_t gfp) 492 { 493 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : 494 sizeof(struct nvme_dsm_range); 495 struct nvme_iod *iod; 496 497 if (rq->nr_phys_segments <= NVME_INT_PAGES && 498 size <= NVME_INT_BYTES(dev)) { 499 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); 500 501 iod = cmd->iod; 502 iod_init(iod, size, rq->nr_phys_segments, 503 (unsigned long) rq | NVME_INT_MASK); 504 return iod; 505 } 506 507 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, 508 (unsigned long) rq, gfp); 509 } 510 511 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) 512 { 513 const int last_prp = dev->ctrl.page_size / 8 - 1; 514 int i; 515 __le64 **list = iod_list(iod); 516 dma_addr_t prp_dma = iod->first_dma; 517 518 if (iod->npages == 0) 519 dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 520 for (i = 0; i < iod->npages; i++) { 521 __le64 *prp_list = list[i]; 522 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 523 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 524 prp_dma = next_prp_dma; 525 } 526 527 if (iod_should_kfree(iod)) 528 kfree(iod); 529 } 530 531 #ifdef CONFIG_BLK_DEV_INTEGRITY 532 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 533 { 534 if (be32_to_cpu(pi->ref_tag) == v) 535 pi->ref_tag = cpu_to_be32(p); 536 } 537 538 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 539 { 540 if (be32_to_cpu(pi->ref_tag) == p) 541 pi->ref_tag = cpu_to_be32(v); 542 } 543 544 /** 545 * nvme_dif_remap - remaps ref tags to bip seed and physical lba 546 * 547 * The virtual start sector is the one that was originally submitted by the 548 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 549 * start sector may be different. Remap protection information to match the 550 * physical LBA on writes, and back to the original seed on reads. 551 * 552 * Type 0 and 3 do not have a ref tag, so no remapping required. 553 */ 554 static void nvme_dif_remap(struct request *req, 555 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 556 { 557 struct nvme_ns *ns = req->rq_disk->private_data; 558 struct bio_integrity_payload *bip; 559 struct t10_pi_tuple *pi; 560 void *p, *pmap; 561 u32 i, nlb, ts, phys, virt; 562 563 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 564 return; 565 566 bip = bio_integrity(req->bio); 567 if (!bip) 568 return; 569 570 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 571 572 p = pmap; 573 virt = bip_get_seed(bip); 574 phys = nvme_block_nr(ns, blk_rq_pos(req)); 575 nlb = (blk_rq_bytes(req) >> ns->lba_shift); 576 ts = ns->disk->queue->integrity.tuple_size; 577 578 for (i = 0; i < nlb; i++, virt++, phys++) { 579 pi = (struct t10_pi_tuple *)p; 580 dif_swap(phys, virt, pi); 581 p += ts; 582 } 583 kunmap_atomic(pmap); 584 } 585 #else /* CONFIG_BLK_DEV_INTEGRITY */ 586 static void nvme_dif_remap(struct request *req, 587 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 588 { 589 } 590 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 591 { 592 } 593 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 594 { 595 } 596 #endif 597 598 static void req_completion(struct nvme_queue *nvmeq, void *ctx, 599 struct nvme_completion *cqe) 600 { 601 struct nvme_iod *iod = ctx; 602 struct request *req = iod_get_private(iod); 603 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); 604 u16 status = le16_to_cpup(&cqe->status) >> 1; 605 int error = 0; 606 607 if (unlikely(status)) { 608 if (!(status & NVME_SC_DNR || blk_noretry_request(req)) 609 && (jiffies - req->start_time) < req->timeout) { 610 unsigned long flags; 611 612 nvme_unmap_data(nvmeq->dev, iod); 613 614 blk_mq_requeue_request(req); 615 spin_lock_irqsave(req->q->queue_lock, flags); 616 if (!blk_queue_stopped(req->q)) 617 blk_mq_kick_requeue_list(req->q); 618 spin_unlock_irqrestore(req->q->queue_lock, flags); 619 return; 620 } 621 622 if (req->cmd_type == REQ_TYPE_DRV_PRIV) { 623 if (cmd_rq->ctx == CMD_CTX_CANCELLED) 624 error = -EINTR; 625 else 626 error = status; 627 } else { 628 error = nvme_error_status(status); 629 } 630 } 631 632 if (req->cmd_type == REQ_TYPE_DRV_PRIV) { 633 u32 result = le32_to_cpup(&cqe->result); 634 req->special = (void *)(uintptr_t)result; 635 } 636 637 if (cmd_rq->aborted) 638 dev_warn(nvmeq->dev->dev, 639 "completing aborted command with status:%04x\n", 640 error); 641 642 nvme_unmap_data(nvmeq->dev, iod); 643 blk_mq_complete_request(req, error); 644 } 645 646 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, 647 int total_len) 648 { 649 struct dma_pool *pool; 650 int length = total_len; 651 struct scatterlist *sg = iod->sg; 652 int dma_len = sg_dma_len(sg); 653 u64 dma_addr = sg_dma_address(sg); 654 u32 page_size = dev->ctrl.page_size; 655 int offset = dma_addr & (page_size - 1); 656 __le64 *prp_list; 657 __le64 **list = iod_list(iod); 658 dma_addr_t prp_dma; 659 int nprps, i; 660 661 length -= (page_size - offset); 662 if (length <= 0) 663 return true; 664 665 dma_len -= (page_size - offset); 666 if (dma_len) { 667 dma_addr += (page_size - offset); 668 } else { 669 sg = sg_next(sg); 670 dma_addr = sg_dma_address(sg); 671 dma_len = sg_dma_len(sg); 672 } 673 674 if (length <= page_size) { 675 iod->first_dma = dma_addr; 676 return true; 677 } 678 679 nprps = DIV_ROUND_UP(length, page_size); 680 if (nprps <= (256 / 8)) { 681 pool = dev->prp_small_pool; 682 iod->npages = 0; 683 } else { 684 pool = dev->prp_page_pool; 685 iod->npages = 1; 686 } 687 688 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 689 if (!prp_list) { 690 iod->first_dma = dma_addr; 691 iod->npages = -1; 692 return false; 693 } 694 list[0] = prp_list; 695 iod->first_dma = prp_dma; 696 i = 0; 697 for (;;) { 698 if (i == page_size >> 3) { 699 __le64 *old_prp_list = prp_list; 700 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 701 if (!prp_list) 702 return false; 703 list[iod->npages++] = prp_list; 704 prp_list[0] = old_prp_list[i - 1]; 705 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 706 i = 1; 707 } 708 prp_list[i++] = cpu_to_le64(dma_addr); 709 dma_len -= page_size; 710 dma_addr += page_size; 711 length -= page_size; 712 if (length <= 0) 713 break; 714 if (dma_len > 0) 715 continue; 716 BUG_ON(dma_len < 0); 717 sg = sg_next(sg); 718 dma_addr = sg_dma_address(sg); 719 dma_len = sg_dma_len(sg); 720 } 721 722 return true; 723 } 724 725 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, 726 struct nvme_command *cmnd) 727 { 728 struct request *req = iod_get_private(iod); 729 struct request_queue *q = req->q; 730 enum dma_data_direction dma_dir = rq_data_dir(req) ? 731 DMA_TO_DEVICE : DMA_FROM_DEVICE; 732 int ret = BLK_MQ_RQ_QUEUE_ERROR; 733 734 sg_init_table(iod->sg, req->nr_phys_segments); 735 iod->nents = blk_rq_map_sg(q, req, iod->sg); 736 if (!iod->nents) 737 goto out; 738 739 ret = BLK_MQ_RQ_QUEUE_BUSY; 740 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) 741 goto out; 742 743 if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) 744 goto out_unmap; 745 746 ret = BLK_MQ_RQ_QUEUE_ERROR; 747 if (blk_integrity_rq(req)) { 748 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 749 goto out_unmap; 750 751 sg_init_table(iod->meta_sg, 1); 752 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) 753 goto out_unmap; 754 755 if (rq_data_dir(req)) 756 nvme_dif_remap(req, nvme_dif_prep); 757 758 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) 759 goto out_unmap; 760 } 761 762 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 763 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); 764 if (blk_integrity_rq(req)) 765 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); 766 return BLK_MQ_RQ_QUEUE_OK; 767 768 out_unmap: 769 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 770 out: 771 return ret; 772 } 773 774 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) 775 { 776 struct request *req = iod_get_private(iod); 777 enum dma_data_direction dma_dir = rq_data_dir(req) ? 778 DMA_TO_DEVICE : DMA_FROM_DEVICE; 779 780 if (iod->nents) { 781 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 782 if (blk_integrity_rq(req)) { 783 if (!rq_data_dir(req)) 784 nvme_dif_remap(req, nvme_dif_complete); 785 dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); 786 } 787 } 788 789 nvme_free_iod(dev, iod); 790 } 791 792 /* 793 * We reuse the small pool to allocate the 16-byte range here as it is not 794 * worth having a special pool for these or additional cases to handle freeing 795 * the iod. 796 */ 797 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, 798 struct nvme_iod *iod, struct nvme_command *cmnd) 799 { 800 struct request *req = iod_get_private(iod); 801 struct nvme_dsm_range *range; 802 803 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, 804 &iod->first_dma); 805 if (!range) 806 return BLK_MQ_RQ_QUEUE_BUSY; 807 iod_list(iod)[0] = (__le64 *)range; 808 iod->npages = 0; 809 810 range->cattr = cpu_to_le32(0); 811 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); 812 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); 813 814 memset(cmnd, 0, sizeof(*cmnd)); 815 cmnd->dsm.opcode = nvme_cmd_dsm; 816 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); 817 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); 818 cmnd->dsm.nr = 0; 819 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); 820 return BLK_MQ_RQ_QUEUE_OK; 821 } 822 823 /* 824 * NOTE: ns is NULL when called on the admin queue. 825 */ 826 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 827 const struct blk_mq_queue_data *bd) 828 { 829 struct nvme_ns *ns = hctx->queue->queuedata; 830 struct nvme_queue *nvmeq = hctx->driver_data; 831 struct nvme_dev *dev = nvmeq->dev; 832 struct request *req = bd->rq; 833 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 834 struct nvme_iod *iod; 835 struct nvme_command cmnd; 836 int ret = BLK_MQ_RQ_QUEUE_OK; 837 838 /* 839 * If formated with metadata, require the block layer provide a buffer 840 * unless this namespace is formated such that the metadata can be 841 * stripped/generated by the controller with PRACT=1. 842 */ 843 if (ns && ns->ms && !blk_integrity_rq(req)) { 844 if (!(ns->pi_type && ns->ms == 8) && 845 req->cmd_type != REQ_TYPE_DRV_PRIV) { 846 blk_mq_complete_request(req, -EFAULT); 847 return BLK_MQ_RQ_QUEUE_OK; 848 } 849 } 850 851 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); 852 if (!iod) 853 return BLK_MQ_RQ_QUEUE_BUSY; 854 855 if (req->cmd_flags & REQ_DISCARD) { 856 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); 857 } else { 858 if (req->cmd_type == REQ_TYPE_DRV_PRIV) 859 memcpy(&cmnd, req->cmd, sizeof(cmnd)); 860 else if (req->cmd_flags & REQ_FLUSH) 861 nvme_setup_flush(ns, &cmnd); 862 else 863 nvme_setup_rw(ns, req, &cmnd); 864 865 if (req->nr_phys_segments) 866 ret = nvme_map_data(dev, iod, &cmnd); 867 } 868 869 if (ret) 870 goto out; 871 872 cmnd.common.command_id = req->tag; 873 nvme_set_info(cmd, iod, req_completion); 874 875 spin_lock_irq(&nvmeq->q_lock); 876 __nvme_submit_cmd(nvmeq, &cmnd); 877 nvme_process_cq(nvmeq); 878 spin_unlock_irq(&nvmeq->q_lock); 879 return BLK_MQ_RQ_QUEUE_OK; 880 out: 881 nvme_free_iod(dev, iod); 882 return ret; 883 } 884 885 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) 886 { 887 u16 head, phase; 888 889 head = nvmeq->cq_head; 890 phase = nvmeq->cq_phase; 891 892 for (;;) { 893 void *ctx; 894 nvme_completion_fn fn; 895 struct nvme_completion cqe = nvmeq->cqes[head]; 896 if ((le16_to_cpu(cqe.status) & 1) != phase) 897 break; 898 nvmeq->sq_head = le16_to_cpu(cqe.sq_head); 899 if (++head == nvmeq->q_depth) { 900 head = 0; 901 phase = !phase; 902 } 903 if (tag && *tag == cqe.command_id) 904 *tag = -1; 905 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); 906 fn(nvmeq, ctx, &cqe); 907 } 908 909 /* If the controller ignores the cq head doorbell and continuously 910 * writes to the queue, it is theoretically possible to wrap around 911 * the queue twice and mistakenly return IRQ_NONE. Linux only 912 * requires that 0.1% of your interrupts are handled, so this isn't 913 * a big problem. 914 */ 915 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) 916 return; 917 918 if (likely(nvmeq->cq_vector >= 0)) 919 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 920 nvmeq->cq_head = head; 921 nvmeq->cq_phase = phase; 922 923 nvmeq->cqe_seen = 1; 924 } 925 926 static void nvme_process_cq(struct nvme_queue *nvmeq) 927 { 928 __nvme_process_cq(nvmeq, NULL); 929 } 930 931 static irqreturn_t nvme_irq(int irq, void *data) 932 { 933 irqreturn_t result; 934 struct nvme_queue *nvmeq = data; 935 spin_lock(&nvmeq->q_lock); 936 nvme_process_cq(nvmeq); 937 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 938 nvmeq->cqe_seen = 0; 939 spin_unlock(&nvmeq->q_lock); 940 return result; 941 } 942 943 static irqreturn_t nvme_irq_check(int irq, void *data) 944 { 945 struct nvme_queue *nvmeq = data; 946 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; 947 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) 948 return IRQ_NONE; 949 return IRQ_WAKE_THREAD; 950 } 951 952 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 953 { 954 struct nvme_queue *nvmeq = hctx->driver_data; 955 956 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 957 nvmeq->cq_phase) { 958 spin_lock_irq(&nvmeq->q_lock); 959 __nvme_process_cq(nvmeq, &tag); 960 spin_unlock_irq(&nvmeq->q_lock); 961 962 if (tag == -1) 963 return 1; 964 } 965 966 return 0; 967 } 968 969 static int nvme_submit_async_admin_req(struct nvme_dev *dev) 970 { 971 struct nvme_queue *nvmeq = dev->queues[0]; 972 struct nvme_command c; 973 struct nvme_cmd_info *cmd_info; 974 struct request *req; 975 976 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 977 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); 978 if (IS_ERR(req)) 979 return PTR_ERR(req); 980 981 req->cmd_flags |= REQ_NO_TIMEOUT; 982 cmd_info = blk_mq_rq_to_pdu(req); 983 nvme_set_info(cmd_info, NULL, async_req_completion); 984 985 memset(&c, 0, sizeof(c)); 986 c.common.opcode = nvme_admin_async_event; 987 c.common.command_id = req->tag; 988 989 blk_mq_free_request(req); 990 __nvme_submit_cmd(nvmeq, &c); 991 return 0; 992 } 993 994 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, 995 struct nvme_command *cmd, 996 struct async_cmd_info *cmdinfo, unsigned timeout) 997 { 998 struct nvme_queue *nvmeq = dev->queues[0]; 999 struct request *req; 1000 struct nvme_cmd_info *cmd_rq; 1001 1002 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); 1003 if (IS_ERR(req)) 1004 return PTR_ERR(req); 1005 1006 req->timeout = timeout; 1007 cmd_rq = blk_mq_rq_to_pdu(req); 1008 cmdinfo->req = req; 1009 nvme_set_info(cmd_rq, cmdinfo, async_completion); 1010 cmdinfo->status = -EINTR; 1011 1012 cmd->common.command_id = req->tag; 1013 1014 nvme_submit_cmd(nvmeq, cmd); 1015 return 0; 1016 } 1017 1018 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1019 { 1020 struct nvme_command c; 1021 1022 memset(&c, 0, sizeof(c)); 1023 c.delete_queue.opcode = opcode; 1024 c.delete_queue.qid = cpu_to_le16(id); 1025 1026 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1027 } 1028 1029 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1030 struct nvme_queue *nvmeq) 1031 { 1032 struct nvme_command c; 1033 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 1034 1035 /* 1036 * Note: we (ab)use the fact the the prp fields survive if no data 1037 * is attached to the request. 1038 */ 1039 memset(&c, 0, sizeof(c)); 1040 c.create_cq.opcode = nvme_admin_create_cq; 1041 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1042 c.create_cq.cqid = cpu_to_le16(qid); 1043 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1044 c.create_cq.cq_flags = cpu_to_le16(flags); 1045 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 1046 1047 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1048 } 1049 1050 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1051 struct nvme_queue *nvmeq) 1052 { 1053 struct nvme_command c; 1054 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; 1055 1056 /* 1057 * Note: we (ab)use the fact the the prp fields survive if no data 1058 * is attached to the request. 1059 */ 1060 memset(&c, 0, sizeof(c)); 1061 c.create_sq.opcode = nvme_admin_create_sq; 1062 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1063 c.create_sq.sqid = cpu_to_le16(qid); 1064 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1065 c.create_sq.sq_flags = cpu_to_le16(flags); 1066 c.create_sq.cqid = cpu_to_le16(qid); 1067 1068 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1069 } 1070 1071 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1072 { 1073 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1074 } 1075 1076 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1077 { 1078 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1079 } 1080 1081 /** 1082 * nvme_abort_req - Attempt aborting a request 1083 * 1084 * Schedule controller reset if the command was already aborted once before and 1085 * still hasn't been returned to the driver, or if this is the admin queue. 1086 */ 1087 static void nvme_abort_req(struct request *req) 1088 { 1089 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); 1090 struct nvme_queue *nvmeq = cmd_rq->nvmeq; 1091 struct nvme_dev *dev = nvmeq->dev; 1092 struct request *abort_req; 1093 struct nvme_cmd_info *abort_cmd; 1094 struct nvme_command cmd; 1095 1096 if (!nvmeq->qid || cmd_rq->aborted) { 1097 spin_lock_irq(&dev_list_lock); 1098 if (!__nvme_reset(dev)) { 1099 dev_warn(dev->dev, 1100 "I/O %d QID %d timeout, reset controller\n", 1101 req->tag, nvmeq->qid); 1102 } 1103 spin_unlock_irq(&dev_list_lock); 1104 return; 1105 } 1106 1107 if (!dev->ctrl.abort_limit) 1108 return; 1109 1110 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 1111 BLK_MQ_REQ_NOWAIT); 1112 if (IS_ERR(abort_req)) 1113 return; 1114 1115 abort_cmd = blk_mq_rq_to_pdu(abort_req); 1116 nvme_set_info(abort_cmd, abort_req, abort_completion); 1117 1118 memset(&cmd, 0, sizeof(cmd)); 1119 cmd.abort.opcode = nvme_admin_abort_cmd; 1120 cmd.abort.cid = req->tag; 1121 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1122 cmd.abort.command_id = abort_req->tag; 1123 1124 --dev->ctrl.abort_limit; 1125 cmd_rq->aborted = 1; 1126 1127 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", req->tag, 1128 nvmeq->qid); 1129 nvme_submit_cmd(dev->queues[0], &cmd); 1130 } 1131 1132 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) 1133 { 1134 struct nvme_queue *nvmeq = data; 1135 void *ctx; 1136 nvme_completion_fn fn; 1137 struct nvme_cmd_info *cmd; 1138 struct nvme_completion cqe; 1139 1140 if (!blk_mq_request_started(req)) 1141 return; 1142 1143 cmd = blk_mq_rq_to_pdu(req); 1144 1145 if (cmd->ctx == CMD_CTX_CANCELLED) 1146 return; 1147 1148 if (blk_queue_dying(req->q)) 1149 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); 1150 else 1151 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); 1152 1153 1154 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", 1155 req->tag, nvmeq->qid); 1156 ctx = cancel_cmd_info(cmd, &fn); 1157 fn(nvmeq, ctx, &cqe); 1158 } 1159 1160 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1161 { 1162 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 1163 struct nvme_queue *nvmeq = cmd->nvmeq; 1164 1165 dev_warn(nvmeq->q_dmadev, "Timeout I/O %d QID %d\n", req->tag, 1166 nvmeq->qid); 1167 nvme_abort_req(req); 1168 1169 /* 1170 * The aborted req will be completed on receiving the abort req. 1171 * We enable the timer again. If hit twice, it'll cause a device reset, 1172 * as the device then is in a faulty state. 1173 */ 1174 return BLK_EH_RESET_TIMER; 1175 } 1176 1177 static void nvme_free_queue(struct nvme_queue *nvmeq) 1178 { 1179 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1180 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1181 if (nvmeq->sq_cmds) 1182 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1183 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1184 kfree(nvmeq); 1185 } 1186 1187 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1188 { 1189 int i; 1190 1191 for (i = dev->queue_count - 1; i >= lowest; i--) { 1192 struct nvme_queue *nvmeq = dev->queues[i]; 1193 dev->queue_count--; 1194 dev->queues[i] = NULL; 1195 nvme_free_queue(nvmeq); 1196 } 1197 } 1198 1199 /** 1200 * nvme_suspend_queue - put queue into suspended state 1201 * @nvmeq - queue to suspend 1202 */ 1203 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1204 { 1205 int vector; 1206 1207 spin_lock_irq(&nvmeq->q_lock); 1208 if (nvmeq->cq_vector == -1) { 1209 spin_unlock_irq(&nvmeq->q_lock); 1210 return 1; 1211 } 1212 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; 1213 nvmeq->dev->online_queues--; 1214 nvmeq->cq_vector = -1; 1215 spin_unlock_irq(&nvmeq->q_lock); 1216 1217 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1218 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); 1219 1220 irq_set_affinity_hint(vector, NULL); 1221 free_irq(vector, nvmeq); 1222 1223 return 0; 1224 } 1225 1226 static void nvme_clear_queue(struct nvme_queue *nvmeq) 1227 { 1228 spin_lock_irq(&nvmeq->q_lock); 1229 if (nvmeq->tags && *nvmeq->tags) 1230 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); 1231 spin_unlock_irq(&nvmeq->q_lock); 1232 } 1233 1234 static void nvme_disable_queue(struct nvme_dev *dev, int qid) 1235 { 1236 struct nvme_queue *nvmeq = dev->queues[qid]; 1237 1238 if (!nvmeq) 1239 return; 1240 if (nvme_suspend_queue(nvmeq)) 1241 return; 1242 1243 /* Don't tell the adapter to delete the admin queue. 1244 * Don't tell a removed adapter to delete IO queues. */ 1245 if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { 1246 adapter_delete_sq(dev, qid); 1247 adapter_delete_cq(dev, qid); 1248 } 1249 1250 spin_lock_irq(&nvmeq->q_lock); 1251 nvme_process_cq(nvmeq); 1252 spin_unlock_irq(&nvmeq->q_lock); 1253 } 1254 1255 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1256 int entry_size) 1257 { 1258 int q_depth = dev->q_depth; 1259 unsigned q_size_aligned = roundup(q_depth * entry_size, 1260 dev->ctrl.page_size); 1261 1262 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1263 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1264 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1265 q_depth = div_u64(mem_per_q, entry_size); 1266 1267 /* 1268 * Ensure the reduced q_depth is above some threshold where it 1269 * would be better to map queues in system memory with the 1270 * original depth 1271 */ 1272 if (q_depth < 64) 1273 return -ENOMEM; 1274 } 1275 1276 return q_depth; 1277 } 1278 1279 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1280 int qid, int depth) 1281 { 1282 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 1283 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 1284 dev->ctrl.page_size); 1285 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 1286 nvmeq->sq_cmds_io = dev->cmb + offset; 1287 } else { 1288 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1289 &nvmeq->sq_dma_addr, GFP_KERNEL); 1290 if (!nvmeq->sq_cmds) 1291 return -ENOMEM; 1292 } 1293 1294 return 0; 1295 } 1296 1297 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1298 int depth) 1299 { 1300 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); 1301 if (!nvmeq) 1302 return NULL; 1303 1304 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 1305 &nvmeq->cq_dma_addr, GFP_KERNEL); 1306 if (!nvmeq->cqes) 1307 goto free_nvmeq; 1308 1309 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1310 goto free_cqdma; 1311 1312 nvmeq->q_dmadev = dev->dev; 1313 nvmeq->dev = dev; 1314 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", 1315 dev->ctrl.instance, qid); 1316 spin_lock_init(&nvmeq->q_lock); 1317 nvmeq->cq_head = 0; 1318 nvmeq->cq_phase = 1; 1319 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1320 nvmeq->q_depth = depth; 1321 nvmeq->qid = qid; 1322 nvmeq->cq_vector = -1; 1323 dev->queues[qid] = nvmeq; 1324 1325 /* make sure queue descriptor is set before queue count, for kthread */ 1326 mb(); 1327 dev->queue_count++; 1328 1329 return nvmeq; 1330 1331 free_cqdma: 1332 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1333 nvmeq->cq_dma_addr); 1334 free_nvmeq: 1335 kfree(nvmeq); 1336 return NULL; 1337 } 1338 1339 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1340 const char *name) 1341 { 1342 if (use_threaded_interrupts) 1343 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, 1344 nvme_irq_check, nvme_irq, IRQF_SHARED, 1345 name, nvmeq); 1346 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, 1347 IRQF_SHARED, name, nvmeq); 1348 } 1349 1350 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1351 { 1352 struct nvme_dev *dev = nvmeq->dev; 1353 1354 spin_lock_irq(&nvmeq->q_lock); 1355 nvmeq->sq_tail = 0; 1356 nvmeq->cq_head = 0; 1357 nvmeq->cq_phase = 1; 1358 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1359 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1360 dev->online_queues++; 1361 spin_unlock_irq(&nvmeq->q_lock); 1362 } 1363 1364 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 1365 { 1366 struct nvme_dev *dev = nvmeq->dev; 1367 int result; 1368 1369 nvmeq->cq_vector = qid - 1; 1370 result = adapter_alloc_cq(dev, qid, nvmeq); 1371 if (result < 0) 1372 return result; 1373 1374 result = adapter_alloc_sq(dev, qid, nvmeq); 1375 if (result < 0) 1376 goto release_cq; 1377 1378 result = queue_request_irq(dev, nvmeq, nvmeq->irqname); 1379 if (result < 0) 1380 goto release_sq; 1381 1382 nvme_init_queue(nvmeq, qid); 1383 return result; 1384 1385 release_sq: 1386 adapter_delete_sq(dev, qid); 1387 release_cq: 1388 adapter_delete_cq(dev, qid); 1389 return result; 1390 } 1391 1392 static struct blk_mq_ops nvme_mq_admin_ops = { 1393 .queue_rq = nvme_queue_rq, 1394 .map_queue = blk_mq_map_queue, 1395 .init_hctx = nvme_admin_init_hctx, 1396 .exit_hctx = nvme_admin_exit_hctx, 1397 .init_request = nvme_admin_init_request, 1398 .timeout = nvme_timeout, 1399 }; 1400 1401 static struct blk_mq_ops nvme_mq_ops = { 1402 .queue_rq = nvme_queue_rq, 1403 .map_queue = blk_mq_map_queue, 1404 .init_hctx = nvme_init_hctx, 1405 .init_request = nvme_init_request, 1406 .timeout = nvme_timeout, 1407 .poll = nvme_poll, 1408 }; 1409 1410 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1411 { 1412 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1413 blk_cleanup_queue(dev->ctrl.admin_q); 1414 blk_mq_free_tag_set(&dev->admin_tagset); 1415 } 1416 } 1417 1418 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1419 { 1420 if (!dev->ctrl.admin_q) { 1421 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1422 dev->admin_tagset.nr_hw_queues = 1; 1423 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; 1424 dev->admin_tagset.reserved_tags = 1; 1425 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1426 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1427 dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1428 dev->admin_tagset.driver_data = dev; 1429 1430 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1431 return -ENOMEM; 1432 1433 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1434 if (IS_ERR(dev->ctrl.admin_q)) { 1435 blk_mq_free_tag_set(&dev->admin_tagset); 1436 return -ENOMEM; 1437 } 1438 if (!blk_get_queue(dev->ctrl.admin_q)) { 1439 nvme_dev_remove_admin(dev); 1440 dev->ctrl.admin_q = NULL; 1441 return -ENODEV; 1442 } 1443 } else 1444 blk_mq_unfreeze_queue(dev->ctrl.admin_q); 1445 1446 return 0; 1447 } 1448 1449 static int nvme_configure_admin_queue(struct nvme_dev *dev) 1450 { 1451 int result; 1452 u32 aqa; 1453 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1454 struct nvme_queue *nvmeq; 1455 1456 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? 1457 NVME_CAP_NSSRC(cap) : 0; 1458 1459 if (dev->subsystem && 1460 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1461 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1462 1463 result = nvme_disable_ctrl(&dev->ctrl, cap); 1464 if (result < 0) 1465 return result; 1466 1467 nvmeq = dev->queues[0]; 1468 if (!nvmeq) { 1469 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1470 if (!nvmeq) 1471 return -ENOMEM; 1472 } 1473 1474 aqa = nvmeq->q_depth - 1; 1475 aqa |= aqa << 16; 1476 1477 writel(aqa, dev->bar + NVME_REG_AQA); 1478 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1479 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1480 1481 result = nvme_enable_ctrl(&dev->ctrl, cap); 1482 if (result) 1483 goto free_nvmeq; 1484 1485 nvmeq->cq_vector = 0; 1486 result = queue_request_irq(dev, nvmeq, nvmeq->irqname); 1487 if (result) { 1488 nvmeq->cq_vector = -1; 1489 goto free_nvmeq; 1490 } 1491 1492 return result; 1493 1494 free_nvmeq: 1495 nvme_free_queues(dev, 0); 1496 return result; 1497 } 1498 1499 static int nvme_kthread(void *data) 1500 { 1501 struct nvme_dev *dev, *next; 1502 1503 while (!kthread_should_stop()) { 1504 set_current_state(TASK_INTERRUPTIBLE); 1505 spin_lock(&dev_list_lock); 1506 list_for_each_entry_safe(dev, next, &dev_list, node) { 1507 int i; 1508 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1509 1510 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || 1511 csts & NVME_CSTS_CFS) { 1512 if (!__nvme_reset(dev)) { 1513 dev_warn(dev->dev, 1514 "Failed status: %x, reset controller\n", 1515 readl(dev->bar + NVME_REG_CSTS)); 1516 } 1517 continue; 1518 } 1519 for (i = 0; i < dev->queue_count; i++) { 1520 struct nvme_queue *nvmeq = dev->queues[i]; 1521 if (!nvmeq) 1522 continue; 1523 spin_lock_irq(&nvmeq->q_lock); 1524 nvme_process_cq(nvmeq); 1525 1526 while (i == 0 && dev->ctrl.event_limit > 0) { 1527 if (nvme_submit_async_admin_req(dev)) 1528 break; 1529 dev->ctrl.event_limit--; 1530 } 1531 spin_unlock_irq(&nvmeq->q_lock); 1532 } 1533 } 1534 spin_unlock(&dev_list_lock); 1535 schedule_timeout(round_jiffies_relative(HZ)); 1536 } 1537 return 0; 1538 } 1539 1540 static int nvme_create_io_queues(struct nvme_dev *dev) 1541 { 1542 unsigned i; 1543 int ret = 0; 1544 1545 for (i = dev->queue_count; i <= dev->max_qid; i++) { 1546 if (!nvme_alloc_queue(dev, i, dev->q_depth)) { 1547 ret = -ENOMEM; 1548 break; 1549 } 1550 } 1551 1552 for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { 1553 ret = nvme_create_queue(dev->queues[i], i); 1554 if (ret) { 1555 nvme_free_queues(dev, i); 1556 break; 1557 } 1558 } 1559 1560 /* 1561 * Ignore failing Create SQ/CQ commands, we can continue with less 1562 * than the desired aount of queues, and even a controller without 1563 * I/O queues an still be used to issue admin commands. This might 1564 * be useful to upgrade a buggy firmware for example. 1565 */ 1566 return ret >= 0 ? 0 : ret; 1567 } 1568 1569 static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 1570 { 1571 u64 szu, size, offset; 1572 u32 cmbloc; 1573 resource_size_t bar_size; 1574 struct pci_dev *pdev = to_pci_dev(dev->dev); 1575 void __iomem *cmb; 1576 dma_addr_t dma_addr; 1577 1578 if (!use_cmb_sqes) 1579 return NULL; 1580 1581 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1582 if (!(NVME_CMB_SZ(dev->cmbsz))) 1583 return NULL; 1584 1585 cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1586 1587 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 1588 size = szu * NVME_CMB_SZ(dev->cmbsz); 1589 offset = szu * NVME_CMB_OFST(cmbloc); 1590 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); 1591 1592 if (offset > bar_size) 1593 return NULL; 1594 1595 /* 1596 * Controllers may support a CMB size larger than their BAR, 1597 * for example, due to being behind a bridge. Reduce the CMB to 1598 * the reported size of the BAR 1599 */ 1600 if (size > bar_size - offset) 1601 size = bar_size - offset; 1602 1603 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; 1604 cmb = ioremap_wc(dma_addr, size); 1605 if (!cmb) 1606 return NULL; 1607 1608 dev->cmb_dma_addr = dma_addr; 1609 dev->cmb_size = size; 1610 return cmb; 1611 } 1612 1613 static inline void nvme_release_cmb(struct nvme_dev *dev) 1614 { 1615 if (dev->cmb) { 1616 iounmap(dev->cmb); 1617 dev->cmb = NULL; 1618 } 1619 } 1620 1621 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1622 { 1623 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); 1624 } 1625 1626 static int nvme_setup_io_queues(struct nvme_dev *dev) 1627 { 1628 struct nvme_queue *adminq = dev->queues[0]; 1629 struct pci_dev *pdev = to_pci_dev(dev->dev); 1630 int result, i, vecs, nr_io_queues, size; 1631 1632 nr_io_queues = num_possible_cpus(); 1633 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 1634 if (result < 0) 1635 return result; 1636 1637 /* 1638 * Degraded controllers might return an error when setting the queue 1639 * count. We still want to be able to bring them online and offer 1640 * access to the admin queue, as that might be only way to fix them up. 1641 */ 1642 if (result > 0) { 1643 dev_err(dev->dev, "Could not set queue count (%d)\n", result); 1644 nr_io_queues = 0; 1645 result = 0; 1646 } 1647 1648 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 1649 result = nvme_cmb_qdepth(dev, nr_io_queues, 1650 sizeof(struct nvme_command)); 1651 if (result > 0) 1652 dev->q_depth = result; 1653 else 1654 nvme_release_cmb(dev); 1655 } 1656 1657 size = db_bar_size(dev, nr_io_queues); 1658 if (size > 8192) { 1659 iounmap(dev->bar); 1660 do { 1661 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1662 if (dev->bar) 1663 break; 1664 if (!--nr_io_queues) 1665 return -ENOMEM; 1666 size = db_bar_size(dev, nr_io_queues); 1667 } while (1); 1668 dev->dbs = dev->bar + 4096; 1669 adminq->q_db = dev->dbs; 1670 } 1671 1672 /* Deregister the admin queue's interrupt */ 1673 free_irq(dev->entry[0].vector, adminq); 1674 1675 /* 1676 * If we enable msix early due to not intx, disable it again before 1677 * setting up the full range we need. 1678 */ 1679 if (!pdev->irq) 1680 pci_disable_msix(pdev); 1681 1682 for (i = 0; i < nr_io_queues; i++) 1683 dev->entry[i].entry = i; 1684 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); 1685 if (vecs < 0) { 1686 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); 1687 if (vecs < 0) { 1688 vecs = 1; 1689 } else { 1690 for (i = 0; i < vecs; i++) 1691 dev->entry[i].vector = i + pdev->irq; 1692 } 1693 } 1694 1695 /* 1696 * Should investigate if there's a performance win from allocating 1697 * more queues than interrupt vectors; it might allow the submission 1698 * path to scale better, even if the receive path is limited by the 1699 * number of interrupts. 1700 */ 1701 nr_io_queues = vecs; 1702 dev->max_qid = nr_io_queues; 1703 1704 result = queue_request_irq(dev, adminq, adminq->irqname); 1705 if (result) { 1706 adminq->cq_vector = -1; 1707 goto free_queues; 1708 } 1709 1710 /* Free previously allocated queues that are no longer usable */ 1711 nvme_free_queues(dev, nr_io_queues + 1); 1712 return nvme_create_io_queues(dev); 1713 1714 free_queues: 1715 nvme_free_queues(dev, 1); 1716 return result; 1717 } 1718 1719 static void nvme_set_irq_hints(struct nvme_dev *dev) 1720 { 1721 struct nvme_queue *nvmeq; 1722 int i; 1723 1724 for (i = 0; i < dev->online_queues; i++) { 1725 nvmeq = dev->queues[i]; 1726 1727 if (!nvmeq->tags || !(*nvmeq->tags)) 1728 continue; 1729 1730 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, 1731 blk_mq_tags_cpumask(*nvmeq->tags)); 1732 } 1733 } 1734 1735 static void nvme_dev_scan(struct work_struct *work) 1736 { 1737 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); 1738 1739 if (!dev->tagset.tags) 1740 return; 1741 nvme_scan_namespaces(&dev->ctrl); 1742 nvme_set_irq_hints(dev); 1743 } 1744 1745 /* 1746 * Return: error value if an error occurred setting up the queues or calling 1747 * Identify Device. 0 if these succeeded, even if adding some of the 1748 * namespaces failed. At the moment, these failures are silent. TBD which 1749 * failures should be reported. 1750 */ 1751 static int nvme_dev_add(struct nvme_dev *dev) 1752 { 1753 if (!dev->ctrl.tagset) { 1754 dev->tagset.ops = &nvme_mq_ops; 1755 dev->tagset.nr_hw_queues = dev->online_queues - 1; 1756 dev->tagset.timeout = NVME_IO_TIMEOUT; 1757 dev->tagset.numa_node = dev_to_node(dev->dev); 1758 dev->tagset.queue_depth = 1759 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 1760 dev->tagset.cmd_size = nvme_cmd_size(dev); 1761 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 1762 dev->tagset.driver_data = dev; 1763 1764 if (blk_mq_alloc_tag_set(&dev->tagset)) 1765 return 0; 1766 dev->ctrl.tagset = &dev->tagset; 1767 } 1768 schedule_work(&dev->scan_work); 1769 return 0; 1770 } 1771 1772 static int nvme_dev_map(struct nvme_dev *dev) 1773 { 1774 u64 cap; 1775 int bars, result = -ENOMEM; 1776 struct pci_dev *pdev = to_pci_dev(dev->dev); 1777 1778 if (pci_enable_device_mem(pdev)) 1779 return result; 1780 1781 dev->entry[0].vector = pdev->irq; 1782 pci_set_master(pdev); 1783 bars = pci_select_bars(pdev, IORESOURCE_MEM); 1784 if (!bars) 1785 goto disable_pci; 1786 1787 if (pci_request_selected_regions(pdev, bars, "nvme")) 1788 goto disable_pci; 1789 1790 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 1791 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 1792 goto disable; 1793 1794 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); 1795 if (!dev->bar) 1796 goto disable; 1797 1798 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 1799 result = -ENODEV; 1800 goto unmap; 1801 } 1802 1803 /* 1804 * Some devices don't advertse INTx interrupts, pre-enable a single 1805 * MSIX vec for setup. We'll adjust this later. 1806 */ 1807 if (!pdev->irq) { 1808 result = pci_enable_msix(pdev, dev->entry, 1); 1809 if (result < 0) 1810 goto unmap; 1811 } 1812 1813 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1814 1815 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); 1816 dev->db_stride = 1 << NVME_CAP_STRIDE(cap); 1817 dev->dbs = dev->bar + 4096; 1818 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) 1819 dev->cmb = nvme_map_cmb(dev); 1820 1821 return 0; 1822 1823 unmap: 1824 iounmap(dev->bar); 1825 dev->bar = NULL; 1826 disable: 1827 pci_release_regions(pdev); 1828 disable_pci: 1829 pci_disable_device(pdev); 1830 return result; 1831 } 1832 1833 static void nvme_dev_unmap(struct nvme_dev *dev) 1834 { 1835 struct pci_dev *pdev = to_pci_dev(dev->dev); 1836 1837 if (pdev->msi_enabled) 1838 pci_disable_msi(pdev); 1839 else if (pdev->msix_enabled) 1840 pci_disable_msix(pdev); 1841 1842 if (dev->bar) { 1843 iounmap(dev->bar); 1844 dev->bar = NULL; 1845 pci_release_regions(pdev); 1846 } 1847 1848 if (pci_is_enabled(pdev)) 1849 pci_disable_device(pdev); 1850 } 1851 1852 struct nvme_delq_ctx { 1853 struct task_struct *waiter; 1854 struct kthread_worker *worker; 1855 atomic_t refcount; 1856 }; 1857 1858 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) 1859 { 1860 dq->waiter = current; 1861 mb(); 1862 1863 for (;;) { 1864 set_current_state(TASK_KILLABLE); 1865 if (!atomic_read(&dq->refcount)) 1866 break; 1867 if (!schedule_timeout(ADMIN_TIMEOUT) || 1868 fatal_signal_pending(current)) { 1869 /* 1870 * Disable the controller first since we can't trust it 1871 * at this point, but leave the admin queue enabled 1872 * until all queue deletion requests are flushed. 1873 * FIXME: This may take a while if there are more h/w 1874 * queues than admin tags. 1875 */ 1876 set_current_state(TASK_RUNNING); 1877 nvme_disable_ctrl(&dev->ctrl, 1878 lo_hi_readq(dev->bar + NVME_REG_CAP)); 1879 nvme_clear_queue(dev->queues[0]); 1880 flush_kthread_worker(dq->worker); 1881 nvme_disable_queue(dev, 0); 1882 return; 1883 } 1884 } 1885 set_current_state(TASK_RUNNING); 1886 } 1887 1888 static void nvme_put_dq(struct nvme_delq_ctx *dq) 1889 { 1890 atomic_dec(&dq->refcount); 1891 if (dq->waiter) 1892 wake_up_process(dq->waiter); 1893 } 1894 1895 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) 1896 { 1897 atomic_inc(&dq->refcount); 1898 return dq; 1899 } 1900 1901 static void nvme_del_queue_end(struct nvme_queue *nvmeq) 1902 { 1903 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; 1904 nvme_put_dq(dq); 1905 1906 spin_lock_irq(&nvmeq->q_lock); 1907 nvme_process_cq(nvmeq); 1908 spin_unlock_irq(&nvmeq->q_lock); 1909 } 1910 1911 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, 1912 kthread_work_func_t fn) 1913 { 1914 struct nvme_command c; 1915 1916 memset(&c, 0, sizeof(c)); 1917 c.delete_queue.opcode = opcode; 1918 c.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1919 1920 init_kthread_work(&nvmeq->cmdinfo.work, fn); 1921 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, 1922 ADMIN_TIMEOUT); 1923 } 1924 1925 static void nvme_del_cq_work_handler(struct kthread_work *work) 1926 { 1927 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1928 cmdinfo.work); 1929 nvme_del_queue_end(nvmeq); 1930 } 1931 1932 static int nvme_delete_cq(struct nvme_queue *nvmeq) 1933 { 1934 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, 1935 nvme_del_cq_work_handler); 1936 } 1937 1938 static void nvme_del_sq_work_handler(struct kthread_work *work) 1939 { 1940 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1941 cmdinfo.work); 1942 int status = nvmeq->cmdinfo.status; 1943 1944 if (!status) 1945 status = nvme_delete_cq(nvmeq); 1946 if (status) 1947 nvme_del_queue_end(nvmeq); 1948 } 1949 1950 static int nvme_delete_sq(struct nvme_queue *nvmeq) 1951 { 1952 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, 1953 nvme_del_sq_work_handler); 1954 } 1955 1956 static void nvme_del_queue_start(struct kthread_work *work) 1957 { 1958 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1959 cmdinfo.work); 1960 if (nvme_delete_sq(nvmeq)) 1961 nvme_del_queue_end(nvmeq); 1962 } 1963 1964 static void nvme_disable_io_queues(struct nvme_dev *dev) 1965 { 1966 int i; 1967 DEFINE_KTHREAD_WORKER_ONSTACK(worker); 1968 struct nvme_delq_ctx dq; 1969 struct task_struct *kworker_task = kthread_run(kthread_worker_fn, 1970 &worker, "nvme%d", dev->ctrl.instance); 1971 1972 if (IS_ERR(kworker_task)) { 1973 dev_err(dev->dev, 1974 "Failed to create queue del task\n"); 1975 for (i = dev->queue_count - 1; i > 0; i--) 1976 nvme_disable_queue(dev, i); 1977 return; 1978 } 1979 1980 dq.waiter = NULL; 1981 atomic_set(&dq.refcount, 0); 1982 dq.worker = &worker; 1983 for (i = dev->queue_count - 1; i > 0; i--) { 1984 struct nvme_queue *nvmeq = dev->queues[i]; 1985 1986 if (nvme_suspend_queue(nvmeq)) 1987 continue; 1988 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); 1989 nvmeq->cmdinfo.worker = dq.worker; 1990 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); 1991 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); 1992 } 1993 nvme_wait_dq(&dq, dev); 1994 kthread_stop(kworker_task); 1995 } 1996 1997 static int nvme_dev_list_add(struct nvme_dev *dev) 1998 { 1999 bool start_thread = false; 2000 2001 spin_lock(&dev_list_lock); 2002 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { 2003 start_thread = true; 2004 nvme_thread = NULL; 2005 } 2006 list_add(&dev->node, &dev_list); 2007 spin_unlock(&dev_list_lock); 2008 2009 if (start_thread) { 2010 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); 2011 wake_up_all(&nvme_kthread_wait); 2012 } else 2013 wait_event_killable(nvme_kthread_wait, nvme_thread); 2014 2015 if (IS_ERR_OR_NULL(nvme_thread)) 2016 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; 2017 2018 return 0; 2019 } 2020 2021 /* 2022 * Remove the node from the device list and check 2023 * for whether or not we need to stop the nvme_thread. 2024 */ 2025 static void nvme_dev_list_remove(struct nvme_dev *dev) 2026 { 2027 struct task_struct *tmp = NULL; 2028 2029 spin_lock(&dev_list_lock); 2030 list_del_init(&dev->node); 2031 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { 2032 tmp = nvme_thread; 2033 nvme_thread = NULL; 2034 } 2035 spin_unlock(&dev_list_lock); 2036 2037 if (tmp) 2038 kthread_stop(tmp); 2039 } 2040 2041 static void nvme_freeze_queues(struct nvme_dev *dev) 2042 { 2043 struct nvme_ns *ns; 2044 2045 list_for_each_entry(ns, &dev->ctrl.namespaces, list) { 2046 blk_mq_freeze_queue_start(ns->queue); 2047 2048 spin_lock_irq(ns->queue->queue_lock); 2049 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); 2050 spin_unlock_irq(ns->queue->queue_lock); 2051 2052 blk_mq_cancel_requeue_work(ns->queue); 2053 blk_mq_stop_hw_queues(ns->queue); 2054 } 2055 } 2056 2057 static void nvme_unfreeze_queues(struct nvme_dev *dev) 2058 { 2059 struct nvme_ns *ns; 2060 2061 list_for_each_entry(ns, &dev->ctrl.namespaces, list) { 2062 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); 2063 blk_mq_unfreeze_queue(ns->queue); 2064 blk_mq_start_stopped_hw_queues(ns->queue, true); 2065 blk_mq_kick_requeue_list(ns->queue); 2066 } 2067 } 2068 2069 static void nvme_dev_shutdown(struct nvme_dev *dev) 2070 { 2071 int i; 2072 u32 csts = -1; 2073 2074 nvme_dev_list_remove(dev); 2075 2076 mutex_lock(&dev->shutdown_lock); 2077 if (dev->bar) { 2078 nvme_freeze_queues(dev); 2079 csts = readl(dev->bar + NVME_REG_CSTS); 2080 } 2081 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { 2082 for (i = dev->queue_count - 1; i >= 0; i--) { 2083 struct nvme_queue *nvmeq = dev->queues[i]; 2084 nvme_suspend_queue(nvmeq); 2085 } 2086 } else { 2087 nvme_disable_io_queues(dev); 2088 nvme_shutdown_ctrl(&dev->ctrl); 2089 nvme_disable_queue(dev, 0); 2090 } 2091 nvme_dev_unmap(dev); 2092 2093 for (i = dev->queue_count - 1; i >= 0; i--) 2094 nvme_clear_queue(dev->queues[i]); 2095 mutex_unlock(&dev->shutdown_lock); 2096 } 2097 2098 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2099 { 2100 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2101 PAGE_SIZE, PAGE_SIZE, 0); 2102 if (!dev->prp_page_pool) 2103 return -ENOMEM; 2104 2105 /* Optimisation for I/Os between 4k and 128k */ 2106 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2107 256, 256, 0); 2108 if (!dev->prp_small_pool) { 2109 dma_pool_destroy(dev->prp_page_pool); 2110 return -ENOMEM; 2111 } 2112 return 0; 2113 } 2114 2115 static void nvme_release_prp_pools(struct nvme_dev *dev) 2116 { 2117 dma_pool_destroy(dev->prp_page_pool); 2118 dma_pool_destroy(dev->prp_small_pool); 2119 } 2120 2121 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2122 { 2123 struct nvme_dev *dev = to_nvme_dev(ctrl); 2124 2125 put_device(dev->dev); 2126 if (dev->tagset.tags) 2127 blk_mq_free_tag_set(&dev->tagset); 2128 if (dev->ctrl.admin_q) 2129 blk_put_queue(dev->ctrl.admin_q); 2130 kfree(dev->queues); 2131 kfree(dev->entry); 2132 kfree(dev); 2133 } 2134 2135 static void nvme_probe_work(struct work_struct *work) 2136 { 2137 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); 2138 int result; 2139 2140 result = nvme_dev_map(dev); 2141 if (result) 2142 goto out; 2143 2144 result = nvme_configure_admin_queue(dev); 2145 if (result) 2146 goto unmap; 2147 2148 nvme_init_queue(dev->queues[0], 0); 2149 result = nvme_alloc_admin_tags(dev); 2150 if (result) 2151 goto disable; 2152 2153 result = nvme_init_identify(&dev->ctrl); 2154 if (result) 2155 goto free_tags; 2156 2157 result = nvme_setup_io_queues(dev); 2158 if (result) 2159 goto free_tags; 2160 2161 dev->ctrl.event_limit = 1; 2162 2163 result = nvme_dev_list_add(dev); 2164 if (result) 2165 goto remove; 2166 2167 /* 2168 * Keep the controller around but remove all namespaces if we don't have 2169 * any working I/O queue. 2170 */ 2171 if (dev->online_queues < 2) { 2172 dev_warn(dev->dev, "IO queues not created\n"); 2173 nvme_remove_namespaces(&dev->ctrl); 2174 } else { 2175 nvme_unfreeze_queues(dev); 2176 nvme_dev_add(dev); 2177 } 2178 2179 return; 2180 2181 remove: 2182 nvme_dev_list_remove(dev); 2183 free_tags: 2184 nvme_dev_remove_admin(dev); 2185 blk_put_queue(dev->ctrl.admin_q); 2186 dev->ctrl.admin_q = NULL; 2187 dev->queues[0]->tags = NULL; 2188 disable: 2189 nvme_disable_queue(dev, 0); 2190 unmap: 2191 nvme_dev_unmap(dev); 2192 out: 2193 if (!work_busy(&dev->reset_work)) 2194 nvme_dead_ctrl(dev); 2195 } 2196 2197 static int nvme_remove_dead_ctrl(void *arg) 2198 { 2199 struct nvme_dev *dev = (struct nvme_dev *)arg; 2200 struct pci_dev *pdev = to_pci_dev(dev->dev); 2201 2202 if (pci_get_drvdata(pdev)) 2203 pci_stop_and_remove_bus_device_locked(pdev); 2204 nvme_put_ctrl(&dev->ctrl); 2205 return 0; 2206 } 2207 2208 static void nvme_dead_ctrl(struct nvme_dev *dev) 2209 { 2210 dev_warn(dev->dev, "Device failed to resume\n"); 2211 kref_get(&dev->ctrl.kref); 2212 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", 2213 dev->ctrl.instance))) { 2214 dev_err(dev->dev, 2215 "Failed to start controller remove task\n"); 2216 nvme_put_ctrl(&dev->ctrl); 2217 } 2218 } 2219 2220 static void nvme_reset_work(struct work_struct *ws) 2221 { 2222 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); 2223 bool in_probe = work_busy(&dev->probe_work); 2224 2225 nvme_dev_shutdown(dev); 2226 2227 /* Synchronize with device probe so that work will see failure status 2228 * and exit gracefully without trying to schedule another reset */ 2229 flush_work(&dev->probe_work); 2230 2231 /* Fail this device if reset occured during probe to avoid 2232 * infinite initialization loops. */ 2233 if (in_probe) { 2234 nvme_dead_ctrl(dev); 2235 return; 2236 } 2237 /* Schedule device resume asynchronously so the reset work is available 2238 * to cleanup errors that may occur during reinitialization */ 2239 schedule_work(&dev->probe_work); 2240 } 2241 2242 static int __nvme_reset(struct nvme_dev *dev) 2243 { 2244 if (work_pending(&dev->reset_work)) 2245 return -EBUSY; 2246 list_del_init(&dev->node); 2247 queue_work(nvme_workq, &dev->reset_work); 2248 return 0; 2249 } 2250 2251 static int nvme_reset(struct nvme_dev *dev) 2252 { 2253 int ret; 2254 2255 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 2256 return -ENODEV; 2257 2258 spin_lock(&dev_list_lock); 2259 ret = __nvme_reset(dev); 2260 spin_unlock(&dev_list_lock); 2261 2262 if (!ret) { 2263 flush_work(&dev->reset_work); 2264 flush_work(&dev->probe_work); 2265 return 0; 2266 } 2267 2268 return ret; 2269 } 2270 2271 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2272 { 2273 *val = readl(to_nvme_dev(ctrl)->bar + off); 2274 return 0; 2275 } 2276 2277 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2278 { 2279 writel(val, to_nvme_dev(ctrl)->bar + off); 2280 return 0; 2281 } 2282 2283 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2284 { 2285 *val = readq(to_nvme_dev(ctrl)->bar + off); 2286 return 0; 2287 } 2288 2289 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) 2290 { 2291 struct nvme_dev *dev = to_nvme_dev(ctrl); 2292 2293 return !dev->bar || dev->online_queues < 2; 2294 } 2295 2296 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 2297 { 2298 return nvme_reset(to_nvme_dev(ctrl)); 2299 } 2300 2301 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2302 .reg_read32 = nvme_pci_reg_read32, 2303 .reg_write32 = nvme_pci_reg_write32, 2304 .reg_read64 = nvme_pci_reg_read64, 2305 .io_incapable = nvme_pci_io_incapable, 2306 .reset_ctrl = nvme_pci_reset_ctrl, 2307 .free_ctrl = nvme_pci_free_ctrl, 2308 }; 2309 2310 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2311 { 2312 int node, result = -ENOMEM; 2313 struct nvme_dev *dev; 2314 2315 node = dev_to_node(&pdev->dev); 2316 if (node == NUMA_NO_NODE) 2317 set_dev_node(&pdev->dev, 0); 2318 2319 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2320 if (!dev) 2321 return -ENOMEM; 2322 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), 2323 GFP_KERNEL, node); 2324 if (!dev->entry) 2325 goto free; 2326 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 2327 GFP_KERNEL, node); 2328 if (!dev->queues) 2329 goto free; 2330 2331 dev->dev = get_device(&pdev->dev); 2332 pci_set_drvdata(pdev, dev); 2333 2334 INIT_LIST_HEAD(&dev->node); 2335 INIT_WORK(&dev->scan_work, nvme_dev_scan); 2336 INIT_WORK(&dev->probe_work, nvme_probe_work); 2337 INIT_WORK(&dev->reset_work, nvme_reset_work); 2338 mutex_init(&dev->shutdown_lock); 2339 2340 result = nvme_setup_prp_pools(dev); 2341 if (result) 2342 goto put_pci; 2343 2344 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2345 id->driver_data); 2346 if (result) 2347 goto release_pools; 2348 2349 schedule_work(&dev->probe_work); 2350 return 0; 2351 2352 release_pools: 2353 nvme_release_prp_pools(dev); 2354 put_pci: 2355 put_device(dev->dev); 2356 free: 2357 kfree(dev->queues); 2358 kfree(dev->entry); 2359 kfree(dev); 2360 return result; 2361 } 2362 2363 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) 2364 { 2365 struct nvme_dev *dev = pci_get_drvdata(pdev); 2366 2367 if (prepare) 2368 nvme_dev_shutdown(dev); 2369 else 2370 schedule_work(&dev->probe_work); 2371 } 2372 2373 static void nvme_shutdown(struct pci_dev *pdev) 2374 { 2375 struct nvme_dev *dev = pci_get_drvdata(pdev); 2376 nvme_dev_shutdown(dev); 2377 } 2378 2379 static void nvme_remove(struct pci_dev *pdev) 2380 { 2381 struct nvme_dev *dev = pci_get_drvdata(pdev); 2382 2383 spin_lock(&dev_list_lock); 2384 list_del_init(&dev->node); 2385 spin_unlock(&dev_list_lock); 2386 2387 pci_set_drvdata(pdev, NULL); 2388 flush_work(&dev->probe_work); 2389 flush_work(&dev->reset_work); 2390 flush_work(&dev->scan_work); 2391 nvme_remove_namespaces(&dev->ctrl); 2392 nvme_dev_shutdown(dev); 2393 nvme_dev_remove_admin(dev); 2394 nvme_free_queues(dev, 0); 2395 nvme_release_cmb(dev); 2396 nvme_release_prp_pools(dev); 2397 nvme_put_ctrl(&dev->ctrl); 2398 } 2399 2400 /* These functions are yet to be implemented */ 2401 #define nvme_error_detected NULL 2402 #define nvme_dump_registers NULL 2403 #define nvme_link_reset NULL 2404 #define nvme_slot_reset NULL 2405 #define nvme_error_resume NULL 2406 2407 #ifdef CONFIG_PM_SLEEP 2408 static int nvme_suspend(struct device *dev) 2409 { 2410 struct pci_dev *pdev = to_pci_dev(dev); 2411 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2412 2413 nvme_dev_shutdown(ndev); 2414 return 0; 2415 } 2416 2417 static int nvme_resume(struct device *dev) 2418 { 2419 struct pci_dev *pdev = to_pci_dev(dev); 2420 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2421 2422 schedule_work(&ndev->probe_work); 2423 return 0; 2424 } 2425 #endif 2426 2427 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2428 2429 static const struct pci_error_handlers nvme_err_handler = { 2430 .error_detected = nvme_error_detected, 2431 .mmio_enabled = nvme_dump_registers, 2432 .link_reset = nvme_link_reset, 2433 .slot_reset = nvme_slot_reset, 2434 .resume = nvme_error_resume, 2435 .reset_notify = nvme_reset_notify, 2436 }; 2437 2438 /* Move to pci_ids.h later */ 2439 #define PCI_CLASS_STORAGE_EXPRESS 0x010802 2440 2441 static const struct pci_device_id nvme_id_table[] = { 2442 { PCI_VDEVICE(INTEL, 0x0953), 2443 .driver_data = NVME_QUIRK_STRIPE_SIZE, }, 2444 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2445 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2446 { 0, } 2447 }; 2448 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2449 2450 static struct pci_driver nvme_driver = { 2451 .name = "nvme", 2452 .id_table = nvme_id_table, 2453 .probe = nvme_probe, 2454 .remove = nvme_remove, 2455 .shutdown = nvme_shutdown, 2456 .driver = { 2457 .pm = &nvme_dev_pm_ops, 2458 }, 2459 .err_handler = &nvme_err_handler, 2460 }; 2461 2462 static int __init nvme_init(void) 2463 { 2464 int result; 2465 2466 init_waitqueue_head(&nvme_kthread_wait); 2467 2468 nvme_workq = create_singlethread_workqueue("nvme"); 2469 if (!nvme_workq) 2470 return -ENOMEM; 2471 2472 result = nvme_core_init(); 2473 if (result < 0) 2474 goto kill_workq; 2475 2476 result = pci_register_driver(&nvme_driver); 2477 if (result) 2478 goto core_exit; 2479 return 0; 2480 2481 core_exit: 2482 nvme_core_exit(); 2483 kill_workq: 2484 destroy_workqueue(nvme_workq); 2485 return result; 2486 } 2487 2488 static void __exit nvme_exit(void) 2489 { 2490 pci_unregister_driver(&nvme_driver); 2491 nvme_core_exit(); 2492 destroy_workqueue(nvme_workq); 2493 BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); 2494 _nvme_check_size(); 2495 } 2496 2497 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2498 MODULE_LICENSE("GPL"); 2499 MODULE_VERSION("1.0"); 2500 module_init(nvme_init); 2501 module_exit(nvme_exit); 2502