1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 72 { 73 unsigned int n; 74 int ret; 75 76 ret = kstrtouint(val, 10, &n); 77 if (ret != 0 || n > num_possible_cpus()) 78 return -EINVAL; 79 return param_set_uint(val, kp); 80 } 81 82 static const struct kernel_param_ops io_queue_count_ops = { 83 .set = io_queue_count_set, 84 .get = param_get_uint, 85 }; 86 87 static unsigned int write_queues; 88 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 89 MODULE_PARM_DESC(write_queues, 90 "Number of queues to use for writes. If not set, reads and writes " 91 "will share a queue set."); 92 93 static unsigned int poll_queues; 94 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 95 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 96 97 struct nvme_dev; 98 struct nvme_queue; 99 100 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 101 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 102 103 /* 104 * Represents an NVM Express device. Each nvme_dev is a PCI function. 105 */ 106 struct nvme_dev { 107 struct nvme_queue *queues; 108 struct blk_mq_tag_set tagset; 109 struct blk_mq_tag_set admin_tagset; 110 u32 __iomem *dbs; 111 struct device *dev; 112 struct dma_pool *prp_page_pool; 113 struct dma_pool *prp_small_pool; 114 unsigned online_queues; 115 unsigned max_qid; 116 unsigned io_queues[HCTX_MAX_TYPES]; 117 unsigned int num_vecs; 118 int q_depth; 119 int io_sqes; 120 u32 db_stride; 121 void __iomem *bar; 122 unsigned long bar_mapped_size; 123 struct work_struct remove_work; 124 struct mutex shutdown_lock; 125 bool subsystem; 126 u64 cmb_size; 127 bool cmb_use_sqes; 128 u32 cmbsz; 129 u32 cmbloc; 130 struct nvme_ctrl ctrl; 131 u32 last_ps; 132 133 mempool_t *iod_mempool; 134 135 /* shadow doorbell buffer support: */ 136 u32 *dbbuf_dbs; 137 dma_addr_t dbbuf_dbs_dma_addr; 138 u32 *dbbuf_eis; 139 dma_addr_t dbbuf_eis_dma_addr; 140 141 /* host memory buffer support: */ 142 u64 host_mem_size; 143 u32 nr_host_mem_descs; 144 dma_addr_t host_mem_descs_dma; 145 struct nvme_host_mem_buf_desc *host_mem_descs; 146 void **host_mem_desc_bufs; 147 unsigned int nr_allocated_queues; 148 unsigned int nr_write_queues; 149 unsigned int nr_poll_queues; 150 }; 151 152 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 153 { 154 int n = 0, ret; 155 156 ret = kstrtoint(val, 10, &n); 157 if (ret != 0 || n < 2) 158 return -EINVAL; 159 160 return param_set_int(val, kp); 161 } 162 163 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 164 { 165 return qid * 2 * stride; 166 } 167 168 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 169 { 170 return (qid * 2 + 1) * stride; 171 } 172 173 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 174 { 175 return container_of(ctrl, struct nvme_dev, ctrl); 176 } 177 178 /* 179 * An NVM Express queue. Each device has at least two (one for admin 180 * commands and one for I/O commands). 181 */ 182 struct nvme_queue { 183 struct nvme_dev *dev; 184 spinlock_t sq_lock; 185 void *sq_cmds; 186 /* only used for poll queues: */ 187 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 188 struct nvme_completion *cqes; 189 dma_addr_t sq_dma_addr; 190 dma_addr_t cq_dma_addr; 191 u32 __iomem *q_db; 192 u16 q_depth; 193 u16 cq_vector; 194 u16 sq_tail; 195 u16 cq_head; 196 u16 qid; 197 u8 cq_phase; 198 u8 sqes; 199 unsigned long flags; 200 #define NVMEQ_ENABLED 0 201 #define NVMEQ_SQ_CMB 1 202 #define NVMEQ_DELETE_ERROR 2 203 #define NVMEQ_POLLED 3 204 u32 *dbbuf_sq_db; 205 u32 *dbbuf_cq_db; 206 u32 *dbbuf_sq_ei; 207 u32 *dbbuf_cq_ei; 208 struct completion delete_done; 209 }; 210 211 /* 212 * The nvme_iod describes the data in an I/O. 213 * 214 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 215 * to the actual struct scatterlist. 216 */ 217 struct nvme_iod { 218 struct nvme_request req; 219 struct nvme_queue *nvmeq; 220 bool use_sgl; 221 int aborted; 222 int npages; /* In the PRP list. 0 means small pool in use */ 223 int nents; /* Used in scatterlist */ 224 dma_addr_t first_dma; 225 unsigned int dma_len; /* length of single DMA segment mapping */ 226 dma_addr_t meta_dma; 227 struct scatterlist *sg; 228 }; 229 230 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 231 { 232 return dev->nr_allocated_queues * 8 * dev->db_stride; 233 } 234 235 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 236 { 237 unsigned int mem_size = nvme_dbbuf_size(dev); 238 239 if (dev->dbbuf_dbs) 240 return 0; 241 242 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 243 &dev->dbbuf_dbs_dma_addr, 244 GFP_KERNEL); 245 if (!dev->dbbuf_dbs) 246 return -ENOMEM; 247 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 248 &dev->dbbuf_eis_dma_addr, 249 GFP_KERNEL); 250 if (!dev->dbbuf_eis) { 251 dma_free_coherent(dev->dev, mem_size, 252 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 253 dev->dbbuf_dbs = NULL; 254 return -ENOMEM; 255 } 256 257 return 0; 258 } 259 260 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 261 { 262 unsigned int mem_size = nvme_dbbuf_size(dev); 263 264 if (dev->dbbuf_dbs) { 265 dma_free_coherent(dev->dev, mem_size, 266 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 267 dev->dbbuf_dbs = NULL; 268 } 269 if (dev->dbbuf_eis) { 270 dma_free_coherent(dev->dev, mem_size, 271 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 272 dev->dbbuf_eis = NULL; 273 } 274 } 275 276 static void nvme_dbbuf_init(struct nvme_dev *dev, 277 struct nvme_queue *nvmeq, int qid) 278 { 279 if (!dev->dbbuf_dbs || !qid) 280 return; 281 282 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 283 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 284 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 285 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 286 } 287 288 static void nvme_dbbuf_set(struct nvme_dev *dev) 289 { 290 struct nvme_command c; 291 292 if (!dev->dbbuf_dbs) 293 return; 294 295 memset(&c, 0, sizeof(c)); 296 c.dbbuf.opcode = nvme_admin_dbbuf; 297 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 298 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 299 300 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 301 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 302 /* Free memory and continue on */ 303 nvme_dbbuf_dma_free(dev); 304 } 305 } 306 307 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 308 { 309 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 310 } 311 312 /* Update dbbuf and return true if an MMIO is required */ 313 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 314 volatile u32 *dbbuf_ei) 315 { 316 if (dbbuf_db) { 317 u16 old_value; 318 319 /* 320 * Ensure that the queue is written before updating 321 * the doorbell in memory 322 */ 323 wmb(); 324 325 old_value = *dbbuf_db; 326 *dbbuf_db = value; 327 328 /* 329 * Ensure that the doorbell is updated before reading the event 330 * index from memory. The controller needs to provide similar 331 * ordering to ensure the envent index is updated before reading 332 * the doorbell. 333 */ 334 mb(); 335 336 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 337 return false; 338 } 339 340 return true; 341 } 342 343 /* 344 * Will slightly overestimate the number of pages needed. This is OK 345 * as it only leads to a small amount of wasted memory for the lifetime of 346 * the I/O. 347 */ 348 static int nvme_npages(unsigned size, struct nvme_dev *dev) 349 { 350 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 351 dev->ctrl.page_size); 352 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 353 } 354 355 /* 356 * Calculates the number of pages needed for the SGL segments. For example a 4k 357 * page can accommodate 256 SGL descriptors. 358 */ 359 static int nvme_pci_npages_sgl(unsigned int num_seg) 360 { 361 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 362 } 363 364 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 365 unsigned int size, unsigned int nseg, bool use_sgl) 366 { 367 size_t alloc_size; 368 369 if (use_sgl) 370 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 371 else 372 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 373 374 return alloc_size + sizeof(struct scatterlist) * nseg; 375 } 376 377 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 378 unsigned int hctx_idx) 379 { 380 struct nvme_dev *dev = data; 381 struct nvme_queue *nvmeq = &dev->queues[0]; 382 383 WARN_ON(hctx_idx != 0); 384 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 385 386 hctx->driver_data = nvmeq; 387 return 0; 388 } 389 390 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 391 unsigned int hctx_idx) 392 { 393 struct nvme_dev *dev = data; 394 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 395 396 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 397 hctx->driver_data = nvmeq; 398 return 0; 399 } 400 401 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 402 unsigned int hctx_idx, unsigned int numa_node) 403 { 404 struct nvme_dev *dev = set->driver_data; 405 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 406 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 407 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 408 409 BUG_ON(!nvmeq); 410 iod->nvmeq = nvmeq; 411 412 nvme_req(req)->ctrl = &dev->ctrl; 413 return 0; 414 } 415 416 static int queue_irq_offset(struct nvme_dev *dev) 417 { 418 /* if we have more than 1 vec, admin queue offsets us by 1 */ 419 if (dev->num_vecs > 1) 420 return 1; 421 422 return 0; 423 } 424 425 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 426 { 427 struct nvme_dev *dev = set->driver_data; 428 int i, qoff, offset; 429 430 offset = queue_irq_offset(dev); 431 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 432 struct blk_mq_queue_map *map = &set->map[i]; 433 434 map->nr_queues = dev->io_queues[i]; 435 if (!map->nr_queues) { 436 BUG_ON(i == HCTX_TYPE_DEFAULT); 437 continue; 438 } 439 440 /* 441 * The poll queue(s) doesn't have an IRQ (and hence IRQ 442 * affinity), so use the regular blk-mq cpu mapping 443 */ 444 map->queue_offset = qoff; 445 if (i != HCTX_TYPE_POLL && offset) 446 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 447 else 448 blk_mq_map_queues(map); 449 qoff += map->nr_queues; 450 offset += map->nr_queues; 451 } 452 453 return 0; 454 } 455 456 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq) 457 { 458 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 459 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 460 writel(nvmeq->sq_tail, nvmeq->q_db); 461 } 462 463 /** 464 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 465 * @nvmeq: The queue to use 466 * @cmd: The command to send 467 * @write_sq: whether to write to the SQ doorbell 468 */ 469 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 470 bool write_sq) 471 { 472 spin_lock(&nvmeq->sq_lock); 473 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 474 cmd, sizeof(*cmd)); 475 if (++nvmeq->sq_tail == nvmeq->q_depth) 476 nvmeq->sq_tail = 0; 477 if (write_sq) 478 nvme_write_sq_db(nvmeq); 479 spin_unlock(&nvmeq->sq_lock); 480 } 481 482 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 483 { 484 struct nvme_queue *nvmeq = hctx->driver_data; 485 486 spin_lock(&nvmeq->sq_lock); 487 nvme_write_sq_db(nvmeq); 488 spin_unlock(&nvmeq->sq_lock); 489 } 490 491 static void **nvme_pci_iod_list(struct request *req) 492 { 493 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 494 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 495 } 496 497 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 498 { 499 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 500 int nseg = blk_rq_nr_phys_segments(req); 501 unsigned int avg_seg_size; 502 503 if (nseg == 0) 504 return false; 505 506 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 507 508 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 509 return false; 510 if (!iod->nvmeq->qid) 511 return false; 512 if (!sgl_threshold || avg_seg_size < sgl_threshold) 513 return false; 514 return true; 515 } 516 517 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 518 { 519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 520 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 521 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 522 int i; 523 524 if (iod->dma_len) { 525 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 526 rq_dma_dir(req)); 527 return; 528 } 529 530 WARN_ON_ONCE(!iod->nents); 531 532 if (is_pci_p2pdma_page(sg_page(iod->sg))) 533 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 534 rq_dma_dir(req)); 535 else 536 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 537 538 539 if (iod->npages == 0) 540 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 541 dma_addr); 542 543 for (i = 0; i < iod->npages; i++) { 544 void *addr = nvme_pci_iod_list(req)[i]; 545 546 if (iod->use_sgl) { 547 struct nvme_sgl_desc *sg_list = addr; 548 549 next_dma_addr = 550 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 551 } else { 552 __le64 *prp_list = addr; 553 554 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 555 } 556 557 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 558 dma_addr = next_dma_addr; 559 } 560 561 mempool_free(iod->sg, dev->iod_mempool); 562 } 563 564 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 565 { 566 int i; 567 struct scatterlist *sg; 568 569 for_each_sg(sgl, sg, nents, i) { 570 dma_addr_t phys = sg_phys(sg); 571 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 572 "dma_address:%pad dma_length:%d\n", 573 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 574 sg_dma_len(sg)); 575 } 576 } 577 578 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 579 struct request *req, struct nvme_rw_command *cmnd) 580 { 581 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 582 struct dma_pool *pool; 583 int length = blk_rq_payload_bytes(req); 584 struct scatterlist *sg = iod->sg; 585 int dma_len = sg_dma_len(sg); 586 u64 dma_addr = sg_dma_address(sg); 587 u32 page_size = dev->ctrl.page_size; 588 int offset = dma_addr & (page_size - 1); 589 __le64 *prp_list; 590 void **list = nvme_pci_iod_list(req); 591 dma_addr_t prp_dma; 592 int nprps, i; 593 594 length -= (page_size - offset); 595 if (length <= 0) { 596 iod->first_dma = 0; 597 goto done; 598 } 599 600 dma_len -= (page_size - offset); 601 if (dma_len) { 602 dma_addr += (page_size - offset); 603 } else { 604 sg = sg_next(sg); 605 dma_addr = sg_dma_address(sg); 606 dma_len = sg_dma_len(sg); 607 } 608 609 if (length <= page_size) { 610 iod->first_dma = dma_addr; 611 goto done; 612 } 613 614 nprps = DIV_ROUND_UP(length, page_size); 615 if (nprps <= (256 / 8)) { 616 pool = dev->prp_small_pool; 617 iod->npages = 0; 618 } else { 619 pool = dev->prp_page_pool; 620 iod->npages = 1; 621 } 622 623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 624 if (!prp_list) { 625 iod->first_dma = dma_addr; 626 iod->npages = -1; 627 return BLK_STS_RESOURCE; 628 } 629 list[0] = prp_list; 630 iod->first_dma = prp_dma; 631 i = 0; 632 for (;;) { 633 if (i == page_size >> 3) { 634 __le64 *old_prp_list = prp_list; 635 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 636 if (!prp_list) 637 return BLK_STS_RESOURCE; 638 list[iod->npages++] = prp_list; 639 prp_list[0] = old_prp_list[i - 1]; 640 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 641 i = 1; 642 } 643 prp_list[i++] = cpu_to_le64(dma_addr); 644 dma_len -= page_size; 645 dma_addr += page_size; 646 length -= page_size; 647 if (length <= 0) 648 break; 649 if (dma_len > 0) 650 continue; 651 if (unlikely(dma_len < 0)) 652 goto bad_sgl; 653 sg = sg_next(sg); 654 dma_addr = sg_dma_address(sg); 655 dma_len = sg_dma_len(sg); 656 } 657 658 done: 659 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 660 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 661 662 return BLK_STS_OK; 663 664 bad_sgl: 665 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 666 "Invalid SGL for payload:%d nents:%d\n", 667 blk_rq_payload_bytes(req), iod->nents); 668 return BLK_STS_IOERR; 669 } 670 671 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 672 struct scatterlist *sg) 673 { 674 sge->addr = cpu_to_le64(sg_dma_address(sg)); 675 sge->length = cpu_to_le32(sg_dma_len(sg)); 676 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 677 } 678 679 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 680 dma_addr_t dma_addr, int entries) 681 { 682 sge->addr = cpu_to_le64(dma_addr); 683 if (entries < SGES_PER_PAGE) { 684 sge->length = cpu_to_le32(entries * sizeof(*sge)); 685 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 686 } else { 687 sge->length = cpu_to_le32(PAGE_SIZE); 688 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 689 } 690 } 691 692 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 693 struct request *req, struct nvme_rw_command *cmd, int entries) 694 { 695 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 696 struct dma_pool *pool; 697 struct nvme_sgl_desc *sg_list; 698 struct scatterlist *sg = iod->sg; 699 dma_addr_t sgl_dma; 700 int i = 0; 701 702 /* setting the transfer type as SGL */ 703 cmd->flags = NVME_CMD_SGL_METABUF; 704 705 if (entries == 1) { 706 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 707 return BLK_STS_OK; 708 } 709 710 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 711 pool = dev->prp_small_pool; 712 iod->npages = 0; 713 } else { 714 pool = dev->prp_page_pool; 715 iod->npages = 1; 716 } 717 718 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 719 if (!sg_list) { 720 iod->npages = -1; 721 return BLK_STS_RESOURCE; 722 } 723 724 nvme_pci_iod_list(req)[0] = sg_list; 725 iod->first_dma = sgl_dma; 726 727 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 728 729 do { 730 if (i == SGES_PER_PAGE) { 731 struct nvme_sgl_desc *old_sg_desc = sg_list; 732 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 733 734 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 735 if (!sg_list) 736 return BLK_STS_RESOURCE; 737 738 i = 0; 739 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 740 sg_list[i++] = *link; 741 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 742 } 743 744 nvme_pci_sgl_set_data(&sg_list[i++], sg); 745 sg = sg_next(sg); 746 } while (--entries > 0); 747 748 return BLK_STS_OK; 749 } 750 751 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 752 struct request *req, struct nvme_rw_command *cmnd, 753 struct bio_vec *bv) 754 { 755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 756 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 757 unsigned int first_prp_len = dev->ctrl.page_size - offset; 758 759 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 760 if (dma_mapping_error(dev->dev, iod->first_dma)) 761 return BLK_STS_RESOURCE; 762 iod->dma_len = bv->bv_len; 763 764 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 765 if (bv->bv_len > first_prp_len) 766 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 767 return 0; 768 } 769 770 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 771 struct request *req, struct nvme_rw_command *cmnd, 772 struct bio_vec *bv) 773 { 774 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 775 776 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 777 if (dma_mapping_error(dev->dev, iod->first_dma)) 778 return BLK_STS_RESOURCE; 779 iod->dma_len = bv->bv_len; 780 781 cmnd->flags = NVME_CMD_SGL_METABUF; 782 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 783 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 784 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 785 return 0; 786 } 787 788 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 789 struct nvme_command *cmnd) 790 { 791 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 792 blk_status_t ret = BLK_STS_RESOURCE; 793 int nr_mapped; 794 795 if (blk_rq_nr_phys_segments(req) == 1) { 796 struct bio_vec bv = req_bvec(req); 797 798 if (!is_pci_p2pdma_page(bv.bv_page)) { 799 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 800 return nvme_setup_prp_simple(dev, req, 801 &cmnd->rw, &bv); 802 803 if (iod->nvmeq->qid && 804 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 805 return nvme_setup_sgl_simple(dev, req, 806 &cmnd->rw, &bv); 807 } 808 } 809 810 iod->dma_len = 0; 811 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 812 if (!iod->sg) 813 return BLK_STS_RESOURCE; 814 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 815 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 816 if (!iod->nents) 817 goto out; 818 819 if (is_pci_p2pdma_page(sg_page(iod->sg))) 820 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 821 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 822 else 823 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 824 rq_dma_dir(req), DMA_ATTR_NO_WARN); 825 if (!nr_mapped) 826 goto out; 827 828 iod->use_sgl = nvme_pci_use_sgls(dev, req); 829 if (iod->use_sgl) 830 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 831 else 832 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 833 out: 834 if (ret != BLK_STS_OK) 835 nvme_unmap_data(dev, req); 836 return ret; 837 } 838 839 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 840 struct nvme_command *cmnd) 841 { 842 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 843 844 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 845 rq_dma_dir(req), 0); 846 if (dma_mapping_error(dev->dev, iod->meta_dma)) 847 return BLK_STS_IOERR; 848 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 849 return 0; 850 } 851 852 /* 853 * NOTE: ns is NULL when called on the admin queue. 854 */ 855 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 856 const struct blk_mq_queue_data *bd) 857 { 858 struct nvme_ns *ns = hctx->queue->queuedata; 859 struct nvme_queue *nvmeq = hctx->driver_data; 860 struct nvme_dev *dev = nvmeq->dev; 861 struct request *req = bd->rq; 862 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 863 struct nvme_command cmnd; 864 blk_status_t ret; 865 866 iod->aborted = 0; 867 iod->npages = -1; 868 iod->nents = 0; 869 870 /* 871 * We should not need to do this, but we're still using this to 872 * ensure we can drain requests on a dying queue. 873 */ 874 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 875 return BLK_STS_IOERR; 876 877 ret = nvme_setup_cmd(ns, req, &cmnd); 878 if (ret) 879 return ret; 880 881 if (blk_rq_nr_phys_segments(req)) { 882 ret = nvme_map_data(dev, req, &cmnd); 883 if (ret) 884 goto out_free_cmd; 885 } 886 887 if (blk_integrity_rq(req)) { 888 ret = nvme_map_metadata(dev, req, &cmnd); 889 if (ret) 890 goto out_unmap_data; 891 } 892 893 blk_mq_start_request(req); 894 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 895 return BLK_STS_OK; 896 out_unmap_data: 897 nvme_unmap_data(dev, req); 898 out_free_cmd: 899 nvme_cleanup_cmd(req); 900 return ret; 901 } 902 903 static void nvme_pci_complete_rq(struct request *req) 904 { 905 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 906 struct nvme_dev *dev = iod->nvmeq->dev; 907 908 if (blk_integrity_rq(req)) 909 dma_unmap_page(dev->dev, iod->meta_dma, 910 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 911 if (blk_rq_nr_phys_segments(req)) 912 nvme_unmap_data(dev, req); 913 nvme_complete_rq(req); 914 } 915 916 /* We read the CQE phase first to check if the rest of the entry is valid */ 917 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 918 { 919 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 920 921 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 922 } 923 924 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 925 { 926 u16 head = nvmeq->cq_head; 927 928 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 929 nvmeq->dbbuf_cq_ei)) 930 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 931 } 932 933 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 934 { 935 if (!nvmeq->qid) 936 return nvmeq->dev->admin_tagset.tags[0]; 937 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 938 } 939 940 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 941 { 942 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 943 struct request *req; 944 945 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 946 dev_warn(nvmeq->dev->ctrl.device, 947 "invalid id %d completed on queue %d\n", 948 cqe->command_id, le16_to_cpu(cqe->sq_id)); 949 return; 950 } 951 952 /* 953 * AEN requests are special as they don't time out and can 954 * survive any kind of queue freeze and often don't respond to 955 * aborts. We don't even bother to allocate a struct request 956 * for them but rather special case them here. 957 */ 958 if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 959 nvme_complete_async_event(&nvmeq->dev->ctrl, 960 cqe->status, &cqe->result); 961 return; 962 } 963 964 req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 965 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 966 nvme_end_request(req, cqe->status, cqe->result); 967 } 968 969 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 970 { 971 u16 tmp = nvmeq->cq_head + 1; 972 973 if (tmp == nvmeq->q_depth) { 974 nvmeq->cq_head = 0; 975 nvmeq->cq_phase ^= 1; 976 } else { 977 nvmeq->cq_head = tmp; 978 } 979 } 980 981 static inline int nvme_process_cq(struct nvme_queue *nvmeq) 982 { 983 int found = 0; 984 985 while (nvme_cqe_pending(nvmeq)) { 986 found++; 987 /* 988 * load-load control dependency between phase and the rest of 989 * the cqe requires a full read memory barrier 990 */ 991 dma_rmb(); 992 nvme_handle_cqe(nvmeq, nvmeq->cq_head); 993 nvme_update_cq_head(nvmeq); 994 } 995 996 if (found) 997 nvme_ring_cq_doorbell(nvmeq); 998 return found; 999 } 1000 1001 static irqreturn_t nvme_irq(int irq, void *data) 1002 { 1003 struct nvme_queue *nvmeq = data; 1004 irqreturn_t ret = IRQ_NONE; 1005 1006 /* 1007 * The rmb/wmb pair ensures we see all updates from a previous run of 1008 * the irq handler, even if that was on another CPU. 1009 */ 1010 rmb(); 1011 if (nvme_process_cq(nvmeq)) 1012 ret = IRQ_HANDLED; 1013 wmb(); 1014 1015 return ret; 1016 } 1017 1018 static irqreturn_t nvme_irq_check(int irq, void *data) 1019 { 1020 struct nvme_queue *nvmeq = data; 1021 if (nvme_cqe_pending(nvmeq)) 1022 return IRQ_WAKE_THREAD; 1023 return IRQ_NONE; 1024 } 1025 1026 /* 1027 * Poll for completions for any interrupt driven queue 1028 * Can be called from any context. 1029 */ 1030 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1031 { 1032 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1033 1034 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1035 1036 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1037 nvme_process_cq(nvmeq); 1038 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1039 } 1040 1041 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1042 { 1043 struct nvme_queue *nvmeq = hctx->driver_data; 1044 bool found; 1045 1046 if (!nvme_cqe_pending(nvmeq)) 1047 return 0; 1048 1049 spin_lock(&nvmeq->cq_poll_lock); 1050 found = nvme_process_cq(nvmeq); 1051 spin_unlock(&nvmeq->cq_poll_lock); 1052 1053 return found; 1054 } 1055 1056 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1057 { 1058 struct nvme_dev *dev = to_nvme_dev(ctrl); 1059 struct nvme_queue *nvmeq = &dev->queues[0]; 1060 struct nvme_command c; 1061 1062 memset(&c, 0, sizeof(c)); 1063 c.common.opcode = nvme_admin_async_event; 1064 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1065 nvme_submit_cmd(nvmeq, &c, true); 1066 } 1067 1068 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1069 { 1070 struct nvme_command c; 1071 1072 memset(&c, 0, sizeof(c)); 1073 c.delete_queue.opcode = opcode; 1074 c.delete_queue.qid = cpu_to_le16(id); 1075 1076 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1077 } 1078 1079 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1080 struct nvme_queue *nvmeq, s16 vector) 1081 { 1082 struct nvme_command c; 1083 int flags = NVME_QUEUE_PHYS_CONTIG; 1084 1085 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1086 flags |= NVME_CQ_IRQ_ENABLED; 1087 1088 /* 1089 * Note: we (ab)use the fact that the prp fields survive if no data 1090 * is attached to the request. 1091 */ 1092 memset(&c, 0, sizeof(c)); 1093 c.create_cq.opcode = nvme_admin_create_cq; 1094 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1095 c.create_cq.cqid = cpu_to_le16(qid); 1096 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1097 c.create_cq.cq_flags = cpu_to_le16(flags); 1098 c.create_cq.irq_vector = cpu_to_le16(vector); 1099 1100 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1101 } 1102 1103 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1104 struct nvme_queue *nvmeq) 1105 { 1106 struct nvme_ctrl *ctrl = &dev->ctrl; 1107 struct nvme_command c; 1108 int flags = NVME_QUEUE_PHYS_CONTIG; 1109 1110 /* 1111 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1112 * set. Since URGENT priority is zeroes, it makes all queues 1113 * URGENT. 1114 */ 1115 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1116 flags |= NVME_SQ_PRIO_MEDIUM; 1117 1118 /* 1119 * Note: we (ab)use the fact that the prp fields survive if no data 1120 * is attached to the request. 1121 */ 1122 memset(&c, 0, sizeof(c)); 1123 c.create_sq.opcode = nvme_admin_create_sq; 1124 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1125 c.create_sq.sqid = cpu_to_le16(qid); 1126 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1127 c.create_sq.sq_flags = cpu_to_le16(flags); 1128 c.create_sq.cqid = cpu_to_le16(qid); 1129 1130 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1131 } 1132 1133 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1134 { 1135 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1136 } 1137 1138 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1139 { 1140 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1141 } 1142 1143 static void abort_endio(struct request *req, blk_status_t error) 1144 { 1145 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1146 struct nvme_queue *nvmeq = iod->nvmeq; 1147 1148 dev_warn(nvmeq->dev->ctrl.device, 1149 "Abort status: 0x%x", nvme_req(req)->status); 1150 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1151 blk_mq_free_request(req); 1152 } 1153 1154 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1155 { 1156 1157 /* If true, indicates loss of adapter communication, possibly by a 1158 * NVMe Subsystem reset. 1159 */ 1160 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1161 1162 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1163 switch (dev->ctrl.state) { 1164 case NVME_CTRL_RESETTING: 1165 case NVME_CTRL_CONNECTING: 1166 return false; 1167 default: 1168 break; 1169 } 1170 1171 /* We shouldn't reset unless the controller is on fatal error state 1172 * _or_ if we lost the communication with it. 1173 */ 1174 if (!(csts & NVME_CSTS_CFS) && !nssro) 1175 return false; 1176 1177 return true; 1178 } 1179 1180 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1181 { 1182 /* Read a config register to help see what died. */ 1183 u16 pci_status; 1184 int result; 1185 1186 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1187 &pci_status); 1188 if (result == PCIBIOS_SUCCESSFUL) 1189 dev_warn(dev->ctrl.device, 1190 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1191 csts, pci_status); 1192 else 1193 dev_warn(dev->ctrl.device, 1194 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1195 csts, result); 1196 } 1197 1198 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1199 { 1200 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1201 struct nvme_queue *nvmeq = iod->nvmeq; 1202 struct nvme_dev *dev = nvmeq->dev; 1203 struct request *abort_req; 1204 struct nvme_command cmd; 1205 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1206 1207 /* If PCI error recovery process is happening, we cannot reset or 1208 * the recovery mechanism will surely fail. 1209 */ 1210 mb(); 1211 if (pci_channel_offline(to_pci_dev(dev->dev))) 1212 return BLK_EH_RESET_TIMER; 1213 1214 /* 1215 * Reset immediately if the controller is failed 1216 */ 1217 if (nvme_should_reset(dev, csts)) { 1218 nvme_warn_reset(dev, csts); 1219 nvme_dev_disable(dev, false); 1220 nvme_reset_ctrl(&dev->ctrl); 1221 return BLK_EH_DONE; 1222 } 1223 1224 /* 1225 * Did we miss an interrupt? 1226 */ 1227 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1228 nvme_poll(req->mq_hctx); 1229 else 1230 nvme_poll_irqdisable(nvmeq); 1231 1232 if (blk_mq_request_completed(req)) { 1233 dev_warn(dev->ctrl.device, 1234 "I/O %d QID %d timeout, completion polled\n", 1235 req->tag, nvmeq->qid); 1236 return BLK_EH_DONE; 1237 } 1238 1239 /* 1240 * Shutdown immediately if controller times out while starting. The 1241 * reset work will see the pci device disabled when it gets the forced 1242 * cancellation error. All outstanding requests are completed on 1243 * shutdown, so we return BLK_EH_DONE. 1244 */ 1245 switch (dev->ctrl.state) { 1246 case NVME_CTRL_CONNECTING: 1247 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1248 /* fall through */ 1249 case NVME_CTRL_DELETING: 1250 dev_warn_ratelimited(dev->ctrl.device, 1251 "I/O %d QID %d timeout, disable controller\n", 1252 req->tag, nvmeq->qid); 1253 nvme_dev_disable(dev, true); 1254 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1255 return BLK_EH_DONE; 1256 case NVME_CTRL_RESETTING: 1257 return BLK_EH_RESET_TIMER; 1258 default: 1259 break; 1260 } 1261 1262 /* 1263 * Shutdown the controller immediately and schedule a reset if the 1264 * command was already aborted once before and still hasn't been 1265 * returned to the driver, or if this is the admin queue. 1266 */ 1267 if (!nvmeq->qid || iod->aborted) { 1268 dev_warn(dev->ctrl.device, 1269 "I/O %d QID %d timeout, reset controller\n", 1270 req->tag, nvmeq->qid); 1271 nvme_dev_disable(dev, false); 1272 nvme_reset_ctrl(&dev->ctrl); 1273 1274 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1275 return BLK_EH_DONE; 1276 } 1277 1278 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1279 atomic_inc(&dev->ctrl.abort_limit); 1280 return BLK_EH_RESET_TIMER; 1281 } 1282 iod->aborted = 1; 1283 1284 memset(&cmd, 0, sizeof(cmd)); 1285 cmd.abort.opcode = nvme_admin_abort_cmd; 1286 cmd.abort.cid = req->tag; 1287 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1288 1289 dev_warn(nvmeq->dev->ctrl.device, 1290 "I/O %d QID %d timeout, aborting\n", 1291 req->tag, nvmeq->qid); 1292 1293 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1294 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1295 if (IS_ERR(abort_req)) { 1296 atomic_inc(&dev->ctrl.abort_limit); 1297 return BLK_EH_RESET_TIMER; 1298 } 1299 1300 abort_req->timeout = ADMIN_TIMEOUT; 1301 abort_req->end_io_data = NULL; 1302 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1303 1304 /* 1305 * The aborted req will be completed on receiving the abort req. 1306 * We enable the timer again. If hit twice, it'll cause a device reset, 1307 * as the device then is in a faulty state. 1308 */ 1309 return BLK_EH_RESET_TIMER; 1310 } 1311 1312 static void nvme_free_queue(struct nvme_queue *nvmeq) 1313 { 1314 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1315 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1316 if (!nvmeq->sq_cmds) 1317 return; 1318 1319 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1320 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1321 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1322 } else { 1323 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1324 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1325 } 1326 } 1327 1328 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1329 { 1330 int i; 1331 1332 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1333 dev->ctrl.queue_count--; 1334 nvme_free_queue(&dev->queues[i]); 1335 } 1336 } 1337 1338 /** 1339 * nvme_suspend_queue - put queue into suspended state 1340 * @nvmeq: queue to suspend 1341 */ 1342 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1343 { 1344 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1345 return 1; 1346 1347 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1348 mb(); 1349 1350 nvmeq->dev->online_queues--; 1351 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1352 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1353 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1354 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1355 return 0; 1356 } 1357 1358 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1359 { 1360 int i; 1361 1362 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1363 nvme_suspend_queue(&dev->queues[i]); 1364 } 1365 1366 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1367 { 1368 struct nvme_queue *nvmeq = &dev->queues[0]; 1369 1370 if (shutdown) 1371 nvme_shutdown_ctrl(&dev->ctrl); 1372 else 1373 nvme_disable_ctrl(&dev->ctrl); 1374 1375 nvme_poll_irqdisable(nvmeq); 1376 } 1377 1378 /* 1379 * Called only on a device that has been disabled and after all other threads 1380 * that can check this device's completion queues have synced, except 1381 * nvme_poll(). This is the last chance for the driver to see a natural 1382 * completion before nvme_cancel_request() terminates all incomplete requests. 1383 */ 1384 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1385 { 1386 int i; 1387 1388 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1389 spin_lock(&dev->queues[i].cq_poll_lock); 1390 nvme_process_cq(&dev->queues[i]); 1391 spin_unlock(&dev->queues[i].cq_poll_lock); 1392 } 1393 } 1394 1395 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1396 int entry_size) 1397 { 1398 int q_depth = dev->q_depth; 1399 unsigned q_size_aligned = roundup(q_depth * entry_size, 1400 dev->ctrl.page_size); 1401 1402 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1403 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1404 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1405 q_depth = div_u64(mem_per_q, entry_size); 1406 1407 /* 1408 * Ensure the reduced q_depth is above some threshold where it 1409 * would be better to map queues in system memory with the 1410 * original depth 1411 */ 1412 if (q_depth < 64) 1413 return -ENOMEM; 1414 } 1415 1416 return q_depth; 1417 } 1418 1419 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1420 int qid) 1421 { 1422 struct pci_dev *pdev = to_pci_dev(dev->dev); 1423 1424 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1425 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1426 if (nvmeq->sq_cmds) { 1427 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1428 nvmeq->sq_cmds); 1429 if (nvmeq->sq_dma_addr) { 1430 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1431 return 0; 1432 } 1433 1434 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1435 } 1436 } 1437 1438 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1439 &nvmeq->sq_dma_addr, GFP_KERNEL); 1440 if (!nvmeq->sq_cmds) 1441 return -ENOMEM; 1442 return 0; 1443 } 1444 1445 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1446 { 1447 struct nvme_queue *nvmeq = &dev->queues[qid]; 1448 1449 if (dev->ctrl.queue_count > qid) 1450 return 0; 1451 1452 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1453 nvmeq->q_depth = depth; 1454 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1455 &nvmeq->cq_dma_addr, GFP_KERNEL); 1456 if (!nvmeq->cqes) 1457 goto free_nvmeq; 1458 1459 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1460 goto free_cqdma; 1461 1462 nvmeq->dev = dev; 1463 spin_lock_init(&nvmeq->sq_lock); 1464 spin_lock_init(&nvmeq->cq_poll_lock); 1465 nvmeq->cq_head = 0; 1466 nvmeq->cq_phase = 1; 1467 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1468 nvmeq->qid = qid; 1469 dev->ctrl.queue_count++; 1470 1471 return 0; 1472 1473 free_cqdma: 1474 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1475 nvmeq->cq_dma_addr); 1476 free_nvmeq: 1477 return -ENOMEM; 1478 } 1479 1480 static int queue_request_irq(struct nvme_queue *nvmeq) 1481 { 1482 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1483 int nr = nvmeq->dev->ctrl.instance; 1484 1485 if (use_threaded_interrupts) { 1486 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1487 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1488 } else { 1489 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1490 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1491 } 1492 } 1493 1494 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1495 { 1496 struct nvme_dev *dev = nvmeq->dev; 1497 1498 nvmeq->sq_tail = 0; 1499 nvmeq->cq_head = 0; 1500 nvmeq->cq_phase = 1; 1501 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1502 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1503 nvme_dbbuf_init(dev, nvmeq, qid); 1504 dev->online_queues++; 1505 wmb(); /* ensure the first interrupt sees the initialization */ 1506 } 1507 1508 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1509 { 1510 struct nvme_dev *dev = nvmeq->dev; 1511 int result; 1512 u16 vector = 0; 1513 1514 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1515 1516 /* 1517 * A queue's vector matches the queue identifier unless the controller 1518 * has only one vector available. 1519 */ 1520 if (!polled) 1521 vector = dev->num_vecs == 1 ? 0 : qid; 1522 else 1523 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1524 1525 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1526 if (result) 1527 return result; 1528 1529 result = adapter_alloc_sq(dev, qid, nvmeq); 1530 if (result < 0) 1531 return result; 1532 if (result) 1533 goto release_cq; 1534 1535 nvmeq->cq_vector = vector; 1536 nvme_init_queue(nvmeq, qid); 1537 1538 if (!polled) { 1539 result = queue_request_irq(nvmeq); 1540 if (result < 0) 1541 goto release_sq; 1542 } 1543 1544 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1545 return result; 1546 1547 release_sq: 1548 dev->online_queues--; 1549 adapter_delete_sq(dev, qid); 1550 release_cq: 1551 adapter_delete_cq(dev, qid); 1552 return result; 1553 } 1554 1555 static const struct blk_mq_ops nvme_mq_admin_ops = { 1556 .queue_rq = nvme_queue_rq, 1557 .complete = nvme_pci_complete_rq, 1558 .init_hctx = nvme_admin_init_hctx, 1559 .init_request = nvme_init_request, 1560 .timeout = nvme_timeout, 1561 }; 1562 1563 static const struct blk_mq_ops nvme_mq_ops = { 1564 .queue_rq = nvme_queue_rq, 1565 .complete = nvme_pci_complete_rq, 1566 .commit_rqs = nvme_commit_rqs, 1567 .init_hctx = nvme_init_hctx, 1568 .init_request = nvme_init_request, 1569 .map_queues = nvme_pci_map_queues, 1570 .timeout = nvme_timeout, 1571 .poll = nvme_poll, 1572 }; 1573 1574 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1575 { 1576 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1577 /* 1578 * If the controller was reset during removal, it's possible 1579 * user requests may be waiting on a stopped queue. Start the 1580 * queue to flush these to completion. 1581 */ 1582 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1583 blk_cleanup_queue(dev->ctrl.admin_q); 1584 blk_mq_free_tag_set(&dev->admin_tagset); 1585 } 1586 } 1587 1588 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1589 { 1590 if (!dev->ctrl.admin_q) { 1591 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1592 dev->admin_tagset.nr_hw_queues = 1; 1593 1594 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1595 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1596 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1597 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1598 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1599 dev->admin_tagset.driver_data = dev; 1600 1601 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1602 return -ENOMEM; 1603 dev->ctrl.admin_tagset = &dev->admin_tagset; 1604 1605 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1606 if (IS_ERR(dev->ctrl.admin_q)) { 1607 blk_mq_free_tag_set(&dev->admin_tagset); 1608 return -ENOMEM; 1609 } 1610 if (!blk_get_queue(dev->ctrl.admin_q)) { 1611 nvme_dev_remove_admin(dev); 1612 dev->ctrl.admin_q = NULL; 1613 return -ENODEV; 1614 } 1615 } else 1616 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1617 1618 return 0; 1619 } 1620 1621 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1622 { 1623 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1624 } 1625 1626 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1627 { 1628 struct pci_dev *pdev = to_pci_dev(dev->dev); 1629 1630 if (size <= dev->bar_mapped_size) 1631 return 0; 1632 if (size > pci_resource_len(pdev, 0)) 1633 return -ENOMEM; 1634 if (dev->bar) 1635 iounmap(dev->bar); 1636 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1637 if (!dev->bar) { 1638 dev->bar_mapped_size = 0; 1639 return -ENOMEM; 1640 } 1641 dev->bar_mapped_size = size; 1642 dev->dbs = dev->bar + NVME_REG_DBS; 1643 1644 return 0; 1645 } 1646 1647 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1648 { 1649 int result; 1650 u32 aqa; 1651 struct nvme_queue *nvmeq; 1652 1653 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1654 if (result < 0) 1655 return result; 1656 1657 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1658 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1659 1660 if (dev->subsystem && 1661 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1662 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1663 1664 result = nvme_disable_ctrl(&dev->ctrl); 1665 if (result < 0) 1666 return result; 1667 1668 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1669 if (result) 1670 return result; 1671 1672 nvmeq = &dev->queues[0]; 1673 aqa = nvmeq->q_depth - 1; 1674 aqa |= aqa << 16; 1675 1676 writel(aqa, dev->bar + NVME_REG_AQA); 1677 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1678 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1679 1680 result = nvme_enable_ctrl(&dev->ctrl); 1681 if (result) 1682 return result; 1683 1684 nvmeq->cq_vector = 0; 1685 nvme_init_queue(nvmeq, 0); 1686 result = queue_request_irq(nvmeq); 1687 if (result) { 1688 dev->online_queues--; 1689 return result; 1690 } 1691 1692 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1693 return result; 1694 } 1695 1696 static int nvme_create_io_queues(struct nvme_dev *dev) 1697 { 1698 unsigned i, max, rw_queues; 1699 int ret = 0; 1700 1701 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1702 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1703 ret = -ENOMEM; 1704 break; 1705 } 1706 } 1707 1708 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1709 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1710 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1711 dev->io_queues[HCTX_TYPE_READ]; 1712 } else { 1713 rw_queues = max; 1714 } 1715 1716 for (i = dev->online_queues; i <= max; i++) { 1717 bool polled = i > rw_queues; 1718 1719 ret = nvme_create_queue(&dev->queues[i], i, polled); 1720 if (ret) 1721 break; 1722 } 1723 1724 /* 1725 * Ignore failing Create SQ/CQ commands, we can continue with less 1726 * than the desired amount of queues, and even a controller without 1727 * I/O queues can still be used to issue admin commands. This might 1728 * be useful to upgrade a buggy firmware for example. 1729 */ 1730 return ret >= 0 ? 0 : ret; 1731 } 1732 1733 static ssize_t nvme_cmb_show(struct device *dev, 1734 struct device_attribute *attr, 1735 char *buf) 1736 { 1737 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1738 1739 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1740 ndev->cmbloc, ndev->cmbsz); 1741 } 1742 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1743 1744 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1745 { 1746 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1747 1748 return 1ULL << (12 + 4 * szu); 1749 } 1750 1751 static u32 nvme_cmb_size(struct nvme_dev *dev) 1752 { 1753 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1754 } 1755 1756 static void nvme_map_cmb(struct nvme_dev *dev) 1757 { 1758 u64 size, offset; 1759 resource_size_t bar_size; 1760 struct pci_dev *pdev = to_pci_dev(dev->dev); 1761 int bar; 1762 1763 if (dev->cmb_size) 1764 return; 1765 1766 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1767 if (!dev->cmbsz) 1768 return; 1769 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1770 1771 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1772 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1773 bar = NVME_CMB_BIR(dev->cmbloc); 1774 bar_size = pci_resource_len(pdev, bar); 1775 1776 if (offset > bar_size) 1777 return; 1778 1779 /* 1780 * Controllers may support a CMB size larger than their BAR, 1781 * for example, due to being behind a bridge. Reduce the CMB to 1782 * the reported size of the BAR 1783 */ 1784 if (size > bar_size - offset) 1785 size = bar_size - offset; 1786 1787 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1788 dev_warn(dev->ctrl.device, 1789 "failed to register the CMB\n"); 1790 return; 1791 } 1792 1793 dev->cmb_size = size; 1794 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1795 1796 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1797 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1798 pci_p2pmem_publish(pdev, true); 1799 1800 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1801 &dev_attr_cmb.attr, NULL)) 1802 dev_warn(dev->ctrl.device, 1803 "failed to add sysfs attribute for CMB\n"); 1804 } 1805 1806 static inline void nvme_release_cmb(struct nvme_dev *dev) 1807 { 1808 if (dev->cmb_size) { 1809 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1810 &dev_attr_cmb.attr, NULL); 1811 dev->cmb_size = 0; 1812 } 1813 } 1814 1815 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1816 { 1817 u64 dma_addr = dev->host_mem_descs_dma; 1818 struct nvme_command c; 1819 int ret; 1820 1821 memset(&c, 0, sizeof(c)); 1822 c.features.opcode = nvme_admin_set_features; 1823 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1824 c.features.dword11 = cpu_to_le32(bits); 1825 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1826 ilog2(dev->ctrl.page_size)); 1827 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1828 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1829 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1830 1831 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1832 if (ret) { 1833 dev_warn(dev->ctrl.device, 1834 "failed to set host mem (err %d, flags %#x).\n", 1835 ret, bits); 1836 } 1837 return ret; 1838 } 1839 1840 static void nvme_free_host_mem(struct nvme_dev *dev) 1841 { 1842 int i; 1843 1844 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1845 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1846 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1847 1848 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1849 le64_to_cpu(desc->addr), 1850 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1851 } 1852 1853 kfree(dev->host_mem_desc_bufs); 1854 dev->host_mem_desc_bufs = NULL; 1855 dma_free_coherent(dev->dev, 1856 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1857 dev->host_mem_descs, dev->host_mem_descs_dma); 1858 dev->host_mem_descs = NULL; 1859 dev->nr_host_mem_descs = 0; 1860 } 1861 1862 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1863 u32 chunk_size) 1864 { 1865 struct nvme_host_mem_buf_desc *descs; 1866 u32 max_entries, len; 1867 dma_addr_t descs_dma; 1868 int i = 0; 1869 void **bufs; 1870 u64 size, tmp; 1871 1872 tmp = (preferred + chunk_size - 1); 1873 do_div(tmp, chunk_size); 1874 max_entries = tmp; 1875 1876 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1877 max_entries = dev->ctrl.hmmaxd; 1878 1879 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1880 &descs_dma, GFP_KERNEL); 1881 if (!descs) 1882 goto out; 1883 1884 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1885 if (!bufs) 1886 goto out_free_descs; 1887 1888 for (size = 0; size < preferred && i < max_entries; size += len) { 1889 dma_addr_t dma_addr; 1890 1891 len = min_t(u64, chunk_size, preferred - size); 1892 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1893 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1894 if (!bufs[i]) 1895 break; 1896 1897 descs[i].addr = cpu_to_le64(dma_addr); 1898 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1899 i++; 1900 } 1901 1902 if (!size) 1903 goto out_free_bufs; 1904 1905 dev->nr_host_mem_descs = i; 1906 dev->host_mem_size = size; 1907 dev->host_mem_descs = descs; 1908 dev->host_mem_descs_dma = descs_dma; 1909 dev->host_mem_desc_bufs = bufs; 1910 return 0; 1911 1912 out_free_bufs: 1913 while (--i >= 0) { 1914 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1915 1916 dma_free_attrs(dev->dev, size, bufs[i], 1917 le64_to_cpu(descs[i].addr), 1918 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1919 } 1920 1921 kfree(bufs); 1922 out_free_descs: 1923 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1924 descs_dma); 1925 out: 1926 dev->host_mem_descs = NULL; 1927 return -ENOMEM; 1928 } 1929 1930 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1931 { 1932 u32 chunk_size; 1933 1934 /* start big and work our way down */ 1935 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1936 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1937 chunk_size /= 2) { 1938 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1939 if (!min || dev->host_mem_size >= min) 1940 return 0; 1941 nvme_free_host_mem(dev); 1942 } 1943 } 1944 1945 return -ENOMEM; 1946 } 1947 1948 static int nvme_setup_host_mem(struct nvme_dev *dev) 1949 { 1950 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1951 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1952 u64 min = (u64)dev->ctrl.hmmin * 4096; 1953 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1954 int ret; 1955 1956 preferred = min(preferred, max); 1957 if (min > max) { 1958 dev_warn(dev->ctrl.device, 1959 "min host memory (%lld MiB) above limit (%d MiB).\n", 1960 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1961 nvme_free_host_mem(dev); 1962 return 0; 1963 } 1964 1965 /* 1966 * If we already have a buffer allocated check if we can reuse it. 1967 */ 1968 if (dev->host_mem_descs) { 1969 if (dev->host_mem_size >= min) 1970 enable_bits |= NVME_HOST_MEM_RETURN; 1971 else 1972 nvme_free_host_mem(dev); 1973 } 1974 1975 if (!dev->host_mem_descs) { 1976 if (nvme_alloc_host_mem(dev, min, preferred)) { 1977 dev_warn(dev->ctrl.device, 1978 "failed to allocate host memory buffer.\n"); 1979 return 0; /* controller must work without HMB */ 1980 } 1981 1982 dev_info(dev->ctrl.device, 1983 "allocated %lld MiB host memory buffer.\n", 1984 dev->host_mem_size >> ilog2(SZ_1M)); 1985 } 1986 1987 ret = nvme_set_host_mem(dev, enable_bits); 1988 if (ret) 1989 nvme_free_host_mem(dev); 1990 return ret; 1991 } 1992 1993 /* 1994 * nirqs is the number of interrupts available for write and read 1995 * queues. The core already reserved an interrupt for the admin queue. 1996 */ 1997 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 1998 { 1999 struct nvme_dev *dev = affd->priv; 2000 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2001 2002 /* 2003 * If there is no interupt available for queues, ensure that 2004 * the default queue is set to 1. The affinity set size is 2005 * also set to one, but the irq core ignores it for this case. 2006 * 2007 * If only one interrupt is available or 'write_queue' == 0, combine 2008 * write and read queues. 2009 * 2010 * If 'write_queues' > 0, ensure it leaves room for at least one read 2011 * queue. 2012 */ 2013 if (!nrirqs) { 2014 nrirqs = 1; 2015 nr_read_queues = 0; 2016 } else if (nrirqs == 1 || !nr_write_queues) { 2017 nr_read_queues = 0; 2018 } else if (nr_write_queues >= nrirqs) { 2019 nr_read_queues = 1; 2020 } else { 2021 nr_read_queues = nrirqs - nr_write_queues; 2022 } 2023 2024 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2025 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2026 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2027 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2028 affd->nr_sets = nr_read_queues ? 2 : 1; 2029 } 2030 2031 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2032 { 2033 struct pci_dev *pdev = to_pci_dev(dev->dev); 2034 struct irq_affinity affd = { 2035 .pre_vectors = 1, 2036 .calc_sets = nvme_calc_irq_sets, 2037 .priv = dev, 2038 }; 2039 unsigned int irq_queues, this_p_queues; 2040 2041 /* 2042 * Poll queues don't need interrupts, but we need at least one IO 2043 * queue left over for non-polled IO. 2044 */ 2045 this_p_queues = dev->nr_poll_queues; 2046 if (this_p_queues >= nr_io_queues) { 2047 this_p_queues = nr_io_queues - 1; 2048 irq_queues = 1; 2049 } else { 2050 irq_queues = nr_io_queues - this_p_queues + 1; 2051 } 2052 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2053 2054 /* Initialize for the single interrupt case */ 2055 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2056 dev->io_queues[HCTX_TYPE_READ] = 0; 2057 2058 /* 2059 * Some Apple controllers require all queues to use the 2060 * first vector. 2061 */ 2062 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2063 irq_queues = 1; 2064 2065 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2066 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2067 } 2068 2069 static void nvme_disable_io_queues(struct nvme_dev *dev) 2070 { 2071 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2072 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2073 } 2074 2075 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2076 { 2077 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2078 } 2079 2080 static int nvme_setup_io_queues(struct nvme_dev *dev) 2081 { 2082 struct nvme_queue *adminq = &dev->queues[0]; 2083 struct pci_dev *pdev = to_pci_dev(dev->dev); 2084 unsigned int nr_io_queues; 2085 unsigned long size; 2086 int result; 2087 2088 /* 2089 * Sample the module parameters once at reset time so that we have 2090 * stable values to work with. 2091 */ 2092 dev->nr_write_queues = write_queues; 2093 dev->nr_poll_queues = poll_queues; 2094 2095 /* 2096 * If tags are shared with admin queue (Apple bug), then 2097 * make sure we only use one IO queue. 2098 */ 2099 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2100 nr_io_queues = 1; 2101 else 2102 nr_io_queues = min(nvme_max_io_queues(dev), 2103 dev->nr_allocated_queues - 1); 2104 2105 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2106 if (result < 0) 2107 return result; 2108 2109 if (nr_io_queues == 0) 2110 return 0; 2111 2112 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2113 2114 if (dev->cmb_use_sqes) { 2115 result = nvme_cmb_qdepth(dev, nr_io_queues, 2116 sizeof(struct nvme_command)); 2117 if (result > 0) 2118 dev->q_depth = result; 2119 else 2120 dev->cmb_use_sqes = false; 2121 } 2122 2123 do { 2124 size = db_bar_size(dev, nr_io_queues); 2125 result = nvme_remap_bar(dev, size); 2126 if (!result) 2127 break; 2128 if (!--nr_io_queues) 2129 return -ENOMEM; 2130 } while (1); 2131 adminq->q_db = dev->dbs; 2132 2133 retry: 2134 /* Deregister the admin queue's interrupt */ 2135 pci_free_irq(pdev, 0, adminq); 2136 2137 /* 2138 * If we enable msix early due to not intx, disable it again before 2139 * setting up the full range we need. 2140 */ 2141 pci_free_irq_vectors(pdev); 2142 2143 result = nvme_setup_irqs(dev, nr_io_queues); 2144 if (result <= 0) 2145 return -EIO; 2146 2147 dev->num_vecs = result; 2148 result = max(result - 1, 1); 2149 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2150 2151 /* 2152 * Should investigate if there's a performance win from allocating 2153 * more queues than interrupt vectors; it might allow the submission 2154 * path to scale better, even if the receive path is limited by the 2155 * number of interrupts. 2156 */ 2157 result = queue_request_irq(adminq); 2158 if (result) 2159 return result; 2160 set_bit(NVMEQ_ENABLED, &adminq->flags); 2161 2162 result = nvme_create_io_queues(dev); 2163 if (result || dev->online_queues < 2) 2164 return result; 2165 2166 if (dev->online_queues - 1 < dev->max_qid) { 2167 nr_io_queues = dev->online_queues - 1; 2168 nvme_disable_io_queues(dev); 2169 nvme_suspend_io_queues(dev); 2170 goto retry; 2171 } 2172 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2173 dev->io_queues[HCTX_TYPE_DEFAULT], 2174 dev->io_queues[HCTX_TYPE_READ], 2175 dev->io_queues[HCTX_TYPE_POLL]); 2176 return 0; 2177 } 2178 2179 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2180 { 2181 struct nvme_queue *nvmeq = req->end_io_data; 2182 2183 blk_mq_free_request(req); 2184 complete(&nvmeq->delete_done); 2185 } 2186 2187 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2188 { 2189 struct nvme_queue *nvmeq = req->end_io_data; 2190 2191 if (error) 2192 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2193 2194 nvme_del_queue_end(req, error); 2195 } 2196 2197 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2198 { 2199 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2200 struct request *req; 2201 struct nvme_command cmd; 2202 2203 memset(&cmd, 0, sizeof(cmd)); 2204 cmd.delete_queue.opcode = opcode; 2205 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2206 2207 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2208 if (IS_ERR(req)) 2209 return PTR_ERR(req); 2210 2211 req->timeout = ADMIN_TIMEOUT; 2212 req->end_io_data = nvmeq; 2213 2214 init_completion(&nvmeq->delete_done); 2215 blk_execute_rq_nowait(q, NULL, req, false, 2216 opcode == nvme_admin_delete_cq ? 2217 nvme_del_cq_end : nvme_del_queue_end); 2218 return 0; 2219 } 2220 2221 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2222 { 2223 int nr_queues = dev->online_queues - 1, sent = 0; 2224 unsigned long timeout; 2225 2226 retry: 2227 timeout = ADMIN_TIMEOUT; 2228 while (nr_queues > 0) { 2229 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2230 break; 2231 nr_queues--; 2232 sent++; 2233 } 2234 while (sent) { 2235 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2236 2237 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2238 timeout); 2239 if (timeout == 0) 2240 return false; 2241 2242 sent--; 2243 if (nr_queues) 2244 goto retry; 2245 } 2246 return true; 2247 } 2248 2249 static void nvme_dev_add(struct nvme_dev *dev) 2250 { 2251 int ret; 2252 2253 if (!dev->ctrl.tagset) { 2254 dev->tagset.ops = &nvme_mq_ops; 2255 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2256 dev->tagset.nr_maps = 2; /* default + read */ 2257 if (dev->io_queues[HCTX_TYPE_POLL]) 2258 dev->tagset.nr_maps++; 2259 dev->tagset.timeout = NVME_IO_TIMEOUT; 2260 dev->tagset.numa_node = dev_to_node(dev->dev); 2261 dev->tagset.queue_depth = 2262 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2263 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2264 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2265 dev->tagset.driver_data = dev; 2266 2267 /* 2268 * Some Apple controllers requires tags to be unique 2269 * across admin and IO queue, so reserve the first 32 2270 * tags of the IO queue. 2271 */ 2272 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2273 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2274 2275 ret = blk_mq_alloc_tag_set(&dev->tagset); 2276 if (ret) { 2277 dev_warn(dev->ctrl.device, 2278 "IO queues tagset allocation failed %d\n", ret); 2279 return; 2280 } 2281 dev->ctrl.tagset = &dev->tagset; 2282 } else { 2283 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2284 2285 /* Free previously allocated queues that are no longer usable */ 2286 nvme_free_queues(dev, dev->online_queues); 2287 } 2288 2289 nvme_dbbuf_set(dev); 2290 } 2291 2292 static int nvme_pci_enable(struct nvme_dev *dev) 2293 { 2294 int result = -ENOMEM; 2295 struct pci_dev *pdev = to_pci_dev(dev->dev); 2296 2297 if (pci_enable_device_mem(pdev)) 2298 return result; 2299 2300 pci_set_master(pdev); 2301 2302 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2303 goto disable; 2304 2305 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2306 result = -ENODEV; 2307 goto disable; 2308 } 2309 2310 /* 2311 * Some devices and/or platforms don't advertise or work with INTx 2312 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2313 * adjust this later. 2314 */ 2315 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2316 if (result < 0) 2317 return result; 2318 2319 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2320 2321 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2322 io_queue_depth); 2323 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2324 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2325 dev->dbs = dev->bar + 4096; 2326 2327 /* 2328 * Some Apple controllers require a non-standard SQE size. 2329 * Interestingly they also seem to ignore the CC:IOSQES register 2330 * so we don't bother updating it here. 2331 */ 2332 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2333 dev->io_sqes = 7; 2334 else 2335 dev->io_sqes = NVME_NVM_IOSQES; 2336 2337 /* 2338 * Temporary fix for the Apple controller found in the MacBook8,1 and 2339 * some MacBook7,1 to avoid controller resets and data loss. 2340 */ 2341 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2342 dev->q_depth = 2; 2343 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2344 "set queue depth=%u to work around controller resets\n", 2345 dev->q_depth); 2346 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2347 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2348 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2349 dev->q_depth = 64; 2350 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2351 "set queue depth=%u\n", dev->q_depth); 2352 } 2353 2354 /* 2355 * Controllers with the shared tags quirk need the IO queue to be 2356 * big enough so that we get 32 tags for the admin queue 2357 */ 2358 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2359 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2360 dev->q_depth = NVME_AQ_DEPTH + 2; 2361 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2362 dev->q_depth); 2363 } 2364 2365 2366 nvme_map_cmb(dev); 2367 2368 pci_enable_pcie_error_reporting(pdev); 2369 pci_save_state(pdev); 2370 return 0; 2371 2372 disable: 2373 pci_disable_device(pdev); 2374 return result; 2375 } 2376 2377 static void nvme_dev_unmap(struct nvme_dev *dev) 2378 { 2379 if (dev->bar) 2380 iounmap(dev->bar); 2381 pci_release_mem_regions(to_pci_dev(dev->dev)); 2382 } 2383 2384 static void nvme_pci_disable(struct nvme_dev *dev) 2385 { 2386 struct pci_dev *pdev = to_pci_dev(dev->dev); 2387 2388 pci_free_irq_vectors(pdev); 2389 2390 if (pci_is_enabled(pdev)) { 2391 pci_disable_pcie_error_reporting(pdev); 2392 pci_disable_device(pdev); 2393 } 2394 } 2395 2396 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2397 { 2398 bool dead = true, freeze = false; 2399 struct pci_dev *pdev = to_pci_dev(dev->dev); 2400 2401 mutex_lock(&dev->shutdown_lock); 2402 if (pci_is_enabled(pdev)) { 2403 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2404 2405 if (dev->ctrl.state == NVME_CTRL_LIVE || 2406 dev->ctrl.state == NVME_CTRL_RESETTING) { 2407 freeze = true; 2408 nvme_start_freeze(&dev->ctrl); 2409 } 2410 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2411 pdev->error_state != pci_channel_io_normal); 2412 } 2413 2414 /* 2415 * Give the controller a chance to complete all entered requests if 2416 * doing a safe shutdown. 2417 */ 2418 if (!dead && shutdown && freeze) 2419 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2420 2421 nvme_stop_queues(&dev->ctrl); 2422 2423 if (!dead && dev->ctrl.queue_count > 0) { 2424 nvme_disable_io_queues(dev); 2425 nvme_disable_admin_queue(dev, shutdown); 2426 } 2427 nvme_suspend_io_queues(dev); 2428 nvme_suspend_queue(&dev->queues[0]); 2429 nvme_pci_disable(dev); 2430 nvme_reap_pending_cqes(dev); 2431 2432 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2433 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2434 blk_mq_tagset_wait_completed_request(&dev->tagset); 2435 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2436 2437 /* 2438 * The driver will not be starting up queues again if shutting down so 2439 * must flush all entered requests to their failed completion to avoid 2440 * deadlocking blk-mq hot-cpu notifier. 2441 */ 2442 if (shutdown) { 2443 nvme_start_queues(&dev->ctrl); 2444 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2445 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2446 } 2447 mutex_unlock(&dev->shutdown_lock); 2448 } 2449 2450 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2451 { 2452 if (!nvme_wait_reset(&dev->ctrl)) 2453 return -EBUSY; 2454 nvme_dev_disable(dev, shutdown); 2455 return 0; 2456 } 2457 2458 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2459 { 2460 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2461 PAGE_SIZE, PAGE_SIZE, 0); 2462 if (!dev->prp_page_pool) 2463 return -ENOMEM; 2464 2465 /* Optimisation for I/Os between 4k and 128k */ 2466 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2467 256, 256, 0); 2468 if (!dev->prp_small_pool) { 2469 dma_pool_destroy(dev->prp_page_pool); 2470 return -ENOMEM; 2471 } 2472 return 0; 2473 } 2474 2475 static void nvme_release_prp_pools(struct nvme_dev *dev) 2476 { 2477 dma_pool_destroy(dev->prp_page_pool); 2478 dma_pool_destroy(dev->prp_small_pool); 2479 } 2480 2481 static void nvme_free_tagset(struct nvme_dev *dev) 2482 { 2483 if (dev->tagset.tags) 2484 blk_mq_free_tag_set(&dev->tagset); 2485 dev->ctrl.tagset = NULL; 2486 } 2487 2488 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2489 { 2490 struct nvme_dev *dev = to_nvme_dev(ctrl); 2491 2492 nvme_dbbuf_dma_free(dev); 2493 nvme_free_tagset(dev); 2494 if (dev->ctrl.admin_q) 2495 blk_put_queue(dev->ctrl.admin_q); 2496 free_opal_dev(dev->ctrl.opal_dev); 2497 mempool_destroy(dev->iod_mempool); 2498 put_device(dev->dev); 2499 kfree(dev->queues); 2500 kfree(dev); 2501 } 2502 2503 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2504 { 2505 /* 2506 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2507 * may be holding this pci_dev's device lock. 2508 */ 2509 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2510 nvme_get_ctrl(&dev->ctrl); 2511 nvme_dev_disable(dev, false); 2512 nvme_kill_queues(&dev->ctrl); 2513 if (!queue_work(nvme_wq, &dev->remove_work)) 2514 nvme_put_ctrl(&dev->ctrl); 2515 } 2516 2517 static void nvme_reset_work(struct work_struct *work) 2518 { 2519 struct nvme_dev *dev = 2520 container_of(work, struct nvme_dev, ctrl.reset_work); 2521 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2522 int result; 2523 2524 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2525 result = -ENODEV; 2526 goto out; 2527 } 2528 2529 /* 2530 * If we're called to reset a live controller first shut it down before 2531 * moving on. 2532 */ 2533 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2534 nvme_dev_disable(dev, false); 2535 nvme_sync_queues(&dev->ctrl); 2536 2537 mutex_lock(&dev->shutdown_lock); 2538 result = nvme_pci_enable(dev); 2539 if (result) 2540 goto out_unlock; 2541 2542 result = nvme_pci_configure_admin_queue(dev); 2543 if (result) 2544 goto out_unlock; 2545 2546 result = nvme_alloc_admin_tags(dev); 2547 if (result) 2548 goto out_unlock; 2549 2550 /* 2551 * Limit the max command size to prevent iod->sg allocations going 2552 * over a single page. 2553 */ 2554 dev->ctrl.max_hw_sectors = min_t(u32, 2555 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2556 dev->ctrl.max_segments = NVME_MAX_SEGS; 2557 2558 /* 2559 * Don't limit the IOMMU merged segment size. 2560 */ 2561 dma_set_max_seg_size(dev->dev, 0xffffffff); 2562 2563 mutex_unlock(&dev->shutdown_lock); 2564 2565 /* 2566 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2567 * initializing procedure here. 2568 */ 2569 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2570 dev_warn(dev->ctrl.device, 2571 "failed to mark controller CONNECTING\n"); 2572 result = -EBUSY; 2573 goto out; 2574 } 2575 2576 /* 2577 * We do not support an SGL for metadata (yet), so we are limited to a 2578 * single integrity segment for the separate metadata pointer. 2579 */ 2580 dev->ctrl.max_integrity_segments = 1; 2581 2582 result = nvme_init_identify(&dev->ctrl); 2583 if (result) 2584 goto out; 2585 2586 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2587 if (!dev->ctrl.opal_dev) 2588 dev->ctrl.opal_dev = 2589 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2590 else if (was_suspend) 2591 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2592 } else { 2593 free_opal_dev(dev->ctrl.opal_dev); 2594 dev->ctrl.opal_dev = NULL; 2595 } 2596 2597 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2598 result = nvme_dbbuf_dma_alloc(dev); 2599 if (result) 2600 dev_warn(dev->dev, 2601 "unable to allocate dma for dbbuf\n"); 2602 } 2603 2604 if (dev->ctrl.hmpre) { 2605 result = nvme_setup_host_mem(dev); 2606 if (result < 0) 2607 goto out; 2608 } 2609 2610 result = nvme_setup_io_queues(dev); 2611 if (result) 2612 goto out; 2613 2614 /* 2615 * Keep the controller around but remove all namespaces if we don't have 2616 * any working I/O queue. 2617 */ 2618 if (dev->online_queues < 2) { 2619 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2620 nvme_kill_queues(&dev->ctrl); 2621 nvme_remove_namespaces(&dev->ctrl); 2622 nvme_free_tagset(dev); 2623 } else { 2624 nvme_start_queues(&dev->ctrl); 2625 nvme_wait_freeze(&dev->ctrl); 2626 nvme_dev_add(dev); 2627 nvme_unfreeze(&dev->ctrl); 2628 } 2629 2630 /* 2631 * If only admin queue live, keep it to do further investigation or 2632 * recovery. 2633 */ 2634 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2635 dev_warn(dev->ctrl.device, 2636 "failed to mark controller live state\n"); 2637 result = -ENODEV; 2638 goto out; 2639 } 2640 2641 nvme_start_ctrl(&dev->ctrl); 2642 return; 2643 2644 out_unlock: 2645 mutex_unlock(&dev->shutdown_lock); 2646 out: 2647 if (result) 2648 dev_warn(dev->ctrl.device, 2649 "Removing after probe failure status: %d\n", result); 2650 nvme_remove_dead_ctrl(dev); 2651 } 2652 2653 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2654 { 2655 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2656 struct pci_dev *pdev = to_pci_dev(dev->dev); 2657 2658 if (pci_get_drvdata(pdev)) 2659 device_release_driver(&pdev->dev); 2660 nvme_put_ctrl(&dev->ctrl); 2661 } 2662 2663 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2664 { 2665 *val = readl(to_nvme_dev(ctrl)->bar + off); 2666 return 0; 2667 } 2668 2669 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2670 { 2671 writel(val, to_nvme_dev(ctrl)->bar + off); 2672 return 0; 2673 } 2674 2675 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2676 { 2677 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2678 return 0; 2679 } 2680 2681 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2682 { 2683 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2684 2685 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2686 } 2687 2688 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2689 .name = "pcie", 2690 .module = THIS_MODULE, 2691 .flags = NVME_F_METADATA_SUPPORTED | 2692 NVME_F_PCI_P2PDMA, 2693 .reg_read32 = nvme_pci_reg_read32, 2694 .reg_write32 = nvme_pci_reg_write32, 2695 .reg_read64 = nvme_pci_reg_read64, 2696 .free_ctrl = nvme_pci_free_ctrl, 2697 .submit_async_event = nvme_pci_submit_async_event, 2698 .get_address = nvme_pci_get_address, 2699 }; 2700 2701 static int nvme_dev_map(struct nvme_dev *dev) 2702 { 2703 struct pci_dev *pdev = to_pci_dev(dev->dev); 2704 2705 if (pci_request_mem_regions(pdev, "nvme")) 2706 return -ENODEV; 2707 2708 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2709 goto release; 2710 2711 return 0; 2712 release: 2713 pci_release_mem_regions(pdev); 2714 return -ENODEV; 2715 } 2716 2717 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2718 { 2719 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2720 /* 2721 * Several Samsung devices seem to drop off the PCIe bus 2722 * randomly when APST is on and uses the deepest sleep state. 2723 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2724 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2725 * 950 PRO 256GB", but it seems to be restricted to two Dell 2726 * laptops. 2727 */ 2728 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2729 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2730 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2731 return NVME_QUIRK_NO_DEEPEST_PS; 2732 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2733 /* 2734 * Samsung SSD 960 EVO drops off the PCIe bus after system 2735 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2736 * within few minutes after bootup on a Coffee Lake board - 2737 * ASUS PRIME Z370-A 2738 */ 2739 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2740 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2741 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2742 return NVME_QUIRK_NO_APST; 2743 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2744 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2745 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2746 /* 2747 * Forcing to use host managed nvme power settings for 2748 * lowest idle power with quick resume latency on 2749 * Samsung and Toshiba SSDs based on suspend behavior 2750 * on Coffee Lake board for LENOVO C640 2751 */ 2752 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2753 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2754 return NVME_QUIRK_SIMPLE_SUSPEND; 2755 } 2756 2757 return 0; 2758 } 2759 2760 static void nvme_async_probe(void *data, async_cookie_t cookie) 2761 { 2762 struct nvme_dev *dev = data; 2763 2764 flush_work(&dev->ctrl.reset_work); 2765 flush_work(&dev->ctrl.scan_work); 2766 nvme_put_ctrl(&dev->ctrl); 2767 } 2768 2769 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2770 { 2771 int node, result = -ENOMEM; 2772 struct nvme_dev *dev; 2773 unsigned long quirks = id->driver_data; 2774 size_t alloc_size; 2775 2776 node = dev_to_node(&pdev->dev); 2777 if (node == NUMA_NO_NODE) 2778 set_dev_node(&pdev->dev, first_memory_node); 2779 2780 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2781 if (!dev) 2782 return -ENOMEM; 2783 2784 dev->nr_write_queues = write_queues; 2785 dev->nr_poll_queues = poll_queues; 2786 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 2787 dev->queues = kcalloc_node(dev->nr_allocated_queues, 2788 sizeof(struct nvme_queue), GFP_KERNEL, node); 2789 if (!dev->queues) 2790 goto free; 2791 2792 dev->dev = get_device(&pdev->dev); 2793 pci_set_drvdata(pdev, dev); 2794 2795 result = nvme_dev_map(dev); 2796 if (result) 2797 goto put_pci; 2798 2799 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2800 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2801 mutex_init(&dev->shutdown_lock); 2802 2803 result = nvme_setup_prp_pools(dev); 2804 if (result) 2805 goto unmap; 2806 2807 quirks |= check_vendor_combination_bug(pdev); 2808 2809 /* 2810 * Double check that our mempool alloc size will cover the biggest 2811 * command we support. 2812 */ 2813 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2814 NVME_MAX_SEGS, true); 2815 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2816 2817 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2818 mempool_kfree, 2819 (void *) alloc_size, 2820 GFP_KERNEL, node); 2821 if (!dev->iod_mempool) { 2822 result = -ENOMEM; 2823 goto release_pools; 2824 } 2825 2826 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2827 quirks); 2828 if (result) 2829 goto release_mempool; 2830 2831 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2832 2833 nvme_reset_ctrl(&dev->ctrl); 2834 async_schedule(nvme_async_probe, dev); 2835 2836 return 0; 2837 2838 release_mempool: 2839 mempool_destroy(dev->iod_mempool); 2840 release_pools: 2841 nvme_release_prp_pools(dev); 2842 unmap: 2843 nvme_dev_unmap(dev); 2844 put_pci: 2845 put_device(dev->dev); 2846 free: 2847 kfree(dev->queues); 2848 kfree(dev); 2849 return result; 2850 } 2851 2852 static void nvme_reset_prepare(struct pci_dev *pdev) 2853 { 2854 struct nvme_dev *dev = pci_get_drvdata(pdev); 2855 2856 /* 2857 * We don't need to check the return value from waiting for the reset 2858 * state as pci_dev device lock is held, making it impossible to race 2859 * with ->remove(). 2860 */ 2861 nvme_disable_prepare_reset(dev, false); 2862 nvme_sync_queues(&dev->ctrl); 2863 } 2864 2865 static void nvme_reset_done(struct pci_dev *pdev) 2866 { 2867 struct nvme_dev *dev = pci_get_drvdata(pdev); 2868 2869 if (!nvme_try_sched_reset(&dev->ctrl)) 2870 flush_work(&dev->ctrl.reset_work); 2871 } 2872 2873 static void nvme_shutdown(struct pci_dev *pdev) 2874 { 2875 struct nvme_dev *dev = pci_get_drvdata(pdev); 2876 nvme_disable_prepare_reset(dev, true); 2877 } 2878 2879 /* 2880 * The driver's remove may be called on a device in a partially initialized 2881 * state. This function must not have any dependencies on the device state in 2882 * order to proceed. 2883 */ 2884 static void nvme_remove(struct pci_dev *pdev) 2885 { 2886 struct nvme_dev *dev = pci_get_drvdata(pdev); 2887 2888 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2889 pci_set_drvdata(pdev, NULL); 2890 2891 if (!pci_device_is_present(pdev)) { 2892 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2893 nvme_dev_disable(dev, true); 2894 nvme_dev_remove_admin(dev); 2895 } 2896 2897 flush_work(&dev->ctrl.reset_work); 2898 nvme_stop_ctrl(&dev->ctrl); 2899 nvme_remove_namespaces(&dev->ctrl); 2900 nvme_dev_disable(dev, true); 2901 nvme_release_cmb(dev); 2902 nvme_free_host_mem(dev); 2903 nvme_dev_remove_admin(dev); 2904 nvme_free_queues(dev, 0); 2905 nvme_release_prp_pools(dev); 2906 nvme_dev_unmap(dev); 2907 nvme_uninit_ctrl(&dev->ctrl); 2908 } 2909 2910 #ifdef CONFIG_PM_SLEEP 2911 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2912 { 2913 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2914 } 2915 2916 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2917 { 2918 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2919 } 2920 2921 static int nvme_resume(struct device *dev) 2922 { 2923 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2924 struct nvme_ctrl *ctrl = &ndev->ctrl; 2925 2926 if (ndev->last_ps == U32_MAX || 2927 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2928 return nvme_try_sched_reset(&ndev->ctrl); 2929 return 0; 2930 } 2931 2932 static int nvme_suspend(struct device *dev) 2933 { 2934 struct pci_dev *pdev = to_pci_dev(dev); 2935 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2936 struct nvme_ctrl *ctrl = &ndev->ctrl; 2937 int ret = -EBUSY; 2938 2939 ndev->last_ps = U32_MAX; 2940 2941 /* 2942 * The platform does not remove power for a kernel managed suspend so 2943 * use host managed nvme power settings for lowest idle power if 2944 * possible. This should have quicker resume latency than a full device 2945 * shutdown. But if the firmware is involved after the suspend or the 2946 * device does not support any non-default power states, shut down the 2947 * device fully. 2948 * 2949 * If ASPM is not enabled for the device, shut down the device and allow 2950 * the PCI bus layer to put it into D3 in order to take the PCIe link 2951 * down, so as to allow the platform to achieve its minimum low-power 2952 * state (which may not be possible if the link is up). 2953 * 2954 * If a host memory buffer is enabled, shut down the device as the NVMe 2955 * specification allows the device to access the host memory buffer in 2956 * host DRAM from all power states, but hosts will fail access to DRAM 2957 * during S3. 2958 */ 2959 if (pm_suspend_via_firmware() || !ctrl->npss || 2960 !pcie_aspm_enabled(pdev) || 2961 ndev->nr_host_mem_descs || 2962 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2963 return nvme_disable_prepare_reset(ndev, true); 2964 2965 nvme_start_freeze(ctrl); 2966 nvme_wait_freeze(ctrl); 2967 nvme_sync_queues(ctrl); 2968 2969 if (ctrl->state != NVME_CTRL_LIVE) 2970 goto unfreeze; 2971 2972 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2973 if (ret < 0) 2974 goto unfreeze; 2975 2976 /* 2977 * A saved state prevents pci pm from generically controlling the 2978 * device's power. If we're using protocol specific settings, we don't 2979 * want pci interfering. 2980 */ 2981 pci_save_state(pdev); 2982 2983 ret = nvme_set_power_state(ctrl, ctrl->npss); 2984 if (ret < 0) 2985 goto unfreeze; 2986 2987 if (ret) { 2988 /* discard the saved state */ 2989 pci_load_saved_state(pdev, NULL); 2990 2991 /* 2992 * Clearing npss forces a controller reset on resume. The 2993 * correct value will be rediscovered then. 2994 */ 2995 ret = nvme_disable_prepare_reset(ndev, true); 2996 ctrl->npss = 0; 2997 } 2998 unfreeze: 2999 nvme_unfreeze(ctrl); 3000 return ret; 3001 } 3002 3003 static int nvme_simple_suspend(struct device *dev) 3004 { 3005 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3006 return nvme_disable_prepare_reset(ndev, true); 3007 } 3008 3009 static int nvme_simple_resume(struct device *dev) 3010 { 3011 struct pci_dev *pdev = to_pci_dev(dev); 3012 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3013 3014 return nvme_try_sched_reset(&ndev->ctrl); 3015 } 3016 3017 static const struct dev_pm_ops nvme_dev_pm_ops = { 3018 .suspend = nvme_suspend, 3019 .resume = nvme_resume, 3020 .freeze = nvme_simple_suspend, 3021 .thaw = nvme_simple_resume, 3022 .poweroff = nvme_simple_suspend, 3023 .restore = nvme_simple_resume, 3024 }; 3025 #endif /* CONFIG_PM_SLEEP */ 3026 3027 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3028 pci_channel_state_t state) 3029 { 3030 struct nvme_dev *dev = pci_get_drvdata(pdev); 3031 3032 /* 3033 * A frozen channel requires a reset. When detected, this method will 3034 * shutdown the controller to quiesce. The controller will be restarted 3035 * after the slot reset through driver's slot_reset callback. 3036 */ 3037 switch (state) { 3038 case pci_channel_io_normal: 3039 return PCI_ERS_RESULT_CAN_RECOVER; 3040 case pci_channel_io_frozen: 3041 dev_warn(dev->ctrl.device, 3042 "frozen state error detected, reset controller\n"); 3043 nvme_dev_disable(dev, false); 3044 return PCI_ERS_RESULT_NEED_RESET; 3045 case pci_channel_io_perm_failure: 3046 dev_warn(dev->ctrl.device, 3047 "failure state error detected, request disconnect\n"); 3048 return PCI_ERS_RESULT_DISCONNECT; 3049 } 3050 return PCI_ERS_RESULT_NEED_RESET; 3051 } 3052 3053 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3054 { 3055 struct nvme_dev *dev = pci_get_drvdata(pdev); 3056 3057 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3058 pci_restore_state(pdev); 3059 nvme_reset_ctrl(&dev->ctrl); 3060 return PCI_ERS_RESULT_RECOVERED; 3061 } 3062 3063 static void nvme_error_resume(struct pci_dev *pdev) 3064 { 3065 struct nvme_dev *dev = pci_get_drvdata(pdev); 3066 3067 flush_work(&dev->ctrl.reset_work); 3068 } 3069 3070 static const struct pci_error_handlers nvme_err_handler = { 3071 .error_detected = nvme_error_detected, 3072 .slot_reset = nvme_slot_reset, 3073 .resume = nvme_error_resume, 3074 .reset_prepare = nvme_reset_prepare, 3075 .reset_done = nvme_reset_done, 3076 }; 3077 3078 static const struct pci_device_id nvme_id_table[] = { 3079 { PCI_VDEVICE(INTEL, 0x0953), 3080 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3081 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3082 { PCI_VDEVICE(INTEL, 0x0a53), 3083 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3084 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3085 { PCI_VDEVICE(INTEL, 0x0a54), 3086 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3087 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3088 { PCI_VDEVICE(INTEL, 0x0a55), 3089 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3090 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3091 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3092 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3093 NVME_QUIRK_MEDIUM_PRIO_SQ | 3094 NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 3095 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3096 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3097 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3098 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3099 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3100 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3101 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3102 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3103 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3104 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3105 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3106 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3107 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3108 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3109 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3110 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3111 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3112 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3113 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3114 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3115 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3116 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3117 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3118 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3119 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3120 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3121 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3122 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3123 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3124 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3125 .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3126 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3127 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3128 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3129 NVME_QUIRK_128_BYTES_SQES | 3130 NVME_QUIRK_SHARED_TAGS }, 3131 { 0, } 3132 }; 3133 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3134 3135 static struct pci_driver nvme_driver = { 3136 .name = "nvme", 3137 .id_table = nvme_id_table, 3138 .probe = nvme_probe, 3139 .remove = nvme_remove, 3140 .shutdown = nvme_shutdown, 3141 #ifdef CONFIG_PM_SLEEP 3142 .driver = { 3143 .pm = &nvme_dev_pm_ops, 3144 }, 3145 #endif 3146 .sriov_configure = pci_sriov_configure_simple, 3147 .err_handler = &nvme_err_handler, 3148 }; 3149 3150 static int __init nvme_init(void) 3151 { 3152 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3153 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3154 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3155 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3156 3157 return pci_register_driver(&nvme_driver); 3158 } 3159 3160 static void __exit nvme_exit(void) 3161 { 3162 pci_unregister_driver(&nvme_driver); 3163 flush_workqueue(nvme_wq); 3164 } 3165 3166 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3167 MODULE_LICENSE("GPL"); 3168 MODULE_VERSION("1.0"); 3169 module_init(nvme_init); 3170 module_exit(nvme_exit); 3171