1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/bitops.h> 16 #include <linux/blkdev.h> 17 #include <linux/blk-mq.h> 18 #include <linux/cpu.h> 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/fs.h> 22 #include <linux/genhd.h> 23 #include <linux/hdreg.h> 24 #include <linux/idr.h> 25 #include <linux/init.h> 26 #include <linux/interrupt.h> 27 #include <linux/io.h> 28 #include <linux/kdev_t.h> 29 #include <linux/kthread.h> 30 #include <linux/kernel.h> 31 #include <linux/mm.h> 32 #include <linux/module.h> 33 #include <linux/moduleparam.h> 34 #include <linux/mutex.h> 35 #include <linux/pci.h> 36 #include <linux/poison.h> 37 #include <linux/ptrace.h> 38 #include <linux/sched.h> 39 #include <linux/slab.h> 40 #include <linux/t10-pi.h> 41 #include <linux/types.h> 42 #include <linux/io-64-nonatomic-lo-hi.h> 43 #include <asm/unaligned.h> 44 45 #include "nvme.h" 46 47 #define NVME_Q_DEPTH 1024 48 #define NVME_AQ_DEPTH 256 49 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 50 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 51 52 unsigned char admin_timeout = 60; 53 module_param(admin_timeout, byte, 0644); 54 MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands"); 55 56 unsigned char nvme_io_timeout = 30; 57 module_param_named(io_timeout, nvme_io_timeout, byte, 0644); 58 MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O"); 59 60 unsigned char shutdown_timeout = 5; 61 module_param(shutdown_timeout, byte, 0644); 62 MODULE_PARM_DESC(shutdown_timeout, "timeout in seconds for controller shutdown"); 63 64 static int use_threaded_interrupts; 65 module_param(use_threaded_interrupts, int, 0); 66 67 static bool use_cmb_sqes = true; 68 module_param(use_cmb_sqes, bool, 0644); 69 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 70 71 static LIST_HEAD(dev_list); 72 static struct task_struct *nvme_thread; 73 static struct workqueue_struct *nvme_workq; 74 static wait_queue_head_t nvme_kthread_wait; 75 76 struct nvme_dev; 77 struct nvme_queue; 78 struct nvme_iod; 79 80 static int __nvme_reset(struct nvme_dev *dev); 81 static int nvme_reset(struct nvme_dev *dev); 82 static void nvme_process_cq(struct nvme_queue *nvmeq); 83 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod); 84 static void nvme_dead_ctrl(struct nvme_dev *dev); 85 86 struct async_cmd_info { 87 struct kthread_work work; 88 struct kthread_worker *worker; 89 struct request *req; 90 u32 result; 91 int status; 92 void *ctx; 93 }; 94 95 /* 96 * Represents an NVM Express device. Each nvme_dev is a PCI function. 97 */ 98 struct nvme_dev { 99 struct list_head node; 100 struct nvme_queue **queues; 101 struct blk_mq_tag_set tagset; 102 struct blk_mq_tag_set admin_tagset; 103 u32 __iomem *dbs; 104 struct device *dev; 105 struct dma_pool *prp_page_pool; 106 struct dma_pool *prp_small_pool; 107 unsigned queue_count; 108 unsigned online_queues; 109 unsigned max_qid; 110 int q_depth; 111 u32 db_stride; 112 struct msix_entry *entry; 113 void __iomem *bar; 114 struct work_struct reset_work; 115 struct work_struct probe_work; 116 struct work_struct scan_work; 117 struct mutex shutdown_lock; 118 bool subsystem; 119 void __iomem *cmb; 120 dma_addr_t cmb_dma_addr; 121 u64 cmb_size; 122 u32 cmbsz; 123 124 struct nvme_ctrl ctrl; 125 }; 126 127 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 128 { 129 return container_of(ctrl, struct nvme_dev, ctrl); 130 } 131 132 /* 133 * An NVM Express queue. Each device has at least two (one for admin 134 * commands and one for I/O commands). 135 */ 136 struct nvme_queue { 137 struct device *q_dmadev; 138 struct nvme_dev *dev; 139 char irqname[24]; /* nvme4294967295-65535\0 */ 140 spinlock_t q_lock; 141 struct nvme_command *sq_cmds; 142 struct nvme_command __iomem *sq_cmds_io; 143 volatile struct nvme_completion *cqes; 144 struct blk_mq_tags **tags; 145 dma_addr_t sq_dma_addr; 146 dma_addr_t cq_dma_addr; 147 u32 __iomem *q_db; 148 u16 q_depth; 149 s16 cq_vector; 150 u16 sq_head; 151 u16 sq_tail; 152 u16 cq_head; 153 u16 qid; 154 u8 cq_phase; 155 u8 cqe_seen; 156 struct async_cmd_info cmdinfo; 157 }; 158 159 /* 160 * The nvme_iod describes the data in an I/O, including the list of PRP 161 * entries. You can't see it in this data structure because C doesn't let 162 * me express that. Use nvme_alloc_iod to ensure there's enough space 163 * allocated to store the PRP list. 164 */ 165 struct nvme_iod { 166 unsigned long private; /* For the use of the submitter of the I/O */ 167 int npages; /* In the PRP list. 0 means small pool in use */ 168 int offset; /* Of PRP list */ 169 int nents; /* Used in scatterlist */ 170 int length; /* Of data, in bytes */ 171 dma_addr_t first_dma; 172 struct scatterlist meta_sg[1]; /* metadata requires single contiguous buffer */ 173 struct scatterlist sg[0]; 174 }; 175 176 /* 177 * Check we didin't inadvertently grow the command struct 178 */ 179 static inline void _nvme_check_size(void) 180 { 181 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 182 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 183 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 184 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 185 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 186 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 187 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 188 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 189 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); 190 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); 191 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 192 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 193 } 194 195 typedef void (*nvme_completion_fn)(struct nvme_queue *, void *, 196 struct nvme_completion *); 197 198 struct nvme_cmd_info { 199 nvme_completion_fn fn; 200 void *ctx; 201 int aborted; 202 struct nvme_queue *nvmeq; 203 struct nvme_iod iod[0]; 204 }; 205 206 /* 207 * Max size of iod being embedded in the request payload 208 */ 209 #define NVME_INT_PAGES 2 210 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 211 #define NVME_INT_MASK 0x01 212 213 /* 214 * Will slightly overestimate the number of pages needed. This is OK 215 * as it only leads to a small amount of wasted memory for the lifetime of 216 * the I/O. 217 */ 218 static int nvme_npages(unsigned size, struct nvme_dev *dev) 219 { 220 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 221 dev->ctrl.page_size); 222 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 223 } 224 225 static unsigned int nvme_cmd_size(struct nvme_dev *dev) 226 { 227 unsigned int ret = sizeof(struct nvme_cmd_info); 228 229 ret += sizeof(struct nvme_iod); 230 ret += sizeof(__le64 *) * nvme_npages(NVME_INT_BYTES(dev), dev); 231 ret += sizeof(struct scatterlist) * NVME_INT_PAGES; 232 233 return ret; 234 } 235 236 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 237 unsigned int hctx_idx) 238 { 239 struct nvme_dev *dev = data; 240 struct nvme_queue *nvmeq = dev->queues[0]; 241 242 WARN_ON(hctx_idx != 0); 243 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 244 WARN_ON(nvmeq->tags); 245 246 hctx->driver_data = nvmeq; 247 nvmeq->tags = &dev->admin_tagset.tags[0]; 248 return 0; 249 } 250 251 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 252 { 253 struct nvme_queue *nvmeq = hctx->driver_data; 254 255 nvmeq->tags = NULL; 256 } 257 258 static int nvme_admin_init_request(void *data, struct request *req, 259 unsigned int hctx_idx, unsigned int rq_idx, 260 unsigned int numa_node) 261 { 262 struct nvme_dev *dev = data; 263 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 264 struct nvme_queue *nvmeq = dev->queues[0]; 265 266 BUG_ON(!nvmeq); 267 cmd->nvmeq = nvmeq; 268 return 0; 269 } 270 271 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 272 unsigned int hctx_idx) 273 { 274 struct nvme_dev *dev = data; 275 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 276 277 if (!nvmeq->tags) 278 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 279 280 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 281 hctx->driver_data = nvmeq; 282 return 0; 283 } 284 285 static int nvme_init_request(void *data, struct request *req, 286 unsigned int hctx_idx, unsigned int rq_idx, 287 unsigned int numa_node) 288 { 289 struct nvme_dev *dev = data; 290 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 291 struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 292 293 BUG_ON(!nvmeq); 294 cmd->nvmeq = nvmeq; 295 return 0; 296 } 297 298 static void nvme_set_info(struct nvme_cmd_info *cmd, void *ctx, 299 nvme_completion_fn handler) 300 { 301 cmd->fn = handler; 302 cmd->ctx = ctx; 303 cmd->aborted = 0; 304 blk_mq_start_request(blk_mq_rq_from_pdu(cmd)); 305 } 306 307 static void *iod_get_private(struct nvme_iod *iod) 308 { 309 return (void *) (iod->private & ~0x1UL); 310 } 311 312 /* 313 * If bit 0 is set, the iod is embedded in the request payload. 314 */ 315 static bool iod_should_kfree(struct nvme_iod *iod) 316 { 317 return (iod->private & NVME_INT_MASK) == 0; 318 } 319 320 /* Special values must be less than 0x1000 */ 321 #define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA) 322 #define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE) 323 #define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE) 324 #define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE) 325 326 static void special_completion(struct nvme_queue *nvmeq, void *ctx, 327 struct nvme_completion *cqe) 328 { 329 if (ctx == CMD_CTX_CANCELLED) 330 return; 331 if (ctx == CMD_CTX_COMPLETED) { 332 dev_warn(nvmeq->q_dmadev, 333 "completed id %d twice on queue %d\n", 334 cqe->command_id, le16_to_cpup(&cqe->sq_id)); 335 return; 336 } 337 if (ctx == CMD_CTX_INVALID) { 338 dev_warn(nvmeq->q_dmadev, 339 "invalid id %d completed on queue %d\n", 340 cqe->command_id, le16_to_cpup(&cqe->sq_id)); 341 return; 342 } 343 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx); 344 } 345 346 static void *cancel_cmd_info(struct nvme_cmd_info *cmd, nvme_completion_fn *fn) 347 { 348 void *ctx; 349 350 if (fn) 351 *fn = cmd->fn; 352 ctx = cmd->ctx; 353 cmd->fn = special_completion; 354 cmd->ctx = CMD_CTX_CANCELLED; 355 return ctx; 356 } 357 358 static void async_req_completion(struct nvme_queue *nvmeq, void *ctx, 359 struct nvme_completion *cqe) 360 { 361 u32 result = le32_to_cpup(&cqe->result); 362 u16 status = le16_to_cpup(&cqe->status) >> 1; 363 364 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ) 365 ++nvmeq->dev->ctrl.event_limit; 366 if (status != NVME_SC_SUCCESS) 367 return; 368 369 switch (result & 0xff07) { 370 case NVME_AER_NOTICE_NS_CHANGED: 371 dev_info(nvmeq->q_dmadev, "rescanning\n"); 372 schedule_work(&nvmeq->dev->scan_work); 373 default: 374 dev_warn(nvmeq->q_dmadev, "async event result %08x\n", result); 375 } 376 } 377 378 static void abort_completion(struct nvme_queue *nvmeq, void *ctx, 379 struct nvme_completion *cqe) 380 { 381 struct request *req = ctx; 382 383 u16 status = le16_to_cpup(&cqe->status) >> 1; 384 u32 result = le32_to_cpup(&cqe->result); 385 386 blk_mq_free_request(req); 387 388 dev_warn(nvmeq->q_dmadev, "Abort status:%x result:%x", status, result); 389 ++nvmeq->dev->ctrl.abort_limit; 390 } 391 392 static void async_completion(struct nvme_queue *nvmeq, void *ctx, 393 struct nvme_completion *cqe) 394 { 395 struct async_cmd_info *cmdinfo = ctx; 396 cmdinfo->result = le32_to_cpup(&cqe->result); 397 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1; 398 queue_kthread_work(cmdinfo->worker, &cmdinfo->work); 399 blk_mq_free_request(cmdinfo->req); 400 } 401 402 static inline struct nvme_cmd_info *get_cmd_from_tag(struct nvme_queue *nvmeq, 403 unsigned int tag) 404 { 405 struct request *req = blk_mq_tag_to_rq(*nvmeq->tags, tag); 406 407 return blk_mq_rq_to_pdu(req); 408 } 409 410 /* 411 * Called with local interrupts disabled and the q_lock held. May not sleep. 412 */ 413 static void *nvme_finish_cmd(struct nvme_queue *nvmeq, int tag, 414 nvme_completion_fn *fn) 415 { 416 struct nvme_cmd_info *cmd = get_cmd_from_tag(nvmeq, tag); 417 void *ctx; 418 if (tag >= nvmeq->q_depth) { 419 *fn = special_completion; 420 return CMD_CTX_INVALID; 421 } 422 if (fn) 423 *fn = cmd->fn; 424 ctx = cmd->ctx; 425 cmd->fn = special_completion; 426 cmd->ctx = CMD_CTX_COMPLETED; 427 return ctx; 428 } 429 430 /** 431 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 432 * @nvmeq: The queue to use 433 * @cmd: The command to send 434 * 435 * Safe to use from interrupt context 436 */ 437 static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 438 struct nvme_command *cmd) 439 { 440 u16 tail = nvmeq->sq_tail; 441 442 if (nvmeq->sq_cmds_io) 443 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 444 else 445 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 446 447 if (++tail == nvmeq->q_depth) 448 tail = 0; 449 writel(tail, nvmeq->q_db); 450 nvmeq->sq_tail = tail; 451 } 452 453 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 454 { 455 unsigned long flags; 456 spin_lock_irqsave(&nvmeq->q_lock, flags); 457 __nvme_submit_cmd(nvmeq, cmd); 458 spin_unlock_irqrestore(&nvmeq->q_lock, flags); 459 } 460 461 static __le64 **iod_list(struct nvme_iod *iod) 462 { 463 return ((void *)iod) + iod->offset; 464 } 465 466 static inline void iod_init(struct nvme_iod *iod, unsigned nbytes, 467 unsigned nseg, unsigned long private) 468 { 469 iod->private = private; 470 iod->offset = offsetof(struct nvme_iod, sg[nseg]); 471 iod->npages = -1; 472 iod->length = nbytes; 473 iod->nents = 0; 474 } 475 476 static struct nvme_iod * 477 __nvme_alloc_iod(unsigned nseg, unsigned bytes, struct nvme_dev *dev, 478 unsigned long priv, gfp_t gfp) 479 { 480 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) + 481 sizeof(__le64 *) * nvme_npages(bytes, dev) + 482 sizeof(struct scatterlist) * nseg, gfp); 483 484 if (iod) 485 iod_init(iod, bytes, nseg, priv); 486 487 return iod; 488 } 489 490 static struct nvme_iod *nvme_alloc_iod(struct request *rq, struct nvme_dev *dev, 491 gfp_t gfp) 492 { 493 unsigned size = !(rq->cmd_flags & REQ_DISCARD) ? blk_rq_bytes(rq) : 494 sizeof(struct nvme_dsm_range); 495 struct nvme_iod *iod; 496 497 if (rq->nr_phys_segments <= NVME_INT_PAGES && 498 size <= NVME_INT_BYTES(dev)) { 499 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(rq); 500 501 iod = cmd->iod; 502 iod_init(iod, size, rq->nr_phys_segments, 503 (unsigned long) rq | NVME_INT_MASK); 504 return iod; 505 } 506 507 return __nvme_alloc_iod(rq->nr_phys_segments, size, dev, 508 (unsigned long) rq, gfp); 509 } 510 511 static void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod) 512 { 513 const int last_prp = dev->ctrl.page_size / 8 - 1; 514 int i; 515 __le64 **list = iod_list(iod); 516 dma_addr_t prp_dma = iod->first_dma; 517 518 if (iod->npages == 0) 519 dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 520 for (i = 0; i < iod->npages; i++) { 521 __le64 *prp_list = list[i]; 522 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 523 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 524 prp_dma = next_prp_dma; 525 } 526 527 if (iod_should_kfree(iod)) 528 kfree(iod); 529 } 530 531 #ifdef CONFIG_BLK_DEV_INTEGRITY 532 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 533 { 534 if (be32_to_cpu(pi->ref_tag) == v) 535 pi->ref_tag = cpu_to_be32(p); 536 } 537 538 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 539 { 540 if (be32_to_cpu(pi->ref_tag) == p) 541 pi->ref_tag = cpu_to_be32(v); 542 } 543 544 /** 545 * nvme_dif_remap - remaps ref tags to bip seed and physical lba 546 * 547 * The virtual start sector is the one that was originally submitted by the 548 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 549 * start sector may be different. Remap protection information to match the 550 * physical LBA on writes, and back to the original seed on reads. 551 * 552 * Type 0 and 3 do not have a ref tag, so no remapping required. 553 */ 554 static void nvme_dif_remap(struct request *req, 555 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 556 { 557 struct nvme_ns *ns = req->rq_disk->private_data; 558 struct bio_integrity_payload *bip; 559 struct t10_pi_tuple *pi; 560 void *p, *pmap; 561 u32 i, nlb, ts, phys, virt; 562 563 if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 564 return; 565 566 bip = bio_integrity(req->bio); 567 if (!bip) 568 return; 569 570 pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 571 572 p = pmap; 573 virt = bip_get_seed(bip); 574 phys = nvme_block_nr(ns, blk_rq_pos(req)); 575 nlb = (blk_rq_bytes(req) >> ns->lba_shift); 576 ts = ns->disk->queue->integrity.tuple_size; 577 578 for (i = 0; i < nlb; i++, virt++, phys++) { 579 pi = (struct t10_pi_tuple *)p; 580 dif_swap(phys, virt, pi); 581 p += ts; 582 } 583 kunmap_atomic(pmap); 584 } 585 #else /* CONFIG_BLK_DEV_INTEGRITY */ 586 static void nvme_dif_remap(struct request *req, 587 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 588 { 589 } 590 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 591 { 592 } 593 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 594 { 595 } 596 #endif 597 598 static void req_completion(struct nvme_queue *nvmeq, void *ctx, 599 struct nvme_completion *cqe) 600 { 601 struct nvme_iod *iod = ctx; 602 struct request *req = iod_get_private(iod); 603 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); 604 u16 status = le16_to_cpup(&cqe->status) >> 1; 605 int error = 0; 606 607 if (unlikely(status)) { 608 if (!(status & NVME_SC_DNR || blk_noretry_request(req)) 609 && (jiffies - req->start_time) < req->timeout) { 610 unsigned long flags; 611 612 nvme_unmap_data(nvmeq->dev, iod); 613 614 blk_mq_requeue_request(req); 615 spin_lock_irqsave(req->q->queue_lock, flags); 616 if (!blk_queue_stopped(req->q)) 617 blk_mq_kick_requeue_list(req->q); 618 spin_unlock_irqrestore(req->q->queue_lock, flags); 619 return; 620 } 621 622 if (req->cmd_type == REQ_TYPE_DRV_PRIV) { 623 if (cmd_rq->ctx == CMD_CTX_CANCELLED) 624 error = -EINTR; 625 else 626 error = status; 627 } else { 628 error = nvme_error_status(status); 629 } 630 } 631 632 if (req->cmd_type == REQ_TYPE_DRV_PRIV) { 633 u32 result = le32_to_cpup(&cqe->result); 634 req->special = (void *)(uintptr_t)result; 635 } 636 637 if (cmd_rq->aborted) 638 dev_warn(nvmeq->dev->dev, 639 "completing aborted command with status:%04x\n", 640 error); 641 642 nvme_unmap_data(nvmeq->dev, iod); 643 blk_mq_complete_request(req, error); 644 } 645 646 static bool nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, 647 int total_len) 648 { 649 struct dma_pool *pool; 650 int length = total_len; 651 struct scatterlist *sg = iod->sg; 652 int dma_len = sg_dma_len(sg); 653 u64 dma_addr = sg_dma_address(sg); 654 u32 page_size = dev->ctrl.page_size; 655 int offset = dma_addr & (page_size - 1); 656 __le64 *prp_list; 657 __le64 **list = iod_list(iod); 658 dma_addr_t prp_dma; 659 int nprps, i; 660 661 length -= (page_size - offset); 662 if (length <= 0) 663 return true; 664 665 dma_len -= (page_size - offset); 666 if (dma_len) { 667 dma_addr += (page_size - offset); 668 } else { 669 sg = sg_next(sg); 670 dma_addr = sg_dma_address(sg); 671 dma_len = sg_dma_len(sg); 672 } 673 674 if (length <= page_size) { 675 iod->first_dma = dma_addr; 676 return true; 677 } 678 679 nprps = DIV_ROUND_UP(length, page_size); 680 if (nprps <= (256 / 8)) { 681 pool = dev->prp_small_pool; 682 iod->npages = 0; 683 } else { 684 pool = dev->prp_page_pool; 685 iod->npages = 1; 686 } 687 688 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 689 if (!prp_list) { 690 iod->first_dma = dma_addr; 691 iod->npages = -1; 692 return false; 693 } 694 list[0] = prp_list; 695 iod->first_dma = prp_dma; 696 i = 0; 697 for (;;) { 698 if (i == page_size >> 3) { 699 __le64 *old_prp_list = prp_list; 700 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 701 if (!prp_list) 702 return false; 703 list[iod->npages++] = prp_list; 704 prp_list[0] = old_prp_list[i - 1]; 705 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 706 i = 1; 707 } 708 prp_list[i++] = cpu_to_le64(dma_addr); 709 dma_len -= page_size; 710 dma_addr += page_size; 711 length -= page_size; 712 if (length <= 0) 713 break; 714 if (dma_len > 0) 715 continue; 716 BUG_ON(dma_len < 0); 717 sg = sg_next(sg); 718 dma_addr = sg_dma_address(sg); 719 dma_len = sg_dma_len(sg); 720 } 721 722 return true; 723 } 724 725 static int nvme_map_data(struct nvme_dev *dev, struct nvme_iod *iod, 726 struct nvme_command *cmnd) 727 { 728 struct request *req = iod_get_private(iod); 729 struct request_queue *q = req->q; 730 enum dma_data_direction dma_dir = rq_data_dir(req) ? 731 DMA_TO_DEVICE : DMA_FROM_DEVICE; 732 int ret = BLK_MQ_RQ_QUEUE_ERROR; 733 734 sg_init_table(iod->sg, req->nr_phys_segments); 735 iod->nents = blk_rq_map_sg(q, req, iod->sg); 736 if (!iod->nents) 737 goto out; 738 739 ret = BLK_MQ_RQ_QUEUE_BUSY; 740 if (!dma_map_sg(dev->dev, iod->sg, iod->nents, dma_dir)) 741 goto out; 742 743 if (!nvme_setup_prps(dev, iod, blk_rq_bytes(req))) 744 goto out_unmap; 745 746 ret = BLK_MQ_RQ_QUEUE_ERROR; 747 if (blk_integrity_rq(req)) { 748 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 749 goto out_unmap; 750 751 sg_init_table(iod->meta_sg, 1); 752 if (blk_rq_map_integrity_sg(q, req->bio, iod->meta_sg) != 1) 753 goto out_unmap; 754 755 if (rq_data_dir(req)) 756 nvme_dif_remap(req, nvme_dif_prep); 757 758 if (!dma_map_sg(dev->dev, iod->meta_sg, 1, dma_dir)) 759 goto out_unmap; 760 } 761 762 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 763 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma); 764 if (blk_integrity_rq(req)) 765 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(iod->meta_sg)); 766 return BLK_MQ_RQ_QUEUE_OK; 767 768 out_unmap: 769 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 770 out: 771 return ret; 772 } 773 774 static void nvme_unmap_data(struct nvme_dev *dev, struct nvme_iod *iod) 775 { 776 struct request *req = iod_get_private(iod); 777 enum dma_data_direction dma_dir = rq_data_dir(req) ? 778 DMA_TO_DEVICE : DMA_FROM_DEVICE; 779 780 if (iod->nents) { 781 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 782 if (blk_integrity_rq(req)) { 783 if (!rq_data_dir(req)) 784 nvme_dif_remap(req, nvme_dif_complete); 785 dma_unmap_sg(dev->dev, iod->meta_sg, 1, dma_dir); 786 } 787 } 788 789 nvme_free_iod(dev, iod); 790 } 791 792 /* 793 * We reuse the small pool to allocate the 16-byte range here as it is not 794 * worth having a special pool for these or additional cases to handle freeing 795 * the iod. 796 */ 797 static int nvme_setup_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns, 798 struct nvme_iod *iod, struct nvme_command *cmnd) 799 { 800 struct request *req = iod_get_private(iod); 801 struct nvme_dsm_range *range; 802 803 range = dma_pool_alloc(nvmeq->dev->prp_small_pool, GFP_ATOMIC, 804 &iod->first_dma); 805 if (!range) 806 return BLK_MQ_RQ_QUEUE_BUSY; 807 iod_list(iod)[0] = (__le64 *)range; 808 iod->npages = 0; 809 810 range->cattr = cpu_to_le32(0); 811 range->nlb = cpu_to_le32(blk_rq_bytes(req) >> ns->lba_shift); 812 range->slba = cpu_to_le64(nvme_block_nr(ns, blk_rq_pos(req))); 813 814 memset(cmnd, 0, sizeof(*cmnd)); 815 cmnd->dsm.opcode = nvme_cmd_dsm; 816 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id); 817 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma); 818 cmnd->dsm.nr = 0; 819 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD); 820 return BLK_MQ_RQ_QUEUE_OK; 821 } 822 823 /* 824 * NOTE: ns is NULL when called on the admin queue. 825 */ 826 static int nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 827 const struct blk_mq_queue_data *bd) 828 { 829 struct nvme_ns *ns = hctx->queue->queuedata; 830 struct nvme_queue *nvmeq = hctx->driver_data; 831 struct nvme_dev *dev = nvmeq->dev; 832 struct request *req = bd->rq; 833 struct nvme_cmd_info *cmd = blk_mq_rq_to_pdu(req); 834 struct nvme_iod *iod; 835 struct nvme_command cmnd; 836 int ret = BLK_MQ_RQ_QUEUE_OK; 837 838 /* 839 * If formated with metadata, require the block layer provide a buffer 840 * unless this namespace is formated such that the metadata can be 841 * stripped/generated by the controller with PRACT=1. 842 */ 843 if (ns && ns->ms && !blk_integrity_rq(req)) { 844 if (!(ns->pi_type && ns->ms == 8) && 845 req->cmd_type != REQ_TYPE_DRV_PRIV) { 846 blk_mq_complete_request(req, -EFAULT); 847 return BLK_MQ_RQ_QUEUE_OK; 848 } 849 } 850 851 iod = nvme_alloc_iod(req, dev, GFP_ATOMIC); 852 if (!iod) 853 return BLK_MQ_RQ_QUEUE_BUSY; 854 855 if (req->cmd_flags & REQ_DISCARD) { 856 ret = nvme_setup_discard(nvmeq, ns, iod, &cmnd); 857 } else { 858 if (req->cmd_type == REQ_TYPE_DRV_PRIV) 859 memcpy(&cmnd, req->cmd, sizeof(cmnd)); 860 else if (req->cmd_flags & REQ_FLUSH) 861 nvme_setup_flush(ns, &cmnd); 862 else 863 nvme_setup_rw(ns, req, &cmnd); 864 865 if (req->nr_phys_segments) 866 ret = nvme_map_data(dev, iod, &cmnd); 867 } 868 869 if (ret) 870 goto out; 871 872 cmnd.common.command_id = req->tag; 873 nvme_set_info(cmd, iod, req_completion); 874 875 spin_lock_irq(&nvmeq->q_lock); 876 __nvme_submit_cmd(nvmeq, &cmnd); 877 nvme_process_cq(nvmeq); 878 spin_unlock_irq(&nvmeq->q_lock); 879 return BLK_MQ_RQ_QUEUE_OK; 880 out: 881 nvme_free_iod(dev, iod); 882 return ret; 883 } 884 885 static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) 886 { 887 u16 head, phase; 888 889 head = nvmeq->cq_head; 890 phase = nvmeq->cq_phase; 891 892 for (;;) { 893 void *ctx; 894 nvme_completion_fn fn; 895 struct nvme_completion cqe = nvmeq->cqes[head]; 896 if ((le16_to_cpu(cqe.status) & 1) != phase) 897 break; 898 nvmeq->sq_head = le16_to_cpu(cqe.sq_head); 899 if (++head == nvmeq->q_depth) { 900 head = 0; 901 phase = !phase; 902 } 903 if (tag && *tag == cqe.command_id) 904 *tag = -1; 905 ctx = nvme_finish_cmd(nvmeq, cqe.command_id, &fn); 906 fn(nvmeq, ctx, &cqe); 907 } 908 909 /* If the controller ignores the cq head doorbell and continuously 910 * writes to the queue, it is theoretically possible to wrap around 911 * the queue twice and mistakenly return IRQ_NONE. Linux only 912 * requires that 0.1% of your interrupts are handled, so this isn't 913 * a big problem. 914 */ 915 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) 916 return; 917 918 if (likely(nvmeq->cq_vector >= 0)) 919 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 920 nvmeq->cq_head = head; 921 nvmeq->cq_phase = phase; 922 923 nvmeq->cqe_seen = 1; 924 } 925 926 static void nvme_process_cq(struct nvme_queue *nvmeq) 927 { 928 __nvme_process_cq(nvmeq, NULL); 929 } 930 931 static irqreturn_t nvme_irq(int irq, void *data) 932 { 933 irqreturn_t result; 934 struct nvme_queue *nvmeq = data; 935 spin_lock(&nvmeq->q_lock); 936 nvme_process_cq(nvmeq); 937 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 938 nvmeq->cqe_seen = 0; 939 spin_unlock(&nvmeq->q_lock); 940 return result; 941 } 942 943 static irqreturn_t nvme_irq_check(int irq, void *data) 944 { 945 struct nvme_queue *nvmeq = data; 946 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head]; 947 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase) 948 return IRQ_NONE; 949 return IRQ_WAKE_THREAD; 950 } 951 952 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 953 { 954 struct nvme_queue *nvmeq = hctx->driver_data; 955 956 if ((le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 957 nvmeq->cq_phase) { 958 spin_lock_irq(&nvmeq->q_lock); 959 __nvme_process_cq(nvmeq, &tag); 960 spin_unlock_irq(&nvmeq->q_lock); 961 962 if (tag == -1) 963 return 1; 964 } 965 966 return 0; 967 } 968 969 static int nvme_submit_async_admin_req(struct nvme_dev *dev) 970 { 971 struct nvme_queue *nvmeq = dev->queues[0]; 972 struct nvme_command c; 973 struct nvme_cmd_info *cmd_info; 974 struct request *req; 975 976 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 977 BLK_MQ_REQ_NOWAIT | BLK_MQ_REQ_RESERVED); 978 if (IS_ERR(req)) 979 return PTR_ERR(req); 980 981 req->cmd_flags |= REQ_NO_TIMEOUT; 982 cmd_info = blk_mq_rq_to_pdu(req); 983 nvme_set_info(cmd_info, NULL, async_req_completion); 984 985 memset(&c, 0, sizeof(c)); 986 c.common.opcode = nvme_admin_async_event; 987 c.common.command_id = req->tag; 988 989 blk_mq_free_request(req); 990 __nvme_submit_cmd(nvmeq, &c); 991 return 0; 992 } 993 994 static int nvme_submit_admin_async_cmd(struct nvme_dev *dev, 995 struct nvme_command *cmd, 996 struct async_cmd_info *cmdinfo, unsigned timeout) 997 { 998 struct nvme_queue *nvmeq = dev->queues[0]; 999 struct request *req; 1000 struct nvme_cmd_info *cmd_rq; 1001 1002 req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 0); 1003 if (IS_ERR(req)) 1004 return PTR_ERR(req); 1005 1006 req->timeout = timeout; 1007 cmd_rq = blk_mq_rq_to_pdu(req); 1008 cmdinfo->req = req; 1009 nvme_set_info(cmd_rq, cmdinfo, async_completion); 1010 cmdinfo->status = -EINTR; 1011 1012 cmd->common.command_id = req->tag; 1013 1014 nvme_submit_cmd(nvmeq, cmd); 1015 return 0; 1016 } 1017 1018 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1019 { 1020 struct nvme_command c; 1021 1022 memset(&c, 0, sizeof(c)); 1023 c.delete_queue.opcode = opcode; 1024 c.delete_queue.qid = cpu_to_le16(id); 1025 1026 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1027 } 1028 1029 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1030 struct nvme_queue *nvmeq) 1031 { 1032 struct nvme_command c; 1033 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 1034 1035 /* 1036 * Note: we (ab)use the fact the the prp fields survive if no data 1037 * is attached to the request. 1038 */ 1039 memset(&c, 0, sizeof(c)); 1040 c.create_cq.opcode = nvme_admin_create_cq; 1041 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1042 c.create_cq.cqid = cpu_to_le16(qid); 1043 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1044 c.create_cq.cq_flags = cpu_to_le16(flags); 1045 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 1046 1047 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1048 } 1049 1050 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1051 struct nvme_queue *nvmeq) 1052 { 1053 struct nvme_command c; 1054 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM; 1055 1056 /* 1057 * Note: we (ab)use the fact the the prp fields survive if no data 1058 * is attached to the request. 1059 */ 1060 memset(&c, 0, sizeof(c)); 1061 c.create_sq.opcode = nvme_admin_create_sq; 1062 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1063 c.create_sq.sqid = cpu_to_le16(qid); 1064 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1065 c.create_sq.sq_flags = cpu_to_le16(flags); 1066 c.create_sq.cqid = cpu_to_le16(qid); 1067 1068 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1069 } 1070 1071 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1072 { 1073 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1074 } 1075 1076 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1077 { 1078 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1079 } 1080 1081 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1082 { 1083 struct nvme_cmd_info *cmd_rq = blk_mq_rq_to_pdu(req); 1084 struct nvme_queue *nvmeq = cmd_rq->nvmeq; 1085 struct nvme_dev *dev = nvmeq->dev; 1086 struct request *abort_req; 1087 struct nvme_cmd_info *abort_cmd; 1088 struct nvme_command cmd; 1089 1090 /* 1091 * Schedule controller reset if the command was already aborted once 1092 * before and still hasn't been returned to the driver, or if this is 1093 * the admin queue. 1094 */ 1095 if (!nvmeq->qid || cmd_rq->aborted) { 1096 spin_lock_irq(&dev_list_lock); 1097 if (!__nvme_reset(dev)) { 1098 dev_warn(dev->dev, 1099 "I/O %d QID %d timeout, reset controller\n", 1100 req->tag, nvmeq->qid); 1101 } 1102 spin_unlock_irq(&dev_list_lock); 1103 return BLK_EH_RESET_TIMER; 1104 } 1105 1106 if (!dev->ctrl.abort_limit) 1107 return BLK_EH_RESET_TIMER; 1108 1109 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, WRITE, 1110 BLK_MQ_REQ_NOWAIT); 1111 if (IS_ERR(abort_req)) 1112 return BLK_EH_RESET_TIMER; 1113 1114 abort_cmd = blk_mq_rq_to_pdu(abort_req); 1115 nvme_set_info(abort_cmd, abort_req, abort_completion); 1116 1117 memset(&cmd, 0, sizeof(cmd)); 1118 cmd.abort.opcode = nvme_admin_abort_cmd; 1119 cmd.abort.cid = req->tag; 1120 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1121 cmd.abort.command_id = abort_req->tag; 1122 1123 --dev->ctrl.abort_limit; 1124 cmd_rq->aborted = 1; 1125 1126 dev_warn(nvmeq->q_dmadev, "I/O %d QID %d timeout, aborting\n", 1127 req->tag, nvmeq->qid); 1128 nvme_submit_cmd(dev->queues[0], &cmd); 1129 1130 /* 1131 * The aborted req will be completed on receiving the abort req. 1132 * We enable the timer again. If hit twice, it'll cause a device reset, 1133 * as the device then is in a faulty state. 1134 */ 1135 return BLK_EH_RESET_TIMER; 1136 } 1137 1138 static void nvme_cancel_queue_ios(struct request *req, void *data, bool reserved) 1139 { 1140 struct nvme_queue *nvmeq = data; 1141 void *ctx; 1142 nvme_completion_fn fn; 1143 struct nvme_cmd_info *cmd; 1144 struct nvme_completion cqe; 1145 1146 if (!blk_mq_request_started(req)) 1147 return; 1148 1149 cmd = blk_mq_rq_to_pdu(req); 1150 1151 if (cmd->ctx == CMD_CTX_CANCELLED) 1152 return; 1153 1154 if (blk_queue_dying(req->q)) 1155 cqe.status = cpu_to_le16((NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1); 1156 else 1157 cqe.status = cpu_to_le16(NVME_SC_ABORT_REQ << 1); 1158 1159 1160 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", 1161 req->tag, nvmeq->qid); 1162 ctx = cancel_cmd_info(cmd, &fn); 1163 fn(nvmeq, ctx, &cqe); 1164 } 1165 1166 static void nvme_free_queue(struct nvme_queue *nvmeq) 1167 { 1168 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1169 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1170 if (nvmeq->sq_cmds) 1171 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1172 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1173 kfree(nvmeq); 1174 } 1175 1176 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1177 { 1178 int i; 1179 1180 for (i = dev->queue_count - 1; i >= lowest; i--) { 1181 struct nvme_queue *nvmeq = dev->queues[i]; 1182 dev->queue_count--; 1183 dev->queues[i] = NULL; 1184 nvme_free_queue(nvmeq); 1185 } 1186 } 1187 1188 /** 1189 * nvme_suspend_queue - put queue into suspended state 1190 * @nvmeq - queue to suspend 1191 */ 1192 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1193 { 1194 int vector; 1195 1196 spin_lock_irq(&nvmeq->q_lock); 1197 if (nvmeq->cq_vector == -1) { 1198 spin_unlock_irq(&nvmeq->q_lock); 1199 return 1; 1200 } 1201 vector = nvmeq->dev->entry[nvmeq->cq_vector].vector; 1202 nvmeq->dev->online_queues--; 1203 nvmeq->cq_vector = -1; 1204 spin_unlock_irq(&nvmeq->q_lock); 1205 1206 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1207 blk_mq_freeze_queue_start(nvmeq->dev->ctrl.admin_q); 1208 1209 irq_set_affinity_hint(vector, NULL); 1210 free_irq(vector, nvmeq); 1211 1212 return 0; 1213 } 1214 1215 static void nvme_clear_queue(struct nvme_queue *nvmeq) 1216 { 1217 spin_lock_irq(&nvmeq->q_lock); 1218 if (nvmeq->tags && *nvmeq->tags) 1219 blk_mq_all_tag_busy_iter(*nvmeq->tags, nvme_cancel_queue_ios, nvmeq); 1220 spin_unlock_irq(&nvmeq->q_lock); 1221 } 1222 1223 static void nvme_disable_queue(struct nvme_dev *dev, int qid) 1224 { 1225 struct nvme_queue *nvmeq = dev->queues[qid]; 1226 1227 if (!nvmeq) 1228 return; 1229 if (nvme_suspend_queue(nvmeq)) 1230 return; 1231 1232 /* Don't tell the adapter to delete the admin queue. 1233 * Don't tell a removed adapter to delete IO queues. */ 1234 if (qid && readl(dev->bar + NVME_REG_CSTS) != -1) { 1235 adapter_delete_sq(dev, qid); 1236 adapter_delete_cq(dev, qid); 1237 } 1238 1239 spin_lock_irq(&nvmeq->q_lock); 1240 nvme_process_cq(nvmeq); 1241 spin_unlock_irq(&nvmeq->q_lock); 1242 } 1243 1244 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1245 int entry_size) 1246 { 1247 int q_depth = dev->q_depth; 1248 unsigned q_size_aligned = roundup(q_depth * entry_size, 1249 dev->ctrl.page_size); 1250 1251 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1252 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1253 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1254 q_depth = div_u64(mem_per_q, entry_size); 1255 1256 /* 1257 * Ensure the reduced q_depth is above some threshold where it 1258 * would be better to map queues in system memory with the 1259 * original depth 1260 */ 1261 if (q_depth < 64) 1262 return -ENOMEM; 1263 } 1264 1265 return q_depth; 1266 } 1267 1268 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1269 int qid, int depth) 1270 { 1271 if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 1272 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 1273 dev->ctrl.page_size); 1274 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 1275 nvmeq->sq_cmds_io = dev->cmb + offset; 1276 } else { 1277 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1278 &nvmeq->sq_dma_addr, GFP_KERNEL); 1279 if (!nvmeq->sq_cmds) 1280 return -ENOMEM; 1281 } 1282 1283 return 0; 1284 } 1285 1286 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1287 int depth) 1288 { 1289 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq), GFP_KERNEL); 1290 if (!nvmeq) 1291 return NULL; 1292 1293 nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 1294 &nvmeq->cq_dma_addr, GFP_KERNEL); 1295 if (!nvmeq->cqes) 1296 goto free_nvmeq; 1297 1298 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1299 goto free_cqdma; 1300 1301 nvmeq->q_dmadev = dev->dev; 1302 nvmeq->dev = dev; 1303 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d", 1304 dev->ctrl.instance, qid); 1305 spin_lock_init(&nvmeq->q_lock); 1306 nvmeq->cq_head = 0; 1307 nvmeq->cq_phase = 1; 1308 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1309 nvmeq->q_depth = depth; 1310 nvmeq->qid = qid; 1311 nvmeq->cq_vector = -1; 1312 dev->queues[qid] = nvmeq; 1313 1314 /* make sure queue descriptor is set before queue count, for kthread */ 1315 mb(); 1316 dev->queue_count++; 1317 1318 return nvmeq; 1319 1320 free_cqdma: 1321 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1322 nvmeq->cq_dma_addr); 1323 free_nvmeq: 1324 kfree(nvmeq); 1325 return NULL; 1326 } 1327 1328 static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1329 const char *name) 1330 { 1331 if (use_threaded_interrupts) 1332 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector, 1333 nvme_irq_check, nvme_irq, IRQF_SHARED, 1334 name, nvmeq); 1335 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq, 1336 IRQF_SHARED, name, nvmeq); 1337 } 1338 1339 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1340 { 1341 struct nvme_dev *dev = nvmeq->dev; 1342 1343 spin_lock_irq(&nvmeq->q_lock); 1344 nvmeq->sq_tail = 0; 1345 nvmeq->cq_head = 0; 1346 nvmeq->cq_phase = 1; 1347 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1348 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1349 dev->online_queues++; 1350 spin_unlock_irq(&nvmeq->q_lock); 1351 } 1352 1353 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 1354 { 1355 struct nvme_dev *dev = nvmeq->dev; 1356 int result; 1357 1358 nvmeq->cq_vector = qid - 1; 1359 result = adapter_alloc_cq(dev, qid, nvmeq); 1360 if (result < 0) 1361 return result; 1362 1363 result = adapter_alloc_sq(dev, qid, nvmeq); 1364 if (result < 0) 1365 goto release_cq; 1366 1367 result = queue_request_irq(dev, nvmeq, nvmeq->irqname); 1368 if (result < 0) 1369 goto release_sq; 1370 1371 nvme_init_queue(nvmeq, qid); 1372 return result; 1373 1374 release_sq: 1375 adapter_delete_sq(dev, qid); 1376 release_cq: 1377 adapter_delete_cq(dev, qid); 1378 return result; 1379 } 1380 1381 static struct blk_mq_ops nvme_mq_admin_ops = { 1382 .queue_rq = nvme_queue_rq, 1383 .map_queue = blk_mq_map_queue, 1384 .init_hctx = nvme_admin_init_hctx, 1385 .exit_hctx = nvme_admin_exit_hctx, 1386 .init_request = nvme_admin_init_request, 1387 .timeout = nvme_timeout, 1388 }; 1389 1390 static struct blk_mq_ops nvme_mq_ops = { 1391 .queue_rq = nvme_queue_rq, 1392 .map_queue = blk_mq_map_queue, 1393 .init_hctx = nvme_init_hctx, 1394 .init_request = nvme_init_request, 1395 .timeout = nvme_timeout, 1396 .poll = nvme_poll, 1397 }; 1398 1399 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1400 { 1401 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1402 blk_cleanup_queue(dev->ctrl.admin_q); 1403 blk_mq_free_tag_set(&dev->admin_tagset); 1404 } 1405 } 1406 1407 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1408 { 1409 if (!dev->ctrl.admin_q) { 1410 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1411 dev->admin_tagset.nr_hw_queues = 1; 1412 dev->admin_tagset.queue_depth = NVME_AQ_DEPTH - 1; 1413 dev->admin_tagset.reserved_tags = 1; 1414 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1415 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1416 dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1417 dev->admin_tagset.driver_data = dev; 1418 1419 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1420 return -ENOMEM; 1421 1422 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1423 if (IS_ERR(dev->ctrl.admin_q)) { 1424 blk_mq_free_tag_set(&dev->admin_tagset); 1425 return -ENOMEM; 1426 } 1427 if (!blk_get_queue(dev->ctrl.admin_q)) { 1428 nvme_dev_remove_admin(dev); 1429 dev->ctrl.admin_q = NULL; 1430 return -ENODEV; 1431 } 1432 } else 1433 blk_mq_unfreeze_queue(dev->ctrl.admin_q); 1434 1435 return 0; 1436 } 1437 1438 static int nvme_configure_admin_queue(struct nvme_dev *dev) 1439 { 1440 int result; 1441 u32 aqa; 1442 u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1443 struct nvme_queue *nvmeq; 1444 1445 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1) ? 1446 NVME_CAP_NSSRC(cap) : 0; 1447 1448 if (dev->subsystem && 1449 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1450 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1451 1452 result = nvme_disable_ctrl(&dev->ctrl, cap); 1453 if (result < 0) 1454 return result; 1455 1456 nvmeq = dev->queues[0]; 1457 if (!nvmeq) { 1458 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1459 if (!nvmeq) 1460 return -ENOMEM; 1461 } 1462 1463 aqa = nvmeq->q_depth - 1; 1464 aqa |= aqa << 16; 1465 1466 writel(aqa, dev->bar + NVME_REG_AQA); 1467 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1468 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1469 1470 result = nvme_enable_ctrl(&dev->ctrl, cap); 1471 if (result) 1472 goto free_nvmeq; 1473 1474 nvmeq->cq_vector = 0; 1475 result = queue_request_irq(dev, nvmeq, nvmeq->irqname); 1476 if (result) { 1477 nvmeq->cq_vector = -1; 1478 goto free_nvmeq; 1479 } 1480 1481 return result; 1482 1483 free_nvmeq: 1484 nvme_free_queues(dev, 0); 1485 return result; 1486 } 1487 1488 static int nvme_kthread(void *data) 1489 { 1490 struct nvme_dev *dev, *next; 1491 1492 while (!kthread_should_stop()) { 1493 set_current_state(TASK_INTERRUPTIBLE); 1494 spin_lock(&dev_list_lock); 1495 list_for_each_entry_safe(dev, next, &dev_list, node) { 1496 int i; 1497 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1498 1499 if ((dev->subsystem && (csts & NVME_CSTS_NSSRO)) || 1500 csts & NVME_CSTS_CFS) { 1501 if (!__nvme_reset(dev)) { 1502 dev_warn(dev->dev, 1503 "Failed status: %x, reset controller\n", 1504 readl(dev->bar + NVME_REG_CSTS)); 1505 } 1506 continue; 1507 } 1508 for (i = 0; i < dev->queue_count; i++) { 1509 struct nvme_queue *nvmeq = dev->queues[i]; 1510 if (!nvmeq) 1511 continue; 1512 spin_lock_irq(&nvmeq->q_lock); 1513 nvme_process_cq(nvmeq); 1514 1515 while (i == 0 && dev->ctrl.event_limit > 0) { 1516 if (nvme_submit_async_admin_req(dev)) 1517 break; 1518 dev->ctrl.event_limit--; 1519 } 1520 spin_unlock_irq(&nvmeq->q_lock); 1521 } 1522 } 1523 spin_unlock(&dev_list_lock); 1524 schedule_timeout(round_jiffies_relative(HZ)); 1525 } 1526 return 0; 1527 } 1528 1529 static int nvme_create_io_queues(struct nvme_dev *dev) 1530 { 1531 unsigned i; 1532 int ret = 0; 1533 1534 for (i = dev->queue_count; i <= dev->max_qid; i++) { 1535 if (!nvme_alloc_queue(dev, i, dev->q_depth)) { 1536 ret = -ENOMEM; 1537 break; 1538 } 1539 } 1540 1541 for (i = dev->online_queues; i <= dev->queue_count - 1; i++) { 1542 ret = nvme_create_queue(dev->queues[i], i); 1543 if (ret) { 1544 nvme_free_queues(dev, i); 1545 break; 1546 } 1547 } 1548 1549 /* 1550 * Ignore failing Create SQ/CQ commands, we can continue with less 1551 * than the desired aount of queues, and even a controller without 1552 * I/O queues an still be used to issue admin commands. This might 1553 * be useful to upgrade a buggy firmware for example. 1554 */ 1555 return ret >= 0 ? 0 : ret; 1556 } 1557 1558 static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 1559 { 1560 u64 szu, size, offset; 1561 u32 cmbloc; 1562 resource_size_t bar_size; 1563 struct pci_dev *pdev = to_pci_dev(dev->dev); 1564 void __iomem *cmb; 1565 dma_addr_t dma_addr; 1566 1567 if (!use_cmb_sqes) 1568 return NULL; 1569 1570 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1571 if (!(NVME_CMB_SZ(dev->cmbsz))) 1572 return NULL; 1573 1574 cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1575 1576 szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 1577 size = szu * NVME_CMB_SZ(dev->cmbsz); 1578 offset = szu * NVME_CMB_OFST(cmbloc); 1579 bar_size = pci_resource_len(pdev, NVME_CMB_BIR(cmbloc)); 1580 1581 if (offset > bar_size) 1582 return NULL; 1583 1584 /* 1585 * Controllers may support a CMB size larger than their BAR, 1586 * for example, due to being behind a bridge. Reduce the CMB to 1587 * the reported size of the BAR 1588 */ 1589 if (size > bar_size - offset) 1590 size = bar_size - offset; 1591 1592 dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(cmbloc)) + offset; 1593 cmb = ioremap_wc(dma_addr, size); 1594 if (!cmb) 1595 return NULL; 1596 1597 dev->cmb_dma_addr = dma_addr; 1598 dev->cmb_size = size; 1599 return cmb; 1600 } 1601 1602 static inline void nvme_release_cmb(struct nvme_dev *dev) 1603 { 1604 if (dev->cmb) { 1605 iounmap(dev->cmb); 1606 dev->cmb = NULL; 1607 } 1608 } 1609 1610 static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1611 { 1612 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); 1613 } 1614 1615 static int nvme_setup_io_queues(struct nvme_dev *dev) 1616 { 1617 struct nvme_queue *adminq = dev->queues[0]; 1618 struct pci_dev *pdev = to_pci_dev(dev->dev); 1619 int result, i, vecs, nr_io_queues, size; 1620 1621 nr_io_queues = num_possible_cpus(); 1622 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 1623 if (result < 0) 1624 return result; 1625 1626 /* 1627 * Degraded controllers might return an error when setting the queue 1628 * count. We still want to be able to bring them online and offer 1629 * access to the admin queue, as that might be only way to fix them up. 1630 */ 1631 if (result > 0) { 1632 dev_err(dev->dev, "Could not set queue count (%d)\n", result); 1633 nr_io_queues = 0; 1634 result = 0; 1635 } 1636 1637 if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 1638 result = nvme_cmb_qdepth(dev, nr_io_queues, 1639 sizeof(struct nvme_command)); 1640 if (result > 0) 1641 dev->q_depth = result; 1642 else 1643 nvme_release_cmb(dev); 1644 } 1645 1646 size = db_bar_size(dev, nr_io_queues); 1647 if (size > 8192) { 1648 iounmap(dev->bar); 1649 do { 1650 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1651 if (dev->bar) 1652 break; 1653 if (!--nr_io_queues) 1654 return -ENOMEM; 1655 size = db_bar_size(dev, nr_io_queues); 1656 } while (1); 1657 dev->dbs = dev->bar + 4096; 1658 adminq->q_db = dev->dbs; 1659 } 1660 1661 /* Deregister the admin queue's interrupt */ 1662 free_irq(dev->entry[0].vector, adminq); 1663 1664 /* 1665 * If we enable msix early due to not intx, disable it again before 1666 * setting up the full range we need. 1667 */ 1668 if (!pdev->irq) 1669 pci_disable_msix(pdev); 1670 1671 for (i = 0; i < nr_io_queues; i++) 1672 dev->entry[i].entry = i; 1673 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues); 1674 if (vecs < 0) { 1675 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32)); 1676 if (vecs < 0) { 1677 vecs = 1; 1678 } else { 1679 for (i = 0; i < vecs; i++) 1680 dev->entry[i].vector = i + pdev->irq; 1681 } 1682 } 1683 1684 /* 1685 * Should investigate if there's a performance win from allocating 1686 * more queues than interrupt vectors; it might allow the submission 1687 * path to scale better, even if the receive path is limited by the 1688 * number of interrupts. 1689 */ 1690 nr_io_queues = vecs; 1691 dev->max_qid = nr_io_queues; 1692 1693 result = queue_request_irq(dev, adminq, adminq->irqname); 1694 if (result) { 1695 adminq->cq_vector = -1; 1696 goto free_queues; 1697 } 1698 1699 /* Free previously allocated queues that are no longer usable */ 1700 nvme_free_queues(dev, nr_io_queues + 1); 1701 return nvme_create_io_queues(dev); 1702 1703 free_queues: 1704 nvme_free_queues(dev, 1); 1705 return result; 1706 } 1707 1708 static void nvme_set_irq_hints(struct nvme_dev *dev) 1709 { 1710 struct nvme_queue *nvmeq; 1711 int i; 1712 1713 for (i = 0; i < dev->online_queues; i++) { 1714 nvmeq = dev->queues[i]; 1715 1716 if (!nvmeq->tags || !(*nvmeq->tags)) 1717 continue; 1718 1719 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector, 1720 blk_mq_tags_cpumask(*nvmeq->tags)); 1721 } 1722 } 1723 1724 static void nvme_dev_scan(struct work_struct *work) 1725 { 1726 struct nvme_dev *dev = container_of(work, struct nvme_dev, scan_work); 1727 1728 if (!dev->tagset.tags) 1729 return; 1730 nvme_scan_namespaces(&dev->ctrl); 1731 nvme_set_irq_hints(dev); 1732 } 1733 1734 /* 1735 * Return: error value if an error occurred setting up the queues or calling 1736 * Identify Device. 0 if these succeeded, even if adding some of the 1737 * namespaces failed. At the moment, these failures are silent. TBD which 1738 * failures should be reported. 1739 */ 1740 static int nvme_dev_add(struct nvme_dev *dev) 1741 { 1742 if (!dev->ctrl.tagset) { 1743 dev->tagset.ops = &nvme_mq_ops; 1744 dev->tagset.nr_hw_queues = dev->online_queues - 1; 1745 dev->tagset.timeout = NVME_IO_TIMEOUT; 1746 dev->tagset.numa_node = dev_to_node(dev->dev); 1747 dev->tagset.queue_depth = 1748 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 1749 dev->tagset.cmd_size = nvme_cmd_size(dev); 1750 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 1751 dev->tagset.driver_data = dev; 1752 1753 if (blk_mq_alloc_tag_set(&dev->tagset)) 1754 return 0; 1755 dev->ctrl.tagset = &dev->tagset; 1756 } 1757 schedule_work(&dev->scan_work); 1758 return 0; 1759 } 1760 1761 static int nvme_dev_map(struct nvme_dev *dev) 1762 { 1763 u64 cap; 1764 int bars, result = -ENOMEM; 1765 struct pci_dev *pdev = to_pci_dev(dev->dev); 1766 1767 if (pci_enable_device_mem(pdev)) 1768 return result; 1769 1770 dev->entry[0].vector = pdev->irq; 1771 pci_set_master(pdev); 1772 bars = pci_select_bars(pdev, IORESOURCE_MEM); 1773 if (!bars) 1774 goto disable_pci; 1775 1776 if (pci_request_selected_regions(pdev, bars, "nvme")) 1777 goto disable_pci; 1778 1779 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 1780 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 1781 goto disable; 1782 1783 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); 1784 if (!dev->bar) 1785 goto disable; 1786 1787 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 1788 result = -ENODEV; 1789 goto unmap; 1790 } 1791 1792 /* 1793 * Some devices don't advertse INTx interrupts, pre-enable a single 1794 * MSIX vec for setup. We'll adjust this later. 1795 */ 1796 if (!pdev->irq) { 1797 result = pci_enable_msix(pdev, dev->entry, 1); 1798 if (result < 0) 1799 goto unmap; 1800 } 1801 1802 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 1803 1804 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); 1805 dev->db_stride = 1 << NVME_CAP_STRIDE(cap); 1806 dev->dbs = dev->bar + 4096; 1807 if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2)) 1808 dev->cmb = nvme_map_cmb(dev); 1809 1810 return 0; 1811 1812 unmap: 1813 iounmap(dev->bar); 1814 dev->bar = NULL; 1815 disable: 1816 pci_release_regions(pdev); 1817 disable_pci: 1818 pci_disable_device(pdev); 1819 return result; 1820 } 1821 1822 static void nvme_dev_unmap(struct nvme_dev *dev) 1823 { 1824 struct pci_dev *pdev = to_pci_dev(dev->dev); 1825 1826 if (pdev->msi_enabled) 1827 pci_disable_msi(pdev); 1828 else if (pdev->msix_enabled) 1829 pci_disable_msix(pdev); 1830 1831 if (dev->bar) { 1832 iounmap(dev->bar); 1833 dev->bar = NULL; 1834 pci_release_regions(pdev); 1835 } 1836 1837 if (pci_is_enabled(pdev)) 1838 pci_disable_device(pdev); 1839 } 1840 1841 struct nvme_delq_ctx { 1842 struct task_struct *waiter; 1843 struct kthread_worker *worker; 1844 atomic_t refcount; 1845 }; 1846 1847 static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev) 1848 { 1849 dq->waiter = current; 1850 mb(); 1851 1852 for (;;) { 1853 set_current_state(TASK_KILLABLE); 1854 if (!atomic_read(&dq->refcount)) 1855 break; 1856 if (!schedule_timeout(ADMIN_TIMEOUT) || 1857 fatal_signal_pending(current)) { 1858 /* 1859 * Disable the controller first since we can't trust it 1860 * at this point, but leave the admin queue enabled 1861 * until all queue deletion requests are flushed. 1862 * FIXME: This may take a while if there are more h/w 1863 * queues than admin tags. 1864 */ 1865 set_current_state(TASK_RUNNING); 1866 nvme_disable_ctrl(&dev->ctrl, 1867 lo_hi_readq(dev->bar + NVME_REG_CAP)); 1868 nvme_clear_queue(dev->queues[0]); 1869 flush_kthread_worker(dq->worker); 1870 nvme_disable_queue(dev, 0); 1871 return; 1872 } 1873 } 1874 set_current_state(TASK_RUNNING); 1875 } 1876 1877 static void nvme_put_dq(struct nvme_delq_ctx *dq) 1878 { 1879 atomic_dec(&dq->refcount); 1880 if (dq->waiter) 1881 wake_up_process(dq->waiter); 1882 } 1883 1884 static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq) 1885 { 1886 atomic_inc(&dq->refcount); 1887 return dq; 1888 } 1889 1890 static void nvme_del_queue_end(struct nvme_queue *nvmeq) 1891 { 1892 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx; 1893 nvme_put_dq(dq); 1894 1895 spin_lock_irq(&nvmeq->q_lock); 1896 nvme_process_cq(nvmeq); 1897 spin_unlock_irq(&nvmeq->q_lock); 1898 } 1899 1900 static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode, 1901 kthread_work_func_t fn) 1902 { 1903 struct nvme_command c; 1904 1905 memset(&c, 0, sizeof(c)); 1906 c.delete_queue.opcode = opcode; 1907 c.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1908 1909 init_kthread_work(&nvmeq->cmdinfo.work, fn); 1910 return nvme_submit_admin_async_cmd(nvmeq->dev, &c, &nvmeq->cmdinfo, 1911 ADMIN_TIMEOUT); 1912 } 1913 1914 static void nvme_del_cq_work_handler(struct kthread_work *work) 1915 { 1916 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1917 cmdinfo.work); 1918 nvme_del_queue_end(nvmeq); 1919 } 1920 1921 static int nvme_delete_cq(struct nvme_queue *nvmeq) 1922 { 1923 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq, 1924 nvme_del_cq_work_handler); 1925 } 1926 1927 static void nvme_del_sq_work_handler(struct kthread_work *work) 1928 { 1929 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1930 cmdinfo.work); 1931 int status = nvmeq->cmdinfo.status; 1932 1933 if (!status) 1934 status = nvme_delete_cq(nvmeq); 1935 if (status) 1936 nvme_del_queue_end(nvmeq); 1937 } 1938 1939 static int nvme_delete_sq(struct nvme_queue *nvmeq) 1940 { 1941 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq, 1942 nvme_del_sq_work_handler); 1943 } 1944 1945 static void nvme_del_queue_start(struct kthread_work *work) 1946 { 1947 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue, 1948 cmdinfo.work); 1949 if (nvme_delete_sq(nvmeq)) 1950 nvme_del_queue_end(nvmeq); 1951 } 1952 1953 static void nvme_disable_io_queues(struct nvme_dev *dev) 1954 { 1955 int i; 1956 DEFINE_KTHREAD_WORKER_ONSTACK(worker); 1957 struct nvme_delq_ctx dq; 1958 struct task_struct *kworker_task = kthread_run(kthread_worker_fn, 1959 &worker, "nvme%d", dev->ctrl.instance); 1960 1961 if (IS_ERR(kworker_task)) { 1962 dev_err(dev->dev, 1963 "Failed to create queue del task\n"); 1964 for (i = dev->queue_count - 1; i > 0; i--) 1965 nvme_disable_queue(dev, i); 1966 return; 1967 } 1968 1969 dq.waiter = NULL; 1970 atomic_set(&dq.refcount, 0); 1971 dq.worker = &worker; 1972 for (i = dev->queue_count - 1; i > 0; i--) { 1973 struct nvme_queue *nvmeq = dev->queues[i]; 1974 1975 if (nvme_suspend_queue(nvmeq)) 1976 continue; 1977 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq); 1978 nvmeq->cmdinfo.worker = dq.worker; 1979 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start); 1980 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work); 1981 } 1982 nvme_wait_dq(&dq, dev); 1983 kthread_stop(kworker_task); 1984 } 1985 1986 static int nvme_dev_list_add(struct nvme_dev *dev) 1987 { 1988 bool start_thread = false; 1989 1990 spin_lock(&dev_list_lock); 1991 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) { 1992 start_thread = true; 1993 nvme_thread = NULL; 1994 } 1995 list_add(&dev->node, &dev_list); 1996 spin_unlock(&dev_list_lock); 1997 1998 if (start_thread) { 1999 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme"); 2000 wake_up_all(&nvme_kthread_wait); 2001 } else 2002 wait_event_killable(nvme_kthread_wait, nvme_thread); 2003 2004 if (IS_ERR_OR_NULL(nvme_thread)) 2005 return nvme_thread ? PTR_ERR(nvme_thread) : -EINTR; 2006 2007 return 0; 2008 } 2009 2010 /* 2011 * Remove the node from the device list and check 2012 * for whether or not we need to stop the nvme_thread. 2013 */ 2014 static void nvme_dev_list_remove(struct nvme_dev *dev) 2015 { 2016 struct task_struct *tmp = NULL; 2017 2018 spin_lock(&dev_list_lock); 2019 list_del_init(&dev->node); 2020 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) { 2021 tmp = nvme_thread; 2022 nvme_thread = NULL; 2023 } 2024 spin_unlock(&dev_list_lock); 2025 2026 if (tmp) 2027 kthread_stop(tmp); 2028 } 2029 2030 static void nvme_freeze_queues(struct nvme_dev *dev) 2031 { 2032 struct nvme_ns *ns; 2033 2034 list_for_each_entry(ns, &dev->ctrl.namespaces, list) { 2035 blk_mq_freeze_queue_start(ns->queue); 2036 2037 spin_lock_irq(ns->queue->queue_lock); 2038 queue_flag_set(QUEUE_FLAG_STOPPED, ns->queue); 2039 spin_unlock_irq(ns->queue->queue_lock); 2040 2041 blk_mq_cancel_requeue_work(ns->queue); 2042 blk_mq_stop_hw_queues(ns->queue); 2043 } 2044 } 2045 2046 static void nvme_unfreeze_queues(struct nvme_dev *dev) 2047 { 2048 struct nvme_ns *ns; 2049 2050 list_for_each_entry(ns, &dev->ctrl.namespaces, list) { 2051 queue_flag_clear_unlocked(QUEUE_FLAG_STOPPED, ns->queue); 2052 blk_mq_unfreeze_queue(ns->queue); 2053 blk_mq_start_stopped_hw_queues(ns->queue, true); 2054 blk_mq_kick_requeue_list(ns->queue); 2055 } 2056 } 2057 2058 static void nvme_dev_shutdown(struct nvme_dev *dev) 2059 { 2060 int i; 2061 u32 csts = -1; 2062 2063 nvme_dev_list_remove(dev); 2064 2065 mutex_lock(&dev->shutdown_lock); 2066 if (dev->bar) { 2067 nvme_freeze_queues(dev); 2068 csts = readl(dev->bar + NVME_REG_CSTS); 2069 } 2070 if (csts & NVME_CSTS_CFS || !(csts & NVME_CSTS_RDY)) { 2071 for (i = dev->queue_count - 1; i >= 0; i--) { 2072 struct nvme_queue *nvmeq = dev->queues[i]; 2073 nvme_suspend_queue(nvmeq); 2074 } 2075 } else { 2076 nvme_disable_io_queues(dev); 2077 nvme_shutdown_ctrl(&dev->ctrl); 2078 nvme_disable_queue(dev, 0); 2079 } 2080 nvme_dev_unmap(dev); 2081 2082 for (i = dev->queue_count - 1; i >= 0; i--) 2083 nvme_clear_queue(dev->queues[i]); 2084 mutex_unlock(&dev->shutdown_lock); 2085 } 2086 2087 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2088 { 2089 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2090 PAGE_SIZE, PAGE_SIZE, 0); 2091 if (!dev->prp_page_pool) 2092 return -ENOMEM; 2093 2094 /* Optimisation for I/Os between 4k and 128k */ 2095 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2096 256, 256, 0); 2097 if (!dev->prp_small_pool) { 2098 dma_pool_destroy(dev->prp_page_pool); 2099 return -ENOMEM; 2100 } 2101 return 0; 2102 } 2103 2104 static void nvme_release_prp_pools(struct nvme_dev *dev) 2105 { 2106 dma_pool_destroy(dev->prp_page_pool); 2107 dma_pool_destroy(dev->prp_small_pool); 2108 } 2109 2110 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2111 { 2112 struct nvme_dev *dev = to_nvme_dev(ctrl); 2113 2114 put_device(dev->dev); 2115 if (dev->tagset.tags) 2116 blk_mq_free_tag_set(&dev->tagset); 2117 if (dev->ctrl.admin_q) 2118 blk_put_queue(dev->ctrl.admin_q); 2119 kfree(dev->queues); 2120 kfree(dev->entry); 2121 kfree(dev); 2122 } 2123 2124 static void nvme_probe_work(struct work_struct *work) 2125 { 2126 struct nvme_dev *dev = container_of(work, struct nvme_dev, probe_work); 2127 int result; 2128 2129 result = nvme_dev_map(dev); 2130 if (result) 2131 goto out; 2132 2133 result = nvme_configure_admin_queue(dev); 2134 if (result) 2135 goto unmap; 2136 2137 nvme_init_queue(dev->queues[0], 0); 2138 result = nvme_alloc_admin_tags(dev); 2139 if (result) 2140 goto disable; 2141 2142 result = nvme_init_identify(&dev->ctrl); 2143 if (result) 2144 goto free_tags; 2145 2146 result = nvme_setup_io_queues(dev); 2147 if (result) 2148 goto free_tags; 2149 2150 dev->ctrl.event_limit = 1; 2151 2152 result = nvme_dev_list_add(dev); 2153 if (result) 2154 goto remove; 2155 2156 /* 2157 * Keep the controller around but remove all namespaces if we don't have 2158 * any working I/O queue. 2159 */ 2160 if (dev->online_queues < 2) { 2161 dev_warn(dev->dev, "IO queues not created\n"); 2162 nvme_remove_namespaces(&dev->ctrl); 2163 } else { 2164 nvme_unfreeze_queues(dev); 2165 nvme_dev_add(dev); 2166 } 2167 2168 return; 2169 2170 remove: 2171 nvme_dev_list_remove(dev); 2172 free_tags: 2173 nvme_dev_remove_admin(dev); 2174 blk_put_queue(dev->ctrl.admin_q); 2175 dev->ctrl.admin_q = NULL; 2176 dev->queues[0]->tags = NULL; 2177 disable: 2178 nvme_disable_queue(dev, 0); 2179 unmap: 2180 nvme_dev_unmap(dev); 2181 out: 2182 if (!work_busy(&dev->reset_work)) 2183 nvme_dead_ctrl(dev); 2184 } 2185 2186 static int nvme_remove_dead_ctrl(void *arg) 2187 { 2188 struct nvme_dev *dev = (struct nvme_dev *)arg; 2189 struct pci_dev *pdev = to_pci_dev(dev->dev); 2190 2191 if (pci_get_drvdata(pdev)) 2192 pci_stop_and_remove_bus_device_locked(pdev); 2193 nvme_put_ctrl(&dev->ctrl); 2194 return 0; 2195 } 2196 2197 static void nvme_dead_ctrl(struct nvme_dev *dev) 2198 { 2199 dev_warn(dev->dev, "Device failed to resume\n"); 2200 kref_get(&dev->ctrl.kref); 2201 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d", 2202 dev->ctrl.instance))) { 2203 dev_err(dev->dev, 2204 "Failed to start controller remove task\n"); 2205 nvme_put_ctrl(&dev->ctrl); 2206 } 2207 } 2208 2209 static void nvme_reset_work(struct work_struct *ws) 2210 { 2211 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work); 2212 bool in_probe = work_busy(&dev->probe_work); 2213 2214 nvme_dev_shutdown(dev); 2215 2216 /* Synchronize with device probe so that work will see failure status 2217 * and exit gracefully without trying to schedule another reset */ 2218 flush_work(&dev->probe_work); 2219 2220 /* Fail this device if reset occured during probe to avoid 2221 * infinite initialization loops. */ 2222 if (in_probe) { 2223 nvme_dead_ctrl(dev); 2224 return; 2225 } 2226 /* Schedule device resume asynchronously so the reset work is available 2227 * to cleanup errors that may occur during reinitialization */ 2228 schedule_work(&dev->probe_work); 2229 } 2230 2231 static int __nvme_reset(struct nvme_dev *dev) 2232 { 2233 if (work_pending(&dev->reset_work)) 2234 return -EBUSY; 2235 list_del_init(&dev->node); 2236 queue_work(nvme_workq, &dev->reset_work); 2237 return 0; 2238 } 2239 2240 static int nvme_reset(struct nvme_dev *dev) 2241 { 2242 int ret; 2243 2244 if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 2245 return -ENODEV; 2246 2247 spin_lock(&dev_list_lock); 2248 ret = __nvme_reset(dev); 2249 spin_unlock(&dev_list_lock); 2250 2251 if (!ret) { 2252 flush_work(&dev->reset_work); 2253 flush_work(&dev->probe_work); 2254 return 0; 2255 } 2256 2257 return ret; 2258 } 2259 2260 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2261 { 2262 *val = readl(to_nvme_dev(ctrl)->bar + off); 2263 return 0; 2264 } 2265 2266 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2267 { 2268 writel(val, to_nvme_dev(ctrl)->bar + off); 2269 return 0; 2270 } 2271 2272 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2273 { 2274 *val = readq(to_nvme_dev(ctrl)->bar + off); 2275 return 0; 2276 } 2277 2278 static bool nvme_pci_io_incapable(struct nvme_ctrl *ctrl) 2279 { 2280 struct nvme_dev *dev = to_nvme_dev(ctrl); 2281 2282 return !dev->bar || dev->online_queues < 2; 2283 } 2284 2285 static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 2286 { 2287 return nvme_reset(to_nvme_dev(ctrl)); 2288 } 2289 2290 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2291 .reg_read32 = nvme_pci_reg_read32, 2292 .reg_write32 = nvme_pci_reg_write32, 2293 .reg_read64 = nvme_pci_reg_read64, 2294 .io_incapable = nvme_pci_io_incapable, 2295 .reset_ctrl = nvme_pci_reset_ctrl, 2296 .free_ctrl = nvme_pci_free_ctrl, 2297 }; 2298 2299 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2300 { 2301 int node, result = -ENOMEM; 2302 struct nvme_dev *dev; 2303 2304 node = dev_to_node(&pdev->dev); 2305 if (node == NUMA_NO_NODE) 2306 set_dev_node(&pdev->dev, 0); 2307 2308 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2309 if (!dev) 2310 return -ENOMEM; 2311 dev->entry = kzalloc_node(num_possible_cpus() * sizeof(*dev->entry), 2312 GFP_KERNEL, node); 2313 if (!dev->entry) 2314 goto free; 2315 dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 2316 GFP_KERNEL, node); 2317 if (!dev->queues) 2318 goto free; 2319 2320 dev->dev = get_device(&pdev->dev); 2321 pci_set_drvdata(pdev, dev); 2322 2323 INIT_LIST_HEAD(&dev->node); 2324 INIT_WORK(&dev->scan_work, nvme_dev_scan); 2325 INIT_WORK(&dev->probe_work, nvme_probe_work); 2326 INIT_WORK(&dev->reset_work, nvme_reset_work); 2327 mutex_init(&dev->shutdown_lock); 2328 2329 result = nvme_setup_prp_pools(dev); 2330 if (result) 2331 goto put_pci; 2332 2333 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2334 id->driver_data); 2335 if (result) 2336 goto release_pools; 2337 2338 schedule_work(&dev->probe_work); 2339 return 0; 2340 2341 release_pools: 2342 nvme_release_prp_pools(dev); 2343 put_pci: 2344 put_device(dev->dev); 2345 free: 2346 kfree(dev->queues); 2347 kfree(dev->entry); 2348 kfree(dev); 2349 return result; 2350 } 2351 2352 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) 2353 { 2354 struct nvme_dev *dev = pci_get_drvdata(pdev); 2355 2356 if (prepare) 2357 nvme_dev_shutdown(dev); 2358 else 2359 schedule_work(&dev->probe_work); 2360 } 2361 2362 static void nvme_shutdown(struct pci_dev *pdev) 2363 { 2364 struct nvme_dev *dev = pci_get_drvdata(pdev); 2365 nvme_dev_shutdown(dev); 2366 } 2367 2368 static void nvme_remove(struct pci_dev *pdev) 2369 { 2370 struct nvme_dev *dev = pci_get_drvdata(pdev); 2371 2372 spin_lock(&dev_list_lock); 2373 list_del_init(&dev->node); 2374 spin_unlock(&dev_list_lock); 2375 2376 pci_set_drvdata(pdev, NULL); 2377 flush_work(&dev->probe_work); 2378 flush_work(&dev->reset_work); 2379 flush_work(&dev->scan_work); 2380 nvme_remove_namespaces(&dev->ctrl); 2381 nvme_dev_shutdown(dev); 2382 nvme_dev_remove_admin(dev); 2383 nvme_free_queues(dev, 0); 2384 nvme_release_cmb(dev); 2385 nvme_release_prp_pools(dev); 2386 nvme_put_ctrl(&dev->ctrl); 2387 } 2388 2389 /* These functions are yet to be implemented */ 2390 #define nvme_error_detected NULL 2391 #define nvme_dump_registers NULL 2392 #define nvme_link_reset NULL 2393 #define nvme_slot_reset NULL 2394 #define nvme_error_resume NULL 2395 2396 #ifdef CONFIG_PM_SLEEP 2397 static int nvme_suspend(struct device *dev) 2398 { 2399 struct pci_dev *pdev = to_pci_dev(dev); 2400 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2401 2402 nvme_dev_shutdown(ndev); 2403 return 0; 2404 } 2405 2406 static int nvme_resume(struct device *dev) 2407 { 2408 struct pci_dev *pdev = to_pci_dev(dev); 2409 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2410 2411 schedule_work(&ndev->probe_work); 2412 return 0; 2413 } 2414 #endif 2415 2416 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2417 2418 static const struct pci_error_handlers nvme_err_handler = { 2419 .error_detected = nvme_error_detected, 2420 .mmio_enabled = nvme_dump_registers, 2421 .link_reset = nvme_link_reset, 2422 .slot_reset = nvme_slot_reset, 2423 .resume = nvme_error_resume, 2424 .reset_notify = nvme_reset_notify, 2425 }; 2426 2427 /* Move to pci_ids.h later */ 2428 #define PCI_CLASS_STORAGE_EXPRESS 0x010802 2429 2430 static const struct pci_device_id nvme_id_table[] = { 2431 { PCI_VDEVICE(INTEL, 0x0953), 2432 .driver_data = NVME_QUIRK_STRIPE_SIZE, }, 2433 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2434 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2435 { 0, } 2436 }; 2437 MODULE_DEVICE_TABLE(pci, nvme_id_table); 2438 2439 static struct pci_driver nvme_driver = { 2440 .name = "nvme", 2441 .id_table = nvme_id_table, 2442 .probe = nvme_probe, 2443 .remove = nvme_remove, 2444 .shutdown = nvme_shutdown, 2445 .driver = { 2446 .pm = &nvme_dev_pm_ops, 2447 }, 2448 .err_handler = &nvme_err_handler, 2449 }; 2450 2451 static int __init nvme_init(void) 2452 { 2453 int result; 2454 2455 init_waitqueue_head(&nvme_kthread_wait); 2456 2457 nvme_workq = create_singlethread_workqueue("nvme"); 2458 if (!nvme_workq) 2459 return -ENOMEM; 2460 2461 result = nvme_core_init(); 2462 if (result < 0) 2463 goto kill_workq; 2464 2465 result = pci_register_driver(&nvme_driver); 2466 if (result) 2467 goto core_exit; 2468 return 0; 2469 2470 core_exit: 2471 nvme_core_exit(); 2472 kill_workq: 2473 destroy_workqueue(nvme_workq); 2474 return result; 2475 } 2476 2477 static void __exit nvme_exit(void) 2478 { 2479 pci_unregister_driver(&nvme_driver); 2480 nvme_core_exit(); 2481 destroy_workqueue(nvme_workq); 2482 BUG_ON(nvme_thread && !IS_ERR(nvme_thread)); 2483 _nvme_check_size(); 2484 } 2485 2486 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 2487 MODULE_LICENSE("GPL"); 2488 MODULE_VERSION("1.0"); 2489 module_init(nvme_init); 2490 module_exit(nvme_exit); 2491