1 /* 2 * NVM Express device driver 3 * Copyright (c) 2011-2014, Intel Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/async.h> 17 #include <linux/blkdev.h> 18 #include <linux/blk-mq.h> 19 #include <linux/blk-mq-pci.h> 20 #include <linux/dmi.h> 21 #include <linux/init.h> 22 #include <linux/interrupt.h> 23 #include <linux/io.h> 24 #include <linux/mm.h> 25 #include <linux/module.h> 26 #include <linux/mutex.h> 27 #include <linux/once.h> 28 #include <linux/pci.h> 29 #include <linux/t10-pi.h> 30 #include <linux/types.h> 31 #include <linux/io-64-nonatomic-lo-hi.h> 32 #include <linux/sed-opal.h> 33 #include <linux/pci-p2pdma.h> 34 35 #include "trace.h" 36 #include "nvme.h" 37 38 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 39 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 40 41 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 42 43 /* 44 * These can be higher, but we need to ensure that any command doesn't 45 * require an sg allocation that needs more than a page of data. 46 */ 47 #define NVME_MAX_KB_SZ 4096 48 #define NVME_MAX_SEGS 127 49 50 static int use_threaded_interrupts; 51 module_param(use_threaded_interrupts, int, 0); 52 53 static bool use_cmb_sqes = true; 54 module_param(use_cmb_sqes, bool, 0444); 55 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 56 57 static unsigned int max_host_mem_size_mb = 128; 58 module_param(max_host_mem_size_mb, uint, 0444); 59 MODULE_PARM_DESC(max_host_mem_size_mb, 60 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 61 62 static unsigned int sgl_threshold = SZ_32K; 63 module_param(sgl_threshold, uint, 0644); 64 MODULE_PARM_DESC(sgl_threshold, 65 "Use SGLs when average request segment size is larger or equal to " 66 "this size. Use 0 to disable SGLs."); 67 68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69 static const struct kernel_param_ops io_queue_depth_ops = { 70 .set = io_queue_depth_set, 71 .get = param_get_int, 72 }; 73 74 static int io_queue_depth = 1024; 75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 77 78 static int queue_count_set(const char *val, const struct kernel_param *kp); 79 static const struct kernel_param_ops queue_count_ops = { 80 .set = queue_count_set, 81 .get = param_get_int, 82 }; 83 84 static int write_queues; 85 module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 86 MODULE_PARM_DESC(write_queues, 87 "Number of queues to use for writes. If not set, reads and writes " 88 "will share a queue set."); 89 90 static int poll_queues = 0; 91 module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 92 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 93 94 struct nvme_dev; 95 struct nvme_queue; 96 97 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 98 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 99 100 /* 101 * Represents an NVM Express device. Each nvme_dev is a PCI function. 102 */ 103 struct nvme_dev { 104 struct nvme_queue *queues; 105 struct blk_mq_tag_set tagset; 106 struct blk_mq_tag_set admin_tagset; 107 u32 __iomem *dbs; 108 struct device *dev; 109 struct dma_pool *prp_page_pool; 110 struct dma_pool *prp_small_pool; 111 unsigned online_queues; 112 unsigned max_qid; 113 unsigned io_queues[HCTX_MAX_TYPES]; 114 unsigned int num_vecs; 115 int q_depth; 116 u32 db_stride; 117 void __iomem *bar; 118 unsigned long bar_mapped_size; 119 struct work_struct remove_work; 120 struct mutex shutdown_lock; 121 bool subsystem; 122 u64 cmb_size; 123 bool cmb_use_sqes; 124 u32 cmbsz; 125 u32 cmbloc; 126 struct nvme_ctrl ctrl; 127 128 mempool_t *iod_mempool; 129 130 /* shadow doorbell buffer support: */ 131 u32 *dbbuf_dbs; 132 dma_addr_t dbbuf_dbs_dma_addr; 133 u32 *dbbuf_eis; 134 dma_addr_t dbbuf_eis_dma_addr; 135 136 /* host memory buffer support: */ 137 u64 host_mem_size; 138 u32 nr_host_mem_descs; 139 dma_addr_t host_mem_descs_dma; 140 struct nvme_host_mem_buf_desc *host_mem_descs; 141 void **host_mem_desc_bufs; 142 }; 143 144 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 145 { 146 int n = 0, ret; 147 148 ret = kstrtoint(val, 10, &n); 149 if (ret != 0 || n < 2) 150 return -EINVAL; 151 152 return param_set_int(val, kp); 153 } 154 155 static int queue_count_set(const char *val, const struct kernel_param *kp) 156 { 157 int n = 0, ret; 158 159 ret = kstrtoint(val, 10, &n); 160 if (n > num_possible_cpus()) 161 n = num_possible_cpus(); 162 163 return param_set_int(val, kp); 164 } 165 166 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 167 { 168 return qid * 2 * stride; 169 } 170 171 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 172 { 173 return (qid * 2 + 1) * stride; 174 } 175 176 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 177 { 178 return container_of(ctrl, struct nvme_dev, ctrl); 179 } 180 181 /* 182 * An NVM Express queue. Each device has at least two (one for admin 183 * commands and one for I/O commands). 184 */ 185 struct nvme_queue { 186 struct device *q_dmadev; 187 struct nvme_dev *dev; 188 spinlock_t sq_lock; 189 struct nvme_command *sq_cmds; 190 /* only used for poll queues: */ 191 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 192 volatile struct nvme_completion *cqes; 193 struct blk_mq_tags **tags; 194 dma_addr_t sq_dma_addr; 195 dma_addr_t cq_dma_addr; 196 u32 __iomem *q_db; 197 u16 q_depth; 198 s16 cq_vector; 199 u16 sq_tail; 200 u16 last_sq_tail; 201 u16 cq_head; 202 u16 last_cq_head; 203 u16 qid; 204 u8 cq_phase; 205 unsigned long flags; 206 #define NVMEQ_ENABLED 0 207 #define NVMEQ_SQ_CMB 1 208 #define NVMEQ_DELETE_ERROR 2 209 u32 *dbbuf_sq_db; 210 u32 *dbbuf_cq_db; 211 u32 *dbbuf_sq_ei; 212 u32 *dbbuf_cq_ei; 213 struct completion delete_done; 214 }; 215 216 /* 217 * The nvme_iod describes the data in an I/O, including the list of PRP 218 * entries. You can't see it in this data structure because C doesn't let 219 * me express that. Use nvme_init_iod to ensure there's enough space 220 * allocated to store the PRP list. 221 */ 222 struct nvme_iod { 223 struct nvme_request req; 224 struct nvme_queue *nvmeq; 225 bool use_sgl; 226 int aborted; 227 int npages; /* In the PRP list. 0 means small pool in use */ 228 int nents; /* Used in scatterlist */ 229 int length; /* Of data, in bytes */ 230 dma_addr_t first_dma; 231 struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 232 struct scatterlist *sg; 233 struct scatterlist inline_sg[0]; 234 }; 235 236 /* 237 * Check we didin't inadvertently grow the command struct 238 */ 239 static inline void _nvme_check_size(void) 240 { 241 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 242 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 243 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 244 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 245 BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 246 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 247 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 248 BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 249 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 250 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 251 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 252 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 253 BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 254 } 255 256 static unsigned int max_io_queues(void) 257 { 258 return num_possible_cpus() + write_queues + poll_queues; 259 } 260 261 static unsigned int max_queue_count(void) 262 { 263 /* IO queues + admin queue */ 264 return 1 + max_io_queues(); 265 } 266 267 static inline unsigned int nvme_dbbuf_size(u32 stride) 268 { 269 return (max_queue_count() * 8 * stride); 270 } 271 272 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 273 { 274 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 275 276 if (dev->dbbuf_dbs) 277 return 0; 278 279 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 280 &dev->dbbuf_dbs_dma_addr, 281 GFP_KERNEL); 282 if (!dev->dbbuf_dbs) 283 return -ENOMEM; 284 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 285 &dev->dbbuf_eis_dma_addr, 286 GFP_KERNEL); 287 if (!dev->dbbuf_eis) { 288 dma_free_coherent(dev->dev, mem_size, 289 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 290 dev->dbbuf_dbs = NULL; 291 return -ENOMEM; 292 } 293 294 return 0; 295 } 296 297 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 298 { 299 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 300 301 if (dev->dbbuf_dbs) { 302 dma_free_coherent(dev->dev, mem_size, 303 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 304 dev->dbbuf_dbs = NULL; 305 } 306 if (dev->dbbuf_eis) { 307 dma_free_coherent(dev->dev, mem_size, 308 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 309 dev->dbbuf_eis = NULL; 310 } 311 } 312 313 static void nvme_dbbuf_init(struct nvme_dev *dev, 314 struct nvme_queue *nvmeq, int qid) 315 { 316 if (!dev->dbbuf_dbs || !qid) 317 return; 318 319 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 320 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 321 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 322 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 323 } 324 325 static void nvme_dbbuf_set(struct nvme_dev *dev) 326 { 327 struct nvme_command c; 328 329 if (!dev->dbbuf_dbs) 330 return; 331 332 memset(&c, 0, sizeof(c)); 333 c.dbbuf.opcode = nvme_admin_dbbuf; 334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 336 337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 339 /* Free memory and continue on */ 340 nvme_dbbuf_dma_free(dev); 341 } 342 } 343 344 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 345 { 346 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 347 } 348 349 /* Update dbbuf and return true if an MMIO is required */ 350 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 351 volatile u32 *dbbuf_ei) 352 { 353 if (dbbuf_db) { 354 u16 old_value; 355 356 /* 357 * Ensure that the queue is written before updating 358 * the doorbell in memory 359 */ 360 wmb(); 361 362 old_value = *dbbuf_db; 363 *dbbuf_db = value; 364 365 /* 366 * Ensure that the doorbell is updated before reading the event 367 * index from memory. The controller needs to provide similar 368 * ordering to ensure the envent index is updated before reading 369 * the doorbell. 370 */ 371 mb(); 372 373 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 374 return false; 375 } 376 377 return true; 378 } 379 380 /* 381 * Max size of iod being embedded in the request payload 382 */ 383 #define NVME_INT_PAGES 2 384 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 385 386 /* 387 * Will slightly overestimate the number of pages needed. This is OK 388 * as it only leads to a small amount of wasted memory for the lifetime of 389 * the I/O. 390 */ 391 static int nvme_npages(unsigned size, struct nvme_dev *dev) 392 { 393 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 394 dev->ctrl.page_size); 395 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 396 } 397 398 /* 399 * Calculates the number of pages needed for the SGL segments. For example a 4k 400 * page can accommodate 256 SGL descriptors. 401 */ 402 static int nvme_pci_npages_sgl(unsigned int num_seg) 403 { 404 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 405 } 406 407 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 408 unsigned int size, unsigned int nseg, bool use_sgl) 409 { 410 size_t alloc_size; 411 412 if (use_sgl) 413 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 414 else 415 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 416 417 return alloc_size + sizeof(struct scatterlist) * nseg; 418 } 419 420 static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 421 { 422 unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 423 NVME_INT_BYTES(dev), NVME_INT_PAGES, 424 use_sgl); 425 426 return sizeof(struct nvme_iod) + alloc_size; 427 } 428 429 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 430 unsigned int hctx_idx) 431 { 432 struct nvme_dev *dev = data; 433 struct nvme_queue *nvmeq = &dev->queues[0]; 434 435 WARN_ON(hctx_idx != 0); 436 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 437 WARN_ON(nvmeq->tags); 438 439 hctx->driver_data = nvmeq; 440 nvmeq->tags = &dev->admin_tagset.tags[0]; 441 return 0; 442 } 443 444 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 445 { 446 struct nvme_queue *nvmeq = hctx->driver_data; 447 448 nvmeq->tags = NULL; 449 } 450 451 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 452 unsigned int hctx_idx) 453 { 454 struct nvme_dev *dev = data; 455 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 456 457 if (!nvmeq->tags) 458 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 459 460 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 461 hctx->driver_data = nvmeq; 462 return 0; 463 } 464 465 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 466 unsigned int hctx_idx, unsigned int numa_node) 467 { 468 struct nvme_dev *dev = set->driver_data; 469 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 470 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 471 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 472 473 BUG_ON(!nvmeq); 474 iod->nvmeq = nvmeq; 475 476 nvme_req(req)->ctrl = &dev->ctrl; 477 return 0; 478 } 479 480 static int queue_irq_offset(struct nvme_dev *dev) 481 { 482 /* if we have more than 1 vec, admin queue offsets us by 1 */ 483 if (dev->num_vecs > 1) 484 return 1; 485 486 return 0; 487 } 488 489 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 490 { 491 struct nvme_dev *dev = set->driver_data; 492 int i, qoff, offset; 493 494 offset = queue_irq_offset(dev); 495 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 496 struct blk_mq_queue_map *map = &set->map[i]; 497 498 map->nr_queues = dev->io_queues[i]; 499 if (!map->nr_queues) { 500 BUG_ON(i == HCTX_TYPE_DEFAULT); 501 continue; 502 } 503 504 /* 505 * The poll queue(s) doesn't have an IRQ (and hence IRQ 506 * affinity), so use the regular blk-mq cpu mapping 507 */ 508 map->queue_offset = qoff; 509 if (i != HCTX_TYPE_POLL) 510 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 511 else 512 blk_mq_map_queues(map); 513 qoff += map->nr_queues; 514 offset += map->nr_queues; 515 } 516 517 return 0; 518 } 519 520 /* 521 * Write sq tail if we are asked to, or if the next command would wrap. 522 */ 523 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 524 { 525 if (!write_sq) { 526 u16 next_tail = nvmeq->sq_tail + 1; 527 528 if (next_tail == nvmeq->q_depth) 529 next_tail = 0; 530 if (next_tail != nvmeq->last_sq_tail) 531 return; 532 } 533 534 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 535 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 536 writel(nvmeq->sq_tail, nvmeq->q_db); 537 nvmeq->last_sq_tail = nvmeq->sq_tail; 538 } 539 540 /** 541 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 542 * @nvmeq: The queue to use 543 * @cmd: The command to send 544 * @write_sq: whether to write to the SQ doorbell 545 */ 546 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 547 bool write_sq) 548 { 549 spin_lock(&nvmeq->sq_lock); 550 memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 551 if (++nvmeq->sq_tail == nvmeq->q_depth) 552 nvmeq->sq_tail = 0; 553 nvme_write_sq_db(nvmeq, write_sq); 554 spin_unlock(&nvmeq->sq_lock); 555 } 556 557 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 558 { 559 struct nvme_queue *nvmeq = hctx->driver_data; 560 561 spin_lock(&nvmeq->sq_lock); 562 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 563 nvme_write_sq_db(nvmeq, true); 564 spin_unlock(&nvmeq->sq_lock); 565 } 566 567 static void **nvme_pci_iod_list(struct request *req) 568 { 569 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 570 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 571 } 572 573 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 574 { 575 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 576 int nseg = blk_rq_nr_phys_segments(req); 577 unsigned int avg_seg_size; 578 579 if (nseg == 0) 580 return false; 581 582 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 583 584 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 585 return false; 586 if (!iod->nvmeq->qid) 587 return false; 588 if (!sgl_threshold || avg_seg_size < sgl_threshold) 589 return false; 590 return true; 591 } 592 593 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 594 { 595 struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 596 int nseg = blk_rq_nr_phys_segments(rq); 597 unsigned int size = blk_rq_payload_bytes(rq); 598 599 iod->use_sgl = nvme_pci_use_sgls(dev, rq); 600 601 if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 602 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 603 if (!iod->sg) 604 return BLK_STS_RESOURCE; 605 } else { 606 iod->sg = iod->inline_sg; 607 } 608 609 iod->aborted = 0; 610 iod->npages = -1; 611 iod->nents = 0; 612 iod->length = size; 613 614 return BLK_STS_OK; 615 } 616 617 static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 618 { 619 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 620 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 621 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 622 623 int i; 624 625 if (iod->npages == 0) 626 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 627 dma_addr); 628 629 for (i = 0; i < iod->npages; i++) { 630 void *addr = nvme_pci_iod_list(req)[i]; 631 632 if (iod->use_sgl) { 633 struct nvme_sgl_desc *sg_list = addr; 634 635 next_dma_addr = 636 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 637 } else { 638 __le64 *prp_list = addr; 639 640 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 641 } 642 643 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 644 dma_addr = next_dma_addr; 645 } 646 647 if (iod->sg != iod->inline_sg) 648 mempool_free(iod->sg, dev->iod_mempool); 649 } 650 651 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 652 { 653 int i; 654 struct scatterlist *sg; 655 656 for_each_sg(sgl, sg, nents, i) { 657 dma_addr_t phys = sg_phys(sg); 658 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 659 "dma_address:%pad dma_length:%d\n", 660 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 661 sg_dma_len(sg)); 662 } 663 } 664 665 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 666 struct request *req, struct nvme_rw_command *cmnd) 667 { 668 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 669 struct dma_pool *pool; 670 int length = blk_rq_payload_bytes(req); 671 struct scatterlist *sg = iod->sg; 672 int dma_len = sg_dma_len(sg); 673 u64 dma_addr = sg_dma_address(sg); 674 u32 page_size = dev->ctrl.page_size; 675 int offset = dma_addr & (page_size - 1); 676 __le64 *prp_list; 677 void **list = nvme_pci_iod_list(req); 678 dma_addr_t prp_dma; 679 int nprps, i; 680 681 length -= (page_size - offset); 682 if (length <= 0) { 683 iod->first_dma = 0; 684 goto done; 685 } 686 687 dma_len -= (page_size - offset); 688 if (dma_len) { 689 dma_addr += (page_size - offset); 690 } else { 691 sg = sg_next(sg); 692 dma_addr = sg_dma_address(sg); 693 dma_len = sg_dma_len(sg); 694 } 695 696 if (length <= page_size) { 697 iod->first_dma = dma_addr; 698 goto done; 699 } 700 701 nprps = DIV_ROUND_UP(length, page_size); 702 if (nprps <= (256 / 8)) { 703 pool = dev->prp_small_pool; 704 iod->npages = 0; 705 } else { 706 pool = dev->prp_page_pool; 707 iod->npages = 1; 708 } 709 710 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 711 if (!prp_list) { 712 iod->first_dma = dma_addr; 713 iod->npages = -1; 714 return BLK_STS_RESOURCE; 715 } 716 list[0] = prp_list; 717 iod->first_dma = prp_dma; 718 i = 0; 719 for (;;) { 720 if (i == page_size >> 3) { 721 __le64 *old_prp_list = prp_list; 722 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 723 if (!prp_list) 724 return BLK_STS_RESOURCE; 725 list[iod->npages++] = prp_list; 726 prp_list[0] = old_prp_list[i - 1]; 727 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 728 i = 1; 729 } 730 prp_list[i++] = cpu_to_le64(dma_addr); 731 dma_len -= page_size; 732 dma_addr += page_size; 733 length -= page_size; 734 if (length <= 0) 735 break; 736 if (dma_len > 0) 737 continue; 738 if (unlikely(dma_len < 0)) 739 goto bad_sgl; 740 sg = sg_next(sg); 741 dma_addr = sg_dma_address(sg); 742 dma_len = sg_dma_len(sg); 743 } 744 745 done: 746 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 747 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 748 749 return BLK_STS_OK; 750 751 bad_sgl: 752 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 753 "Invalid SGL for payload:%d nents:%d\n", 754 blk_rq_payload_bytes(req), iod->nents); 755 return BLK_STS_IOERR; 756 } 757 758 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 759 struct scatterlist *sg) 760 { 761 sge->addr = cpu_to_le64(sg_dma_address(sg)); 762 sge->length = cpu_to_le32(sg_dma_len(sg)); 763 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 764 } 765 766 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 767 dma_addr_t dma_addr, int entries) 768 { 769 sge->addr = cpu_to_le64(dma_addr); 770 if (entries < SGES_PER_PAGE) { 771 sge->length = cpu_to_le32(entries * sizeof(*sge)); 772 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 773 } else { 774 sge->length = cpu_to_le32(PAGE_SIZE); 775 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 776 } 777 } 778 779 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 780 struct request *req, struct nvme_rw_command *cmd, int entries) 781 { 782 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 783 struct dma_pool *pool; 784 struct nvme_sgl_desc *sg_list; 785 struct scatterlist *sg = iod->sg; 786 dma_addr_t sgl_dma; 787 int i = 0; 788 789 /* setting the transfer type as SGL */ 790 cmd->flags = NVME_CMD_SGL_METABUF; 791 792 if (entries == 1) { 793 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 794 return BLK_STS_OK; 795 } 796 797 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 798 pool = dev->prp_small_pool; 799 iod->npages = 0; 800 } else { 801 pool = dev->prp_page_pool; 802 iod->npages = 1; 803 } 804 805 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 806 if (!sg_list) { 807 iod->npages = -1; 808 return BLK_STS_RESOURCE; 809 } 810 811 nvme_pci_iod_list(req)[0] = sg_list; 812 iod->first_dma = sgl_dma; 813 814 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 815 816 do { 817 if (i == SGES_PER_PAGE) { 818 struct nvme_sgl_desc *old_sg_desc = sg_list; 819 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 820 821 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 822 if (!sg_list) 823 return BLK_STS_RESOURCE; 824 825 i = 0; 826 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 827 sg_list[i++] = *link; 828 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 829 } 830 831 nvme_pci_sgl_set_data(&sg_list[i++], sg); 832 sg = sg_next(sg); 833 } while (--entries > 0); 834 835 return BLK_STS_OK; 836 } 837 838 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 839 struct nvme_command *cmnd) 840 { 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 842 struct request_queue *q = req->q; 843 enum dma_data_direction dma_dir = rq_data_dir(req) ? 844 DMA_TO_DEVICE : DMA_FROM_DEVICE; 845 blk_status_t ret = BLK_STS_IOERR; 846 int nr_mapped; 847 848 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 849 iod->nents = blk_rq_map_sg(q, req, iod->sg); 850 if (!iod->nents) 851 goto out; 852 853 ret = BLK_STS_RESOURCE; 854 855 if (is_pci_p2pdma_page(sg_page(iod->sg))) 856 nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 857 dma_dir); 858 else 859 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 860 dma_dir, DMA_ATTR_NO_WARN); 861 if (!nr_mapped) 862 goto out; 863 864 if (iod->use_sgl) 865 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 866 else 867 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 868 869 if (ret != BLK_STS_OK) 870 goto out_unmap; 871 872 ret = BLK_STS_IOERR; 873 if (blk_integrity_rq(req)) { 874 if (blk_rq_count_integrity_sg(q, req->bio) != 1) 875 goto out_unmap; 876 877 sg_init_table(&iod->meta_sg, 1); 878 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 879 goto out_unmap; 880 881 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 882 goto out_unmap; 883 884 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 885 } 886 887 return BLK_STS_OK; 888 889 out_unmap: 890 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 891 out: 892 return ret; 893 } 894 895 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 896 { 897 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 898 enum dma_data_direction dma_dir = rq_data_dir(req) ? 899 DMA_TO_DEVICE : DMA_FROM_DEVICE; 900 901 if (iod->nents) { 902 /* P2PDMA requests do not need to be unmapped */ 903 if (!is_pci_p2pdma_page(sg_page(iod->sg))) 904 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 905 906 if (blk_integrity_rq(req)) 907 dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 908 } 909 910 nvme_cleanup_cmd(req); 911 nvme_free_iod(dev, req); 912 } 913 914 /* 915 * NOTE: ns is NULL when called on the admin queue. 916 */ 917 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 918 const struct blk_mq_queue_data *bd) 919 { 920 struct nvme_ns *ns = hctx->queue->queuedata; 921 struct nvme_queue *nvmeq = hctx->driver_data; 922 struct nvme_dev *dev = nvmeq->dev; 923 struct request *req = bd->rq; 924 struct nvme_command cmnd; 925 blk_status_t ret; 926 927 /* 928 * We should not need to do this, but we're still using this to 929 * ensure we can drain requests on a dying queue. 930 */ 931 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 932 return BLK_STS_IOERR; 933 934 ret = nvme_setup_cmd(ns, req, &cmnd); 935 if (ret) 936 return ret; 937 938 ret = nvme_init_iod(req, dev); 939 if (ret) 940 goto out_free_cmd; 941 942 if (blk_rq_nr_phys_segments(req)) { 943 ret = nvme_map_data(dev, req, &cmnd); 944 if (ret) 945 goto out_cleanup_iod; 946 } 947 948 blk_mq_start_request(req); 949 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 950 return BLK_STS_OK; 951 out_cleanup_iod: 952 nvme_free_iod(dev, req); 953 out_free_cmd: 954 nvme_cleanup_cmd(req); 955 return ret; 956 } 957 958 static void nvme_pci_complete_rq(struct request *req) 959 { 960 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 961 962 nvme_unmap_data(iod->nvmeq->dev, req); 963 nvme_complete_rq(req); 964 } 965 966 /* We read the CQE phase first to check if the rest of the entry is valid */ 967 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 968 { 969 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 970 nvmeq->cq_phase; 971 } 972 973 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 974 { 975 u16 head = nvmeq->cq_head; 976 977 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 978 nvmeq->dbbuf_cq_ei)) 979 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 980 } 981 982 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 983 { 984 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 985 struct request *req; 986 987 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 988 dev_warn(nvmeq->dev->ctrl.device, 989 "invalid id %d completed on queue %d\n", 990 cqe->command_id, le16_to_cpu(cqe->sq_id)); 991 return; 992 } 993 994 /* 995 * AEN requests are special as they don't time out and can 996 * survive any kind of queue freeze and often don't respond to 997 * aborts. We don't even bother to allocate a struct request 998 * for them but rather special case them here. 999 */ 1000 if (unlikely(nvmeq->qid == 0 && 1001 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 1002 nvme_complete_async_event(&nvmeq->dev->ctrl, 1003 cqe->status, &cqe->result); 1004 return; 1005 } 1006 1007 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 1008 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1009 nvme_end_request(req, cqe->status, cqe->result); 1010 } 1011 1012 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 1013 { 1014 while (start != end) { 1015 nvme_handle_cqe(nvmeq, start); 1016 if (++start == nvmeq->q_depth) 1017 start = 0; 1018 } 1019 } 1020 1021 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1022 { 1023 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1024 nvmeq->cq_head = 0; 1025 nvmeq->cq_phase = !nvmeq->cq_phase; 1026 } else { 1027 nvmeq->cq_head++; 1028 } 1029 } 1030 1031 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 1032 u16 *end, unsigned int tag) 1033 { 1034 int found = 0; 1035 1036 *start = nvmeq->cq_head; 1037 while (nvme_cqe_pending(nvmeq)) { 1038 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1039 found++; 1040 nvme_update_cq_head(nvmeq); 1041 } 1042 *end = nvmeq->cq_head; 1043 1044 if (*start != *end) 1045 nvme_ring_cq_doorbell(nvmeq); 1046 return found; 1047 } 1048 1049 static irqreturn_t nvme_irq(int irq, void *data) 1050 { 1051 struct nvme_queue *nvmeq = data; 1052 irqreturn_t ret = IRQ_NONE; 1053 u16 start, end; 1054 1055 /* 1056 * The rmb/wmb pair ensures we see all updates from a previous run of 1057 * the irq handler, even if that was on another CPU. 1058 */ 1059 rmb(); 1060 if (nvmeq->cq_head != nvmeq->last_cq_head) 1061 ret = IRQ_HANDLED; 1062 nvme_process_cq(nvmeq, &start, &end, -1); 1063 nvmeq->last_cq_head = nvmeq->cq_head; 1064 wmb(); 1065 1066 if (start != end) { 1067 nvme_complete_cqes(nvmeq, start, end); 1068 return IRQ_HANDLED; 1069 } 1070 1071 return ret; 1072 } 1073 1074 static irqreturn_t nvme_irq_check(int irq, void *data) 1075 { 1076 struct nvme_queue *nvmeq = data; 1077 if (nvme_cqe_pending(nvmeq)) 1078 return IRQ_WAKE_THREAD; 1079 return IRQ_NONE; 1080 } 1081 1082 /* 1083 * Poll for completions any queue, including those not dedicated to polling. 1084 * Can be called from any context. 1085 */ 1086 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1087 { 1088 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1089 u16 start, end; 1090 int found; 1091 1092 /* 1093 * For a poll queue we need to protect against the polling thread 1094 * using the CQ lock. For normal interrupt driven threads we have 1095 * to disable the interrupt to avoid racing with it. 1096 */ 1097 if (nvmeq->cq_vector == -1) { 1098 spin_lock(&nvmeq->cq_poll_lock); 1099 found = nvme_process_cq(nvmeq, &start, &end, tag); 1100 spin_unlock(&nvmeq->cq_poll_lock); 1101 } else { 1102 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1103 found = nvme_process_cq(nvmeq, &start, &end, tag); 1104 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1105 } 1106 1107 nvme_complete_cqes(nvmeq, start, end); 1108 return found; 1109 } 1110 1111 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1112 { 1113 struct nvme_queue *nvmeq = hctx->driver_data; 1114 u16 start, end; 1115 bool found; 1116 1117 if (!nvme_cqe_pending(nvmeq)) 1118 return 0; 1119 1120 spin_lock(&nvmeq->cq_poll_lock); 1121 found = nvme_process_cq(nvmeq, &start, &end, -1); 1122 spin_unlock(&nvmeq->cq_poll_lock); 1123 1124 nvme_complete_cqes(nvmeq, start, end); 1125 return found; 1126 } 1127 1128 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1129 { 1130 struct nvme_dev *dev = to_nvme_dev(ctrl); 1131 struct nvme_queue *nvmeq = &dev->queues[0]; 1132 struct nvme_command c; 1133 1134 memset(&c, 0, sizeof(c)); 1135 c.common.opcode = nvme_admin_async_event; 1136 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1137 nvme_submit_cmd(nvmeq, &c, true); 1138 } 1139 1140 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1141 { 1142 struct nvme_command c; 1143 1144 memset(&c, 0, sizeof(c)); 1145 c.delete_queue.opcode = opcode; 1146 c.delete_queue.qid = cpu_to_le16(id); 1147 1148 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1149 } 1150 1151 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1152 struct nvme_queue *nvmeq, s16 vector) 1153 { 1154 struct nvme_command c; 1155 int flags = NVME_QUEUE_PHYS_CONTIG; 1156 1157 if (vector != -1) 1158 flags |= NVME_CQ_IRQ_ENABLED; 1159 1160 /* 1161 * Note: we (ab)use the fact that the prp fields survive if no data 1162 * is attached to the request. 1163 */ 1164 memset(&c, 0, sizeof(c)); 1165 c.create_cq.opcode = nvme_admin_create_cq; 1166 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1167 c.create_cq.cqid = cpu_to_le16(qid); 1168 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1169 c.create_cq.cq_flags = cpu_to_le16(flags); 1170 if (vector != -1) 1171 c.create_cq.irq_vector = cpu_to_le16(vector); 1172 else 1173 c.create_cq.irq_vector = 0; 1174 1175 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1176 } 1177 1178 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1179 struct nvme_queue *nvmeq) 1180 { 1181 struct nvme_ctrl *ctrl = &dev->ctrl; 1182 struct nvme_command c; 1183 int flags = NVME_QUEUE_PHYS_CONTIG; 1184 1185 /* 1186 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1187 * set. Since URGENT priority is zeroes, it makes all queues 1188 * URGENT. 1189 */ 1190 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1191 flags |= NVME_SQ_PRIO_MEDIUM; 1192 1193 /* 1194 * Note: we (ab)use the fact that the prp fields survive if no data 1195 * is attached to the request. 1196 */ 1197 memset(&c, 0, sizeof(c)); 1198 c.create_sq.opcode = nvme_admin_create_sq; 1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1200 c.create_sq.sqid = cpu_to_le16(qid); 1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1202 c.create_sq.sq_flags = cpu_to_le16(flags); 1203 c.create_sq.cqid = cpu_to_le16(qid); 1204 1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1206 } 1207 1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1209 { 1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1211 } 1212 1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1214 { 1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1216 } 1217 1218 static void abort_endio(struct request *req, blk_status_t error) 1219 { 1220 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1221 struct nvme_queue *nvmeq = iod->nvmeq; 1222 1223 dev_warn(nvmeq->dev->ctrl.device, 1224 "Abort status: 0x%x", nvme_req(req)->status); 1225 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1226 blk_mq_free_request(req); 1227 } 1228 1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1230 { 1231 1232 /* If true, indicates loss of adapter communication, possibly by a 1233 * NVMe Subsystem reset. 1234 */ 1235 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1236 1237 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1238 switch (dev->ctrl.state) { 1239 case NVME_CTRL_RESETTING: 1240 case NVME_CTRL_CONNECTING: 1241 return false; 1242 default: 1243 break; 1244 } 1245 1246 /* We shouldn't reset unless the controller is on fatal error state 1247 * _or_ if we lost the communication with it. 1248 */ 1249 if (!(csts & NVME_CSTS_CFS) && !nssro) 1250 return false; 1251 1252 return true; 1253 } 1254 1255 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1256 { 1257 /* Read a config register to help see what died. */ 1258 u16 pci_status; 1259 int result; 1260 1261 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1262 &pci_status); 1263 if (result == PCIBIOS_SUCCESSFUL) 1264 dev_warn(dev->ctrl.device, 1265 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1266 csts, pci_status); 1267 else 1268 dev_warn(dev->ctrl.device, 1269 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1270 csts, result); 1271 } 1272 1273 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1274 { 1275 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1276 struct nvme_queue *nvmeq = iod->nvmeq; 1277 struct nvme_dev *dev = nvmeq->dev; 1278 struct request *abort_req; 1279 struct nvme_command cmd; 1280 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1281 1282 /* If PCI error recovery process is happening, we cannot reset or 1283 * the recovery mechanism will surely fail. 1284 */ 1285 mb(); 1286 if (pci_channel_offline(to_pci_dev(dev->dev))) 1287 return BLK_EH_RESET_TIMER; 1288 1289 /* 1290 * Reset immediately if the controller is failed 1291 */ 1292 if (nvme_should_reset(dev, csts)) { 1293 nvme_warn_reset(dev, csts); 1294 nvme_dev_disable(dev, false); 1295 nvme_reset_ctrl(&dev->ctrl); 1296 return BLK_EH_DONE; 1297 } 1298 1299 /* 1300 * Did we miss an interrupt? 1301 */ 1302 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1303 dev_warn(dev->ctrl.device, 1304 "I/O %d QID %d timeout, completion polled\n", 1305 req->tag, nvmeq->qid); 1306 return BLK_EH_DONE; 1307 } 1308 1309 /* 1310 * Shutdown immediately if controller times out while starting. The 1311 * reset work will see the pci device disabled when it gets the forced 1312 * cancellation error. All outstanding requests are completed on 1313 * shutdown, so we return BLK_EH_DONE. 1314 */ 1315 switch (dev->ctrl.state) { 1316 case NVME_CTRL_CONNECTING: 1317 case NVME_CTRL_RESETTING: 1318 dev_warn_ratelimited(dev->ctrl.device, 1319 "I/O %d QID %d timeout, disable controller\n", 1320 req->tag, nvmeq->qid); 1321 nvme_dev_disable(dev, false); 1322 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1323 return BLK_EH_DONE; 1324 default: 1325 break; 1326 } 1327 1328 /* 1329 * Shutdown the controller immediately and schedule a reset if the 1330 * command was already aborted once before and still hasn't been 1331 * returned to the driver, or if this is the admin queue. 1332 */ 1333 if (!nvmeq->qid || iod->aborted) { 1334 dev_warn(dev->ctrl.device, 1335 "I/O %d QID %d timeout, reset controller\n", 1336 req->tag, nvmeq->qid); 1337 nvme_dev_disable(dev, false); 1338 nvme_reset_ctrl(&dev->ctrl); 1339 1340 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1341 return BLK_EH_DONE; 1342 } 1343 1344 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1345 atomic_inc(&dev->ctrl.abort_limit); 1346 return BLK_EH_RESET_TIMER; 1347 } 1348 iod->aborted = 1; 1349 1350 memset(&cmd, 0, sizeof(cmd)); 1351 cmd.abort.opcode = nvme_admin_abort_cmd; 1352 cmd.abort.cid = req->tag; 1353 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1354 1355 dev_warn(nvmeq->dev->ctrl.device, 1356 "I/O %d QID %d timeout, aborting\n", 1357 req->tag, nvmeq->qid); 1358 1359 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1360 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1361 if (IS_ERR(abort_req)) { 1362 atomic_inc(&dev->ctrl.abort_limit); 1363 return BLK_EH_RESET_TIMER; 1364 } 1365 1366 abort_req->timeout = ADMIN_TIMEOUT; 1367 abort_req->end_io_data = NULL; 1368 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1369 1370 /* 1371 * The aborted req will be completed on receiving the abort req. 1372 * We enable the timer again. If hit twice, it'll cause a device reset, 1373 * as the device then is in a faulty state. 1374 */ 1375 return BLK_EH_RESET_TIMER; 1376 } 1377 1378 static void nvme_free_queue(struct nvme_queue *nvmeq) 1379 { 1380 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 1381 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1382 if (!nvmeq->sq_cmds) 1383 return; 1384 1385 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1386 pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 1387 nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 1388 } else { 1389 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 1390 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1391 } 1392 } 1393 1394 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1395 { 1396 int i; 1397 1398 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1399 dev->ctrl.queue_count--; 1400 nvme_free_queue(&dev->queues[i]); 1401 } 1402 } 1403 1404 /** 1405 * nvme_suspend_queue - put queue into suspended state 1406 * @nvmeq: queue to suspend 1407 */ 1408 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1409 { 1410 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1411 return 1; 1412 1413 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1414 mb(); 1415 1416 nvmeq->dev->online_queues--; 1417 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1418 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1419 if (nvmeq->cq_vector == -1) 1420 return 0; 1421 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1422 nvmeq->cq_vector = -1; 1423 return 0; 1424 } 1425 1426 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1427 { 1428 int i; 1429 1430 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1431 nvme_suspend_queue(&dev->queues[i]); 1432 } 1433 1434 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1435 { 1436 struct nvme_queue *nvmeq = &dev->queues[0]; 1437 1438 if (shutdown) 1439 nvme_shutdown_ctrl(&dev->ctrl); 1440 else 1441 nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1442 1443 nvme_poll_irqdisable(nvmeq, -1); 1444 } 1445 1446 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1447 int entry_size) 1448 { 1449 int q_depth = dev->q_depth; 1450 unsigned q_size_aligned = roundup(q_depth * entry_size, 1451 dev->ctrl.page_size); 1452 1453 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1454 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1455 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1456 q_depth = div_u64(mem_per_q, entry_size); 1457 1458 /* 1459 * Ensure the reduced q_depth is above some threshold where it 1460 * would be better to map queues in system memory with the 1461 * original depth 1462 */ 1463 if (q_depth < 64) 1464 return -ENOMEM; 1465 } 1466 1467 return q_depth; 1468 } 1469 1470 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1471 int qid, int depth) 1472 { 1473 struct pci_dev *pdev = to_pci_dev(dev->dev); 1474 1475 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1476 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 1477 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1478 nvmeq->sq_cmds); 1479 if (nvmeq->sq_dma_addr) { 1480 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1481 return 0; 1482 } 1483 } 1484 1485 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 1486 &nvmeq->sq_dma_addr, GFP_KERNEL); 1487 if (!nvmeq->sq_cmds) 1488 return -ENOMEM; 1489 return 0; 1490 } 1491 1492 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1493 { 1494 struct nvme_queue *nvmeq = &dev->queues[qid]; 1495 1496 if (dev->ctrl.queue_count > qid) 1497 return 0; 1498 1499 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 1500 &nvmeq->cq_dma_addr, GFP_KERNEL); 1501 if (!nvmeq->cqes) 1502 goto free_nvmeq; 1503 1504 if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 1505 goto free_cqdma; 1506 1507 nvmeq->q_dmadev = dev->dev; 1508 nvmeq->dev = dev; 1509 spin_lock_init(&nvmeq->sq_lock); 1510 spin_lock_init(&nvmeq->cq_poll_lock); 1511 nvmeq->cq_head = 0; 1512 nvmeq->cq_phase = 1; 1513 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1514 nvmeq->q_depth = depth; 1515 nvmeq->qid = qid; 1516 nvmeq->cq_vector = -1; 1517 dev->ctrl.queue_count++; 1518 1519 return 0; 1520 1521 free_cqdma: 1522 dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 1523 nvmeq->cq_dma_addr); 1524 free_nvmeq: 1525 return -ENOMEM; 1526 } 1527 1528 static int queue_request_irq(struct nvme_queue *nvmeq) 1529 { 1530 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1531 int nr = nvmeq->dev->ctrl.instance; 1532 1533 if (use_threaded_interrupts) { 1534 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1535 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1536 } else { 1537 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1538 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1539 } 1540 } 1541 1542 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1543 { 1544 struct nvme_dev *dev = nvmeq->dev; 1545 1546 nvmeq->sq_tail = 0; 1547 nvmeq->last_sq_tail = 0; 1548 nvmeq->cq_head = 0; 1549 nvmeq->cq_phase = 1; 1550 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1551 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1552 nvme_dbbuf_init(dev, nvmeq, qid); 1553 dev->online_queues++; 1554 wmb(); /* ensure the first interrupt sees the initialization */ 1555 } 1556 1557 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1558 { 1559 struct nvme_dev *dev = nvmeq->dev; 1560 int result; 1561 s16 vector; 1562 1563 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1564 1565 /* 1566 * A queue's vector matches the queue identifier unless the controller 1567 * has only one vector available. 1568 */ 1569 if (!polled) 1570 vector = dev->num_vecs == 1 ? 0 : qid; 1571 else 1572 vector = -1; 1573 1574 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1575 if (result) 1576 return result; 1577 1578 result = adapter_alloc_sq(dev, qid, nvmeq); 1579 if (result < 0) 1580 return result; 1581 else if (result) 1582 goto release_cq; 1583 1584 nvmeq->cq_vector = vector; 1585 nvme_init_queue(nvmeq, qid); 1586 1587 if (vector != -1) { 1588 result = queue_request_irq(nvmeq); 1589 if (result < 0) 1590 goto release_sq; 1591 } 1592 1593 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1594 return result; 1595 1596 release_sq: 1597 nvmeq->cq_vector = -1; 1598 dev->online_queues--; 1599 adapter_delete_sq(dev, qid); 1600 release_cq: 1601 adapter_delete_cq(dev, qid); 1602 return result; 1603 } 1604 1605 static const struct blk_mq_ops nvme_mq_admin_ops = { 1606 .queue_rq = nvme_queue_rq, 1607 .complete = nvme_pci_complete_rq, 1608 .init_hctx = nvme_admin_init_hctx, 1609 .exit_hctx = nvme_admin_exit_hctx, 1610 .init_request = nvme_init_request, 1611 .timeout = nvme_timeout, 1612 }; 1613 1614 static const struct blk_mq_ops nvme_mq_ops = { 1615 .queue_rq = nvme_queue_rq, 1616 .complete = nvme_pci_complete_rq, 1617 .commit_rqs = nvme_commit_rqs, 1618 .init_hctx = nvme_init_hctx, 1619 .init_request = nvme_init_request, 1620 .map_queues = nvme_pci_map_queues, 1621 .timeout = nvme_timeout, 1622 .poll = nvme_poll, 1623 }; 1624 1625 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1626 { 1627 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1628 /* 1629 * If the controller was reset during removal, it's possible 1630 * user requests may be waiting on a stopped queue. Start the 1631 * queue to flush these to completion. 1632 */ 1633 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1634 blk_cleanup_queue(dev->ctrl.admin_q); 1635 blk_mq_free_tag_set(&dev->admin_tagset); 1636 } 1637 } 1638 1639 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1640 { 1641 if (!dev->ctrl.admin_q) { 1642 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1643 dev->admin_tagset.nr_hw_queues = 1; 1644 1645 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1646 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1647 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1648 dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1649 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1650 dev->admin_tagset.driver_data = dev; 1651 1652 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1653 return -ENOMEM; 1654 dev->ctrl.admin_tagset = &dev->admin_tagset; 1655 1656 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1657 if (IS_ERR(dev->ctrl.admin_q)) { 1658 blk_mq_free_tag_set(&dev->admin_tagset); 1659 return -ENOMEM; 1660 } 1661 if (!blk_get_queue(dev->ctrl.admin_q)) { 1662 nvme_dev_remove_admin(dev); 1663 dev->ctrl.admin_q = NULL; 1664 return -ENODEV; 1665 } 1666 } else 1667 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1668 1669 return 0; 1670 } 1671 1672 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1673 { 1674 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1675 } 1676 1677 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1678 { 1679 struct pci_dev *pdev = to_pci_dev(dev->dev); 1680 1681 if (size <= dev->bar_mapped_size) 1682 return 0; 1683 if (size > pci_resource_len(pdev, 0)) 1684 return -ENOMEM; 1685 if (dev->bar) 1686 iounmap(dev->bar); 1687 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1688 if (!dev->bar) { 1689 dev->bar_mapped_size = 0; 1690 return -ENOMEM; 1691 } 1692 dev->bar_mapped_size = size; 1693 dev->dbs = dev->bar + NVME_REG_DBS; 1694 1695 return 0; 1696 } 1697 1698 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1699 { 1700 int result; 1701 u32 aqa; 1702 struct nvme_queue *nvmeq; 1703 1704 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1705 if (result < 0) 1706 return result; 1707 1708 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1709 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1710 1711 if (dev->subsystem && 1712 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1713 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1714 1715 result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 1716 if (result < 0) 1717 return result; 1718 1719 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1720 if (result) 1721 return result; 1722 1723 nvmeq = &dev->queues[0]; 1724 aqa = nvmeq->q_depth - 1; 1725 aqa |= aqa << 16; 1726 1727 writel(aqa, dev->bar + NVME_REG_AQA); 1728 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1729 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1730 1731 result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 1732 if (result) 1733 return result; 1734 1735 nvmeq->cq_vector = 0; 1736 nvme_init_queue(nvmeq, 0); 1737 result = queue_request_irq(nvmeq); 1738 if (result) { 1739 nvmeq->cq_vector = -1; 1740 return result; 1741 } 1742 1743 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1744 return result; 1745 } 1746 1747 static int nvme_create_io_queues(struct nvme_dev *dev) 1748 { 1749 unsigned i, max, rw_queues; 1750 int ret = 0; 1751 1752 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1753 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1754 ret = -ENOMEM; 1755 break; 1756 } 1757 } 1758 1759 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1760 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1761 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1762 dev->io_queues[HCTX_TYPE_READ]; 1763 } else { 1764 rw_queues = max; 1765 } 1766 1767 for (i = dev->online_queues; i <= max; i++) { 1768 bool polled = i > rw_queues; 1769 1770 ret = nvme_create_queue(&dev->queues[i], i, polled); 1771 if (ret) 1772 break; 1773 } 1774 1775 /* 1776 * Ignore failing Create SQ/CQ commands, we can continue with less 1777 * than the desired amount of queues, and even a controller without 1778 * I/O queues can still be used to issue admin commands. This might 1779 * be useful to upgrade a buggy firmware for example. 1780 */ 1781 return ret >= 0 ? 0 : ret; 1782 } 1783 1784 static ssize_t nvme_cmb_show(struct device *dev, 1785 struct device_attribute *attr, 1786 char *buf) 1787 { 1788 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1789 1790 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1791 ndev->cmbloc, ndev->cmbsz); 1792 } 1793 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1794 1795 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1796 { 1797 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1798 1799 return 1ULL << (12 + 4 * szu); 1800 } 1801 1802 static u32 nvme_cmb_size(struct nvme_dev *dev) 1803 { 1804 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1805 } 1806 1807 static void nvme_map_cmb(struct nvme_dev *dev) 1808 { 1809 u64 size, offset; 1810 resource_size_t bar_size; 1811 struct pci_dev *pdev = to_pci_dev(dev->dev); 1812 int bar; 1813 1814 if (dev->cmb_size) 1815 return; 1816 1817 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1818 if (!dev->cmbsz) 1819 return; 1820 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1821 1822 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1823 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1824 bar = NVME_CMB_BIR(dev->cmbloc); 1825 bar_size = pci_resource_len(pdev, bar); 1826 1827 if (offset > bar_size) 1828 return; 1829 1830 /* 1831 * Controllers may support a CMB size larger than their BAR, 1832 * for example, due to being behind a bridge. Reduce the CMB to 1833 * the reported size of the BAR 1834 */ 1835 if (size > bar_size - offset) 1836 size = bar_size - offset; 1837 1838 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1839 dev_warn(dev->ctrl.device, 1840 "failed to register the CMB\n"); 1841 return; 1842 } 1843 1844 dev->cmb_size = size; 1845 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1846 1847 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1848 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1849 pci_p2pmem_publish(pdev, true); 1850 1851 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1852 &dev_attr_cmb.attr, NULL)) 1853 dev_warn(dev->ctrl.device, 1854 "failed to add sysfs attribute for CMB\n"); 1855 } 1856 1857 static inline void nvme_release_cmb(struct nvme_dev *dev) 1858 { 1859 if (dev->cmb_size) { 1860 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1861 &dev_attr_cmb.attr, NULL); 1862 dev->cmb_size = 0; 1863 } 1864 } 1865 1866 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1867 { 1868 u64 dma_addr = dev->host_mem_descs_dma; 1869 struct nvme_command c; 1870 int ret; 1871 1872 memset(&c, 0, sizeof(c)); 1873 c.features.opcode = nvme_admin_set_features; 1874 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1875 c.features.dword11 = cpu_to_le32(bits); 1876 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1877 ilog2(dev->ctrl.page_size)); 1878 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1879 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1880 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1881 1882 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1883 if (ret) { 1884 dev_warn(dev->ctrl.device, 1885 "failed to set host mem (err %d, flags %#x).\n", 1886 ret, bits); 1887 } 1888 return ret; 1889 } 1890 1891 static void nvme_free_host_mem(struct nvme_dev *dev) 1892 { 1893 int i; 1894 1895 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1896 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1897 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1898 1899 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1900 le64_to_cpu(desc->addr), 1901 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1902 } 1903 1904 kfree(dev->host_mem_desc_bufs); 1905 dev->host_mem_desc_bufs = NULL; 1906 dma_free_coherent(dev->dev, 1907 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1908 dev->host_mem_descs, dev->host_mem_descs_dma); 1909 dev->host_mem_descs = NULL; 1910 dev->nr_host_mem_descs = 0; 1911 } 1912 1913 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1914 u32 chunk_size) 1915 { 1916 struct nvme_host_mem_buf_desc *descs; 1917 u32 max_entries, len; 1918 dma_addr_t descs_dma; 1919 int i = 0; 1920 void **bufs; 1921 u64 size, tmp; 1922 1923 tmp = (preferred + chunk_size - 1); 1924 do_div(tmp, chunk_size); 1925 max_entries = tmp; 1926 1927 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1928 max_entries = dev->ctrl.hmmaxd; 1929 1930 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1931 &descs_dma, GFP_KERNEL); 1932 if (!descs) 1933 goto out; 1934 1935 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1936 if (!bufs) 1937 goto out_free_descs; 1938 1939 for (size = 0; size < preferred && i < max_entries; size += len) { 1940 dma_addr_t dma_addr; 1941 1942 len = min_t(u64, chunk_size, preferred - size); 1943 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1944 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1945 if (!bufs[i]) 1946 break; 1947 1948 descs[i].addr = cpu_to_le64(dma_addr); 1949 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1950 i++; 1951 } 1952 1953 if (!size) 1954 goto out_free_bufs; 1955 1956 dev->nr_host_mem_descs = i; 1957 dev->host_mem_size = size; 1958 dev->host_mem_descs = descs; 1959 dev->host_mem_descs_dma = descs_dma; 1960 dev->host_mem_desc_bufs = bufs; 1961 return 0; 1962 1963 out_free_bufs: 1964 while (--i >= 0) { 1965 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1966 1967 dma_free_attrs(dev->dev, size, bufs[i], 1968 le64_to_cpu(descs[i].addr), 1969 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1970 } 1971 1972 kfree(bufs); 1973 out_free_descs: 1974 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1975 descs_dma); 1976 out: 1977 dev->host_mem_descs = NULL; 1978 return -ENOMEM; 1979 } 1980 1981 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1982 { 1983 u32 chunk_size; 1984 1985 /* start big and work our way down */ 1986 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1987 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1988 chunk_size /= 2) { 1989 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1990 if (!min || dev->host_mem_size >= min) 1991 return 0; 1992 nvme_free_host_mem(dev); 1993 } 1994 } 1995 1996 return -ENOMEM; 1997 } 1998 1999 static int nvme_setup_host_mem(struct nvme_dev *dev) 2000 { 2001 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2002 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2003 u64 min = (u64)dev->ctrl.hmmin * 4096; 2004 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2005 int ret; 2006 2007 preferred = min(preferred, max); 2008 if (min > max) { 2009 dev_warn(dev->ctrl.device, 2010 "min host memory (%lld MiB) above limit (%d MiB).\n", 2011 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2012 nvme_free_host_mem(dev); 2013 return 0; 2014 } 2015 2016 /* 2017 * If we already have a buffer allocated check if we can reuse it. 2018 */ 2019 if (dev->host_mem_descs) { 2020 if (dev->host_mem_size >= min) 2021 enable_bits |= NVME_HOST_MEM_RETURN; 2022 else 2023 nvme_free_host_mem(dev); 2024 } 2025 2026 if (!dev->host_mem_descs) { 2027 if (nvme_alloc_host_mem(dev, min, preferred)) { 2028 dev_warn(dev->ctrl.device, 2029 "failed to allocate host memory buffer.\n"); 2030 return 0; /* controller must work without HMB */ 2031 } 2032 2033 dev_info(dev->ctrl.device, 2034 "allocated %lld MiB host memory buffer.\n", 2035 dev->host_mem_size >> ilog2(SZ_1M)); 2036 } 2037 2038 ret = nvme_set_host_mem(dev, enable_bits); 2039 if (ret) 2040 nvme_free_host_mem(dev); 2041 return ret; 2042 } 2043 2044 /* irq_queues covers admin queue */ 2045 static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues) 2046 { 2047 unsigned int this_w_queues = write_queues; 2048 2049 WARN_ON(!irq_queues); 2050 2051 /* 2052 * Setup read/write queue split, assign admin queue one independent 2053 * irq vector if irq_queues is > 1. 2054 */ 2055 if (irq_queues <= 2) { 2056 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2057 dev->io_queues[HCTX_TYPE_READ] = 0; 2058 return; 2059 } 2060 2061 /* 2062 * If 'write_queues' is set, ensure it leaves room for at least 2063 * one read queue and one admin queue 2064 */ 2065 if (this_w_queues >= irq_queues) 2066 this_w_queues = irq_queues - 2; 2067 2068 /* 2069 * If 'write_queues' is set to zero, reads and writes will share 2070 * a queue set. 2071 */ 2072 if (!this_w_queues) { 2073 dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues - 1; 2074 dev->io_queues[HCTX_TYPE_READ] = 0; 2075 } else { 2076 dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues; 2077 dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues - 1; 2078 } 2079 } 2080 2081 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2082 { 2083 struct pci_dev *pdev = to_pci_dev(dev->dev); 2084 int irq_sets[2]; 2085 struct irq_affinity affd = { 2086 .pre_vectors = 1, 2087 .nr_sets = ARRAY_SIZE(irq_sets), 2088 .sets = irq_sets, 2089 }; 2090 int result = 0; 2091 unsigned int irq_queues, this_p_queues; 2092 2093 /* 2094 * Poll queues don't need interrupts, but we need at least one IO 2095 * queue left over for non-polled IO. 2096 */ 2097 this_p_queues = poll_queues; 2098 if (this_p_queues >= nr_io_queues) { 2099 this_p_queues = nr_io_queues - 1; 2100 irq_queues = 1; 2101 } else { 2102 irq_queues = nr_io_queues - this_p_queues + 1; 2103 } 2104 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2105 2106 /* 2107 * For irq sets, we have to ask for minvec == maxvec. This passes 2108 * any reduction back to us, so we can adjust our queue counts and 2109 * IRQ vector needs. 2110 */ 2111 do { 2112 nvme_calc_io_queues(dev, irq_queues); 2113 irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT]; 2114 irq_sets[1] = dev->io_queues[HCTX_TYPE_READ]; 2115 if (!irq_sets[1]) 2116 affd.nr_sets = 1; 2117 2118 /* 2119 * If we got a failure and we're down to asking for just 2120 * 1 + 1 queues, just ask for a single vector. We'll share 2121 * that between the single IO queue and the admin queue. 2122 * Otherwise, we assign one independent vector to admin queue. 2123 */ 2124 if (irq_queues > 1) 2125 irq_queues = irq_sets[0] + irq_sets[1] + 1; 2126 2127 result = pci_alloc_irq_vectors_affinity(pdev, irq_queues, 2128 irq_queues, 2129 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2130 2131 /* 2132 * Need to reduce our vec counts. If we get ENOSPC, the 2133 * platform should support mulitple vecs, we just need 2134 * to decrease our ask. If we get EINVAL, the platform 2135 * likely does not. Back down to ask for just one vector. 2136 */ 2137 if (result == -ENOSPC) { 2138 irq_queues--; 2139 if (!irq_queues) 2140 return result; 2141 continue; 2142 } else if (result == -EINVAL) { 2143 irq_queues = 1; 2144 continue; 2145 } else if (result <= 0) 2146 return -EIO; 2147 break; 2148 } while (1); 2149 2150 return result; 2151 } 2152 2153 static void nvme_disable_io_queues(struct nvme_dev *dev) 2154 { 2155 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2156 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2157 } 2158 2159 static int nvme_setup_io_queues(struct nvme_dev *dev) 2160 { 2161 struct nvme_queue *adminq = &dev->queues[0]; 2162 struct pci_dev *pdev = to_pci_dev(dev->dev); 2163 int result, nr_io_queues; 2164 unsigned long size; 2165 2166 nr_io_queues = max_io_queues(); 2167 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2168 if (result < 0) 2169 return result; 2170 2171 if (nr_io_queues == 0) 2172 return 0; 2173 2174 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2175 2176 if (dev->cmb_use_sqes) { 2177 result = nvme_cmb_qdepth(dev, nr_io_queues, 2178 sizeof(struct nvme_command)); 2179 if (result > 0) 2180 dev->q_depth = result; 2181 else 2182 dev->cmb_use_sqes = false; 2183 } 2184 2185 do { 2186 size = db_bar_size(dev, nr_io_queues); 2187 result = nvme_remap_bar(dev, size); 2188 if (!result) 2189 break; 2190 if (!--nr_io_queues) 2191 return -ENOMEM; 2192 } while (1); 2193 adminq->q_db = dev->dbs; 2194 2195 retry: 2196 /* Deregister the admin queue's interrupt */ 2197 pci_free_irq(pdev, 0, adminq); 2198 2199 /* 2200 * If we enable msix early due to not intx, disable it again before 2201 * setting up the full range we need. 2202 */ 2203 pci_free_irq_vectors(pdev); 2204 2205 result = nvme_setup_irqs(dev, nr_io_queues); 2206 if (result <= 0) 2207 return -EIO; 2208 2209 dev->num_vecs = result; 2210 result = max(result - 1, 1); 2211 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2212 2213 /* 2214 * Should investigate if there's a performance win from allocating 2215 * more queues than interrupt vectors; it might allow the submission 2216 * path to scale better, even if the receive path is limited by the 2217 * number of interrupts. 2218 */ 2219 result = queue_request_irq(adminq); 2220 if (result) { 2221 adminq->cq_vector = -1; 2222 return result; 2223 } 2224 set_bit(NVMEQ_ENABLED, &adminq->flags); 2225 2226 result = nvme_create_io_queues(dev); 2227 if (result || dev->online_queues < 2) 2228 return result; 2229 2230 if (dev->online_queues - 1 < dev->max_qid) { 2231 nr_io_queues = dev->online_queues - 1; 2232 nvme_disable_io_queues(dev); 2233 nvme_suspend_io_queues(dev); 2234 goto retry; 2235 } 2236 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2237 dev->io_queues[HCTX_TYPE_DEFAULT], 2238 dev->io_queues[HCTX_TYPE_READ], 2239 dev->io_queues[HCTX_TYPE_POLL]); 2240 return 0; 2241 } 2242 2243 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2244 { 2245 struct nvme_queue *nvmeq = req->end_io_data; 2246 2247 blk_mq_free_request(req); 2248 complete(&nvmeq->delete_done); 2249 } 2250 2251 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2252 { 2253 struct nvme_queue *nvmeq = req->end_io_data; 2254 2255 if (error) 2256 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2257 2258 nvme_del_queue_end(req, error); 2259 } 2260 2261 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2262 { 2263 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2264 struct request *req; 2265 struct nvme_command cmd; 2266 2267 memset(&cmd, 0, sizeof(cmd)); 2268 cmd.delete_queue.opcode = opcode; 2269 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2270 2271 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2272 if (IS_ERR(req)) 2273 return PTR_ERR(req); 2274 2275 req->timeout = ADMIN_TIMEOUT; 2276 req->end_io_data = nvmeq; 2277 2278 init_completion(&nvmeq->delete_done); 2279 blk_execute_rq_nowait(q, NULL, req, false, 2280 opcode == nvme_admin_delete_cq ? 2281 nvme_del_cq_end : nvme_del_queue_end); 2282 return 0; 2283 } 2284 2285 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2286 { 2287 int nr_queues = dev->online_queues - 1, sent = 0; 2288 unsigned long timeout; 2289 2290 retry: 2291 timeout = ADMIN_TIMEOUT; 2292 while (nr_queues > 0) { 2293 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2294 break; 2295 nr_queues--; 2296 sent++; 2297 } 2298 while (sent) { 2299 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2300 2301 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2302 timeout); 2303 if (timeout == 0) 2304 return false; 2305 2306 /* handle any remaining CQEs */ 2307 if (opcode == nvme_admin_delete_cq && 2308 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2309 nvme_poll_irqdisable(nvmeq, -1); 2310 2311 sent--; 2312 if (nr_queues) 2313 goto retry; 2314 } 2315 return true; 2316 } 2317 2318 /* 2319 * return error value only when tagset allocation failed 2320 */ 2321 static int nvme_dev_add(struct nvme_dev *dev) 2322 { 2323 int ret; 2324 2325 if (!dev->ctrl.tagset) { 2326 dev->tagset.ops = &nvme_mq_ops; 2327 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2328 dev->tagset.nr_maps = 2; /* default + read */ 2329 if (dev->io_queues[HCTX_TYPE_POLL]) 2330 dev->tagset.nr_maps++; 2331 dev->tagset.timeout = NVME_IO_TIMEOUT; 2332 dev->tagset.numa_node = dev_to_node(dev->dev); 2333 dev->tagset.queue_depth = 2334 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2335 dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2336 if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2337 dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2338 nvme_pci_cmd_size(dev, true)); 2339 } 2340 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2341 dev->tagset.driver_data = dev; 2342 2343 ret = blk_mq_alloc_tag_set(&dev->tagset); 2344 if (ret) { 2345 dev_warn(dev->ctrl.device, 2346 "IO queues tagset allocation failed %d\n", ret); 2347 return ret; 2348 } 2349 dev->ctrl.tagset = &dev->tagset; 2350 2351 nvme_dbbuf_set(dev); 2352 } else { 2353 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2354 2355 /* Free previously allocated queues that are no longer usable */ 2356 nvme_free_queues(dev, dev->online_queues); 2357 } 2358 2359 return 0; 2360 } 2361 2362 static int nvme_pci_enable(struct nvme_dev *dev) 2363 { 2364 int result = -ENOMEM; 2365 struct pci_dev *pdev = to_pci_dev(dev->dev); 2366 2367 if (pci_enable_device_mem(pdev)) 2368 return result; 2369 2370 pci_set_master(pdev); 2371 2372 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 2373 dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 2374 goto disable; 2375 2376 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2377 result = -ENODEV; 2378 goto disable; 2379 } 2380 2381 /* 2382 * Some devices and/or platforms don't advertise or work with INTx 2383 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2384 * adjust this later. 2385 */ 2386 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2387 if (result < 0) 2388 return result; 2389 2390 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2391 2392 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2393 io_queue_depth); 2394 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2395 dev->dbs = dev->bar + 4096; 2396 2397 /* 2398 * Temporary fix for the Apple controller found in the MacBook8,1 and 2399 * some MacBook7,1 to avoid controller resets and data loss. 2400 */ 2401 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2402 dev->q_depth = 2; 2403 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2404 "set queue depth=%u to work around controller resets\n", 2405 dev->q_depth); 2406 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2407 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2408 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2409 dev->q_depth = 64; 2410 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2411 "set queue depth=%u\n", dev->q_depth); 2412 } 2413 2414 nvme_map_cmb(dev); 2415 2416 pci_enable_pcie_error_reporting(pdev); 2417 pci_save_state(pdev); 2418 return 0; 2419 2420 disable: 2421 pci_disable_device(pdev); 2422 return result; 2423 } 2424 2425 static void nvme_dev_unmap(struct nvme_dev *dev) 2426 { 2427 if (dev->bar) 2428 iounmap(dev->bar); 2429 pci_release_mem_regions(to_pci_dev(dev->dev)); 2430 } 2431 2432 static void nvme_pci_disable(struct nvme_dev *dev) 2433 { 2434 struct pci_dev *pdev = to_pci_dev(dev->dev); 2435 2436 pci_free_irq_vectors(pdev); 2437 2438 if (pci_is_enabled(pdev)) { 2439 pci_disable_pcie_error_reporting(pdev); 2440 pci_disable_device(pdev); 2441 } 2442 } 2443 2444 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2445 { 2446 bool dead = true; 2447 struct pci_dev *pdev = to_pci_dev(dev->dev); 2448 2449 mutex_lock(&dev->shutdown_lock); 2450 if (pci_is_enabled(pdev)) { 2451 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2452 2453 if (dev->ctrl.state == NVME_CTRL_LIVE || 2454 dev->ctrl.state == NVME_CTRL_RESETTING) 2455 nvme_start_freeze(&dev->ctrl); 2456 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2457 pdev->error_state != pci_channel_io_normal); 2458 } 2459 2460 /* 2461 * Give the controller a chance to complete all entered requests if 2462 * doing a safe shutdown. 2463 */ 2464 if (!dead) { 2465 if (shutdown) 2466 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2467 } 2468 2469 nvme_stop_queues(&dev->ctrl); 2470 2471 if (!dead && dev->ctrl.queue_count > 0) { 2472 nvme_disable_io_queues(dev); 2473 nvme_disable_admin_queue(dev, shutdown); 2474 } 2475 nvme_suspend_io_queues(dev); 2476 nvme_suspend_queue(&dev->queues[0]); 2477 nvme_pci_disable(dev); 2478 2479 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2480 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2481 2482 /* 2483 * The driver will not be starting up queues again if shutting down so 2484 * must flush all entered requests to their failed completion to avoid 2485 * deadlocking blk-mq hot-cpu notifier. 2486 */ 2487 if (shutdown) 2488 nvme_start_queues(&dev->ctrl); 2489 mutex_unlock(&dev->shutdown_lock); 2490 } 2491 2492 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2493 { 2494 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2495 PAGE_SIZE, PAGE_SIZE, 0); 2496 if (!dev->prp_page_pool) 2497 return -ENOMEM; 2498 2499 /* Optimisation for I/Os between 4k and 128k */ 2500 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2501 256, 256, 0); 2502 if (!dev->prp_small_pool) { 2503 dma_pool_destroy(dev->prp_page_pool); 2504 return -ENOMEM; 2505 } 2506 return 0; 2507 } 2508 2509 static void nvme_release_prp_pools(struct nvme_dev *dev) 2510 { 2511 dma_pool_destroy(dev->prp_page_pool); 2512 dma_pool_destroy(dev->prp_small_pool); 2513 } 2514 2515 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2516 { 2517 struct nvme_dev *dev = to_nvme_dev(ctrl); 2518 2519 nvme_dbbuf_dma_free(dev); 2520 put_device(dev->dev); 2521 if (dev->tagset.tags) 2522 blk_mq_free_tag_set(&dev->tagset); 2523 if (dev->ctrl.admin_q) 2524 blk_put_queue(dev->ctrl.admin_q); 2525 kfree(dev->queues); 2526 free_opal_dev(dev->ctrl.opal_dev); 2527 mempool_destroy(dev->iod_mempool); 2528 kfree(dev); 2529 } 2530 2531 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2532 { 2533 dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2534 2535 nvme_get_ctrl(&dev->ctrl); 2536 nvme_dev_disable(dev, false); 2537 nvme_kill_queues(&dev->ctrl); 2538 if (!queue_work(nvme_wq, &dev->remove_work)) 2539 nvme_put_ctrl(&dev->ctrl); 2540 } 2541 2542 static void nvme_reset_work(struct work_struct *work) 2543 { 2544 struct nvme_dev *dev = 2545 container_of(work, struct nvme_dev, ctrl.reset_work); 2546 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2547 int result = -ENODEV; 2548 enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 2549 2550 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2551 goto out; 2552 2553 /* 2554 * If we're called to reset a live controller first shut it down before 2555 * moving on. 2556 */ 2557 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2558 nvme_dev_disable(dev, false); 2559 2560 /* 2561 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2562 * initializing procedure here. 2563 */ 2564 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2565 dev_warn(dev->ctrl.device, 2566 "failed to mark controller CONNECTING\n"); 2567 goto out; 2568 } 2569 2570 result = nvme_pci_enable(dev); 2571 if (result) 2572 goto out; 2573 2574 result = nvme_pci_configure_admin_queue(dev); 2575 if (result) 2576 goto out; 2577 2578 result = nvme_alloc_admin_tags(dev); 2579 if (result) 2580 goto out; 2581 2582 /* 2583 * Limit the max command size to prevent iod->sg allocations going 2584 * over a single page. 2585 */ 2586 dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2587 dev->ctrl.max_segments = NVME_MAX_SEGS; 2588 2589 result = nvme_init_identify(&dev->ctrl); 2590 if (result) 2591 goto out; 2592 2593 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2594 if (!dev->ctrl.opal_dev) 2595 dev->ctrl.opal_dev = 2596 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2597 else if (was_suspend) 2598 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2599 } else { 2600 free_opal_dev(dev->ctrl.opal_dev); 2601 dev->ctrl.opal_dev = NULL; 2602 } 2603 2604 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2605 result = nvme_dbbuf_dma_alloc(dev); 2606 if (result) 2607 dev_warn(dev->dev, 2608 "unable to allocate dma for dbbuf\n"); 2609 } 2610 2611 if (dev->ctrl.hmpre) { 2612 result = nvme_setup_host_mem(dev); 2613 if (result < 0) 2614 goto out; 2615 } 2616 2617 result = nvme_setup_io_queues(dev); 2618 if (result) 2619 goto out; 2620 2621 /* 2622 * Keep the controller around but remove all namespaces if we don't have 2623 * any working I/O queue. 2624 */ 2625 if (dev->online_queues < 2) { 2626 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2627 nvme_kill_queues(&dev->ctrl); 2628 nvme_remove_namespaces(&dev->ctrl); 2629 new_state = NVME_CTRL_ADMIN_ONLY; 2630 } else { 2631 nvme_start_queues(&dev->ctrl); 2632 nvme_wait_freeze(&dev->ctrl); 2633 /* hit this only when allocate tagset fails */ 2634 if (nvme_dev_add(dev)) 2635 new_state = NVME_CTRL_ADMIN_ONLY; 2636 nvme_unfreeze(&dev->ctrl); 2637 } 2638 2639 /* 2640 * If only admin queue live, keep it to do further investigation or 2641 * recovery. 2642 */ 2643 if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 2644 dev_warn(dev->ctrl.device, 2645 "failed to mark controller state %d\n", new_state); 2646 goto out; 2647 } 2648 2649 nvme_start_ctrl(&dev->ctrl); 2650 return; 2651 2652 out: 2653 nvme_remove_dead_ctrl(dev, result); 2654 } 2655 2656 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2657 { 2658 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2659 struct pci_dev *pdev = to_pci_dev(dev->dev); 2660 2661 if (pci_get_drvdata(pdev)) 2662 device_release_driver(&pdev->dev); 2663 nvme_put_ctrl(&dev->ctrl); 2664 } 2665 2666 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2667 { 2668 *val = readl(to_nvme_dev(ctrl)->bar + off); 2669 return 0; 2670 } 2671 2672 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2673 { 2674 writel(val, to_nvme_dev(ctrl)->bar + off); 2675 return 0; 2676 } 2677 2678 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2679 { 2680 *val = readq(to_nvme_dev(ctrl)->bar + off); 2681 return 0; 2682 } 2683 2684 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2685 { 2686 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2687 2688 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2689 } 2690 2691 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2692 .name = "pcie", 2693 .module = THIS_MODULE, 2694 .flags = NVME_F_METADATA_SUPPORTED | 2695 NVME_F_PCI_P2PDMA, 2696 .reg_read32 = nvme_pci_reg_read32, 2697 .reg_write32 = nvme_pci_reg_write32, 2698 .reg_read64 = nvme_pci_reg_read64, 2699 .free_ctrl = nvme_pci_free_ctrl, 2700 .submit_async_event = nvme_pci_submit_async_event, 2701 .get_address = nvme_pci_get_address, 2702 }; 2703 2704 static int nvme_dev_map(struct nvme_dev *dev) 2705 { 2706 struct pci_dev *pdev = to_pci_dev(dev->dev); 2707 2708 if (pci_request_mem_regions(pdev, "nvme")) 2709 return -ENODEV; 2710 2711 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2712 goto release; 2713 2714 return 0; 2715 release: 2716 pci_release_mem_regions(pdev); 2717 return -ENODEV; 2718 } 2719 2720 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2721 { 2722 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2723 /* 2724 * Several Samsung devices seem to drop off the PCIe bus 2725 * randomly when APST is on and uses the deepest sleep state. 2726 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2727 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2728 * 950 PRO 256GB", but it seems to be restricted to two Dell 2729 * laptops. 2730 */ 2731 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2732 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2733 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2734 return NVME_QUIRK_NO_DEEPEST_PS; 2735 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2736 /* 2737 * Samsung SSD 960 EVO drops off the PCIe bus after system 2738 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2739 * within few minutes after bootup on a Coffee Lake board - 2740 * ASUS PRIME Z370-A 2741 */ 2742 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2743 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2744 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2745 return NVME_QUIRK_NO_APST; 2746 } 2747 2748 return 0; 2749 } 2750 2751 static void nvme_async_probe(void *data, async_cookie_t cookie) 2752 { 2753 struct nvme_dev *dev = data; 2754 2755 nvme_reset_ctrl_sync(&dev->ctrl); 2756 flush_work(&dev->ctrl.scan_work); 2757 nvme_put_ctrl(&dev->ctrl); 2758 } 2759 2760 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2761 { 2762 int node, result = -ENOMEM; 2763 struct nvme_dev *dev; 2764 unsigned long quirks = id->driver_data; 2765 size_t alloc_size; 2766 2767 node = dev_to_node(&pdev->dev); 2768 if (node == NUMA_NO_NODE) 2769 set_dev_node(&pdev->dev, first_memory_node); 2770 2771 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2772 if (!dev) 2773 return -ENOMEM; 2774 2775 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2776 GFP_KERNEL, node); 2777 if (!dev->queues) 2778 goto free; 2779 2780 dev->dev = get_device(&pdev->dev); 2781 pci_set_drvdata(pdev, dev); 2782 2783 result = nvme_dev_map(dev); 2784 if (result) 2785 goto put_pci; 2786 2787 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2788 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2789 mutex_init(&dev->shutdown_lock); 2790 2791 result = nvme_setup_prp_pools(dev); 2792 if (result) 2793 goto unmap; 2794 2795 quirks |= check_vendor_combination_bug(pdev); 2796 2797 /* 2798 * Double check that our mempool alloc size will cover the biggest 2799 * command we support. 2800 */ 2801 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2802 NVME_MAX_SEGS, true); 2803 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2804 2805 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2806 mempool_kfree, 2807 (void *) alloc_size, 2808 GFP_KERNEL, node); 2809 if (!dev->iod_mempool) { 2810 result = -ENOMEM; 2811 goto release_pools; 2812 } 2813 2814 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2815 quirks); 2816 if (result) 2817 goto release_mempool; 2818 2819 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2820 2821 nvme_get_ctrl(&dev->ctrl); 2822 async_schedule(nvme_async_probe, dev); 2823 2824 return 0; 2825 2826 release_mempool: 2827 mempool_destroy(dev->iod_mempool); 2828 release_pools: 2829 nvme_release_prp_pools(dev); 2830 unmap: 2831 nvme_dev_unmap(dev); 2832 put_pci: 2833 put_device(dev->dev); 2834 free: 2835 kfree(dev->queues); 2836 kfree(dev); 2837 return result; 2838 } 2839 2840 static void nvme_reset_prepare(struct pci_dev *pdev) 2841 { 2842 struct nvme_dev *dev = pci_get_drvdata(pdev); 2843 nvme_dev_disable(dev, false); 2844 } 2845 2846 static void nvme_reset_done(struct pci_dev *pdev) 2847 { 2848 struct nvme_dev *dev = pci_get_drvdata(pdev); 2849 nvme_reset_ctrl_sync(&dev->ctrl); 2850 } 2851 2852 static void nvme_shutdown(struct pci_dev *pdev) 2853 { 2854 struct nvme_dev *dev = pci_get_drvdata(pdev); 2855 nvme_dev_disable(dev, true); 2856 } 2857 2858 /* 2859 * The driver's remove may be called on a device in a partially initialized 2860 * state. This function must not have any dependencies on the device state in 2861 * order to proceed. 2862 */ 2863 static void nvme_remove(struct pci_dev *pdev) 2864 { 2865 struct nvme_dev *dev = pci_get_drvdata(pdev); 2866 2867 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2868 pci_set_drvdata(pdev, NULL); 2869 2870 if (!pci_device_is_present(pdev)) { 2871 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2872 nvme_dev_disable(dev, true); 2873 nvme_dev_remove_admin(dev); 2874 } 2875 2876 flush_work(&dev->ctrl.reset_work); 2877 nvme_stop_ctrl(&dev->ctrl); 2878 nvme_remove_namespaces(&dev->ctrl); 2879 nvme_dev_disable(dev, true); 2880 nvme_release_cmb(dev); 2881 nvme_free_host_mem(dev); 2882 nvme_dev_remove_admin(dev); 2883 nvme_free_queues(dev, 0); 2884 nvme_uninit_ctrl(&dev->ctrl); 2885 nvme_release_prp_pools(dev); 2886 nvme_dev_unmap(dev); 2887 nvme_put_ctrl(&dev->ctrl); 2888 } 2889 2890 #ifdef CONFIG_PM_SLEEP 2891 static int nvme_suspend(struct device *dev) 2892 { 2893 struct pci_dev *pdev = to_pci_dev(dev); 2894 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2895 2896 nvme_dev_disable(ndev, true); 2897 return 0; 2898 } 2899 2900 static int nvme_resume(struct device *dev) 2901 { 2902 struct pci_dev *pdev = to_pci_dev(dev); 2903 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2904 2905 nvme_reset_ctrl(&ndev->ctrl); 2906 return 0; 2907 } 2908 #endif 2909 2910 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 2911 2912 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2913 pci_channel_state_t state) 2914 { 2915 struct nvme_dev *dev = pci_get_drvdata(pdev); 2916 2917 /* 2918 * A frozen channel requires a reset. When detected, this method will 2919 * shutdown the controller to quiesce. The controller will be restarted 2920 * after the slot reset through driver's slot_reset callback. 2921 */ 2922 switch (state) { 2923 case pci_channel_io_normal: 2924 return PCI_ERS_RESULT_CAN_RECOVER; 2925 case pci_channel_io_frozen: 2926 dev_warn(dev->ctrl.device, 2927 "frozen state error detected, reset controller\n"); 2928 nvme_dev_disable(dev, false); 2929 return PCI_ERS_RESULT_NEED_RESET; 2930 case pci_channel_io_perm_failure: 2931 dev_warn(dev->ctrl.device, 2932 "failure state error detected, request disconnect\n"); 2933 return PCI_ERS_RESULT_DISCONNECT; 2934 } 2935 return PCI_ERS_RESULT_NEED_RESET; 2936 } 2937 2938 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2939 { 2940 struct nvme_dev *dev = pci_get_drvdata(pdev); 2941 2942 dev_info(dev->ctrl.device, "restart after slot reset\n"); 2943 pci_restore_state(pdev); 2944 nvme_reset_ctrl(&dev->ctrl); 2945 return PCI_ERS_RESULT_RECOVERED; 2946 } 2947 2948 static void nvme_error_resume(struct pci_dev *pdev) 2949 { 2950 struct nvme_dev *dev = pci_get_drvdata(pdev); 2951 2952 flush_work(&dev->ctrl.reset_work); 2953 } 2954 2955 static const struct pci_error_handlers nvme_err_handler = { 2956 .error_detected = nvme_error_detected, 2957 .slot_reset = nvme_slot_reset, 2958 .resume = nvme_error_resume, 2959 .reset_prepare = nvme_reset_prepare, 2960 .reset_done = nvme_reset_done, 2961 }; 2962 2963 static const struct pci_device_id nvme_id_table[] = { 2964 { PCI_VDEVICE(INTEL, 0x0953), 2965 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2966 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2967 { PCI_VDEVICE(INTEL, 0x0a53), 2968 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2969 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2970 { PCI_VDEVICE(INTEL, 0x0a54), 2971 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2972 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2973 { PCI_VDEVICE(INTEL, 0x0a55), 2974 .driver_data = NVME_QUIRK_STRIPE_SIZE | 2975 NVME_QUIRK_DEALLOCATE_ZEROES, }, 2976 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 2977 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 2978 NVME_QUIRK_MEDIUM_PRIO_SQ }, 2979 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 2980 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2981 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2982 .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 2983 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 2984 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2985 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 2986 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2987 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 2988 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2989 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2990 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2991 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2992 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2993 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2994 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2995 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2996 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2997 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2998 .driver_data = NVME_QUIRK_LIGHTNVM, }, 2999 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3000 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3001 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3002 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3003 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3004 { 0, } 3005 }; 3006 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3007 3008 static struct pci_driver nvme_driver = { 3009 .name = "nvme", 3010 .id_table = nvme_id_table, 3011 .probe = nvme_probe, 3012 .remove = nvme_remove, 3013 .shutdown = nvme_shutdown, 3014 .driver = { 3015 .pm = &nvme_dev_pm_ops, 3016 }, 3017 .sriov_configure = pci_sriov_configure_simple, 3018 .err_handler = &nvme_err_handler, 3019 }; 3020 3021 static int __init nvme_init(void) 3022 { 3023 return pci_register_driver(&nvme_driver); 3024 } 3025 3026 static void __exit nvme_exit(void) 3027 { 3028 pci_unregister_driver(&nvme_driver); 3029 flush_workqueue(nvme_wq); 3030 _nvme_check_size(); 3031 } 3032 3033 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3034 MODULE_LICENSE("GPL"); 3035 MODULE_VERSION("1.0"); 3036 module_init(nvme_init); 3037 module_exit(nvme_exit); 3038