1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/aer.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/dmi.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/mm.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/once.h> 20 #include <linux/pci.h> 21 #include <linux/suspend.h> 22 #include <linux/t10-pi.h> 23 #include <linux/types.h> 24 #include <linux/io-64-nonatomic-lo-hi.h> 25 #include <linux/sed-opal.h> 26 #include <linux/pci-p2pdma.h> 27 28 #include "trace.h" 29 #include "nvme.h" 30 31 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 32 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 33 34 #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35 36 /* 37 * These can be higher, but we need to ensure that any command doesn't 38 * require an sg allocation that needs more than a page of data. 39 */ 40 #define NVME_MAX_KB_SZ 4096 41 #define NVME_MAX_SEGS 127 42 43 static int use_threaded_interrupts; 44 module_param(use_threaded_interrupts, int, 0); 45 46 static bool use_cmb_sqes = true; 47 module_param(use_cmb_sqes, bool, 0444); 48 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 49 50 static unsigned int max_host_mem_size_mb = 128; 51 module_param(max_host_mem_size_mb, uint, 0444); 52 MODULE_PARM_DESC(max_host_mem_size_mb, 53 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 54 55 static unsigned int sgl_threshold = SZ_32K; 56 module_param(sgl_threshold, uint, 0644); 57 MODULE_PARM_DESC(sgl_threshold, 58 "Use SGLs when average request segment size is larger or equal to " 59 "this size. Use 0 to disable SGLs."); 60 61 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62 static const struct kernel_param_ops io_queue_depth_ops = { 63 .set = io_queue_depth_set, 64 .get = param_get_int, 65 }; 66 67 static int io_queue_depth = 1024; 68 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70 71 static int write_queues; 72 module_param(write_queues, int, 0644); 73 MODULE_PARM_DESC(write_queues, 74 "Number of queues to use for writes. If not set, reads and writes " 75 "will share a queue set."); 76 77 static int poll_queues; 78 module_param(poll_queues, int, 0644); 79 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 80 81 struct nvme_dev; 82 struct nvme_queue; 83 84 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 85 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 86 87 /* 88 * Represents an NVM Express device. Each nvme_dev is a PCI function. 89 */ 90 struct nvme_dev { 91 struct nvme_queue *queues; 92 struct blk_mq_tag_set tagset; 93 struct blk_mq_tag_set admin_tagset; 94 u32 __iomem *dbs; 95 struct device *dev; 96 struct dma_pool *prp_page_pool; 97 struct dma_pool *prp_small_pool; 98 unsigned online_queues; 99 unsigned max_qid; 100 unsigned io_queues[HCTX_MAX_TYPES]; 101 unsigned int num_vecs; 102 int q_depth; 103 int io_sqes; 104 u32 db_stride; 105 void __iomem *bar; 106 unsigned long bar_mapped_size; 107 struct work_struct remove_work; 108 struct mutex shutdown_lock; 109 bool subsystem; 110 u64 cmb_size; 111 bool cmb_use_sqes; 112 u32 cmbsz; 113 u32 cmbloc; 114 struct nvme_ctrl ctrl; 115 u32 last_ps; 116 117 mempool_t *iod_mempool; 118 119 /* shadow doorbell buffer support: */ 120 u32 *dbbuf_dbs; 121 dma_addr_t dbbuf_dbs_dma_addr; 122 u32 *dbbuf_eis; 123 dma_addr_t dbbuf_eis_dma_addr; 124 125 /* host memory buffer support: */ 126 u64 host_mem_size; 127 u32 nr_host_mem_descs; 128 dma_addr_t host_mem_descs_dma; 129 struct nvme_host_mem_buf_desc *host_mem_descs; 130 void **host_mem_desc_bufs; 131 }; 132 133 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134 { 135 int n = 0, ret; 136 137 ret = kstrtoint(val, 10, &n); 138 if (ret != 0 || n < 2) 139 return -EINVAL; 140 141 return param_set_int(val, kp); 142 } 143 144 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145 { 146 return qid * 2 * stride; 147 } 148 149 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150 { 151 return (qid * 2 + 1) * stride; 152 } 153 154 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 155 { 156 return container_of(ctrl, struct nvme_dev, ctrl); 157 } 158 159 /* 160 * An NVM Express queue. Each device has at least two (one for admin 161 * commands and one for I/O commands). 162 */ 163 struct nvme_queue { 164 struct nvme_dev *dev; 165 spinlock_t sq_lock; 166 void *sq_cmds; 167 /* only used for poll queues: */ 168 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 169 volatile struct nvme_completion *cqes; 170 struct blk_mq_tags **tags; 171 dma_addr_t sq_dma_addr; 172 dma_addr_t cq_dma_addr; 173 u32 __iomem *q_db; 174 u16 q_depth; 175 u16 cq_vector; 176 u16 sq_tail; 177 u16 last_sq_tail; 178 u16 cq_head; 179 u16 last_cq_head; 180 u16 qid; 181 u8 cq_phase; 182 u8 sqes; 183 unsigned long flags; 184 #define NVMEQ_ENABLED 0 185 #define NVMEQ_SQ_CMB 1 186 #define NVMEQ_DELETE_ERROR 2 187 #define NVMEQ_POLLED 3 188 u32 *dbbuf_sq_db; 189 u32 *dbbuf_cq_db; 190 u32 *dbbuf_sq_ei; 191 u32 *dbbuf_cq_ei; 192 struct completion delete_done; 193 }; 194 195 /* 196 * The nvme_iod describes the data in an I/O. 197 * 198 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 199 * to the actual struct scatterlist. 200 */ 201 struct nvme_iod { 202 struct nvme_request req; 203 struct nvme_queue *nvmeq; 204 bool use_sgl; 205 int aborted; 206 int npages; /* In the PRP list. 0 means small pool in use */ 207 int nents; /* Used in scatterlist */ 208 dma_addr_t first_dma; 209 unsigned int dma_len; /* length of single DMA segment mapping */ 210 dma_addr_t meta_dma; 211 struct scatterlist *sg; 212 }; 213 214 static unsigned int max_io_queues(void) 215 { 216 return num_possible_cpus() + write_queues + poll_queues; 217 } 218 219 static unsigned int max_queue_count(void) 220 { 221 /* IO queues + admin queue */ 222 return 1 + max_io_queues(); 223 } 224 225 static inline unsigned int nvme_dbbuf_size(u32 stride) 226 { 227 return (max_queue_count() * 8 * stride); 228 } 229 230 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 231 { 232 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 233 234 if (dev->dbbuf_dbs) 235 return 0; 236 237 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 238 &dev->dbbuf_dbs_dma_addr, 239 GFP_KERNEL); 240 if (!dev->dbbuf_dbs) 241 return -ENOMEM; 242 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 243 &dev->dbbuf_eis_dma_addr, 244 GFP_KERNEL); 245 if (!dev->dbbuf_eis) { 246 dma_free_coherent(dev->dev, mem_size, 247 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 248 dev->dbbuf_dbs = NULL; 249 return -ENOMEM; 250 } 251 252 return 0; 253 } 254 255 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 256 { 257 unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 258 259 if (dev->dbbuf_dbs) { 260 dma_free_coherent(dev->dev, mem_size, 261 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 262 dev->dbbuf_dbs = NULL; 263 } 264 if (dev->dbbuf_eis) { 265 dma_free_coherent(dev->dev, mem_size, 266 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 267 dev->dbbuf_eis = NULL; 268 } 269 } 270 271 static void nvme_dbbuf_init(struct nvme_dev *dev, 272 struct nvme_queue *nvmeq, int qid) 273 { 274 if (!dev->dbbuf_dbs || !qid) 275 return; 276 277 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 278 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 279 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 280 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 281 } 282 283 static void nvme_dbbuf_set(struct nvme_dev *dev) 284 { 285 struct nvme_command c; 286 287 if (!dev->dbbuf_dbs) 288 return; 289 290 memset(&c, 0, sizeof(c)); 291 c.dbbuf.opcode = nvme_admin_dbbuf; 292 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 293 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 294 295 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 296 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 297 /* Free memory and continue on */ 298 nvme_dbbuf_dma_free(dev); 299 } 300 } 301 302 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 303 { 304 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 305 } 306 307 /* Update dbbuf and return true if an MMIO is required */ 308 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 309 volatile u32 *dbbuf_ei) 310 { 311 if (dbbuf_db) { 312 u16 old_value; 313 314 /* 315 * Ensure that the queue is written before updating 316 * the doorbell in memory 317 */ 318 wmb(); 319 320 old_value = *dbbuf_db; 321 *dbbuf_db = value; 322 323 /* 324 * Ensure that the doorbell is updated before reading the event 325 * index from memory. The controller needs to provide similar 326 * ordering to ensure the envent index is updated before reading 327 * the doorbell. 328 */ 329 mb(); 330 331 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 332 return false; 333 } 334 335 return true; 336 } 337 338 /* 339 * Will slightly overestimate the number of pages needed. This is OK 340 * as it only leads to a small amount of wasted memory for the lifetime of 341 * the I/O. 342 */ 343 static int nvme_npages(unsigned size, struct nvme_dev *dev) 344 { 345 unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 346 dev->ctrl.page_size); 347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 348 } 349 350 /* 351 * Calculates the number of pages needed for the SGL segments. For example a 4k 352 * page can accommodate 256 SGL descriptors. 353 */ 354 static int nvme_pci_npages_sgl(unsigned int num_seg) 355 { 356 return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 357 } 358 359 static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 360 unsigned int size, unsigned int nseg, bool use_sgl) 361 { 362 size_t alloc_size; 363 364 if (use_sgl) 365 alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 366 else 367 alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 368 369 return alloc_size + sizeof(struct scatterlist) * nseg; 370 } 371 372 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 373 unsigned int hctx_idx) 374 { 375 struct nvme_dev *dev = data; 376 struct nvme_queue *nvmeq = &dev->queues[0]; 377 378 WARN_ON(hctx_idx != 0); 379 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 380 WARN_ON(nvmeq->tags); 381 382 hctx->driver_data = nvmeq; 383 nvmeq->tags = &dev->admin_tagset.tags[0]; 384 return 0; 385 } 386 387 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 388 { 389 struct nvme_queue *nvmeq = hctx->driver_data; 390 391 nvmeq->tags = NULL; 392 } 393 394 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 395 unsigned int hctx_idx) 396 { 397 struct nvme_dev *dev = data; 398 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 399 400 if (!nvmeq->tags) 401 nvmeq->tags = &dev->tagset.tags[hctx_idx]; 402 403 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 404 hctx->driver_data = nvmeq; 405 return 0; 406 } 407 408 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 409 unsigned int hctx_idx, unsigned int numa_node) 410 { 411 struct nvme_dev *dev = set->driver_data; 412 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 413 int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 414 struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 415 416 BUG_ON(!nvmeq); 417 iod->nvmeq = nvmeq; 418 419 nvme_req(req)->ctrl = &dev->ctrl; 420 return 0; 421 } 422 423 static int queue_irq_offset(struct nvme_dev *dev) 424 { 425 /* if we have more than 1 vec, admin queue offsets us by 1 */ 426 if (dev->num_vecs > 1) 427 return 1; 428 429 return 0; 430 } 431 432 static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 433 { 434 struct nvme_dev *dev = set->driver_data; 435 int i, qoff, offset; 436 437 offset = queue_irq_offset(dev); 438 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 439 struct blk_mq_queue_map *map = &set->map[i]; 440 441 map->nr_queues = dev->io_queues[i]; 442 if (!map->nr_queues) { 443 BUG_ON(i == HCTX_TYPE_DEFAULT); 444 continue; 445 } 446 447 /* 448 * The poll queue(s) doesn't have an IRQ (and hence IRQ 449 * affinity), so use the regular blk-mq cpu mapping 450 */ 451 map->queue_offset = qoff; 452 if (i != HCTX_TYPE_POLL && offset) 453 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 454 else 455 blk_mq_map_queues(map); 456 qoff += map->nr_queues; 457 offset += map->nr_queues; 458 } 459 460 return 0; 461 } 462 463 /* 464 * Write sq tail if we are asked to, or if the next command would wrap. 465 */ 466 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 467 { 468 if (!write_sq) { 469 u16 next_tail = nvmeq->sq_tail + 1; 470 471 if (next_tail == nvmeq->q_depth) 472 next_tail = 0; 473 if (next_tail != nvmeq->last_sq_tail) 474 return; 475 } 476 477 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 478 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 479 writel(nvmeq->sq_tail, nvmeq->q_db); 480 nvmeq->last_sq_tail = nvmeq->sq_tail; 481 } 482 483 /** 484 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 485 * @nvmeq: The queue to use 486 * @cmd: The command to send 487 * @write_sq: whether to write to the SQ doorbell 488 */ 489 static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 490 bool write_sq) 491 { 492 spin_lock(&nvmeq->sq_lock); 493 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 494 cmd, sizeof(*cmd)); 495 if (++nvmeq->sq_tail == nvmeq->q_depth) 496 nvmeq->sq_tail = 0; 497 nvme_write_sq_db(nvmeq, write_sq); 498 spin_unlock(&nvmeq->sq_lock); 499 } 500 501 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 502 { 503 struct nvme_queue *nvmeq = hctx->driver_data; 504 505 spin_lock(&nvmeq->sq_lock); 506 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 507 nvme_write_sq_db(nvmeq, true); 508 spin_unlock(&nvmeq->sq_lock); 509 } 510 511 static void **nvme_pci_iod_list(struct request *req) 512 { 513 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514 return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 515 } 516 517 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518 { 519 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 520 int nseg = blk_rq_nr_phys_segments(req); 521 unsigned int avg_seg_size; 522 523 if (nseg == 0) 524 return false; 525 526 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 527 528 if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 529 return false; 530 if (!iod->nvmeq->qid) 531 return false; 532 if (!sgl_threshold || avg_seg_size < sgl_threshold) 533 return false; 534 return true; 535 } 536 537 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 538 { 539 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 540 const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 541 dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 542 int i; 543 544 if (iod->dma_len) { 545 dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 546 rq_dma_dir(req)); 547 return; 548 } 549 550 WARN_ON_ONCE(!iod->nents); 551 552 if (is_pci_p2pdma_page(sg_page(iod->sg))) 553 pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 554 rq_dma_dir(req)); 555 else 556 dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 557 558 559 if (iod->npages == 0) 560 dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 561 dma_addr); 562 563 for (i = 0; i < iod->npages; i++) { 564 void *addr = nvme_pci_iod_list(req)[i]; 565 566 if (iod->use_sgl) { 567 struct nvme_sgl_desc *sg_list = addr; 568 569 next_dma_addr = 570 le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 571 } else { 572 __le64 *prp_list = addr; 573 574 next_dma_addr = le64_to_cpu(prp_list[last_prp]); 575 } 576 577 dma_pool_free(dev->prp_page_pool, addr, dma_addr); 578 dma_addr = next_dma_addr; 579 } 580 581 mempool_free(iod->sg, dev->iod_mempool); 582 } 583 584 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 585 { 586 int i; 587 struct scatterlist *sg; 588 589 for_each_sg(sgl, sg, nents, i) { 590 dma_addr_t phys = sg_phys(sg); 591 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 592 "dma_address:%pad dma_length:%d\n", 593 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 594 sg_dma_len(sg)); 595 } 596 } 597 598 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 599 struct request *req, struct nvme_rw_command *cmnd) 600 { 601 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 602 struct dma_pool *pool; 603 int length = blk_rq_payload_bytes(req); 604 struct scatterlist *sg = iod->sg; 605 int dma_len = sg_dma_len(sg); 606 u64 dma_addr = sg_dma_address(sg); 607 u32 page_size = dev->ctrl.page_size; 608 int offset = dma_addr & (page_size - 1); 609 __le64 *prp_list; 610 void **list = nvme_pci_iod_list(req); 611 dma_addr_t prp_dma; 612 int nprps, i; 613 614 length -= (page_size - offset); 615 if (length <= 0) { 616 iod->first_dma = 0; 617 goto done; 618 } 619 620 dma_len -= (page_size - offset); 621 if (dma_len) { 622 dma_addr += (page_size - offset); 623 } else { 624 sg = sg_next(sg); 625 dma_addr = sg_dma_address(sg); 626 dma_len = sg_dma_len(sg); 627 } 628 629 if (length <= page_size) { 630 iod->first_dma = dma_addr; 631 goto done; 632 } 633 634 nprps = DIV_ROUND_UP(length, page_size); 635 if (nprps <= (256 / 8)) { 636 pool = dev->prp_small_pool; 637 iod->npages = 0; 638 } else { 639 pool = dev->prp_page_pool; 640 iod->npages = 1; 641 } 642 643 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 644 if (!prp_list) { 645 iod->first_dma = dma_addr; 646 iod->npages = -1; 647 return BLK_STS_RESOURCE; 648 } 649 list[0] = prp_list; 650 iod->first_dma = prp_dma; 651 i = 0; 652 for (;;) { 653 if (i == page_size >> 3) { 654 __le64 *old_prp_list = prp_list; 655 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 656 if (!prp_list) 657 return BLK_STS_RESOURCE; 658 list[iod->npages++] = prp_list; 659 prp_list[0] = old_prp_list[i - 1]; 660 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 661 i = 1; 662 } 663 prp_list[i++] = cpu_to_le64(dma_addr); 664 dma_len -= page_size; 665 dma_addr += page_size; 666 length -= page_size; 667 if (length <= 0) 668 break; 669 if (dma_len > 0) 670 continue; 671 if (unlikely(dma_len < 0)) 672 goto bad_sgl; 673 sg = sg_next(sg); 674 dma_addr = sg_dma_address(sg); 675 dma_len = sg_dma_len(sg); 676 } 677 678 done: 679 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 680 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 681 682 return BLK_STS_OK; 683 684 bad_sgl: 685 WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 686 "Invalid SGL for payload:%d nents:%d\n", 687 blk_rq_payload_bytes(req), iod->nents); 688 return BLK_STS_IOERR; 689 } 690 691 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 692 struct scatterlist *sg) 693 { 694 sge->addr = cpu_to_le64(sg_dma_address(sg)); 695 sge->length = cpu_to_le32(sg_dma_len(sg)); 696 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 697 } 698 699 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 700 dma_addr_t dma_addr, int entries) 701 { 702 sge->addr = cpu_to_le64(dma_addr); 703 if (entries < SGES_PER_PAGE) { 704 sge->length = cpu_to_le32(entries * sizeof(*sge)); 705 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 706 } else { 707 sge->length = cpu_to_le32(PAGE_SIZE); 708 sge->type = NVME_SGL_FMT_SEG_DESC << 4; 709 } 710 } 711 712 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 713 struct request *req, struct nvme_rw_command *cmd, int entries) 714 { 715 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 716 struct dma_pool *pool; 717 struct nvme_sgl_desc *sg_list; 718 struct scatterlist *sg = iod->sg; 719 dma_addr_t sgl_dma; 720 int i = 0; 721 722 /* setting the transfer type as SGL */ 723 cmd->flags = NVME_CMD_SGL_METABUF; 724 725 if (entries == 1) { 726 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 727 return BLK_STS_OK; 728 } 729 730 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 731 pool = dev->prp_small_pool; 732 iod->npages = 0; 733 } else { 734 pool = dev->prp_page_pool; 735 iod->npages = 1; 736 } 737 738 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 739 if (!sg_list) { 740 iod->npages = -1; 741 return BLK_STS_RESOURCE; 742 } 743 744 nvme_pci_iod_list(req)[0] = sg_list; 745 iod->first_dma = sgl_dma; 746 747 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 748 749 do { 750 if (i == SGES_PER_PAGE) { 751 struct nvme_sgl_desc *old_sg_desc = sg_list; 752 struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 753 754 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 755 if (!sg_list) 756 return BLK_STS_RESOURCE; 757 758 i = 0; 759 nvme_pci_iod_list(req)[iod->npages++] = sg_list; 760 sg_list[i++] = *link; 761 nvme_pci_sgl_set_seg(link, sgl_dma, entries); 762 } 763 764 nvme_pci_sgl_set_data(&sg_list[i++], sg); 765 sg = sg_next(sg); 766 } while (--entries > 0); 767 768 return BLK_STS_OK; 769 } 770 771 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 772 struct request *req, struct nvme_rw_command *cmnd, 773 struct bio_vec *bv) 774 { 775 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 776 unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 777 unsigned int first_prp_len = dev->ctrl.page_size - offset; 778 779 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 780 if (dma_mapping_error(dev->dev, iod->first_dma)) 781 return BLK_STS_RESOURCE; 782 iod->dma_len = bv->bv_len; 783 784 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 785 if (bv->bv_len > first_prp_len) 786 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 787 return 0; 788 } 789 790 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 791 struct request *req, struct nvme_rw_command *cmnd, 792 struct bio_vec *bv) 793 { 794 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 795 796 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 797 if (dma_mapping_error(dev->dev, iod->first_dma)) 798 return BLK_STS_RESOURCE; 799 iod->dma_len = bv->bv_len; 800 801 cmnd->flags = NVME_CMD_SGL_METABUF; 802 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 803 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 804 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 805 return 0; 806 } 807 808 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 809 struct nvme_command *cmnd) 810 { 811 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 812 blk_status_t ret = BLK_STS_RESOURCE; 813 int nr_mapped; 814 815 if (blk_rq_nr_phys_segments(req) == 1) { 816 struct bio_vec bv = req_bvec(req); 817 818 if (!is_pci_p2pdma_page(bv.bv_page)) { 819 if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 820 return nvme_setup_prp_simple(dev, req, 821 &cmnd->rw, &bv); 822 823 if (iod->nvmeq->qid && 824 dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 825 return nvme_setup_sgl_simple(dev, req, 826 &cmnd->rw, &bv); 827 } 828 } 829 830 iod->dma_len = 0; 831 iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 832 if (!iod->sg) 833 return BLK_STS_RESOURCE; 834 sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 835 iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 836 if (!iod->nents) 837 goto out; 838 839 if (is_pci_p2pdma_page(sg_page(iod->sg))) 840 nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 841 iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 842 else 843 nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 844 rq_dma_dir(req), DMA_ATTR_NO_WARN); 845 if (!nr_mapped) 846 goto out; 847 848 iod->use_sgl = nvme_pci_use_sgls(dev, req); 849 if (iod->use_sgl) 850 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 851 else 852 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 853 out: 854 if (ret != BLK_STS_OK) 855 nvme_unmap_data(dev, req); 856 return ret; 857 } 858 859 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 860 struct nvme_command *cmnd) 861 { 862 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 863 864 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 865 rq_dma_dir(req), 0); 866 if (dma_mapping_error(dev->dev, iod->meta_dma)) 867 return BLK_STS_IOERR; 868 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 869 return 0; 870 } 871 872 /* 873 * NOTE: ns is NULL when called on the admin queue. 874 */ 875 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 876 const struct blk_mq_queue_data *bd) 877 { 878 struct nvme_ns *ns = hctx->queue->queuedata; 879 struct nvme_queue *nvmeq = hctx->driver_data; 880 struct nvme_dev *dev = nvmeq->dev; 881 struct request *req = bd->rq; 882 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 883 struct nvme_command cmnd; 884 blk_status_t ret; 885 886 iod->aborted = 0; 887 iod->npages = -1; 888 iod->nents = 0; 889 890 /* 891 * We should not need to do this, but we're still using this to 892 * ensure we can drain requests on a dying queue. 893 */ 894 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 895 return BLK_STS_IOERR; 896 897 ret = nvme_setup_cmd(ns, req, &cmnd); 898 if (ret) 899 return ret; 900 901 if (blk_rq_nr_phys_segments(req)) { 902 ret = nvme_map_data(dev, req, &cmnd); 903 if (ret) 904 goto out_free_cmd; 905 } 906 907 if (blk_integrity_rq(req)) { 908 ret = nvme_map_metadata(dev, req, &cmnd); 909 if (ret) 910 goto out_unmap_data; 911 } 912 913 blk_mq_start_request(req); 914 nvme_submit_cmd(nvmeq, &cmnd, bd->last); 915 return BLK_STS_OK; 916 out_unmap_data: 917 nvme_unmap_data(dev, req); 918 out_free_cmd: 919 nvme_cleanup_cmd(req); 920 return ret; 921 } 922 923 static void nvme_pci_complete_rq(struct request *req) 924 { 925 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 926 struct nvme_dev *dev = iod->nvmeq->dev; 927 928 nvme_cleanup_cmd(req); 929 if (blk_integrity_rq(req)) 930 dma_unmap_page(dev->dev, iod->meta_dma, 931 rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 932 if (blk_rq_nr_phys_segments(req)) 933 nvme_unmap_data(dev, req); 934 nvme_complete_rq(req); 935 } 936 937 /* We read the CQE phase first to check if the rest of the entry is valid */ 938 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 939 { 940 return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 941 nvmeq->cq_phase; 942 } 943 944 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 945 { 946 u16 head = nvmeq->cq_head; 947 948 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 949 nvmeq->dbbuf_cq_ei)) 950 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 951 } 952 953 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 954 { 955 volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 956 struct request *req; 957 958 if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 959 dev_warn(nvmeq->dev->ctrl.device, 960 "invalid id %d completed on queue %d\n", 961 cqe->command_id, le16_to_cpu(cqe->sq_id)); 962 return; 963 } 964 965 /* 966 * AEN requests are special as they don't time out and can 967 * survive any kind of queue freeze and often don't respond to 968 * aborts. We don't even bother to allocate a struct request 969 * for them but rather special case them here. 970 */ 971 if (unlikely(nvmeq->qid == 0 && 972 cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 973 nvme_complete_async_event(&nvmeq->dev->ctrl, 974 cqe->status, &cqe->result); 975 return; 976 } 977 978 req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 979 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 980 nvme_end_request(req, cqe->status, cqe->result); 981 } 982 983 static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 984 { 985 while (start != end) { 986 nvme_handle_cqe(nvmeq, start); 987 if (++start == nvmeq->q_depth) 988 start = 0; 989 } 990 } 991 992 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 993 { 994 if (nvmeq->cq_head == nvmeq->q_depth - 1) { 995 nvmeq->cq_head = 0; 996 nvmeq->cq_phase = !nvmeq->cq_phase; 997 } else { 998 nvmeq->cq_head++; 999 } 1000 } 1001 1002 static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 1003 u16 *end, unsigned int tag) 1004 { 1005 int found = 0; 1006 1007 *start = nvmeq->cq_head; 1008 while (nvme_cqe_pending(nvmeq)) { 1009 if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 1010 found++; 1011 nvme_update_cq_head(nvmeq); 1012 } 1013 *end = nvmeq->cq_head; 1014 1015 if (*start != *end) 1016 nvme_ring_cq_doorbell(nvmeq); 1017 return found; 1018 } 1019 1020 static irqreturn_t nvme_irq(int irq, void *data) 1021 { 1022 struct nvme_queue *nvmeq = data; 1023 irqreturn_t ret = IRQ_NONE; 1024 u16 start, end; 1025 1026 /* 1027 * The rmb/wmb pair ensures we see all updates from a previous run of 1028 * the irq handler, even if that was on another CPU. 1029 */ 1030 rmb(); 1031 if (nvmeq->cq_head != nvmeq->last_cq_head) 1032 ret = IRQ_HANDLED; 1033 nvme_process_cq(nvmeq, &start, &end, -1); 1034 nvmeq->last_cq_head = nvmeq->cq_head; 1035 wmb(); 1036 1037 if (start != end) { 1038 nvme_complete_cqes(nvmeq, start, end); 1039 return IRQ_HANDLED; 1040 } 1041 1042 return ret; 1043 } 1044 1045 static irqreturn_t nvme_irq_check(int irq, void *data) 1046 { 1047 struct nvme_queue *nvmeq = data; 1048 if (nvme_cqe_pending(nvmeq)) 1049 return IRQ_WAKE_THREAD; 1050 return IRQ_NONE; 1051 } 1052 1053 /* 1054 * Poll for completions any queue, including those not dedicated to polling. 1055 * Can be called from any context. 1056 */ 1057 static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1058 { 1059 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1060 u16 start, end; 1061 int found; 1062 1063 /* 1064 * For a poll queue we need to protect against the polling thread 1065 * using the CQ lock. For normal interrupt driven threads we have 1066 * to disable the interrupt to avoid racing with it. 1067 */ 1068 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 1069 spin_lock(&nvmeq->cq_poll_lock); 1070 found = nvme_process_cq(nvmeq, &start, &end, tag); 1071 spin_unlock(&nvmeq->cq_poll_lock); 1072 } else { 1073 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1074 found = nvme_process_cq(nvmeq, &start, &end, tag); 1075 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1076 } 1077 1078 nvme_complete_cqes(nvmeq, start, end); 1079 return found; 1080 } 1081 1082 static int nvme_poll(struct blk_mq_hw_ctx *hctx) 1083 { 1084 struct nvme_queue *nvmeq = hctx->driver_data; 1085 u16 start, end; 1086 bool found; 1087 1088 if (!nvme_cqe_pending(nvmeq)) 1089 return 0; 1090 1091 spin_lock(&nvmeq->cq_poll_lock); 1092 found = nvme_process_cq(nvmeq, &start, &end, -1); 1093 spin_unlock(&nvmeq->cq_poll_lock); 1094 1095 nvme_complete_cqes(nvmeq, start, end); 1096 return found; 1097 } 1098 1099 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1100 { 1101 struct nvme_dev *dev = to_nvme_dev(ctrl); 1102 struct nvme_queue *nvmeq = &dev->queues[0]; 1103 struct nvme_command c; 1104 1105 memset(&c, 0, sizeof(c)); 1106 c.common.opcode = nvme_admin_async_event; 1107 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1108 nvme_submit_cmd(nvmeq, &c, true); 1109 } 1110 1111 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1112 { 1113 struct nvme_command c; 1114 1115 memset(&c, 0, sizeof(c)); 1116 c.delete_queue.opcode = opcode; 1117 c.delete_queue.qid = cpu_to_le16(id); 1118 1119 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1120 } 1121 1122 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1123 struct nvme_queue *nvmeq, s16 vector) 1124 { 1125 struct nvme_command c; 1126 int flags = NVME_QUEUE_PHYS_CONTIG; 1127 1128 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1129 flags |= NVME_CQ_IRQ_ENABLED; 1130 1131 /* 1132 * Note: we (ab)use the fact that the prp fields survive if no data 1133 * is attached to the request. 1134 */ 1135 memset(&c, 0, sizeof(c)); 1136 c.create_cq.opcode = nvme_admin_create_cq; 1137 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1138 c.create_cq.cqid = cpu_to_le16(qid); 1139 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1140 c.create_cq.cq_flags = cpu_to_le16(flags); 1141 c.create_cq.irq_vector = cpu_to_le16(vector); 1142 1143 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1144 } 1145 1146 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1147 struct nvme_queue *nvmeq) 1148 { 1149 struct nvme_ctrl *ctrl = &dev->ctrl; 1150 struct nvme_command c; 1151 int flags = NVME_QUEUE_PHYS_CONTIG; 1152 1153 /* 1154 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1155 * set. Since URGENT priority is zeroes, it makes all queues 1156 * URGENT. 1157 */ 1158 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1159 flags |= NVME_SQ_PRIO_MEDIUM; 1160 1161 /* 1162 * Note: we (ab)use the fact that the prp fields survive if no data 1163 * is attached to the request. 1164 */ 1165 memset(&c, 0, sizeof(c)); 1166 c.create_sq.opcode = nvme_admin_create_sq; 1167 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1168 c.create_sq.sqid = cpu_to_le16(qid); 1169 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1170 c.create_sq.sq_flags = cpu_to_le16(flags); 1171 c.create_sq.cqid = cpu_to_le16(qid); 1172 1173 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1174 } 1175 1176 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1177 { 1178 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1179 } 1180 1181 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1182 { 1183 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1184 } 1185 1186 static void abort_endio(struct request *req, blk_status_t error) 1187 { 1188 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1189 struct nvme_queue *nvmeq = iod->nvmeq; 1190 1191 dev_warn(nvmeq->dev->ctrl.device, 1192 "Abort status: 0x%x", nvme_req(req)->status); 1193 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1194 blk_mq_free_request(req); 1195 } 1196 1197 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1198 { 1199 1200 /* If true, indicates loss of adapter communication, possibly by a 1201 * NVMe Subsystem reset. 1202 */ 1203 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1204 1205 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1206 switch (dev->ctrl.state) { 1207 case NVME_CTRL_RESETTING: 1208 case NVME_CTRL_CONNECTING: 1209 return false; 1210 default: 1211 break; 1212 } 1213 1214 /* We shouldn't reset unless the controller is on fatal error state 1215 * _or_ if we lost the communication with it. 1216 */ 1217 if (!(csts & NVME_CSTS_CFS) && !nssro) 1218 return false; 1219 1220 return true; 1221 } 1222 1223 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1224 { 1225 /* Read a config register to help see what died. */ 1226 u16 pci_status; 1227 int result; 1228 1229 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1230 &pci_status); 1231 if (result == PCIBIOS_SUCCESSFUL) 1232 dev_warn(dev->ctrl.device, 1233 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1234 csts, pci_status); 1235 else 1236 dev_warn(dev->ctrl.device, 1237 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1238 csts, result); 1239 } 1240 1241 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 1242 { 1243 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1244 struct nvme_queue *nvmeq = iod->nvmeq; 1245 struct nvme_dev *dev = nvmeq->dev; 1246 struct request *abort_req; 1247 struct nvme_command cmd; 1248 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1249 1250 /* If PCI error recovery process is happening, we cannot reset or 1251 * the recovery mechanism will surely fail. 1252 */ 1253 mb(); 1254 if (pci_channel_offline(to_pci_dev(dev->dev))) 1255 return BLK_EH_RESET_TIMER; 1256 1257 /* 1258 * Reset immediately if the controller is failed 1259 */ 1260 if (nvme_should_reset(dev, csts)) { 1261 nvme_warn_reset(dev, csts); 1262 nvme_dev_disable(dev, false); 1263 nvme_reset_ctrl(&dev->ctrl); 1264 return BLK_EH_DONE; 1265 } 1266 1267 /* 1268 * Did we miss an interrupt? 1269 */ 1270 if (nvme_poll_irqdisable(nvmeq, req->tag)) { 1271 dev_warn(dev->ctrl.device, 1272 "I/O %d QID %d timeout, completion polled\n", 1273 req->tag, nvmeq->qid); 1274 return BLK_EH_DONE; 1275 } 1276 1277 /* 1278 * Shutdown immediately if controller times out while starting. The 1279 * reset work will see the pci device disabled when it gets the forced 1280 * cancellation error. All outstanding requests are completed on 1281 * shutdown, so we return BLK_EH_DONE. 1282 */ 1283 switch (dev->ctrl.state) { 1284 case NVME_CTRL_CONNECTING: 1285 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1286 /* fall through */ 1287 case NVME_CTRL_DELETING: 1288 dev_warn_ratelimited(dev->ctrl.device, 1289 "I/O %d QID %d timeout, disable controller\n", 1290 req->tag, nvmeq->qid); 1291 nvme_dev_disable(dev, true); 1292 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1293 return BLK_EH_DONE; 1294 case NVME_CTRL_RESETTING: 1295 return BLK_EH_RESET_TIMER; 1296 default: 1297 break; 1298 } 1299 1300 /* 1301 * Shutdown the controller immediately and schedule a reset if the 1302 * command was already aborted once before and still hasn't been 1303 * returned to the driver, or if this is the admin queue. 1304 */ 1305 if (!nvmeq->qid || iod->aborted) { 1306 dev_warn(dev->ctrl.device, 1307 "I/O %d QID %d timeout, reset controller\n", 1308 req->tag, nvmeq->qid); 1309 nvme_dev_disable(dev, false); 1310 nvme_reset_ctrl(&dev->ctrl); 1311 1312 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1313 return BLK_EH_DONE; 1314 } 1315 1316 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1317 atomic_inc(&dev->ctrl.abort_limit); 1318 return BLK_EH_RESET_TIMER; 1319 } 1320 iod->aborted = 1; 1321 1322 memset(&cmd, 0, sizeof(cmd)); 1323 cmd.abort.opcode = nvme_admin_abort_cmd; 1324 cmd.abort.cid = req->tag; 1325 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1326 1327 dev_warn(nvmeq->dev->ctrl.device, 1328 "I/O %d QID %d timeout, aborting\n", 1329 req->tag, nvmeq->qid); 1330 1331 abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1332 BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1333 if (IS_ERR(abort_req)) { 1334 atomic_inc(&dev->ctrl.abort_limit); 1335 return BLK_EH_RESET_TIMER; 1336 } 1337 1338 abort_req->timeout = ADMIN_TIMEOUT; 1339 abort_req->end_io_data = NULL; 1340 blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 1341 1342 /* 1343 * The aborted req will be completed on receiving the abort req. 1344 * We enable the timer again. If hit twice, it'll cause a device reset, 1345 * as the device then is in a faulty state. 1346 */ 1347 return BLK_EH_RESET_TIMER; 1348 } 1349 1350 static void nvme_free_queue(struct nvme_queue *nvmeq) 1351 { 1352 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1353 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1354 if (!nvmeq->sq_cmds) 1355 return; 1356 1357 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1358 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1359 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1360 } else { 1361 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1362 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1363 } 1364 } 1365 1366 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1367 { 1368 int i; 1369 1370 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1371 dev->ctrl.queue_count--; 1372 nvme_free_queue(&dev->queues[i]); 1373 } 1374 } 1375 1376 /** 1377 * nvme_suspend_queue - put queue into suspended state 1378 * @nvmeq: queue to suspend 1379 */ 1380 static int nvme_suspend_queue(struct nvme_queue *nvmeq) 1381 { 1382 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1383 return 1; 1384 1385 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1386 mb(); 1387 1388 nvmeq->dev->online_queues--; 1389 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1390 blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 1391 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1392 pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 1393 return 0; 1394 } 1395 1396 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1397 { 1398 int i; 1399 1400 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1401 nvme_suspend_queue(&dev->queues[i]); 1402 } 1403 1404 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 1405 { 1406 struct nvme_queue *nvmeq = &dev->queues[0]; 1407 1408 if (shutdown) 1409 nvme_shutdown_ctrl(&dev->ctrl); 1410 else 1411 nvme_disable_ctrl(&dev->ctrl); 1412 1413 nvme_poll_irqdisable(nvmeq, -1); 1414 } 1415 1416 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1417 int entry_size) 1418 { 1419 int q_depth = dev->q_depth; 1420 unsigned q_size_aligned = roundup(q_depth * entry_size, 1421 dev->ctrl.page_size); 1422 1423 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1424 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1425 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 1426 q_depth = div_u64(mem_per_q, entry_size); 1427 1428 /* 1429 * Ensure the reduced q_depth is above some threshold where it 1430 * would be better to map queues in system memory with the 1431 * original depth 1432 */ 1433 if (q_depth < 64) 1434 return -ENOMEM; 1435 } 1436 1437 return q_depth; 1438 } 1439 1440 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1441 int qid) 1442 { 1443 struct pci_dev *pdev = to_pci_dev(dev->dev); 1444 1445 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1446 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1447 if (nvmeq->sq_cmds) { 1448 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1449 nvmeq->sq_cmds); 1450 if (nvmeq->sq_dma_addr) { 1451 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1452 return 0; 1453 } 1454 1455 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1456 } 1457 } 1458 1459 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1460 &nvmeq->sq_dma_addr, GFP_KERNEL); 1461 if (!nvmeq->sq_cmds) 1462 return -ENOMEM; 1463 return 0; 1464 } 1465 1466 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1467 { 1468 struct nvme_queue *nvmeq = &dev->queues[qid]; 1469 1470 if (dev->ctrl.queue_count > qid) 1471 return 0; 1472 1473 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1474 nvmeq->q_depth = depth; 1475 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1476 &nvmeq->cq_dma_addr, GFP_KERNEL); 1477 if (!nvmeq->cqes) 1478 goto free_nvmeq; 1479 1480 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1481 goto free_cqdma; 1482 1483 nvmeq->dev = dev; 1484 spin_lock_init(&nvmeq->sq_lock); 1485 spin_lock_init(&nvmeq->cq_poll_lock); 1486 nvmeq->cq_head = 0; 1487 nvmeq->cq_phase = 1; 1488 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1489 nvmeq->qid = qid; 1490 dev->ctrl.queue_count++; 1491 1492 return 0; 1493 1494 free_cqdma: 1495 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1496 nvmeq->cq_dma_addr); 1497 free_nvmeq: 1498 return -ENOMEM; 1499 } 1500 1501 static int queue_request_irq(struct nvme_queue *nvmeq) 1502 { 1503 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1504 int nr = nvmeq->dev->ctrl.instance; 1505 1506 if (use_threaded_interrupts) { 1507 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1508 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1509 } else { 1510 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1511 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1512 } 1513 } 1514 1515 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1516 { 1517 struct nvme_dev *dev = nvmeq->dev; 1518 1519 nvmeq->sq_tail = 0; 1520 nvmeq->last_sq_tail = 0; 1521 nvmeq->cq_head = 0; 1522 nvmeq->cq_phase = 1; 1523 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1524 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1525 nvme_dbbuf_init(dev, nvmeq, qid); 1526 dev->online_queues++; 1527 wmb(); /* ensure the first interrupt sees the initialization */ 1528 } 1529 1530 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1531 { 1532 struct nvme_dev *dev = nvmeq->dev; 1533 int result; 1534 u16 vector = 0; 1535 1536 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1537 1538 /* 1539 * A queue's vector matches the queue identifier unless the controller 1540 * has only one vector available. 1541 */ 1542 if (!polled) 1543 vector = dev->num_vecs == 1 ? 0 : qid; 1544 else 1545 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1546 1547 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1548 if (result) 1549 return result; 1550 1551 result = adapter_alloc_sq(dev, qid, nvmeq); 1552 if (result < 0) 1553 return result; 1554 else if (result) 1555 goto release_cq; 1556 1557 nvmeq->cq_vector = vector; 1558 nvme_init_queue(nvmeq, qid); 1559 1560 if (!polled) { 1561 result = queue_request_irq(nvmeq); 1562 if (result < 0) 1563 goto release_sq; 1564 } 1565 1566 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1567 return result; 1568 1569 release_sq: 1570 dev->online_queues--; 1571 adapter_delete_sq(dev, qid); 1572 release_cq: 1573 adapter_delete_cq(dev, qid); 1574 return result; 1575 } 1576 1577 static const struct blk_mq_ops nvme_mq_admin_ops = { 1578 .queue_rq = nvme_queue_rq, 1579 .complete = nvme_pci_complete_rq, 1580 .init_hctx = nvme_admin_init_hctx, 1581 .exit_hctx = nvme_admin_exit_hctx, 1582 .init_request = nvme_init_request, 1583 .timeout = nvme_timeout, 1584 }; 1585 1586 static const struct blk_mq_ops nvme_mq_ops = { 1587 .queue_rq = nvme_queue_rq, 1588 .complete = nvme_pci_complete_rq, 1589 .commit_rqs = nvme_commit_rqs, 1590 .init_hctx = nvme_init_hctx, 1591 .init_request = nvme_init_request, 1592 .map_queues = nvme_pci_map_queues, 1593 .timeout = nvme_timeout, 1594 .poll = nvme_poll, 1595 }; 1596 1597 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1598 { 1599 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1600 /* 1601 * If the controller was reset during removal, it's possible 1602 * user requests may be waiting on a stopped queue. Start the 1603 * queue to flush these to completion. 1604 */ 1605 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1606 blk_cleanup_queue(dev->ctrl.admin_q); 1607 blk_mq_free_tag_set(&dev->admin_tagset); 1608 } 1609 } 1610 1611 static int nvme_alloc_admin_tags(struct nvme_dev *dev) 1612 { 1613 if (!dev->ctrl.admin_q) { 1614 dev->admin_tagset.ops = &nvme_mq_admin_ops; 1615 dev->admin_tagset.nr_hw_queues = 1; 1616 1617 dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1618 dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1619 dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1620 dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1621 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 1622 dev->admin_tagset.driver_data = dev; 1623 1624 if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 1625 return -ENOMEM; 1626 dev->ctrl.admin_tagset = &dev->admin_tagset; 1627 1628 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 1629 if (IS_ERR(dev->ctrl.admin_q)) { 1630 blk_mq_free_tag_set(&dev->admin_tagset); 1631 return -ENOMEM; 1632 } 1633 if (!blk_get_queue(dev->ctrl.admin_q)) { 1634 nvme_dev_remove_admin(dev); 1635 dev->ctrl.admin_q = NULL; 1636 return -ENODEV; 1637 } 1638 } else 1639 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 1640 1641 return 0; 1642 } 1643 1644 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1645 { 1646 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1647 } 1648 1649 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1650 { 1651 struct pci_dev *pdev = to_pci_dev(dev->dev); 1652 1653 if (size <= dev->bar_mapped_size) 1654 return 0; 1655 if (size > pci_resource_len(pdev, 0)) 1656 return -ENOMEM; 1657 if (dev->bar) 1658 iounmap(dev->bar); 1659 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1660 if (!dev->bar) { 1661 dev->bar_mapped_size = 0; 1662 return -ENOMEM; 1663 } 1664 dev->bar_mapped_size = size; 1665 dev->dbs = dev->bar + NVME_REG_DBS; 1666 1667 return 0; 1668 } 1669 1670 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1671 { 1672 int result; 1673 u32 aqa; 1674 struct nvme_queue *nvmeq; 1675 1676 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1677 if (result < 0) 1678 return result; 1679 1680 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1681 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1682 1683 if (dev->subsystem && 1684 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1685 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1686 1687 result = nvme_disable_ctrl(&dev->ctrl); 1688 if (result < 0) 1689 return result; 1690 1691 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1692 if (result) 1693 return result; 1694 1695 nvmeq = &dev->queues[0]; 1696 aqa = nvmeq->q_depth - 1; 1697 aqa |= aqa << 16; 1698 1699 writel(aqa, dev->bar + NVME_REG_AQA); 1700 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1701 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1702 1703 result = nvme_enable_ctrl(&dev->ctrl); 1704 if (result) 1705 return result; 1706 1707 nvmeq->cq_vector = 0; 1708 nvme_init_queue(nvmeq, 0); 1709 result = queue_request_irq(nvmeq); 1710 if (result) { 1711 dev->online_queues--; 1712 return result; 1713 } 1714 1715 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1716 return result; 1717 } 1718 1719 static int nvme_create_io_queues(struct nvme_dev *dev) 1720 { 1721 unsigned i, max, rw_queues; 1722 int ret = 0; 1723 1724 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1725 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1726 ret = -ENOMEM; 1727 break; 1728 } 1729 } 1730 1731 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1732 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1733 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1734 dev->io_queues[HCTX_TYPE_READ]; 1735 } else { 1736 rw_queues = max; 1737 } 1738 1739 for (i = dev->online_queues; i <= max; i++) { 1740 bool polled = i > rw_queues; 1741 1742 ret = nvme_create_queue(&dev->queues[i], i, polled); 1743 if (ret) 1744 break; 1745 } 1746 1747 /* 1748 * Ignore failing Create SQ/CQ commands, we can continue with less 1749 * than the desired amount of queues, and even a controller without 1750 * I/O queues can still be used to issue admin commands. This might 1751 * be useful to upgrade a buggy firmware for example. 1752 */ 1753 return ret >= 0 ? 0 : ret; 1754 } 1755 1756 static ssize_t nvme_cmb_show(struct device *dev, 1757 struct device_attribute *attr, 1758 char *buf) 1759 { 1760 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1761 1762 return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1763 ndev->cmbloc, ndev->cmbsz); 1764 } 1765 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1766 1767 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1768 { 1769 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1770 1771 return 1ULL << (12 + 4 * szu); 1772 } 1773 1774 static u32 nvme_cmb_size(struct nvme_dev *dev) 1775 { 1776 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1777 } 1778 1779 static void nvme_map_cmb(struct nvme_dev *dev) 1780 { 1781 u64 size, offset; 1782 resource_size_t bar_size; 1783 struct pci_dev *pdev = to_pci_dev(dev->dev); 1784 int bar; 1785 1786 if (dev->cmb_size) 1787 return; 1788 1789 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1790 if (!dev->cmbsz) 1791 return; 1792 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1793 1794 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1795 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1796 bar = NVME_CMB_BIR(dev->cmbloc); 1797 bar_size = pci_resource_len(pdev, bar); 1798 1799 if (offset > bar_size) 1800 return; 1801 1802 /* 1803 * Controllers may support a CMB size larger than their BAR, 1804 * for example, due to being behind a bridge. Reduce the CMB to 1805 * the reported size of the BAR 1806 */ 1807 if (size > bar_size - offset) 1808 size = bar_size - offset; 1809 1810 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1811 dev_warn(dev->ctrl.device, 1812 "failed to register the CMB\n"); 1813 return; 1814 } 1815 1816 dev->cmb_size = size; 1817 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1818 1819 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1820 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1821 pci_p2pmem_publish(pdev, true); 1822 1823 if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1824 &dev_attr_cmb.attr, NULL)) 1825 dev_warn(dev->ctrl.device, 1826 "failed to add sysfs attribute for CMB\n"); 1827 } 1828 1829 static inline void nvme_release_cmb(struct nvme_dev *dev) 1830 { 1831 if (dev->cmb_size) { 1832 sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1833 &dev_attr_cmb.attr, NULL); 1834 dev->cmb_size = 0; 1835 } 1836 } 1837 1838 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1839 { 1840 u64 dma_addr = dev->host_mem_descs_dma; 1841 struct nvme_command c; 1842 int ret; 1843 1844 memset(&c, 0, sizeof(c)); 1845 c.features.opcode = nvme_admin_set_features; 1846 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1847 c.features.dword11 = cpu_to_le32(bits); 1848 c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 1849 ilog2(dev->ctrl.page_size)); 1850 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1851 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1852 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1853 1854 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1855 if (ret) { 1856 dev_warn(dev->ctrl.device, 1857 "failed to set host mem (err %d, flags %#x).\n", 1858 ret, bits); 1859 } 1860 return ret; 1861 } 1862 1863 static void nvme_free_host_mem(struct nvme_dev *dev) 1864 { 1865 int i; 1866 1867 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1868 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1869 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 1870 1871 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1872 le64_to_cpu(desc->addr), 1873 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1874 } 1875 1876 kfree(dev->host_mem_desc_bufs); 1877 dev->host_mem_desc_bufs = NULL; 1878 dma_free_coherent(dev->dev, 1879 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 1880 dev->host_mem_descs, dev->host_mem_descs_dma); 1881 dev->host_mem_descs = NULL; 1882 dev->nr_host_mem_descs = 0; 1883 } 1884 1885 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1886 u32 chunk_size) 1887 { 1888 struct nvme_host_mem_buf_desc *descs; 1889 u32 max_entries, len; 1890 dma_addr_t descs_dma; 1891 int i = 0; 1892 void **bufs; 1893 u64 size, tmp; 1894 1895 tmp = (preferred + chunk_size - 1); 1896 do_div(tmp, chunk_size); 1897 max_entries = tmp; 1898 1899 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1900 max_entries = dev->ctrl.hmmaxd; 1901 1902 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 1903 &descs_dma, GFP_KERNEL); 1904 if (!descs) 1905 goto out; 1906 1907 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1908 if (!bufs) 1909 goto out_free_descs; 1910 1911 for (size = 0; size < preferred && i < max_entries; size += len) { 1912 dma_addr_t dma_addr; 1913 1914 len = min_t(u64, chunk_size, preferred - size); 1915 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1916 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1917 if (!bufs[i]) 1918 break; 1919 1920 descs[i].addr = cpu_to_le64(dma_addr); 1921 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 1922 i++; 1923 } 1924 1925 if (!size) 1926 goto out_free_bufs; 1927 1928 dev->nr_host_mem_descs = i; 1929 dev->host_mem_size = size; 1930 dev->host_mem_descs = descs; 1931 dev->host_mem_descs_dma = descs_dma; 1932 dev->host_mem_desc_bufs = bufs; 1933 return 0; 1934 1935 out_free_bufs: 1936 while (--i >= 0) { 1937 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 1938 1939 dma_free_attrs(dev->dev, size, bufs[i], 1940 le64_to_cpu(descs[i].addr), 1941 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1942 } 1943 1944 kfree(bufs); 1945 out_free_descs: 1946 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 1947 descs_dma); 1948 out: 1949 dev->host_mem_descs = NULL; 1950 return -ENOMEM; 1951 } 1952 1953 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 1954 { 1955 u32 chunk_size; 1956 1957 /* start big and work our way down */ 1958 for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1959 chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 1960 chunk_size /= 2) { 1961 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 1962 if (!min || dev->host_mem_size >= min) 1963 return 0; 1964 nvme_free_host_mem(dev); 1965 } 1966 } 1967 1968 return -ENOMEM; 1969 } 1970 1971 static int nvme_setup_host_mem(struct nvme_dev *dev) 1972 { 1973 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 1974 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 1975 u64 min = (u64)dev->ctrl.hmmin * 4096; 1976 u32 enable_bits = NVME_HOST_MEM_ENABLE; 1977 int ret; 1978 1979 preferred = min(preferred, max); 1980 if (min > max) { 1981 dev_warn(dev->ctrl.device, 1982 "min host memory (%lld MiB) above limit (%d MiB).\n", 1983 min >> ilog2(SZ_1M), max_host_mem_size_mb); 1984 nvme_free_host_mem(dev); 1985 return 0; 1986 } 1987 1988 /* 1989 * If we already have a buffer allocated check if we can reuse it. 1990 */ 1991 if (dev->host_mem_descs) { 1992 if (dev->host_mem_size >= min) 1993 enable_bits |= NVME_HOST_MEM_RETURN; 1994 else 1995 nvme_free_host_mem(dev); 1996 } 1997 1998 if (!dev->host_mem_descs) { 1999 if (nvme_alloc_host_mem(dev, min, preferred)) { 2000 dev_warn(dev->ctrl.device, 2001 "failed to allocate host memory buffer.\n"); 2002 return 0; /* controller must work without HMB */ 2003 } 2004 2005 dev_info(dev->ctrl.device, 2006 "allocated %lld MiB host memory buffer.\n", 2007 dev->host_mem_size >> ilog2(SZ_1M)); 2008 } 2009 2010 ret = nvme_set_host_mem(dev, enable_bits); 2011 if (ret) 2012 nvme_free_host_mem(dev); 2013 return ret; 2014 } 2015 2016 /* 2017 * nirqs is the number of interrupts available for write and read 2018 * queues. The core already reserved an interrupt for the admin queue. 2019 */ 2020 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2021 { 2022 struct nvme_dev *dev = affd->priv; 2023 unsigned int nr_read_queues; 2024 2025 /* 2026 * If there is no interupt available for queues, ensure that 2027 * the default queue is set to 1. The affinity set size is 2028 * also set to one, but the irq core ignores it for this case. 2029 * 2030 * If only one interrupt is available or 'write_queue' == 0, combine 2031 * write and read queues. 2032 * 2033 * If 'write_queues' > 0, ensure it leaves room for at least one read 2034 * queue. 2035 */ 2036 if (!nrirqs) { 2037 nrirqs = 1; 2038 nr_read_queues = 0; 2039 } else if (nrirqs == 1 || !write_queues) { 2040 nr_read_queues = 0; 2041 } else if (write_queues >= nrirqs) { 2042 nr_read_queues = 1; 2043 } else { 2044 nr_read_queues = nrirqs - write_queues; 2045 } 2046 2047 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2048 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2049 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2050 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2051 affd->nr_sets = nr_read_queues ? 2 : 1; 2052 } 2053 2054 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2055 { 2056 struct pci_dev *pdev = to_pci_dev(dev->dev); 2057 struct irq_affinity affd = { 2058 .pre_vectors = 1, 2059 .calc_sets = nvme_calc_irq_sets, 2060 .priv = dev, 2061 }; 2062 unsigned int irq_queues, this_p_queues; 2063 unsigned int nr_cpus = num_possible_cpus(); 2064 2065 /* 2066 * Poll queues don't need interrupts, but we need at least one IO 2067 * queue left over for non-polled IO. 2068 */ 2069 this_p_queues = poll_queues; 2070 if (this_p_queues >= nr_io_queues) { 2071 this_p_queues = nr_io_queues - 1; 2072 irq_queues = 1; 2073 } else { 2074 if (nr_cpus < nr_io_queues - this_p_queues) 2075 irq_queues = nr_cpus + 1; 2076 else 2077 irq_queues = nr_io_queues - this_p_queues + 1; 2078 } 2079 dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 2080 2081 /* Initialize for the single interrupt case */ 2082 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2083 dev->io_queues[HCTX_TYPE_READ] = 0; 2084 2085 /* 2086 * Some Apple controllers require all queues to use the 2087 * first vector. 2088 */ 2089 if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 2090 irq_queues = 1; 2091 2092 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 2093 PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 2094 } 2095 2096 static void nvme_disable_io_queues(struct nvme_dev *dev) 2097 { 2098 if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 2099 __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2100 } 2101 2102 static int nvme_setup_io_queues(struct nvme_dev *dev) 2103 { 2104 struct nvme_queue *adminq = &dev->queues[0]; 2105 struct pci_dev *pdev = to_pci_dev(dev->dev); 2106 int result, nr_io_queues; 2107 unsigned long size; 2108 2109 nr_io_queues = max_io_queues(); 2110 2111 /* 2112 * If tags are shared with admin queue (Apple bug), then 2113 * make sure we only use one IO queue. 2114 */ 2115 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2116 nr_io_queues = 1; 2117 2118 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2119 if (result < 0) 2120 return result; 2121 2122 if (nr_io_queues == 0) 2123 return 0; 2124 2125 clear_bit(NVMEQ_ENABLED, &adminq->flags); 2126 2127 if (dev->cmb_use_sqes) { 2128 result = nvme_cmb_qdepth(dev, nr_io_queues, 2129 sizeof(struct nvme_command)); 2130 if (result > 0) 2131 dev->q_depth = result; 2132 else 2133 dev->cmb_use_sqes = false; 2134 } 2135 2136 do { 2137 size = db_bar_size(dev, nr_io_queues); 2138 result = nvme_remap_bar(dev, size); 2139 if (!result) 2140 break; 2141 if (!--nr_io_queues) 2142 return -ENOMEM; 2143 } while (1); 2144 adminq->q_db = dev->dbs; 2145 2146 retry: 2147 /* Deregister the admin queue's interrupt */ 2148 pci_free_irq(pdev, 0, adminq); 2149 2150 /* 2151 * If we enable msix early due to not intx, disable it again before 2152 * setting up the full range we need. 2153 */ 2154 pci_free_irq_vectors(pdev); 2155 2156 result = nvme_setup_irqs(dev, nr_io_queues); 2157 if (result <= 0) 2158 return -EIO; 2159 2160 dev->num_vecs = result; 2161 result = max(result - 1, 1); 2162 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2163 2164 /* 2165 * Should investigate if there's a performance win from allocating 2166 * more queues than interrupt vectors; it might allow the submission 2167 * path to scale better, even if the receive path is limited by the 2168 * number of interrupts. 2169 */ 2170 result = queue_request_irq(adminq); 2171 if (result) 2172 return result; 2173 set_bit(NVMEQ_ENABLED, &adminq->flags); 2174 2175 result = nvme_create_io_queues(dev); 2176 if (result || dev->online_queues < 2) 2177 return result; 2178 2179 if (dev->online_queues - 1 < dev->max_qid) { 2180 nr_io_queues = dev->online_queues - 1; 2181 nvme_disable_io_queues(dev); 2182 nvme_suspend_io_queues(dev); 2183 goto retry; 2184 } 2185 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2186 dev->io_queues[HCTX_TYPE_DEFAULT], 2187 dev->io_queues[HCTX_TYPE_READ], 2188 dev->io_queues[HCTX_TYPE_POLL]); 2189 return 0; 2190 } 2191 2192 static void nvme_del_queue_end(struct request *req, blk_status_t error) 2193 { 2194 struct nvme_queue *nvmeq = req->end_io_data; 2195 2196 blk_mq_free_request(req); 2197 complete(&nvmeq->delete_done); 2198 } 2199 2200 static void nvme_del_cq_end(struct request *req, blk_status_t error) 2201 { 2202 struct nvme_queue *nvmeq = req->end_io_data; 2203 2204 if (error) 2205 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2206 2207 nvme_del_queue_end(req, error); 2208 } 2209 2210 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2211 { 2212 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2213 struct request *req; 2214 struct nvme_command cmd; 2215 2216 memset(&cmd, 0, sizeof(cmd)); 2217 cmd.delete_queue.opcode = opcode; 2218 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2219 2220 req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2221 if (IS_ERR(req)) 2222 return PTR_ERR(req); 2223 2224 req->timeout = ADMIN_TIMEOUT; 2225 req->end_io_data = nvmeq; 2226 2227 init_completion(&nvmeq->delete_done); 2228 blk_execute_rq_nowait(q, NULL, req, false, 2229 opcode == nvme_admin_delete_cq ? 2230 nvme_del_cq_end : nvme_del_queue_end); 2231 return 0; 2232 } 2233 2234 static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2235 { 2236 int nr_queues = dev->online_queues - 1, sent = 0; 2237 unsigned long timeout; 2238 2239 retry: 2240 timeout = ADMIN_TIMEOUT; 2241 while (nr_queues > 0) { 2242 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2243 break; 2244 nr_queues--; 2245 sent++; 2246 } 2247 while (sent) { 2248 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2249 2250 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2251 timeout); 2252 if (timeout == 0) 2253 return false; 2254 2255 /* handle any remaining CQEs */ 2256 if (opcode == nvme_admin_delete_cq && 2257 !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2258 nvme_poll_irqdisable(nvmeq, -1); 2259 2260 sent--; 2261 if (nr_queues) 2262 goto retry; 2263 } 2264 return true; 2265 } 2266 2267 static void nvme_dev_add(struct nvme_dev *dev) 2268 { 2269 int ret; 2270 2271 if (!dev->ctrl.tagset) { 2272 dev->tagset.ops = &nvme_mq_ops; 2273 dev->tagset.nr_hw_queues = dev->online_queues - 1; 2274 dev->tagset.nr_maps = 2; /* default + read */ 2275 if (dev->io_queues[HCTX_TYPE_POLL]) 2276 dev->tagset.nr_maps++; 2277 dev->tagset.timeout = NVME_IO_TIMEOUT; 2278 dev->tagset.numa_node = dev_to_node(dev->dev); 2279 dev->tagset.queue_depth = 2280 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2281 dev->tagset.cmd_size = sizeof(struct nvme_iod); 2282 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 2283 dev->tagset.driver_data = dev; 2284 2285 /* 2286 * Some Apple controllers requires tags to be unique 2287 * across admin and IO queue, so reserve the first 32 2288 * tags of the IO queue. 2289 */ 2290 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2291 dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2292 2293 ret = blk_mq_alloc_tag_set(&dev->tagset); 2294 if (ret) { 2295 dev_warn(dev->ctrl.device, 2296 "IO queues tagset allocation failed %d\n", ret); 2297 return; 2298 } 2299 dev->ctrl.tagset = &dev->tagset; 2300 } else { 2301 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2302 2303 /* Free previously allocated queues that are no longer usable */ 2304 nvme_free_queues(dev, dev->online_queues); 2305 } 2306 2307 nvme_dbbuf_set(dev); 2308 } 2309 2310 static int nvme_pci_enable(struct nvme_dev *dev) 2311 { 2312 int result = -ENOMEM; 2313 struct pci_dev *pdev = to_pci_dev(dev->dev); 2314 2315 if (pci_enable_device_mem(pdev)) 2316 return result; 2317 2318 pci_set_master(pdev); 2319 2320 if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 2321 goto disable; 2322 2323 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2324 result = -ENODEV; 2325 goto disable; 2326 } 2327 2328 /* 2329 * Some devices and/or platforms don't advertise or work with INTx 2330 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2331 * adjust this later. 2332 */ 2333 result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2334 if (result < 0) 2335 return result; 2336 2337 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2338 2339 dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2340 io_queue_depth); 2341 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2342 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2343 dev->dbs = dev->bar + 4096; 2344 2345 /* 2346 * Some Apple controllers require a non-standard SQE size. 2347 * Interestingly they also seem to ignore the CC:IOSQES register 2348 * so we don't bother updating it here. 2349 */ 2350 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2351 dev->io_sqes = 7; 2352 else 2353 dev->io_sqes = NVME_NVM_IOSQES; 2354 2355 /* 2356 * Temporary fix for the Apple controller found in the MacBook8,1 and 2357 * some MacBook7,1 to avoid controller resets and data loss. 2358 */ 2359 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 2360 dev->q_depth = 2; 2361 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 2362 "set queue depth=%u to work around controller resets\n", 2363 dev->q_depth); 2364 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2365 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2366 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2367 dev->q_depth = 64; 2368 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2369 "set queue depth=%u\n", dev->q_depth); 2370 } 2371 2372 /* 2373 * Controllers with the shared tags quirk need the IO queue to be 2374 * big enough so that we get 32 tags for the admin queue 2375 */ 2376 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2377 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2378 dev->q_depth = NVME_AQ_DEPTH + 2; 2379 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2380 dev->q_depth); 2381 } 2382 2383 2384 nvme_map_cmb(dev); 2385 2386 pci_enable_pcie_error_reporting(pdev); 2387 pci_save_state(pdev); 2388 return 0; 2389 2390 disable: 2391 pci_disable_device(pdev); 2392 return result; 2393 } 2394 2395 static void nvme_dev_unmap(struct nvme_dev *dev) 2396 { 2397 if (dev->bar) 2398 iounmap(dev->bar); 2399 pci_release_mem_regions(to_pci_dev(dev->dev)); 2400 } 2401 2402 static void nvme_pci_disable(struct nvme_dev *dev) 2403 { 2404 struct pci_dev *pdev = to_pci_dev(dev->dev); 2405 2406 pci_free_irq_vectors(pdev); 2407 2408 if (pci_is_enabled(pdev)) { 2409 pci_disable_pcie_error_reporting(pdev); 2410 pci_disable_device(pdev); 2411 } 2412 } 2413 2414 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2415 { 2416 bool dead = true, freeze = false; 2417 struct pci_dev *pdev = to_pci_dev(dev->dev); 2418 2419 mutex_lock(&dev->shutdown_lock); 2420 if (pci_is_enabled(pdev)) { 2421 u32 csts = readl(dev->bar + NVME_REG_CSTS); 2422 2423 if (dev->ctrl.state == NVME_CTRL_LIVE || 2424 dev->ctrl.state == NVME_CTRL_RESETTING) { 2425 freeze = true; 2426 nvme_start_freeze(&dev->ctrl); 2427 } 2428 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2429 pdev->error_state != pci_channel_io_normal); 2430 } 2431 2432 /* 2433 * Give the controller a chance to complete all entered requests if 2434 * doing a safe shutdown. 2435 */ 2436 if (!dead && shutdown && freeze) 2437 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2438 2439 nvme_stop_queues(&dev->ctrl); 2440 2441 if (!dead && dev->ctrl.queue_count > 0) { 2442 nvme_disable_io_queues(dev); 2443 nvme_disable_admin_queue(dev, shutdown); 2444 } 2445 nvme_suspend_io_queues(dev); 2446 nvme_suspend_queue(&dev->queues[0]); 2447 nvme_pci_disable(dev); 2448 2449 blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2450 blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2451 blk_mq_tagset_wait_completed_request(&dev->tagset); 2452 blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2453 2454 /* 2455 * The driver will not be starting up queues again if shutting down so 2456 * must flush all entered requests to their failed completion to avoid 2457 * deadlocking blk-mq hot-cpu notifier. 2458 */ 2459 if (shutdown) { 2460 nvme_start_queues(&dev->ctrl); 2461 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2462 blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2463 } 2464 mutex_unlock(&dev->shutdown_lock); 2465 } 2466 2467 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2468 { 2469 if (!nvme_wait_reset(&dev->ctrl)) 2470 return -EBUSY; 2471 nvme_dev_disable(dev, shutdown); 2472 return 0; 2473 } 2474 2475 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2476 { 2477 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2478 PAGE_SIZE, PAGE_SIZE, 0); 2479 if (!dev->prp_page_pool) 2480 return -ENOMEM; 2481 2482 /* Optimisation for I/Os between 4k and 128k */ 2483 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2484 256, 256, 0); 2485 if (!dev->prp_small_pool) { 2486 dma_pool_destroy(dev->prp_page_pool); 2487 return -ENOMEM; 2488 } 2489 return 0; 2490 } 2491 2492 static void nvme_release_prp_pools(struct nvme_dev *dev) 2493 { 2494 dma_pool_destroy(dev->prp_page_pool); 2495 dma_pool_destroy(dev->prp_small_pool); 2496 } 2497 2498 static void nvme_free_tagset(struct nvme_dev *dev) 2499 { 2500 if (dev->tagset.tags) 2501 blk_mq_free_tag_set(&dev->tagset); 2502 dev->ctrl.tagset = NULL; 2503 } 2504 2505 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2506 { 2507 struct nvme_dev *dev = to_nvme_dev(ctrl); 2508 2509 nvme_dbbuf_dma_free(dev); 2510 put_device(dev->dev); 2511 nvme_free_tagset(dev); 2512 if (dev->ctrl.admin_q) 2513 blk_put_queue(dev->ctrl.admin_q); 2514 kfree(dev->queues); 2515 free_opal_dev(dev->ctrl.opal_dev); 2516 mempool_destroy(dev->iod_mempool); 2517 kfree(dev); 2518 } 2519 2520 static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2521 { 2522 /* 2523 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2524 * may be holding this pci_dev's device lock. 2525 */ 2526 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2527 nvme_get_ctrl(&dev->ctrl); 2528 nvme_dev_disable(dev, false); 2529 nvme_kill_queues(&dev->ctrl); 2530 if (!queue_work(nvme_wq, &dev->remove_work)) 2531 nvme_put_ctrl(&dev->ctrl); 2532 } 2533 2534 static void nvme_reset_work(struct work_struct *work) 2535 { 2536 struct nvme_dev *dev = 2537 container_of(work, struct nvme_dev, ctrl.reset_work); 2538 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2539 int result; 2540 2541 if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2542 result = -ENODEV; 2543 goto out; 2544 } 2545 2546 /* 2547 * If we're called to reset a live controller first shut it down before 2548 * moving on. 2549 */ 2550 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2551 nvme_dev_disable(dev, false); 2552 nvme_sync_queues(&dev->ctrl); 2553 2554 mutex_lock(&dev->shutdown_lock); 2555 result = nvme_pci_enable(dev); 2556 if (result) 2557 goto out_unlock; 2558 2559 result = nvme_pci_configure_admin_queue(dev); 2560 if (result) 2561 goto out_unlock; 2562 2563 result = nvme_alloc_admin_tags(dev); 2564 if (result) 2565 goto out_unlock; 2566 2567 /* 2568 * Limit the max command size to prevent iod->sg allocations going 2569 * over a single page. 2570 */ 2571 dev->ctrl.max_hw_sectors = min_t(u32, 2572 NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2573 dev->ctrl.max_segments = NVME_MAX_SEGS; 2574 2575 /* 2576 * Don't limit the IOMMU merged segment size. 2577 */ 2578 dma_set_max_seg_size(dev->dev, 0xffffffff); 2579 2580 mutex_unlock(&dev->shutdown_lock); 2581 2582 /* 2583 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2584 * initializing procedure here. 2585 */ 2586 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2587 dev_warn(dev->ctrl.device, 2588 "failed to mark controller CONNECTING\n"); 2589 result = -EBUSY; 2590 goto out; 2591 } 2592 2593 result = nvme_init_identify(&dev->ctrl); 2594 if (result) 2595 goto out; 2596 2597 if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2598 if (!dev->ctrl.opal_dev) 2599 dev->ctrl.opal_dev = 2600 init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2601 else if (was_suspend) 2602 opal_unlock_from_suspend(dev->ctrl.opal_dev); 2603 } else { 2604 free_opal_dev(dev->ctrl.opal_dev); 2605 dev->ctrl.opal_dev = NULL; 2606 } 2607 2608 if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2609 result = nvme_dbbuf_dma_alloc(dev); 2610 if (result) 2611 dev_warn(dev->dev, 2612 "unable to allocate dma for dbbuf\n"); 2613 } 2614 2615 if (dev->ctrl.hmpre) { 2616 result = nvme_setup_host_mem(dev); 2617 if (result < 0) 2618 goto out; 2619 } 2620 2621 result = nvme_setup_io_queues(dev); 2622 if (result) 2623 goto out; 2624 2625 /* 2626 * Keep the controller around but remove all namespaces if we don't have 2627 * any working I/O queue. 2628 */ 2629 if (dev->online_queues < 2) { 2630 dev_warn(dev->ctrl.device, "IO queues not created\n"); 2631 nvme_kill_queues(&dev->ctrl); 2632 nvme_remove_namespaces(&dev->ctrl); 2633 nvme_free_tagset(dev); 2634 } else { 2635 nvme_start_queues(&dev->ctrl); 2636 nvme_wait_freeze(&dev->ctrl); 2637 nvme_dev_add(dev); 2638 nvme_unfreeze(&dev->ctrl); 2639 } 2640 2641 /* 2642 * If only admin queue live, keep it to do further investigation or 2643 * recovery. 2644 */ 2645 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2646 dev_warn(dev->ctrl.device, 2647 "failed to mark controller live state\n"); 2648 result = -ENODEV; 2649 goto out; 2650 } 2651 2652 nvme_start_ctrl(&dev->ctrl); 2653 return; 2654 2655 out_unlock: 2656 mutex_unlock(&dev->shutdown_lock); 2657 out: 2658 if (result) 2659 dev_warn(dev->ctrl.device, 2660 "Removing after probe failure status: %d\n", result); 2661 nvme_remove_dead_ctrl(dev); 2662 } 2663 2664 static void nvme_remove_dead_ctrl_work(struct work_struct *work) 2665 { 2666 struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 2667 struct pci_dev *pdev = to_pci_dev(dev->dev); 2668 2669 if (pci_get_drvdata(pdev)) 2670 device_release_driver(&pdev->dev); 2671 nvme_put_ctrl(&dev->ctrl); 2672 } 2673 2674 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2675 { 2676 *val = readl(to_nvme_dev(ctrl)->bar + off); 2677 return 0; 2678 } 2679 2680 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2681 { 2682 writel(val, to_nvme_dev(ctrl)->bar + off); 2683 return 0; 2684 } 2685 2686 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2687 { 2688 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2689 return 0; 2690 } 2691 2692 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2693 { 2694 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2695 2696 return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 2697 } 2698 2699 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2700 .name = "pcie", 2701 .module = THIS_MODULE, 2702 .flags = NVME_F_METADATA_SUPPORTED | 2703 NVME_F_PCI_P2PDMA, 2704 .reg_read32 = nvme_pci_reg_read32, 2705 .reg_write32 = nvme_pci_reg_write32, 2706 .reg_read64 = nvme_pci_reg_read64, 2707 .free_ctrl = nvme_pci_free_ctrl, 2708 .submit_async_event = nvme_pci_submit_async_event, 2709 .get_address = nvme_pci_get_address, 2710 }; 2711 2712 static int nvme_dev_map(struct nvme_dev *dev) 2713 { 2714 struct pci_dev *pdev = to_pci_dev(dev->dev); 2715 2716 if (pci_request_mem_regions(pdev, "nvme")) 2717 return -ENODEV; 2718 2719 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2720 goto release; 2721 2722 return 0; 2723 release: 2724 pci_release_mem_regions(pdev); 2725 return -ENODEV; 2726 } 2727 2728 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2729 { 2730 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2731 /* 2732 * Several Samsung devices seem to drop off the PCIe bus 2733 * randomly when APST is on and uses the deepest sleep state. 2734 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2735 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2736 * 950 PRO 256GB", but it seems to be restricted to two Dell 2737 * laptops. 2738 */ 2739 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2740 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2741 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2742 return NVME_QUIRK_NO_DEEPEST_PS; 2743 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2744 /* 2745 * Samsung SSD 960 EVO drops off the PCIe bus after system 2746 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2747 * within few minutes after bootup on a Coffee Lake board - 2748 * ASUS PRIME Z370-A 2749 */ 2750 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2751 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2752 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2753 return NVME_QUIRK_NO_APST; 2754 } 2755 2756 return 0; 2757 } 2758 2759 static void nvme_async_probe(void *data, async_cookie_t cookie) 2760 { 2761 struct nvme_dev *dev = data; 2762 2763 flush_work(&dev->ctrl.reset_work); 2764 flush_work(&dev->ctrl.scan_work); 2765 nvme_put_ctrl(&dev->ctrl); 2766 } 2767 2768 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 2769 { 2770 int node, result = -ENOMEM; 2771 struct nvme_dev *dev; 2772 unsigned long quirks = id->driver_data; 2773 size_t alloc_size; 2774 2775 node = dev_to_node(&pdev->dev); 2776 if (node == NUMA_NO_NODE) 2777 set_dev_node(&pdev->dev, first_memory_node); 2778 2779 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2780 if (!dev) 2781 return -ENOMEM; 2782 2783 dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 2784 GFP_KERNEL, node); 2785 if (!dev->queues) 2786 goto free; 2787 2788 dev->dev = get_device(&pdev->dev); 2789 pci_set_drvdata(pdev, dev); 2790 2791 result = nvme_dev_map(dev); 2792 if (result) 2793 goto put_pci; 2794 2795 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2796 INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 2797 mutex_init(&dev->shutdown_lock); 2798 2799 result = nvme_setup_prp_pools(dev); 2800 if (result) 2801 goto unmap; 2802 2803 quirks |= check_vendor_combination_bug(pdev); 2804 2805 /* 2806 * Double check that our mempool alloc size will cover the biggest 2807 * command we support. 2808 */ 2809 alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2810 NVME_MAX_SEGS, true); 2811 WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2812 2813 dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2814 mempool_kfree, 2815 (void *) alloc_size, 2816 GFP_KERNEL, node); 2817 if (!dev->iod_mempool) { 2818 result = -ENOMEM; 2819 goto release_pools; 2820 } 2821 2822 result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2823 quirks); 2824 if (result) 2825 goto release_mempool; 2826 2827 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 2828 2829 nvme_reset_ctrl(&dev->ctrl); 2830 nvme_get_ctrl(&dev->ctrl); 2831 async_schedule(nvme_async_probe, dev); 2832 2833 return 0; 2834 2835 release_mempool: 2836 mempool_destroy(dev->iod_mempool); 2837 release_pools: 2838 nvme_release_prp_pools(dev); 2839 unmap: 2840 nvme_dev_unmap(dev); 2841 put_pci: 2842 put_device(dev->dev); 2843 free: 2844 kfree(dev->queues); 2845 kfree(dev); 2846 return result; 2847 } 2848 2849 static void nvme_reset_prepare(struct pci_dev *pdev) 2850 { 2851 struct nvme_dev *dev = pci_get_drvdata(pdev); 2852 2853 /* 2854 * We don't need to check the return value from waiting for the reset 2855 * state as pci_dev device lock is held, making it impossible to race 2856 * with ->remove(). 2857 */ 2858 nvme_disable_prepare_reset(dev, false); 2859 nvme_sync_queues(&dev->ctrl); 2860 } 2861 2862 static void nvme_reset_done(struct pci_dev *pdev) 2863 { 2864 struct nvme_dev *dev = pci_get_drvdata(pdev); 2865 2866 if (!nvme_try_sched_reset(&dev->ctrl)) 2867 flush_work(&dev->ctrl.reset_work); 2868 } 2869 2870 static void nvme_shutdown(struct pci_dev *pdev) 2871 { 2872 struct nvme_dev *dev = pci_get_drvdata(pdev); 2873 nvme_disable_prepare_reset(dev, true); 2874 } 2875 2876 /* 2877 * The driver's remove may be called on a device in a partially initialized 2878 * state. This function must not have any dependencies on the device state in 2879 * order to proceed. 2880 */ 2881 static void nvme_remove(struct pci_dev *pdev) 2882 { 2883 struct nvme_dev *dev = pci_get_drvdata(pdev); 2884 2885 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2886 pci_set_drvdata(pdev, NULL); 2887 2888 if (!pci_device_is_present(pdev)) { 2889 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2890 nvme_dev_disable(dev, true); 2891 nvme_dev_remove_admin(dev); 2892 } 2893 2894 flush_work(&dev->ctrl.reset_work); 2895 nvme_stop_ctrl(&dev->ctrl); 2896 nvme_remove_namespaces(&dev->ctrl); 2897 nvme_dev_disable(dev, true); 2898 nvme_release_cmb(dev); 2899 nvme_free_host_mem(dev); 2900 nvme_dev_remove_admin(dev); 2901 nvme_free_queues(dev, 0); 2902 nvme_uninit_ctrl(&dev->ctrl); 2903 nvme_release_prp_pools(dev); 2904 nvme_dev_unmap(dev); 2905 nvme_put_ctrl(&dev->ctrl); 2906 } 2907 2908 #ifdef CONFIG_PM_SLEEP 2909 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2910 { 2911 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2912 } 2913 2914 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2915 { 2916 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2917 } 2918 2919 static int nvme_resume(struct device *dev) 2920 { 2921 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2922 struct nvme_ctrl *ctrl = &ndev->ctrl; 2923 2924 if (ndev->last_ps == U32_MAX || 2925 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2926 return nvme_try_sched_reset(&ndev->ctrl); 2927 return 0; 2928 } 2929 2930 static int nvme_suspend(struct device *dev) 2931 { 2932 struct pci_dev *pdev = to_pci_dev(dev); 2933 struct nvme_dev *ndev = pci_get_drvdata(pdev); 2934 struct nvme_ctrl *ctrl = &ndev->ctrl; 2935 int ret = -EBUSY; 2936 2937 ndev->last_ps = U32_MAX; 2938 2939 /* 2940 * The platform does not remove power for a kernel managed suspend so 2941 * use host managed nvme power settings for lowest idle power if 2942 * possible. This should have quicker resume latency than a full device 2943 * shutdown. But if the firmware is involved after the suspend or the 2944 * device does not support any non-default power states, shut down the 2945 * device fully. 2946 * 2947 * If ASPM is not enabled for the device, shut down the device and allow 2948 * the PCI bus layer to put it into D3 in order to take the PCIe link 2949 * down, so as to allow the platform to achieve its minimum low-power 2950 * state (which may not be possible if the link is up). 2951 */ 2952 if (pm_suspend_via_firmware() || !ctrl->npss || 2953 !pcie_aspm_enabled(pdev) || 2954 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2955 return nvme_disable_prepare_reset(ndev, true); 2956 2957 nvme_start_freeze(ctrl); 2958 nvme_wait_freeze(ctrl); 2959 nvme_sync_queues(ctrl); 2960 2961 if (ctrl->state != NVME_CTRL_LIVE) 2962 goto unfreeze; 2963 2964 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2965 if (ret < 0) 2966 goto unfreeze; 2967 2968 /* 2969 * A saved state prevents pci pm from generically controlling the 2970 * device's power. If we're using protocol specific settings, we don't 2971 * want pci interfering. 2972 */ 2973 pci_save_state(pdev); 2974 2975 ret = nvme_set_power_state(ctrl, ctrl->npss); 2976 if (ret < 0) 2977 goto unfreeze; 2978 2979 if (ret) { 2980 /* discard the saved state */ 2981 pci_load_saved_state(pdev, NULL); 2982 2983 /* 2984 * Clearing npss forces a controller reset on resume. The 2985 * correct value will be resdicovered then. 2986 */ 2987 ret = nvme_disable_prepare_reset(ndev, true); 2988 ctrl->npss = 0; 2989 } 2990 unfreeze: 2991 nvme_unfreeze(ctrl); 2992 return ret; 2993 } 2994 2995 static int nvme_simple_suspend(struct device *dev) 2996 { 2997 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2998 return nvme_disable_prepare_reset(ndev, true); 2999 } 3000 3001 static int nvme_simple_resume(struct device *dev) 3002 { 3003 struct pci_dev *pdev = to_pci_dev(dev); 3004 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3005 3006 return nvme_try_sched_reset(&ndev->ctrl); 3007 } 3008 3009 static const struct dev_pm_ops nvme_dev_pm_ops = { 3010 .suspend = nvme_suspend, 3011 .resume = nvme_resume, 3012 .freeze = nvme_simple_suspend, 3013 .thaw = nvme_simple_resume, 3014 .poweroff = nvme_simple_suspend, 3015 .restore = nvme_simple_resume, 3016 }; 3017 #endif /* CONFIG_PM_SLEEP */ 3018 3019 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3020 pci_channel_state_t state) 3021 { 3022 struct nvme_dev *dev = pci_get_drvdata(pdev); 3023 3024 /* 3025 * A frozen channel requires a reset. When detected, this method will 3026 * shutdown the controller to quiesce. The controller will be restarted 3027 * after the slot reset through driver's slot_reset callback. 3028 */ 3029 switch (state) { 3030 case pci_channel_io_normal: 3031 return PCI_ERS_RESULT_CAN_RECOVER; 3032 case pci_channel_io_frozen: 3033 dev_warn(dev->ctrl.device, 3034 "frozen state error detected, reset controller\n"); 3035 nvme_dev_disable(dev, false); 3036 return PCI_ERS_RESULT_NEED_RESET; 3037 case pci_channel_io_perm_failure: 3038 dev_warn(dev->ctrl.device, 3039 "failure state error detected, request disconnect\n"); 3040 return PCI_ERS_RESULT_DISCONNECT; 3041 } 3042 return PCI_ERS_RESULT_NEED_RESET; 3043 } 3044 3045 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3046 { 3047 struct nvme_dev *dev = pci_get_drvdata(pdev); 3048 3049 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3050 pci_restore_state(pdev); 3051 nvme_reset_ctrl(&dev->ctrl); 3052 return PCI_ERS_RESULT_RECOVERED; 3053 } 3054 3055 static void nvme_error_resume(struct pci_dev *pdev) 3056 { 3057 struct nvme_dev *dev = pci_get_drvdata(pdev); 3058 3059 flush_work(&dev->ctrl.reset_work); 3060 } 3061 3062 static const struct pci_error_handlers nvme_err_handler = { 3063 .error_detected = nvme_error_detected, 3064 .slot_reset = nvme_slot_reset, 3065 .resume = nvme_error_resume, 3066 .reset_prepare = nvme_reset_prepare, 3067 .reset_done = nvme_reset_done, 3068 }; 3069 3070 static const struct pci_device_id nvme_id_table[] = { 3071 { PCI_VDEVICE(INTEL, 0x0953), 3072 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3073 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3074 { PCI_VDEVICE(INTEL, 0x0a53), 3075 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3076 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3077 { PCI_VDEVICE(INTEL, 0x0a54), 3078 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3079 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3080 { PCI_VDEVICE(INTEL, 0x0a55), 3081 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3082 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3083 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3084 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3085 NVME_QUIRK_MEDIUM_PRIO_SQ }, 3086 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3087 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3088 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3089 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3090 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3091 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3092 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3093 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3094 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3095 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3096 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3097 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3098 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3099 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3100 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3101 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3102 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3103 { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3104 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3105 { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3106 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3107 { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3108 .driver_data = NVME_QUIRK_LIGHTNVM, }, 3109 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3110 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3111 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3112 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3113 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3114 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3115 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3116 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3117 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3118 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3119 NVME_QUIRK_128_BYTES_SQES | 3120 NVME_QUIRK_SHARED_TAGS }, 3121 { 0, } 3122 }; 3123 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3124 3125 static struct pci_driver nvme_driver = { 3126 .name = "nvme", 3127 .id_table = nvme_id_table, 3128 .probe = nvme_probe, 3129 .remove = nvme_remove, 3130 .shutdown = nvme_shutdown, 3131 #ifdef CONFIG_PM_SLEEP 3132 .driver = { 3133 .pm = &nvme_dev_pm_ops, 3134 }, 3135 #endif 3136 .sriov_configure = pci_sriov_configure_simple, 3137 .err_handler = &nvme_err_handler, 3138 }; 3139 3140 static int __init nvme_init(void) 3141 { 3142 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3143 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3144 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3145 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3146 return pci_register_driver(&nvme_driver); 3147 } 3148 3149 static void __exit nvme_exit(void) 3150 { 3151 pci_unregister_driver(&nvme_driver); 3152 flush_workqueue(nvme_wq); 3153 } 3154 3155 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3156 MODULE_LICENSE("GPL"); 3157 MODULE_VERSION("1.0"); 3158 module_init(nvme_init); 3159 module_exit(nvme_exit); 3160