1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NVM Express device driver 4 * Copyright (c) 2011-2014, Intel Corporation. 5 */ 6 7 #include <linux/acpi.h> 8 #include <linux/async.h> 9 #include <linux/blkdev.h> 10 #include <linux/blk-mq.h> 11 #include <linux/blk-mq-pci.h> 12 #include <linux/blk-integrity.h> 13 #include <linux/dmi.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kstrtox.h> 18 #include <linux/memremap.h> 19 #include <linux/mm.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/once.h> 23 #include <linux/pci.h> 24 #include <linux/suspend.h> 25 #include <linux/t10-pi.h> 26 #include <linux/types.h> 27 #include <linux/io-64-nonatomic-lo-hi.h> 28 #include <linux/io-64-nonatomic-hi-lo.h> 29 #include <linux/sed-opal.h> 30 #include <linux/pci-p2pdma.h> 31 32 #include "trace.h" 33 #include "nvme.h" 34 35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 37 38 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39 40 /* 41 * These can be higher, but we need to ensure that any command doesn't 42 * require an sg allocation that needs more than a page of data. 43 */ 44 #define NVME_MAX_KB_SZ 8192 45 #define NVME_MAX_SEGS 128 46 #define NVME_MAX_NR_ALLOCATIONS 5 47 48 static int use_threaded_interrupts; 49 module_param(use_threaded_interrupts, int, 0444); 50 51 static bool use_cmb_sqes = true; 52 module_param(use_cmb_sqes, bool, 0444); 53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 54 55 static unsigned int max_host_mem_size_mb = 128; 56 module_param(max_host_mem_size_mb, uint, 0444); 57 MODULE_PARM_DESC(max_host_mem_size_mb, 58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 59 60 static unsigned int sgl_threshold = SZ_32K; 61 module_param(sgl_threshold, uint, 0644); 62 MODULE_PARM_DESC(sgl_threshold, 63 "Use SGLs when average request segment size is larger or equal to " 64 "this size. Use 0 to disable SGLs."); 65 66 #define NVME_PCI_MIN_QUEUE_SIZE 2 67 #define NVME_PCI_MAX_QUEUE_SIZE 4095 68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69 static const struct kernel_param_ops io_queue_depth_ops = { 70 .set = io_queue_depth_set, 71 .get = param_get_uint, 72 }; 73 74 static unsigned int io_queue_depth = 1024; 75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 77 78 static int io_queue_count_set(const char *val, const struct kernel_param *kp) 79 { 80 unsigned int n; 81 int ret; 82 83 ret = kstrtouint(val, 10, &n); 84 if (ret != 0 || n > num_possible_cpus()) 85 return -EINVAL; 86 return param_set_uint(val, kp); 87 } 88 89 static const struct kernel_param_ops io_queue_count_ops = { 90 .set = io_queue_count_set, 91 .get = param_get_uint, 92 }; 93 94 static unsigned int write_queues; 95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 96 MODULE_PARM_DESC(write_queues, 97 "Number of queues to use for writes. If not set, reads and writes " 98 "will share a queue set."); 99 100 static unsigned int poll_queues; 101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 103 104 static bool noacpi; 105 module_param(noacpi, bool, 0444); 106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 107 108 struct nvme_dev; 109 struct nvme_queue; 110 111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 112 static void nvme_delete_io_queues(struct nvme_dev *dev); 113 static void nvme_update_attrs(struct nvme_dev *dev); 114 115 /* 116 * Represents an NVM Express device. Each nvme_dev is a PCI function. 117 */ 118 struct nvme_dev { 119 struct nvme_queue *queues; 120 struct blk_mq_tag_set tagset; 121 struct blk_mq_tag_set admin_tagset; 122 u32 __iomem *dbs; 123 struct device *dev; 124 struct dma_pool *prp_page_pool; 125 struct dma_pool *prp_small_pool; 126 unsigned online_queues; 127 unsigned max_qid; 128 unsigned io_queues[HCTX_MAX_TYPES]; 129 unsigned int num_vecs; 130 u32 q_depth; 131 int io_sqes; 132 u32 db_stride; 133 void __iomem *bar; 134 unsigned long bar_mapped_size; 135 struct mutex shutdown_lock; 136 bool subsystem; 137 u64 cmb_size; 138 bool cmb_use_sqes; 139 u32 cmbsz; 140 u32 cmbloc; 141 struct nvme_ctrl ctrl; 142 u32 last_ps; 143 bool hmb; 144 145 mempool_t *iod_mempool; 146 147 /* shadow doorbell buffer support: */ 148 __le32 *dbbuf_dbs; 149 dma_addr_t dbbuf_dbs_dma_addr; 150 __le32 *dbbuf_eis; 151 dma_addr_t dbbuf_eis_dma_addr; 152 153 /* host memory buffer support: */ 154 u64 host_mem_size; 155 u32 nr_host_mem_descs; 156 u32 host_mem_descs_size; 157 dma_addr_t host_mem_descs_dma; 158 struct nvme_host_mem_buf_desc *host_mem_descs; 159 void **host_mem_desc_bufs; 160 unsigned int nr_allocated_queues; 161 unsigned int nr_write_queues; 162 unsigned int nr_poll_queues; 163 }; 164 165 static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 166 { 167 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 168 NVME_PCI_MAX_QUEUE_SIZE); 169 } 170 171 static inline unsigned int sq_idx(unsigned int qid, u32 stride) 172 { 173 return qid * 2 * stride; 174 } 175 176 static inline unsigned int cq_idx(unsigned int qid, u32 stride) 177 { 178 return (qid * 2 + 1) * stride; 179 } 180 181 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 182 { 183 return container_of(ctrl, struct nvme_dev, ctrl); 184 } 185 186 /* 187 * An NVM Express queue. Each device has at least two (one for admin 188 * commands and one for I/O commands). 189 */ 190 struct nvme_queue { 191 struct nvme_dev *dev; 192 spinlock_t sq_lock; 193 void *sq_cmds; 194 /* only used for poll queues: */ 195 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 196 struct nvme_completion *cqes; 197 dma_addr_t sq_dma_addr; 198 dma_addr_t cq_dma_addr; 199 u32 __iomem *q_db; 200 u32 q_depth; 201 u16 cq_vector; 202 u16 sq_tail; 203 u16 last_sq_tail; 204 u16 cq_head; 205 u16 qid; 206 u8 cq_phase; 207 u8 sqes; 208 unsigned long flags; 209 #define NVMEQ_ENABLED 0 210 #define NVMEQ_SQ_CMB 1 211 #define NVMEQ_DELETE_ERROR 2 212 #define NVMEQ_POLLED 3 213 __le32 *dbbuf_sq_db; 214 __le32 *dbbuf_cq_db; 215 __le32 *dbbuf_sq_ei; 216 __le32 *dbbuf_cq_ei; 217 struct completion delete_done; 218 }; 219 220 union nvme_descriptor { 221 struct nvme_sgl_desc *sg_list; 222 __le64 *prp_list; 223 }; 224 225 /* 226 * The nvme_iod describes the data in an I/O. 227 * 228 * The sg pointer contains the list of PRP/SGL chunk allocations in addition 229 * to the actual struct scatterlist. 230 */ 231 struct nvme_iod { 232 struct nvme_request req; 233 struct nvme_command cmd; 234 bool aborted; 235 s8 nr_allocations; /* PRP list pool allocations. 0 means small 236 pool in use */ 237 unsigned int dma_len; /* length of single DMA segment mapping */ 238 dma_addr_t first_dma; 239 dma_addr_t meta_dma; 240 struct sg_table sgt; 241 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS]; 242 }; 243 244 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 245 { 246 return dev->nr_allocated_queues * 8 * dev->db_stride; 247 } 248 249 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 250 { 251 unsigned int mem_size = nvme_dbbuf_size(dev); 252 253 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 254 return; 255 256 if (dev->dbbuf_dbs) { 257 /* 258 * Clear the dbbuf memory so the driver doesn't observe stale 259 * values from the previous instantiation. 260 */ 261 memset(dev->dbbuf_dbs, 0, mem_size); 262 memset(dev->dbbuf_eis, 0, mem_size); 263 return; 264 } 265 266 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 267 &dev->dbbuf_dbs_dma_addr, 268 GFP_KERNEL); 269 if (!dev->dbbuf_dbs) 270 goto fail; 271 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 272 &dev->dbbuf_eis_dma_addr, 273 GFP_KERNEL); 274 if (!dev->dbbuf_eis) 275 goto fail_free_dbbuf_dbs; 276 return; 277 278 fail_free_dbbuf_dbs: 279 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 280 dev->dbbuf_dbs_dma_addr); 281 dev->dbbuf_dbs = NULL; 282 fail: 283 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 284 } 285 286 static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 287 { 288 unsigned int mem_size = nvme_dbbuf_size(dev); 289 290 if (dev->dbbuf_dbs) { 291 dma_free_coherent(dev->dev, mem_size, 292 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 293 dev->dbbuf_dbs = NULL; 294 } 295 if (dev->dbbuf_eis) { 296 dma_free_coherent(dev->dev, mem_size, 297 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 298 dev->dbbuf_eis = NULL; 299 } 300 } 301 302 static void nvme_dbbuf_init(struct nvme_dev *dev, 303 struct nvme_queue *nvmeq, int qid) 304 { 305 if (!dev->dbbuf_dbs || !qid) 306 return; 307 308 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 309 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 310 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 311 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 312 } 313 314 static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 315 { 316 if (!nvmeq->qid) 317 return; 318 319 nvmeq->dbbuf_sq_db = NULL; 320 nvmeq->dbbuf_cq_db = NULL; 321 nvmeq->dbbuf_sq_ei = NULL; 322 nvmeq->dbbuf_cq_ei = NULL; 323 } 324 325 static void nvme_dbbuf_set(struct nvme_dev *dev) 326 { 327 struct nvme_command c = { }; 328 unsigned int i; 329 330 if (!dev->dbbuf_dbs) 331 return; 332 333 c.dbbuf.opcode = nvme_admin_dbbuf; 334 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 335 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 336 337 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 338 dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 339 /* Free memory and continue on */ 340 nvme_dbbuf_dma_free(dev); 341 342 for (i = 1; i <= dev->online_queues; i++) 343 nvme_dbbuf_free(&dev->queues[i]); 344 } 345 } 346 347 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 348 { 349 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 350 } 351 352 /* Update dbbuf and return true if an MMIO is required */ 353 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db, 354 volatile __le32 *dbbuf_ei) 355 { 356 if (dbbuf_db) { 357 u16 old_value, event_idx; 358 359 /* 360 * Ensure that the queue is written before updating 361 * the doorbell in memory 362 */ 363 wmb(); 364 365 old_value = le32_to_cpu(*dbbuf_db); 366 *dbbuf_db = cpu_to_le32(value); 367 368 /* 369 * Ensure that the doorbell is updated before reading the event 370 * index from memory. The controller needs to provide similar 371 * ordering to ensure the envent index is updated before reading 372 * the doorbell. 373 */ 374 mb(); 375 376 event_idx = le32_to_cpu(*dbbuf_ei); 377 if (!nvme_dbbuf_need_event(event_idx, value, old_value)) 378 return false; 379 } 380 381 return true; 382 } 383 384 /* 385 * Will slightly overestimate the number of pages needed. This is OK 386 * as it only leads to a small amount of wasted memory for the lifetime of 387 * the I/O. 388 */ 389 static int nvme_pci_npages_prp(void) 390 { 391 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; 392 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); 393 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); 394 } 395 396 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 397 unsigned int hctx_idx) 398 { 399 struct nvme_dev *dev = to_nvme_dev(data); 400 struct nvme_queue *nvmeq = &dev->queues[0]; 401 402 WARN_ON(hctx_idx != 0); 403 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 404 405 hctx->driver_data = nvmeq; 406 return 0; 407 } 408 409 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 410 unsigned int hctx_idx) 411 { 412 struct nvme_dev *dev = to_nvme_dev(data); 413 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 414 415 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 416 hctx->driver_data = nvmeq; 417 return 0; 418 } 419 420 static int nvme_pci_init_request(struct blk_mq_tag_set *set, 421 struct request *req, unsigned int hctx_idx, 422 unsigned int numa_node) 423 { 424 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 425 426 nvme_req(req)->ctrl = set->driver_data; 427 nvme_req(req)->cmd = &iod->cmd; 428 return 0; 429 } 430 431 static int queue_irq_offset(struct nvme_dev *dev) 432 { 433 /* if we have more than 1 vec, admin queue offsets us by 1 */ 434 if (dev->num_vecs > 1) 435 return 1; 436 437 return 0; 438 } 439 440 static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 441 { 442 struct nvme_dev *dev = to_nvme_dev(set->driver_data); 443 int i, qoff, offset; 444 445 offset = queue_irq_offset(dev); 446 for (i = 0, qoff = 0; i < set->nr_maps; i++) { 447 struct blk_mq_queue_map *map = &set->map[i]; 448 449 map->nr_queues = dev->io_queues[i]; 450 if (!map->nr_queues) { 451 BUG_ON(i == HCTX_TYPE_DEFAULT); 452 continue; 453 } 454 455 /* 456 * The poll queue(s) doesn't have an IRQ (and hence IRQ 457 * affinity), so use the regular blk-mq cpu mapping 458 */ 459 map->queue_offset = qoff; 460 if (i != HCTX_TYPE_POLL && offset) 461 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 462 else 463 blk_mq_map_queues(map); 464 qoff += map->nr_queues; 465 offset += map->nr_queues; 466 } 467 } 468 469 /* 470 * Write sq tail if we are asked to, or if the next command would wrap. 471 */ 472 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 473 { 474 if (!write_sq) { 475 u16 next_tail = nvmeq->sq_tail + 1; 476 477 if (next_tail == nvmeq->q_depth) 478 next_tail = 0; 479 if (next_tail != nvmeq->last_sq_tail) 480 return; 481 } 482 483 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 484 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 485 writel(nvmeq->sq_tail, nvmeq->q_db); 486 nvmeq->last_sq_tail = nvmeq->sq_tail; 487 } 488 489 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 490 struct nvme_command *cmd) 491 { 492 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 493 absolute_pointer(cmd), sizeof(*cmd)); 494 if (++nvmeq->sq_tail == nvmeq->q_depth) 495 nvmeq->sq_tail = 0; 496 } 497 498 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 499 { 500 struct nvme_queue *nvmeq = hctx->driver_data; 501 502 spin_lock(&nvmeq->sq_lock); 503 if (nvmeq->sq_tail != nvmeq->last_sq_tail) 504 nvme_write_sq_db(nvmeq, true); 505 spin_unlock(&nvmeq->sq_lock); 506 } 507 508 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req, 509 int nseg) 510 { 511 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 512 unsigned int avg_seg_size; 513 514 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 515 516 if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 517 return false; 518 if (!nvmeq->qid) 519 return false; 520 if (!sgl_threshold || avg_seg_size < sgl_threshold) 521 return false; 522 return true; 523 } 524 525 static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 526 { 527 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 528 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 529 dma_addr_t dma_addr = iod->first_dma; 530 int i; 531 532 for (i = 0; i < iod->nr_allocations; i++) { 533 __le64 *prp_list = iod->list[i].prp_list; 534 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 535 536 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 537 dma_addr = next_dma_addr; 538 } 539 } 540 541 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 542 { 543 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 544 545 if (iod->dma_len) { 546 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 547 rq_dma_dir(req)); 548 return; 549 } 550 551 WARN_ON_ONCE(!iod->sgt.nents); 552 553 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 554 555 if (iod->nr_allocations == 0) 556 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, 557 iod->first_dma); 558 else if (iod->nr_allocations == 1) 559 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, 560 iod->first_dma); 561 else 562 nvme_free_prps(dev, req); 563 mempool_free(iod->sgt.sgl, dev->iod_mempool); 564 } 565 566 static void nvme_print_sgl(struct scatterlist *sgl, int nents) 567 { 568 int i; 569 struct scatterlist *sg; 570 571 for_each_sg(sgl, sg, nents, i) { 572 dma_addr_t phys = sg_phys(sg); 573 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 574 "dma_address:%pad dma_length:%d\n", 575 i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 576 sg_dma_len(sg)); 577 } 578 } 579 580 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 581 struct request *req, struct nvme_rw_command *cmnd) 582 { 583 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 584 struct dma_pool *pool; 585 int length = blk_rq_payload_bytes(req); 586 struct scatterlist *sg = iod->sgt.sgl; 587 int dma_len = sg_dma_len(sg); 588 u64 dma_addr = sg_dma_address(sg); 589 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 590 __le64 *prp_list; 591 dma_addr_t prp_dma; 592 int nprps, i; 593 594 length -= (NVME_CTRL_PAGE_SIZE - offset); 595 if (length <= 0) { 596 iod->first_dma = 0; 597 goto done; 598 } 599 600 dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 601 if (dma_len) { 602 dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 603 } else { 604 sg = sg_next(sg); 605 dma_addr = sg_dma_address(sg); 606 dma_len = sg_dma_len(sg); 607 } 608 609 if (length <= NVME_CTRL_PAGE_SIZE) { 610 iod->first_dma = dma_addr; 611 goto done; 612 } 613 614 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 615 if (nprps <= (256 / 8)) { 616 pool = dev->prp_small_pool; 617 iod->nr_allocations = 0; 618 } else { 619 pool = dev->prp_page_pool; 620 iod->nr_allocations = 1; 621 } 622 623 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 624 if (!prp_list) { 625 iod->nr_allocations = -1; 626 return BLK_STS_RESOURCE; 627 } 628 iod->list[0].prp_list = prp_list; 629 iod->first_dma = prp_dma; 630 i = 0; 631 for (;;) { 632 if (i == NVME_CTRL_PAGE_SIZE >> 3) { 633 __le64 *old_prp_list = prp_list; 634 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 635 if (!prp_list) 636 goto free_prps; 637 iod->list[iod->nr_allocations++].prp_list = prp_list; 638 prp_list[0] = old_prp_list[i - 1]; 639 old_prp_list[i - 1] = cpu_to_le64(prp_dma); 640 i = 1; 641 } 642 prp_list[i++] = cpu_to_le64(dma_addr); 643 dma_len -= NVME_CTRL_PAGE_SIZE; 644 dma_addr += NVME_CTRL_PAGE_SIZE; 645 length -= NVME_CTRL_PAGE_SIZE; 646 if (length <= 0) 647 break; 648 if (dma_len > 0) 649 continue; 650 if (unlikely(dma_len < 0)) 651 goto bad_sgl; 652 sg = sg_next(sg); 653 dma_addr = sg_dma_address(sg); 654 dma_len = sg_dma_len(sg); 655 } 656 done: 657 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 658 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 659 return BLK_STS_OK; 660 free_prps: 661 nvme_free_prps(dev, req); 662 return BLK_STS_RESOURCE; 663 bad_sgl: 664 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 665 "Invalid SGL for payload:%d nents:%d\n", 666 blk_rq_payload_bytes(req), iod->sgt.nents); 667 return BLK_STS_IOERR; 668 } 669 670 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 671 struct scatterlist *sg) 672 { 673 sge->addr = cpu_to_le64(sg_dma_address(sg)); 674 sge->length = cpu_to_le32(sg_dma_len(sg)); 675 sge->type = NVME_SGL_FMT_DATA_DESC << 4; 676 } 677 678 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 679 dma_addr_t dma_addr, int entries) 680 { 681 sge->addr = cpu_to_le64(dma_addr); 682 sge->length = cpu_to_le32(entries * sizeof(*sge)); 683 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 684 } 685 686 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 687 struct request *req, struct nvme_rw_command *cmd) 688 { 689 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 690 struct dma_pool *pool; 691 struct nvme_sgl_desc *sg_list; 692 struct scatterlist *sg = iod->sgt.sgl; 693 unsigned int entries = iod->sgt.nents; 694 dma_addr_t sgl_dma; 695 int i = 0; 696 697 /* setting the transfer type as SGL */ 698 cmd->flags = NVME_CMD_SGL_METABUF; 699 700 if (entries == 1) { 701 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 702 return BLK_STS_OK; 703 } 704 705 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 706 pool = dev->prp_small_pool; 707 iod->nr_allocations = 0; 708 } else { 709 pool = dev->prp_page_pool; 710 iod->nr_allocations = 1; 711 } 712 713 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 714 if (!sg_list) { 715 iod->nr_allocations = -1; 716 return BLK_STS_RESOURCE; 717 } 718 719 iod->list[0].sg_list = sg_list; 720 iod->first_dma = sgl_dma; 721 722 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 723 do { 724 nvme_pci_sgl_set_data(&sg_list[i++], sg); 725 sg = sg_next(sg); 726 } while (--entries > 0); 727 728 return BLK_STS_OK; 729 } 730 731 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 732 struct request *req, struct nvme_rw_command *cmnd, 733 struct bio_vec *bv) 734 { 735 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 736 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 737 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 738 739 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 740 if (dma_mapping_error(dev->dev, iod->first_dma)) 741 return BLK_STS_RESOURCE; 742 iod->dma_len = bv->bv_len; 743 744 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 745 if (bv->bv_len > first_prp_len) 746 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 747 else 748 cmnd->dptr.prp2 = 0; 749 return BLK_STS_OK; 750 } 751 752 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 753 struct request *req, struct nvme_rw_command *cmnd, 754 struct bio_vec *bv) 755 { 756 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 757 758 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 759 if (dma_mapping_error(dev->dev, iod->first_dma)) 760 return BLK_STS_RESOURCE; 761 iod->dma_len = bv->bv_len; 762 763 cmnd->flags = NVME_CMD_SGL_METABUF; 764 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 765 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 766 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 767 return BLK_STS_OK; 768 } 769 770 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 771 struct nvme_command *cmnd) 772 { 773 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 774 blk_status_t ret = BLK_STS_RESOURCE; 775 int rc; 776 777 if (blk_rq_nr_phys_segments(req) == 1) { 778 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 779 struct bio_vec bv = req_bvec(req); 780 781 if (!is_pci_p2pdma_page(bv.bv_page)) { 782 if ((bv.bv_offset & (NVME_CTRL_PAGE_SIZE - 1)) + 783 bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 784 return nvme_setup_prp_simple(dev, req, 785 &cmnd->rw, &bv); 786 787 if (nvmeq->qid && sgl_threshold && 788 nvme_ctrl_sgl_supported(&dev->ctrl)) 789 return nvme_setup_sgl_simple(dev, req, 790 &cmnd->rw, &bv); 791 } 792 } 793 794 iod->dma_len = 0; 795 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 796 if (!iod->sgt.sgl) 797 return BLK_STS_RESOURCE; 798 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 799 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 800 if (!iod->sgt.orig_nents) 801 goto out_free_sg; 802 803 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 804 DMA_ATTR_NO_WARN); 805 if (rc) { 806 if (rc == -EREMOTEIO) 807 ret = BLK_STS_TARGET; 808 goto out_free_sg; 809 } 810 811 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents)) 812 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 813 else 814 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 815 if (ret != BLK_STS_OK) 816 goto out_unmap_sg; 817 return BLK_STS_OK; 818 819 out_unmap_sg: 820 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 821 out_free_sg: 822 mempool_free(iod->sgt.sgl, dev->iod_mempool); 823 return ret; 824 } 825 826 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 827 struct nvme_command *cmnd) 828 { 829 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 830 struct bio_vec bv = rq_integrity_vec(req); 831 832 iod->meta_dma = dma_map_bvec(dev->dev, &bv, rq_dma_dir(req), 0); 833 if (dma_mapping_error(dev->dev, iod->meta_dma)) 834 return BLK_STS_IOERR; 835 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 836 return BLK_STS_OK; 837 } 838 839 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 840 { 841 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 842 blk_status_t ret; 843 844 iod->aborted = false; 845 iod->nr_allocations = -1; 846 iod->sgt.nents = 0; 847 848 ret = nvme_setup_cmd(req->q->queuedata, req); 849 if (ret) 850 return ret; 851 852 if (blk_rq_nr_phys_segments(req)) { 853 ret = nvme_map_data(dev, req, &iod->cmd); 854 if (ret) 855 goto out_free_cmd; 856 } 857 858 if (blk_integrity_rq(req)) { 859 ret = nvme_map_metadata(dev, req, &iod->cmd); 860 if (ret) 861 goto out_unmap_data; 862 } 863 864 nvme_start_request(req); 865 return BLK_STS_OK; 866 out_unmap_data: 867 if (blk_rq_nr_phys_segments(req)) 868 nvme_unmap_data(dev, req); 869 out_free_cmd: 870 nvme_cleanup_cmd(req); 871 return ret; 872 } 873 874 /* 875 * NOTE: ns is NULL when called on the admin queue. 876 */ 877 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 878 const struct blk_mq_queue_data *bd) 879 { 880 struct nvme_queue *nvmeq = hctx->driver_data; 881 struct nvme_dev *dev = nvmeq->dev; 882 struct request *req = bd->rq; 883 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 884 blk_status_t ret; 885 886 /* 887 * We should not need to do this, but we're still using this to 888 * ensure we can drain requests on a dying queue. 889 */ 890 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 891 return BLK_STS_IOERR; 892 893 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 894 return nvme_fail_nonready_command(&dev->ctrl, req); 895 896 ret = nvme_prep_rq(dev, req); 897 if (unlikely(ret)) 898 return ret; 899 spin_lock(&nvmeq->sq_lock); 900 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 901 nvme_write_sq_db(nvmeq, bd->last); 902 spin_unlock(&nvmeq->sq_lock); 903 return BLK_STS_OK; 904 } 905 906 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 907 { 908 struct request *req; 909 910 spin_lock(&nvmeq->sq_lock); 911 while ((req = rq_list_pop(rqlist))) { 912 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 913 914 nvme_sq_copy_cmd(nvmeq, &iod->cmd); 915 } 916 nvme_write_sq_db(nvmeq, true); 917 spin_unlock(&nvmeq->sq_lock); 918 } 919 920 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 921 { 922 /* 923 * We should not need to do this, but we're still using this to 924 * ensure we can drain requests on a dying queue. 925 */ 926 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 927 return false; 928 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 929 return false; 930 931 req->mq_hctx->tags->rqs[req->tag] = req; 932 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 933 } 934 935 static void nvme_queue_rqs(struct request **rqlist) 936 { 937 struct request *submit_list = NULL; 938 struct request *requeue_list = NULL; 939 struct request **requeue_lastp = &requeue_list; 940 struct nvme_queue *nvmeq = NULL; 941 struct request *req; 942 943 while ((req = rq_list_pop(rqlist))) { 944 if (nvmeq && nvmeq != req->mq_hctx->driver_data) 945 nvme_submit_cmds(nvmeq, &submit_list); 946 nvmeq = req->mq_hctx->driver_data; 947 948 if (nvme_prep_rq_batch(nvmeq, req)) 949 rq_list_add(&submit_list, req); /* reverse order */ 950 else 951 rq_list_add_tail(&requeue_lastp, req); 952 } 953 954 if (nvmeq) 955 nvme_submit_cmds(nvmeq, &submit_list); 956 *rqlist = requeue_list; 957 } 958 959 static __always_inline void nvme_pci_unmap_rq(struct request *req) 960 { 961 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 962 struct nvme_dev *dev = nvmeq->dev; 963 964 if (blk_integrity_rq(req)) { 965 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 966 967 dma_unmap_page(dev->dev, iod->meta_dma, 968 rq_integrity_vec(req).bv_len, rq_dma_dir(req)); 969 } 970 971 if (blk_rq_nr_phys_segments(req)) 972 nvme_unmap_data(dev, req); 973 } 974 975 static void nvme_pci_complete_rq(struct request *req) 976 { 977 nvme_pci_unmap_rq(req); 978 nvme_complete_rq(req); 979 } 980 981 static void nvme_pci_complete_batch(struct io_comp_batch *iob) 982 { 983 nvme_complete_batch(iob, nvme_pci_unmap_rq); 984 } 985 986 /* We read the CQE phase first to check if the rest of the entry is valid */ 987 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 988 { 989 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 990 991 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 992 } 993 994 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 995 { 996 u16 head = nvmeq->cq_head; 997 998 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 999 nvmeq->dbbuf_cq_ei)) 1000 writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1001 } 1002 1003 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1004 { 1005 if (!nvmeq->qid) 1006 return nvmeq->dev->admin_tagset.tags[0]; 1007 return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1008 } 1009 1010 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1011 struct io_comp_batch *iob, u16 idx) 1012 { 1013 struct nvme_completion *cqe = &nvmeq->cqes[idx]; 1014 __u16 command_id = READ_ONCE(cqe->command_id); 1015 struct request *req; 1016 1017 /* 1018 * AEN requests are special as they don't time out and can 1019 * survive any kind of queue freeze and often don't respond to 1020 * aborts. We don't even bother to allocate a struct request 1021 * for them but rather special case them here. 1022 */ 1023 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 1024 nvme_complete_async_event(&nvmeq->dev->ctrl, 1025 cqe->status, &cqe->result); 1026 return; 1027 } 1028 1029 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 1030 if (unlikely(!req)) { 1031 dev_warn(nvmeq->dev->ctrl.device, 1032 "invalid id %d completed on queue %d\n", 1033 command_id, le16_to_cpu(cqe->sq_id)); 1034 return; 1035 } 1036 1037 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1038 if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1039 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1040 nvme_pci_complete_batch)) 1041 nvme_pci_complete_rq(req); 1042 } 1043 1044 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 1045 { 1046 u32 tmp = nvmeq->cq_head + 1; 1047 1048 if (tmp == nvmeq->q_depth) { 1049 nvmeq->cq_head = 0; 1050 nvmeq->cq_phase ^= 1; 1051 } else { 1052 nvmeq->cq_head = tmp; 1053 } 1054 } 1055 1056 static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1057 struct io_comp_batch *iob) 1058 { 1059 int found = 0; 1060 1061 while (nvme_cqe_pending(nvmeq)) { 1062 found++; 1063 /* 1064 * load-load control dependency between phase and the rest of 1065 * the cqe requires a full read memory barrier 1066 */ 1067 dma_rmb(); 1068 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 1069 nvme_update_cq_head(nvmeq); 1070 } 1071 1072 if (found) 1073 nvme_ring_cq_doorbell(nvmeq); 1074 return found; 1075 } 1076 1077 static irqreturn_t nvme_irq(int irq, void *data) 1078 { 1079 struct nvme_queue *nvmeq = data; 1080 DEFINE_IO_COMP_BATCH(iob); 1081 1082 if (nvme_poll_cq(nvmeq, &iob)) { 1083 if (!rq_list_empty(iob.req_list)) 1084 nvme_pci_complete_batch(&iob); 1085 return IRQ_HANDLED; 1086 } 1087 return IRQ_NONE; 1088 } 1089 1090 static irqreturn_t nvme_irq_check(int irq, void *data) 1091 { 1092 struct nvme_queue *nvmeq = data; 1093 1094 if (nvme_cqe_pending(nvmeq)) 1095 return IRQ_WAKE_THREAD; 1096 return IRQ_NONE; 1097 } 1098 1099 /* 1100 * Poll for completions for any interrupt driven queue 1101 * Can be called from any context. 1102 */ 1103 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1104 { 1105 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1106 1107 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1108 1109 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1110 nvme_poll_cq(nvmeq, NULL); 1111 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1112 } 1113 1114 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 1115 { 1116 struct nvme_queue *nvmeq = hctx->driver_data; 1117 bool found; 1118 1119 if (!nvme_cqe_pending(nvmeq)) 1120 return 0; 1121 1122 spin_lock(&nvmeq->cq_poll_lock); 1123 found = nvme_poll_cq(nvmeq, iob); 1124 spin_unlock(&nvmeq->cq_poll_lock); 1125 1126 return found; 1127 } 1128 1129 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 1130 { 1131 struct nvme_dev *dev = to_nvme_dev(ctrl); 1132 struct nvme_queue *nvmeq = &dev->queues[0]; 1133 struct nvme_command c = { }; 1134 1135 c.common.opcode = nvme_admin_async_event; 1136 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 1137 1138 spin_lock(&nvmeq->sq_lock); 1139 nvme_sq_copy_cmd(nvmeq, &c); 1140 nvme_write_sq_db(nvmeq, true); 1141 spin_unlock(&nvmeq->sq_lock); 1142 } 1143 1144 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 1145 { 1146 struct nvme_command c = { }; 1147 1148 c.delete_queue.opcode = opcode; 1149 c.delete_queue.qid = cpu_to_le16(id); 1150 1151 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1152 } 1153 1154 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1155 struct nvme_queue *nvmeq, s16 vector) 1156 { 1157 struct nvme_command c = { }; 1158 int flags = NVME_QUEUE_PHYS_CONTIG; 1159 1160 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1161 flags |= NVME_CQ_IRQ_ENABLED; 1162 1163 /* 1164 * Note: we (ab)use the fact that the prp fields survive if no data 1165 * is attached to the request. 1166 */ 1167 c.create_cq.opcode = nvme_admin_create_cq; 1168 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 1169 c.create_cq.cqid = cpu_to_le16(qid); 1170 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1171 c.create_cq.cq_flags = cpu_to_le16(flags); 1172 c.create_cq.irq_vector = cpu_to_le16(vector); 1173 1174 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1175 } 1176 1177 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 1178 struct nvme_queue *nvmeq) 1179 { 1180 struct nvme_ctrl *ctrl = &dev->ctrl; 1181 struct nvme_command c = { }; 1182 int flags = NVME_QUEUE_PHYS_CONTIG; 1183 1184 /* 1185 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 1186 * set. Since URGENT priority is zeroes, it makes all queues 1187 * URGENT. 1188 */ 1189 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 1190 flags |= NVME_SQ_PRIO_MEDIUM; 1191 1192 /* 1193 * Note: we (ab)use the fact that the prp fields survive if no data 1194 * is attached to the request. 1195 */ 1196 c.create_sq.opcode = nvme_admin_create_sq; 1197 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 1198 c.create_sq.sqid = cpu_to_le16(qid); 1199 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 1200 c.create_sq.sq_flags = cpu_to_le16(flags); 1201 c.create_sq.cqid = cpu_to_le16(qid); 1202 1203 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1204 } 1205 1206 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 1207 { 1208 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 1209 } 1210 1211 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 1212 { 1213 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 1214 } 1215 1216 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 1217 { 1218 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1219 1220 dev_warn(nvmeq->dev->ctrl.device, 1221 "Abort status: 0x%x", nvme_req(req)->status); 1222 atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1223 blk_mq_free_request(req); 1224 return RQ_END_IO_NONE; 1225 } 1226 1227 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1228 { 1229 /* If true, indicates loss of adapter communication, possibly by a 1230 * NVMe Subsystem reset. 1231 */ 1232 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1233 1234 /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1235 switch (nvme_ctrl_state(&dev->ctrl)) { 1236 case NVME_CTRL_RESETTING: 1237 case NVME_CTRL_CONNECTING: 1238 return false; 1239 default: 1240 break; 1241 } 1242 1243 /* We shouldn't reset unless the controller is on fatal error state 1244 * _or_ if we lost the communication with it. 1245 */ 1246 if (!(csts & NVME_CSTS_CFS) && !nssro) 1247 return false; 1248 1249 return true; 1250 } 1251 1252 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1253 { 1254 /* Read a config register to help see what died. */ 1255 u16 pci_status; 1256 int result; 1257 1258 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1259 &pci_status); 1260 if (result == PCIBIOS_SUCCESSFUL) 1261 dev_warn(dev->ctrl.device, 1262 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1263 csts, pci_status); 1264 else 1265 dev_warn(dev->ctrl.device, 1266 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1267 csts, result); 1268 1269 if (csts != ~0) 1270 return; 1271 1272 dev_warn(dev->ctrl.device, 1273 "Does your device have a faulty power saving mode enabled?\n"); 1274 dev_warn(dev->ctrl.device, 1275 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off pcie_port_pm=off\" and report a bug\n"); 1276 } 1277 1278 static enum blk_eh_timer_return nvme_timeout(struct request *req) 1279 { 1280 struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1281 struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1282 struct nvme_dev *dev = nvmeq->dev; 1283 struct request *abort_req; 1284 struct nvme_command cmd = { }; 1285 struct pci_dev *pdev = to_pci_dev(dev->dev); 1286 u32 csts = readl(dev->bar + NVME_REG_CSTS); 1287 1288 /* 1289 * Shutdown the device immediately if we see it is disconnected. This 1290 * unblocks PCIe error handling if the nvme driver is waiting in 1291 * error_resume for a device that has been removed. We can't unbind the 1292 * driver while the driver's error callback is waiting to complete, so 1293 * we're relying on a timeout to break that deadlock if a removal 1294 * occurs while reset work is running. 1295 */ 1296 if (pci_dev_is_disconnected(pdev)) 1297 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1298 if (nvme_state_terminal(&dev->ctrl)) 1299 goto disable; 1300 1301 /* If PCI error recovery process is happening, we cannot reset or 1302 * the recovery mechanism will surely fail. 1303 */ 1304 mb(); 1305 if (pci_channel_offline(pdev)) 1306 return BLK_EH_RESET_TIMER; 1307 1308 /* 1309 * Reset immediately if the controller is failed 1310 */ 1311 if (nvme_should_reset(dev, csts)) { 1312 nvme_warn_reset(dev, csts); 1313 goto disable; 1314 } 1315 1316 /* 1317 * Did we miss an interrupt? 1318 */ 1319 if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1320 nvme_poll(req->mq_hctx, NULL); 1321 else 1322 nvme_poll_irqdisable(nvmeq); 1323 1324 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { 1325 dev_warn(dev->ctrl.device, 1326 "I/O %d QID %d timeout, completion polled\n", 1327 req->tag, nvmeq->qid); 1328 return BLK_EH_DONE; 1329 } 1330 1331 /* 1332 * Shutdown immediately if controller times out while starting. The 1333 * reset work will see the pci device disabled when it gets the forced 1334 * cancellation error. All outstanding requests are completed on 1335 * shutdown, so we return BLK_EH_DONE. 1336 */ 1337 switch (nvme_ctrl_state(&dev->ctrl)) { 1338 case NVME_CTRL_CONNECTING: 1339 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1340 fallthrough; 1341 case NVME_CTRL_DELETING: 1342 dev_warn_ratelimited(dev->ctrl.device, 1343 "I/O %d QID %d timeout, disable controller\n", 1344 req->tag, nvmeq->qid); 1345 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1346 nvme_dev_disable(dev, true); 1347 return BLK_EH_DONE; 1348 case NVME_CTRL_RESETTING: 1349 return BLK_EH_RESET_TIMER; 1350 default: 1351 break; 1352 } 1353 1354 /* 1355 * Shutdown the controller immediately and schedule a reset if the 1356 * command was already aborted once before and still hasn't been 1357 * returned to the driver, or if this is the admin queue. 1358 */ 1359 if (!nvmeq->qid || iod->aborted) { 1360 dev_warn(dev->ctrl.device, 1361 "I/O %d QID %d timeout, reset controller\n", 1362 req->tag, nvmeq->qid); 1363 nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1364 goto disable; 1365 } 1366 1367 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1368 atomic_inc(&dev->ctrl.abort_limit); 1369 return BLK_EH_RESET_TIMER; 1370 } 1371 iod->aborted = true; 1372 1373 cmd.abort.opcode = nvme_admin_abort_cmd; 1374 cmd.abort.cid = nvme_cid(req); 1375 cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 1376 1377 dev_warn(nvmeq->dev->ctrl.device, 1378 "I/O %d (%s) QID %d timeout, aborting\n", 1379 req->tag, 1380 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 1381 nvmeq->qid); 1382 1383 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 1384 BLK_MQ_REQ_NOWAIT); 1385 if (IS_ERR(abort_req)) { 1386 atomic_inc(&dev->ctrl.abort_limit); 1387 return BLK_EH_RESET_TIMER; 1388 } 1389 nvme_init_request(abort_req, &cmd); 1390 1391 abort_req->end_io = abort_endio; 1392 abort_req->end_io_data = NULL; 1393 blk_execute_rq_nowait(abort_req, false); 1394 1395 /* 1396 * The aborted req will be completed on receiving the abort req. 1397 * We enable the timer again. If hit twice, it'll cause a device reset, 1398 * as the device then is in a faulty state. 1399 */ 1400 return BLK_EH_RESET_TIMER; 1401 1402 disable: 1403 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { 1404 if (nvme_state_terminal(&dev->ctrl)) 1405 nvme_dev_disable(dev, true); 1406 return BLK_EH_DONE; 1407 } 1408 1409 nvme_dev_disable(dev, false); 1410 if (nvme_try_sched_reset(&dev->ctrl)) 1411 nvme_unquiesce_io_queues(&dev->ctrl); 1412 return BLK_EH_DONE; 1413 } 1414 1415 static void nvme_free_queue(struct nvme_queue *nvmeq) 1416 { 1417 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 1418 (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 1419 if (!nvmeq->sq_cmds) 1420 return; 1421 1422 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 1423 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 1424 nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1425 } else { 1426 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 1427 nvmeq->sq_cmds, nvmeq->sq_dma_addr); 1428 } 1429 } 1430 1431 static void nvme_free_queues(struct nvme_dev *dev, int lowest) 1432 { 1433 int i; 1434 1435 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1436 dev->ctrl.queue_count--; 1437 nvme_free_queue(&dev->queues[i]); 1438 } 1439 } 1440 1441 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid) 1442 { 1443 struct nvme_queue *nvmeq = &dev->queues[qid]; 1444 1445 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 1446 return; 1447 1448 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1449 mb(); 1450 1451 nvmeq->dev->online_queues--; 1452 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1453 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 1454 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 1455 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); 1456 } 1457 1458 static void nvme_suspend_io_queues(struct nvme_dev *dev) 1459 { 1460 int i; 1461 1462 for (i = dev->ctrl.queue_count - 1; i > 0; i--) 1463 nvme_suspend_queue(dev, i); 1464 } 1465 1466 /* 1467 * Called only on a device that has been disabled and after all other threads 1468 * that can check this device's completion queues have synced, except 1469 * nvme_poll(). This is the last chance for the driver to see a natural 1470 * completion before nvme_cancel_request() terminates all incomplete requests. 1471 */ 1472 static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1473 { 1474 int i; 1475 1476 for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1477 spin_lock(&dev->queues[i].cq_poll_lock); 1478 nvme_poll_cq(&dev->queues[i], NULL); 1479 spin_unlock(&dev->queues[i].cq_poll_lock); 1480 } 1481 } 1482 1483 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 1484 int entry_size) 1485 { 1486 int q_depth = dev->q_depth; 1487 unsigned q_size_aligned = roundup(q_depth * entry_size, 1488 NVME_CTRL_PAGE_SIZE); 1489 1490 if (q_size_aligned * nr_io_queues > dev->cmb_size) { 1491 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 1492 1493 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 1494 q_depth = div_u64(mem_per_q, entry_size); 1495 1496 /* 1497 * Ensure the reduced q_depth is above some threshold where it 1498 * would be better to map queues in system memory with the 1499 * original depth 1500 */ 1501 if (q_depth < 64) 1502 return -ENOMEM; 1503 } 1504 1505 return q_depth; 1506 } 1507 1508 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 1509 int qid) 1510 { 1511 struct pci_dev *pdev = to_pci_dev(dev->dev); 1512 1513 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1514 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1515 if (nvmeq->sq_cmds) { 1516 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 1517 nvmeq->sq_cmds); 1518 if (nvmeq->sq_dma_addr) { 1519 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 1520 return 0; 1521 } 1522 1523 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1524 } 1525 } 1526 1527 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 1528 &nvmeq->sq_dma_addr, GFP_KERNEL); 1529 if (!nvmeq->sq_cmds) 1530 return -ENOMEM; 1531 return 0; 1532 } 1533 1534 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 1535 { 1536 struct nvme_queue *nvmeq = &dev->queues[qid]; 1537 1538 if (dev->ctrl.queue_count > qid) 1539 return 0; 1540 1541 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 1542 nvmeq->q_depth = depth; 1543 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 1544 &nvmeq->cq_dma_addr, GFP_KERNEL); 1545 if (!nvmeq->cqes) 1546 goto free_nvmeq; 1547 1548 if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 1549 goto free_cqdma; 1550 1551 nvmeq->dev = dev; 1552 spin_lock_init(&nvmeq->sq_lock); 1553 spin_lock_init(&nvmeq->cq_poll_lock); 1554 nvmeq->cq_head = 0; 1555 nvmeq->cq_phase = 1; 1556 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1557 nvmeq->qid = qid; 1558 dev->ctrl.queue_count++; 1559 1560 return 0; 1561 1562 free_cqdma: 1563 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 1564 nvmeq->cq_dma_addr); 1565 free_nvmeq: 1566 return -ENOMEM; 1567 } 1568 1569 static int queue_request_irq(struct nvme_queue *nvmeq) 1570 { 1571 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1572 int nr = nvmeq->dev->ctrl.instance; 1573 1574 if (use_threaded_interrupts) { 1575 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 1576 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1577 } else { 1578 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 1579 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 1580 } 1581 } 1582 1583 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 1584 { 1585 struct nvme_dev *dev = nvmeq->dev; 1586 1587 nvmeq->sq_tail = 0; 1588 nvmeq->last_sq_tail = 0; 1589 nvmeq->cq_head = 0; 1590 nvmeq->cq_phase = 1; 1591 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 1592 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1593 nvme_dbbuf_init(dev, nvmeq, qid); 1594 dev->online_queues++; 1595 wmb(); /* ensure the first interrupt sees the initialization */ 1596 } 1597 1598 /* 1599 * Try getting shutdown_lock while setting up IO queues. 1600 */ 1601 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1602 { 1603 /* 1604 * Give up if the lock is being held by nvme_dev_disable. 1605 */ 1606 if (!mutex_trylock(&dev->shutdown_lock)) 1607 return -ENODEV; 1608 1609 /* 1610 * Controller is in wrong state, fail early. 1611 */ 1612 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) { 1613 mutex_unlock(&dev->shutdown_lock); 1614 return -ENODEV; 1615 } 1616 1617 return 0; 1618 } 1619 1620 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 1621 { 1622 struct nvme_dev *dev = nvmeq->dev; 1623 int result; 1624 u16 vector = 0; 1625 1626 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1627 1628 /* 1629 * A queue's vector matches the queue identifier unless the controller 1630 * has only one vector available. 1631 */ 1632 if (!polled) 1633 vector = dev->num_vecs == 1 ? 0 : qid; 1634 else 1635 set_bit(NVMEQ_POLLED, &nvmeq->flags); 1636 1637 result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1638 if (result) 1639 return result; 1640 1641 result = adapter_alloc_sq(dev, qid, nvmeq); 1642 if (result < 0) 1643 return result; 1644 if (result) 1645 goto release_cq; 1646 1647 nvmeq->cq_vector = vector; 1648 1649 result = nvme_setup_io_queues_trylock(dev); 1650 if (result) 1651 return result; 1652 nvme_init_queue(nvmeq, qid); 1653 if (!polled) { 1654 result = queue_request_irq(nvmeq); 1655 if (result < 0) 1656 goto release_sq; 1657 } 1658 1659 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1660 mutex_unlock(&dev->shutdown_lock); 1661 return result; 1662 1663 release_sq: 1664 dev->online_queues--; 1665 mutex_unlock(&dev->shutdown_lock); 1666 adapter_delete_sq(dev, qid); 1667 release_cq: 1668 adapter_delete_cq(dev, qid); 1669 return result; 1670 } 1671 1672 static const struct blk_mq_ops nvme_mq_admin_ops = { 1673 .queue_rq = nvme_queue_rq, 1674 .complete = nvme_pci_complete_rq, 1675 .init_hctx = nvme_admin_init_hctx, 1676 .init_request = nvme_pci_init_request, 1677 .timeout = nvme_timeout, 1678 }; 1679 1680 static const struct blk_mq_ops nvme_mq_ops = { 1681 .queue_rq = nvme_queue_rq, 1682 .queue_rqs = nvme_queue_rqs, 1683 .complete = nvme_pci_complete_rq, 1684 .commit_rqs = nvme_commit_rqs, 1685 .init_hctx = nvme_init_hctx, 1686 .init_request = nvme_pci_init_request, 1687 .map_queues = nvme_pci_map_queues, 1688 .timeout = nvme_timeout, 1689 .poll = nvme_poll, 1690 }; 1691 1692 static void nvme_dev_remove_admin(struct nvme_dev *dev) 1693 { 1694 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 1695 /* 1696 * If the controller was reset during removal, it's possible 1697 * user requests may be waiting on a stopped queue. Start the 1698 * queue to flush these to completion. 1699 */ 1700 nvme_unquiesce_admin_queue(&dev->ctrl); 1701 nvme_remove_admin_tag_set(&dev->ctrl); 1702 } 1703 } 1704 1705 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 1706 { 1707 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 1708 } 1709 1710 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 1711 { 1712 struct pci_dev *pdev = to_pci_dev(dev->dev); 1713 1714 if (size <= dev->bar_mapped_size) 1715 return 0; 1716 if (size > pci_resource_len(pdev, 0)) 1717 return -ENOMEM; 1718 if (dev->bar) 1719 iounmap(dev->bar); 1720 dev->bar = ioremap(pci_resource_start(pdev, 0), size); 1721 if (!dev->bar) { 1722 dev->bar_mapped_size = 0; 1723 return -ENOMEM; 1724 } 1725 dev->bar_mapped_size = size; 1726 dev->dbs = dev->bar + NVME_REG_DBS; 1727 1728 return 0; 1729 } 1730 1731 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 1732 { 1733 int result; 1734 u32 aqa; 1735 struct nvme_queue *nvmeq; 1736 1737 result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 1738 if (result < 0) 1739 return result; 1740 1741 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 1742 NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 1743 1744 if (dev->subsystem && 1745 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 1746 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 1747 1748 /* 1749 * If the device has been passed off to us in an enabled state, just 1750 * clear the enabled bit. The spec says we should set the 'shutdown 1751 * notification bits', but doing so may cause the device to complete 1752 * commands to the admin queue ... and we don't know what memory that 1753 * might be pointing at! 1754 */ 1755 result = nvme_disable_ctrl(&dev->ctrl, false); 1756 if (result < 0) 1757 return result; 1758 1759 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1760 if (result) 1761 return result; 1762 1763 dev->ctrl.numa_node = dev_to_node(dev->dev); 1764 1765 nvmeq = &dev->queues[0]; 1766 aqa = nvmeq->q_depth - 1; 1767 aqa |= aqa << 16; 1768 1769 writel(aqa, dev->bar + NVME_REG_AQA); 1770 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 1771 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 1772 1773 result = nvme_enable_ctrl(&dev->ctrl); 1774 if (result) 1775 return result; 1776 1777 nvmeq->cq_vector = 0; 1778 nvme_init_queue(nvmeq, 0); 1779 result = queue_request_irq(nvmeq); 1780 if (result) { 1781 dev->online_queues--; 1782 return result; 1783 } 1784 1785 set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1786 return result; 1787 } 1788 1789 static int nvme_create_io_queues(struct nvme_dev *dev) 1790 { 1791 unsigned i, max, rw_queues; 1792 int ret = 0; 1793 1794 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1795 if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1796 ret = -ENOMEM; 1797 break; 1798 } 1799 } 1800 1801 max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1802 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1803 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1804 dev->io_queues[HCTX_TYPE_READ]; 1805 } else { 1806 rw_queues = max; 1807 } 1808 1809 for (i = dev->online_queues; i <= max; i++) { 1810 bool polled = i > rw_queues; 1811 1812 ret = nvme_create_queue(&dev->queues[i], i, polled); 1813 if (ret) 1814 break; 1815 } 1816 1817 /* 1818 * Ignore failing Create SQ/CQ commands, we can continue with less 1819 * than the desired amount of queues, and even a controller without 1820 * I/O queues can still be used to issue admin commands. This might 1821 * be useful to upgrade a buggy firmware for example. 1822 */ 1823 return ret >= 0 ? 0 : ret; 1824 } 1825 1826 static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 1827 { 1828 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 1829 1830 return 1ULL << (12 + 4 * szu); 1831 } 1832 1833 static u32 nvme_cmb_size(struct nvme_dev *dev) 1834 { 1835 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 1836 } 1837 1838 static void nvme_map_cmb(struct nvme_dev *dev) 1839 { 1840 u64 size, offset; 1841 resource_size_t bar_size; 1842 struct pci_dev *pdev = to_pci_dev(dev->dev); 1843 int bar; 1844 1845 if (dev->cmb_size) 1846 return; 1847 1848 if (NVME_CAP_CMBS(dev->ctrl.cap)) 1849 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 1850 1851 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1852 if (!dev->cmbsz) 1853 return; 1854 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 1855 1856 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 1857 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 1858 bar = NVME_CMB_BIR(dev->cmbloc); 1859 bar_size = pci_resource_len(pdev, bar); 1860 1861 if (offset > bar_size) 1862 return; 1863 1864 /* 1865 * Controllers may support a CMB size larger than their BAR, for 1866 * example, due to being behind a bridge. Reduce the CMB to the 1867 * reported size of the BAR 1868 */ 1869 size = min(size, bar_size - offset); 1870 1871 if (!IS_ALIGNED(size, memremap_compat_align()) || 1872 !IS_ALIGNED(pci_resource_start(pdev, bar), 1873 memremap_compat_align())) 1874 return; 1875 1876 /* 1877 * Tell the controller about the host side address mapping the CMB, 1878 * and enable CMB decoding for the NVMe 1.4+ scheme: 1879 */ 1880 if (NVME_CAP_CMBS(dev->ctrl.cap)) { 1881 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 1882 (pci_bus_address(pdev, bar) + offset), 1883 dev->bar + NVME_REG_CMBMSC); 1884 } 1885 1886 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 1887 dev_warn(dev->ctrl.device, 1888 "failed to register the CMB\n"); 1889 hi_lo_writeq(0, dev->bar + NVME_REG_CMBMSC); 1890 return; 1891 } 1892 1893 dev->cmb_size = size; 1894 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 1895 1896 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 1897 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 1898 pci_p2pmem_publish(pdev, true); 1899 1900 nvme_update_attrs(dev); 1901 } 1902 1903 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 1904 { 1905 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 1906 u64 dma_addr = dev->host_mem_descs_dma; 1907 struct nvme_command c = { }; 1908 int ret; 1909 1910 c.features.opcode = nvme_admin_set_features; 1911 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 1912 c.features.dword11 = cpu_to_le32(bits); 1913 c.features.dword12 = cpu_to_le32(host_mem_size); 1914 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 1915 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 1916 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 1917 1918 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 1919 if (ret) { 1920 dev_warn(dev->ctrl.device, 1921 "failed to set host mem (err %d, flags %#x).\n", 1922 ret, bits); 1923 } else 1924 dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1925 1926 return ret; 1927 } 1928 1929 static void nvme_free_host_mem(struct nvme_dev *dev) 1930 { 1931 int i; 1932 1933 for (i = 0; i < dev->nr_host_mem_descs; i++) { 1934 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 1935 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 1936 1937 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1938 le64_to_cpu(desc->addr), 1939 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1940 } 1941 1942 kfree(dev->host_mem_desc_bufs); 1943 dev->host_mem_desc_bufs = NULL; 1944 dma_free_coherent(dev->dev, dev->host_mem_descs_size, 1945 dev->host_mem_descs, dev->host_mem_descs_dma); 1946 dev->host_mem_descs = NULL; 1947 dev->host_mem_descs_size = 0; 1948 dev->nr_host_mem_descs = 0; 1949 } 1950 1951 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 1952 u32 chunk_size) 1953 { 1954 struct nvme_host_mem_buf_desc *descs; 1955 u32 max_entries, len, descs_size; 1956 dma_addr_t descs_dma; 1957 int i = 0; 1958 void **bufs; 1959 u64 size, tmp; 1960 1961 tmp = (preferred + chunk_size - 1); 1962 do_div(tmp, chunk_size); 1963 max_entries = tmp; 1964 1965 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1966 max_entries = dev->ctrl.hmmaxd; 1967 1968 descs_size = max_entries * sizeof(*descs); 1969 descs = dma_alloc_coherent(dev->dev, descs_size, &descs_dma, 1970 GFP_KERNEL); 1971 if (!descs) 1972 goto out; 1973 1974 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 1975 if (!bufs) 1976 goto out_free_descs; 1977 1978 for (size = 0; size < preferred && i < max_entries; size += len) { 1979 dma_addr_t dma_addr; 1980 1981 len = min_t(u64, chunk_size, preferred - size); 1982 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 1983 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 1984 if (!bufs[i]) 1985 break; 1986 1987 descs[i].addr = cpu_to_le64(dma_addr); 1988 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 1989 i++; 1990 } 1991 1992 if (!size) 1993 goto out_free_bufs; 1994 1995 dev->nr_host_mem_descs = i; 1996 dev->host_mem_size = size; 1997 dev->host_mem_descs = descs; 1998 dev->host_mem_descs_dma = descs_dma; 1999 dev->host_mem_descs_size = descs_size; 2000 dev->host_mem_desc_bufs = bufs; 2001 return 0; 2002 2003 out_free_bufs: 2004 while (--i >= 0) { 2005 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 2006 2007 dma_free_attrs(dev->dev, size, bufs[i], 2008 le64_to_cpu(descs[i].addr), 2009 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 2010 } 2011 2012 kfree(bufs); 2013 out_free_descs: 2014 dma_free_coherent(dev->dev, descs_size, descs, descs_dma); 2015 out: 2016 dev->host_mem_descs = NULL; 2017 return -ENOMEM; 2018 } 2019 2020 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 2021 { 2022 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 2023 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 2024 u64 chunk_size; 2025 2026 /* start big and work our way down */ 2027 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 2028 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 2029 if (!min || dev->host_mem_size >= min) 2030 return 0; 2031 nvme_free_host_mem(dev); 2032 } 2033 } 2034 2035 return -ENOMEM; 2036 } 2037 2038 static int nvme_setup_host_mem(struct nvme_dev *dev) 2039 { 2040 u64 max = (u64)max_host_mem_size_mb * SZ_1M; 2041 u64 preferred = (u64)dev->ctrl.hmpre * 4096; 2042 u64 min = (u64)dev->ctrl.hmmin * 4096; 2043 u32 enable_bits = NVME_HOST_MEM_ENABLE; 2044 int ret; 2045 2046 if (!dev->ctrl.hmpre) 2047 return 0; 2048 2049 preferred = min(preferred, max); 2050 if (min > max) { 2051 dev_warn(dev->ctrl.device, 2052 "min host memory (%lld MiB) above limit (%d MiB).\n", 2053 min >> ilog2(SZ_1M), max_host_mem_size_mb); 2054 nvme_free_host_mem(dev); 2055 return 0; 2056 } 2057 2058 /* 2059 * If we already have a buffer allocated check if we can reuse it. 2060 */ 2061 if (dev->host_mem_descs) { 2062 if (dev->host_mem_size >= min) 2063 enable_bits |= NVME_HOST_MEM_RETURN; 2064 else 2065 nvme_free_host_mem(dev); 2066 } 2067 2068 if (!dev->host_mem_descs) { 2069 if (nvme_alloc_host_mem(dev, min, preferred)) { 2070 dev_warn(dev->ctrl.device, 2071 "failed to allocate host memory buffer.\n"); 2072 return 0; /* controller must work without HMB */ 2073 } 2074 2075 dev_info(dev->ctrl.device, 2076 "allocated %lld MiB host memory buffer.\n", 2077 dev->host_mem_size >> ilog2(SZ_1M)); 2078 } 2079 2080 ret = nvme_set_host_mem(dev, enable_bits); 2081 if (ret) 2082 nvme_free_host_mem(dev); 2083 return ret; 2084 } 2085 2086 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 2087 char *buf) 2088 { 2089 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2090 2091 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 2092 ndev->cmbloc, ndev->cmbsz); 2093 } 2094 static DEVICE_ATTR_RO(cmb); 2095 2096 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 2097 char *buf) 2098 { 2099 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2100 2101 return sysfs_emit(buf, "%u\n", ndev->cmbloc); 2102 } 2103 static DEVICE_ATTR_RO(cmbloc); 2104 2105 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 2106 char *buf) 2107 { 2108 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2109 2110 return sysfs_emit(buf, "%u\n", ndev->cmbsz); 2111 } 2112 static DEVICE_ATTR_RO(cmbsz); 2113 2114 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2115 char *buf) 2116 { 2117 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2118 2119 return sysfs_emit(buf, "%d\n", ndev->hmb); 2120 } 2121 2122 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2123 const char *buf, size_t count) 2124 { 2125 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2126 bool new; 2127 int ret; 2128 2129 if (kstrtobool(buf, &new) < 0) 2130 return -EINVAL; 2131 2132 if (new == ndev->hmb) 2133 return count; 2134 2135 if (new) { 2136 ret = nvme_setup_host_mem(ndev); 2137 } else { 2138 ret = nvme_set_host_mem(ndev, 0); 2139 if (!ret) 2140 nvme_free_host_mem(ndev); 2141 } 2142 2143 if (ret < 0) 2144 return ret; 2145 2146 return count; 2147 } 2148 static DEVICE_ATTR_RW(hmb); 2149 2150 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 2151 struct attribute *a, int n) 2152 { 2153 struct nvme_ctrl *ctrl = 2154 dev_get_drvdata(container_of(kobj, struct device, kobj)); 2155 struct nvme_dev *dev = to_nvme_dev(ctrl); 2156 2157 if (a == &dev_attr_cmb.attr || 2158 a == &dev_attr_cmbloc.attr || 2159 a == &dev_attr_cmbsz.attr) { 2160 if (!dev->cmbsz) 2161 return 0; 2162 } 2163 if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2164 return 0; 2165 2166 return a->mode; 2167 } 2168 2169 static struct attribute *nvme_pci_attrs[] = { 2170 &dev_attr_cmb.attr, 2171 &dev_attr_cmbloc.attr, 2172 &dev_attr_cmbsz.attr, 2173 &dev_attr_hmb.attr, 2174 NULL, 2175 }; 2176 2177 static const struct attribute_group nvme_pci_dev_attrs_group = { 2178 .attrs = nvme_pci_attrs, 2179 .is_visible = nvme_pci_attrs_are_visible, 2180 }; 2181 2182 static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 2183 &nvme_dev_attrs_group, 2184 &nvme_pci_dev_attrs_group, 2185 NULL, 2186 }; 2187 2188 static void nvme_update_attrs(struct nvme_dev *dev) 2189 { 2190 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group); 2191 } 2192 2193 /* 2194 * nirqs is the number of interrupts available for write and read 2195 * queues. The core already reserved an interrupt for the admin queue. 2196 */ 2197 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 2198 { 2199 struct nvme_dev *dev = affd->priv; 2200 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2201 2202 /* 2203 * If there is no interrupt available for queues, ensure that 2204 * the default queue is set to 1. The affinity set size is 2205 * also set to one, but the irq core ignores it for this case. 2206 * 2207 * If only one interrupt is available or 'write_queue' == 0, combine 2208 * write and read queues. 2209 * 2210 * If 'write_queues' > 0, ensure it leaves room for at least one read 2211 * queue. 2212 */ 2213 if (!nrirqs) { 2214 nrirqs = 1; 2215 nr_read_queues = 0; 2216 } else if (nrirqs == 1 || !nr_write_queues) { 2217 nr_read_queues = 0; 2218 } else if (nr_write_queues >= nrirqs) { 2219 nr_read_queues = 1; 2220 } else { 2221 nr_read_queues = nrirqs - nr_write_queues; 2222 } 2223 2224 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2225 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2226 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2227 affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2228 affd->nr_sets = nr_read_queues ? 2 : 1; 2229 } 2230 2231 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 2232 { 2233 struct pci_dev *pdev = to_pci_dev(dev->dev); 2234 struct irq_affinity affd = { 2235 .pre_vectors = 1, 2236 .calc_sets = nvme_calc_irq_sets, 2237 .priv = dev, 2238 }; 2239 unsigned int irq_queues, poll_queues; 2240 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY; 2241 2242 /* 2243 * Poll queues don't need interrupts, but we need at least one I/O queue 2244 * left over for non-polled I/O. 2245 */ 2246 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 2247 dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 2248 2249 /* 2250 * Initialize for the single interrupt case, will be updated in 2251 * nvme_calc_irq_sets(). 2252 */ 2253 dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2254 dev->io_queues[HCTX_TYPE_READ] = 0; 2255 2256 /* 2257 * We need interrupts for the admin queue and each non-polled I/O queue, 2258 * but some Apple controllers require all queues to use the first 2259 * vector. 2260 */ 2261 irq_queues = 1; 2262 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 2263 irq_queues += (nr_io_queues - poll_queues); 2264 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) 2265 flags &= ~PCI_IRQ_MSI; 2266 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags, 2267 &affd); 2268 } 2269 2270 static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 2271 { 2272 /* 2273 * If tags are shared with admin queue (Apple bug), then 2274 * make sure we only use one IO queue. 2275 */ 2276 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2277 return 1; 2278 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 2279 } 2280 2281 static int nvme_setup_io_queues(struct nvme_dev *dev) 2282 { 2283 struct nvme_queue *adminq = &dev->queues[0]; 2284 struct pci_dev *pdev = to_pci_dev(dev->dev); 2285 unsigned int nr_io_queues; 2286 unsigned long size; 2287 int result; 2288 2289 /* 2290 * Sample the module parameters once at reset time so that we have 2291 * stable values to work with. 2292 */ 2293 dev->nr_write_queues = write_queues; 2294 dev->nr_poll_queues = poll_queues; 2295 2296 nr_io_queues = dev->nr_allocated_queues - 1; 2297 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 2298 if (result < 0) 2299 return result; 2300 2301 if (nr_io_queues == 0) 2302 return 0; 2303 2304 /* 2305 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2306 * from set to unset. If there is a window to it is truely freed, 2307 * pci_free_irq_vectors() jumping into this window will crash. 2308 * And take lock to avoid racing with pci_free_irq_vectors() in 2309 * nvme_dev_disable() path. 2310 */ 2311 result = nvme_setup_io_queues_trylock(dev); 2312 if (result) 2313 return result; 2314 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2315 pci_free_irq(pdev, 0, adminq); 2316 2317 if (dev->cmb_use_sqes) { 2318 result = nvme_cmb_qdepth(dev, nr_io_queues, 2319 sizeof(struct nvme_command)); 2320 if (result > 0) { 2321 dev->q_depth = result; 2322 dev->ctrl.sqsize = result - 1; 2323 } else { 2324 dev->cmb_use_sqes = false; 2325 } 2326 } 2327 2328 do { 2329 size = db_bar_size(dev, nr_io_queues); 2330 result = nvme_remap_bar(dev, size); 2331 if (!result) 2332 break; 2333 if (!--nr_io_queues) { 2334 result = -ENOMEM; 2335 goto out_unlock; 2336 } 2337 } while (1); 2338 adminq->q_db = dev->dbs; 2339 2340 retry: 2341 /* Deregister the admin queue's interrupt */ 2342 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2343 pci_free_irq(pdev, 0, adminq); 2344 2345 /* 2346 * If we enable msix early due to not intx, disable it again before 2347 * setting up the full range we need. 2348 */ 2349 pci_free_irq_vectors(pdev); 2350 2351 result = nvme_setup_irqs(dev, nr_io_queues); 2352 if (result <= 0) { 2353 result = -EIO; 2354 goto out_unlock; 2355 } 2356 2357 dev->num_vecs = result; 2358 result = max(result - 1, 1); 2359 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 2360 2361 /* 2362 * Should investigate if there's a performance win from allocating 2363 * more queues than interrupt vectors; it might allow the submission 2364 * path to scale better, even if the receive path is limited by the 2365 * number of interrupts. 2366 */ 2367 result = queue_request_irq(adminq); 2368 if (result) 2369 goto out_unlock; 2370 set_bit(NVMEQ_ENABLED, &adminq->flags); 2371 mutex_unlock(&dev->shutdown_lock); 2372 2373 result = nvme_create_io_queues(dev); 2374 if (result || dev->online_queues < 2) 2375 return result; 2376 2377 if (dev->online_queues - 1 < dev->max_qid) { 2378 nr_io_queues = dev->online_queues - 1; 2379 nvme_delete_io_queues(dev); 2380 result = nvme_setup_io_queues_trylock(dev); 2381 if (result) 2382 return result; 2383 nvme_suspend_io_queues(dev); 2384 goto retry; 2385 } 2386 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2387 dev->io_queues[HCTX_TYPE_DEFAULT], 2388 dev->io_queues[HCTX_TYPE_READ], 2389 dev->io_queues[HCTX_TYPE_POLL]); 2390 return 0; 2391 out_unlock: 2392 mutex_unlock(&dev->shutdown_lock); 2393 return result; 2394 } 2395 2396 static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2397 blk_status_t error) 2398 { 2399 struct nvme_queue *nvmeq = req->end_io_data; 2400 2401 blk_mq_free_request(req); 2402 complete(&nvmeq->delete_done); 2403 return RQ_END_IO_NONE; 2404 } 2405 2406 static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2407 blk_status_t error) 2408 { 2409 struct nvme_queue *nvmeq = req->end_io_data; 2410 2411 if (error) 2412 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2413 2414 return nvme_del_queue_end(req, error); 2415 } 2416 2417 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2418 { 2419 struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2420 struct request *req; 2421 struct nvme_command cmd = { }; 2422 2423 cmd.delete_queue.opcode = opcode; 2424 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2425 2426 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2427 if (IS_ERR(req)) 2428 return PTR_ERR(req); 2429 nvme_init_request(req, &cmd); 2430 2431 if (opcode == nvme_admin_delete_cq) 2432 req->end_io = nvme_del_cq_end; 2433 else 2434 req->end_io = nvme_del_queue_end; 2435 req->end_io_data = nvmeq; 2436 2437 init_completion(&nvmeq->delete_done); 2438 blk_execute_rq_nowait(req, false); 2439 return 0; 2440 } 2441 2442 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode) 2443 { 2444 int nr_queues = dev->online_queues - 1, sent = 0; 2445 unsigned long timeout; 2446 2447 retry: 2448 timeout = NVME_ADMIN_TIMEOUT; 2449 while (nr_queues > 0) { 2450 if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2451 break; 2452 nr_queues--; 2453 sent++; 2454 } 2455 while (sent) { 2456 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2457 2458 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 2459 timeout); 2460 if (timeout == 0) 2461 return false; 2462 2463 sent--; 2464 if (nr_queues) 2465 goto retry; 2466 } 2467 return true; 2468 } 2469 2470 static void nvme_delete_io_queues(struct nvme_dev *dev) 2471 { 2472 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq)) 2473 __nvme_delete_io_queues(dev, nvme_admin_delete_cq); 2474 } 2475 2476 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev) 2477 { 2478 if (dev->io_queues[HCTX_TYPE_POLL]) 2479 return 3; 2480 if (dev->io_queues[HCTX_TYPE_READ]) 2481 return 2; 2482 return 1; 2483 } 2484 2485 static bool nvme_pci_update_nr_queues(struct nvme_dev *dev) 2486 { 2487 if (!dev->ctrl.tagset) { 2488 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, 2489 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod)); 2490 return true; 2491 } 2492 2493 /* Give up if we are racing with nvme_dev_disable() */ 2494 if (!mutex_trylock(&dev->shutdown_lock)) 2495 return false; 2496 2497 /* Check if nvme_dev_disable() has been executed already */ 2498 if (!dev->online_queues) { 2499 mutex_unlock(&dev->shutdown_lock); 2500 return false; 2501 } 2502 2503 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2504 /* free previously allocated queues that are no longer usable */ 2505 nvme_free_queues(dev, dev->online_queues); 2506 mutex_unlock(&dev->shutdown_lock); 2507 return true; 2508 } 2509 2510 static int nvme_pci_enable(struct nvme_dev *dev) 2511 { 2512 int result = -ENOMEM; 2513 struct pci_dev *pdev = to_pci_dev(dev->dev); 2514 unsigned int flags = PCI_IRQ_ALL_TYPES; 2515 2516 if (pci_enable_device_mem(pdev)) 2517 return result; 2518 2519 pci_set_master(pdev); 2520 2521 if (readl(dev->bar + NVME_REG_CSTS) == -1) { 2522 result = -ENODEV; 2523 goto disable; 2524 } 2525 2526 /* 2527 * Some devices and/or platforms don't advertise or work with INTx 2528 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2529 * adjust this later. 2530 */ 2531 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI) 2532 flags &= ~PCI_IRQ_MSI; 2533 result = pci_alloc_irq_vectors(pdev, 1, 1, flags); 2534 if (result < 0) 2535 goto disable; 2536 2537 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 2538 2539 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2540 io_queue_depth); 2541 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 2542 dev->dbs = dev->bar + 4096; 2543 2544 /* 2545 * Some Apple controllers require a non-standard SQE size. 2546 * Interestingly they also seem to ignore the CC:IOSQES register 2547 * so we don't bother updating it here. 2548 */ 2549 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 2550 dev->io_sqes = 7; 2551 else 2552 dev->io_sqes = NVME_NVM_IOSQES; 2553 2554 if (dev->ctrl.quirks & NVME_QUIRK_QDEPTH_ONE) { 2555 dev->q_depth = 2; 2556 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2557 (pdev->device == 0xa821 || pdev->device == 0xa822) && 2558 NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2559 dev->q_depth = 64; 2560 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2561 "set queue depth=%u\n", dev->q_depth); 2562 } 2563 2564 /* 2565 * Controllers with the shared tags quirk need the IO queue to be 2566 * big enough so that we get 32 tags for the admin queue 2567 */ 2568 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2569 (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2570 dev->q_depth = NVME_AQ_DEPTH + 2; 2571 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2572 dev->q_depth); 2573 } 2574 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2575 2576 nvme_map_cmb(dev); 2577 2578 pci_save_state(pdev); 2579 2580 result = nvme_pci_configure_admin_queue(dev); 2581 if (result) 2582 goto free_irq; 2583 return result; 2584 2585 free_irq: 2586 pci_free_irq_vectors(pdev); 2587 disable: 2588 pci_disable_device(pdev); 2589 return result; 2590 } 2591 2592 static void nvme_dev_unmap(struct nvme_dev *dev) 2593 { 2594 if (dev->bar) 2595 iounmap(dev->bar); 2596 pci_release_mem_regions(to_pci_dev(dev->dev)); 2597 } 2598 2599 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev) 2600 { 2601 struct pci_dev *pdev = to_pci_dev(dev->dev); 2602 u32 csts; 2603 2604 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev)) 2605 return true; 2606 if (pdev->error_state != pci_channel_io_normal) 2607 return true; 2608 2609 csts = readl(dev->bar + NVME_REG_CSTS); 2610 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY); 2611 } 2612 2613 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 2614 { 2615 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl); 2616 struct pci_dev *pdev = to_pci_dev(dev->dev); 2617 bool dead; 2618 2619 mutex_lock(&dev->shutdown_lock); 2620 dead = nvme_pci_ctrl_is_dead(dev); 2621 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) { 2622 if (pci_is_enabled(pdev)) 2623 nvme_start_freeze(&dev->ctrl); 2624 /* 2625 * Give the controller a chance to complete all entered requests 2626 * if doing a safe shutdown. 2627 */ 2628 if (!dead && shutdown) 2629 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 2630 } 2631 2632 nvme_quiesce_io_queues(&dev->ctrl); 2633 2634 if (!dead && dev->ctrl.queue_count > 0) { 2635 nvme_delete_io_queues(dev); 2636 nvme_disable_ctrl(&dev->ctrl, shutdown); 2637 nvme_poll_irqdisable(&dev->queues[0]); 2638 } 2639 nvme_suspend_io_queues(dev); 2640 nvme_suspend_queue(dev, 0); 2641 pci_free_irq_vectors(pdev); 2642 if (pci_is_enabled(pdev)) 2643 pci_disable_device(pdev); 2644 nvme_reap_pending_cqes(dev); 2645 2646 nvme_cancel_tagset(&dev->ctrl); 2647 nvme_cancel_admin_tagset(&dev->ctrl); 2648 2649 /* 2650 * The driver will not be starting up queues again if shutting down so 2651 * must flush all entered requests to their failed completion to avoid 2652 * deadlocking blk-mq hot-cpu notifier. 2653 */ 2654 if (shutdown) { 2655 nvme_unquiesce_io_queues(&dev->ctrl); 2656 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2657 nvme_unquiesce_admin_queue(&dev->ctrl); 2658 } 2659 mutex_unlock(&dev->shutdown_lock); 2660 } 2661 2662 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2663 { 2664 if (!nvme_wait_reset(&dev->ctrl)) 2665 return -EBUSY; 2666 nvme_dev_disable(dev, shutdown); 2667 return 0; 2668 } 2669 2670 static int nvme_setup_prp_pools(struct nvme_dev *dev) 2671 { 2672 size_t small_align = 256; 2673 2674 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2675 NVME_CTRL_PAGE_SIZE, 2676 NVME_CTRL_PAGE_SIZE, 0); 2677 if (!dev->prp_page_pool) 2678 return -ENOMEM; 2679 2680 if (dev->ctrl.quirks & NVME_QUIRK_DMAPOOL_ALIGN_512) 2681 small_align = 512; 2682 2683 /* Optimisation for I/Os between 4k and 128k */ 2684 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 2685 256, small_align, 0); 2686 if (!dev->prp_small_pool) { 2687 dma_pool_destroy(dev->prp_page_pool); 2688 return -ENOMEM; 2689 } 2690 return 0; 2691 } 2692 2693 static void nvme_release_prp_pools(struct nvme_dev *dev) 2694 { 2695 dma_pool_destroy(dev->prp_page_pool); 2696 dma_pool_destroy(dev->prp_small_pool); 2697 } 2698 2699 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2700 { 2701 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS; 2702 2703 dev->iod_mempool = mempool_create_node(1, 2704 mempool_kmalloc, mempool_kfree, 2705 (void *)alloc_size, GFP_KERNEL, 2706 dev_to_node(dev->dev)); 2707 if (!dev->iod_mempool) 2708 return -ENOMEM; 2709 return 0; 2710 } 2711 2712 static void nvme_free_tagset(struct nvme_dev *dev) 2713 { 2714 if (dev->tagset.tags) 2715 nvme_remove_io_tag_set(&dev->ctrl); 2716 dev->ctrl.tagset = NULL; 2717 } 2718 2719 /* pairs with nvme_pci_alloc_dev */ 2720 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 2721 { 2722 struct nvme_dev *dev = to_nvme_dev(ctrl); 2723 2724 nvme_free_tagset(dev); 2725 put_device(dev->dev); 2726 kfree(dev->queues); 2727 kfree(dev); 2728 } 2729 2730 static void nvme_reset_work(struct work_struct *work) 2731 { 2732 struct nvme_dev *dev = 2733 container_of(work, struct nvme_dev, ctrl.reset_work); 2734 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2735 int result; 2736 2737 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) { 2738 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 2739 dev->ctrl.state); 2740 result = -ENODEV; 2741 goto out; 2742 } 2743 2744 /* 2745 * If we're called to reset a live controller first shut it down before 2746 * moving on. 2747 */ 2748 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2749 nvme_dev_disable(dev, false); 2750 nvme_sync_queues(&dev->ctrl); 2751 2752 mutex_lock(&dev->shutdown_lock); 2753 result = nvme_pci_enable(dev); 2754 if (result) 2755 goto out_unlock; 2756 nvme_unquiesce_admin_queue(&dev->ctrl); 2757 mutex_unlock(&dev->shutdown_lock); 2758 2759 /* 2760 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2761 * initializing procedure here. 2762 */ 2763 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2764 dev_warn(dev->ctrl.device, 2765 "failed to mark controller CONNECTING\n"); 2766 result = -EBUSY; 2767 goto out; 2768 } 2769 2770 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2771 if (result) 2772 goto out; 2773 2774 nvme_dbbuf_dma_alloc(dev); 2775 2776 result = nvme_setup_host_mem(dev); 2777 if (result < 0) 2778 goto out; 2779 2780 result = nvme_setup_io_queues(dev); 2781 if (result) 2782 goto out; 2783 2784 /* 2785 * Freeze and update the number of I/O queues as thos might have 2786 * changed. If there are no I/O queues left after this reset, keep the 2787 * controller around but remove all namespaces. 2788 */ 2789 if (dev->online_queues > 1) { 2790 nvme_dbbuf_set(dev); 2791 nvme_unquiesce_io_queues(&dev->ctrl); 2792 nvme_wait_freeze(&dev->ctrl); 2793 if (!nvme_pci_update_nr_queues(dev)) 2794 goto out; 2795 nvme_unfreeze(&dev->ctrl); 2796 } else { 2797 dev_warn(dev->ctrl.device, "IO queues lost\n"); 2798 nvme_mark_namespaces_dead(&dev->ctrl); 2799 nvme_unquiesce_io_queues(&dev->ctrl); 2800 nvme_remove_namespaces(&dev->ctrl); 2801 nvme_free_tagset(dev); 2802 } 2803 2804 /* 2805 * If only admin queue live, keep it to do further investigation or 2806 * recovery. 2807 */ 2808 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2809 dev_warn(dev->ctrl.device, 2810 "failed to mark controller live state\n"); 2811 result = -ENODEV; 2812 goto out; 2813 } 2814 2815 nvme_start_ctrl(&dev->ctrl); 2816 return; 2817 2818 out_unlock: 2819 mutex_unlock(&dev->shutdown_lock); 2820 out: 2821 /* 2822 * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2823 * may be holding this pci_dev's device lock. 2824 */ 2825 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2826 result); 2827 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2828 nvme_dev_disable(dev, true); 2829 nvme_sync_queues(&dev->ctrl); 2830 nvme_mark_namespaces_dead(&dev->ctrl); 2831 nvme_unquiesce_io_queues(&dev->ctrl); 2832 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 2833 } 2834 2835 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 2836 { 2837 *val = readl(to_nvme_dev(ctrl)->bar + off); 2838 return 0; 2839 } 2840 2841 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 2842 { 2843 writel(val, to_nvme_dev(ctrl)->bar + off); 2844 return 0; 2845 } 2846 2847 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 2848 { 2849 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 2850 return 0; 2851 } 2852 2853 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 2854 { 2855 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2856 2857 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 2858 } 2859 2860 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 2861 { 2862 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 2863 struct nvme_subsystem *subsys = ctrl->subsys; 2864 2865 dev_err(ctrl->device, 2866 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 2867 pdev->vendor, pdev->device, 2868 nvme_strlen(subsys->model, sizeof(subsys->model)), 2869 subsys->model, nvme_strlen(subsys->firmware_rev, 2870 sizeof(subsys->firmware_rev)), 2871 subsys->firmware_rev); 2872 } 2873 2874 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 2875 { 2876 struct nvme_dev *dev = to_nvme_dev(ctrl); 2877 2878 return dma_pci_p2pdma_supported(dev->dev); 2879 } 2880 2881 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 2882 .name = "pcie", 2883 .module = THIS_MODULE, 2884 .flags = NVME_F_METADATA_SUPPORTED, 2885 .dev_attr_groups = nvme_pci_dev_attr_groups, 2886 .reg_read32 = nvme_pci_reg_read32, 2887 .reg_write32 = nvme_pci_reg_write32, 2888 .reg_read64 = nvme_pci_reg_read64, 2889 .free_ctrl = nvme_pci_free_ctrl, 2890 .submit_async_event = nvme_pci_submit_async_event, 2891 .get_address = nvme_pci_get_address, 2892 .print_device_info = nvme_pci_print_device_info, 2893 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 2894 }; 2895 2896 static int nvme_dev_map(struct nvme_dev *dev) 2897 { 2898 struct pci_dev *pdev = to_pci_dev(dev->dev); 2899 2900 if (pci_request_mem_regions(pdev, "nvme")) 2901 return -ENODEV; 2902 2903 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2904 goto release; 2905 2906 return 0; 2907 release: 2908 pci_release_mem_regions(pdev); 2909 return -ENODEV; 2910 } 2911 2912 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2913 { 2914 if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2915 /* 2916 * Several Samsung devices seem to drop off the PCIe bus 2917 * randomly when APST is on and uses the deepest sleep state. 2918 * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2919 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2920 * 950 PRO 256GB", but it seems to be restricted to two Dell 2921 * laptops. 2922 */ 2923 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2924 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2925 dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2926 return NVME_QUIRK_NO_DEEPEST_PS; 2927 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 2928 /* 2929 * Samsung SSD 960 EVO drops off the PCIe bus after system 2930 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2931 * within few minutes after bootup on a Coffee Lake board - 2932 * ASUS PRIME Z370-A 2933 */ 2934 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2935 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2936 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 2937 return NVME_QUIRK_NO_APST; 2938 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 2939 pdev->device == 0xa808 || pdev->device == 0xa809)) || 2940 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 2941 /* 2942 * Forcing to use host managed nvme power settings for 2943 * lowest idle power with quick resume latency on 2944 * Samsung and Toshiba SSDs based on suspend behavior 2945 * on Coffee Lake board for LENOVO C640 2946 */ 2947 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 2948 dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 2949 return NVME_QUIRK_SIMPLE_SUSPEND; 2950 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 || 2951 pdev->device == 0x500f)) { 2952 /* 2953 * Exclude some Kingston NV1 and A2000 devices from 2954 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a 2955 * lot fo energy with s2idle sleep on some TUXEDO platforms. 2956 */ 2957 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") || 2958 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") || 2959 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") || 2960 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1")) 2961 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND; 2962 } else if (pdev->vendor == 0x144d && pdev->device == 0xa80d) { 2963 /* 2964 * Exclude Samsung 990 Evo from NVME_QUIRK_SIMPLE_SUSPEND 2965 * because of high power consumption (> 2 Watt) in s2idle 2966 * sleep. Only some boards with Intel CPU are affected. 2967 */ 2968 if (dmi_match(DMI_BOARD_NAME, "DN50Z-140HC-YD") || 2969 dmi_match(DMI_BOARD_NAME, "GMxPXxx") || 2970 dmi_match(DMI_BOARD_NAME, "GXxMRXx") || 2971 dmi_match(DMI_BOARD_NAME, "PH4PG31") || 2972 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1") || 2973 dmi_match(DMI_BOARD_NAME, "PH6PG01_PH6PG71")) 2974 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND; 2975 } 2976 2977 /* 2978 * NVMe SSD drops off the PCIe bus after system idle 2979 * for 10 hours on a Lenovo N60z board. 2980 */ 2981 if (dmi_match(DMI_BOARD_NAME, "LXKT-ZXEG-N6")) 2982 return NVME_QUIRK_NO_APST; 2983 2984 return 0; 2985 } 2986 2987 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 2988 const struct pci_device_id *id) 2989 { 2990 unsigned long quirks = id->driver_data; 2991 int node = dev_to_node(&pdev->dev); 2992 struct nvme_dev *dev; 2993 int ret = -ENOMEM; 2994 2995 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 2996 if (!dev) 2997 return ERR_PTR(-ENOMEM); 2998 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 2999 mutex_init(&dev->shutdown_lock); 3000 3001 dev->nr_write_queues = write_queues; 3002 dev->nr_poll_queues = poll_queues; 3003 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 3004 dev->queues = kcalloc_node(dev->nr_allocated_queues, 3005 sizeof(struct nvme_queue), GFP_KERNEL, node); 3006 if (!dev->queues) 3007 goto out_free_dev; 3008 3009 dev->dev = get_device(&pdev->dev); 3010 3011 quirks |= check_vendor_combination_bug(pdev); 3012 if (!noacpi && 3013 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) && 3014 acpi_storage_d3(&pdev->dev)) { 3015 /* 3016 * Some systems use a bios work around to ask for D3 on 3017 * platforms that support kernel managed suspend. 3018 */ 3019 dev_info(&pdev->dev, 3020 "platform quirk: setting simple suspend\n"); 3021 quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3022 } 3023 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3024 quirks); 3025 if (ret) 3026 goto out_put_device; 3027 3028 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 3029 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)); 3030 else 3031 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 3032 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 3033 dma_set_max_seg_size(&pdev->dev, 0xffffffff); 3034 3035 /* 3036 * Limit the max command size to prevent iod->sg allocations going 3037 * over a single page. 3038 */ 3039 dev->ctrl.max_hw_sectors = min_t(u32, 3040 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9); 3041 dev->ctrl.max_segments = NVME_MAX_SEGS; 3042 3043 /* 3044 * There is no support for SGLs for metadata (yet), so we are limited to 3045 * a single integrity segment for the separate metadata pointer. 3046 */ 3047 dev->ctrl.max_integrity_segments = 1; 3048 return dev; 3049 3050 out_put_device: 3051 put_device(dev->dev); 3052 kfree(dev->queues); 3053 out_free_dev: 3054 kfree(dev); 3055 return ERR_PTR(ret); 3056 } 3057 3058 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3059 { 3060 struct nvme_dev *dev; 3061 int result = -ENOMEM; 3062 3063 dev = nvme_pci_alloc_dev(pdev, id); 3064 if (IS_ERR(dev)) 3065 return PTR_ERR(dev); 3066 3067 result = nvme_dev_map(dev); 3068 if (result) 3069 goto out_uninit_ctrl; 3070 3071 result = nvme_setup_prp_pools(dev); 3072 if (result) 3073 goto out_dev_unmap; 3074 3075 result = nvme_pci_alloc_iod_mempool(dev); 3076 if (result) 3077 goto out_release_prp_pools; 3078 3079 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3080 3081 result = nvme_pci_enable(dev); 3082 if (result) 3083 goto out_release_iod_mempool; 3084 3085 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset, 3086 &nvme_mq_admin_ops, sizeof(struct nvme_iod)); 3087 if (result) 3088 goto out_disable; 3089 3090 /* 3091 * Mark the controller as connecting before sending admin commands to 3092 * allow the timeout handler to do the right thing. 3093 */ 3094 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3095 dev_warn(dev->ctrl.device, 3096 "failed to mark controller CONNECTING\n"); 3097 result = -EBUSY; 3098 goto out_disable; 3099 } 3100 3101 result = nvme_init_ctrl_finish(&dev->ctrl, false); 3102 if (result) 3103 goto out_disable; 3104 3105 nvme_dbbuf_dma_alloc(dev); 3106 3107 result = nvme_setup_host_mem(dev); 3108 if (result < 0) 3109 goto out_disable; 3110 3111 result = nvme_setup_io_queues(dev); 3112 if (result) 3113 goto out_disable; 3114 3115 if (dev->online_queues > 1) { 3116 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, 3117 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod)); 3118 nvme_dbbuf_set(dev); 3119 } 3120 3121 if (!dev->ctrl.tagset) 3122 dev_warn(dev->ctrl.device, "IO queues not created\n"); 3123 3124 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3125 dev_warn(dev->ctrl.device, 3126 "failed to mark controller live state\n"); 3127 result = -ENODEV; 3128 goto out_disable; 3129 } 3130 3131 pci_set_drvdata(pdev, dev); 3132 3133 nvme_start_ctrl(&dev->ctrl); 3134 nvme_put_ctrl(&dev->ctrl); 3135 flush_work(&dev->ctrl.scan_work); 3136 return 0; 3137 3138 out_disable: 3139 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3140 nvme_dev_disable(dev, true); 3141 nvme_free_host_mem(dev); 3142 nvme_dev_remove_admin(dev); 3143 nvme_dbbuf_dma_free(dev); 3144 nvme_free_queues(dev, 0); 3145 out_release_iod_mempool: 3146 mempool_destroy(dev->iod_mempool); 3147 out_release_prp_pools: 3148 nvme_release_prp_pools(dev); 3149 out_dev_unmap: 3150 nvme_dev_unmap(dev); 3151 out_uninit_ctrl: 3152 nvme_uninit_ctrl(&dev->ctrl); 3153 nvme_put_ctrl(&dev->ctrl); 3154 return result; 3155 } 3156 3157 static void nvme_reset_prepare(struct pci_dev *pdev) 3158 { 3159 struct nvme_dev *dev = pci_get_drvdata(pdev); 3160 3161 /* 3162 * We don't need to check the return value from waiting for the reset 3163 * state as pci_dev device lock is held, making it impossible to race 3164 * with ->remove(). 3165 */ 3166 nvme_disable_prepare_reset(dev, false); 3167 nvme_sync_queues(&dev->ctrl); 3168 } 3169 3170 static void nvme_reset_done(struct pci_dev *pdev) 3171 { 3172 struct nvme_dev *dev = pci_get_drvdata(pdev); 3173 3174 if (!nvme_try_sched_reset(&dev->ctrl)) 3175 flush_work(&dev->ctrl.reset_work); 3176 } 3177 3178 static void nvme_shutdown(struct pci_dev *pdev) 3179 { 3180 struct nvme_dev *dev = pci_get_drvdata(pdev); 3181 3182 nvme_disable_prepare_reset(dev, true); 3183 } 3184 3185 /* 3186 * The driver's remove may be called on a device in a partially initialized 3187 * state. This function must not have any dependencies on the device state in 3188 * order to proceed. 3189 */ 3190 static void nvme_remove(struct pci_dev *pdev) 3191 { 3192 struct nvme_dev *dev = pci_get_drvdata(pdev); 3193 3194 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3195 pci_set_drvdata(pdev, NULL); 3196 3197 if (!pci_device_is_present(pdev)) { 3198 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 3199 nvme_dev_disable(dev, true); 3200 } 3201 3202 flush_work(&dev->ctrl.reset_work); 3203 nvme_stop_ctrl(&dev->ctrl); 3204 nvme_remove_namespaces(&dev->ctrl); 3205 nvme_dev_disable(dev, true); 3206 nvme_free_host_mem(dev); 3207 nvme_dev_remove_admin(dev); 3208 nvme_dbbuf_dma_free(dev); 3209 nvme_free_queues(dev, 0); 3210 mempool_destroy(dev->iod_mempool); 3211 nvme_release_prp_pools(dev); 3212 nvme_dev_unmap(dev); 3213 nvme_uninit_ctrl(&dev->ctrl); 3214 } 3215 3216 #ifdef CONFIG_PM_SLEEP 3217 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3218 { 3219 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3220 } 3221 3222 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3223 { 3224 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3225 } 3226 3227 static int nvme_resume(struct device *dev) 3228 { 3229 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3230 struct nvme_ctrl *ctrl = &ndev->ctrl; 3231 3232 if (ndev->last_ps == U32_MAX || 3233 nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3234 goto reset; 3235 if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3236 goto reset; 3237 3238 return 0; 3239 reset: 3240 return nvme_try_sched_reset(ctrl); 3241 } 3242 3243 static int nvme_suspend(struct device *dev) 3244 { 3245 struct pci_dev *pdev = to_pci_dev(dev); 3246 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3247 struct nvme_ctrl *ctrl = &ndev->ctrl; 3248 int ret = -EBUSY; 3249 3250 ndev->last_ps = U32_MAX; 3251 3252 /* 3253 * The platform does not remove power for a kernel managed suspend so 3254 * use host managed nvme power settings for lowest idle power if 3255 * possible. This should have quicker resume latency than a full device 3256 * shutdown. But if the firmware is involved after the suspend or the 3257 * device does not support any non-default power states, shut down the 3258 * device fully. 3259 * 3260 * If ASPM is not enabled for the device, shut down the device and allow 3261 * the PCI bus layer to put it into D3 in order to take the PCIe link 3262 * down, so as to allow the platform to achieve its minimum low-power 3263 * state (which may not be possible if the link is up). 3264 */ 3265 if (pm_suspend_via_firmware() || !ctrl->npss || 3266 !pcie_aspm_enabled(pdev) || 3267 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3268 return nvme_disable_prepare_reset(ndev, true); 3269 3270 nvme_start_freeze(ctrl); 3271 nvme_wait_freeze(ctrl); 3272 nvme_sync_queues(ctrl); 3273 3274 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE) 3275 goto unfreeze; 3276 3277 /* 3278 * Host memory access may not be successful in a system suspend state, 3279 * but the specification allows the controller to access memory in a 3280 * non-operational power state. 3281 */ 3282 if (ndev->hmb) { 3283 ret = nvme_set_host_mem(ndev, 0); 3284 if (ret < 0) 3285 goto unfreeze; 3286 } 3287 3288 ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3289 if (ret < 0) 3290 goto unfreeze; 3291 3292 /* 3293 * A saved state prevents pci pm from generically controlling the 3294 * device's power. If we're using protocol specific settings, we don't 3295 * want pci interfering. 3296 */ 3297 pci_save_state(pdev); 3298 3299 ret = nvme_set_power_state(ctrl, ctrl->npss); 3300 if (ret < 0) 3301 goto unfreeze; 3302 3303 if (ret) { 3304 /* discard the saved state */ 3305 pci_load_saved_state(pdev, NULL); 3306 3307 /* 3308 * Clearing npss forces a controller reset on resume. The 3309 * correct value will be rediscovered then. 3310 */ 3311 ret = nvme_disable_prepare_reset(ndev, true); 3312 ctrl->npss = 0; 3313 } 3314 unfreeze: 3315 nvme_unfreeze(ctrl); 3316 return ret; 3317 } 3318 3319 static int nvme_simple_suspend(struct device *dev) 3320 { 3321 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3322 3323 return nvme_disable_prepare_reset(ndev, true); 3324 } 3325 3326 static int nvme_simple_resume(struct device *dev) 3327 { 3328 struct pci_dev *pdev = to_pci_dev(dev); 3329 struct nvme_dev *ndev = pci_get_drvdata(pdev); 3330 3331 return nvme_try_sched_reset(&ndev->ctrl); 3332 } 3333 3334 static const struct dev_pm_ops nvme_dev_pm_ops = { 3335 .suspend = nvme_suspend, 3336 .resume = nvme_resume, 3337 .freeze = nvme_simple_suspend, 3338 .thaw = nvme_simple_resume, 3339 .poweroff = nvme_simple_suspend, 3340 .restore = nvme_simple_resume, 3341 }; 3342 #endif /* CONFIG_PM_SLEEP */ 3343 3344 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3345 pci_channel_state_t state) 3346 { 3347 struct nvme_dev *dev = pci_get_drvdata(pdev); 3348 3349 /* 3350 * A frozen channel requires a reset. When detected, this method will 3351 * shutdown the controller to quiesce. The controller will be restarted 3352 * after the slot reset through driver's slot_reset callback. 3353 */ 3354 switch (state) { 3355 case pci_channel_io_normal: 3356 return PCI_ERS_RESULT_CAN_RECOVER; 3357 case pci_channel_io_frozen: 3358 dev_warn(dev->ctrl.device, 3359 "frozen state error detected, reset controller\n"); 3360 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { 3361 nvme_dev_disable(dev, true); 3362 return PCI_ERS_RESULT_DISCONNECT; 3363 } 3364 nvme_dev_disable(dev, false); 3365 return PCI_ERS_RESULT_NEED_RESET; 3366 case pci_channel_io_perm_failure: 3367 dev_warn(dev->ctrl.device, 3368 "failure state error detected, request disconnect\n"); 3369 return PCI_ERS_RESULT_DISCONNECT; 3370 } 3371 return PCI_ERS_RESULT_NEED_RESET; 3372 } 3373 3374 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3375 { 3376 struct nvme_dev *dev = pci_get_drvdata(pdev); 3377 3378 dev_info(dev->ctrl.device, "restart after slot reset\n"); 3379 pci_restore_state(pdev); 3380 if (!nvme_try_sched_reset(&dev->ctrl)) 3381 nvme_unquiesce_io_queues(&dev->ctrl); 3382 return PCI_ERS_RESULT_RECOVERED; 3383 } 3384 3385 static void nvme_error_resume(struct pci_dev *pdev) 3386 { 3387 struct nvme_dev *dev = pci_get_drvdata(pdev); 3388 3389 flush_work(&dev->ctrl.reset_work); 3390 } 3391 3392 static const struct pci_error_handlers nvme_err_handler = { 3393 .error_detected = nvme_error_detected, 3394 .slot_reset = nvme_slot_reset, 3395 .resume = nvme_error_resume, 3396 .reset_prepare = nvme_reset_prepare, 3397 .reset_done = nvme_reset_done, 3398 }; 3399 3400 static const struct pci_device_id nvme_id_table[] = { 3401 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 3402 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3403 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3404 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 3405 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3406 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3407 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 3408 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3409 NVME_QUIRK_DEALLOCATE_ZEROES | 3410 NVME_QUIRK_IGNORE_DEV_SUBNQN | 3411 NVME_QUIRK_BOGUS_NID, }, 3412 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3413 .driver_data = NVME_QUIRK_STRIPE_SIZE | 3414 NVME_QUIRK_DEALLOCATE_ZEROES, }, 3415 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 3416 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3417 NVME_QUIRK_MEDIUM_PRIO_SQ | 3418 NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3419 NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3420 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 3421 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3422 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 3423 .driver_data = NVME_QUIRK_IDENTIFY_CNS | 3424 NVME_QUIRK_DISABLE_WRITE_ZEROES | 3425 NVME_QUIRK_BOGUS_NID, }, 3426 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 3427 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3428 { PCI_DEVICE(0x1217, 0x8760), /* O2 Micro 64GB Steam Deck */ 3429 .driver_data = NVME_QUIRK_DMAPOOL_ALIGN_512, }, 3430 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */ 3431 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3432 NVME_QUIRK_BOGUS_NID, }, 3433 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3434 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3435 NVME_QUIRK_BOGUS_NID, }, 3436 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 3437 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3438 NVME_QUIRK_NO_NS_DESC_LIST, }, 3439 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 3440 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3441 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 3442 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3443 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3444 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3445 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3446 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3447 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3448 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3449 NVME_QUIRK_DISABLE_WRITE_ZEROES| 3450 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3451 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */ 3452 .driver_data = NVME_QUIRK_BROKEN_MSI }, 3453 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 3454 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3455 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3456 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3457 NVME_QUIRK_BOGUS_NID, }, 3458 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3459 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3460 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3461 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3462 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 3463 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3464 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3465 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3466 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3467 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 3468 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 3469 NVME_QUIRK_BOGUS_NID, }, 3470 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */ 3471 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3472 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3473 .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3474 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3475 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 3476 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3477 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3478 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3479 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 3480 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3481 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3482 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3483 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 3484 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3485 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 3486 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3487 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 3488 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES | 3489 NVME_QUIRK_BOGUS_NID, }, 3490 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 3491 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3492 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */ 3493 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3494 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 3495 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3496 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 3497 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3498 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3499 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3500 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3501 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3502 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */ 3503 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, }, 3504 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3505 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3506 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3507 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3508 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3509 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3510 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3511 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3512 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3513 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3514 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */ 3515 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3516 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */ 3517 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3518 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3519 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3520 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3521 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3522 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3523 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3524 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */ 3525 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3526 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 3527 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3528 { PCI_DEVICE(0x1dbe, 0x5216), /* Acer/INNOGRIT FA100/5216 NVMe SSD */ 3529 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3530 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3531 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3532 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3533 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3534 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 3535 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3536 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3537 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3538 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3539 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3540 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */ 3541 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3542 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 3543 .driver_data = NVME_QUIRK_BOGUS_NID | 3544 NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3545 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */ 3546 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3547 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */ 3548 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3549 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */ 3550 .driver_data = NVME_QUIRK_BOGUS_NID, }, 3551 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 3552 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3553 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 3554 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3555 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 3556 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3557 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 3558 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3559 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 3560 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3561 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 3562 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 3563 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 3564 /* 3565 * Fix for the Apple controller found in the MacBook8,1 and 3566 * some MacBook7,1 to avoid controller resets and data loss. 3567 */ 3568 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3569 NVME_QUIRK_QDEPTH_ONE }, 3570 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 3571 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 3572 .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3573 NVME_QUIRK_128_BYTES_SQES | 3574 NVME_QUIRK_SHARED_TAGS | 3575 NVME_QUIRK_SKIP_CID_GEN | 3576 NVME_QUIRK_IDENTIFY_CNS }, 3577 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3578 { 0, } 3579 }; 3580 MODULE_DEVICE_TABLE(pci, nvme_id_table); 3581 3582 static struct pci_driver nvme_driver = { 3583 .name = "nvme", 3584 .id_table = nvme_id_table, 3585 .probe = nvme_probe, 3586 .remove = nvme_remove, 3587 .shutdown = nvme_shutdown, 3588 .driver = { 3589 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3590 #ifdef CONFIG_PM_SLEEP 3591 .pm = &nvme_dev_pm_ops, 3592 #endif 3593 }, 3594 .sriov_configure = pci_sriov_configure_simple, 3595 .err_handler = &nvme_err_handler, 3596 }; 3597 3598 static int __init nvme_init(void) 3599 { 3600 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 3601 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 3602 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3603 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3604 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE); 3605 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE); 3606 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS); 3607 3608 return pci_register_driver(&nvme_driver); 3609 } 3610 3611 static void __exit nvme_exit(void) 3612 { 3613 pci_unregister_driver(&nvme_driver); 3614 flush_workqueue(nvme_wq); 3615 } 3616 3617 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 3618 MODULE_LICENSE("GPL"); 3619 MODULE_VERSION("1.0"); 3620 module_init(nvme_init); 3621 module_exit(nvme_exit); 3622