1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVM Express device driver
4 * Copyright (c) 2011-2014, Intel Corporation.
5 */
6
7 #include <linux/acpi.h>
8 #include <linux/async.h>
9 #include <linux/blkdev.h>
10 #include <linux/blk-mq.h>
11 #include <linux/blk-mq-pci.h>
12 #include <linux/blk-integrity.h>
13 #include <linux/dmi.h>
14 #include <linux/init.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/kstrtox.h>
18 #include <linux/memremap.h>
19 #include <linux/mm.h>
20 #include <linux/module.h>
21 #include <linux/mutex.h>
22 #include <linux/once.h>
23 #include <linux/pci.h>
24 #include <linux/suspend.h>
25 #include <linux/t10-pi.h>
26 #include <linux/types.h>
27 #include <linux/io-64-nonatomic-lo-hi.h>
28 #include <linux/io-64-nonatomic-hi-lo.h>
29 #include <linux/sed-opal.h>
30 #include <linux/pci-p2pdma.h>
31
32 #include "trace.h"
33 #include "nvme.h"
34
35 #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes)
36 #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion))
37
38 #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc))
39
40 /*
41 * These can be higher, but we need to ensure that any command doesn't
42 * require an sg allocation that needs more than a page of data.
43 */
44 #define NVME_MAX_KB_SZ 8192
45 #define NVME_MAX_SEGS 128
46 #define NVME_MAX_NR_ALLOCATIONS 5
47
48 static int use_threaded_interrupts;
49 module_param(use_threaded_interrupts, int, 0444);
50
51 static bool use_cmb_sqes = true;
52 module_param(use_cmb_sqes, bool, 0444);
53 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
54
55 static unsigned int max_host_mem_size_mb = 128;
56 module_param(max_host_mem_size_mb, uint, 0444);
57 MODULE_PARM_DESC(max_host_mem_size_mb,
58 "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
59
60 static unsigned int sgl_threshold = SZ_32K;
61 module_param(sgl_threshold, uint, 0644);
62 MODULE_PARM_DESC(sgl_threshold,
63 "Use SGLs when average request segment size is larger or equal to "
64 "this size. Use 0 to disable SGLs.");
65
66 #define NVME_PCI_MIN_QUEUE_SIZE 2
67 #define NVME_PCI_MAX_QUEUE_SIZE 4095
68 static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops io_queue_depth_ops = {
70 .set = io_queue_depth_set,
71 .get = param_get_uint,
72 };
73
74 static unsigned int io_queue_depth = 1024;
75 module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
76 MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096");
77
io_queue_count_set(const char * val,const struct kernel_param * kp)78 static int io_queue_count_set(const char *val, const struct kernel_param *kp)
79 {
80 unsigned int n;
81 int ret;
82
83 ret = kstrtouint(val, 10, &n);
84 if (ret != 0 || n > num_possible_cpus())
85 return -EINVAL;
86 return param_set_uint(val, kp);
87 }
88
89 static const struct kernel_param_ops io_queue_count_ops = {
90 .set = io_queue_count_set,
91 .get = param_get_uint,
92 };
93
94 static unsigned int write_queues;
95 module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
96 MODULE_PARM_DESC(write_queues,
97 "Number of queues to use for writes. If not set, reads and writes "
98 "will share a queue set.");
99
100 static unsigned int poll_queues;
101 module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
102 MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
103
104 static bool noacpi;
105 module_param(noacpi, bool, 0444);
106 MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
107
108 struct nvme_dev;
109 struct nvme_queue;
110
111 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
112 static void nvme_delete_io_queues(struct nvme_dev *dev);
113 static void nvme_update_attrs(struct nvme_dev *dev);
114
115 /*
116 * Represents an NVM Express device. Each nvme_dev is a PCI function.
117 */
118 struct nvme_dev {
119 struct nvme_queue *queues;
120 struct blk_mq_tag_set tagset;
121 struct blk_mq_tag_set admin_tagset;
122 u32 __iomem *dbs;
123 struct device *dev;
124 struct dma_pool *prp_page_pool;
125 struct dma_pool *prp_small_pool;
126 unsigned online_queues;
127 unsigned max_qid;
128 unsigned io_queues[HCTX_MAX_TYPES];
129 unsigned int num_vecs;
130 u32 q_depth;
131 int io_sqes;
132 u32 db_stride;
133 void __iomem *bar;
134 unsigned long bar_mapped_size;
135 struct mutex shutdown_lock;
136 bool subsystem;
137 u64 cmb_size;
138 bool cmb_use_sqes;
139 u32 cmbsz;
140 u32 cmbloc;
141 struct nvme_ctrl ctrl;
142 u32 last_ps;
143 bool hmb;
144
145 mempool_t *iod_mempool;
146
147 /* shadow doorbell buffer support: */
148 __le32 *dbbuf_dbs;
149 dma_addr_t dbbuf_dbs_dma_addr;
150 __le32 *dbbuf_eis;
151 dma_addr_t dbbuf_eis_dma_addr;
152
153 /* host memory buffer support: */
154 u64 host_mem_size;
155 u32 nr_host_mem_descs;
156 dma_addr_t host_mem_descs_dma;
157 struct nvme_host_mem_buf_desc *host_mem_descs;
158 void **host_mem_desc_bufs;
159 unsigned int nr_allocated_queues;
160 unsigned int nr_write_queues;
161 unsigned int nr_poll_queues;
162 };
163
io_queue_depth_set(const char * val,const struct kernel_param * kp)164 static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
165 {
166 return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE,
167 NVME_PCI_MAX_QUEUE_SIZE);
168 }
169
sq_idx(unsigned int qid,u32 stride)170 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
171 {
172 return qid * 2 * stride;
173 }
174
cq_idx(unsigned int qid,u32 stride)175 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
176 {
177 return (qid * 2 + 1) * stride;
178 }
179
to_nvme_dev(struct nvme_ctrl * ctrl)180 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
181 {
182 return container_of(ctrl, struct nvme_dev, ctrl);
183 }
184
185 /*
186 * An NVM Express queue. Each device has at least two (one for admin
187 * commands and one for I/O commands).
188 */
189 struct nvme_queue {
190 struct nvme_dev *dev;
191 spinlock_t sq_lock;
192 void *sq_cmds;
193 /* only used for poll queues: */
194 spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
195 struct nvme_completion *cqes;
196 dma_addr_t sq_dma_addr;
197 dma_addr_t cq_dma_addr;
198 u32 __iomem *q_db;
199 u32 q_depth;
200 u16 cq_vector;
201 u16 sq_tail;
202 u16 last_sq_tail;
203 u16 cq_head;
204 u16 qid;
205 u8 cq_phase;
206 u8 sqes;
207 unsigned long flags;
208 #define NVMEQ_ENABLED 0
209 #define NVMEQ_SQ_CMB 1
210 #define NVMEQ_DELETE_ERROR 2
211 #define NVMEQ_POLLED 3
212 __le32 *dbbuf_sq_db;
213 __le32 *dbbuf_cq_db;
214 __le32 *dbbuf_sq_ei;
215 __le32 *dbbuf_cq_ei;
216 struct completion delete_done;
217 };
218
219 union nvme_descriptor {
220 struct nvme_sgl_desc *sg_list;
221 __le64 *prp_list;
222 };
223
224 /*
225 * The nvme_iod describes the data in an I/O.
226 *
227 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
228 * to the actual struct scatterlist.
229 */
230 struct nvme_iod {
231 struct nvme_request req;
232 struct nvme_command cmd;
233 bool aborted;
234 s8 nr_allocations; /* PRP list pool allocations. 0 means small
235 pool in use */
236 unsigned int dma_len; /* length of single DMA segment mapping */
237 dma_addr_t first_dma;
238 dma_addr_t meta_dma;
239 struct sg_table sgt;
240 union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS];
241 };
242
nvme_dbbuf_size(struct nvme_dev * dev)243 static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
244 {
245 return dev->nr_allocated_queues * 8 * dev->db_stride;
246 }
247
nvme_dbbuf_dma_alloc(struct nvme_dev * dev)248 static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
249 {
250 unsigned int mem_size = nvme_dbbuf_size(dev);
251
252 if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP))
253 return;
254
255 if (dev->dbbuf_dbs) {
256 /*
257 * Clear the dbbuf memory so the driver doesn't observe stale
258 * values from the previous instantiation.
259 */
260 memset(dev->dbbuf_dbs, 0, mem_size);
261 memset(dev->dbbuf_eis, 0, mem_size);
262 return;
263 }
264
265 dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
266 &dev->dbbuf_dbs_dma_addr,
267 GFP_KERNEL);
268 if (!dev->dbbuf_dbs)
269 goto fail;
270 dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
271 &dev->dbbuf_eis_dma_addr,
272 GFP_KERNEL);
273 if (!dev->dbbuf_eis)
274 goto fail_free_dbbuf_dbs;
275 return;
276
277 fail_free_dbbuf_dbs:
278 dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs,
279 dev->dbbuf_dbs_dma_addr);
280 dev->dbbuf_dbs = NULL;
281 fail:
282 dev_warn(dev->dev, "unable to allocate dma for dbbuf\n");
283 }
284
nvme_dbbuf_dma_free(struct nvme_dev * dev)285 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
286 {
287 unsigned int mem_size = nvme_dbbuf_size(dev);
288
289 if (dev->dbbuf_dbs) {
290 dma_free_coherent(dev->dev, mem_size,
291 dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
292 dev->dbbuf_dbs = NULL;
293 }
294 if (dev->dbbuf_eis) {
295 dma_free_coherent(dev->dev, mem_size,
296 dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
297 dev->dbbuf_eis = NULL;
298 }
299 }
300
nvme_dbbuf_init(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)301 static void nvme_dbbuf_init(struct nvme_dev *dev,
302 struct nvme_queue *nvmeq, int qid)
303 {
304 if (!dev->dbbuf_dbs || !qid)
305 return;
306
307 nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
308 nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
309 nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
310 nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
311 }
312
nvme_dbbuf_free(struct nvme_queue * nvmeq)313 static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
314 {
315 if (!nvmeq->qid)
316 return;
317
318 nvmeq->dbbuf_sq_db = NULL;
319 nvmeq->dbbuf_cq_db = NULL;
320 nvmeq->dbbuf_sq_ei = NULL;
321 nvmeq->dbbuf_cq_ei = NULL;
322 }
323
nvme_dbbuf_set(struct nvme_dev * dev)324 static void nvme_dbbuf_set(struct nvme_dev *dev)
325 {
326 struct nvme_command c = { };
327 unsigned int i;
328
329 if (!dev->dbbuf_dbs)
330 return;
331
332 c.dbbuf.opcode = nvme_admin_dbbuf;
333 c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
334 c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
335
336 if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
337 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
338 /* Free memory and continue on */
339 nvme_dbbuf_dma_free(dev);
340
341 for (i = 1; i <= dev->online_queues; i++)
342 nvme_dbbuf_free(&dev->queues[i]);
343 }
344 }
345
nvme_dbbuf_need_event(u16 event_idx,u16 new_idx,u16 old)346 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
347 {
348 return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
349 }
350
351 /* Update dbbuf and return true if an MMIO is required */
nvme_dbbuf_update_and_check_event(u16 value,__le32 * dbbuf_db,volatile __le32 * dbbuf_ei)352 static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db,
353 volatile __le32 *dbbuf_ei)
354 {
355 if (dbbuf_db) {
356 u16 old_value, event_idx;
357
358 /*
359 * Ensure that the queue is written before updating
360 * the doorbell in memory
361 */
362 wmb();
363
364 old_value = le32_to_cpu(*dbbuf_db);
365 *dbbuf_db = cpu_to_le32(value);
366
367 /*
368 * Ensure that the doorbell is updated before reading the event
369 * index from memory. The controller needs to provide similar
370 * ordering to ensure the envent index is updated before reading
371 * the doorbell.
372 */
373 mb();
374
375 event_idx = le32_to_cpu(*dbbuf_ei);
376 if (!nvme_dbbuf_need_event(event_idx, value, old_value))
377 return false;
378 }
379
380 return true;
381 }
382
383 /*
384 * Will slightly overestimate the number of pages needed. This is OK
385 * as it only leads to a small amount of wasted memory for the lifetime of
386 * the I/O.
387 */
nvme_pci_npages_prp(void)388 static int nvme_pci_npages_prp(void)
389 {
390 unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE;
391 unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE);
392 return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8);
393 }
394
nvme_admin_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)395 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
396 unsigned int hctx_idx)
397 {
398 struct nvme_dev *dev = to_nvme_dev(data);
399 struct nvme_queue *nvmeq = &dev->queues[0];
400
401 WARN_ON(hctx_idx != 0);
402 WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
403
404 hctx->driver_data = nvmeq;
405 return 0;
406 }
407
nvme_init_hctx(struct blk_mq_hw_ctx * hctx,void * data,unsigned int hctx_idx)408 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
409 unsigned int hctx_idx)
410 {
411 struct nvme_dev *dev = to_nvme_dev(data);
412 struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
413
414 WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
415 hctx->driver_data = nvmeq;
416 return 0;
417 }
418
nvme_pci_init_request(struct blk_mq_tag_set * set,struct request * req,unsigned int hctx_idx,unsigned int numa_node)419 static int nvme_pci_init_request(struct blk_mq_tag_set *set,
420 struct request *req, unsigned int hctx_idx,
421 unsigned int numa_node)
422 {
423 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
424
425 nvme_req(req)->ctrl = set->driver_data;
426 nvme_req(req)->cmd = &iod->cmd;
427 return 0;
428 }
429
queue_irq_offset(struct nvme_dev * dev)430 static int queue_irq_offset(struct nvme_dev *dev)
431 {
432 /* if we have more than 1 vec, admin queue offsets us by 1 */
433 if (dev->num_vecs > 1)
434 return 1;
435
436 return 0;
437 }
438
nvme_pci_map_queues(struct blk_mq_tag_set * set)439 static void nvme_pci_map_queues(struct blk_mq_tag_set *set)
440 {
441 struct nvme_dev *dev = to_nvme_dev(set->driver_data);
442 int i, qoff, offset;
443
444 offset = queue_irq_offset(dev);
445 for (i = 0, qoff = 0; i < set->nr_maps; i++) {
446 struct blk_mq_queue_map *map = &set->map[i];
447
448 map->nr_queues = dev->io_queues[i];
449 if (!map->nr_queues) {
450 BUG_ON(i == HCTX_TYPE_DEFAULT);
451 continue;
452 }
453
454 /*
455 * The poll queue(s) doesn't have an IRQ (and hence IRQ
456 * affinity), so use the regular blk-mq cpu mapping
457 */
458 map->queue_offset = qoff;
459 if (i != HCTX_TYPE_POLL && offset)
460 blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
461 else
462 blk_mq_map_queues(map);
463 qoff += map->nr_queues;
464 offset += map->nr_queues;
465 }
466 }
467
468 /*
469 * Write sq tail if we are asked to, or if the next command would wrap.
470 */
nvme_write_sq_db(struct nvme_queue * nvmeq,bool write_sq)471 static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
472 {
473 if (!write_sq) {
474 u16 next_tail = nvmeq->sq_tail + 1;
475
476 if (next_tail == nvmeq->q_depth)
477 next_tail = 0;
478 if (next_tail != nvmeq->last_sq_tail)
479 return;
480 }
481
482 if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
483 nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
484 writel(nvmeq->sq_tail, nvmeq->q_db);
485 nvmeq->last_sq_tail = nvmeq->sq_tail;
486 }
487
nvme_sq_copy_cmd(struct nvme_queue * nvmeq,struct nvme_command * cmd)488 static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq,
489 struct nvme_command *cmd)
490 {
491 memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
492 absolute_pointer(cmd), sizeof(*cmd));
493 if (++nvmeq->sq_tail == nvmeq->q_depth)
494 nvmeq->sq_tail = 0;
495 }
496
nvme_commit_rqs(struct blk_mq_hw_ctx * hctx)497 static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
498 {
499 struct nvme_queue *nvmeq = hctx->driver_data;
500
501 spin_lock(&nvmeq->sq_lock);
502 if (nvmeq->sq_tail != nvmeq->last_sq_tail)
503 nvme_write_sq_db(nvmeq, true);
504 spin_unlock(&nvmeq->sq_lock);
505 }
506
nvme_pci_use_sgls(struct nvme_dev * dev,struct request * req,int nseg)507 static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req,
508 int nseg)
509 {
510 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
511 unsigned int avg_seg_size;
512
513 avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
514
515 if (!nvme_ctrl_sgl_supported(&dev->ctrl))
516 return false;
517 if (!nvmeq->qid)
518 return false;
519 if (!sgl_threshold || avg_seg_size < sgl_threshold)
520 return false;
521 return true;
522 }
523
nvme_free_prps(struct nvme_dev * dev,struct request * req)524 static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
525 {
526 const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
527 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
528 dma_addr_t dma_addr = iod->first_dma;
529 int i;
530
531 for (i = 0; i < iod->nr_allocations; i++) {
532 __le64 *prp_list = iod->list[i].prp_list;
533 dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
534
535 dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
536 dma_addr = next_dma_addr;
537 }
538 }
539
nvme_unmap_data(struct nvme_dev * dev,struct request * req)540 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
541 {
542 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
543
544 if (iod->dma_len) {
545 dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
546 rq_dma_dir(req));
547 return;
548 }
549
550 WARN_ON_ONCE(!iod->sgt.nents);
551
552 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
553
554 if (iod->nr_allocations == 0)
555 dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list,
556 iod->first_dma);
557 else if (iod->nr_allocations == 1)
558 dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list,
559 iod->first_dma);
560 else
561 nvme_free_prps(dev, req);
562 mempool_free(iod->sgt.sgl, dev->iod_mempool);
563 }
564
nvme_print_sgl(struct scatterlist * sgl,int nents)565 static void nvme_print_sgl(struct scatterlist *sgl, int nents)
566 {
567 int i;
568 struct scatterlist *sg;
569
570 for_each_sg(sgl, sg, nents, i) {
571 dma_addr_t phys = sg_phys(sg);
572 pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
573 "dma_address:%pad dma_length:%d\n",
574 i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
575 sg_dma_len(sg));
576 }
577 }
578
nvme_pci_setup_prps(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd)579 static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
580 struct request *req, struct nvme_rw_command *cmnd)
581 {
582 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
583 struct dma_pool *pool;
584 int length = blk_rq_payload_bytes(req);
585 struct scatterlist *sg = iod->sgt.sgl;
586 int dma_len = sg_dma_len(sg);
587 u64 dma_addr = sg_dma_address(sg);
588 int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
589 __le64 *prp_list;
590 dma_addr_t prp_dma;
591 int nprps, i;
592
593 length -= (NVME_CTRL_PAGE_SIZE - offset);
594 if (length <= 0) {
595 iod->first_dma = 0;
596 goto done;
597 }
598
599 dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
600 if (dma_len) {
601 dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
602 } else {
603 sg = sg_next(sg);
604 dma_addr = sg_dma_address(sg);
605 dma_len = sg_dma_len(sg);
606 }
607
608 if (length <= NVME_CTRL_PAGE_SIZE) {
609 iod->first_dma = dma_addr;
610 goto done;
611 }
612
613 nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
614 if (nprps <= (256 / 8)) {
615 pool = dev->prp_small_pool;
616 iod->nr_allocations = 0;
617 } else {
618 pool = dev->prp_page_pool;
619 iod->nr_allocations = 1;
620 }
621
622 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
623 if (!prp_list) {
624 iod->nr_allocations = -1;
625 return BLK_STS_RESOURCE;
626 }
627 iod->list[0].prp_list = prp_list;
628 iod->first_dma = prp_dma;
629 i = 0;
630 for (;;) {
631 if (i == NVME_CTRL_PAGE_SIZE >> 3) {
632 __le64 *old_prp_list = prp_list;
633 prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
634 if (!prp_list)
635 goto free_prps;
636 iod->list[iod->nr_allocations++].prp_list = prp_list;
637 prp_list[0] = old_prp_list[i - 1];
638 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
639 i = 1;
640 }
641 prp_list[i++] = cpu_to_le64(dma_addr);
642 dma_len -= NVME_CTRL_PAGE_SIZE;
643 dma_addr += NVME_CTRL_PAGE_SIZE;
644 length -= NVME_CTRL_PAGE_SIZE;
645 if (length <= 0)
646 break;
647 if (dma_len > 0)
648 continue;
649 if (unlikely(dma_len < 0))
650 goto bad_sgl;
651 sg = sg_next(sg);
652 dma_addr = sg_dma_address(sg);
653 dma_len = sg_dma_len(sg);
654 }
655 done:
656 cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl));
657 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
658 return BLK_STS_OK;
659 free_prps:
660 nvme_free_prps(dev, req);
661 return BLK_STS_RESOURCE;
662 bad_sgl:
663 WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents),
664 "Invalid SGL for payload:%d nents:%d\n",
665 blk_rq_payload_bytes(req), iod->sgt.nents);
666 return BLK_STS_IOERR;
667 }
668
nvme_pci_sgl_set_data(struct nvme_sgl_desc * sge,struct scatterlist * sg)669 static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
670 struct scatterlist *sg)
671 {
672 sge->addr = cpu_to_le64(sg_dma_address(sg));
673 sge->length = cpu_to_le32(sg_dma_len(sg));
674 sge->type = NVME_SGL_FMT_DATA_DESC << 4;
675 }
676
nvme_pci_sgl_set_seg(struct nvme_sgl_desc * sge,dma_addr_t dma_addr,int entries)677 static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
678 dma_addr_t dma_addr, int entries)
679 {
680 sge->addr = cpu_to_le64(dma_addr);
681 sge->length = cpu_to_le32(entries * sizeof(*sge));
682 sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
683 }
684
nvme_pci_setup_sgls(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmd)685 static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
686 struct request *req, struct nvme_rw_command *cmd)
687 {
688 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
689 struct dma_pool *pool;
690 struct nvme_sgl_desc *sg_list;
691 struct scatterlist *sg = iod->sgt.sgl;
692 unsigned int entries = iod->sgt.nents;
693 dma_addr_t sgl_dma;
694 int i = 0;
695
696 /* setting the transfer type as SGL */
697 cmd->flags = NVME_CMD_SGL_METABUF;
698
699 if (entries == 1) {
700 nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
701 return BLK_STS_OK;
702 }
703
704 if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
705 pool = dev->prp_small_pool;
706 iod->nr_allocations = 0;
707 } else {
708 pool = dev->prp_page_pool;
709 iod->nr_allocations = 1;
710 }
711
712 sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
713 if (!sg_list) {
714 iod->nr_allocations = -1;
715 return BLK_STS_RESOURCE;
716 }
717
718 iod->list[0].sg_list = sg_list;
719 iod->first_dma = sgl_dma;
720
721 nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
722 do {
723 nvme_pci_sgl_set_data(&sg_list[i++], sg);
724 sg = sg_next(sg);
725 } while (--entries > 0);
726
727 return BLK_STS_OK;
728 }
729
nvme_setup_prp_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)730 static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
731 struct request *req, struct nvme_rw_command *cmnd,
732 struct bio_vec *bv)
733 {
734 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
735 unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
736 unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
737
738 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
739 if (dma_mapping_error(dev->dev, iod->first_dma))
740 return BLK_STS_RESOURCE;
741 iod->dma_len = bv->bv_len;
742
743 cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
744 if (bv->bv_len > first_prp_len)
745 cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
746 else
747 cmnd->dptr.prp2 = 0;
748 return BLK_STS_OK;
749 }
750
nvme_setup_sgl_simple(struct nvme_dev * dev,struct request * req,struct nvme_rw_command * cmnd,struct bio_vec * bv)751 static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
752 struct request *req, struct nvme_rw_command *cmnd,
753 struct bio_vec *bv)
754 {
755 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
756
757 iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
758 if (dma_mapping_error(dev->dev, iod->first_dma))
759 return BLK_STS_RESOURCE;
760 iod->dma_len = bv->bv_len;
761
762 cmnd->flags = NVME_CMD_SGL_METABUF;
763 cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
764 cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
765 cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
766 return BLK_STS_OK;
767 }
768
nvme_map_data(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)769 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
770 struct nvme_command *cmnd)
771 {
772 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
773 blk_status_t ret = BLK_STS_RESOURCE;
774 int rc;
775
776 if (blk_rq_nr_phys_segments(req) == 1) {
777 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
778 struct bio_vec bv = req_bvec(req);
779
780 if (!is_pci_p2pdma_page(bv.bv_page)) {
781 if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
782 return nvme_setup_prp_simple(dev, req,
783 &cmnd->rw, &bv);
784
785 if (nvmeq->qid && sgl_threshold &&
786 nvme_ctrl_sgl_supported(&dev->ctrl))
787 return nvme_setup_sgl_simple(dev, req,
788 &cmnd->rw, &bv);
789 }
790 }
791
792 iod->dma_len = 0;
793 iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
794 if (!iod->sgt.sgl)
795 return BLK_STS_RESOURCE;
796 sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req));
797 iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl);
798 if (!iod->sgt.orig_nents)
799 goto out_free_sg;
800
801 rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req),
802 DMA_ATTR_NO_WARN);
803 if (rc) {
804 if (rc == -EREMOTEIO)
805 ret = BLK_STS_TARGET;
806 goto out_free_sg;
807 }
808
809 if (nvme_pci_use_sgls(dev, req, iod->sgt.nents))
810 ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw);
811 else
812 ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
813 if (ret != BLK_STS_OK)
814 goto out_unmap_sg;
815 return BLK_STS_OK;
816
817 out_unmap_sg:
818 dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0);
819 out_free_sg:
820 mempool_free(iod->sgt.sgl, dev->iod_mempool);
821 return ret;
822 }
823
nvme_map_metadata(struct nvme_dev * dev,struct request * req,struct nvme_command * cmnd)824 static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
825 struct nvme_command *cmnd)
826 {
827 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
828
829 iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
830 rq_dma_dir(req), 0);
831 if (dma_mapping_error(dev->dev, iod->meta_dma))
832 return BLK_STS_IOERR;
833 cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
834 return BLK_STS_OK;
835 }
836
nvme_prep_rq(struct nvme_dev * dev,struct request * req)837 static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req)
838 {
839 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
840 blk_status_t ret;
841
842 iod->aborted = false;
843 iod->nr_allocations = -1;
844 iod->sgt.nents = 0;
845
846 ret = nvme_setup_cmd(req->q->queuedata, req);
847 if (ret)
848 return ret;
849
850 if (blk_rq_nr_phys_segments(req)) {
851 ret = nvme_map_data(dev, req, &iod->cmd);
852 if (ret)
853 goto out_free_cmd;
854 }
855
856 if (blk_integrity_rq(req)) {
857 ret = nvme_map_metadata(dev, req, &iod->cmd);
858 if (ret)
859 goto out_unmap_data;
860 }
861
862 nvme_start_request(req);
863 return BLK_STS_OK;
864 out_unmap_data:
865 nvme_unmap_data(dev, req);
866 out_free_cmd:
867 nvme_cleanup_cmd(req);
868 return ret;
869 }
870
871 /*
872 * NOTE: ns is NULL when called on the admin queue.
873 */
nvme_queue_rq(struct blk_mq_hw_ctx * hctx,const struct blk_mq_queue_data * bd)874 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
875 const struct blk_mq_queue_data *bd)
876 {
877 struct nvme_queue *nvmeq = hctx->driver_data;
878 struct nvme_dev *dev = nvmeq->dev;
879 struct request *req = bd->rq;
880 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
881 blk_status_t ret;
882
883 /*
884 * We should not need to do this, but we're still using this to
885 * ensure we can drain requests on a dying queue.
886 */
887 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
888 return BLK_STS_IOERR;
889
890 if (unlikely(!nvme_check_ready(&dev->ctrl, req, true)))
891 return nvme_fail_nonready_command(&dev->ctrl, req);
892
893 ret = nvme_prep_rq(dev, req);
894 if (unlikely(ret))
895 return ret;
896 spin_lock(&nvmeq->sq_lock);
897 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
898 nvme_write_sq_db(nvmeq, bd->last);
899 spin_unlock(&nvmeq->sq_lock);
900 return BLK_STS_OK;
901 }
902
nvme_submit_cmds(struct nvme_queue * nvmeq,struct request ** rqlist)903 static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist)
904 {
905 spin_lock(&nvmeq->sq_lock);
906 while (!rq_list_empty(*rqlist)) {
907 struct request *req = rq_list_pop(rqlist);
908 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
909
910 nvme_sq_copy_cmd(nvmeq, &iod->cmd);
911 }
912 nvme_write_sq_db(nvmeq, true);
913 spin_unlock(&nvmeq->sq_lock);
914 }
915
nvme_prep_rq_batch(struct nvme_queue * nvmeq,struct request * req)916 static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req)
917 {
918 /*
919 * We should not need to do this, but we're still using this to
920 * ensure we can drain requests on a dying queue.
921 */
922 if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
923 return false;
924 if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true)))
925 return false;
926
927 req->mq_hctx->tags->rqs[req->tag] = req;
928 return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK;
929 }
930
nvme_queue_rqs(struct request ** rqlist)931 static void nvme_queue_rqs(struct request **rqlist)
932 {
933 struct request *req, *next, *prev = NULL;
934 struct request *requeue_list = NULL;
935
936 rq_list_for_each_safe(rqlist, req, next) {
937 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
938
939 if (!nvme_prep_rq_batch(nvmeq, req)) {
940 /* detach 'req' and add to remainder list */
941 rq_list_move(rqlist, &requeue_list, req, prev);
942
943 req = prev;
944 if (!req)
945 continue;
946 }
947
948 if (!next || req->mq_hctx != next->mq_hctx) {
949 /* detach rest of list, and submit */
950 req->rq_next = NULL;
951 nvme_submit_cmds(nvmeq, rqlist);
952 *rqlist = next;
953 prev = NULL;
954 } else
955 prev = req;
956 }
957
958 *rqlist = requeue_list;
959 }
960
nvme_pci_unmap_rq(struct request * req)961 static __always_inline void nvme_pci_unmap_rq(struct request *req)
962 {
963 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
964 struct nvme_dev *dev = nvmeq->dev;
965
966 if (blk_integrity_rq(req)) {
967 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
968
969 dma_unmap_page(dev->dev, iod->meta_dma,
970 rq_integrity_vec(req)->bv_len, rq_dma_dir(req));
971 }
972
973 if (blk_rq_nr_phys_segments(req))
974 nvme_unmap_data(dev, req);
975 }
976
nvme_pci_complete_rq(struct request * req)977 static void nvme_pci_complete_rq(struct request *req)
978 {
979 nvme_pci_unmap_rq(req);
980 nvme_complete_rq(req);
981 }
982
nvme_pci_complete_batch(struct io_comp_batch * iob)983 static void nvme_pci_complete_batch(struct io_comp_batch *iob)
984 {
985 nvme_complete_batch(iob, nvme_pci_unmap_rq);
986 }
987
988 /* We read the CQE phase first to check if the rest of the entry is valid */
nvme_cqe_pending(struct nvme_queue * nvmeq)989 static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
990 {
991 struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
992
993 return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
994 }
995
nvme_ring_cq_doorbell(struct nvme_queue * nvmeq)996 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
997 {
998 u16 head = nvmeq->cq_head;
999
1000 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
1001 nvmeq->dbbuf_cq_ei))
1002 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
1003 }
1004
nvme_queue_tagset(struct nvme_queue * nvmeq)1005 static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
1006 {
1007 if (!nvmeq->qid)
1008 return nvmeq->dev->admin_tagset.tags[0];
1009 return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
1010 }
1011
nvme_handle_cqe(struct nvme_queue * nvmeq,struct io_comp_batch * iob,u16 idx)1012 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
1013 struct io_comp_batch *iob, u16 idx)
1014 {
1015 struct nvme_completion *cqe = &nvmeq->cqes[idx];
1016 __u16 command_id = READ_ONCE(cqe->command_id);
1017 struct request *req;
1018
1019 /*
1020 * AEN requests are special as they don't time out and can
1021 * survive any kind of queue freeze and often don't respond to
1022 * aborts. We don't even bother to allocate a struct request
1023 * for them but rather special case them here.
1024 */
1025 if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1026 nvme_complete_async_event(&nvmeq->dev->ctrl,
1027 cqe->status, &cqe->result);
1028 return;
1029 }
1030
1031 req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id);
1032 if (unlikely(!req)) {
1033 dev_warn(nvmeq->dev->ctrl.device,
1034 "invalid id %d completed on queue %d\n",
1035 command_id, le16_to_cpu(cqe->sq_id));
1036 return;
1037 }
1038
1039 trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1040 if (!nvme_try_complete_req(req, cqe->status, cqe->result) &&
1041 !blk_mq_add_to_batch(req, iob, nvme_req(req)->status,
1042 nvme_pci_complete_batch))
1043 nvme_pci_complete_rq(req);
1044 }
1045
nvme_update_cq_head(struct nvme_queue * nvmeq)1046 static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1047 {
1048 u32 tmp = nvmeq->cq_head + 1;
1049
1050 if (tmp == nvmeq->q_depth) {
1051 nvmeq->cq_head = 0;
1052 nvmeq->cq_phase ^= 1;
1053 } else {
1054 nvmeq->cq_head = tmp;
1055 }
1056 }
1057
nvme_poll_cq(struct nvme_queue * nvmeq,struct io_comp_batch * iob)1058 static inline int nvme_poll_cq(struct nvme_queue *nvmeq,
1059 struct io_comp_batch *iob)
1060 {
1061 int found = 0;
1062
1063 while (nvme_cqe_pending(nvmeq)) {
1064 found++;
1065 /*
1066 * load-load control dependency between phase and the rest of
1067 * the cqe requires a full read memory barrier
1068 */
1069 dma_rmb();
1070 nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head);
1071 nvme_update_cq_head(nvmeq);
1072 }
1073
1074 if (found)
1075 nvme_ring_cq_doorbell(nvmeq);
1076 return found;
1077 }
1078
nvme_irq(int irq,void * data)1079 static irqreturn_t nvme_irq(int irq, void *data)
1080 {
1081 struct nvme_queue *nvmeq = data;
1082 DEFINE_IO_COMP_BATCH(iob);
1083
1084 if (nvme_poll_cq(nvmeq, &iob)) {
1085 if (!rq_list_empty(iob.req_list))
1086 nvme_pci_complete_batch(&iob);
1087 return IRQ_HANDLED;
1088 }
1089 return IRQ_NONE;
1090 }
1091
nvme_irq_check(int irq,void * data)1092 static irqreturn_t nvme_irq_check(int irq, void *data)
1093 {
1094 struct nvme_queue *nvmeq = data;
1095
1096 if (nvme_cqe_pending(nvmeq))
1097 return IRQ_WAKE_THREAD;
1098 return IRQ_NONE;
1099 }
1100
1101 /*
1102 * Poll for completions for any interrupt driven queue
1103 * Can be called from any context.
1104 */
nvme_poll_irqdisable(struct nvme_queue * nvmeq)1105 static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1106 {
1107 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1108
1109 WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1110
1111 disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1112 nvme_poll_cq(nvmeq, NULL);
1113 enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1114 }
1115
nvme_poll(struct blk_mq_hw_ctx * hctx,struct io_comp_batch * iob)1116 static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob)
1117 {
1118 struct nvme_queue *nvmeq = hctx->driver_data;
1119 bool found;
1120
1121 if (!nvme_cqe_pending(nvmeq))
1122 return 0;
1123
1124 spin_lock(&nvmeq->cq_poll_lock);
1125 found = nvme_poll_cq(nvmeq, iob);
1126 spin_unlock(&nvmeq->cq_poll_lock);
1127
1128 return found;
1129 }
1130
nvme_pci_submit_async_event(struct nvme_ctrl * ctrl)1131 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1132 {
1133 struct nvme_dev *dev = to_nvme_dev(ctrl);
1134 struct nvme_queue *nvmeq = &dev->queues[0];
1135 struct nvme_command c = { };
1136
1137 c.common.opcode = nvme_admin_async_event;
1138 c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1139
1140 spin_lock(&nvmeq->sq_lock);
1141 nvme_sq_copy_cmd(nvmeq, &c);
1142 nvme_write_sq_db(nvmeq, true);
1143 spin_unlock(&nvmeq->sq_lock);
1144 }
1145
adapter_delete_queue(struct nvme_dev * dev,u8 opcode,u16 id)1146 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1147 {
1148 struct nvme_command c = { };
1149
1150 c.delete_queue.opcode = opcode;
1151 c.delete_queue.qid = cpu_to_le16(id);
1152
1153 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1154 }
1155
adapter_alloc_cq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq,s16 vector)1156 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1157 struct nvme_queue *nvmeq, s16 vector)
1158 {
1159 struct nvme_command c = { };
1160 int flags = NVME_QUEUE_PHYS_CONTIG;
1161
1162 if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1163 flags |= NVME_CQ_IRQ_ENABLED;
1164
1165 /*
1166 * Note: we (ab)use the fact that the prp fields survive if no data
1167 * is attached to the request.
1168 */
1169 c.create_cq.opcode = nvme_admin_create_cq;
1170 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1171 c.create_cq.cqid = cpu_to_le16(qid);
1172 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1173 c.create_cq.cq_flags = cpu_to_le16(flags);
1174 c.create_cq.irq_vector = cpu_to_le16(vector);
1175
1176 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1177 }
1178
adapter_alloc_sq(struct nvme_dev * dev,u16 qid,struct nvme_queue * nvmeq)1179 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1180 struct nvme_queue *nvmeq)
1181 {
1182 struct nvme_ctrl *ctrl = &dev->ctrl;
1183 struct nvme_command c = { };
1184 int flags = NVME_QUEUE_PHYS_CONTIG;
1185
1186 /*
1187 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1188 * set. Since URGENT priority is zeroes, it makes all queues
1189 * URGENT.
1190 */
1191 if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1192 flags |= NVME_SQ_PRIO_MEDIUM;
1193
1194 /*
1195 * Note: we (ab)use the fact that the prp fields survive if no data
1196 * is attached to the request.
1197 */
1198 c.create_sq.opcode = nvme_admin_create_sq;
1199 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1200 c.create_sq.sqid = cpu_to_le16(qid);
1201 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1202 c.create_sq.sq_flags = cpu_to_le16(flags);
1203 c.create_sq.cqid = cpu_to_le16(qid);
1204
1205 return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1206 }
1207
adapter_delete_cq(struct nvme_dev * dev,u16 cqid)1208 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1209 {
1210 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1211 }
1212
adapter_delete_sq(struct nvme_dev * dev,u16 sqid)1213 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1214 {
1215 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1216 }
1217
abort_endio(struct request * req,blk_status_t error)1218 static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error)
1219 {
1220 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1221
1222 dev_warn(nvmeq->dev->ctrl.device,
1223 "Abort status: 0x%x", nvme_req(req)->status);
1224 atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1225 blk_mq_free_request(req);
1226 return RQ_END_IO_NONE;
1227 }
1228
nvme_should_reset(struct nvme_dev * dev,u32 csts)1229 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1230 {
1231 /* If true, indicates loss of adapter communication, possibly by a
1232 * NVMe Subsystem reset.
1233 */
1234 bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1235
1236 /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1237 switch (nvme_ctrl_state(&dev->ctrl)) {
1238 case NVME_CTRL_RESETTING:
1239 case NVME_CTRL_CONNECTING:
1240 return false;
1241 default:
1242 break;
1243 }
1244
1245 /* We shouldn't reset unless the controller is on fatal error state
1246 * _or_ if we lost the communication with it.
1247 */
1248 if (!(csts & NVME_CSTS_CFS) && !nssro)
1249 return false;
1250
1251 return true;
1252 }
1253
nvme_warn_reset(struct nvme_dev * dev,u32 csts)1254 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1255 {
1256 /* Read a config register to help see what died. */
1257 u16 pci_status;
1258 int result;
1259
1260 result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1261 &pci_status);
1262 if (result == PCIBIOS_SUCCESSFUL)
1263 dev_warn(dev->ctrl.device,
1264 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1265 csts, pci_status);
1266 else
1267 dev_warn(dev->ctrl.device,
1268 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1269 csts, result);
1270
1271 if (csts != ~0)
1272 return;
1273
1274 dev_warn(dev->ctrl.device,
1275 "Does your device have a faulty power saving mode enabled?\n");
1276 dev_warn(dev->ctrl.device,
1277 "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n");
1278 }
1279
nvme_timeout(struct request * req)1280 static enum blk_eh_timer_return nvme_timeout(struct request *req)
1281 {
1282 struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1283 struct nvme_queue *nvmeq = req->mq_hctx->driver_data;
1284 struct nvme_dev *dev = nvmeq->dev;
1285 struct request *abort_req;
1286 struct nvme_command cmd = { };
1287 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1288
1289 if (nvme_state_terminal(&dev->ctrl))
1290 goto disable;
1291
1292 /* If PCI error recovery process is happening, we cannot reset or
1293 * the recovery mechanism will surely fail.
1294 */
1295 mb();
1296 if (pci_channel_offline(to_pci_dev(dev->dev)))
1297 return BLK_EH_RESET_TIMER;
1298
1299 /*
1300 * Reset immediately if the controller is failed
1301 */
1302 if (nvme_should_reset(dev, csts)) {
1303 nvme_warn_reset(dev, csts);
1304 goto disable;
1305 }
1306
1307 /*
1308 * Did we miss an interrupt?
1309 */
1310 if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1311 nvme_poll(req->mq_hctx, NULL);
1312 else
1313 nvme_poll_irqdisable(nvmeq);
1314
1315 if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) {
1316 dev_warn(dev->ctrl.device,
1317 "I/O %d QID %d timeout, completion polled\n",
1318 req->tag, nvmeq->qid);
1319 return BLK_EH_DONE;
1320 }
1321
1322 /*
1323 * Shutdown immediately if controller times out while starting. The
1324 * reset work will see the pci device disabled when it gets the forced
1325 * cancellation error. All outstanding requests are completed on
1326 * shutdown, so we return BLK_EH_DONE.
1327 */
1328 switch (nvme_ctrl_state(&dev->ctrl)) {
1329 case NVME_CTRL_CONNECTING:
1330 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1331 fallthrough;
1332 case NVME_CTRL_DELETING:
1333 dev_warn_ratelimited(dev->ctrl.device,
1334 "I/O %d QID %d timeout, disable controller\n",
1335 req->tag, nvmeq->qid);
1336 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1337 nvme_dev_disable(dev, true);
1338 return BLK_EH_DONE;
1339 case NVME_CTRL_RESETTING:
1340 return BLK_EH_RESET_TIMER;
1341 default:
1342 break;
1343 }
1344
1345 /*
1346 * Shutdown the controller immediately and schedule a reset if the
1347 * command was already aborted once before and still hasn't been
1348 * returned to the driver, or if this is the admin queue.
1349 */
1350 if (!nvmeq->qid || iod->aborted) {
1351 dev_warn(dev->ctrl.device,
1352 "I/O %d QID %d timeout, reset controller\n",
1353 req->tag, nvmeq->qid);
1354 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1355 goto disable;
1356 }
1357
1358 if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1359 atomic_inc(&dev->ctrl.abort_limit);
1360 return BLK_EH_RESET_TIMER;
1361 }
1362 iod->aborted = true;
1363
1364 cmd.abort.opcode = nvme_admin_abort_cmd;
1365 cmd.abort.cid = nvme_cid(req);
1366 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1367
1368 dev_warn(nvmeq->dev->ctrl.device,
1369 "I/O %d (%s) QID %d timeout, aborting\n",
1370 req->tag,
1371 nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode),
1372 nvmeq->qid);
1373
1374 abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd),
1375 BLK_MQ_REQ_NOWAIT);
1376 if (IS_ERR(abort_req)) {
1377 atomic_inc(&dev->ctrl.abort_limit);
1378 return BLK_EH_RESET_TIMER;
1379 }
1380 nvme_init_request(abort_req, &cmd);
1381
1382 abort_req->end_io = abort_endio;
1383 abort_req->end_io_data = NULL;
1384 blk_execute_rq_nowait(abort_req, false);
1385
1386 /*
1387 * The aborted req will be completed on receiving the abort req.
1388 * We enable the timer again. If hit twice, it'll cause a device reset,
1389 * as the device then is in a faulty state.
1390 */
1391 return BLK_EH_RESET_TIMER;
1392
1393 disable:
1394 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
1395 if (nvme_state_terminal(&dev->ctrl))
1396 nvme_dev_disable(dev, true);
1397 return BLK_EH_DONE;
1398 }
1399
1400 nvme_dev_disable(dev, false);
1401 if (nvme_try_sched_reset(&dev->ctrl))
1402 nvme_unquiesce_io_queues(&dev->ctrl);
1403 return BLK_EH_DONE;
1404 }
1405
nvme_free_queue(struct nvme_queue * nvmeq)1406 static void nvme_free_queue(struct nvme_queue *nvmeq)
1407 {
1408 dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1409 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1410 if (!nvmeq->sq_cmds)
1411 return;
1412
1413 if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1414 pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1415 nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1416 } else {
1417 dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1418 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1419 }
1420 }
1421
nvme_free_queues(struct nvme_dev * dev,int lowest)1422 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1423 {
1424 int i;
1425
1426 for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1427 dev->ctrl.queue_count--;
1428 nvme_free_queue(&dev->queues[i]);
1429 }
1430 }
1431
nvme_suspend_queue(struct nvme_dev * dev,unsigned int qid)1432 static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid)
1433 {
1434 struct nvme_queue *nvmeq = &dev->queues[qid];
1435
1436 if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1437 return;
1438
1439 /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1440 mb();
1441
1442 nvmeq->dev->online_queues--;
1443 if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1444 nvme_quiesce_admin_queue(&nvmeq->dev->ctrl);
1445 if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1446 pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq);
1447 }
1448
nvme_suspend_io_queues(struct nvme_dev * dev)1449 static void nvme_suspend_io_queues(struct nvme_dev *dev)
1450 {
1451 int i;
1452
1453 for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1454 nvme_suspend_queue(dev, i);
1455 }
1456
1457 /*
1458 * Called only on a device that has been disabled and after all other threads
1459 * that can check this device's completion queues have synced, except
1460 * nvme_poll(). This is the last chance for the driver to see a natural
1461 * completion before nvme_cancel_request() terminates all incomplete requests.
1462 */
nvme_reap_pending_cqes(struct nvme_dev * dev)1463 static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1464 {
1465 int i;
1466
1467 for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1468 spin_lock(&dev->queues[i].cq_poll_lock);
1469 nvme_poll_cq(&dev->queues[i], NULL);
1470 spin_unlock(&dev->queues[i].cq_poll_lock);
1471 }
1472 }
1473
nvme_cmb_qdepth(struct nvme_dev * dev,int nr_io_queues,int entry_size)1474 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1475 int entry_size)
1476 {
1477 int q_depth = dev->q_depth;
1478 unsigned q_size_aligned = roundup(q_depth * entry_size,
1479 NVME_CTRL_PAGE_SIZE);
1480
1481 if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1482 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1483
1484 mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1485 q_depth = div_u64(mem_per_q, entry_size);
1486
1487 /*
1488 * Ensure the reduced q_depth is above some threshold where it
1489 * would be better to map queues in system memory with the
1490 * original depth
1491 */
1492 if (q_depth < 64)
1493 return -ENOMEM;
1494 }
1495
1496 return q_depth;
1497 }
1498
nvme_alloc_sq_cmds(struct nvme_dev * dev,struct nvme_queue * nvmeq,int qid)1499 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1500 int qid)
1501 {
1502 struct pci_dev *pdev = to_pci_dev(dev->dev);
1503
1504 if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1505 nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1506 if (nvmeq->sq_cmds) {
1507 nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1508 nvmeq->sq_cmds);
1509 if (nvmeq->sq_dma_addr) {
1510 set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1511 return 0;
1512 }
1513
1514 pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1515 }
1516 }
1517
1518 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1519 &nvmeq->sq_dma_addr, GFP_KERNEL);
1520 if (!nvmeq->sq_cmds)
1521 return -ENOMEM;
1522 return 0;
1523 }
1524
nvme_alloc_queue(struct nvme_dev * dev,int qid,int depth)1525 static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1526 {
1527 struct nvme_queue *nvmeq = &dev->queues[qid];
1528
1529 if (dev->ctrl.queue_count > qid)
1530 return 0;
1531
1532 nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1533 nvmeq->q_depth = depth;
1534 nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1535 &nvmeq->cq_dma_addr, GFP_KERNEL);
1536 if (!nvmeq->cqes)
1537 goto free_nvmeq;
1538
1539 if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1540 goto free_cqdma;
1541
1542 nvmeq->dev = dev;
1543 spin_lock_init(&nvmeq->sq_lock);
1544 spin_lock_init(&nvmeq->cq_poll_lock);
1545 nvmeq->cq_head = 0;
1546 nvmeq->cq_phase = 1;
1547 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1548 nvmeq->qid = qid;
1549 dev->ctrl.queue_count++;
1550
1551 return 0;
1552
1553 free_cqdma:
1554 dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1555 nvmeq->cq_dma_addr);
1556 free_nvmeq:
1557 return -ENOMEM;
1558 }
1559
queue_request_irq(struct nvme_queue * nvmeq)1560 static int queue_request_irq(struct nvme_queue *nvmeq)
1561 {
1562 struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1563 int nr = nvmeq->dev->ctrl.instance;
1564
1565 if (use_threaded_interrupts) {
1566 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1567 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1568 } else {
1569 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1570 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1571 }
1572 }
1573
nvme_init_queue(struct nvme_queue * nvmeq,u16 qid)1574 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1575 {
1576 struct nvme_dev *dev = nvmeq->dev;
1577
1578 nvmeq->sq_tail = 0;
1579 nvmeq->last_sq_tail = 0;
1580 nvmeq->cq_head = 0;
1581 nvmeq->cq_phase = 1;
1582 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1583 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1584 nvme_dbbuf_init(dev, nvmeq, qid);
1585 dev->online_queues++;
1586 wmb(); /* ensure the first interrupt sees the initialization */
1587 }
1588
1589 /*
1590 * Try getting shutdown_lock while setting up IO queues.
1591 */
nvme_setup_io_queues_trylock(struct nvme_dev * dev)1592 static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1593 {
1594 /*
1595 * Give up if the lock is being held by nvme_dev_disable.
1596 */
1597 if (!mutex_trylock(&dev->shutdown_lock))
1598 return -ENODEV;
1599
1600 /*
1601 * Controller is in wrong state, fail early.
1602 */
1603 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_CONNECTING) {
1604 mutex_unlock(&dev->shutdown_lock);
1605 return -ENODEV;
1606 }
1607
1608 return 0;
1609 }
1610
nvme_create_queue(struct nvme_queue * nvmeq,int qid,bool polled)1611 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1612 {
1613 struct nvme_dev *dev = nvmeq->dev;
1614 int result;
1615 u16 vector = 0;
1616
1617 clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1618
1619 /*
1620 * A queue's vector matches the queue identifier unless the controller
1621 * has only one vector available.
1622 */
1623 if (!polled)
1624 vector = dev->num_vecs == 1 ? 0 : qid;
1625 else
1626 set_bit(NVMEQ_POLLED, &nvmeq->flags);
1627
1628 result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1629 if (result)
1630 return result;
1631
1632 result = adapter_alloc_sq(dev, qid, nvmeq);
1633 if (result < 0)
1634 return result;
1635 if (result)
1636 goto release_cq;
1637
1638 nvmeq->cq_vector = vector;
1639
1640 result = nvme_setup_io_queues_trylock(dev);
1641 if (result)
1642 return result;
1643 nvme_init_queue(nvmeq, qid);
1644 if (!polled) {
1645 result = queue_request_irq(nvmeq);
1646 if (result < 0)
1647 goto release_sq;
1648 }
1649
1650 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1651 mutex_unlock(&dev->shutdown_lock);
1652 return result;
1653
1654 release_sq:
1655 dev->online_queues--;
1656 mutex_unlock(&dev->shutdown_lock);
1657 adapter_delete_sq(dev, qid);
1658 release_cq:
1659 adapter_delete_cq(dev, qid);
1660 return result;
1661 }
1662
1663 static const struct blk_mq_ops nvme_mq_admin_ops = {
1664 .queue_rq = nvme_queue_rq,
1665 .complete = nvme_pci_complete_rq,
1666 .init_hctx = nvme_admin_init_hctx,
1667 .init_request = nvme_pci_init_request,
1668 .timeout = nvme_timeout,
1669 };
1670
1671 static const struct blk_mq_ops nvme_mq_ops = {
1672 .queue_rq = nvme_queue_rq,
1673 .queue_rqs = nvme_queue_rqs,
1674 .complete = nvme_pci_complete_rq,
1675 .commit_rqs = nvme_commit_rqs,
1676 .init_hctx = nvme_init_hctx,
1677 .init_request = nvme_pci_init_request,
1678 .map_queues = nvme_pci_map_queues,
1679 .timeout = nvme_timeout,
1680 .poll = nvme_poll,
1681 };
1682
nvme_dev_remove_admin(struct nvme_dev * dev)1683 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1684 {
1685 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1686 /*
1687 * If the controller was reset during removal, it's possible
1688 * user requests may be waiting on a stopped queue. Start the
1689 * queue to flush these to completion.
1690 */
1691 nvme_unquiesce_admin_queue(&dev->ctrl);
1692 nvme_remove_admin_tag_set(&dev->ctrl);
1693 }
1694 }
1695
db_bar_size(struct nvme_dev * dev,unsigned nr_io_queues)1696 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1697 {
1698 return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1699 }
1700
nvme_remap_bar(struct nvme_dev * dev,unsigned long size)1701 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1702 {
1703 struct pci_dev *pdev = to_pci_dev(dev->dev);
1704
1705 if (size <= dev->bar_mapped_size)
1706 return 0;
1707 if (size > pci_resource_len(pdev, 0))
1708 return -ENOMEM;
1709 if (dev->bar)
1710 iounmap(dev->bar);
1711 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1712 if (!dev->bar) {
1713 dev->bar_mapped_size = 0;
1714 return -ENOMEM;
1715 }
1716 dev->bar_mapped_size = size;
1717 dev->dbs = dev->bar + NVME_REG_DBS;
1718
1719 return 0;
1720 }
1721
nvme_pci_configure_admin_queue(struct nvme_dev * dev)1722 static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1723 {
1724 int result;
1725 u32 aqa;
1726 struct nvme_queue *nvmeq;
1727
1728 result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1729 if (result < 0)
1730 return result;
1731
1732 dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1733 NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1734
1735 if (dev->subsystem &&
1736 (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1737 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1738
1739 /*
1740 * If the device has been passed off to us in an enabled state, just
1741 * clear the enabled bit. The spec says we should set the 'shutdown
1742 * notification bits', but doing so may cause the device to complete
1743 * commands to the admin queue ... and we don't know what memory that
1744 * might be pointing at!
1745 */
1746 result = nvme_disable_ctrl(&dev->ctrl, false);
1747 if (result < 0)
1748 return result;
1749
1750 result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1751 if (result)
1752 return result;
1753
1754 dev->ctrl.numa_node = dev_to_node(dev->dev);
1755
1756 nvmeq = &dev->queues[0];
1757 aqa = nvmeq->q_depth - 1;
1758 aqa |= aqa << 16;
1759
1760 writel(aqa, dev->bar + NVME_REG_AQA);
1761 lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1762 lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1763
1764 result = nvme_enable_ctrl(&dev->ctrl);
1765 if (result)
1766 return result;
1767
1768 nvmeq->cq_vector = 0;
1769 nvme_init_queue(nvmeq, 0);
1770 result = queue_request_irq(nvmeq);
1771 if (result) {
1772 dev->online_queues--;
1773 return result;
1774 }
1775
1776 set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1777 return result;
1778 }
1779
nvme_create_io_queues(struct nvme_dev * dev)1780 static int nvme_create_io_queues(struct nvme_dev *dev)
1781 {
1782 unsigned i, max, rw_queues;
1783 int ret = 0;
1784
1785 for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1786 if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1787 ret = -ENOMEM;
1788 break;
1789 }
1790 }
1791
1792 max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1793 if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1794 rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1795 dev->io_queues[HCTX_TYPE_READ];
1796 } else {
1797 rw_queues = max;
1798 }
1799
1800 for (i = dev->online_queues; i <= max; i++) {
1801 bool polled = i > rw_queues;
1802
1803 ret = nvme_create_queue(&dev->queues[i], i, polled);
1804 if (ret)
1805 break;
1806 }
1807
1808 /*
1809 * Ignore failing Create SQ/CQ commands, we can continue with less
1810 * than the desired amount of queues, and even a controller without
1811 * I/O queues can still be used to issue admin commands. This might
1812 * be useful to upgrade a buggy firmware for example.
1813 */
1814 return ret >= 0 ? 0 : ret;
1815 }
1816
nvme_cmb_size_unit(struct nvme_dev * dev)1817 static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1818 {
1819 u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1820
1821 return 1ULL << (12 + 4 * szu);
1822 }
1823
nvme_cmb_size(struct nvme_dev * dev)1824 static u32 nvme_cmb_size(struct nvme_dev *dev)
1825 {
1826 return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1827 }
1828
nvme_map_cmb(struct nvme_dev * dev)1829 static void nvme_map_cmb(struct nvme_dev *dev)
1830 {
1831 u64 size, offset;
1832 resource_size_t bar_size;
1833 struct pci_dev *pdev = to_pci_dev(dev->dev);
1834 int bar;
1835
1836 if (dev->cmb_size)
1837 return;
1838
1839 if (NVME_CAP_CMBS(dev->ctrl.cap))
1840 writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1841
1842 dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1843 if (!dev->cmbsz)
1844 return;
1845 dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1846
1847 size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1848 offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1849 bar = NVME_CMB_BIR(dev->cmbloc);
1850 bar_size = pci_resource_len(pdev, bar);
1851
1852 if (offset > bar_size)
1853 return;
1854
1855 /*
1856 * Tell the controller about the host side address mapping the CMB,
1857 * and enable CMB decoding for the NVMe 1.4+ scheme:
1858 */
1859 if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1860 hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1861 (pci_bus_address(pdev, bar) + offset),
1862 dev->bar + NVME_REG_CMBMSC);
1863 }
1864
1865 /*
1866 * Controllers may support a CMB size larger than their BAR,
1867 * for example, due to being behind a bridge. Reduce the CMB to
1868 * the reported size of the BAR
1869 */
1870 if (size > bar_size - offset)
1871 size = bar_size - offset;
1872
1873 if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1874 dev_warn(dev->ctrl.device,
1875 "failed to register the CMB\n");
1876 return;
1877 }
1878
1879 dev->cmb_size = size;
1880 dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1881
1882 if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1883 (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1884 pci_p2pmem_publish(pdev, true);
1885
1886 nvme_update_attrs(dev);
1887 }
1888
nvme_set_host_mem(struct nvme_dev * dev,u32 bits)1889 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1890 {
1891 u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1892 u64 dma_addr = dev->host_mem_descs_dma;
1893 struct nvme_command c = { };
1894 int ret;
1895
1896 c.features.opcode = nvme_admin_set_features;
1897 c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1898 c.features.dword11 = cpu_to_le32(bits);
1899 c.features.dword12 = cpu_to_le32(host_mem_size);
1900 c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr));
1901 c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr));
1902 c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs);
1903
1904 ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1905 if (ret) {
1906 dev_warn(dev->ctrl.device,
1907 "failed to set host mem (err %d, flags %#x).\n",
1908 ret, bits);
1909 } else
1910 dev->hmb = bits & NVME_HOST_MEM_ENABLE;
1911
1912 return ret;
1913 }
1914
nvme_free_host_mem(struct nvme_dev * dev)1915 static void nvme_free_host_mem(struct nvme_dev *dev)
1916 {
1917 int i;
1918
1919 for (i = 0; i < dev->nr_host_mem_descs; i++) {
1920 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1921 size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1922
1923 dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1924 le64_to_cpu(desc->addr),
1925 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1926 }
1927
1928 kfree(dev->host_mem_desc_bufs);
1929 dev->host_mem_desc_bufs = NULL;
1930 dma_free_coherent(dev->dev,
1931 dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1932 dev->host_mem_descs, dev->host_mem_descs_dma);
1933 dev->host_mem_descs = NULL;
1934 dev->nr_host_mem_descs = 0;
1935 }
1936
__nvme_alloc_host_mem(struct nvme_dev * dev,u64 preferred,u32 chunk_size)1937 static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1938 u32 chunk_size)
1939 {
1940 struct nvme_host_mem_buf_desc *descs;
1941 u32 max_entries, len;
1942 dma_addr_t descs_dma;
1943 int i = 0;
1944 void **bufs;
1945 u64 size, tmp;
1946
1947 tmp = (preferred + chunk_size - 1);
1948 do_div(tmp, chunk_size);
1949 max_entries = tmp;
1950
1951 if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1952 max_entries = dev->ctrl.hmmaxd;
1953
1954 descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1955 &descs_dma, GFP_KERNEL);
1956 if (!descs)
1957 goto out;
1958
1959 bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1960 if (!bufs)
1961 goto out_free_descs;
1962
1963 for (size = 0; size < preferred && i < max_entries; size += len) {
1964 dma_addr_t dma_addr;
1965
1966 len = min_t(u64, chunk_size, preferred - size);
1967 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1968 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1969 if (!bufs[i])
1970 break;
1971
1972 descs[i].addr = cpu_to_le64(dma_addr);
1973 descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1974 i++;
1975 }
1976
1977 if (!size)
1978 goto out_free_bufs;
1979
1980 dev->nr_host_mem_descs = i;
1981 dev->host_mem_size = size;
1982 dev->host_mem_descs = descs;
1983 dev->host_mem_descs_dma = descs_dma;
1984 dev->host_mem_desc_bufs = bufs;
1985 return 0;
1986
1987 out_free_bufs:
1988 while (--i >= 0) {
1989 size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
1990
1991 dma_free_attrs(dev->dev, size, bufs[i],
1992 le64_to_cpu(descs[i].addr),
1993 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1994 }
1995
1996 kfree(bufs);
1997 out_free_descs:
1998 dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
1999 descs_dma);
2000 out:
2001 dev->host_mem_descs = NULL;
2002 return -ENOMEM;
2003 }
2004
nvme_alloc_host_mem(struct nvme_dev * dev,u64 min,u64 preferred)2005 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2006 {
2007 u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2008 u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2009 u64 chunk_size;
2010
2011 /* start big and work our way down */
2012 for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2013 if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2014 if (!min || dev->host_mem_size >= min)
2015 return 0;
2016 nvme_free_host_mem(dev);
2017 }
2018 }
2019
2020 return -ENOMEM;
2021 }
2022
nvme_setup_host_mem(struct nvme_dev * dev)2023 static int nvme_setup_host_mem(struct nvme_dev *dev)
2024 {
2025 u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2026 u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2027 u64 min = (u64)dev->ctrl.hmmin * 4096;
2028 u32 enable_bits = NVME_HOST_MEM_ENABLE;
2029 int ret;
2030
2031 if (!dev->ctrl.hmpre)
2032 return 0;
2033
2034 preferred = min(preferred, max);
2035 if (min > max) {
2036 dev_warn(dev->ctrl.device,
2037 "min host memory (%lld MiB) above limit (%d MiB).\n",
2038 min >> ilog2(SZ_1M), max_host_mem_size_mb);
2039 nvme_free_host_mem(dev);
2040 return 0;
2041 }
2042
2043 /*
2044 * If we already have a buffer allocated check if we can reuse it.
2045 */
2046 if (dev->host_mem_descs) {
2047 if (dev->host_mem_size >= min)
2048 enable_bits |= NVME_HOST_MEM_RETURN;
2049 else
2050 nvme_free_host_mem(dev);
2051 }
2052
2053 if (!dev->host_mem_descs) {
2054 if (nvme_alloc_host_mem(dev, min, preferred)) {
2055 dev_warn(dev->ctrl.device,
2056 "failed to allocate host memory buffer.\n");
2057 return 0; /* controller must work without HMB */
2058 }
2059
2060 dev_info(dev->ctrl.device,
2061 "allocated %lld MiB host memory buffer.\n",
2062 dev->host_mem_size >> ilog2(SZ_1M));
2063 }
2064
2065 ret = nvme_set_host_mem(dev, enable_bits);
2066 if (ret)
2067 nvme_free_host_mem(dev);
2068 return ret;
2069 }
2070
cmb_show(struct device * dev,struct device_attribute * attr,char * buf)2071 static ssize_t cmb_show(struct device *dev, struct device_attribute *attr,
2072 char *buf)
2073 {
2074 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2075
2076 return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n",
2077 ndev->cmbloc, ndev->cmbsz);
2078 }
2079 static DEVICE_ATTR_RO(cmb);
2080
cmbloc_show(struct device * dev,struct device_attribute * attr,char * buf)2081 static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr,
2082 char *buf)
2083 {
2084 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2085
2086 return sysfs_emit(buf, "%u\n", ndev->cmbloc);
2087 }
2088 static DEVICE_ATTR_RO(cmbloc);
2089
cmbsz_show(struct device * dev,struct device_attribute * attr,char * buf)2090 static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr,
2091 char *buf)
2092 {
2093 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2094
2095 return sysfs_emit(buf, "%u\n", ndev->cmbsz);
2096 }
2097 static DEVICE_ATTR_RO(cmbsz);
2098
hmb_show(struct device * dev,struct device_attribute * attr,char * buf)2099 static ssize_t hmb_show(struct device *dev, struct device_attribute *attr,
2100 char *buf)
2101 {
2102 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2103
2104 return sysfs_emit(buf, "%d\n", ndev->hmb);
2105 }
2106
hmb_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)2107 static ssize_t hmb_store(struct device *dev, struct device_attribute *attr,
2108 const char *buf, size_t count)
2109 {
2110 struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
2111 bool new;
2112 int ret;
2113
2114 if (kstrtobool(buf, &new) < 0)
2115 return -EINVAL;
2116
2117 if (new == ndev->hmb)
2118 return count;
2119
2120 if (new) {
2121 ret = nvme_setup_host_mem(ndev);
2122 } else {
2123 ret = nvme_set_host_mem(ndev, 0);
2124 if (!ret)
2125 nvme_free_host_mem(ndev);
2126 }
2127
2128 if (ret < 0)
2129 return ret;
2130
2131 return count;
2132 }
2133 static DEVICE_ATTR_RW(hmb);
2134
nvme_pci_attrs_are_visible(struct kobject * kobj,struct attribute * a,int n)2135 static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj,
2136 struct attribute *a, int n)
2137 {
2138 struct nvme_ctrl *ctrl =
2139 dev_get_drvdata(container_of(kobj, struct device, kobj));
2140 struct nvme_dev *dev = to_nvme_dev(ctrl);
2141
2142 if (a == &dev_attr_cmb.attr ||
2143 a == &dev_attr_cmbloc.attr ||
2144 a == &dev_attr_cmbsz.attr) {
2145 if (!dev->cmbsz)
2146 return 0;
2147 }
2148 if (a == &dev_attr_hmb.attr && !ctrl->hmpre)
2149 return 0;
2150
2151 return a->mode;
2152 }
2153
2154 static struct attribute *nvme_pci_attrs[] = {
2155 &dev_attr_cmb.attr,
2156 &dev_attr_cmbloc.attr,
2157 &dev_attr_cmbsz.attr,
2158 &dev_attr_hmb.attr,
2159 NULL,
2160 };
2161
2162 static const struct attribute_group nvme_pci_dev_attrs_group = {
2163 .attrs = nvme_pci_attrs,
2164 .is_visible = nvme_pci_attrs_are_visible,
2165 };
2166
2167 static const struct attribute_group *nvme_pci_dev_attr_groups[] = {
2168 &nvme_dev_attrs_group,
2169 &nvme_pci_dev_attrs_group,
2170 NULL,
2171 };
2172
nvme_update_attrs(struct nvme_dev * dev)2173 static void nvme_update_attrs(struct nvme_dev *dev)
2174 {
2175 sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group);
2176 }
2177
2178 /*
2179 * nirqs is the number of interrupts available for write and read
2180 * queues. The core already reserved an interrupt for the admin queue.
2181 */
nvme_calc_irq_sets(struct irq_affinity * affd,unsigned int nrirqs)2182 static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2183 {
2184 struct nvme_dev *dev = affd->priv;
2185 unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2186
2187 /*
2188 * If there is no interrupt available for queues, ensure that
2189 * the default queue is set to 1. The affinity set size is
2190 * also set to one, but the irq core ignores it for this case.
2191 *
2192 * If only one interrupt is available or 'write_queue' == 0, combine
2193 * write and read queues.
2194 *
2195 * If 'write_queues' > 0, ensure it leaves room for at least one read
2196 * queue.
2197 */
2198 if (!nrirqs) {
2199 nrirqs = 1;
2200 nr_read_queues = 0;
2201 } else if (nrirqs == 1 || !nr_write_queues) {
2202 nr_read_queues = 0;
2203 } else if (nr_write_queues >= nrirqs) {
2204 nr_read_queues = 1;
2205 } else {
2206 nr_read_queues = nrirqs - nr_write_queues;
2207 }
2208
2209 dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2210 affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2211 dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2212 affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2213 affd->nr_sets = nr_read_queues ? 2 : 1;
2214 }
2215
nvme_setup_irqs(struct nvme_dev * dev,unsigned int nr_io_queues)2216 static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2217 {
2218 struct pci_dev *pdev = to_pci_dev(dev->dev);
2219 struct irq_affinity affd = {
2220 .pre_vectors = 1,
2221 .calc_sets = nvme_calc_irq_sets,
2222 .priv = dev,
2223 };
2224 unsigned int irq_queues, poll_queues;
2225 unsigned int flags = PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY;
2226
2227 /*
2228 * Poll queues don't need interrupts, but we need at least one I/O queue
2229 * left over for non-polled I/O.
2230 */
2231 poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2232 dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2233
2234 /*
2235 * Initialize for the single interrupt case, will be updated in
2236 * nvme_calc_irq_sets().
2237 */
2238 dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2239 dev->io_queues[HCTX_TYPE_READ] = 0;
2240
2241 /*
2242 * We need interrupts for the admin queue and each non-polled I/O queue,
2243 * but some Apple controllers require all queues to use the first
2244 * vector.
2245 */
2246 irq_queues = 1;
2247 if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2248 irq_queues += (nr_io_queues - poll_queues);
2249 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2250 flags &= ~PCI_IRQ_MSI;
2251 return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, flags,
2252 &affd);
2253 }
2254
nvme_max_io_queues(struct nvme_dev * dev)2255 static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2256 {
2257 /*
2258 * If tags are shared with admin queue (Apple bug), then
2259 * make sure we only use one IO queue.
2260 */
2261 if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2262 return 1;
2263 return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2264 }
2265
nvme_setup_io_queues(struct nvme_dev * dev)2266 static int nvme_setup_io_queues(struct nvme_dev *dev)
2267 {
2268 struct nvme_queue *adminq = &dev->queues[0];
2269 struct pci_dev *pdev = to_pci_dev(dev->dev);
2270 unsigned int nr_io_queues;
2271 unsigned long size;
2272 int result;
2273
2274 /*
2275 * Sample the module parameters once at reset time so that we have
2276 * stable values to work with.
2277 */
2278 dev->nr_write_queues = write_queues;
2279 dev->nr_poll_queues = poll_queues;
2280
2281 nr_io_queues = dev->nr_allocated_queues - 1;
2282 result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2283 if (result < 0)
2284 return result;
2285
2286 if (nr_io_queues == 0)
2287 return 0;
2288
2289 /*
2290 * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2291 * from set to unset. If there is a window to it is truely freed,
2292 * pci_free_irq_vectors() jumping into this window will crash.
2293 * And take lock to avoid racing with pci_free_irq_vectors() in
2294 * nvme_dev_disable() path.
2295 */
2296 result = nvme_setup_io_queues_trylock(dev);
2297 if (result)
2298 return result;
2299 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2300 pci_free_irq(pdev, 0, adminq);
2301
2302 if (dev->cmb_use_sqes) {
2303 result = nvme_cmb_qdepth(dev, nr_io_queues,
2304 sizeof(struct nvme_command));
2305 if (result > 0) {
2306 dev->q_depth = result;
2307 dev->ctrl.sqsize = result - 1;
2308 } else {
2309 dev->cmb_use_sqes = false;
2310 }
2311 }
2312
2313 do {
2314 size = db_bar_size(dev, nr_io_queues);
2315 result = nvme_remap_bar(dev, size);
2316 if (!result)
2317 break;
2318 if (!--nr_io_queues) {
2319 result = -ENOMEM;
2320 goto out_unlock;
2321 }
2322 } while (1);
2323 adminq->q_db = dev->dbs;
2324
2325 retry:
2326 /* Deregister the admin queue's interrupt */
2327 if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2328 pci_free_irq(pdev, 0, adminq);
2329
2330 /*
2331 * If we enable msix early due to not intx, disable it again before
2332 * setting up the full range we need.
2333 */
2334 pci_free_irq_vectors(pdev);
2335
2336 result = nvme_setup_irqs(dev, nr_io_queues);
2337 if (result <= 0) {
2338 result = -EIO;
2339 goto out_unlock;
2340 }
2341
2342 dev->num_vecs = result;
2343 result = max(result - 1, 1);
2344 dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2345
2346 /*
2347 * Should investigate if there's a performance win from allocating
2348 * more queues than interrupt vectors; it might allow the submission
2349 * path to scale better, even if the receive path is limited by the
2350 * number of interrupts.
2351 */
2352 result = queue_request_irq(adminq);
2353 if (result)
2354 goto out_unlock;
2355 set_bit(NVMEQ_ENABLED, &adminq->flags);
2356 mutex_unlock(&dev->shutdown_lock);
2357
2358 result = nvme_create_io_queues(dev);
2359 if (result || dev->online_queues < 2)
2360 return result;
2361
2362 if (dev->online_queues - 1 < dev->max_qid) {
2363 nr_io_queues = dev->online_queues - 1;
2364 nvme_delete_io_queues(dev);
2365 result = nvme_setup_io_queues_trylock(dev);
2366 if (result)
2367 return result;
2368 nvme_suspend_io_queues(dev);
2369 goto retry;
2370 }
2371 dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2372 dev->io_queues[HCTX_TYPE_DEFAULT],
2373 dev->io_queues[HCTX_TYPE_READ],
2374 dev->io_queues[HCTX_TYPE_POLL]);
2375 return 0;
2376 out_unlock:
2377 mutex_unlock(&dev->shutdown_lock);
2378 return result;
2379 }
2380
nvme_del_queue_end(struct request * req,blk_status_t error)2381 static enum rq_end_io_ret nvme_del_queue_end(struct request *req,
2382 blk_status_t error)
2383 {
2384 struct nvme_queue *nvmeq = req->end_io_data;
2385
2386 blk_mq_free_request(req);
2387 complete(&nvmeq->delete_done);
2388 return RQ_END_IO_NONE;
2389 }
2390
nvme_del_cq_end(struct request * req,blk_status_t error)2391 static enum rq_end_io_ret nvme_del_cq_end(struct request *req,
2392 blk_status_t error)
2393 {
2394 struct nvme_queue *nvmeq = req->end_io_data;
2395
2396 if (error)
2397 set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2398
2399 return nvme_del_queue_end(req, error);
2400 }
2401
nvme_delete_queue(struct nvme_queue * nvmeq,u8 opcode)2402 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2403 {
2404 struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2405 struct request *req;
2406 struct nvme_command cmd = { };
2407
2408 cmd.delete_queue.opcode = opcode;
2409 cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2410
2411 req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT);
2412 if (IS_ERR(req))
2413 return PTR_ERR(req);
2414 nvme_init_request(req, &cmd);
2415
2416 if (opcode == nvme_admin_delete_cq)
2417 req->end_io = nvme_del_cq_end;
2418 else
2419 req->end_io = nvme_del_queue_end;
2420 req->end_io_data = nvmeq;
2421
2422 init_completion(&nvmeq->delete_done);
2423 blk_execute_rq_nowait(req, false);
2424 return 0;
2425 }
2426
__nvme_delete_io_queues(struct nvme_dev * dev,u8 opcode)2427 static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode)
2428 {
2429 int nr_queues = dev->online_queues - 1, sent = 0;
2430 unsigned long timeout;
2431
2432 retry:
2433 timeout = NVME_ADMIN_TIMEOUT;
2434 while (nr_queues > 0) {
2435 if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2436 break;
2437 nr_queues--;
2438 sent++;
2439 }
2440 while (sent) {
2441 struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2442
2443 timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2444 timeout);
2445 if (timeout == 0)
2446 return false;
2447
2448 sent--;
2449 if (nr_queues)
2450 goto retry;
2451 }
2452 return true;
2453 }
2454
nvme_delete_io_queues(struct nvme_dev * dev)2455 static void nvme_delete_io_queues(struct nvme_dev *dev)
2456 {
2457 if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq))
2458 __nvme_delete_io_queues(dev, nvme_admin_delete_cq);
2459 }
2460
nvme_pci_nr_maps(struct nvme_dev * dev)2461 static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev)
2462 {
2463 if (dev->io_queues[HCTX_TYPE_POLL])
2464 return 3;
2465 if (dev->io_queues[HCTX_TYPE_READ])
2466 return 2;
2467 return 1;
2468 }
2469
nvme_pci_update_nr_queues(struct nvme_dev * dev)2470 static void nvme_pci_update_nr_queues(struct nvme_dev *dev)
2471 {
2472 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2473 /* free previously allocated queues that are no longer usable */
2474 nvme_free_queues(dev, dev->online_queues);
2475 }
2476
nvme_pci_enable(struct nvme_dev * dev)2477 static int nvme_pci_enable(struct nvme_dev *dev)
2478 {
2479 int result = -ENOMEM;
2480 struct pci_dev *pdev = to_pci_dev(dev->dev);
2481 unsigned int flags = PCI_IRQ_ALL_TYPES;
2482
2483 if (pci_enable_device_mem(pdev))
2484 return result;
2485
2486 pci_set_master(pdev);
2487
2488 if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2489 result = -ENODEV;
2490 goto disable;
2491 }
2492
2493 /*
2494 * Some devices and/or platforms don't advertise or work with INTx
2495 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2496 * adjust this later.
2497 */
2498 if (dev->ctrl.quirks & NVME_QUIRK_BROKEN_MSI)
2499 flags &= ~PCI_IRQ_MSI;
2500 result = pci_alloc_irq_vectors(pdev, 1, 1, flags);
2501 if (result < 0)
2502 goto disable;
2503
2504 dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2505
2506 dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2507 io_queue_depth);
2508 dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2509 dev->dbs = dev->bar + 4096;
2510
2511 /*
2512 * Some Apple controllers require a non-standard SQE size.
2513 * Interestingly they also seem to ignore the CC:IOSQES register
2514 * so we don't bother updating it here.
2515 */
2516 if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2517 dev->io_sqes = 7;
2518 else
2519 dev->io_sqes = NVME_NVM_IOSQES;
2520
2521 /*
2522 * Temporary fix for the Apple controller found in the MacBook8,1 and
2523 * some MacBook7,1 to avoid controller resets and data loss.
2524 */
2525 if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2526 dev->q_depth = 2;
2527 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2528 "set queue depth=%u to work around controller resets\n",
2529 dev->q_depth);
2530 } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2531 (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2532 NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2533 dev->q_depth = 64;
2534 dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2535 "set queue depth=%u\n", dev->q_depth);
2536 }
2537
2538 /*
2539 * Controllers with the shared tags quirk need the IO queue to be
2540 * big enough so that we get 32 tags for the admin queue
2541 */
2542 if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2543 (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2544 dev->q_depth = NVME_AQ_DEPTH + 2;
2545 dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2546 dev->q_depth);
2547 }
2548 dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2549
2550 nvme_map_cmb(dev);
2551
2552 pci_save_state(pdev);
2553
2554 result = nvme_pci_configure_admin_queue(dev);
2555 if (result)
2556 goto free_irq;
2557 return result;
2558
2559 free_irq:
2560 pci_free_irq_vectors(pdev);
2561 disable:
2562 pci_disable_device(pdev);
2563 return result;
2564 }
2565
nvme_dev_unmap(struct nvme_dev * dev)2566 static void nvme_dev_unmap(struct nvme_dev *dev)
2567 {
2568 if (dev->bar)
2569 iounmap(dev->bar);
2570 pci_release_mem_regions(to_pci_dev(dev->dev));
2571 }
2572
nvme_pci_ctrl_is_dead(struct nvme_dev * dev)2573 static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev)
2574 {
2575 struct pci_dev *pdev = to_pci_dev(dev->dev);
2576 u32 csts;
2577
2578 if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev))
2579 return true;
2580 if (pdev->error_state != pci_channel_io_normal)
2581 return true;
2582
2583 csts = readl(dev->bar + NVME_REG_CSTS);
2584 return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY);
2585 }
2586
nvme_dev_disable(struct nvme_dev * dev,bool shutdown)2587 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2588 {
2589 enum nvme_ctrl_state state = nvme_ctrl_state(&dev->ctrl);
2590 struct pci_dev *pdev = to_pci_dev(dev->dev);
2591 bool dead;
2592
2593 mutex_lock(&dev->shutdown_lock);
2594 dead = nvme_pci_ctrl_is_dead(dev);
2595 if (state == NVME_CTRL_LIVE || state == NVME_CTRL_RESETTING) {
2596 if (pci_is_enabled(pdev))
2597 nvme_start_freeze(&dev->ctrl);
2598 /*
2599 * Give the controller a chance to complete all entered requests
2600 * if doing a safe shutdown.
2601 */
2602 if (!dead && shutdown)
2603 nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2604 }
2605
2606 nvme_quiesce_io_queues(&dev->ctrl);
2607
2608 if (!dead && dev->ctrl.queue_count > 0) {
2609 nvme_delete_io_queues(dev);
2610 nvme_disable_ctrl(&dev->ctrl, shutdown);
2611 nvme_poll_irqdisable(&dev->queues[0]);
2612 }
2613 nvme_suspend_io_queues(dev);
2614 nvme_suspend_queue(dev, 0);
2615 pci_free_irq_vectors(pdev);
2616 if (pci_is_enabled(pdev))
2617 pci_disable_device(pdev);
2618 nvme_reap_pending_cqes(dev);
2619
2620 nvme_cancel_tagset(&dev->ctrl);
2621 nvme_cancel_admin_tagset(&dev->ctrl);
2622
2623 /*
2624 * The driver will not be starting up queues again if shutting down so
2625 * must flush all entered requests to their failed completion to avoid
2626 * deadlocking blk-mq hot-cpu notifier.
2627 */
2628 if (shutdown) {
2629 nvme_unquiesce_io_queues(&dev->ctrl);
2630 if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2631 nvme_unquiesce_admin_queue(&dev->ctrl);
2632 }
2633 mutex_unlock(&dev->shutdown_lock);
2634 }
2635
nvme_disable_prepare_reset(struct nvme_dev * dev,bool shutdown)2636 static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2637 {
2638 if (!nvme_wait_reset(&dev->ctrl))
2639 return -EBUSY;
2640 nvme_dev_disable(dev, shutdown);
2641 return 0;
2642 }
2643
nvme_setup_prp_pools(struct nvme_dev * dev)2644 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2645 {
2646 dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2647 NVME_CTRL_PAGE_SIZE,
2648 NVME_CTRL_PAGE_SIZE, 0);
2649 if (!dev->prp_page_pool)
2650 return -ENOMEM;
2651
2652 /* Optimisation for I/Os between 4k and 128k */
2653 dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2654 256, 256, 0);
2655 if (!dev->prp_small_pool) {
2656 dma_pool_destroy(dev->prp_page_pool);
2657 return -ENOMEM;
2658 }
2659 return 0;
2660 }
2661
nvme_release_prp_pools(struct nvme_dev * dev)2662 static void nvme_release_prp_pools(struct nvme_dev *dev)
2663 {
2664 dma_pool_destroy(dev->prp_page_pool);
2665 dma_pool_destroy(dev->prp_small_pool);
2666 }
2667
nvme_pci_alloc_iod_mempool(struct nvme_dev * dev)2668 static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev)
2669 {
2670 size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS;
2671
2672 dev->iod_mempool = mempool_create_node(1,
2673 mempool_kmalloc, mempool_kfree,
2674 (void *)alloc_size, GFP_KERNEL,
2675 dev_to_node(dev->dev));
2676 if (!dev->iod_mempool)
2677 return -ENOMEM;
2678 return 0;
2679 }
2680
nvme_free_tagset(struct nvme_dev * dev)2681 static void nvme_free_tagset(struct nvme_dev *dev)
2682 {
2683 if (dev->tagset.tags)
2684 nvme_remove_io_tag_set(&dev->ctrl);
2685 dev->ctrl.tagset = NULL;
2686 }
2687
2688 /* pairs with nvme_pci_alloc_dev */
nvme_pci_free_ctrl(struct nvme_ctrl * ctrl)2689 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2690 {
2691 struct nvme_dev *dev = to_nvme_dev(ctrl);
2692
2693 nvme_free_tagset(dev);
2694 put_device(dev->dev);
2695 kfree(dev->queues);
2696 kfree(dev);
2697 }
2698
nvme_reset_work(struct work_struct * work)2699 static void nvme_reset_work(struct work_struct *work)
2700 {
2701 struct nvme_dev *dev =
2702 container_of(work, struct nvme_dev, ctrl.reset_work);
2703 bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2704 int result;
2705
2706 if (nvme_ctrl_state(&dev->ctrl) != NVME_CTRL_RESETTING) {
2707 dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2708 dev->ctrl.state);
2709 result = -ENODEV;
2710 goto out;
2711 }
2712
2713 /*
2714 * If we're called to reset a live controller first shut it down before
2715 * moving on.
2716 */
2717 if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2718 nvme_dev_disable(dev, false);
2719 nvme_sync_queues(&dev->ctrl);
2720
2721 mutex_lock(&dev->shutdown_lock);
2722 result = nvme_pci_enable(dev);
2723 if (result)
2724 goto out_unlock;
2725 nvme_unquiesce_admin_queue(&dev->ctrl);
2726 mutex_unlock(&dev->shutdown_lock);
2727
2728 /*
2729 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2730 * initializing procedure here.
2731 */
2732 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2733 dev_warn(dev->ctrl.device,
2734 "failed to mark controller CONNECTING\n");
2735 result = -EBUSY;
2736 goto out;
2737 }
2738
2739 result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend);
2740 if (result)
2741 goto out;
2742
2743 nvme_dbbuf_dma_alloc(dev);
2744
2745 result = nvme_setup_host_mem(dev);
2746 if (result < 0)
2747 goto out;
2748
2749 result = nvme_setup_io_queues(dev);
2750 if (result)
2751 goto out;
2752
2753 /*
2754 * Freeze and update the number of I/O queues as thos might have
2755 * changed. If there are no I/O queues left after this reset, keep the
2756 * controller around but remove all namespaces.
2757 */
2758 if (dev->online_queues > 1) {
2759 nvme_unquiesce_io_queues(&dev->ctrl);
2760 nvme_wait_freeze(&dev->ctrl);
2761 nvme_pci_update_nr_queues(dev);
2762 nvme_dbbuf_set(dev);
2763 nvme_unfreeze(&dev->ctrl);
2764 } else {
2765 dev_warn(dev->ctrl.device, "IO queues lost\n");
2766 nvme_mark_namespaces_dead(&dev->ctrl);
2767 nvme_unquiesce_io_queues(&dev->ctrl);
2768 nvme_remove_namespaces(&dev->ctrl);
2769 nvme_free_tagset(dev);
2770 }
2771
2772 /*
2773 * If only admin queue live, keep it to do further investigation or
2774 * recovery.
2775 */
2776 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2777 dev_warn(dev->ctrl.device,
2778 "failed to mark controller live state\n");
2779 result = -ENODEV;
2780 goto out;
2781 }
2782
2783 nvme_start_ctrl(&dev->ctrl);
2784 return;
2785
2786 out_unlock:
2787 mutex_unlock(&dev->shutdown_lock);
2788 out:
2789 /*
2790 * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2791 * may be holding this pci_dev's device lock.
2792 */
2793 dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n",
2794 result);
2795 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2796 nvme_dev_disable(dev, true);
2797 nvme_sync_queues(&dev->ctrl);
2798 nvme_mark_namespaces_dead(&dev->ctrl);
2799 nvme_unquiesce_io_queues(&dev->ctrl);
2800 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2801 }
2802
nvme_pci_reg_read32(struct nvme_ctrl * ctrl,u32 off,u32 * val)2803 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2804 {
2805 *val = readl(to_nvme_dev(ctrl)->bar + off);
2806 return 0;
2807 }
2808
nvme_pci_reg_write32(struct nvme_ctrl * ctrl,u32 off,u32 val)2809 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2810 {
2811 writel(val, to_nvme_dev(ctrl)->bar + off);
2812 return 0;
2813 }
2814
nvme_pci_reg_read64(struct nvme_ctrl * ctrl,u32 off,u64 * val)2815 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2816 {
2817 *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2818 return 0;
2819 }
2820
nvme_pci_get_address(struct nvme_ctrl * ctrl,char * buf,int size)2821 static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2822 {
2823 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2824
2825 return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2826 }
2827
nvme_pci_print_device_info(struct nvme_ctrl * ctrl)2828 static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl)
2829 {
2830 struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2831 struct nvme_subsystem *subsys = ctrl->subsys;
2832
2833 dev_err(ctrl->device,
2834 "VID:DID %04x:%04x model:%.*s firmware:%.*s\n",
2835 pdev->vendor, pdev->device,
2836 nvme_strlen(subsys->model, sizeof(subsys->model)),
2837 subsys->model, nvme_strlen(subsys->firmware_rev,
2838 sizeof(subsys->firmware_rev)),
2839 subsys->firmware_rev);
2840 }
2841
nvme_pci_supports_pci_p2pdma(struct nvme_ctrl * ctrl)2842 static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl)
2843 {
2844 struct nvme_dev *dev = to_nvme_dev(ctrl);
2845
2846 return dma_pci_p2pdma_supported(dev->dev);
2847 }
2848
2849 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2850 .name = "pcie",
2851 .module = THIS_MODULE,
2852 .flags = NVME_F_METADATA_SUPPORTED,
2853 .dev_attr_groups = nvme_pci_dev_attr_groups,
2854 .reg_read32 = nvme_pci_reg_read32,
2855 .reg_write32 = nvme_pci_reg_write32,
2856 .reg_read64 = nvme_pci_reg_read64,
2857 .free_ctrl = nvme_pci_free_ctrl,
2858 .submit_async_event = nvme_pci_submit_async_event,
2859 .get_address = nvme_pci_get_address,
2860 .print_device_info = nvme_pci_print_device_info,
2861 .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma,
2862 };
2863
nvme_dev_map(struct nvme_dev * dev)2864 static int nvme_dev_map(struct nvme_dev *dev)
2865 {
2866 struct pci_dev *pdev = to_pci_dev(dev->dev);
2867
2868 if (pci_request_mem_regions(pdev, "nvme"))
2869 return -ENODEV;
2870
2871 if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2872 goto release;
2873
2874 return 0;
2875 release:
2876 pci_release_mem_regions(pdev);
2877 return -ENODEV;
2878 }
2879
check_vendor_combination_bug(struct pci_dev * pdev)2880 static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2881 {
2882 if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2883 /*
2884 * Several Samsung devices seem to drop off the PCIe bus
2885 * randomly when APST is on and uses the deepest sleep state.
2886 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2887 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2888 * 950 PRO 256GB", but it seems to be restricted to two Dell
2889 * laptops.
2890 */
2891 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2892 (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2893 dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2894 return NVME_QUIRK_NO_DEEPEST_PS;
2895 } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2896 /*
2897 * Samsung SSD 960 EVO drops off the PCIe bus after system
2898 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2899 * within few minutes after bootup on a Coffee Lake board -
2900 * ASUS PRIME Z370-A
2901 */
2902 if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2903 (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2904 dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2905 return NVME_QUIRK_NO_APST;
2906 } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2907 pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2908 (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2909 /*
2910 * Forcing to use host managed nvme power settings for
2911 * lowest idle power with quick resume latency on
2912 * Samsung and Toshiba SSDs based on suspend behavior
2913 * on Coffee Lake board for LENOVO C640
2914 */
2915 if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2916 dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2917 return NVME_QUIRK_SIMPLE_SUSPEND;
2918 } else if (pdev->vendor == 0x2646 && (pdev->device == 0x2263 ||
2919 pdev->device == 0x500f)) {
2920 /*
2921 * Exclude some Kingston NV1 and A2000 devices from
2922 * NVME_QUIRK_SIMPLE_SUSPEND. Do a full suspend to save a
2923 * lot fo energy with s2idle sleep on some TUXEDO platforms.
2924 */
2925 if (dmi_match(DMI_BOARD_NAME, "NS5X_NS7XAU") ||
2926 dmi_match(DMI_BOARD_NAME, "NS5x_7xAU") ||
2927 dmi_match(DMI_BOARD_NAME, "NS5x_7xPU") ||
2928 dmi_match(DMI_BOARD_NAME, "PH4PRX1_PH6PRX1"))
2929 return NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND;
2930 }
2931
2932 return 0;
2933 }
2934
nvme_pci_alloc_dev(struct pci_dev * pdev,const struct pci_device_id * id)2935 static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev,
2936 const struct pci_device_id *id)
2937 {
2938 unsigned long quirks = id->driver_data;
2939 int node = dev_to_node(&pdev->dev);
2940 struct nvme_dev *dev;
2941 int ret = -ENOMEM;
2942
2943 dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2944 if (!dev)
2945 return ERR_PTR(-ENOMEM);
2946 INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2947 mutex_init(&dev->shutdown_lock);
2948
2949 dev->nr_write_queues = write_queues;
2950 dev->nr_poll_queues = poll_queues;
2951 dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2952 dev->queues = kcalloc_node(dev->nr_allocated_queues,
2953 sizeof(struct nvme_queue), GFP_KERNEL, node);
2954 if (!dev->queues)
2955 goto out_free_dev;
2956
2957 dev->dev = get_device(&pdev->dev);
2958
2959 quirks |= check_vendor_combination_bug(pdev);
2960 if (!noacpi &&
2961 !(quirks & NVME_QUIRK_FORCE_NO_SIMPLE_SUSPEND) &&
2962 acpi_storage_d3(&pdev->dev)) {
2963 /*
2964 * Some systems use a bios work around to ask for D3 on
2965 * platforms that support kernel managed suspend.
2966 */
2967 dev_info(&pdev->dev,
2968 "platform quirk: setting simple suspend\n");
2969 quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2970 }
2971 ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2972 quirks);
2973 if (ret)
2974 goto out_put_device;
2975
2976 if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2977 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48));
2978 else
2979 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
2980 dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1);
2981 dma_set_max_seg_size(&pdev->dev, 0xffffffff);
2982
2983 /*
2984 * Limit the max command size to prevent iod->sg allocations going
2985 * over a single page.
2986 */
2987 dev->ctrl.max_hw_sectors = min_t(u32,
2988 NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9);
2989 dev->ctrl.max_segments = NVME_MAX_SEGS;
2990
2991 /*
2992 * There is no support for SGLs for metadata (yet), so we are limited to
2993 * a single integrity segment for the separate metadata pointer.
2994 */
2995 dev->ctrl.max_integrity_segments = 1;
2996 return dev;
2997
2998 out_put_device:
2999 put_device(dev->dev);
3000 kfree(dev->queues);
3001 out_free_dev:
3002 kfree(dev);
3003 return ERR_PTR(ret);
3004 }
3005
nvme_probe(struct pci_dev * pdev,const struct pci_device_id * id)3006 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
3007 {
3008 struct nvme_dev *dev;
3009 int result = -ENOMEM;
3010
3011 dev = nvme_pci_alloc_dev(pdev, id);
3012 if (IS_ERR(dev))
3013 return PTR_ERR(dev);
3014
3015 result = nvme_dev_map(dev);
3016 if (result)
3017 goto out_uninit_ctrl;
3018
3019 result = nvme_setup_prp_pools(dev);
3020 if (result)
3021 goto out_dev_unmap;
3022
3023 result = nvme_pci_alloc_iod_mempool(dev);
3024 if (result)
3025 goto out_release_prp_pools;
3026
3027 dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
3028
3029 result = nvme_pci_enable(dev);
3030 if (result)
3031 goto out_release_iod_mempool;
3032
3033 result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset,
3034 &nvme_mq_admin_ops, sizeof(struct nvme_iod));
3035 if (result)
3036 goto out_disable;
3037
3038 /*
3039 * Mark the controller as connecting before sending admin commands to
3040 * allow the timeout handler to do the right thing.
3041 */
3042 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
3043 dev_warn(dev->ctrl.device,
3044 "failed to mark controller CONNECTING\n");
3045 result = -EBUSY;
3046 goto out_disable;
3047 }
3048
3049 result = nvme_init_ctrl_finish(&dev->ctrl, false);
3050 if (result)
3051 goto out_disable;
3052
3053 nvme_dbbuf_dma_alloc(dev);
3054
3055 result = nvme_setup_host_mem(dev);
3056 if (result < 0)
3057 goto out_disable;
3058
3059 result = nvme_setup_io_queues(dev);
3060 if (result)
3061 goto out_disable;
3062
3063 if (dev->online_queues > 1) {
3064 nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops,
3065 nvme_pci_nr_maps(dev), sizeof(struct nvme_iod));
3066 nvme_dbbuf_set(dev);
3067 }
3068
3069 if (!dev->ctrl.tagset)
3070 dev_warn(dev->ctrl.device, "IO queues not created\n");
3071
3072 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
3073 dev_warn(dev->ctrl.device,
3074 "failed to mark controller live state\n");
3075 result = -ENODEV;
3076 goto out_disable;
3077 }
3078
3079 pci_set_drvdata(pdev, dev);
3080
3081 nvme_start_ctrl(&dev->ctrl);
3082 nvme_put_ctrl(&dev->ctrl);
3083 flush_work(&dev->ctrl.scan_work);
3084 return 0;
3085
3086 out_disable:
3087 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3088 nvme_dev_disable(dev, true);
3089 nvme_free_host_mem(dev);
3090 nvme_dev_remove_admin(dev);
3091 nvme_dbbuf_dma_free(dev);
3092 nvme_free_queues(dev, 0);
3093 out_release_iod_mempool:
3094 mempool_destroy(dev->iod_mempool);
3095 out_release_prp_pools:
3096 nvme_release_prp_pools(dev);
3097 out_dev_unmap:
3098 nvme_dev_unmap(dev);
3099 out_uninit_ctrl:
3100 nvme_uninit_ctrl(&dev->ctrl);
3101 nvme_put_ctrl(&dev->ctrl);
3102 return result;
3103 }
3104
nvme_reset_prepare(struct pci_dev * pdev)3105 static void nvme_reset_prepare(struct pci_dev *pdev)
3106 {
3107 struct nvme_dev *dev = pci_get_drvdata(pdev);
3108
3109 /*
3110 * We don't need to check the return value from waiting for the reset
3111 * state as pci_dev device lock is held, making it impossible to race
3112 * with ->remove().
3113 */
3114 nvme_disable_prepare_reset(dev, false);
3115 nvme_sync_queues(&dev->ctrl);
3116 }
3117
nvme_reset_done(struct pci_dev * pdev)3118 static void nvme_reset_done(struct pci_dev *pdev)
3119 {
3120 struct nvme_dev *dev = pci_get_drvdata(pdev);
3121
3122 if (!nvme_try_sched_reset(&dev->ctrl))
3123 flush_work(&dev->ctrl.reset_work);
3124 }
3125
nvme_shutdown(struct pci_dev * pdev)3126 static void nvme_shutdown(struct pci_dev *pdev)
3127 {
3128 struct nvme_dev *dev = pci_get_drvdata(pdev);
3129
3130 nvme_disable_prepare_reset(dev, true);
3131 }
3132
3133 /*
3134 * The driver's remove may be called on a device in a partially initialized
3135 * state. This function must not have any dependencies on the device state in
3136 * order to proceed.
3137 */
nvme_remove(struct pci_dev * pdev)3138 static void nvme_remove(struct pci_dev *pdev)
3139 {
3140 struct nvme_dev *dev = pci_get_drvdata(pdev);
3141
3142 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3143 pci_set_drvdata(pdev, NULL);
3144
3145 if (!pci_device_is_present(pdev)) {
3146 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3147 nvme_dev_disable(dev, true);
3148 }
3149
3150 flush_work(&dev->ctrl.reset_work);
3151 nvme_stop_ctrl(&dev->ctrl);
3152 nvme_remove_namespaces(&dev->ctrl);
3153 nvme_dev_disable(dev, true);
3154 nvme_free_host_mem(dev);
3155 nvme_dev_remove_admin(dev);
3156 nvme_dbbuf_dma_free(dev);
3157 nvme_free_queues(dev, 0);
3158 mempool_destroy(dev->iod_mempool);
3159 nvme_release_prp_pools(dev);
3160 nvme_dev_unmap(dev);
3161 nvme_uninit_ctrl(&dev->ctrl);
3162 }
3163
3164 #ifdef CONFIG_PM_SLEEP
nvme_get_power_state(struct nvme_ctrl * ctrl,u32 * ps)3165 static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3166 {
3167 return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3168 }
3169
nvme_set_power_state(struct nvme_ctrl * ctrl,u32 ps)3170 static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3171 {
3172 return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3173 }
3174
nvme_resume(struct device * dev)3175 static int nvme_resume(struct device *dev)
3176 {
3177 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3178 struct nvme_ctrl *ctrl = &ndev->ctrl;
3179
3180 if (ndev->last_ps == U32_MAX ||
3181 nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3182 goto reset;
3183 if (ctrl->hmpre && nvme_setup_host_mem(ndev))
3184 goto reset;
3185
3186 return 0;
3187 reset:
3188 return nvme_try_sched_reset(ctrl);
3189 }
3190
nvme_suspend(struct device * dev)3191 static int nvme_suspend(struct device *dev)
3192 {
3193 struct pci_dev *pdev = to_pci_dev(dev);
3194 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3195 struct nvme_ctrl *ctrl = &ndev->ctrl;
3196 int ret = -EBUSY;
3197
3198 ndev->last_ps = U32_MAX;
3199
3200 /*
3201 * The platform does not remove power for a kernel managed suspend so
3202 * use host managed nvme power settings for lowest idle power if
3203 * possible. This should have quicker resume latency than a full device
3204 * shutdown. But if the firmware is involved after the suspend or the
3205 * device does not support any non-default power states, shut down the
3206 * device fully.
3207 *
3208 * If ASPM is not enabled for the device, shut down the device and allow
3209 * the PCI bus layer to put it into D3 in order to take the PCIe link
3210 * down, so as to allow the platform to achieve its minimum low-power
3211 * state (which may not be possible if the link is up).
3212 */
3213 if (pm_suspend_via_firmware() || !ctrl->npss ||
3214 !pcie_aspm_enabled(pdev) ||
3215 (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3216 return nvme_disable_prepare_reset(ndev, true);
3217
3218 nvme_start_freeze(ctrl);
3219 nvme_wait_freeze(ctrl);
3220 nvme_sync_queues(ctrl);
3221
3222 if (nvme_ctrl_state(ctrl) != NVME_CTRL_LIVE)
3223 goto unfreeze;
3224
3225 /*
3226 * Host memory access may not be successful in a system suspend state,
3227 * but the specification allows the controller to access memory in a
3228 * non-operational power state.
3229 */
3230 if (ndev->hmb) {
3231 ret = nvme_set_host_mem(ndev, 0);
3232 if (ret < 0)
3233 goto unfreeze;
3234 }
3235
3236 ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3237 if (ret < 0)
3238 goto unfreeze;
3239
3240 /*
3241 * A saved state prevents pci pm from generically controlling the
3242 * device's power. If we're using protocol specific settings, we don't
3243 * want pci interfering.
3244 */
3245 pci_save_state(pdev);
3246
3247 ret = nvme_set_power_state(ctrl, ctrl->npss);
3248 if (ret < 0)
3249 goto unfreeze;
3250
3251 if (ret) {
3252 /* discard the saved state */
3253 pci_load_saved_state(pdev, NULL);
3254
3255 /*
3256 * Clearing npss forces a controller reset on resume. The
3257 * correct value will be rediscovered then.
3258 */
3259 ret = nvme_disable_prepare_reset(ndev, true);
3260 ctrl->npss = 0;
3261 }
3262 unfreeze:
3263 nvme_unfreeze(ctrl);
3264 return ret;
3265 }
3266
nvme_simple_suspend(struct device * dev)3267 static int nvme_simple_suspend(struct device *dev)
3268 {
3269 struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3270
3271 return nvme_disable_prepare_reset(ndev, true);
3272 }
3273
nvme_simple_resume(struct device * dev)3274 static int nvme_simple_resume(struct device *dev)
3275 {
3276 struct pci_dev *pdev = to_pci_dev(dev);
3277 struct nvme_dev *ndev = pci_get_drvdata(pdev);
3278
3279 return nvme_try_sched_reset(&ndev->ctrl);
3280 }
3281
3282 static const struct dev_pm_ops nvme_dev_pm_ops = {
3283 .suspend = nvme_suspend,
3284 .resume = nvme_resume,
3285 .freeze = nvme_simple_suspend,
3286 .thaw = nvme_simple_resume,
3287 .poweroff = nvme_simple_suspend,
3288 .restore = nvme_simple_resume,
3289 };
3290 #endif /* CONFIG_PM_SLEEP */
3291
nvme_error_detected(struct pci_dev * pdev,pci_channel_state_t state)3292 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3293 pci_channel_state_t state)
3294 {
3295 struct nvme_dev *dev = pci_get_drvdata(pdev);
3296
3297 /*
3298 * A frozen channel requires a reset. When detected, this method will
3299 * shutdown the controller to quiesce. The controller will be restarted
3300 * after the slot reset through driver's slot_reset callback.
3301 */
3302 switch (state) {
3303 case pci_channel_io_normal:
3304 return PCI_ERS_RESULT_CAN_RECOVER;
3305 case pci_channel_io_frozen:
3306 dev_warn(dev->ctrl.device,
3307 "frozen state error detected, reset controller\n");
3308 if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) {
3309 nvme_dev_disable(dev, true);
3310 return PCI_ERS_RESULT_DISCONNECT;
3311 }
3312 nvme_dev_disable(dev, false);
3313 return PCI_ERS_RESULT_NEED_RESET;
3314 case pci_channel_io_perm_failure:
3315 dev_warn(dev->ctrl.device,
3316 "failure state error detected, request disconnect\n");
3317 return PCI_ERS_RESULT_DISCONNECT;
3318 }
3319 return PCI_ERS_RESULT_NEED_RESET;
3320 }
3321
nvme_slot_reset(struct pci_dev * pdev)3322 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3323 {
3324 struct nvme_dev *dev = pci_get_drvdata(pdev);
3325
3326 dev_info(dev->ctrl.device, "restart after slot reset\n");
3327 pci_restore_state(pdev);
3328 if (!nvme_try_sched_reset(&dev->ctrl))
3329 nvme_unquiesce_io_queues(&dev->ctrl);
3330 return PCI_ERS_RESULT_RECOVERED;
3331 }
3332
nvme_error_resume(struct pci_dev * pdev)3333 static void nvme_error_resume(struct pci_dev *pdev)
3334 {
3335 struct nvme_dev *dev = pci_get_drvdata(pdev);
3336
3337 flush_work(&dev->ctrl.reset_work);
3338 }
3339
3340 static const struct pci_error_handlers nvme_err_handler = {
3341 .error_detected = nvme_error_detected,
3342 .slot_reset = nvme_slot_reset,
3343 .resume = nvme_error_resume,
3344 .reset_prepare = nvme_reset_prepare,
3345 .reset_done = nvme_reset_done,
3346 };
3347
3348 static const struct pci_device_id nvme_id_table[] = {
3349 { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */
3350 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3351 NVME_QUIRK_DEALLOCATE_ZEROES, },
3352 { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */
3353 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3354 NVME_QUIRK_DEALLOCATE_ZEROES, },
3355 { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */
3356 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3357 NVME_QUIRK_DEALLOCATE_ZEROES |
3358 NVME_QUIRK_IGNORE_DEV_SUBNQN |
3359 NVME_QUIRK_BOGUS_NID, },
3360 { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */
3361 .driver_data = NVME_QUIRK_STRIPE_SIZE |
3362 NVME_QUIRK_DEALLOCATE_ZEROES, },
3363 { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */
3364 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3365 NVME_QUIRK_MEDIUM_PRIO_SQ |
3366 NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3367 NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3368 { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */
3369 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3370 { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */
3371 .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3372 NVME_QUIRK_DISABLE_WRITE_ZEROES |
3373 NVME_QUIRK_BOGUS_NID, },
3374 { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */
3375 .driver_data = NVME_QUIRK_BOGUS_NID, },
3376 { PCI_DEVICE(0x126f, 0x2262), /* Silicon Motion generic */
3377 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3378 NVME_QUIRK_BOGUS_NID, },
3379 { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */
3380 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3381 NVME_QUIRK_BOGUS_NID, },
3382 { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */
3383 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3384 NVME_QUIRK_NO_NS_DESC_LIST, },
3385 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
3386 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3387 { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */
3388 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3389 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
3390 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3391 { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */
3392 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3393 { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */
3394 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3395 NVME_QUIRK_DISABLE_WRITE_ZEROES|
3396 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3397 { PCI_DEVICE(0x15b7, 0x5008), /* Sandisk SN530 */
3398 .driver_data = NVME_QUIRK_BROKEN_MSI },
3399 { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */
3400 .driver_data = NVME_QUIRK_BOGUS_NID, },
3401 { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */
3402 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3403 NVME_QUIRK_BOGUS_NID, },
3404 { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */
3405 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3406 { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */
3407 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3408 { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */
3409 .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3410 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3411 { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */
3412 .driver_data = NVME_QUIRK_BOGUS_NID, },
3413 { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */
3414 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN |
3415 NVME_QUIRK_BOGUS_NID, },
3416 { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */
3417 .driver_data = NVME_QUIRK_BOGUS_NID, },
3418 { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */
3419 .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3420 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3421 { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */
3422 .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN },
3423 { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */
3424 .driver_data = NVME_QUIRK_BOGUS_NID, },
3425 { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */
3426 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3427 { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */
3428 .driver_data = NVME_QUIRK_BOGUS_NID, },
3429 { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */
3430 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3431 { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */
3432 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3433 { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */
3434 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES |
3435 NVME_QUIRK_BOGUS_NID, },
3436 { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */
3437 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3438 { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */
3439 .driver_data = NVME_QUIRK_BOGUS_NID, },
3440 { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */
3441 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3442 { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */
3443 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3444 { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */
3445 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3446 { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */
3447 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3448 { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */
3449 .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, },
3450 { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */
3451 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3452 { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */
3453 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3454 { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */
3455 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3456 { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */
3457 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3458 { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */
3459 .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3460 { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */
3461 .driver_data = NVME_QUIRK_BOGUS_NID, },
3462 { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */
3463 .driver_data = NVME_QUIRK_BOGUS_NID, },
3464 { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */
3465 .driver_data = NVME_QUIRK_BOGUS_NID, },
3466 { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */
3467 .driver_data = NVME_QUIRK_BOGUS_NID, },
3468 { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */
3469 .driver_data = NVME_QUIRK_BOGUS_NID, },
3470 { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */
3471 .driver_data = NVME_QUIRK_BOGUS_NID, },
3472 { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */
3473 .driver_data = NVME_QUIRK_BOGUS_NID, },
3474 { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */
3475 .driver_data = NVME_QUIRK_BOGUS_NID, },
3476 { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */
3477 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3478 { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */
3479 .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3480 { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */
3481 .driver_data = NVME_QUIRK_BOGUS_NID, },
3482 { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */
3483 .driver_data = NVME_QUIRK_BOGUS_NID, },
3484 { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */
3485 .driver_data = NVME_QUIRK_BOGUS_NID, },
3486 { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */
3487 .driver_data = NVME_QUIRK_BOGUS_NID |
3488 NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3489 { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */
3490 .driver_data = NVME_QUIRK_BOGUS_NID, },
3491 { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */
3492 .driver_data = NVME_QUIRK_BOGUS_NID, },
3493 { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */
3494 .driver_data = NVME_QUIRK_BOGUS_NID, },
3495 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3496 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3497 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3498 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3499 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3500 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3501 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3502 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3503 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3504 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3505 { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3506 .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3507 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3508 .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3509 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3510 { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3511 .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3512 NVME_QUIRK_128_BYTES_SQES |
3513 NVME_QUIRK_SHARED_TAGS |
3514 NVME_QUIRK_SKIP_CID_GEN |
3515 NVME_QUIRK_IDENTIFY_CNS },
3516 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3517 { 0, }
3518 };
3519 MODULE_DEVICE_TABLE(pci, nvme_id_table);
3520
3521 static struct pci_driver nvme_driver = {
3522 .name = "nvme",
3523 .id_table = nvme_id_table,
3524 .probe = nvme_probe,
3525 .remove = nvme_remove,
3526 .shutdown = nvme_shutdown,
3527 .driver = {
3528 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3529 #ifdef CONFIG_PM_SLEEP
3530 .pm = &nvme_dev_pm_ops,
3531 #endif
3532 },
3533 .sriov_configure = pci_sriov_configure_simple,
3534 .err_handler = &nvme_err_handler,
3535 };
3536
nvme_init(void)3537 static int __init nvme_init(void)
3538 {
3539 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3540 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3541 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3542 BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3543 BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE);
3544 BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE);
3545 BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS);
3546
3547 return pci_register_driver(&nvme_driver);
3548 }
3549
nvme_exit(void)3550 static void __exit nvme_exit(void)
3551 {
3552 pci_unregister_driver(&nvme_driver);
3553 flush_workqueue(nvme_wq);
3554 }
3555
3556 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3557 MODULE_LICENSE("GPL");
3558 MODULE_VERSION("1.0");
3559 module_init(nvme_init);
3560 module_exit(nvme_exit);
3561