15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1457dacad5SJay Sternberg #include <linux/init.h> 1557dacad5SJay Sternberg #include <linux/interrupt.h> 1657dacad5SJay Sternberg #include <linux/io.h> 1757dacad5SJay Sternberg #include <linux/mm.h> 1857dacad5SJay Sternberg #include <linux/module.h> 1977bf25eaSKeith Busch #include <linux/mutex.h> 20d0877473SKeith Busch #include <linux/once.h> 2157dacad5SJay Sternberg #include <linux/pci.h> 22d916b1beSKeith Busch #include <linux/suspend.h> 2357dacad5SJay Sternberg #include <linux/t10-pi.h> 2457dacad5SJay Sternberg #include <linux/types.h> 259cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2620d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 27a98e58e5SScott Bauer #include <linux/sed-opal.h> 280f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2957dacad5SJay Sternberg 30604c01d5Syupeng #include "trace.h" 3157dacad5SJay Sternberg #include "nvme.h" 3257dacad5SJay Sternberg 33c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 348a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3557dacad5SJay Sternberg 36a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 37adf68f21SChristoph Hellwig 38943e942eSJens Axboe /* 39943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 40943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 41943e942eSJens Axboe */ 42943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 43943e942eSJens Axboe #define NVME_MAX_SEGS 127 44943e942eSJens Axboe 4557dacad5SJay Sternberg static int use_threaded_interrupts; 4657dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4757dacad5SJay Sternberg 4857dacad5SJay Sternberg static bool use_cmb_sqes = true; 4969f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5057dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5157dacad5SJay Sternberg 5287ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5387ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5487ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5587ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5657dacad5SJay Sternberg 57a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 58a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 59a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 60a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 61a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 62a7a7cbe3SChaitanya Kulkarni 63b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 64b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 65b27c1e68Sweiping zhang .set = io_queue_depth_set, 6661f3b896SChaitanya Kulkarni .get = param_get_uint, 67b27c1e68Sweiping zhang }; 68b27c1e68Sweiping zhang 6961f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 70b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 71b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 72b27c1e68Sweiping zhang 739c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 749c9e76d5SWeiping Zhang { 759c9e76d5SWeiping Zhang unsigned int n; 769c9e76d5SWeiping Zhang int ret; 779c9e76d5SWeiping Zhang 789c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 799c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 809c9e76d5SWeiping Zhang return -EINVAL; 819c9e76d5SWeiping Zhang return param_set_uint(val, kp); 829c9e76d5SWeiping Zhang } 839c9e76d5SWeiping Zhang 849c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 859c9e76d5SWeiping Zhang .set = io_queue_count_set, 869c9e76d5SWeiping Zhang .get = param_get_uint, 879c9e76d5SWeiping Zhang }; 889c9e76d5SWeiping Zhang 893f68baf7SKeith Busch static unsigned int write_queues; 909c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 913b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 923b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 933b6592f7SJens Axboe "will share a queue set."); 943b6592f7SJens Axboe 953f68baf7SKeith Busch static unsigned int poll_queues; 969c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 974b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 984b04cc6aSJens Axboe 99df4f9bc4SDavid E. Box static bool noacpi; 100df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 101df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 102df4f9bc4SDavid E. Box 1031c63dc66SChristoph Hellwig struct nvme_dev; 1041c63dc66SChristoph Hellwig struct nvme_queue; 10557dacad5SJay Sternberg 106a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1078fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 10857dacad5SJay Sternberg 10957dacad5SJay Sternberg /* 1101c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1111c63dc66SChristoph Hellwig */ 1121c63dc66SChristoph Hellwig struct nvme_dev { 113147b27e4SSagi Grimberg struct nvme_queue *queues; 1141c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1151c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1161c63dc66SChristoph Hellwig u32 __iomem *dbs; 1171c63dc66SChristoph Hellwig struct device *dev; 1181c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1191c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1201c63dc66SChristoph Hellwig unsigned online_queues; 1211c63dc66SChristoph Hellwig unsigned max_qid; 122e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12322b55601SKeith Busch unsigned int num_vecs; 1247442ddceSJohn Garry u32 q_depth; 125c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1261c63dc66SChristoph Hellwig u32 db_stride; 1271c63dc66SChristoph Hellwig void __iomem *bar; 12897f6ef64SXu Yu unsigned long bar_mapped_size; 1295c8809e6SChristoph Hellwig struct work_struct remove_work; 13077bf25eaSKeith Busch struct mutex shutdown_lock; 1311c63dc66SChristoph Hellwig bool subsystem; 1321c63dc66SChristoph Hellwig u64 cmb_size; 1330f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1341c63dc66SChristoph Hellwig u32 cmbsz; 135202021c1SStephen Bates u32 cmbloc; 1361c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 137d916b1beSKeith Busch u32 last_ps; 13887ad72a5SChristoph Hellwig 139943e942eSJens Axboe mempool_t *iod_mempool; 140943e942eSJens Axboe 14187ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 142f9f38e33SHelen Koike u32 *dbbuf_dbs; 143f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 144f9f38e33SHelen Koike u32 *dbbuf_eis; 145f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14687ad72a5SChristoph Hellwig 14787ad72a5SChristoph Hellwig /* host memory buffer support: */ 14887ad72a5SChristoph Hellwig u64 host_mem_size; 14987ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1504033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15287ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1532a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1542a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1552a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 15657dacad5SJay Sternberg }; 15757dacad5SJay Sternberg 158b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 159b27c1e68Sweiping zhang { 16061f3b896SChaitanya Kulkarni int ret; 1617442ddceSJohn Garry u32 n; 162b27c1e68Sweiping zhang 1637442ddceSJohn Garry ret = kstrtou32(val, 10, &n); 164b27c1e68Sweiping zhang if (ret != 0 || n < 2) 165b27c1e68Sweiping zhang return -EINVAL; 166b27c1e68Sweiping zhang 1677442ddceSJohn Garry return param_set_uint(val, kp); 168b27c1e68Sweiping zhang } 169b27c1e68Sweiping zhang 170f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171f9f38e33SHelen Koike { 172f9f38e33SHelen Koike return qid * 2 * stride; 173f9f38e33SHelen Koike } 174f9f38e33SHelen Koike 175f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176f9f38e33SHelen Koike { 177f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 178f9f38e33SHelen Koike } 179f9f38e33SHelen Koike 1801c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1811c63dc66SChristoph Hellwig { 1821c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1831c63dc66SChristoph Hellwig } 1841c63dc66SChristoph Hellwig 18557dacad5SJay Sternberg /* 18657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18757dacad5SJay Sternberg * commands and one for I/O commands). 18857dacad5SJay Sternberg */ 18957dacad5SJay Sternberg struct nvme_queue { 19057dacad5SJay Sternberg struct nvme_dev *dev; 1911ab0cd69SJens Axboe spinlock_t sq_lock; 192c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1933a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1943a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19574943d45SKeith Busch struct nvme_completion *cqes; 19657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19857dacad5SJay Sternberg u32 __iomem *q_db; 1997442ddceSJohn Garry u32 q_depth; 2007c349ddeSKeith Busch u16 cq_vector; 20157dacad5SJay Sternberg u16 sq_tail; 20238210800SKeith Busch u16 last_sq_tail; 20357dacad5SJay Sternberg u16 cq_head; 20457dacad5SJay Sternberg u16 qid; 20557dacad5SJay Sternberg u8 cq_phase; 206c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2074e224106SChristoph Hellwig unsigned long flags; 2084e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20963223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 210d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2117c349ddeSKeith Busch #define NVMEQ_POLLED 3 212f9f38e33SHelen Koike u32 *dbbuf_sq_db; 213f9f38e33SHelen Koike u32 *dbbuf_cq_db; 214f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 215f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 216d1ed6aa1SChristoph Hellwig struct completion delete_done; 21757dacad5SJay Sternberg }; 21857dacad5SJay Sternberg 21957dacad5SJay Sternberg /* 2209b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2219b048119SChristoph Hellwig * 2229b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2239b048119SChristoph Hellwig * to the actual struct scatterlist. 22471bd150cSChristoph Hellwig */ 22571bd150cSChristoph Hellwig struct nvme_iod { 226d49187e9SChristoph Hellwig struct nvme_request req; 227f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 228a7a7cbe3SChaitanya Kulkarni bool use_sgl; 229f4800d6dSChristoph Hellwig int aborted; 23071bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23171bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23271bd150cSChristoph Hellwig dma_addr_t first_dma; 233dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 234783b94bdSChristoph Hellwig dma_addr_t meta_dma; 235f4800d6dSChristoph Hellwig struct scatterlist *sg; 23657dacad5SJay Sternberg }; 23757dacad5SJay Sternberg 2382a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2393b6592f7SJens Axboe { 2402a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 241f9f38e33SHelen Koike } 242f9f38e33SHelen Koike 243f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 244f9f38e33SHelen Koike { 2452a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 246f9f38e33SHelen Koike 247f9f38e33SHelen Koike if (dev->dbbuf_dbs) 248f9f38e33SHelen Koike return 0; 249f9f38e33SHelen Koike 250f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 251f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 252f9f38e33SHelen Koike GFP_KERNEL); 253f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 254f9f38e33SHelen Koike return -ENOMEM; 255f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 256f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 257f9f38e33SHelen Koike GFP_KERNEL); 258f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 259f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 261f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 262f9f38e33SHelen Koike return -ENOMEM; 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike return 0; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 269f9f38e33SHelen Koike { 2702a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 273f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 274f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 275f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 276f9f38e33SHelen Koike } 277f9f38e33SHelen Koike if (dev->dbbuf_eis) { 278f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 279f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 280f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 281f9f38e33SHelen Koike } 282f9f38e33SHelen Koike } 283f9f38e33SHelen Koike 284f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 285f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 286f9f38e33SHelen Koike { 287f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 288f9f38e33SHelen Koike return; 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 291f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 292f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 293f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 294f9f38e33SHelen Koike } 295f9f38e33SHelen Koike 2960f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 2970f0d2c87SMinwoo Im { 2980f0d2c87SMinwoo Im if (!nvmeq->qid) 2990f0d2c87SMinwoo Im return; 3000f0d2c87SMinwoo Im 3010f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3020f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3030f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3040f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3050f0d2c87SMinwoo Im } 3060f0d2c87SMinwoo Im 307f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike struct nvme_command c; 3100f0d2c87SMinwoo Im unsigned int i; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 313f9f38e33SHelen Koike return; 314f9f38e33SHelen Koike 315f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 316f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 317f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 318f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 319f9f38e33SHelen Koike 320f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3219bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 322f9f38e33SHelen Koike /* Free memory and continue on */ 323f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3240f0d2c87SMinwoo Im 3250f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3260f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 327f9f38e33SHelen Koike } 328f9f38e33SHelen Koike } 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 331f9f38e33SHelen Koike { 332f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 333f9f38e33SHelen Koike } 334f9f38e33SHelen Koike 335f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 336f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 337f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 338f9f38e33SHelen Koike { 339f9f38e33SHelen Koike if (dbbuf_db) { 340f9f38e33SHelen Koike u16 old_value; 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike /* 343f9f38e33SHelen Koike * Ensure that the queue is written before updating 344f9f38e33SHelen Koike * the doorbell in memory 345f9f38e33SHelen Koike */ 346f9f38e33SHelen Koike wmb(); 347f9f38e33SHelen Koike 348f9f38e33SHelen Koike old_value = *dbbuf_db; 349f9f38e33SHelen Koike *dbbuf_db = value; 350f9f38e33SHelen Koike 351f1ed3df2SMichal Wnukowski /* 352f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 353f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 354f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 355f1ed3df2SMichal Wnukowski * the doorbell. 356f1ed3df2SMichal Wnukowski */ 357f1ed3df2SMichal Wnukowski mb(); 358f1ed3df2SMichal Wnukowski 359f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 360f9f38e33SHelen Koike return false; 361f9f38e33SHelen Koike } 362f9f38e33SHelen Koike 363f9f38e33SHelen Koike return true; 36457dacad5SJay Sternberg } 36557dacad5SJay Sternberg 36657dacad5SJay Sternberg /* 36757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 36857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 36957dacad5SJay Sternberg * the I/O. 37057dacad5SJay Sternberg */ 371b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37257dacad5SJay Sternberg { 373b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3746c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 37557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 37657dacad5SJay Sternberg } 37757dacad5SJay Sternberg 378a7a7cbe3SChaitanya Kulkarni /* 379a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 380a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 381a7a7cbe3SChaitanya Kulkarni */ 382b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 383f4800d6dSChristoph Hellwig { 384b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 385b13c6393SChaitanya Kulkarni PAGE_SIZE); 386f4800d6dSChristoph Hellwig } 387f4800d6dSChristoph Hellwig 388b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 38957dacad5SJay Sternberg { 390b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 391a7a7cbe3SChaitanya Kulkarni 392b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 393b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 394a7a7cbe3SChaitanya Kulkarni } 395a7a7cbe3SChaitanya Kulkarni 39657dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39757dacad5SJay Sternberg unsigned int hctx_idx) 39857dacad5SJay Sternberg { 39957dacad5SJay Sternberg struct nvme_dev *dev = data; 400147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40357dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40457dacad5SJay Sternberg 40557dacad5SJay Sternberg hctx->driver_data = nvmeq; 40657dacad5SJay Sternberg return 0; 40757dacad5SJay Sternberg } 40857dacad5SJay Sternberg 40957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41057dacad5SJay Sternberg unsigned int hctx_idx) 41157dacad5SJay Sternberg { 41257dacad5SJay Sternberg struct nvme_dev *dev = data; 413147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41457dacad5SJay Sternberg 41557dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41657dacad5SJay Sternberg hctx->driver_data = nvmeq; 41757dacad5SJay Sternberg return 0; 41857dacad5SJay Sternberg } 41957dacad5SJay Sternberg 420d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 421d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42257dacad5SJay Sternberg { 423d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 424f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4250350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 426147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 42757dacad5SJay Sternberg 42857dacad5SJay Sternberg BUG_ON(!nvmeq); 429f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 43059e29ce6SSagi Grimberg 43159e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 43257dacad5SJay Sternberg return 0; 43357dacad5SJay Sternberg } 43457dacad5SJay Sternberg 4353b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4363b6592f7SJens Axboe { 4373b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4383b6592f7SJens Axboe if (dev->num_vecs > 1) 4393b6592f7SJens Axboe return 1; 4403b6592f7SJens Axboe 4413b6592f7SJens Axboe return 0; 4423b6592f7SJens Axboe } 4433b6592f7SJens Axboe 444dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 445dca51e78SChristoph Hellwig { 446dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4473b6592f7SJens Axboe int i, qoff, offset; 448dca51e78SChristoph Hellwig 4493b6592f7SJens Axboe offset = queue_irq_offset(dev); 4503b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4513b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4523b6592f7SJens Axboe 4533b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4543b6592f7SJens Axboe if (!map->nr_queues) { 455e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4567e849dd9SChristoph Hellwig continue; 4573b6592f7SJens Axboe } 4583b6592f7SJens Axboe 4594b04cc6aSJens Axboe /* 4604b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4614b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4624b04cc6aSJens Axboe */ 4633b6592f7SJens Axboe map->queue_offset = qoff; 464cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4653b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4664b04cc6aSJens Axboe else 4674b04cc6aSJens Axboe blk_mq_map_queues(map); 4683b6592f7SJens Axboe qoff += map->nr_queues; 4693b6592f7SJens Axboe offset += map->nr_queues; 4703b6592f7SJens Axboe } 4713b6592f7SJens Axboe 4723b6592f7SJens Axboe return 0; 473dca51e78SChristoph Hellwig } 474dca51e78SChristoph Hellwig 47538210800SKeith Busch /* 47638210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47738210800SKeith Busch */ 47838210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47904f3eafdSJens Axboe { 48038210800SKeith Busch if (!write_sq) { 48138210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 48238210800SKeith Busch 48338210800SKeith Busch if (next_tail == nvmeq->q_depth) 48438210800SKeith Busch next_tail = 0; 48538210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48638210800SKeith Busch return; 48738210800SKeith Busch } 48838210800SKeith Busch 48904f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 49004f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49104f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 49238210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49304f3eafdSJens Axboe } 49404f3eafdSJens Axboe 49557dacad5SJay Sternberg /** 49690ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 49757dacad5SJay Sternberg * @nvmeq: The queue to use 49857dacad5SJay Sternberg * @cmd: The command to send 49904f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 50057dacad5SJay Sternberg */ 50104f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 50204f3eafdSJens Axboe bool write_sq) 50357dacad5SJay Sternberg { 50490ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 505c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 506c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 50790ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50890ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 50938210800SKeith Busch nvme_write_sq_db(nvmeq, write_sq); 51004f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 51104f3eafdSJens Axboe } 51204f3eafdSJens Axboe 51304f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51404f3eafdSJens Axboe { 51504f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51604f3eafdSJens Axboe 51704f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51838210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51938210800SKeith Busch nvme_write_sq_db(nvmeq, true); 52090ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52157dacad5SJay Sternberg } 52257dacad5SJay Sternberg 523a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52457dacad5SJay Sternberg { 525f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52757dacad5SJay Sternberg } 52857dacad5SJay Sternberg 529955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 530955b1b5aSMinwoo Im { 531955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53220469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 533955b1b5aSMinwoo Im unsigned int avg_seg_size; 534955b1b5aSMinwoo Im 53520469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 536955b1b5aSMinwoo Im 537955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 538955b1b5aSMinwoo Im return false; 539955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 540955b1b5aSMinwoo Im return false; 541955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 542955b1b5aSMinwoo Im return false; 543955b1b5aSMinwoo Im return true; 544955b1b5aSMinwoo Im } 545955b1b5aSMinwoo Im 5469275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54757dacad5SJay Sternberg { 5486c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5499275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5509275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 55157dacad5SJay Sternberg int i; 55257dacad5SJay Sternberg 5539275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5549275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5559275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5569275c206SChristoph Hellwig 5579275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5589275c206SChristoph Hellwig dma_addr = next_dma_addr; 559dff824b2SChristoph Hellwig } 560dff824b2SChristoph Hellwig 5619275c206SChristoph Hellwig } 5629275c206SChristoph Hellwig 5639275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5649275c206SChristoph Hellwig { 5659275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5669275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5679275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5689275c206SChristoph Hellwig int i; 5699275c206SChristoph Hellwig 5709275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5719275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5729275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5739275c206SChristoph Hellwig 5749275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5759275c206SChristoph Hellwig dma_addr = next_dma_addr; 5769275c206SChristoph Hellwig } 5779275c206SChristoph Hellwig 5789275c206SChristoph Hellwig } 5799275c206SChristoph Hellwig 5809275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5819275c206SChristoph Hellwig { 5829275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 583dff824b2SChristoph Hellwig 5847f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5857f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5867f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5877f73eac3SLogan Gunthorpe else 588dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5899275c206SChristoph Hellwig } 5907fe07d14SChristoph Hellwig 5919275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5929275c206SChristoph Hellwig { 5939275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5947fe07d14SChristoph Hellwig 5959275c206SChristoph Hellwig if (iod->dma_len) { 5969275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5979275c206SChristoph Hellwig rq_dma_dir(req)); 5989275c206SChristoph Hellwig return; 5999275c206SChristoph Hellwig } 6009275c206SChristoph Hellwig 6019275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 6029275c206SChristoph Hellwig 6039275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 60457dacad5SJay Sternberg if (iod->npages == 0) 605a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6069275c206SChristoph Hellwig iod->first_dma); 6079275c206SChristoph Hellwig else if (iod->use_sgl) 6089275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6099275c206SChristoph Hellwig else 6109275c206SChristoph Hellwig nvme_free_prps(dev, req); 611943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61257dacad5SJay Sternberg } 61357dacad5SJay Sternberg 614d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 615d0877473SKeith Busch { 616d0877473SKeith Busch int i; 617d0877473SKeith Busch struct scatterlist *sg; 618d0877473SKeith Busch 619d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 620d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 621d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 622d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 623d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 624d0877473SKeith Busch sg_dma_len(sg)); 625d0877473SKeith Busch } 626d0877473SKeith Busch } 627d0877473SKeith Busch 628a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 629a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 63057dacad5SJay Sternberg { 631f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63257dacad5SJay Sternberg struct dma_pool *pool; 633b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63457dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63557dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63657dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6376c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63857dacad5SJay Sternberg __le64 *prp_list; 639a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 64057dacad5SJay Sternberg dma_addr_t prp_dma; 64157dacad5SJay Sternberg int nprps, i; 64257dacad5SJay Sternberg 6436c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6445228b328SJan H. Schönherr if (length <= 0) { 6455228b328SJan H. Schönherr iod->first_dma = 0; 646a7a7cbe3SChaitanya Kulkarni goto done; 6475228b328SJan H. Schönherr } 64857dacad5SJay Sternberg 6496c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 65057dacad5SJay Sternberg if (dma_len) { 6516c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 65257dacad5SJay Sternberg } else { 65357dacad5SJay Sternberg sg = sg_next(sg); 65457dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65557dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65657dacad5SJay Sternberg } 65757dacad5SJay Sternberg 6586c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65957dacad5SJay Sternberg iod->first_dma = dma_addr; 660a7a7cbe3SChaitanya Kulkarni goto done; 66157dacad5SJay Sternberg } 66257dacad5SJay Sternberg 6636c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 66457dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66557dacad5SJay Sternberg pool = dev->prp_small_pool; 66657dacad5SJay Sternberg iod->npages = 0; 66757dacad5SJay Sternberg } else { 66857dacad5SJay Sternberg pool = dev->prp_page_pool; 66957dacad5SJay Sternberg iod->npages = 1; 67057dacad5SJay Sternberg } 67157dacad5SJay Sternberg 67269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67357dacad5SJay Sternberg if (!prp_list) { 67457dacad5SJay Sternberg iod->first_dma = dma_addr; 67557dacad5SJay Sternberg iod->npages = -1; 67686eea289SKeith Busch return BLK_STS_RESOURCE; 67757dacad5SJay Sternberg } 67857dacad5SJay Sternberg list[0] = prp_list; 67957dacad5SJay Sternberg iod->first_dma = prp_dma; 68057dacad5SJay Sternberg i = 0; 68157dacad5SJay Sternberg for (;;) { 6826c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 68357dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68557dacad5SJay Sternberg if (!prp_list) 686*fa073216SChristoph Hellwig goto free_prps; 68757dacad5SJay Sternberg list[iod->npages++] = prp_list; 68857dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68957dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 69057dacad5SJay Sternberg i = 1; 69157dacad5SJay Sternberg } 69257dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6936c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6946c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6956c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69657dacad5SJay Sternberg if (length <= 0) 69757dacad5SJay Sternberg break; 69857dacad5SJay Sternberg if (dma_len > 0) 69957dacad5SJay Sternberg continue; 70086eea289SKeith Busch if (unlikely(dma_len < 0)) 70186eea289SKeith Busch goto bad_sgl; 70257dacad5SJay Sternberg sg = sg_next(sg); 70357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70557dacad5SJay Sternberg } 706a7a7cbe3SChaitanya Kulkarni done: 707a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 708a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70986eea289SKeith Busch return BLK_STS_OK; 710*fa073216SChristoph Hellwig free_prps: 711*fa073216SChristoph Hellwig nvme_free_prps(dev, req); 712*fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 71386eea289SKeith Busch bad_sgl: 714d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 715d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 716d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71786eea289SKeith Busch return BLK_STS_IOERR; 71857dacad5SJay Sternberg } 71957dacad5SJay Sternberg 720a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 721a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 722a7a7cbe3SChaitanya Kulkarni { 723a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 724a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 725a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 726a7a7cbe3SChaitanya Kulkarni } 727a7a7cbe3SChaitanya Kulkarni 728a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 729a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 730a7a7cbe3SChaitanya Kulkarni { 731a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 732a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 733a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 734a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 735a7a7cbe3SChaitanya Kulkarni } else { 736a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 737a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 738a7a7cbe3SChaitanya Kulkarni } 739a7a7cbe3SChaitanya Kulkarni } 740a7a7cbe3SChaitanya Kulkarni 741a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 742b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 743a7a7cbe3SChaitanya Kulkarni { 744a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 745a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 746a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 747a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 748a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 749b0f2853bSChristoph Hellwig int i = 0; 750a7a7cbe3SChaitanya Kulkarni 751a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 752a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 753a7a7cbe3SChaitanya Kulkarni 754b0f2853bSChristoph Hellwig if (entries == 1) { 755a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 756a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 757a7a7cbe3SChaitanya Kulkarni } 758a7a7cbe3SChaitanya Kulkarni 759a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 760a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 761a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 762a7a7cbe3SChaitanya Kulkarni } else { 763a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 764a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 765a7a7cbe3SChaitanya Kulkarni } 766a7a7cbe3SChaitanya Kulkarni 767a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 768a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 769a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 770a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 771a7a7cbe3SChaitanya Kulkarni } 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 774a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 775a7a7cbe3SChaitanya Kulkarni 776a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 777a7a7cbe3SChaitanya Kulkarni 778a7a7cbe3SChaitanya Kulkarni do { 779a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 780a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 781a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 782a7a7cbe3SChaitanya Kulkarni 783a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 784a7a7cbe3SChaitanya Kulkarni if (!sg_list) 785*fa073216SChristoph Hellwig goto free_sgls; 786a7a7cbe3SChaitanya Kulkarni 787a7a7cbe3SChaitanya Kulkarni i = 0; 788a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 789a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 790a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 791a7a7cbe3SChaitanya Kulkarni } 792a7a7cbe3SChaitanya Kulkarni 793a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 794a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 795b0f2853bSChristoph Hellwig } while (--entries > 0); 796a7a7cbe3SChaitanya Kulkarni 797a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 798*fa073216SChristoph Hellwig free_sgls: 799*fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 800*fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 801a7a7cbe3SChaitanya Kulkarni } 802a7a7cbe3SChaitanya Kulkarni 803dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 804dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 805dff824b2SChristoph Hellwig struct bio_vec *bv) 806dff824b2SChristoph Hellwig { 807dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8086c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8096c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 810dff824b2SChristoph Hellwig 811dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 812dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 813dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 814dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 815dff824b2SChristoph Hellwig 816dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 817dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 818dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 819359c1f88SBaolin Wang return BLK_STS_OK; 820dff824b2SChristoph Hellwig } 821dff824b2SChristoph Hellwig 82229791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82329791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82429791057SChristoph Hellwig struct bio_vec *bv) 82529791057SChristoph Hellwig { 82629791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82729791057SChristoph Hellwig 82829791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82929791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 83029791057SChristoph Hellwig return BLK_STS_RESOURCE; 83129791057SChristoph Hellwig iod->dma_len = bv->bv_len; 83229791057SChristoph Hellwig 833049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 83429791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83529791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83629791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 837359c1f88SBaolin Wang return BLK_STS_OK; 83829791057SChristoph Hellwig } 83929791057SChristoph Hellwig 840fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 841b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84257dacad5SJay Sternberg { 843f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84470479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 845b0f2853bSChristoph Hellwig int nr_mapped; 84657dacad5SJay Sternberg 847dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 848dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 849dff824b2SChristoph Hellwig 850dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8516c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 852dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 853dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85429791057SChristoph Hellwig 85529791057SChristoph Hellwig if (iod->nvmeq->qid && 85629791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 85729791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85829791057SChristoph Hellwig &cmnd->rw, &bv); 859dff824b2SChristoph Hellwig } 860dff824b2SChristoph Hellwig } 861dff824b2SChristoph Hellwig 862dff824b2SChristoph Hellwig iod->dma_len = 0; 8639b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8649b048119SChristoph Hellwig if (!iod->sg) 8659b048119SChristoph Hellwig return BLK_STS_RESOURCE; 866f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86770479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 868ba1ca37eSChristoph Hellwig if (!iod->nents) 869*fa073216SChristoph Hellwig goto out_free_sg; 870ba1ca37eSChristoph Hellwig 871e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8722b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8732b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 874e0596ab2SLogan Gunthorpe else 875e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87670479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 877b0f2853bSChristoph Hellwig if (!nr_mapped) 878*fa073216SChristoph Hellwig goto out_free_sg; 879ba1ca37eSChristoph Hellwig 88070479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 881955b1b5aSMinwoo Im if (iod->use_sgl) 882b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 883a7a7cbe3SChaitanya Kulkarni else 884a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8854aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 886*fa073216SChristoph Hellwig goto out_unmap_sg; 887*fa073216SChristoph Hellwig return BLK_STS_OK; 888*fa073216SChristoph Hellwig 889*fa073216SChristoph Hellwig out_unmap_sg: 890*fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 891*fa073216SChristoph Hellwig out_free_sg: 892*fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 893ba1ca37eSChristoph Hellwig return ret; 89457dacad5SJay Sternberg } 89557dacad5SJay Sternberg 8964aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8974aedb705SChristoph Hellwig struct nvme_command *cmnd) 8984aedb705SChristoph Hellwig { 8994aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9004aedb705SChristoph Hellwig 9014aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 9024aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9034aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9044aedb705SChristoph Hellwig return BLK_STS_IOERR; 9054aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 906359c1f88SBaolin Wang return BLK_STS_OK; 9074aedb705SChristoph Hellwig } 9084aedb705SChristoph Hellwig 90957dacad5SJay Sternberg /* 91057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91157dacad5SJay Sternberg */ 912fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91457dacad5SJay Sternberg { 91557dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 91757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 91857dacad5SJay Sternberg struct request *req = bd->rq; 9199b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 920ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 921ebe6d874SChristoph Hellwig blk_status_t ret; 92257dacad5SJay Sternberg 9239b048119SChristoph Hellwig iod->aborted = 0; 9249b048119SChristoph Hellwig iod->npages = -1; 9259b048119SChristoph Hellwig iod->nents = 0; 9269b048119SChristoph Hellwig 927d1f06f4aSJens Axboe /* 928d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 929d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 930d1f06f4aSJens Axboe */ 9314e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 932d1f06f4aSJens Axboe return BLK_STS_IOERR; 933d1f06f4aSJens Axboe 934f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 935fc17b653SChristoph Hellwig if (ret) 936f4800d6dSChristoph Hellwig return ret; 93757dacad5SJay Sternberg 938fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 939b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 940fc17b653SChristoph Hellwig if (ret) 9419b048119SChristoph Hellwig goto out_free_cmd; 942fc17b653SChristoph Hellwig } 943ba1ca37eSChristoph Hellwig 9444aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9454aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9464aedb705SChristoph Hellwig if (ret) 9474aedb705SChristoph Hellwig goto out_unmap_data; 9484aedb705SChristoph Hellwig } 9494aedb705SChristoph Hellwig 950aae239e1SChristoph Hellwig blk_mq_start_request(req); 95104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 952fc17b653SChristoph Hellwig return BLK_STS_OK; 9534aedb705SChristoph Hellwig out_unmap_data: 9544aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 955f9d03f96SChristoph Hellwig out_free_cmd: 956f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 957ba1ca37eSChristoph Hellwig return ret; 95857dacad5SJay Sternberg } 95957dacad5SJay Sternberg 96077f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 961eee417b0SChristoph Hellwig { 962f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9634aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 964eee417b0SChristoph Hellwig 9654aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9664aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9674aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 968b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9694aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 97077f02a7aSChristoph Hellwig nvme_complete_rq(req); 97157dacad5SJay Sternberg } 97257dacad5SJay Sternberg 973d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 974750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 975d783e0bdSMarta Rybczynska { 97674943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 97774943d45SKeith Busch 97874943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 979d783e0bdSMarta Rybczynska } 980d783e0bdSMarta Rybczynska 981eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 98257dacad5SJay Sternberg { 983eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 98457dacad5SJay Sternberg 985eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 986eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 987eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 988eb281c82SSagi Grimberg } 989adf68f21SChristoph Hellwig 990cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 991cfa27356SChristoph Hellwig { 992cfa27356SChristoph Hellwig if (!nvmeq->qid) 993cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 994cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 995cfa27356SChristoph Hellwig } 996cfa27356SChristoph Hellwig 9975cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 99857dacad5SJay Sternberg { 99974943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 100062df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 100157dacad5SJay Sternberg struct request *req; 1002adf68f21SChristoph Hellwig 1003adf68f21SChristoph Hellwig /* 1004adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1005adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1006adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1007adf68f21SChristoph Hellwig * for them but rather special case them here. 1008adf68f21SChristoph Hellwig */ 100962df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10107bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 101183a12fb7SSagi Grimberg cqe->status, &cqe->result); 1012a0fa9647SJens Axboe return; 101357dacad5SJay Sternberg } 101457dacad5SJay Sternberg 101562df8016SLalithambika Krishnakumar req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id); 101650b7c243SXianting Tian if (unlikely(!req)) { 101750b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 101850b7c243SXianting Tian "invalid id %d completed on queue %d\n", 101962df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 102050b7c243SXianting Tian return; 102150b7c243SXianting Tian } 102250b7c243SXianting Tian 1023604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 10242eb81a33SChristoph Hellwig if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 1025ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 102683a12fb7SSagi Grimberg } 102757dacad5SJay Sternberg 10285cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10295cb525c8SJens Axboe { 1030a8de6639SAlexey Dobriyan u16 tmp = nvmeq->cq_head + 1; 1031a8de6639SAlexey Dobriyan 1032a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1033920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1034e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1035a8de6639SAlexey Dobriyan } else { 1036a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1037920d13a8SSagi Grimberg } 1038a0fa9647SJens Axboe } 1039a0fa9647SJens Axboe 1040324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 1041a0fa9647SJens Axboe { 10421052b8acSJens Axboe int found = 0; 104383a12fb7SSagi Grimberg 10441052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10451052b8acSJens Axboe found++; 1046b69e2ef2SKeith Busch /* 1047b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1048b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1049b69e2ef2SKeith Busch */ 1050b69e2ef2SKeith Busch dma_rmb(); 1051324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 10525cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 105357dacad5SJay Sternberg } 105457dacad5SJay Sternberg 1055324b494cSKeith Busch if (found) 1056eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10575cb525c8SJens Axboe return found; 105857dacad5SJay Sternberg } 105957dacad5SJay Sternberg 106057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 106157dacad5SJay Sternberg { 106257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 106368fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10645cb525c8SJens Axboe 10653a7afd8eSChristoph Hellwig /* 10663a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10673a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10683a7afd8eSChristoph Hellwig */ 10693a7afd8eSChristoph Hellwig rmb(); 1070324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 1071324b494cSKeith Busch ret = IRQ_HANDLED; 10723a7afd8eSChristoph Hellwig wmb(); 10735cb525c8SJens Axboe 107468fa9dbeSJens Axboe return ret; 107557dacad5SJay Sternberg } 107657dacad5SJay Sternberg 107757dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 107857dacad5SJay Sternberg { 107957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10804e523547SBaolin Wang 1081750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 108257dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1083d783e0bdSMarta Rybczynska return IRQ_NONE; 108457dacad5SJay Sternberg } 108557dacad5SJay Sternberg 10860b2a8a9fSChristoph Hellwig /* 1087fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10880b2a8a9fSChristoph Hellwig * Can be called from any context. 10890b2a8a9fSChristoph Hellwig */ 1090fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1091a0fa9647SJens Axboe { 10923a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1093a0fa9647SJens Axboe 1094fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1095fa059b85SKeith Busch 10963a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1097fa059b85SKeith Busch nvme_process_cq(nvmeq); 10983a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 109991a509f8SChristoph Hellwig } 1100442e19b7SSagi Grimberg 11019743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 11027776db1cSKeith Busch { 11037776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1104dabcefabSJens Axboe bool found; 1105dabcefabSJens Axboe 1106dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1107dabcefabSJens Axboe return 0; 1108dabcefabSJens Axboe 11093a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1110324b494cSKeith Busch found = nvme_process_cq(nvmeq); 11113a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1112dabcefabSJens Axboe 1113dabcefabSJens Axboe return found; 1114dabcefabSJens Axboe } 1115dabcefabSJens Axboe 1116ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 111757dacad5SJay Sternberg { 1118f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1119147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 112057dacad5SJay Sternberg struct nvme_command c; 112157dacad5SJay Sternberg 112257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112357dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1124ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 112504f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 112657dacad5SJay Sternberg } 112757dacad5SJay Sternberg 112857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 112957dacad5SJay Sternberg { 113057dacad5SJay Sternberg struct nvme_command c; 113157dacad5SJay Sternberg 113257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 113457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 113557dacad5SJay Sternberg 11361c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113757dacad5SJay Sternberg } 113857dacad5SJay Sternberg 113957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1140a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 114157dacad5SJay Sternberg { 114257dacad5SJay Sternberg struct nvme_command c; 11434b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11444b04cc6aSJens Axboe 11457c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11464b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 114757dacad5SJay Sternberg 114857dacad5SJay Sternberg /* 114916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 115057dacad5SJay Sternberg * is attached to the request. 115157dacad5SJay Sternberg */ 115257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 115457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 115557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 115657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 115757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1158a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 115957dacad5SJay Sternberg 11601c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116157dacad5SJay Sternberg } 116257dacad5SJay Sternberg 116357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 116457dacad5SJay Sternberg struct nvme_queue *nvmeq) 116557dacad5SJay Sternberg { 11669abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 116757dacad5SJay Sternberg struct nvme_command c; 116881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 116957dacad5SJay Sternberg 117057dacad5SJay Sternberg /* 11719abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11729abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11739abd68efSJens Axboe * URGENT. 11749abd68efSJens Axboe */ 11759abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11769abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11779abd68efSJens Axboe 11789abd68efSJens Axboe /* 117916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 118057dacad5SJay Sternberg * is attached to the request. 118157dacad5SJay Sternberg */ 118257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 118357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 118457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 118557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 118657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 118757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 118857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 118957dacad5SJay Sternberg 11901c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 119157dacad5SJay Sternberg } 119257dacad5SJay Sternberg 119357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 119457dacad5SJay Sternberg { 119557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 119657dacad5SJay Sternberg } 119757dacad5SJay Sternberg 119857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 119957dacad5SJay Sternberg { 120057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 120157dacad5SJay Sternberg } 120257dacad5SJay Sternberg 12032a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 120457dacad5SJay Sternberg { 1205f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1206f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 120757dacad5SJay Sternberg 120827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 120927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1210e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1211e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 121257dacad5SJay Sternberg } 121357dacad5SJay Sternberg 1214b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1215b2a0eb1aSKeith Busch { 1216b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1217b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1218b2a0eb1aSKeith Busch */ 1219b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1220b2a0eb1aSKeith Busch 1221ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1222ad70062cSJianchao Wang switch (dev->ctrl.state) { 1223ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1224ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1225b2a0eb1aSKeith Busch return false; 1226ad70062cSJianchao Wang default: 1227ad70062cSJianchao Wang break; 1228ad70062cSJianchao Wang } 1229b2a0eb1aSKeith Busch 1230b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1231b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1232b2a0eb1aSKeith Busch */ 1233b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1234b2a0eb1aSKeith Busch return false; 1235b2a0eb1aSKeith Busch 1236b2a0eb1aSKeith Busch return true; 1237b2a0eb1aSKeith Busch } 1238b2a0eb1aSKeith Busch 1239b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1240b2a0eb1aSKeith Busch { 1241b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1242b2a0eb1aSKeith Busch u16 pci_status; 1243b2a0eb1aSKeith Busch int result; 1244b2a0eb1aSKeith Busch 1245b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1246b2a0eb1aSKeith Busch &pci_status); 1247b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1248b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1249b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1250b2a0eb1aSKeith Busch csts, pci_status); 1251b2a0eb1aSKeith Busch else 1252b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1253b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1254b2a0eb1aSKeith Busch csts, result); 1255b2a0eb1aSKeith Busch } 1256b2a0eb1aSKeith Busch 125731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 125857dacad5SJay Sternberg { 1259f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1260f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 126157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 126257dacad5SJay Sternberg struct request *abort_req; 126357dacad5SJay Sternberg struct nvme_command cmd; 1264b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1265b2a0eb1aSKeith Busch 1266651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1267651438bbSWen Xiong * the recovery mechanism will surely fail. 1268651438bbSWen Xiong */ 1269651438bbSWen Xiong mb(); 1270651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1271651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1272651438bbSWen Xiong 1273b2a0eb1aSKeith Busch /* 1274b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1275b2a0eb1aSKeith Busch */ 1276b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1277b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1278b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1279d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1280db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1281b2a0eb1aSKeith Busch } 128257dacad5SJay Sternberg 128331c7c7d2SChristoph Hellwig /* 12847776db1cSKeith Busch * Did we miss an interrupt? 12857776db1cSKeith Busch */ 1286fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1287fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1288fa059b85SKeith Busch else 1289bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1290fa059b85SKeith Busch 1291bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12927776db1cSKeith Busch dev_warn(dev->ctrl.device, 12937776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12947776db1cSKeith Busch req->tag, nvmeq->qid); 1295db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12967776db1cSKeith Busch } 12977776db1cSKeith Busch 12987776db1cSKeith Busch /* 1299fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1300fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1301fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1302db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1303fd634f41SChristoph Hellwig */ 13044244140dSKeith Busch switch (dev->ctrl.state) { 13054244140dSKeith Busch case NVME_CTRL_CONNECTING: 13062036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1307df561f66SGustavo A. R. Silva fallthrough; 13082036f726SKeith Busch case NVME_CTRL_DELETING: 1309b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1310fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1311fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 131227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13137ad92f65STong Zhang nvme_dev_disable(dev, true); 1314db8c48e4SChristoph Hellwig return BLK_EH_DONE; 131539a9dd81SKeith Busch case NVME_CTRL_RESETTING: 131639a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13174244140dSKeith Busch default: 13184244140dSKeith Busch break; 1319fd634f41SChristoph Hellwig } 1320fd634f41SChristoph Hellwig 1321fd634f41SChristoph Hellwig /* 1322e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1323e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1324e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 132531c7c7d2SChristoph Hellwig */ 1326f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13271b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 132857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 132957dacad5SJay Sternberg req->tag, nvmeq->qid); 13307ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1331a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1332d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1333e1569a16SKeith Busch 1334db8c48e4SChristoph Hellwig return BLK_EH_DONE; 133557dacad5SJay Sternberg } 133657dacad5SJay Sternberg 1337e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1338e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1339e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1340e7a2a87dSChristoph Hellwig } 13417bf7d778SKeith Busch iod->aborted = 1; 134257dacad5SJay Sternberg 134357dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 134457dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 134557dacad5SJay Sternberg cmd.abort.cid = req->tag; 134657dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 134757dacad5SJay Sternberg 13481b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13491b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 135057dacad5SJay Sternberg req->tag, nvmeq->qid); 1351e7a2a87dSChristoph Hellwig 1352e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 135339dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13546bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13556bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 135631c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 135757dacad5SJay Sternberg } 135857dacad5SJay Sternberg 1359e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1360e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 136157dacad5SJay Sternberg 136257dacad5SJay Sternberg /* 136357dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 136457dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 136557dacad5SJay Sternberg * as the device then is in a faulty state. 136657dacad5SJay Sternberg */ 136757dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 136857dacad5SJay Sternberg } 136957dacad5SJay Sternberg 137057dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 137157dacad5SJay Sternberg { 13728a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 137357dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 137463223078SChristoph Hellwig if (!nvmeq->sq_cmds) 137563223078SChristoph Hellwig return; 13760f238ff5SLogan Gunthorpe 137763223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 137888a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13798a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 138063223078SChristoph Hellwig } else { 13818a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 138263223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13830f238ff5SLogan Gunthorpe } 138457dacad5SJay Sternberg } 138557dacad5SJay Sternberg 138657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 138757dacad5SJay Sternberg { 138857dacad5SJay Sternberg int i; 138957dacad5SJay Sternberg 1390d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1391d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1392147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 139357dacad5SJay Sternberg } 139457dacad5SJay Sternberg } 139557dacad5SJay Sternberg 139657dacad5SJay Sternberg /** 139757dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 139840581d1aSBart Van Assche * @nvmeq: queue to suspend 139957dacad5SJay Sternberg */ 140057dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 140157dacad5SJay Sternberg { 14024e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 140357dacad5SJay Sternberg return 1; 140457dacad5SJay Sternberg 14054e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1406d1f06f4aSJens Axboe mb(); 140757dacad5SJay Sternberg 14084e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14091c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1410c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14117c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14124e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 141357dacad5SJay Sternberg return 0; 141457dacad5SJay Sternberg } 141557dacad5SJay Sternberg 14168fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14178fae268bSKeith Busch { 14188fae268bSKeith Busch int i; 14198fae268bSKeith Busch 14208fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14218fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14228fae268bSKeith Busch } 14238fae268bSKeith Busch 1424a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 142557dacad5SJay Sternberg { 1426147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 142757dacad5SJay Sternberg 1428a5cdb68cSKeith Busch if (shutdown) 1429a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1430a5cdb68cSKeith Busch else 1431b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 143257dacad5SJay Sternberg 1433bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 143457dacad5SJay Sternberg } 143557dacad5SJay Sternberg 1436fa46c6fbSKeith Busch /* 1437fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14389210c075SDongli Zhang * that can check this device's completion queues have synced, except 14399210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14409210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1441fa46c6fbSKeith Busch */ 1442fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1443fa46c6fbSKeith Busch { 1444fa46c6fbSKeith Busch int i; 1445fa46c6fbSKeith Busch 14469210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14479210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1448324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 14499210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14509210c075SDongli Zhang } 1451fa46c6fbSKeith Busch } 1452fa46c6fbSKeith Busch 145357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 145457dacad5SJay Sternberg int entry_size) 145557dacad5SJay Sternberg { 145657dacad5SJay Sternberg int q_depth = dev->q_depth; 14575fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14586c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 145957dacad5SJay Sternberg 146057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 146157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14624e523547SBaolin Wang 14636c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 146457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 146557dacad5SJay Sternberg 146657dacad5SJay Sternberg /* 146757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 146857dacad5SJay Sternberg * would be better to map queues in system memory with the 146957dacad5SJay Sternberg * original depth 147057dacad5SJay Sternberg */ 147157dacad5SJay Sternberg if (q_depth < 64) 147257dacad5SJay Sternberg return -ENOMEM; 147357dacad5SJay Sternberg } 147457dacad5SJay Sternberg 147557dacad5SJay Sternberg return q_depth; 147657dacad5SJay Sternberg } 147757dacad5SJay Sternberg 147857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14798a1d09a6SBenjamin Herrenschmidt int qid) 148057dacad5SJay Sternberg { 14810f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1482815c6704SKeith Busch 14830f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14848a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1485bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14860f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14870f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 148863223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 148963223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 149063223078SChristoph Hellwig return 0; 149163223078SChristoph Hellwig } 1492bfac8e9fSAlan Mikhak 14938a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1494bfac8e9fSAlan Mikhak } 14950f238ff5SLogan Gunthorpe } 14960f238ff5SLogan Gunthorpe 14978a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 149857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 149957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 150057dacad5SJay Sternberg return -ENOMEM; 150157dacad5SJay Sternberg return 0; 150257dacad5SJay Sternberg } 150357dacad5SJay Sternberg 1504a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 150557dacad5SJay Sternberg { 1506147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 150757dacad5SJay Sternberg 150862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 150962314e40SKeith Busch return 0; 151057dacad5SJay Sternberg 1511c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15128a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15138a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 151457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 151557dacad5SJay Sternberg if (!nvmeq->cqes) 151657dacad5SJay Sternberg goto free_nvmeq; 151757dacad5SJay Sternberg 15188a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 151957dacad5SJay Sternberg goto free_cqdma; 152057dacad5SJay Sternberg 152157dacad5SJay Sternberg nvmeq->dev = dev; 15221ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15233a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 152457dacad5SJay Sternberg nvmeq->cq_head = 0; 152557dacad5SJay Sternberg nvmeq->cq_phase = 1; 152657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 152757dacad5SJay Sternberg nvmeq->qid = qid; 1528d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 152957dacad5SJay Sternberg 1530147b27e4SSagi Grimberg return 0; 153157dacad5SJay Sternberg 153257dacad5SJay Sternberg free_cqdma: 15338a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 153457dacad5SJay Sternberg nvmeq->cq_dma_addr); 153557dacad5SJay Sternberg free_nvmeq: 1536147b27e4SSagi Grimberg return -ENOMEM; 153757dacad5SJay Sternberg } 153857dacad5SJay Sternberg 1539dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 154057dacad5SJay Sternberg { 15410ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15420ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15430ff199cbSChristoph Hellwig 15440ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15450ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15460ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15470ff199cbSChristoph Hellwig } else { 15480ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15490ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15500ff199cbSChristoph Hellwig } 155157dacad5SJay Sternberg } 155257dacad5SJay Sternberg 155357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 155457dacad5SJay Sternberg { 155557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 155657dacad5SJay Sternberg 155757dacad5SJay Sternberg nvmeq->sq_tail = 0; 155838210800SKeith Busch nvmeq->last_sq_tail = 0; 155957dacad5SJay Sternberg nvmeq->cq_head = 0; 156057dacad5SJay Sternberg nvmeq->cq_phase = 1; 156157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15628a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1563f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 156457dacad5SJay Sternberg dev->online_queues++; 15653a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 156657dacad5SJay Sternberg } 156757dacad5SJay Sternberg 15684b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 156957dacad5SJay Sternberg { 157057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 157157dacad5SJay Sternberg int result; 15727c349ddeSKeith Busch u16 vector = 0; 157357dacad5SJay Sternberg 1574d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1575d1ed6aa1SChristoph Hellwig 157622b55601SKeith Busch /* 157722b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 157822b55601SKeith Busch * has only one vector available. 157922b55601SKeith Busch */ 15804b04cc6aSJens Axboe if (!polled) 1581a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15824b04cc6aSJens Axboe else 15837c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15844b04cc6aSJens Axboe 1585a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1586ded45505SKeith Busch if (result) 1587ded45505SKeith Busch return result; 158857dacad5SJay Sternberg 158957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 159057dacad5SJay Sternberg if (result < 0) 1591ded45505SKeith Busch return result; 1592c80b36cdSEdmund Nadolski if (result) 159357dacad5SJay Sternberg goto release_cq; 159457dacad5SJay Sternberg 1595a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1596161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15974b04cc6aSJens Axboe 15987c349ddeSKeith Busch if (!polled) { 1599dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 160057dacad5SJay Sternberg if (result < 0) 160157dacad5SJay Sternberg goto release_sq; 16024b04cc6aSJens Axboe } 160357dacad5SJay Sternberg 16044e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 160557dacad5SJay Sternberg return result; 160657dacad5SJay Sternberg 160757dacad5SJay Sternberg release_sq: 1608f25a2dfcSJianchao Wang dev->online_queues--; 160957dacad5SJay Sternberg adapter_delete_sq(dev, qid); 161057dacad5SJay Sternberg release_cq: 161157dacad5SJay Sternberg adapter_delete_cq(dev, qid); 161257dacad5SJay Sternberg return result; 161357dacad5SJay Sternberg } 161457dacad5SJay Sternberg 1615f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 161657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 161777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 161857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 16190350815aSChristoph Hellwig .init_request = nvme_init_request, 162057dacad5SJay Sternberg .timeout = nvme_timeout, 162157dacad5SJay Sternberg }; 162257dacad5SJay Sternberg 1623f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1624376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1625376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1626376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1627376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1628376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1629376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1630376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1631c6d962aeSChristoph Hellwig .poll = nvme_poll, 1632dabcefabSJens Axboe }; 1633dabcefabSJens Axboe 163457dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 163557dacad5SJay Sternberg { 16361c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 163769d9a99cSKeith Busch /* 163869d9a99cSKeith Busch * If the controller was reset during removal, it's possible 163969d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 164069d9a99cSKeith Busch * queue to flush these to completion. 164169d9a99cSKeith Busch */ 1642c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16431c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 164457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 164557dacad5SJay Sternberg } 164657dacad5SJay Sternberg } 164757dacad5SJay Sternberg 164857dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 164957dacad5SJay Sternberg { 16501c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 165157dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 165257dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1653e3e9d50cSKeith Busch 165438dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1655dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1656d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1657d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1658d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 165957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 166057dacad5SJay Sternberg 166157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 166257dacad5SJay Sternberg return -ENOMEM; 166334b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 166457dacad5SJay Sternberg 16651c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16661c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 166757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 166857dacad5SJay Sternberg return -ENOMEM; 166957dacad5SJay Sternberg } 16701c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 167157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16721c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 167357dacad5SJay Sternberg return -ENODEV; 167457dacad5SJay Sternberg } 167557dacad5SJay Sternberg } else 1676c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 167757dacad5SJay Sternberg 167857dacad5SJay Sternberg return 0; 167957dacad5SJay Sternberg } 168057dacad5SJay Sternberg 168197f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 168297f6ef64SXu Yu { 168397f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 168497f6ef64SXu Yu } 168597f6ef64SXu Yu 168697f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 168797f6ef64SXu Yu { 168897f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 168997f6ef64SXu Yu 169097f6ef64SXu Yu if (size <= dev->bar_mapped_size) 169197f6ef64SXu Yu return 0; 169297f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 169397f6ef64SXu Yu return -ENOMEM; 169497f6ef64SXu Yu if (dev->bar) 169597f6ef64SXu Yu iounmap(dev->bar); 169697f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 169797f6ef64SXu Yu if (!dev->bar) { 169897f6ef64SXu Yu dev->bar_mapped_size = 0; 169997f6ef64SXu Yu return -ENOMEM; 170097f6ef64SXu Yu } 170197f6ef64SXu Yu dev->bar_mapped_size = size; 170297f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 170397f6ef64SXu Yu 170497f6ef64SXu Yu return 0; 170597f6ef64SXu Yu } 170697f6ef64SXu Yu 170701ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 170857dacad5SJay Sternberg { 170957dacad5SJay Sternberg int result; 171057dacad5SJay Sternberg u32 aqa; 171157dacad5SJay Sternberg struct nvme_queue *nvmeq; 171257dacad5SJay Sternberg 171397f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 171497f6ef64SXu Yu if (result < 0) 171597f6ef64SXu Yu return result; 171697f6ef64SXu Yu 17178ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 171820d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 171957dacad5SJay Sternberg 17207a67cbeaSChristoph Hellwig if (dev->subsystem && 17217a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17227a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 172357dacad5SJay Sternberg 1724b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 172557dacad5SJay Sternberg if (result < 0) 172657dacad5SJay Sternberg return result; 172757dacad5SJay Sternberg 1728a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1729147b27e4SSagi Grimberg if (result) 1730147b27e4SSagi Grimberg return result; 173157dacad5SJay Sternberg 1732635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1733635333e4SMax Gurtovoy 1734147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 173557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 173657dacad5SJay Sternberg aqa |= aqa << 16; 173757dacad5SJay Sternberg 17387a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17397a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17407a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 174157dacad5SJay Sternberg 1742c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 174357dacad5SJay Sternberg if (result) 1744d4875622SKeith Busch return result; 174557dacad5SJay Sternberg 174657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1747161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1748dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 174957dacad5SJay Sternberg if (result) { 17507c349ddeSKeith Busch dev->online_queues--; 1751d4875622SKeith Busch return result; 175257dacad5SJay Sternberg } 175357dacad5SJay Sternberg 17544e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 175557dacad5SJay Sternberg return result; 175657dacad5SJay Sternberg } 175757dacad5SJay Sternberg 1758749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 175957dacad5SJay Sternberg { 17604b04cc6aSJens Axboe unsigned i, max, rw_queues; 1761749941f2SChristoph Hellwig int ret = 0; 176257dacad5SJay Sternberg 1763d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1764a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1765749941f2SChristoph Hellwig ret = -ENOMEM; 176657dacad5SJay Sternberg break; 1767749941f2SChristoph Hellwig } 1768749941f2SChristoph Hellwig } 176957dacad5SJay Sternberg 1770d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1771e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1772e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1773e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17744b04cc6aSJens Axboe } else { 17754b04cc6aSJens Axboe rw_queues = max; 17764b04cc6aSJens Axboe } 17774b04cc6aSJens Axboe 1778949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17794b04cc6aSJens Axboe bool polled = i > rw_queues; 17804b04cc6aSJens Axboe 17814b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1782d4875622SKeith Busch if (ret) 178357dacad5SJay Sternberg break; 178457dacad5SJay Sternberg } 178557dacad5SJay Sternberg 1786749941f2SChristoph Hellwig /* 1787749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17888adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17898adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1790749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1791749941f2SChristoph Hellwig */ 1792749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 179357dacad5SJay Sternberg } 179457dacad5SJay Sternberg 1795202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1796202021c1SStephen Bates struct device_attribute *attr, 1797202021c1SStephen Bates char *buf) 1798202021c1SStephen Bates { 1799202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1800202021c1SStephen Bates 1801c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1802202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1803202021c1SStephen Bates } 1804202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1805202021c1SStephen Bates 180688de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 180757dacad5SJay Sternberg { 180888de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 180988de4598SChristoph Hellwig 181088de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 181188de4598SChristoph Hellwig } 181288de4598SChristoph Hellwig 181388de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 181488de4598SChristoph Hellwig { 181588de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 181688de4598SChristoph Hellwig } 181788de4598SChristoph Hellwig 1818f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 181957dacad5SJay Sternberg { 182088de4598SChristoph Hellwig u64 size, offset; 182157dacad5SJay Sternberg resource_size_t bar_size; 182257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18238969f1f8SChristoph Hellwig int bar; 182457dacad5SJay Sternberg 18259fe5c59fSKeith Busch if (dev->cmb_size) 18269fe5c59fSKeith Busch return; 18279fe5c59fSKeith Busch 182820d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 182920d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 183020d3bb92SKlaus Jensen 18317a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1832f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1833f65efd6dSChristoph Hellwig return; 1834202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 183557dacad5SJay Sternberg 183688de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 183788de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18388969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18398969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 184057dacad5SJay Sternberg 184157dacad5SJay Sternberg if (offset > bar_size) 1842f65efd6dSChristoph Hellwig return; 184357dacad5SJay Sternberg 184457dacad5SJay Sternberg /* 184520d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 184620d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 184720d3bb92SKlaus Jensen */ 184820d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 184920d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 185020d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 185120d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 185220d3bb92SKlaus Jensen } 185320d3bb92SKlaus Jensen 185420d3bb92SKlaus Jensen /* 185557dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 185657dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 185757dacad5SJay Sternberg * the reported size of the BAR 185857dacad5SJay Sternberg */ 185957dacad5SJay Sternberg if (size > bar_size - offset) 186057dacad5SJay Sternberg size = bar_size - offset; 186157dacad5SJay Sternberg 18620f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18630f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18640f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1865f65efd6dSChristoph Hellwig return; 18660f238ff5SLogan Gunthorpe } 18670f238ff5SLogan Gunthorpe 186857dacad5SJay Sternberg dev->cmb_size = size; 18690f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18700f238ff5SLogan Gunthorpe 18710f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18720f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18730f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1874f65efd6dSChristoph Hellwig 1875f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1876f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1877f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1878f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 187957dacad5SJay Sternberg } 188057dacad5SJay Sternberg 188157dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 188257dacad5SJay Sternberg { 18830f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1884f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1885f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18860f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1887f63572dfSJon Derrick } 188857dacad5SJay Sternberg } 188957dacad5SJay Sternberg 189087ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 189157dacad5SJay Sternberg { 18926c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18934033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 189487ad72a5SChristoph Hellwig struct nvme_command c; 189587ad72a5SChristoph Hellwig int ret; 189687ad72a5SChristoph Hellwig 189787ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 189887ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 189987ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 190087ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19016c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 190287ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 190387ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 190487ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 190587ad72a5SChristoph Hellwig 190687ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 190787ad72a5SChristoph Hellwig if (ret) { 190887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 190987ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 191087ad72a5SChristoph Hellwig ret, bits); 191187ad72a5SChristoph Hellwig } 191287ad72a5SChristoph Hellwig return ret; 191387ad72a5SChristoph Hellwig } 191487ad72a5SChristoph Hellwig 191587ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 191687ad72a5SChristoph Hellwig { 191787ad72a5SChristoph Hellwig int i; 191887ad72a5SChristoph Hellwig 191987ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 192087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19216c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 192287ad72a5SChristoph Hellwig 1923cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1924cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1925cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192687ad72a5SChristoph Hellwig } 192787ad72a5SChristoph Hellwig 192887ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 192987ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19304033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19314033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19324033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 193387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19347e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 193587ad72a5SChristoph Hellwig } 193687ad72a5SChristoph Hellwig 193792dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 193892dc6895SChristoph Hellwig u32 chunk_size) 193987ad72a5SChristoph Hellwig { 194087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 194192dc6895SChristoph Hellwig u32 max_entries, len; 19424033f35dSChristoph Hellwig dma_addr_t descs_dma; 19432ee0e4edSDan Carpenter int i = 0; 194487ad72a5SChristoph Hellwig void **bufs; 19456fbcde66SMinwoo Im u64 size, tmp; 194687ad72a5SChristoph Hellwig 194787ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 194887ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 194987ad72a5SChristoph Hellwig max_entries = tmp; 1950044a9df1SChristoph Hellwig 1951044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1952044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1953044a9df1SChristoph Hellwig 1954750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19554033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 195687ad72a5SChristoph Hellwig if (!descs) 195787ad72a5SChristoph Hellwig goto out; 195887ad72a5SChristoph Hellwig 195987ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 196087ad72a5SChristoph Hellwig if (!bufs) 196187ad72a5SChristoph Hellwig goto out_free_descs; 196287ad72a5SChristoph Hellwig 1963244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 196487ad72a5SChristoph Hellwig dma_addr_t dma_addr; 196587ad72a5SChristoph Hellwig 196650cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 196787ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 196887ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 196987ad72a5SChristoph Hellwig if (!bufs[i]) 197087ad72a5SChristoph Hellwig break; 197187ad72a5SChristoph Hellwig 197287ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19736c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 197487ad72a5SChristoph Hellwig i++; 197587ad72a5SChristoph Hellwig } 197687ad72a5SChristoph Hellwig 197792dc6895SChristoph Hellwig if (!size) 197887ad72a5SChristoph Hellwig goto out_free_bufs; 197987ad72a5SChristoph Hellwig 198087ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 198187ad72a5SChristoph Hellwig dev->host_mem_size = size; 198287ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19834033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 198487ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 198587ad72a5SChristoph Hellwig return 0; 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig out_free_bufs: 198887ad72a5SChristoph Hellwig while (--i >= 0) { 19896c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 199087ad72a5SChristoph Hellwig 1991cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1992cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1993cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199687ad72a5SChristoph Hellwig kfree(bufs); 199787ad72a5SChristoph Hellwig out_free_descs: 19984033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19994033f35dSChristoph Hellwig descs_dma); 200087ad72a5SChristoph Hellwig out: 200187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 200287ad72a5SChristoph Hellwig return -ENOMEM; 200387ad72a5SChristoph Hellwig } 200487ad72a5SChristoph Hellwig 200592dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 200692dc6895SChristoph Hellwig { 20079dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20089dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20099dc54a0dSChaitanya Kulkarni u64 chunk_size; 201092dc6895SChristoph Hellwig 201192dc6895SChristoph Hellwig /* start big and work our way down */ 20129dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 201392dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 201492dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 201592dc6895SChristoph Hellwig return 0; 201692dc6895SChristoph Hellwig nvme_free_host_mem(dev); 201792dc6895SChristoph Hellwig } 201892dc6895SChristoph Hellwig } 201992dc6895SChristoph Hellwig 202092dc6895SChristoph Hellwig return -ENOMEM; 202192dc6895SChristoph Hellwig } 202292dc6895SChristoph Hellwig 20239620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 202487ad72a5SChristoph Hellwig { 202587ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 202687ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 202787ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 202887ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20296fbcde66SMinwoo Im int ret; 203087ad72a5SChristoph Hellwig 203187ad72a5SChristoph Hellwig preferred = min(preferred, max); 203287ad72a5SChristoph Hellwig if (min > max) { 203387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 203487ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 203587ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 203687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20379620cfbaSChristoph Hellwig return 0; 203887ad72a5SChristoph Hellwig } 203987ad72a5SChristoph Hellwig 204087ad72a5SChristoph Hellwig /* 204187ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 204287ad72a5SChristoph Hellwig */ 204387ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 204487ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 204587ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 204687ad72a5SChristoph Hellwig else 204787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 204887ad72a5SChristoph Hellwig } 204987ad72a5SChristoph Hellwig 205087ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 205192dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 205292dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 205392dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20549620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 205587ad72a5SChristoph Hellwig } 205687ad72a5SChristoph Hellwig 205792dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 205892dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 205992dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 206092dc6895SChristoph Hellwig } 206192dc6895SChristoph Hellwig 20629620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20639620cfbaSChristoph Hellwig if (ret) 206487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20659620cfbaSChristoph Hellwig return ret; 206657dacad5SJay Sternberg } 206757dacad5SJay Sternberg 2068612b7286SMing Lei /* 2069612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2070612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2071612b7286SMing Lei */ 2072612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20733b6592f7SJens Axboe { 2074612b7286SMing Lei struct nvme_dev *dev = affd->priv; 20752a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2076c45b1fa2SMing Lei 20773b6592f7SJens Axboe /* 2078ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2079612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2080612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2081612b7286SMing Lei * 2082612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2083612b7286SMing Lei * write and read queues. 2084612b7286SMing Lei * 2085612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2086612b7286SMing Lei * queue. 20873b6592f7SJens Axboe */ 2088612b7286SMing Lei if (!nrirqs) { 2089612b7286SMing Lei nrirqs = 1; 2090612b7286SMing Lei nr_read_queues = 0; 20912a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2092612b7286SMing Lei nr_read_queues = 0; 20932a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2094612b7286SMing Lei nr_read_queues = 1; 20953b6592f7SJens Axboe } else { 20962a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 20973b6592f7SJens Axboe } 2098612b7286SMing Lei 2099612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2100612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2101612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2102612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2103612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 21043b6592f7SJens Axboe } 21053b6592f7SJens Axboe 21066451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 21073b6592f7SJens Axboe { 21083b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 21093b6592f7SJens Axboe struct irq_affinity affd = { 21103b6592f7SJens Axboe .pre_vectors = 1, 2111612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2112612b7286SMing Lei .priv = dev, 21133b6592f7SJens Axboe }; 211421cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 21156451fe73SJens Axboe 21166451fe73SJens Axboe /* 211721cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 211821cc2f3fSJeffle Xu * left over for non-polled I/O. 21196451fe73SJens Axboe */ 212021cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 212121cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 21223b6592f7SJens Axboe 212321cc2f3fSJeffle Xu /* 212421cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 212521cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 212621cc2f3fSJeffle Xu */ 2127612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2128612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 21293b6592f7SJens Axboe 213066341331SBenjamin Herrenschmidt /* 213121cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 213221cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 213321cc2f3fSJeffle Xu * vector. 213466341331SBenjamin Herrenschmidt */ 213566341331SBenjamin Herrenschmidt irq_queues = 1; 213621cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 213721cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2138612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 21393b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21403b6592f7SJens Axboe } 21413b6592f7SJens Axboe 21428fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 21438fae268bSKeith Busch { 21448fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 21458fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 21468fae268bSKeith Busch } 21478fae268bSKeith Busch 21482a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 21492a5bcfddSWeiping Zhang { 2150e3aef095SNiklas Schnelle /* 2151e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2152e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2153e3aef095SNiklas Schnelle */ 2154e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2155e3aef095SNiklas Schnelle return 1; 21562a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 21572a5bcfddSWeiping Zhang } 21582a5bcfddSWeiping Zhang 215957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 216057dacad5SJay Sternberg { 2161147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 216257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 21632a5bcfddSWeiping Zhang unsigned int nr_io_queues; 216497f6ef64SXu Yu unsigned long size; 21652a5bcfddSWeiping Zhang int result; 216657dacad5SJay Sternberg 21672a5bcfddSWeiping Zhang /* 21682a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 21692a5bcfddSWeiping Zhang * stable values to work with. 21702a5bcfddSWeiping Zhang */ 21712a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 21722a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2173d38e9f04SBenjamin Herrenschmidt 2174ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 21759a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21769a0be7abSChristoph Hellwig if (result < 0) 217757dacad5SJay Sternberg return result; 21789a0be7abSChristoph Hellwig 2179f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2180a5229050SKeith Busch return 0; 218157dacad5SJay Sternberg 21824e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21834e224106SChristoph Hellwig 21840f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 218557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 218657dacad5SJay Sternberg sizeof(struct nvme_command)); 218757dacad5SJay Sternberg if (result > 0) 218857dacad5SJay Sternberg dev->q_depth = result; 218957dacad5SJay Sternberg else 21900f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 219157dacad5SJay Sternberg } 219257dacad5SJay Sternberg 219357dacad5SJay Sternberg do { 219497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 219597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 219697f6ef64SXu Yu if (!result) 219757dacad5SJay Sternberg break; 219857dacad5SJay Sternberg if (!--nr_io_queues) 219957dacad5SJay Sternberg return -ENOMEM; 220057dacad5SJay Sternberg } while (1); 220157dacad5SJay Sternberg adminq->q_db = dev->dbs; 220257dacad5SJay Sternberg 22038fae268bSKeith Busch retry: 220457dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 22050ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 220657dacad5SJay Sternberg 220757dacad5SJay Sternberg /* 220857dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 220957dacad5SJay Sternberg * setting up the full range we need. 221057dacad5SJay Sternberg */ 2211dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 22123b6592f7SJens Axboe 22133b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 221422b55601SKeith Busch if (result <= 0) 2215dca51e78SChristoph Hellwig return -EIO; 22163b6592f7SJens Axboe 221722b55601SKeith Busch dev->num_vecs = result; 22184b04cc6aSJens Axboe result = max(result - 1, 1); 2219e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 222057dacad5SJay Sternberg 222157dacad5SJay Sternberg /* 222257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 222357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 222457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 222557dacad5SJay Sternberg * number of interrupts. 222657dacad5SJay Sternberg */ 2227dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 22287c349ddeSKeith Busch if (result) 2229d4875622SKeith Busch return result; 22304e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 22318fae268bSKeith Busch 22328fae268bSKeith Busch result = nvme_create_io_queues(dev); 22338fae268bSKeith Busch if (result || dev->online_queues < 2) 22348fae268bSKeith Busch return result; 22358fae268bSKeith Busch 22368fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 22378fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 22388fae268bSKeith Busch nvme_disable_io_queues(dev); 22398fae268bSKeith Busch nvme_suspend_io_queues(dev); 22408fae268bSKeith Busch goto retry; 22418fae268bSKeith Busch } 22428fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 22438fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 22448fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 22458fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 22468fae268bSKeith Busch return 0; 224757dacad5SJay Sternberg } 224857dacad5SJay Sternberg 22492a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2250db3cbfffSKeith Busch { 2251db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2252db3cbfffSKeith Busch 2253db3cbfffSKeith Busch blk_mq_free_request(req); 2254d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2255db3cbfffSKeith Busch } 2256db3cbfffSKeith Busch 22572a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2258db3cbfffSKeith Busch { 2259db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2260db3cbfffSKeith Busch 2261d1ed6aa1SChristoph Hellwig if (error) 2262d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2263db3cbfffSKeith Busch 2264db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2265db3cbfffSKeith Busch } 2266db3cbfffSKeith Busch 2267db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2268db3cbfffSKeith Busch { 2269db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2270db3cbfffSKeith Busch struct request *req; 2271db3cbfffSKeith Busch struct nvme_command cmd; 2272db3cbfffSKeith Busch 2273db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2274db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2275db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2276db3cbfffSKeith Busch 227739dfe844SChaitanya Kulkarni req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2278db3cbfffSKeith Busch if (IS_ERR(req)) 2279db3cbfffSKeith Busch return PTR_ERR(req); 2280db3cbfffSKeith Busch 2281db3cbfffSKeith Busch req->end_io_data = nvmeq; 2282db3cbfffSKeith Busch 2283d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2284db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2285db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2286db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2287db3cbfffSKeith Busch return 0; 2288db3cbfffSKeith Busch } 2289db3cbfffSKeith Busch 22908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2291db3cbfffSKeith Busch { 22925271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2293db3cbfffSKeith Busch unsigned long timeout; 2294db3cbfffSKeith Busch 2295db3cbfffSKeith Busch retry: 2296dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 22975271edd4SChristoph Hellwig while (nr_queues > 0) { 22985271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2299db3cbfffSKeith Busch break; 23005271edd4SChristoph Hellwig nr_queues--; 23015271edd4SChristoph Hellwig sent++; 23025271edd4SChristoph Hellwig } 2303d1ed6aa1SChristoph Hellwig while (sent) { 2304d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2305d1ed6aa1SChristoph Hellwig 2306d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 23075271edd4SChristoph Hellwig timeout); 2308db3cbfffSKeith Busch if (timeout == 0) 23095271edd4SChristoph Hellwig return false; 2310d1ed6aa1SChristoph Hellwig 2311d1ed6aa1SChristoph Hellwig sent--; 23125271edd4SChristoph Hellwig if (nr_queues) 2313db3cbfffSKeith Busch goto retry; 2314db3cbfffSKeith Busch } 23155271edd4SChristoph Hellwig return true; 2316db3cbfffSKeith Busch } 2317db3cbfffSKeith Busch 23185d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 231957dacad5SJay Sternberg { 23202b1b7e78SJianchao Wang int ret; 23212b1b7e78SJianchao Wang 23225bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2323c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 232457dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 23258fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2326ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2327ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 232857dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2329d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 233061f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 233161f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2332d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 233357dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 233457dacad5SJay Sternberg dev->tagset.driver_data = dev; 233557dacad5SJay Sternberg 2336d38e9f04SBenjamin Herrenschmidt /* 2337d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2338d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2339d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2340d38e9f04SBenjamin Herrenschmidt */ 2341d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2342d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2343d38e9f04SBenjamin Herrenschmidt 23442b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23452b1b7e78SJianchao Wang if (ret) { 23462b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23472b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23485d02a5c1SKeith Busch return; 23492b1b7e78SJianchao Wang } 23505bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2351949928c1SKeith Busch } else { 2352949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2353949928c1SKeith Busch 2354949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2355949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 235657dacad5SJay Sternberg } 2357949928c1SKeith Busch 2358e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 235957dacad5SJay Sternberg } 236057dacad5SJay Sternberg 2361b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 236257dacad5SJay Sternberg { 2363b00a726aSKeith Busch int result = -ENOMEM; 236457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 236557dacad5SJay Sternberg 236657dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 236757dacad5SJay Sternberg return result; 236857dacad5SJay Sternberg 236957dacad5SJay Sternberg pci_set_master(pdev); 237057dacad5SJay Sternberg 23714fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 237257dacad5SJay Sternberg goto disable; 237357dacad5SJay Sternberg 23747a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 237557dacad5SJay Sternberg result = -ENODEV; 2376b00a726aSKeith Busch goto disable; 237757dacad5SJay Sternberg } 237857dacad5SJay Sternberg 237957dacad5SJay Sternberg /* 2380a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2381a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2382a5229050SKeith Busch * adjust this later. 238357dacad5SJay Sternberg */ 2384dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2385dca51e78SChristoph Hellwig if (result < 0) 2386dca51e78SChristoph Hellwig return result; 238757dacad5SJay Sternberg 238820d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23897a67cbeaSChristoph Hellwig 23907442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2391b27c1e68Sweiping zhang io_queue_depth); 2392aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 239320d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23947a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23951f390c1fSStephan Günther 23961f390c1fSStephan Günther /* 239766341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 239866341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 239966341331SBenjamin Herrenschmidt * so we don't bother updating it here. 240066341331SBenjamin Herrenschmidt */ 240166341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 240266341331SBenjamin Herrenschmidt dev->io_sqes = 7; 240366341331SBenjamin Herrenschmidt else 2404c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 24051f390c1fSStephan Günther 24061f390c1fSStephan Günther /* 24071f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 24081f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 24091f390c1fSStephan Günther */ 24101f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 24111f390c1fSStephan Günther dev->q_depth = 2; 24129bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 24139bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 24141f390c1fSStephan Günther dev->q_depth); 2415d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2416d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 241720d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2418d554b5e1SMartin K. Petersen dev->q_depth = 64; 2419d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2420d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 24211f390c1fSStephan Günther } 24221f390c1fSStephan Günther 2423d38e9f04SBenjamin Herrenschmidt /* 2424d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2425d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2426d38e9f04SBenjamin Herrenschmidt */ 2427d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2428d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2429d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2430d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2431d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2432d38e9f04SBenjamin Herrenschmidt } 2433d38e9f04SBenjamin Herrenschmidt 2434d38e9f04SBenjamin Herrenschmidt 2435f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2436202021c1SStephen Bates 2437a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2438a0a3408eSKeith Busch pci_save_state(pdev); 243957dacad5SJay Sternberg return 0; 244057dacad5SJay Sternberg 244157dacad5SJay Sternberg disable: 244257dacad5SJay Sternberg pci_disable_device(pdev); 244357dacad5SJay Sternberg return result; 244457dacad5SJay Sternberg } 244557dacad5SJay Sternberg 244657dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 244757dacad5SJay Sternberg { 2448b00a726aSKeith Busch if (dev->bar) 2449b00a726aSKeith Busch iounmap(dev->bar); 2450a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2451b00a726aSKeith Busch } 2452b00a726aSKeith Busch 2453b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2454b00a726aSKeith Busch { 245557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 245657dacad5SJay Sternberg 2457dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 245857dacad5SJay Sternberg 2459a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2460a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 246157dacad5SJay Sternberg pci_disable_device(pdev); 246257dacad5SJay Sternberg } 2463a0a3408eSKeith Busch } 246457dacad5SJay Sternberg 2465a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 246657dacad5SJay Sternberg { 2467e43269e6SKeith Busch bool dead = true, freeze = false; 2468302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 246957dacad5SJay Sternberg 247077bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2471302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2472302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2473302ad8ccSKeith Busch 2474ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2475e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2476e43269e6SKeith Busch freeze = true; 2477302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2478e43269e6SKeith Busch } 2479302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2480302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 248157dacad5SJay Sternberg } 2482c21377f8SGabriel Krisman Bertazi 2483302ad8ccSKeith Busch /* 2484302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2485302ad8ccSKeith Busch * doing a safe shutdown. 2486302ad8ccSKeith Busch */ 2487e43269e6SKeith Busch if (!dead && shutdown && freeze) 2488302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 248987ad72a5SChristoph Hellwig 24909a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24919a915a5bSJianchao Wang 249264ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24938fae268bSKeith Busch nvme_disable_io_queues(dev); 2494a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 249557dacad5SJay Sternberg } 24968fae268bSKeith Busch nvme_suspend_io_queues(dev); 24978fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2498b00a726aSKeith Busch nvme_pci_disable(dev); 2499fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 250057dacad5SJay Sternberg 2501e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2502e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2503622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2504622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2505302ad8ccSKeith Busch 2506302ad8ccSKeith Busch /* 2507302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2508302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2509302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2510302ad8ccSKeith Busch */ 2511c8e9e9b7SKeith Busch if (shutdown) { 2512302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2513c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2514c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2515c8e9e9b7SKeith Busch } 251677bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 251757dacad5SJay Sternberg } 251857dacad5SJay Sternberg 2519c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2520c1ac9a4bSKeith Busch { 2521c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2522c1ac9a4bSKeith Busch return -EBUSY; 2523c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2524c1ac9a4bSKeith Busch return 0; 2525c1ac9a4bSKeith Busch } 2526c1ac9a4bSKeith Busch 252757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 252857dacad5SJay Sternberg { 252957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2530c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2531c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 253257dacad5SJay Sternberg if (!dev->prp_page_pool) 253357dacad5SJay Sternberg return -ENOMEM; 253457dacad5SJay Sternberg 253557dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 253657dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 253757dacad5SJay Sternberg 256, 256, 0); 253857dacad5SJay Sternberg if (!dev->prp_small_pool) { 253957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 254057dacad5SJay Sternberg return -ENOMEM; 254157dacad5SJay Sternberg } 254257dacad5SJay Sternberg return 0; 254357dacad5SJay Sternberg } 254457dacad5SJay Sternberg 254557dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 254657dacad5SJay Sternberg { 254757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 254857dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 254957dacad5SJay Sternberg } 255057dacad5SJay Sternberg 2551770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2552770597ecSKeith Busch { 2553770597ecSKeith Busch if (dev->tagset.tags) 2554770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2555770597ecSKeith Busch dev->ctrl.tagset = NULL; 2556770597ecSKeith Busch } 2557770597ecSKeith Busch 25581673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 255957dacad5SJay Sternberg { 25601673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 256157dacad5SJay Sternberg 2562f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2563770597ecSKeith Busch nvme_free_tagset(dev); 25641c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 25651c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2566e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2567943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2568253fd4acSIsrael Rukshin put_device(dev->dev); 2569253fd4acSIsrael Rukshin kfree(dev->queues); 257057dacad5SJay Sternberg kfree(dev); 257157dacad5SJay Sternberg } 257257dacad5SJay Sternberg 25737c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2574f58944e2SKeith Busch { 2575c1ac9a4bSKeith Busch /* 2576c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2577c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2578c1ac9a4bSKeith Busch */ 2579c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2580d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 258169d9a99cSKeith Busch nvme_dev_disable(dev, false); 25829f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 258303e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2584f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2585f58944e2SKeith Busch } 2586f58944e2SKeith Busch 2587fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 258857dacad5SJay Sternberg { 2589d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2590d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2591a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2592e71afda4SChaitanya Kulkarni int result; 259357dacad5SJay Sternberg 2594e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2595e71afda4SChaitanya Kulkarni result = -ENODEV; 2596fd634f41SChristoph Hellwig goto out; 2597e71afda4SChaitanya Kulkarni } 2598fd634f41SChristoph Hellwig 2599fd634f41SChristoph Hellwig /* 2600fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2601fd634f41SChristoph Hellwig * moving on. 2602fd634f41SChristoph Hellwig */ 2603b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2604a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2605d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2606fd634f41SChristoph Hellwig 26075c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2608b00a726aSKeith Busch result = nvme_pci_enable(dev); 260957dacad5SJay Sternberg if (result) 26104726bcf3SKeith Busch goto out_unlock; 261157dacad5SJay Sternberg 261201ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 261357dacad5SJay Sternberg if (result) 26144726bcf3SKeith Busch goto out_unlock; 261557dacad5SJay Sternberg 261657dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 261757dacad5SJay Sternberg if (result) 26184726bcf3SKeith Busch goto out_unlock; 261957dacad5SJay Sternberg 2620943e942eSJens Axboe /* 2621943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2622943e942eSJens Axboe * over a single page. 2623943e942eSJens Axboe */ 26247637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 26257637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2626943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2627a48bc520SChristoph Hellwig 2628a48bc520SChristoph Hellwig /* 2629a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2630a48bc520SChristoph Hellwig */ 2631a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2632a48bc520SChristoph Hellwig 26335c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 26345c959d73SKeith Busch 26355c959d73SKeith Busch /* 26365c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 26375c959d73SKeith Busch * initializing procedure here. 26385c959d73SKeith Busch */ 26395c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 26405c959d73SKeith Busch dev_warn(dev->ctrl.device, 26415c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2642cee6c269SMinwoo Im result = -EBUSY; 26435c959d73SKeith Busch goto out; 26445c959d73SKeith Busch } 2645943e942eSJens Axboe 264695093350SMax Gurtovoy /* 264795093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 264895093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 264995093350SMax Gurtovoy */ 265095093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 265195093350SMax Gurtovoy 2652ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2653ce4541f4SChristoph Hellwig if (result) 2654f58944e2SKeith Busch goto out; 2655ce4541f4SChristoph Hellwig 2656e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2657e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 26584f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 26594f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2660e286bcfcSScott Bauer else if (was_suspend) 26614f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2662e286bcfcSScott Bauer } else { 2663e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2664e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2665e286bcfcSScott Bauer } 2666a98e58e5SScott Bauer 2667f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2668f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2669f9f38e33SHelen Koike if (result) 2670f9f38e33SHelen Koike dev_warn(dev->dev, 2671f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2672f9f38e33SHelen Koike } 2673f9f38e33SHelen Koike 26749620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 26759620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26769620cfbaSChristoph Hellwig if (result < 0) 26779620cfbaSChristoph Hellwig goto out; 26789620cfbaSChristoph Hellwig } 267987ad72a5SChristoph Hellwig 268057dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 268157dacad5SJay Sternberg if (result) 2682f58944e2SKeith Busch goto out; 268357dacad5SJay Sternberg 268421f033f7SKeith Busch /* 268557dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 268657dacad5SJay Sternberg * any working I/O queue. 268757dacad5SJay Sternberg */ 268857dacad5SJay Sternberg if (dev->online_queues < 2) { 26891b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26903b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26915bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2692770597ecSKeith Busch nvme_free_tagset(dev); 269357dacad5SJay Sternberg } else { 269425646264SKeith Busch nvme_start_queues(&dev->ctrl); 2695302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26965d02a5c1SKeith Busch nvme_dev_add(dev); 2697302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 269857dacad5SJay Sternberg } 269957dacad5SJay Sternberg 27002b1b7e78SJianchao Wang /* 27012b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 27022b1b7e78SJianchao Wang * recovery. 27032b1b7e78SJianchao Wang */ 27045d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 27052b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 27065d02a5c1SKeith Busch "failed to mark controller live state\n"); 2707e71afda4SChaitanya Kulkarni result = -ENODEV; 2708bb8d261eSChristoph Hellwig goto out; 2709bb8d261eSChristoph Hellwig } 271092911a55SChristoph Hellwig 2711d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 271257dacad5SJay Sternberg return; 271357dacad5SJay Sternberg 27144726bcf3SKeith Busch out_unlock: 27154726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 271657dacad5SJay Sternberg out: 27177c1ce408SChaitanya Kulkarni if (result) 27187c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 27197c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 27207c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 272157dacad5SJay Sternberg } 272257dacad5SJay Sternberg 27235c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 272457dacad5SJay Sternberg { 27255c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 272657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 272757dacad5SJay Sternberg 272857dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2729921920abSKeith Busch device_release_driver(&pdev->dev); 27301673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 273157dacad5SJay Sternberg } 273257dacad5SJay Sternberg 27331c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 273457dacad5SJay Sternberg { 27351c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 27361c63dc66SChristoph Hellwig return 0; 273757dacad5SJay Sternberg } 27381c63dc66SChristoph Hellwig 27395fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 27405fd4ce1bSChristoph Hellwig { 27415fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 27425fd4ce1bSChristoph Hellwig return 0; 27435fd4ce1bSChristoph Hellwig } 27445fd4ce1bSChristoph Hellwig 27457fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 27467fd8930fSChristoph Hellwig { 27473a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 27487fd8930fSChristoph Hellwig return 0; 27497fd8930fSChristoph Hellwig } 27507fd8930fSChristoph Hellwig 275197c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 275297c12223SKeith Busch { 275397c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 275497c12223SKeith Busch 27552db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 275697c12223SKeith Busch } 275797c12223SKeith Busch 27581c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 27591a353d85SMing Lin .name = "pcie", 2760e439bb12SSagi Grimberg .module = THIS_MODULE, 2761e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2762e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 27631c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 27645fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 27657fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 27661673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2767f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 276897c12223SKeith Busch .get_address = nvme_pci_get_address, 27691c63dc66SChristoph Hellwig }; 277057dacad5SJay Sternberg 2771b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2772b00a726aSKeith Busch { 2773b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2774b00a726aSKeith Busch 2775a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2776b00a726aSKeith Busch return -ENODEV; 2777b00a726aSKeith Busch 277897f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2779b00a726aSKeith Busch goto release; 2780b00a726aSKeith Busch 2781b00a726aSKeith Busch return 0; 2782b00a726aSKeith Busch release: 2783a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2784b00a726aSKeith Busch return -ENODEV; 2785b00a726aSKeith Busch } 2786b00a726aSKeith Busch 27878427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2788ff5350a8SAndy Lutomirski { 2789ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2790ff5350a8SAndy Lutomirski /* 2791ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2792ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2793ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2794ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2795ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2796ff5350a8SAndy Lutomirski * laptops. 2797ff5350a8SAndy Lutomirski */ 2798ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2799ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2800ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2801ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 28028427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 28038427bbc2SKai-Heng Feng /* 28048427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2805467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2806467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2807467c77d4SJarosław Janik * ASUS PRIME Z370-A 28088427bbc2SKai-Heng Feng */ 28098427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2810467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2811467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 28128427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 28131fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 28141fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 28151fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 28161fae37acSShyjumon N /* 28171fae37acSShyjumon N * Forcing to use host managed nvme power settings for 28181fae37acSShyjumon N * lowest idle power with quick resume latency on 28191fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 28201fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 28211fae37acSShyjumon N */ 28221fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 28231fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 28241fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2825ff5350a8SAndy Lutomirski } 2826ff5350a8SAndy Lutomirski 2827ff5350a8SAndy Lutomirski return 0; 2828ff5350a8SAndy Lutomirski } 2829ff5350a8SAndy Lutomirski 2830df4f9bc4SDavid E. Box #ifdef CONFIG_ACPI 2831df4f9bc4SDavid E. Box static bool nvme_acpi_storage_d3(struct pci_dev *dev) 2832df4f9bc4SDavid E. Box { 2833df4f9bc4SDavid E. Box struct acpi_device *adev; 2834df4f9bc4SDavid E. Box struct pci_dev *root; 2835df4f9bc4SDavid E. Box acpi_handle handle; 2836df4f9bc4SDavid E. Box acpi_status status; 2837df4f9bc4SDavid E. Box u8 val; 2838df4f9bc4SDavid E. Box 2839df4f9bc4SDavid E. Box /* 2840df4f9bc4SDavid E. Box * Look for _DSD property specifying that the storage device on the port 2841df4f9bc4SDavid E. Box * must use D3 to support deep platform power savings during 2842df4f9bc4SDavid E. Box * suspend-to-idle. 2843df4f9bc4SDavid E. Box */ 2844df4f9bc4SDavid E. Box root = pcie_find_root_port(dev); 2845df4f9bc4SDavid E. Box if (!root) 2846df4f9bc4SDavid E. Box return false; 2847df4f9bc4SDavid E. Box 2848df4f9bc4SDavid E. Box adev = ACPI_COMPANION(&root->dev); 2849df4f9bc4SDavid E. Box if (!adev) 2850df4f9bc4SDavid E. Box return false; 2851df4f9bc4SDavid E. Box 2852df4f9bc4SDavid E. Box /* 2853df4f9bc4SDavid E. Box * The property is defined in the PXSX device for South complex ports 2854df4f9bc4SDavid E. Box * and in the PEGP device for North complex ports. 2855df4f9bc4SDavid E. Box */ 2856df4f9bc4SDavid E. Box status = acpi_get_handle(adev->handle, "PXSX", &handle); 2857df4f9bc4SDavid E. Box if (ACPI_FAILURE(status)) { 2858df4f9bc4SDavid E. Box status = acpi_get_handle(adev->handle, "PEGP", &handle); 2859df4f9bc4SDavid E. Box if (ACPI_FAILURE(status)) 2860df4f9bc4SDavid E. Box return false; 2861df4f9bc4SDavid E. Box } 2862df4f9bc4SDavid E. Box 2863df4f9bc4SDavid E. Box if (acpi_bus_get_device(handle, &adev)) 2864df4f9bc4SDavid E. Box return false; 2865df4f9bc4SDavid E. Box 2866df4f9bc4SDavid E. Box if (fwnode_property_read_u8(acpi_fwnode_handle(adev), "StorageD3Enable", 2867df4f9bc4SDavid E. Box &val)) 2868df4f9bc4SDavid E. Box return false; 2869df4f9bc4SDavid E. Box return val == 1; 2870df4f9bc4SDavid E. Box } 2871df4f9bc4SDavid E. Box #else 2872df4f9bc4SDavid E. Box static inline bool nvme_acpi_storage_d3(struct pci_dev *dev) 2873df4f9bc4SDavid E. Box { 2874df4f9bc4SDavid E. Box return false; 2875df4f9bc4SDavid E. Box } 2876df4f9bc4SDavid E. Box #endif /* CONFIG_ACPI */ 2877df4f9bc4SDavid E. Box 287818119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 287918119775SKeith Busch { 288018119775SKeith Busch struct nvme_dev *dev = data; 288180f513b5SKeith Busch 2882bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 288318119775SKeith Busch flush_work(&dev->ctrl.scan_work); 288480f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 288518119775SKeith Busch } 288618119775SKeith Busch 288757dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 288857dacad5SJay Sternberg { 288957dacad5SJay Sternberg int node, result = -ENOMEM; 289057dacad5SJay Sternberg struct nvme_dev *dev; 2891ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2892943e942eSJens Axboe size_t alloc_size; 289357dacad5SJay Sternberg 289457dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 289557dacad5SJay Sternberg if (node == NUMA_NO_NODE) 28962fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 289757dacad5SJay Sternberg 289857dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 289957dacad5SJay Sternberg if (!dev) 290057dacad5SJay Sternberg return -ENOMEM; 2901147b27e4SSagi Grimberg 29022a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 29032a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 29042a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 29052a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 29062a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 290757dacad5SJay Sternberg if (!dev->queues) 290857dacad5SJay Sternberg goto free; 290957dacad5SJay Sternberg 291057dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 291157dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 291257dacad5SJay Sternberg 2913b00a726aSKeith Busch result = nvme_dev_map(dev); 2914b00a726aSKeith Busch if (result) 2915b00c9b7aSChristophe JAILLET goto put_pci; 2916b00a726aSKeith Busch 2917d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 29185c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 291977bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2920f3ca80fcSChristoph Hellwig 2921f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2922f3ca80fcSChristoph Hellwig if (result) 2923b00c9b7aSChristophe JAILLET goto unmap; 2924f3ca80fcSChristoph Hellwig 29258427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2926ff5350a8SAndy Lutomirski 2927df4f9bc4SDavid E. Box if (!noacpi && nvme_acpi_storage_d3(pdev)) { 2928df4f9bc4SDavid E. Box /* 2929df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 2930df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 2931df4f9bc4SDavid E. Box */ 2932df4f9bc4SDavid E. Box dev_info(&pdev->dev, 2933df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 2934df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2935df4f9bc4SDavid E. Box } 2936df4f9bc4SDavid E. Box 2937943e942eSJens Axboe /* 2938943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2939943e942eSJens Axboe * command we support. 2940943e942eSJens Axboe */ 2941b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 2942943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2943943e942eSJens Axboe 2944943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2945943e942eSJens Axboe mempool_kfree, 2946943e942eSJens Axboe (void *) alloc_size, 2947943e942eSJens Axboe GFP_KERNEL, node); 2948943e942eSJens Axboe if (!dev->iod_mempool) { 2949943e942eSJens Axboe result = -ENOMEM; 2950943e942eSJens Axboe goto release_pools; 2951943e942eSJens Axboe } 2952943e942eSJens Axboe 2953b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2954b6e44b4cSKeith Busch quirks); 2955b6e44b4cSKeith Busch if (result) 2956b6e44b4cSKeith Busch goto release_mempool; 2957b6e44b4cSKeith Busch 29581b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 29591b3c47c1SSagi Grimberg 2960bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 296118119775SKeith Busch async_schedule(nvme_async_probe, dev); 29624caff8fcSSagi Grimberg 296357dacad5SJay Sternberg return 0; 296457dacad5SJay Sternberg 2965b6e44b4cSKeith Busch release_mempool: 2966b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 296757dacad5SJay Sternberg release_pools: 296857dacad5SJay Sternberg nvme_release_prp_pools(dev); 2969b00c9b7aSChristophe JAILLET unmap: 2970b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 297157dacad5SJay Sternberg put_pci: 297257dacad5SJay Sternberg put_device(dev->dev); 297357dacad5SJay Sternberg free: 297457dacad5SJay Sternberg kfree(dev->queues); 297557dacad5SJay Sternberg kfree(dev); 297657dacad5SJay Sternberg return result; 297757dacad5SJay Sternberg } 297857dacad5SJay Sternberg 2979775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 298057dacad5SJay Sternberg { 298157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2982c1ac9a4bSKeith Busch 2983c1ac9a4bSKeith Busch /* 2984c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2985c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2986c1ac9a4bSKeith Busch * with ->remove(). 2987c1ac9a4bSKeith Busch */ 2988c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2989c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2990775755edSChristoph Hellwig } 299157dacad5SJay Sternberg 2992775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2993775755edSChristoph Hellwig { 2994f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2995c1ac9a4bSKeith Busch 2996c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2997c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 299857dacad5SJay Sternberg } 299957dacad5SJay Sternberg 300057dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 300157dacad5SJay Sternberg { 300257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 30034e523547SBaolin Wang 3004c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 300557dacad5SJay Sternberg } 300657dacad5SJay Sternberg 3007f58944e2SKeith Busch /* 3008f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3009f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3010f58944e2SKeith Busch * order to proceed. 3011f58944e2SKeith Busch */ 301257dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 301357dacad5SJay Sternberg { 301457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 301557dacad5SJay Sternberg 3016bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 301757dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 30180ff9d4e1SKeith Busch 30196db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 30200ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 30211d39e692SKeith Busch nvme_dev_disable(dev, true); 3022cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 30236db28edaSKeith Busch } 30240ff9d4e1SKeith Busch 3025d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3026d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3027d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3028a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 30299fe5c59fSKeith Busch nvme_release_cmb(dev); 303087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 303157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 303257dacad5SJay Sternberg nvme_free_queues(dev, 0); 303357dacad5SJay Sternberg nvme_release_prp_pools(dev); 3034b00a726aSKeith Busch nvme_dev_unmap(dev); 3035726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 303657dacad5SJay Sternberg } 303757dacad5SJay Sternberg 303857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3039d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3040d916b1beSKeith Busch { 3041d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3042d916b1beSKeith Busch } 3043d916b1beSKeith Busch 3044d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3045d916b1beSKeith Busch { 3046d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3047d916b1beSKeith Busch } 3048d916b1beSKeith Busch 3049d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3050d916b1beSKeith Busch { 3051d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3052d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3053d916b1beSKeith Busch 30544eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3055d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3056c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 3057d916b1beSKeith Busch return 0; 3058d916b1beSKeith Busch } 3059d916b1beSKeith Busch 306057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 306157dacad5SJay Sternberg { 306257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 306357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3064d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3065d916b1beSKeith Busch int ret = -EBUSY; 3066d916b1beSKeith Busch 30674eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 30684eaefe8cSRafael J. Wysocki 3069d916b1beSKeith Busch /* 3070d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3071d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3072d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3073d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3074d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3075d916b1beSKeith Busch * device fully. 30764eaefe8cSRafael J. Wysocki * 30774eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 30784eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 30794eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 30804eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3081b97120b1SChristoph Hellwig * 3082b97120b1SChristoph Hellwig * If a host memory buffer is enabled, shut down the device as the NVMe 3083b97120b1SChristoph Hellwig * specification allows the device to access the host memory buffer in 3084b97120b1SChristoph Hellwig * host DRAM from all power states, but hosts will fail access to DRAM 3085b97120b1SChristoph Hellwig * during S3. 3086d916b1beSKeith Busch */ 30874eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3088cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3089b97120b1SChristoph Hellwig ndev->nr_host_mem_descs || 3090c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3091c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3092d916b1beSKeith Busch 3093d916b1beSKeith Busch nvme_start_freeze(ctrl); 3094d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3095d916b1beSKeith Busch nvme_sync_queues(ctrl); 3096d916b1beSKeith Busch 30975d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3098d916b1beSKeith Busch goto unfreeze; 3099d916b1beSKeith Busch 3100d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3101d916b1beSKeith Busch if (ret < 0) 3102d916b1beSKeith Busch goto unfreeze; 3103d916b1beSKeith Busch 31047cbb5c6fSMario Limonciello /* 31057cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 31067cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 31077cbb5c6fSMario Limonciello * want pci interfering. 31087cbb5c6fSMario Limonciello */ 31097cbb5c6fSMario Limonciello pci_save_state(pdev); 31107cbb5c6fSMario Limonciello 3111d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3112d916b1beSKeith Busch if (ret < 0) 3113d916b1beSKeith Busch goto unfreeze; 3114d916b1beSKeith Busch 3115d916b1beSKeith Busch if (ret) { 31167cbb5c6fSMario Limonciello /* discard the saved state */ 31177cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 31187cbb5c6fSMario Limonciello 3119d916b1beSKeith Busch /* 3120d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 312105d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3122d916b1beSKeith Busch */ 3123c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3124d916b1beSKeith Busch ctrl->npss = 0; 3125d916b1beSKeith Busch } 3126d916b1beSKeith Busch unfreeze: 3127d916b1beSKeith Busch nvme_unfreeze(ctrl); 3128d916b1beSKeith Busch return ret; 3129d916b1beSKeith Busch } 3130d916b1beSKeith Busch 3131d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3132d916b1beSKeith Busch { 3133d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 31344e523547SBaolin Wang 3135c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 313657dacad5SJay Sternberg } 313757dacad5SJay Sternberg 3138d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 313957dacad5SJay Sternberg { 314057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 314157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 314257dacad5SJay Sternberg 3143c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 314457dacad5SJay Sternberg } 314557dacad5SJay Sternberg 314621774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3147d916b1beSKeith Busch .suspend = nvme_suspend, 3148d916b1beSKeith Busch .resume = nvme_resume, 3149d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3150d916b1beSKeith Busch .thaw = nvme_simple_resume, 3151d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3152d916b1beSKeith Busch .restore = nvme_simple_resume, 3153d916b1beSKeith Busch }; 3154d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 315557dacad5SJay Sternberg 3156a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3157a0a3408eSKeith Busch pci_channel_state_t state) 3158a0a3408eSKeith Busch { 3159a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3160a0a3408eSKeith Busch 3161a0a3408eSKeith Busch /* 3162a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3163a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3164a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3165a0a3408eSKeith Busch */ 3166a0a3408eSKeith Busch switch (state) { 3167a0a3408eSKeith Busch case pci_channel_io_normal: 3168a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3169a0a3408eSKeith Busch case pci_channel_io_frozen: 3170d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3171d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3172a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3173a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3174a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3175d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3176d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3177a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3178a0a3408eSKeith Busch } 3179a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3180a0a3408eSKeith Busch } 3181a0a3408eSKeith Busch 3182a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3183a0a3408eSKeith Busch { 3184a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3185a0a3408eSKeith Busch 31861b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3187a0a3408eSKeith Busch pci_restore_state(pdev); 3188d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3189a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3190a0a3408eSKeith Busch } 3191a0a3408eSKeith Busch 3192a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3193a0a3408eSKeith Busch { 319472cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 319572cd4cc2SKeith Busch 319672cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3197a0a3408eSKeith Busch } 3198a0a3408eSKeith Busch 319957dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 320057dacad5SJay Sternberg .error_detected = nvme_error_detected, 320157dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 320257dacad5SJay Sternberg .resume = nvme_error_resume, 3203775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3204775755edSChristoph Hellwig .reset_done = nvme_reset_done, 320557dacad5SJay Sternberg }; 320657dacad5SJay Sternberg 320757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3208972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 320908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3210e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3211972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 321299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3213e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3214972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 321599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3216e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3217972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3218f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3219f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 322050af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 32219abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 32226c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3223ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3224ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 32256299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 32266299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3227540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 32287b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 32297b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 32305bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 32315bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 32320302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 32330302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 323454adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 323554adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 32368c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 32378c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3238015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3239015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3240d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3241d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3242d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 32437ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 32447ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3245608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3246608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3247608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3248608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3249ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3250ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 325108b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 325208b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3253f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3254f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3255f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 32565611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 32575611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 325802ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 325902ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 326098f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 326198f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3262124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 326366341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 326466341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3265d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3266d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 32670b85f59dSAndy Shevchenko 32680b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 326957dacad5SJay Sternberg { 0, } 327057dacad5SJay Sternberg }; 327157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 327257dacad5SJay Sternberg 327357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 327457dacad5SJay Sternberg .name = "nvme", 327557dacad5SJay Sternberg .id_table = nvme_id_table, 327657dacad5SJay Sternberg .probe = nvme_probe, 327757dacad5SJay Sternberg .remove = nvme_remove, 327857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3279d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 328057dacad5SJay Sternberg .driver = { 328157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 328257dacad5SJay Sternberg }, 3283d916b1beSKeith Busch #endif 328474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 328557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 328657dacad5SJay Sternberg }; 328757dacad5SJay Sternberg 328857dacad5SJay Sternberg static int __init nvme_init(void) 328957dacad5SJay Sternberg { 329081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 329181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 329281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3293612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 329417c33167SKeith Busch 32959a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 329657dacad5SJay Sternberg } 329757dacad5SJay Sternberg 329857dacad5SJay Sternberg static void __exit nvme_exit(void) 329957dacad5SJay Sternberg { 330057dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 330103e0f3a6SMing Lei flush_workqueue(nvme_wq); 330257dacad5SJay Sternberg } 330357dacad5SJay Sternberg 330457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 330557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 330657dacad5SJay Sternberg MODULE_VERSION("1.0"); 330757dacad5SJay Sternberg module_init(nvme_init); 330857dacad5SJay Sternberg module_exit(nvme_exit); 3309