157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/bitops.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 2757dacad5SJay Sternberg #include <linux/pci.h> 2857dacad5SJay Sternberg #include <linux/poison.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 302d55cd5fSChristoph Hellwig #include <linux/timer.h> 3157dacad5SJay Sternberg #include <linux/types.h> 329cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 331d277a63SKeith Busch #include <asm/unaligned.h> 34a98e58e5SScott Bauer #include <linux/sed-opal.h> 3557dacad5SJay Sternberg 3657dacad5SJay Sternberg #include "nvme.h" 3757dacad5SJay Sternberg 3857dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3957dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 4057dacad5SJay Sternberg 41adf68f21SChristoph Hellwig /* 42adf68f21SChristoph Hellwig * We handle AEN commands ourselves and don't even let the 43adf68f21SChristoph Hellwig * block layer know about them. 44adf68f21SChristoph Hellwig */ 45f866fc42SChristoph Hellwig #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) 46adf68f21SChristoph Hellwig 4757dacad5SJay Sternberg static int use_threaded_interrupts; 4857dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5157dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 60b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 61b27c1e68Sweiping zhang .set = io_queue_depth_set, 62b27c1e68Sweiping zhang .get = param_get_int, 63b27c1e68Sweiping zhang }; 64b27c1e68Sweiping zhang 65b27c1e68Sweiping zhang static int io_queue_depth = 1024; 66b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 67b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 68b27c1e68Sweiping zhang 691c63dc66SChristoph Hellwig struct nvme_dev; 701c63dc66SChristoph Hellwig struct nvme_queue; 7157dacad5SJay Sternberg 72a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 73a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7457dacad5SJay Sternberg 7557dacad5SJay Sternberg /* 761c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 771c63dc66SChristoph Hellwig */ 781c63dc66SChristoph Hellwig struct nvme_dev { 791c63dc66SChristoph Hellwig struct nvme_queue **queues; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 811c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 821c63dc66SChristoph Hellwig u32 __iomem *dbs; 831c63dc66SChristoph Hellwig struct device *dev; 841c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 851c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 861c63dc66SChristoph Hellwig unsigned online_queues; 871c63dc66SChristoph Hellwig unsigned max_qid; 881c63dc66SChristoph Hellwig int q_depth; 891c63dc66SChristoph Hellwig u32 db_stride; 901c63dc66SChristoph Hellwig void __iomem *bar; 9197f6ef64SXu Yu unsigned long bar_mapped_size; 925c8809e6SChristoph Hellwig struct work_struct remove_work; 9377bf25eaSKeith Busch struct mutex shutdown_lock; 941c63dc66SChristoph Hellwig bool subsystem; 951c63dc66SChristoph Hellwig void __iomem *cmb; 961c63dc66SChristoph Hellwig dma_addr_t cmb_dma_addr; 971c63dc66SChristoph Hellwig u64 cmb_size; 981c63dc66SChristoph Hellwig u32 cmbsz; 99202021c1SStephen Bates u32 cmbloc; 1001c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 101db3cbfffSKeith Busch struct completion ioq_wait; 10287ad72a5SChristoph Hellwig 10387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 104f9f38e33SHelen Koike u32 *dbbuf_dbs; 105f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 106f9f38e33SHelen Koike u32 *dbbuf_eis; 107f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10887ad72a5SChristoph Hellwig 10987ad72a5SChristoph Hellwig /* host memory buffer support: */ 11087ad72a5SChristoph Hellwig u64 host_mem_size; 11187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 11287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11457dacad5SJay Sternberg }; 11557dacad5SJay Sternberg 116b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 117b27c1e68Sweiping zhang { 118b27c1e68Sweiping zhang int n = 0, ret; 119b27c1e68Sweiping zhang 120b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 121b27c1e68Sweiping zhang if (ret != 0 || n < 2) 122b27c1e68Sweiping zhang return -EINVAL; 123b27c1e68Sweiping zhang 124b27c1e68Sweiping zhang return param_set_int(val, kp); 125b27c1e68Sweiping zhang } 126b27c1e68Sweiping zhang 127f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 128f9f38e33SHelen Koike { 129f9f38e33SHelen Koike return qid * 2 * stride; 130f9f38e33SHelen Koike } 131f9f38e33SHelen Koike 132f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 133f9f38e33SHelen Koike { 134f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 135f9f38e33SHelen Koike } 136f9f38e33SHelen Koike 1371c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1381c63dc66SChristoph Hellwig { 1391c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1401c63dc66SChristoph Hellwig } 1411c63dc66SChristoph Hellwig 14257dacad5SJay Sternberg /* 14357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14457dacad5SJay Sternberg * commands and one for I/O commands). 14557dacad5SJay Sternberg */ 14657dacad5SJay Sternberg struct nvme_queue { 14757dacad5SJay Sternberg struct device *q_dmadev; 14857dacad5SJay Sternberg struct nvme_dev *dev; 14957dacad5SJay Sternberg spinlock_t q_lock; 15057dacad5SJay Sternberg struct nvme_command *sq_cmds; 15157dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15257dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15357dacad5SJay Sternberg struct blk_mq_tags **tags; 15457dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15557dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15657dacad5SJay Sternberg u32 __iomem *q_db; 15757dacad5SJay Sternberg u16 q_depth; 15857dacad5SJay Sternberg s16 cq_vector; 15957dacad5SJay Sternberg u16 sq_tail; 16057dacad5SJay Sternberg u16 cq_head; 16157dacad5SJay Sternberg u16 qid; 16257dacad5SJay Sternberg u8 cq_phase; 16357dacad5SJay Sternberg u8 cqe_seen; 164f9f38e33SHelen Koike u32 *dbbuf_sq_db; 165f9f38e33SHelen Koike u32 *dbbuf_cq_db; 166f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 167f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16857dacad5SJay Sternberg }; 16957dacad5SJay Sternberg 17057dacad5SJay Sternberg /* 17171bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17271bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 173f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17471bd150cSChristoph Hellwig * allocated to store the PRP list. 17571bd150cSChristoph Hellwig */ 17671bd150cSChristoph Hellwig struct nvme_iod { 177d49187e9SChristoph Hellwig struct nvme_request req; 178f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 179f4800d6dSChristoph Hellwig int aborted; 18071bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18171bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18271bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18371bd150cSChristoph Hellwig dma_addr_t first_dma; 184bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 185f4800d6dSChristoph Hellwig struct scatterlist *sg; 186f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18757dacad5SJay Sternberg }; 18857dacad5SJay Sternberg 18957dacad5SJay Sternberg /* 19057dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19157dacad5SJay Sternberg */ 19257dacad5SJay Sternberg static inline void _nvme_check_size(void) 19357dacad5SJay Sternberg { 19457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2020add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2030add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 206f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 207f9f38e33SHelen Koike } 208f9f38e33SHelen Koike 209f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 210f9f38e33SHelen Koike { 211f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 212f9f38e33SHelen Koike } 213f9f38e33SHelen Koike 214f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 215f9f38e33SHelen Koike { 216f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 217f9f38e33SHelen Koike 218f9f38e33SHelen Koike if (dev->dbbuf_dbs) 219f9f38e33SHelen Koike return 0; 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 222f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 223f9f38e33SHelen Koike GFP_KERNEL); 224f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 225f9f38e33SHelen Koike return -ENOMEM; 226f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 227f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 228f9f38e33SHelen Koike GFP_KERNEL); 229f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 230f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 231f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 232f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 233f9f38e33SHelen Koike return -ENOMEM; 234f9f38e33SHelen Koike } 235f9f38e33SHelen Koike 236f9f38e33SHelen Koike return 0; 237f9f38e33SHelen Koike } 238f9f38e33SHelen Koike 239f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 240f9f38e33SHelen Koike { 241f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 242f9f38e33SHelen Koike 243f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 244f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 245f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 247f9f38e33SHelen Koike } 248f9f38e33SHelen Koike if (dev->dbbuf_eis) { 249f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 250f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 251f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 252f9f38e33SHelen Koike } 253f9f38e33SHelen Koike } 254f9f38e33SHelen Koike 255f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 256f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 257f9f38e33SHelen Koike { 258f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 259f9f38e33SHelen Koike return; 260f9f38e33SHelen Koike 261f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 262f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 263f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike } 266f9f38e33SHelen Koike 267f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 268f9f38e33SHelen Koike { 269f9f38e33SHelen Koike struct nvme_command c; 270f9f38e33SHelen Koike 271f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 272f9f38e33SHelen Koike return; 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 275f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 276f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 277f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2809bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 281f9f38e33SHelen Koike /* Free memory and continue on */ 282f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 283f9f38e33SHelen Koike } 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike 286f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 287f9f38e33SHelen Koike { 288f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 289f9f38e33SHelen Koike } 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 292f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 293f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 294f9f38e33SHelen Koike { 295f9f38e33SHelen Koike if (dbbuf_db) { 296f9f38e33SHelen Koike u16 old_value; 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike /* 299f9f38e33SHelen Koike * Ensure that the queue is written before updating 300f9f38e33SHelen Koike * the doorbell in memory 301f9f38e33SHelen Koike */ 302f9f38e33SHelen Koike wmb(); 303f9f38e33SHelen Koike 304f9f38e33SHelen Koike old_value = *dbbuf_db; 305f9f38e33SHelen Koike *dbbuf_db = value; 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 308f9f38e33SHelen Koike return false; 309f9f38e33SHelen Koike } 310f9f38e33SHelen Koike 311f9f38e33SHelen Koike return true; 31257dacad5SJay Sternberg } 31357dacad5SJay Sternberg 31457dacad5SJay Sternberg /* 31557dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31657dacad5SJay Sternberg */ 31757dacad5SJay Sternberg #define NVME_INT_PAGES 2 3185fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 31957dacad5SJay Sternberg 32057dacad5SJay Sternberg /* 32157dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32257dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32357dacad5SJay Sternberg * the I/O. 32457dacad5SJay Sternberg */ 32557dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32657dacad5SJay Sternberg { 3275fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3285fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 32957dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33057dacad5SJay Sternberg } 33157dacad5SJay Sternberg 332f4800d6dSChristoph Hellwig static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, 333f4800d6dSChristoph Hellwig unsigned int size, unsigned int nseg) 334f4800d6dSChristoph Hellwig { 335f4800d6dSChristoph Hellwig return sizeof(__le64 *) * nvme_npages(size, dev) + 336f4800d6dSChristoph Hellwig sizeof(struct scatterlist) * nseg; 337f4800d6dSChristoph Hellwig } 338f4800d6dSChristoph Hellwig 33957dacad5SJay Sternberg static unsigned int nvme_cmd_size(struct nvme_dev *dev) 34057dacad5SJay Sternberg { 341f4800d6dSChristoph Hellwig return sizeof(struct nvme_iod) + 342f4800d6dSChristoph Hellwig nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); 34357dacad5SJay Sternberg } 34457dacad5SJay Sternberg 34557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 34657dacad5SJay Sternberg unsigned int hctx_idx) 34757dacad5SJay Sternberg { 34857dacad5SJay Sternberg struct nvme_dev *dev = data; 34957dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 35057dacad5SJay Sternberg 35157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 35257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 35357dacad5SJay Sternberg WARN_ON(nvmeq->tags); 35457dacad5SJay Sternberg 35557dacad5SJay Sternberg hctx->driver_data = nvmeq; 35657dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 35757dacad5SJay Sternberg return 0; 35857dacad5SJay Sternberg } 35957dacad5SJay Sternberg 36057dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 36157dacad5SJay Sternberg { 36257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 36357dacad5SJay Sternberg 36457dacad5SJay Sternberg nvmeq->tags = NULL; 36557dacad5SJay Sternberg } 36657dacad5SJay Sternberg 36757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36857dacad5SJay Sternberg unsigned int hctx_idx) 36957dacad5SJay Sternberg { 37057dacad5SJay Sternberg struct nvme_dev *dev = data; 37157dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg if (!nvmeq->tags) 37457dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 37757dacad5SJay Sternberg hctx->driver_data = nvmeq; 37857dacad5SJay Sternberg return 0; 37957dacad5SJay Sternberg } 38057dacad5SJay Sternberg 381d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 382d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 38357dacad5SJay Sternberg { 384d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 385f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 3860350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 3870350815aSChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[queue_idx]; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg BUG_ON(!nvmeq); 390f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 39157dacad5SJay Sternberg return 0; 39257dacad5SJay Sternberg } 39357dacad5SJay Sternberg 394dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 395dca51e78SChristoph Hellwig { 396dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 397dca51e78SChristoph Hellwig 398dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 399dca51e78SChristoph Hellwig } 400dca51e78SChristoph Hellwig 40157dacad5SJay Sternberg /** 402adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 40357dacad5SJay Sternberg * @nvmeq: The queue to use 40457dacad5SJay Sternberg * @cmd: The command to send 40557dacad5SJay Sternberg * 40657dacad5SJay Sternberg * Safe to use from interrupt context 40757dacad5SJay Sternberg */ 40857dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 40957dacad5SJay Sternberg struct nvme_command *cmd) 41057dacad5SJay Sternberg { 41157dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 41257dacad5SJay Sternberg 41357dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 41457dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 41557dacad5SJay Sternberg else 41657dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 41757dacad5SJay Sternberg 41857dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 41957dacad5SJay Sternberg tail = 0; 420f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 421f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 42257dacad5SJay Sternberg writel(tail, nvmeq->q_db); 42357dacad5SJay Sternberg nvmeq->sq_tail = tail; 42457dacad5SJay Sternberg } 42557dacad5SJay Sternberg 426f4800d6dSChristoph Hellwig static __le64 **iod_list(struct request *req) 42757dacad5SJay Sternberg { 428f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 429f9d03f96SChristoph Hellwig return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); 43057dacad5SJay Sternberg } 43157dacad5SJay Sternberg 432fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 43357dacad5SJay Sternberg { 434f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 435f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 436b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 437f4800d6dSChristoph Hellwig 438f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 439f4800d6dSChristoph Hellwig iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); 440f4800d6dSChristoph Hellwig if (!iod->sg) 441fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 442f4800d6dSChristoph Hellwig } else { 443f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 44457dacad5SJay Sternberg } 44557dacad5SJay Sternberg 446f4800d6dSChristoph Hellwig iod->aborted = 0; 44757dacad5SJay Sternberg iod->npages = -1; 44857dacad5SJay Sternberg iod->nents = 0; 449f4800d6dSChristoph Hellwig iod->length = size; 450f80ec966SKeith Busch 451fc17b653SChristoph Hellwig return BLK_STS_OK; 45257dacad5SJay Sternberg } 45357dacad5SJay Sternberg 454f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 45557dacad5SJay Sternberg { 456f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4575fd4ce1bSChristoph Hellwig const int last_prp = dev->ctrl.page_size / 8 - 1; 45857dacad5SJay Sternberg int i; 459f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 46057dacad5SJay Sternberg dma_addr_t prp_dma = iod->first_dma; 46157dacad5SJay Sternberg 46257dacad5SJay Sternberg if (iod->npages == 0) 46357dacad5SJay Sternberg dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 46457dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 46557dacad5SJay Sternberg __le64 *prp_list = list[i]; 46657dacad5SJay Sternberg dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 46757dacad5SJay Sternberg dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 46857dacad5SJay Sternberg prp_dma = next_prp_dma; 46957dacad5SJay Sternberg } 47057dacad5SJay Sternberg 471f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 472f4800d6dSChristoph Hellwig kfree(iod->sg); 47357dacad5SJay Sternberg } 47457dacad5SJay Sternberg 47557dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 47657dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 47757dacad5SJay Sternberg { 47857dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 47957dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 48057dacad5SJay Sternberg } 48157dacad5SJay Sternberg 48257dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 48357dacad5SJay Sternberg { 48457dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 48557dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 48657dacad5SJay Sternberg } 48757dacad5SJay Sternberg 48857dacad5SJay Sternberg /** 48957dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 49057dacad5SJay Sternberg * 49157dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 49257dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 49357dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 49457dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 49557dacad5SJay Sternberg * 49657dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 49757dacad5SJay Sternberg */ 49857dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 49957dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 50057dacad5SJay Sternberg { 50157dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 50257dacad5SJay Sternberg struct bio_integrity_payload *bip; 50357dacad5SJay Sternberg struct t10_pi_tuple *pi; 50457dacad5SJay Sternberg void *p, *pmap; 50557dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 50657dacad5SJay Sternberg 50757dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 50857dacad5SJay Sternberg return; 50957dacad5SJay Sternberg 51057dacad5SJay Sternberg bip = bio_integrity(req->bio); 51157dacad5SJay Sternberg if (!bip) 51257dacad5SJay Sternberg return; 51357dacad5SJay Sternberg 51457dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 51557dacad5SJay Sternberg 51657dacad5SJay Sternberg p = pmap; 51757dacad5SJay Sternberg virt = bip_get_seed(bip); 51857dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 51957dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 520ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 52157dacad5SJay Sternberg 52257dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 52357dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 52457dacad5SJay Sternberg dif_swap(phys, virt, pi); 52557dacad5SJay Sternberg p += ts; 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg kunmap_atomic(pmap); 52857dacad5SJay Sternberg } 52957dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 53057dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 53157dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 53257dacad5SJay Sternberg { 53357dacad5SJay Sternberg } 53457dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53557dacad5SJay Sternberg { 53657dacad5SJay Sternberg } 53757dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 53857dacad5SJay Sternberg { 53957dacad5SJay Sternberg } 54057dacad5SJay Sternberg #endif 54157dacad5SJay Sternberg 542b131c61dSChristoph Hellwig static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) 54357dacad5SJay Sternberg { 544f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 54557dacad5SJay Sternberg struct dma_pool *pool; 546b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 54757dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 54857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 54957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5505fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 55157dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 55257dacad5SJay Sternberg __le64 *prp_list; 553f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 55457dacad5SJay Sternberg dma_addr_t prp_dma; 55557dacad5SJay Sternberg int nprps, i; 55657dacad5SJay Sternberg 55757dacad5SJay Sternberg length -= (page_size - offset); 55857dacad5SJay Sternberg if (length <= 0) 55969d2b571SChristoph Hellwig return true; 56057dacad5SJay Sternberg 56157dacad5SJay Sternberg dma_len -= (page_size - offset); 56257dacad5SJay Sternberg if (dma_len) { 56357dacad5SJay Sternberg dma_addr += (page_size - offset); 56457dacad5SJay Sternberg } else { 56557dacad5SJay Sternberg sg = sg_next(sg); 56657dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 56757dacad5SJay Sternberg dma_len = sg_dma_len(sg); 56857dacad5SJay Sternberg } 56957dacad5SJay Sternberg 57057dacad5SJay Sternberg if (length <= page_size) { 57157dacad5SJay Sternberg iod->first_dma = dma_addr; 57269d2b571SChristoph Hellwig return true; 57357dacad5SJay Sternberg } 57457dacad5SJay Sternberg 57557dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 57657dacad5SJay Sternberg if (nprps <= (256 / 8)) { 57757dacad5SJay Sternberg pool = dev->prp_small_pool; 57857dacad5SJay Sternberg iod->npages = 0; 57957dacad5SJay Sternberg } else { 58057dacad5SJay Sternberg pool = dev->prp_page_pool; 58157dacad5SJay Sternberg iod->npages = 1; 58257dacad5SJay Sternberg } 58357dacad5SJay Sternberg 58469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 58557dacad5SJay Sternberg if (!prp_list) { 58657dacad5SJay Sternberg iod->first_dma = dma_addr; 58757dacad5SJay Sternberg iod->npages = -1; 58869d2b571SChristoph Hellwig return false; 58957dacad5SJay Sternberg } 59057dacad5SJay Sternberg list[0] = prp_list; 59157dacad5SJay Sternberg iod->first_dma = prp_dma; 59257dacad5SJay Sternberg i = 0; 59357dacad5SJay Sternberg for (;;) { 59457dacad5SJay Sternberg if (i == page_size >> 3) { 59557dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 59669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 59757dacad5SJay Sternberg if (!prp_list) 59869d2b571SChristoph Hellwig return false; 59957dacad5SJay Sternberg list[iod->npages++] = prp_list; 60057dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 60157dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 60257dacad5SJay Sternberg i = 1; 60357dacad5SJay Sternberg } 60457dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 60557dacad5SJay Sternberg dma_len -= page_size; 60657dacad5SJay Sternberg dma_addr += page_size; 60757dacad5SJay Sternberg length -= page_size; 60857dacad5SJay Sternberg if (length <= 0) 60957dacad5SJay Sternberg break; 61057dacad5SJay Sternberg if (dma_len > 0) 61157dacad5SJay Sternberg continue; 61257dacad5SJay Sternberg BUG_ON(dma_len < 0); 61357dacad5SJay Sternberg sg = sg_next(sg); 61457dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 61557dacad5SJay Sternberg dma_len = sg_dma_len(sg); 61657dacad5SJay Sternberg } 61757dacad5SJay Sternberg 61869d2b571SChristoph Hellwig return true; 61957dacad5SJay Sternberg } 62057dacad5SJay Sternberg 621fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 622b131c61dSChristoph Hellwig struct nvme_command *cmnd) 62357dacad5SJay Sternberg { 624f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 625ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 626ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 627ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 628fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 62957dacad5SJay Sternberg 630f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 631ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 632ba1ca37eSChristoph Hellwig if (!iod->nents) 633ba1ca37eSChristoph Hellwig goto out; 634ba1ca37eSChristoph Hellwig 635fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 6362b6b535dSMauricio Faria de Oliveira if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 6372b6b535dSMauricio Faria de Oliveira DMA_ATTR_NO_WARN)) 638ba1ca37eSChristoph Hellwig goto out; 639ba1ca37eSChristoph Hellwig 640b131c61dSChristoph Hellwig if (!nvme_setup_prps(dev, req)) 641ba1ca37eSChristoph Hellwig goto out_unmap; 642ba1ca37eSChristoph Hellwig 643fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 644ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 645ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 646ba1ca37eSChristoph Hellwig goto out_unmap; 647ba1ca37eSChristoph Hellwig 648bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 649bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 650ba1ca37eSChristoph Hellwig goto out_unmap; 651ba1ca37eSChristoph Hellwig 652ba1ca37eSChristoph Hellwig if (rq_data_dir(req)) 653ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 654ba1ca37eSChristoph Hellwig 655bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 656ba1ca37eSChristoph Hellwig goto out_unmap; 65757dacad5SJay Sternberg } 65857dacad5SJay Sternberg 659eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 660eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); 661ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 662bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 663fc17b653SChristoph Hellwig return BLK_STS_OK; 664ba1ca37eSChristoph Hellwig 665ba1ca37eSChristoph Hellwig out_unmap: 666ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 667ba1ca37eSChristoph Hellwig out: 668ba1ca37eSChristoph Hellwig return ret; 66957dacad5SJay Sternberg } 67057dacad5SJay Sternberg 671f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 672d4f6c3abSChristoph Hellwig { 673f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 674d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 675d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 676d4f6c3abSChristoph Hellwig 677d4f6c3abSChristoph Hellwig if (iod->nents) { 678d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 679d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 680d4f6c3abSChristoph Hellwig if (!rq_data_dir(req)) 681d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 682bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 683d4f6c3abSChristoph Hellwig } 684d4f6c3abSChristoph Hellwig } 685d4f6c3abSChristoph Hellwig 686f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 687f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 68857dacad5SJay Sternberg } 68957dacad5SJay Sternberg 69057dacad5SJay Sternberg /* 69157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 69257dacad5SJay Sternberg */ 693fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 69457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 69557dacad5SJay Sternberg { 69657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 69757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 69857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 69957dacad5SJay Sternberg struct request *req = bd->rq; 700ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 701ebe6d874SChristoph Hellwig blk_status_t ret; 70257dacad5SJay Sternberg 703f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 704fc17b653SChristoph Hellwig if (ret) 705f4800d6dSChristoph Hellwig return ret; 70657dacad5SJay Sternberg 707b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 708fc17b653SChristoph Hellwig if (ret) 709f9d03f96SChristoph Hellwig goto out_free_cmd; 71057dacad5SJay Sternberg 711fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 712b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 713fc17b653SChristoph Hellwig if (ret) 714f9d03f96SChristoph Hellwig goto out_cleanup_iod; 715fc17b653SChristoph Hellwig } 716ba1ca37eSChristoph Hellwig 717aae239e1SChristoph Hellwig blk_mq_start_request(req); 718ba1ca37eSChristoph Hellwig 719ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 720ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 721fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 722ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 723f9d03f96SChristoph Hellwig goto out_cleanup_iod; 724ae1fba20SKeith Busch } 725ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 72657dacad5SJay Sternberg nvme_process_cq(nvmeq); 72757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 728fc17b653SChristoph Hellwig return BLK_STS_OK; 729f9d03f96SChristoph Hellwig out_cleanup_iod: 730f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 731f9d03f96SChristoph Hellwig out_free_cmd: 732f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 733ba1ca37eSChristoph Hellwig return ret; 73457dacad5SJay Sternberg } 73557dacad5SJay Sternberg 73677f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 737eee417b0SChristoph Hellwig { 738f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 739eee417b0SChristoph Hellwig 74077f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 74177f02a7aSChristoph Hellwig nvme_complete_rq(req); 74257dacad5SJay Sternberg } 74357dacad5SJay Sternberg 744d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 745d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 746d783e0bdSMarta Rybczynska u16 phase) 747d783e0bdSMarta Rybczynska { 748d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 749d783e0bdSMarta Rybczynska } 750d783e0bdSMarta Rybczynska 751eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 75257dacad5SJay Sternberg { 753eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 75457dacad5SJay Sternberg 755eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 756eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 757eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 758eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 759eb281c82SSagi Grimberg } 76057dacad5SJay Sternberg } 761adf68f21SChristoph Hellwig 76283a12fb7SSagi Grimberg static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 76383a12fb7SSagi Grimberg struct nvme_completion *cqe) 76457dacad5SJay Sternberg { 76557dacad5SJay Sternberg struct request *req; 766adf68f21SChristoph Hellwig 76783a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 7681b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 769aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 77083a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 77183a12fb7SSagi Grimberg return; 772aae239e1SChristoph Hellwig } 773aae239e1SChristoph Hellwig 774adf68f21SChristoph Hellwig /* 775adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 776adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 777adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 778adf68f21SChristoph Hellwig * for them but rather special case them here. 779adf68f21SChristoph Hellwig */ 780adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 78183a12fb7SSagi Grimberg cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) { 7827bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 78383a12fb7SSagi Grimberg cqe->status, &cqe->result); 784a0fa9647SJens Axboe return; 78557dacad5SJay Sternberg } 78657dacad5SJay Sternberg 78783a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 78883a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 78983a12fb7SSagi Grimberg } 79057dacad5SJay Sternberg 791920d13a8SSagi Grimberg static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, 792920d13a8SSagi Grimberg struct nvme_completion *cqe) 79383a12fb7SSagi Grimberg { 794920d13a8SSagi Grimberg if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 795920d13a8SSagi Grimberg *cqe = nvmeq->cqes[nvmeq->cq_head]; 79683a12fb7SSagi Grimberg 797920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 798920d13a8SSagi Grimberg nvmeq->cq_head = 0; 799920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 800920d13a8SSagi Grimberg } 801920d13a8SSagi Grimberg return true; 802920d13a8SSagi Grimberg } 803920d13a8SSagi Grimberg return false; 804a0fa9647SJens Axboe } 805a0fa9647SJens Axboe 806a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 807a0fa9647SJens Axboe { 808920d13a8SSagi Grimberg struct nvme_completion cqe; 809920d13a8SSagi Grimberg int consumed = 0; 81083a12fb7SSagi Grimberg 811920d13a8SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 81283a12fb7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 813920d13a8SSagi Grimberg consumed++; 81457dacad5SJay Sternberg } 81557dacad5SJay Sternberg 816920d13a8SSagi Grimberg if (consumed) { 817eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 81857dacad5SJay Sternberg nvmeq->cqe_seen = 1; 819a0fa9647SJens Axboe } 82057dacad5SJay Sternberg } 82157dacad5SJay Sternberg 82257dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 82357dacad5SJay Sternberg { 82457dacad5SJay Sternberg irqreturn_t result; 82557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 82657dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 82757dacad5SJay Sternberg nvme_process_cq(nvmeq); 82857dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 82957dacad5SJay Sternberg nvmeq->cqe_seen = 0; 83057dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 83157dacad5SJay Sternberg return result; 83257dacad5SJay Sternberg } 83357dacad5SJay Sternberg 83457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 83557dacad5SJay Sternberg { 83657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 837d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 83857dacad5SJay Sternberg return IRQ_WAKE_THREAD; 839d783e0bdSMarta Rybczynska return IRQ_NONE; 84057dacad5SJay Sternberg } 84157dacad5SJay Sternberg 8427776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 843a0fa9647SJens Axboe { 844442e19b7SSagi Grimberg struct nvme_completion cqe; 845442e19b7SSagi Grimberg int found = 0, consumed = 0; 846a0fa9647SJens Axboe 847442e19b7SSagi Grimberg if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 848442e19b7SSagi Grimberg return 0; 849442e19b7SSagi Grimberg 850442e19b7SSagi Grimberg spin_lock_irq(&nvmeq->q_lock); 851442e19b7SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 852442e19b7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 853442e19b7SSagi Grimberg consumed++; 854442e19b7SSagi Grimberg 855442e19b7SSagi Grimberg if (tag == cqe.command_id) { 856442e19b7SSagi Grimberg found = 1; 857442e19b7SSagi Grimberg break; 858442e19b7SSagi Grimberg } 859a0fa9647SJens Axboe } 860a0fa9647SJens Axboe 861442e19b7SSagi Grimberg if (consumed) 862442e19b7SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 863442e19b7SSagi Grimberg spin_unlock_irq(&nvmeq->q_lock); 864442e19b7SSagi Grimberg 865442e19b7SSagi Grimberg return found; 866a0fa9647SJens Axboe } 867a0fa9647SJens Axboe 8687776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 8697776db1cSKeith Busch { 8707776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 8717776db1cSKeith Busch 8727776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 8737776db1cSKeith Busch } 8747776db1cSKeith Busch 875f866fc42SChristoph Hellwig static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) 87657dacad5SJay Sternberg { 877f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 8789396dec9SChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[0]; 87957dacad5SJay Sternberg struct nvme_command c; 88057dacad5SJay Sternberg 88157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 88257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 883f866fc42SChristoph Hellwig c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; 88457dacad5SJay Sternberg 8859396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 8869396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 8879396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 88857dacad5SJay Sternberg } 88957dacad5SJay Sternberg 89057dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 89157dacad5SJay Sternberg { 89257dacad5SJay Sternberg struct nvme_command c; 89357dacad5SJay Sternberg 89457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 89557dacad5SJay Sternberg c.delete_queue.opcode = opcode; 89657dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 89757dacad5SJay Sternberg 8981c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 89957dacad5SJay Sternberg } 90057dacad5SJay Sternberg 90157dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 90257dacad5SJay Sternberg struct nvme_queue *nvmeq) 90357dacad5SJay Sternberg { 90457dacad5SJay Sternberg struct nvme_command c; 90557dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 90657dacad5SJay Sternberg 90757dacad5SJay Sternberg /* 90857dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 90957dacad5SJay Sternberg * is attached to the request. 91057dacad5SJay Sternberg */ 91157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 91257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 91357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 91457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 91557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 91657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 91757dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 91857dacad5SJay Sternberg 9191c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 92057dacad5SJay Sternberg } 92157dacad5SJay Sternberg 92257dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 92357dacad5SJay Sternberg struct nvme_queue *nvmeq) 92457dacad5SJay Sternberg { 92557dacad5SJay Sternberg struct nvme_command c; 92681c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 92757dacad5SJay Sternberg 92857dacad5SJay Sternberg /* 92957dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 93057dacad5SJay Sternberg * is attached to the request. 93157dacad5SJay Sternberg */ 93257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 93357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 93457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 93557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 93657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 93757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 93857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 93957dacad5SJay Sternberg 9401c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 94157dacad5SJay Sternberg } 94257dacad5SJay Sternberg 94357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 94457dacad5SJay Sternberg { 94557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 94657dacad5SJay Sternberg } 94757dacad5SJay Sternberg 94857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 94957dacad5SJay Sternberg { 95057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 95157dacad5SJay Sternberg } 95257dacad5SJay Sternberg 9532a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 95457dacad5SJay Sternberg { 955f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 956f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 95757dacad5SJay Sternberg 95827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 95927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 960e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 961e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 96257dacad5SJay Sternberg } 96357dacad5SJay Sternberg 964b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 965b2a0eb1aSKeith Busch { 966b2a0eb1aSKeith Busch 967b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 968b2a0eb1aSKeith Busch * NVMe Subsystem reset. 969b2a0eb1aSKeith Busch */ 970b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 971b2a0eb1aSKeith Busch 972b2a0eb1aSKeith Busch /* If there is a reset ongoing, we shouldn't reset again. */ 973b2a0eb1aSKeith Busch if (dev->ctrl.state == NVME_CTRL_RESETTING) 974b2a0eb1aSKeith Busch return false; 975b2a0eb1aSKeith Busch 976b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 977b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 978b2a0eb1aSKeith Busch */ 979b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 980b2a0eb1aSKeith Busch return false; 981b2a0eb1aSKeith Busch 982b2a0eb1aSKeith Busch /* If PCI error recovery process is happening, we cannot reset or 983b2a0eb1aSKeith Busch * the recovery mechanism will surely fail. 984b2a0eb1aSKeith Busch */ 985b2a0eb1aSKeith Busch if (pci_channel_offline(to_pci_dev(dev->dev))) 986b2a0eb1aSKeith Busch return false; 987b2a0eb1aSKeith Busch 988b2a0eb1aSKeith Busch return true; 989b2a0eb1aSKeith Busch } 990b2a0eb1aSKeith Busch 991b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 992b2a0eb1aSKeith Busch { 993b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 994b2a0eb1aSKeith Busch u16 pci_status; 995b2a0eb1aSKeith Busch int result; 996b2a0eb1aSKeith Busch 997b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 998b2a0eb1aSKeith Busch &pci_status); 999b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1000b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1001b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1002b2a0eb1aSKeith Busch csts, pci_status); 1003b2a0eb1aSKeith Busch else 1004b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1005b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1006b2a0eb1aSKeith Busch csts, result); 1007b2a0eb1aSKeith Busch } 1008b2a0eb1aSKeith Busch 100931c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 101057dacad5SJay Sternberg { 1011f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1012f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 101357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 101457dacad5SJay Sternberg struct request *abort_req; 101557dacad5SJay Sternberg struct nvme_command cmd; 1016b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1017b2a0eb1aSKeith Busch 1018b2a0eb1aSKeith Busch /* 1019b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1020b2a0eb1aSKeith Busch */ 1021b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1022b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1023b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1024d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1025b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1026b2a0eb1aSKeith Busch } 102757dacad5SJay Sternberg 102831c7c7d2SChristoph Hellwig /* 10297776db1cSKeith Busch * Did we miss an interrupt? 10307776db1cSKeith Busch */ 10317776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 10327776db1cSKeith Busch dev_warn(dev->ctrl.device, 10337776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 10347776db1cSKeith Busch req->tag, nvmeq->qid); 10357776db1cSKeith Busch return BLK_EH_HANDLED; 10367776db1cSKeith Busch } 10377776db1cSKeith Busch 10387776db1cSKeith Busch /* 1039fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1040fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1041fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1042fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1043fd634f41SChristoph Hellwig */ 1044bb8d261eSChristoph Hellwig if (dev->ctrl.state == NVME_CTRL_RESETTING) { 10451b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1046fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1047fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1048a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 104927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1050fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 1051fd634f41SChristoph Hellwig } 1052fd634f41SChristoph Hellwig 1053fd634f41SChristoph Hellwig /* 1054e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1055e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1056e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 105731c7c7d2SChristoph Hellwig */ 1058f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 10591b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 106057dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 106157dacad5SJay Sternberg req->tag, nvmeq->qid); 1062a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1063d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1064e1569a16SKeith Busch 1065e1569a16SKeith Busch /* 1066e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1067e1569a16SKeith Busch * forces all outstanding requests to complete. 1068e1569a16SKeith Busch */ 106927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1070e1569a16SKeith Busch return BLK_EH_HANDLED; 107157dacad5SJay Sternberg } 107257dacad5SJay Sternberg 1073e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1074e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1075e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1076e7a2a87dSChristoph Hellwig } 10777bf7d778SKeith Busch iod->aborted = 1; 107857dacad5SJay Sternberg 107957dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 108057dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 108157dacad5SJay Sternberg cmd.abort.cid = req->tag; 108257dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 108357dacad5SJay Sternberg 10841b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 10851b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 108657dacad5SJay Sternberg req->tag, nvmeq->qid); 1087e7a2a87dSChristoph Hellwig 1088e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1089eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 10906bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 10916bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 109231c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 109357dacad5SJay Sternberg } 109457dacad5SJay Sternberg 1095e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1096e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1097e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 109857dacad5SJay Sternberg 109957dacad5SJay Sternberg /* 110057dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 110157dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 110257dacad5SJay Sternberg * as the device then is in a faulty state. 110357dacad5SJay Sternberg */ 110457dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 110557dacad5SJay Sternberg } 110657dacad5SJay Sternberg 110757dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 110857dacad5SJay Sternberg { 110957dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 111057dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 111157dacad5SJay Sternberg if (nvmeq->sq_cmds) 111257dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 111357dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 111457dacad5SJay Sternberg kfree(nvmeq); 111557dacad5SJay Sternberg } 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 111857dacad5SJay Sternberg { 111957dacad5SJay Sternberg int i; 112057dacad5SJay Sternberg 1121d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 112257dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[i]; 1123d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 112457dacad5SJay Sternberg dev->queues[i] = NULL; 112557dacad5SJay Sternberg nvme_free_queue(nvmeq); 112657dacad5SJay Sternberg } 112757dacad5SJay Sternberg } 112857dacad5SJay Sternberg 112957dacad5SJay Sternberg /** 113057dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 113157dacad5SJay Sternberg * @nvmeq - queue to suspend 113257dacad5SJay Sternberg */ 113357dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 113457dacad5SJay Sternberg { 113557dacad5SJay Sternberg int vector; 113657dacad5SJay Sternberg 113757dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 113857dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 113957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 114057dacad5SJay Sternberg return 1; 114157dacad5SJay Sternberg } 11420ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 114357dacad5SJay Sternberg nvmeq->dev->online_queues--; 114457dacad5SJay Sternberg nvmeq->cq_vector = -1; 114557dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 114657dacad5SJay Sternberg 11471c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1148c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 114957dacad5SJay Sternberg 11500ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 115157dacad5SJay Sternberg 115257dacad5SJay Sternberg return 0; 115357dacad5SJay Sternberg } 115457dacad5SJay Sternberg 1155a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 115657dacad5SJay Sternberg { 1157a5cdb68cSKeith Busch struct nvme_queue *nvmeq = dev->queues[0]; 115857dacad5SJay Sternberg 115957dacad5SJay Sternberg if (!nvmeq) 116057dacad5SJay Sternberg return; 116157dacad5SJay Sternberg if (nvme_suspend_queue(nvmeq)) 116257dacad5SJay Sternberg return; 116357dacad5SJay Sternberg 1164a5cdb68cSKeith Busch if (shutdown) 1165a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1166a5cdb68cSKeith Busch else 116720d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 116857dacad5SJay Sternberg 116957dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 117057dacad5SJay Sternberg nvme_process_cq(nvmeq); 117157dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 117257dacad5SJay Sternberg } 117357dacad5SJay Sternberg 117457dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 117557dacad5SJay Sternberg int entry_size) 117657dacad5SJay Sternberg { 117757dacad5SJay Sternberg int q_depth = dev->q_depth; 11785fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 11795fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 118057dacad5SJay Sternberg 118157dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 118257dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 11835fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 118457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 118557dacad5SJay Sternberg 118657dacad5SJay Sternberg /* 118757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 118857dacad5SJay Sternberg * would be better to map queues in system memory with the 118957dacad5SJay Sternberg * original depth 119057dacad5SJay Sternberg */ 119157dacad5SJay Sternberg if (q_depth < 64) 119257dacad5SJay Sternberg return -ENOMEM; 119357dacad5SJay Sternberg } 119457dacad5SJay Sternberg 119557dacad5SJay Sternberg return q_depth; 119657dacad5SJay Sternberg } 119757dacad5SJay Sternberg 119857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 119957dacad5SJay Sternberg int qid, int depth) 120057dacad5SJay Sternberg { 120157dacad5SJay Sternberg if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 12025fd4ce1bSChristoph Hellwig unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 12035fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 120457dacad5SJay Sternberg nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 120557dacad5SJay Sternberg nvmeq->sq_cmds_io = dev->cmb + offset; 120657dacad5SJay Sternberg } else { 120757dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 120857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 120957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 121057dacad5SJay Sternberg return -ENOMEM; 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg return 0; 121457dacad5SJay Sternberg } 121557dacad5SJay Sternberg 121657dacad5SJay Sternberg static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1217d3af3ecdSShaohua Li int depth, int node) 121857dacad5SJay Sternberg { 1219d3af3ecdSShaohua Li struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, 1220d3af3ecdSShaohua Li node); 122157dacad5SJay Sternberg if (!nvmeq) 122257dacad5SJay Sternberg return NULL; 122357dacad5SJay Sternberg 122457dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 122557dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 122657dacad5SJay Sternberg if (!nvmeq->cqes) 122757dacad5SJay Sternberg goto free_nvmeq; 122857dacad5SJay Sternberg 122957dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 123057dacad5SJay Sternberg goto free_cqdma; 123157dacad5SJay Sternberg 123257dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 123357dacad5SJay Sternberg nvmeq->dev = dev; 123457dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 123557dacad5SJay Sternberg nvmeq->cq_head = 0; 123657dacad5SJay Sternberg nvmeq->cq_phase = 1; 123757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 123857dacad5SJay Sternberg nvmeq->q_depth = depth; 123957dacad5SJay Sternberg nvmeq->qid = qid; 124057dacad5SJay Sternberg nvmeq->cq_vector = -1; 124157dacad5SJay Sternberg dev->queues[qid] = nvmeq; 1242d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 124357dacad5SJay Sternberg 124457dacad5SJay Sternberg return nvmeq; 124557dacad5SJay Sternberg 124657dacad5SJay Sternberg free_cqdma: 124757dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 124857dacad5SJay Sternberg nvmeq->cq_dma_addr); 124957dacad5SJay Sternberg free_nvmeq: 125057dacad5SJay Sternberg kfree(nvmeq); 125157dacad5SJay Sternberg return NULL; 125257dacad5SJay Sternberg } 125357dacad5SJay Sternberg 1254dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 125557dacad5SJay Sternberg { 12560ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 12570ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 12580ff199cbSChristoph Hellwig 12590ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 12600ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 12610ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12620ff199cbSChristoph Hellwig } else { 12630ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 12640ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12650ff199cbSChristoph Hellwig } 126657dacad5SJay Sternberg } 126757dacad5SJay Sternberg 126857dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 126957dacad5SJay Sternberg { 127057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 127157dacad5SJay Sternberg 127257dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 127357dacad5SJay Sternberg nvmeq->sq_tail = 0; 127457dacad5SJay Sternberg nvmeq->cq_head = 0; 127557dacad5SJay Sternberg nvmeq->cq_phase = 1; 127657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 127757dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1278f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 127957dacad5SJay Sternberg dev->online_queues++; 128057dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 128157dacad5SJay Sternberg } 128257dacad5SJay Sternberg 128357dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 128457dacad5SJay Sternberg { 128557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 128657dacad5SJay Sternberg int result; 128757dacad5SJay Sternberg 128857dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 128957dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 129057dacad5SJay Sternberg if (result < 0) 129157dacad5SJay Sternberg return result; 129257dacad5SJay Sternberg 129357dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 129457dacad5SJay Sternberg if (result < 0) 129557dacad5SJay Sternberg goto release_cq; 129657dacad5SJay Sternberg 1297dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 129857dacad5SJay Sternberg if (result < 0) 129957dacad5SJay Sternberg goto release_sq; 130057dacad5SJay Sternberg 130157dacad5SJay Sternberg nvme_init_queue(nvmeq, qid); 130257dacad5SJay Sternberg return result; 130357dacad5SJay Sternberg 130457dacad5SJay Sternberg release_sq: 130557dacad5SJay Sternberg adapter_delete_sq(dev, qid); 130657dacad5SJay Sternberg release_cq: 130757dacad5SJay Sternberg adapter_delete_cq(dev, qid); 130857dacad5SJay Sternberg return result; 130957dacad5SJay Sternberg } 131057dacad5SJay Sternberg 1311f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 131257dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 131377f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 131457dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 131557dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 13160350815aSChristoph Hellwig .init_request = nvme_init_request, 131757dacad5SJay Sternberg .timeout = nvme_timeout, 131857dacad5SJay Sternberg }; 131957dacad5SJay Sternberg 1320f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 132157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 132277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 132357dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 132457dacad5SJay Sternberg .init_request = nvme_init_request, 1325dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 132657dacad5SJay Sternberg .timeout = nvme_timeout, 1327a0fa9647SJens Axboe .poll = nvme_poll, 132857dacad5SJay Sternberg }; 132957dacad5SJay Sternberg 133057dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 133157dacad5SJay Sternberg { 13321c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 133369d9a99cSKeith Busch /* 133469d9a99cSKeith Busch * If the controller was reset during removal, it's possible 133569d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 133669d9a99cSKeith Busch * queue to flush these to completion. 133769d9a99cSKeith Busch */ 1338c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 13391c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 134057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 134157dacad5SJay Sternberg } 134257dacad5SJay Sternberg } 134357dacad5SJay Sternberg 134457dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 134557dacad5SJay Sternberg { 13461c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 134757dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 134857dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1349e3e9d50cSKeith Busch 1350e3e9d50cSKeith Busch /* 1351e3e9d50cSKeith Busch * Subtract one to leave an empty queue entry for 'Full Queue' 1352e3e9d50cSKeith Busch * condition. See NVM-Express 1.2 specification, section 4.1.2. 1353e3e9d50cSKeith Busch */ 1354e3e9d50cSKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; 135557dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 135657dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 135757dacad5SJay Sternberg dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1358d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 135957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 136057dacad5SJay Sternberg 136157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 136257dacad5SJay Sternberg return -ENOMEM; 136357dacad5SJay Sternberg 13641c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 13651c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 136657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 136757dacad5SJay Sternberg return -ENOMEM; 136857dacad5SJay Sternberg } 13691c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 137057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 13711c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 137257dacad5SJay Sternberg return -ENODEV; 137357dacad5SJay Sternberg } 137457dacad5SJay Sternberg } else 1375c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 137657dacad5SJay Sternberg 137757dacad5SJay Sternberg return 0; 137857dacad5SJay Sternberg } 137957dacad5SJay Sternberg 138097f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 138197f6ef64SXu Yu { 138297f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 138397f6ef64SXu Yu } 138497f6ef64SXu Yu 138597f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 138697f6ef64SXu Yu { 138797f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 138897f6ef64SXu Yu 138997f6ef64SXu Yu if (size <= dev->bar_mapped_size) 139097f6ef64SXu Yu return 0; 139197f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 139297f6ef64SXu Yu return -ENOMEM; 139397f6ef64SXu Yu if (dev->bar) 139497f6ef64SXu Yu iounmap(dev->bar); 139597f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 139697f6ef64SXu Yu if (!dev->bar) { 139797f6ef64SXu Yu dev->bar_mapped_size = 0; 139897f6ef64SXu Yu return -ENOMEM; 139997f6ef64SXu Yu } 140097f6ef64SXu Yu dev->bar_mapped_size = size; 140197f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 140297f6ef64SXu Yu 140397f6ef64SXu Yu return 0; 140497f6ef64SXu Yu } 140597f6ef64SXu Yu 140601ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 140757dacad5SJay Sternberg { 140857dacad5SJay Sternberg int result; 140957dacad5SJay Sternberg u32 aqa; 141057dacad5SJay Sternberg struct nvme_queue *nvmeq; 141157dacad5SJay Sternberg 141297f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 141397f6ef64SXu Yu if (result < 0) 141497f6ef64SXu Yu return result; 141597f6ef64SXu Yu 14168ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 141720d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 141857dacad5SJay Sternberg 14197a67cbeaSChristoph Hellwig if (dev->subsystem && 14207a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 14217a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 142257dacad5SJay Sternberg 142320d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 142457dacad5SJay Sternberg if (result < 0) 142557dacad5SJay Sternberg return result; 142657dacad5SJay Sternberg 142757dacad5SJay Sternberg nvmeq = dev->queues[0]; 142857dacad5SJay Sternberg if (!nvmeq) { 1429d3af3ecdSShaohua Li nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1430d3af3ecdSShaohua Li dev_to_node(dev->dev)); 143157dacad5SJay Sternberg if (!nvmeq) 143257dacad5SJay Sternberg return -ENOMEM; 143357dacad5SJay Sternberg } 143457dacad5SJay Sternberg 143557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 143657dacad5SJay Sternberg aqa |= aqa << 16; 143757dacad5SJay Sternberg 14387a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 14397a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 14407a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 144157dacad5SJay Sternberg 144220d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 144357dacad5SJay Sternberg if (result) 1444d4875622SKeith Busch return result; 144557dacad5SJay Sternberg 144657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1447dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 144857dacad5SJay Sternberg if (result) { 144957dacad5SJay Sternberg nvmeq->cq_vector = -1; 1450d4875622SKeith Busch return result; 145157dacad5SJay Sternberg } 145257dacad5SJay Sternberg 145357dacad5SJay Sternberg return result; 145457dacad5SJay Sternberg } 145557dacad5SJay Sternberg 1456749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 145757dacad5SJay Sternberg { 1458949928c1SKeith Busch unsigned i, max; 1459749941f2SChristoph Hellwig int ret = 0; 146057dacad5SJay Sternberg 1461d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1462d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1463d3af3ecdSShaohua Li if (!nvme_alloc_queue(dev, i, dev->q_depth, 1464d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1465749941f2SChristoph Hellwig ret = -ENOMEM; 146657dacad5SJay Sternberg break; 1467749941f2SChristoph Hellwig } 1468749941f2SChristoph Hellwig } 146957dacad5SJay Sternberg 1470d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1471949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1472749941f2SChristoph Hellwig ret = nvme_create_queue(dev->queues[i], i); 1473d4875622SKeith Busch if (ret) 147457dacad5SJay Sternberg break; 147557dacad5SJay Sternberg } 147657dacad5SJay Sternberg 1477749941f2SChristoph Hellwig /* 1478749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 1479749941f2SChristoph Hellwig * than the desired aount of queues, and even a controller without 1480749941f2SChristoph Hellwig * I/O queues an still be used to issue admin commands. This might 1481749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1482749941f2SChristoph Hellwig */ 1483749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 148457dacad5SJay Sternberg } 148557dacad5SJay Sternberg 1486202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1487202021c1SStephen Bates struct device_attribute *attr, 1488202021c1SStephen Bates char *buf) 1489202021c1SStephen Bates { 1490202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1491202021c1SStephen Bates 1492c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1493202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1494202021c1SStephen Bates } 1495202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1496202021c1SStephen Bates 149757dacad5SJay Sternberg static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 149857dacad5SJay Sternberg { 149957dacad5SJay Sternberg u64 szu, size, offset; 150057dacad5SJay Sternberg resource_size_t bar_size; 150157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 150257dacad5SJay Sternberg void __iomem *cmb; 150357dacad5SJay Sternberg dma_addr_t dma_addr; 150457dacad5SJay Sternberg 15057a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 150657dacad5SJay Sternberg if (!(NVME_CMB_SZ(dev->cmbsz))) 150757dacad5SJay Sternberg return NULL; 1508202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 150957dacad5SJay Sternberg 1510202021c1SStephen Bates if (!use_cmb_sqes) 1511202021c1SStephen Bates return NULL; 151257dacad5SJay Sternberg 151357dacad5SJay Sternberg szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 151457dacad5SJay Sternberg size = szu * NVME_CMB_SZ(dev->cmbsz); 1515202021c1SStephen Bates offset = szu * NVME_CMB_OFST(dev->cmbloc); 1516202021c1SStephen Bates bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 151757dacad5SJay Sternberg 151857dacad5SJay Sternberg if (offset > bar_size) 151957dacad5SJay Sternberg return NULL; 152057dacad5SJay Sternberg 152157dacad5SJay Sternberg /* 152257dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 152357dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 152457dacad5SJay Sternberg * the reported size of the BAR 152557dacad5SJay Sternberg */ 152657dacad5SJay Sternberg if (size > bar_size - offset) 152757dacad5SJay Sternberg size = bar_size - offset; 152857dacad5SJay Sternberg 1529202021c1SStephen Bates dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 153057dacad5SJay Sternberg cmb = ioremap_wc(dma_addr, size); 153157dacad5SJay Sternberg if (!cmb) 153257dacad5SJay Sternberg return NULL; 153357dacad5SJay Sternberg 153457dacad5SJay Sternberg dev->cmb_dma_addr = dma_addr; 153557dacad5SJay Sternberg dev->cmb_size = size; 153657dacad5SJay Sternberg return cmb; 153757dacad5SJay Sternberg } 153857dacad5SJay Sternberg 153957dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 154057dacad5SJay Sternberg { 154157dacad5SJay Sternberg if (dev->cmb) { 154257dacad5SJay Sternberg iounmap(dev->cmb); 154357dacad5SJay Sternberg dev->cmb = NULL; 1544f63572dfSJon Derrick if (dev->cmbsz) { 1545f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1546f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1547f63572dfSJon Derrick dev->cmbsz = 0; 1548f63572dfSJon Derrick } 154957dacad5SJay Sternberg } 155057dacad5SJay Sternberg } 155157dacad5SJay Sternberg 155287ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 155357dacad5SJay Sternberg { 155487ad72a5SChristoph Hellwig size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); 155587ad72a5SChristoph Hellwig struct nvme_command c; 155687ad72a5SChristoph Hellwig u64 dma_addr; 155787ad72a5SChristoph Hellwig int ret; 155887ad72a5SChristoph Hellwig 155987ad72a5SChristoph Hellwig dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, 156087ad72a5SChristoph Hellwig DMA_TO_DEVICE); 156187ad72a5SChristoph Hellwig if (dma_mapping_error(dev->dev, dma_addr)) 156287ad72a5SChristoph Hellwig return -ENOMEM; 156387ad72a5SChristoph Hellwig 156487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 156587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 156687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 156787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 156887ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 156987ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 157087ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 157187ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 157287ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 157387ad72a5SChristoph Hellwig 157487ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 157587ad72a5SChristoph Hellwig if (ret) { 157687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 157787ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 157887ad72a5SChristoph Hellwig ret, bits); 157987ad72a5SChristoph Hellwig } 158087ad72a5SChristoph Hellwig dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); 158187ad72a5SChristoph Hellwig return ret; 158287ad72a5SChristoph Hellwig } 158387ad72a5SChristoph Hellwig 158487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 158587ad72a5SChristoph Hellwig { 158687ad72a5SChristoph Hellwig int i; 158787ad72a5SChristoph Hellwig 158887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 158987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 159087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 159187ad72a5SChristoph Hellwig 159287ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 159387ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 159487ad72a5SChristoph Hellwig } 159587ad72a5SChristoph Hellwig 159687ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 159787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 159887ad72a5SChristoph Hellwig kfree(dev->host_mem_descs); 159987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 160087ad72a5SChristoph Hellwig } 160187ad72a5SChristoph Hellwig 160287ad72a5SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 160387ad72a5SChristoph Hellwig { 160487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 16052ee0e4edSDan Carpenter u32 chunk_size, max_entries; 16062ee0e4edSDan Carpenter int i = 0; 160787ad72a5SChristoph Hellwig void **bufs; 16082ee0e4edSDan Carpenter u64 size = 0, tmp; 160987ad72a5SChristoph Hellwig 161087ad72a5SChristoph Hellwig /* start big and work our way down */ 161187ad72a5SChristoph Hellwig chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); 161287ad72a5SChristoph Hellwig retry: 161387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 161487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 161587ad72a5SChristoph Hellwig max_entries = tmp; 161687ad72a5SChristoph Hellwig descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); 161787ad72a5SChristoph Hellwig if (!descs) 161887ad72a5SChristoph Hellwig goto out; 161987ad72a5SChristoph Hellwig 162087ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 162187ad72a5SChristoph Hellwig if (!bufs) 162287ad72a5SChristoph Hellwig goto out_free_descs; 162387ad72a5SChristoph Hellwig 162487ad72a5SChristoph Hellwig for (size = 0; size < preferred; size += chunk_size) { 162587ad72a5SChristoph Hellwig u32 len = min_t(u64, chunk_size, preferred - size); 162687ad72a5SChristoph Hellwig dma_addr_t dma_addr; 162787ad72a5SChristoph Hellwig 162887ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 162987ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 163087ad72a5SChristoph Hellwig if (!bufs[i]) 163187ad72a5SChristoph Hellwig break; 163287ad72a5SChristoph Hellwig 163387ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 163487ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 163587ad72a5SChristoph Hellwig i++; 163687ad72a5SChristoph Hellwig } 163787ad72a5SChristoph Hellwig 163887ad72a5SChristoph Hellwig if (!size || (min && size < min)) { 163987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 164087ad72a5SChristoph Hellwig "failed to allocate host memory buffer.\n"); 164187ad72a5SChristoph Hellwig goto out_free_bufs; 164287ad72a5SChristoph Hellwig } 164387ad72a5SChristoph Hellwig 164487ad72a5SChristoph Hellwig dev_info(dev->ctrl.device, 164587ad72a5SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 164687ad72a5SChristoph Hellwig size >> ilog2(SZ_1M)); 164787ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 164887ad72a5SChristoph Hellwig dev->host_mem_size = size; 164987ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 165087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 165187ad72a5SChristoph Hellwig return 0; 165287ad72a5SChristoph Hellwig 165387ad72a5SChristoph Hellwig out_free_bufs: 165487ad72a5SChristoph Hellwig while (--i >= 0) { 165587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 165687ad72a5SChristoph Hellwig 165787ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 165887ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 165987ad72a5SChristoph Hellwig } 166087ad72a5SChristoph Hellwig 166187ad72a5SChristoph Hellwig kfree(bufs); 166287ad72a5SChristoph Hellwig out_free_descs: 166387ad72a5SChristoph Hellwig kfree(descs); 166487ad72a5SChristoph Hellwig out: 166587ad72a5SChristoph Hellwig /* try a smaller chunk size if we failed early */ 166687ad72a5SChristoph Hellwig if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { 166787ad72a5SChristoph Hellwig chunk_size /= 2; 166887ad72a5SChristoph Hellwig goto retry; 166987ad72a5SChristoph Hellwig } 167087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 167187ad72a5SChristoph Hellwig return -ENOMEM; 167287ad72a5SChristoph Hellwig } 167387ad72a5SChristoph Hellwig 167487ad72a5SChristoph Hellwig static void nvme_setup_host_mem(struct nvme_dev *dev) 167587ad72a5SChristoph Hellwig { 167687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 167787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 167887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 167987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 168087ad72a5SChristoph Hellwig 168187ad72a5SChristoph Hellwig preferred = min(preferred, max); 168287ad72a5SChristoph Hellwig if (min > max) { 168387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 168487ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 168587ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 168687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 168787ad72a5SChristoph Hellwig return; 168887ad72a5SChristoph Hellwig } 168987ad72a5SChristoph Hellwig 169087ad72a5SChristoph Hellwig /* 169187ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 169287ad72a5SChristoph Hellwig */ 169387ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 169487ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 169587ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 169687ad72a5SChristoph Hellwig else 169787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 169887ad72a5SChristoph Hellwig } 169987ad72a5SChristoph Hellwig 170087ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 170187ad72a5SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) 170287ad72a5SChristoph Hellwig return; 170387ad72a5SChristoph Hellwig } 170487ad72a5SChristoph Hellwig 170587ad72a5SChristoph Hellwig if (nvme_set_host_mem(dev, enable_bits)) 170687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 170757dacad5SJay Sternberg } 170857dacad5SJay Sternberg 170957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 171057dacad5SJay Sternberg { 171157dacad5SJay Sternberg struct nvme_queue *adminq = dev->queues[0]; 171257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 171397f6ef64SXu Yu int result, nr_io_queues; 171497f6ef64SXu Yu unsigned long size; 171557dacad5SJay Sternberg 1716425a17cbSChristoph Hellwig nr_io_queues = num_present_cpus(); 17179a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 17189a0be7abSChristoph Hellwig if (result < 0) 171957dacad5SJay Sternberg return result; 17209a0be7abSChristoph Hellwig 1721f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1722a5229050SKeith Busch return 0; 172357dacad5SJay Sternberg 172457dacad5SJay Sternberg if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 172557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 172657dacad5SJay Sternberg sizeof(struct nvme_command)); 172757dacad5SJay Sternberg if (result > 0) 172857dacad5SJay Sternberg dev->q_depth = result; 172957dacad5SJay Sternberg else 173057dacad5SJay Sternberg nvme_release_cmb(dev); 173157dacad5SJay Sternberg } 173257dacad5SJay Sternberg 173357dacad5SJay Sternberg do { 173497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 173597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 173697f6ef64SXu Yu if (!result) 173757dacad5SJay Sternberg break; 173857dacad5SJay Sternberg if (!--nr_io_queues) 173957dacad5SJay Sternberg return -ENOMEM; 174057dacad5SJay Sternberg } while (1); 174157dacad5SJay Sternberg adminq->q_db = dev->dbs; 174257dacad5SJay Sternberg 174357dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 17440ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 174557dacad5SJay Sternberg 174657dacad5SJay Sternberg /* 174757dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 174857dacad5SJay Sternberg * setting up the full range we need. 174957dacad5SJay Sternberg */ 1750dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1751dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1752dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1753dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1754dca51e78SChristoph Hellwig return -EIO; 1755dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 175657dacad5SJay Sternberg 175757dacad5SJay Sternberg /* 175857dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 175957dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 176057dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 176157dacad5SJay Sternberg * number of interrupts. 176257dacad5SJay Sternberg */ 176357dacad5SJay Sternberg 1764dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 176557dacad5SJay Sternberg if (result) { 176657dacad5SJay Sternberg adminq->cq_vector = -1; 1767d4875622SKeith Busch return result; 176857dacad5SJay Sternberg } 1769749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 177057dacad5SJay Sternberg } 177157dacad5SJay Sternberg 17722a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1773db3cbfffSKeith Busch { 1774db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1775db3cbfffSKeith Busch 1776db3cbfffSKeith Busch blk_mq_free_request(req); 1777db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1778db3cbfffSKeith Busch } 1779db3cbfffSKeith Busch 17802a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1781db3cbfffSKeith Busch { 1782db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1783db3cbfffSKeith Busch 1784db3cbfffSKeith Busch if (!error) { 1785db3cbfffSKeith Busch unsigned long flags; 1786db3cbfffSKeith Busch 17872e39e0f6SMing Lin /* 17882e39e0f6SMing Lin * We might be called with the AQ q_lock held 17892e39e0f6SMing Lin * and the I/O queue q_lock should always 17902e39e0f6SMing Lin * nest inside the AQ one. 17912e39e0f6SMing Lin */ 17922e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 17932e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1794db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1795db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1796db3cbfffSKeith Busch } 1797db3cbfffSKeith Busch 1798db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1799db3cbfffSKeith Busch } 1800db3cbfffSKeith Busch 1801db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1802db3cbfffSKeith Busch { 1803db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1804db3cbfffSKeith Busch struct request *req; 1805db3cbfffSKeith Busch struct nvme_command cmd; 1806db3cbfffSKeith Busch 1807db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1808db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1809db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1810db3cbfffSKeith Busch 1811eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1812db3cbfffSKeith Busch if (IS_ERR(req)) 1813db3cbfffSKeith Busch return PTR_ERR(req); 1814db3cbfffSKeith Busch 1815db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1816db3cbfffSKeith Busch req->end_io_data = nvmeq; 1817db3cbfffSKeith Busch 1818db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1819db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1820db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1821db3cbfffSKeith Busch return 0; 1822db3cbfffSKeith Busch } 1823db3cbfffSKeith Busch 182470659060SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1825db3cbfffSKeith Busch { 182670659060SKeith Busch int pass; 1827db3cbfffSKeith Busch unsigned long timeout; 1828db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 1829db3cbfffSKeith Busch 1830db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 1831014a0d60SKeith Busch int sent = 0, i = queues; 1832db3cbfffSKeith Busch 1833db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 1834db3cbfffSKeith Busch retry: 1835db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 1836c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 1837c21377f8SGabriel Krisman Bertazi if (nvme_delete_queue(dev->queues[i], opcode)) 1838db3cbfffSKeith Busch break; 1839c21377f8SGabriel Krisman Bertazi 1840db3cbfffSKeith Busch while (sent--) { 1841db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 1842db3cbfffSKeith Busch if (timeout == 0) 1843db3cbfffSKeith Busch return; 1844db3cbfffSKeith Busch if (i) 1845db3cbfffSKeith Busch goto retry; 1846db3cbfffSKeith Busch } 1847db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 1848db3cbfffSKeith Busch } 1849db3cbfffSKeith Busch } 1850db3cbfffSKeith Busch 185157dacad5SJay Sternberg /* 185257dacad5SJay Sternberg * Return: error value if an error occurred setting up the queues or calling 185357dacad5SJay Sternberg * Identify Device. 0 if these succeeded, even if adding some of the 185457dacad5SJay Sternberg * namespaces failed. At the moment, these failures are silent. TBD which 185557dacad5SJay Sternberg * failures should be reported. 185657dacad5SJay Sternberg */ 185757dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 185857dacad5SJay Sternberg { 18595bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 186057dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 186157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 186257dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 186357dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 186457dacad5SJay Sternberg dev->tagset.queue_depth = 186557dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 186657dacad5SJay Sternberg dev->tagset.cmd_size = nvme_cmd_size(dev); 186757dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 186857dacad5SJay Sternberg dev->tagset.driver_data = dev; 186957dacad5SJay Sternberg 187057dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->tagset)) 187157dacad5SJay Sternberg return 0; 18725bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 1873f9f38e33SHelen Koike 1874f9f38e33SHelen Koike nvme_dbbuf_set(dev); 1875949928c1SKeith Busch } else { 1876949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 1877949928c1SKeith Busch 1878949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 1879949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 188057dacad5SJay Sternberg } 1881949928c1SKeith Busch 188257dacad5SJay Sternberg return 0; 188357dacad5SJay Sternberg } 188457dacad5SJay Sternberg 1885b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 188657dacad5SJay Sternberg { 1887b00a726aSKeith Busch int result = -ENOMEM; 188857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 188957dacad5SJay Sternberg 189057dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 189157dacad5SJay Sternberg return result; 189257dacad5SJay Sternberg 189357dacad5SJay Sternberg pci_set_master(pdev); 189457dacad5SJay Sternberg 189557dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 189657dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 189757dacad5SJay Sternberg goto disable; 189857dacad5SJay Sternberg 18997a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 190057dacad5SJay Sternberg result = -ENODEV; 1901b00a726aSKeith Busch goto disable; 190257dacad5SJay Sternberg } 190357dacad5SJay Sternberg 190457dacad5SJay Sternberg /* 1905a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 1906a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 1907a5229050SKeith Busch * adjust this later. 190857dacad5SJay Sternberg */ 1909dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1910dca51e78SChristoph Hellwig if (result < 0) 1911dca51e78SChristoph Hellwig return result; 191257dacad5SJay Sternberg 191320d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 19147a67cbeaSChristoph Hellwig 191520d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 1916b27c1e68Sweiping zhang io_queue_depth); 191720d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 19187a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 19191f390c1fSStephan Günther 19201f390c1fSStephan Günther /* 19211f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 19221f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 19231f390c1fSStephan Günther */ 19241f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 19251f390c1fSStephan Günther dev->q_depth = 2; 19269bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 19279bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 19281f390c1fSStephan Günther dev->q_depth); 1929d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 1930d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 193120d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 1932d554b5e1SMartin K. Petersen dev->q_depth = 64; 1933d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 1934d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 19351f390c1fSStephan Günther } 19361f390c1fSStephan Günther 1937202021c1SStephen Bates /* 1938202021c1SStephen Bates * CMBs can currently only exist on >=1.2 PCIe devices. We only 1939202021c1SStephen Bates * populate sysfs if a CMB is implemented. Note that we add the 1940202021c1SStephen Bates * CMB attribute to the nvme_ctrl kobj which removes the need to remove 1941202021c1SStephen Bates * it on exit. Since nvme_dev_attrs_group has no name we can pass 1942202021c1SStephen Bates * NULL as final argument to sysfs_add_file_to_group. 1943202021c1SStephen Bates */ 1944202021c1SStephen Bates 19458ef2074dSGabriel Krisman Bertazi if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 194657dacad5SJay Sternberg dev->cmb = nvme_map_cmb(dev); 194757dacad5SJay Sternberg 1948202021c1SStephen Bates if (dev->cmbsz) { 1949202021c1SStephen Bates if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1950202021c1SStephen Bates &dev_attr_cmb.attr, NULL)) 19519bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1952202021c1SStephen Bates "failed to add sysfs attribute for CMB\n"); 1953202021c1SStephen Bates } 1954202021c1SStephen Bates } 1955202021c1SStephen Bates 1956a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 1957a0a3408eSKeith Busch pci_save_state(pdev); 195857dacad5SJay Sternberg return 0; 195957dacad5SJay Sternberg 196057dacad5SJay Sternberg disable: 196157dacad5SJay Sternberg pci_disable_device(pdev); 196257dacad5SJay Sternberg return result; 196357dacad5SJay Sternberg } 196457dacad5SJay Sternberg 196557dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 196657dacad5SJay Sternberg { 1967b00a726aSKeith Busch if (dev->bar) 1968b00a726aSKeith Busch iounmap(dev->bar); 1969a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 1970b00a726aSKeith Busch } 1971b00a726aSKeith Busch 1972b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 1973b00a726aSKeith Busch { 197457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 197557dacad5SJay Sternberg 1976f63572dfSJon Derrick nvme_release_cmb(dev); 1977dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 197857dacad5SJay Sternberg 1979a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 1980a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 198157dacad5SJay Sternberg pci_disable_device(pdev); 198257dacad5SJay Sternberg } 1983a0a3408eSKeith Busch } 198457dacad5SJay Sternberg 1985a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 198657dacad5SJay Sternberg { 198770659060SKeith Busch int i, queues; 1988302ad8ccSKeith Busch bool dead = true; 1989302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 199057dacad5SJay Sternberg 199177bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 1992302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 1993302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1994302ad8ccSKeith Busch 1995ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 1996ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 1997302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 1998302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 1999302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 200057dacad5SJay Sternberg } 2001c21377f8SGabriel Krisman Bertazi 2002302ad8ccSKeith Busch /* 2003302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2004302ad8ccSKeith Busch * doing a safe shutdown. 2005302ad8ccSKeith Busch */ 200687ad72a5SChristoph Hellwig if (!dead) { 200787ad72a5SChristoph Hellwig if (shutdown) 2008302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 200987ad72a5SChristoph Hellwig 201087ad72a5SChristoph Hellwig /* 201187ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 201287ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 201387ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 201487ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 201587ad72a5SChristoph Hellwig */ 201687ad72a5SChristoph Hellwig if (dev->host_mem_descs) 201787ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 201887ad72a5SChristoph Hellwig 201987ad72a5SChristoph Hellwig } 2020302ad8ccSKeith Busch nvme_stop_queues(&dev->ctrl); 2021302ad8ccSKeith Busch 202270659060SKeith Busch queues = dev->online_queues - 1; 2023d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i > 0; i--) 2024c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[i]); 2025c21377f8SGabriel Krisman Bertazi 2026302ad8ccSKeith Busch if (dead) { 202782469c59SGabriel Krisman Bertazi /* A device might become IO incapable very soon during 202882469c59SGabriel Krisman Bertazi * probe, before the admin queue is configured. Thus, 202982469c59SGabriel Krisman Bertazi * queue_count can be 0 here. 203082469c59SGabriel Krisman Bertazi */ 2031d858e5f0SSagi Grimberg if (dev->ctrl.queue_count) 2032c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[0]); 203357dacad5SJay Sternberg } else { 203470659060SKeith Busch nvme_disable_io_queues(dev, queues); 2035a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 203657dacad5SJay Sternberg } 2037b00a726aSKeith Busch nvme_pci_disable(dev); 203857dacad5SJay Sternberg 2039e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2040e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2041302ad8ccSKeith Busch 2042302ad8ccSKeith Busch /* 2043302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2044302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2045302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2046302ad8ccSKeith Busch */ 2047302ad8ccSKeith Busch if (shutdown) 2048302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 204977bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 205057dacad5SJay Sternberg } 205157dacad5SJay Sternberg 205257dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 205357dacad5SJay Sternberg { 205457dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 205557dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 205657dacad5SJay Sternberg if (!dev->prp_page_pool) 205757dacad5SJay Sternberg return -ENOMEM; 205857dacad5SJay Sternberg 205957dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 206057dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 206157dacad5SJay Sternberg 256, 256, 0); 206257dacad5SJay Sternberg if (!dev->prp_small_pool) { 206357dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 206457dacad5SJay Sternberg return -ENOMEM; 206557dacad5SJay Sternberg } 206657dacad5SJay Sternberg return 0; 206757dacad5SJay Sternberg } 206857dacad5SJay Sternberg 206957dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 207057dacad5SJay Sternberg { 207157dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 207257dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 207357dacad5SJay Sternberg } 207457dacad5SJay Sternberg 20751673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 207657dacad5SJay Sternberg { 20771673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 207857dacad5SJay Sternberg 2079f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 208057dacad5SJay Sternberg put_device(dev->dev); 208157dacad5SJay Sternberg if (dev->tagset.tags) 208257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 20831c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 20841c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 208557dacad5SJay Sternberg kfree(dev->queues); 2086e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 208757dacad5SJay Sternberg kfree(dev); 208857dacad5SJay Sternberg } 208957dacad5SJay Sternberg 2090f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2091f58944e2SKeith Busch { 2092237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2093f58944e2SKeith Busch 2094f58944e2SKeith Busch kref_get(&dev->ctrl.kref); 209569d9a99cSKeith Busch nvme_dev_disable(dev, false); 2096f58944e2SKeith Busch if (!schedule_work(&dev->remove_work)) 2097f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2098f58944e2SKeith Busch } 2099f58944e2SKeith Busch 2100fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 210157dacad5SJay Sternberg { 2102d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2103d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2104a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2105f58944e2SKeith Busch int result = -ENODEV; 210657dacad5SJay Sternberg 210782b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2108fd634f41SChristoph Hellwig goto out; 2109fd634f41SChristoph Hellwig 2110fd634f41SChristoph Hellwig /* 2111fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2112fd634f41SChristoph Hellwig * moving on. 2113fd634f41SChristoph Hellwig */ 2114b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2115a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2116fd634f41SChristoph Hellwig 2117b00a726aSKeith Busch result = nvme_pci_enable(dev); 211857dacad5SJay Sternberg if (result) 211957dacad5SJay Sternberg goto out; 212057dacad5SJay Sternberg 212101ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 212257dacad5SJay Sternberg if (result) 2123f58944e2SKeith Busch goto out; 212457dacad5SJay Sternberg 212557dacad5SJay Sternberg nvme_init_queue(dev->queues[0], 0); 212657dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 212757dacad5SJay Sternberg if (result) 2128f58944e2SKeith Busch goto out; 212957dacad5SJay Sternberg 2130ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2131ce4541f4SChristoph Hellwig if (result) 2132f58944e2SKeith Busch goto out; 2133ce4541f4SChristoph Hellwig 2134e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2135e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 21364f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 21374f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2138e286bcfcSScott Bauer else if (was_suspend) 21394f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2140e286bcfcSScott Bauer } else { 2141e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2142e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2143e286bcfcSScott Bauer } 2144a98e58e5SScott Bauer 2145f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2146f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2147f9f38e33SHelen Koike if (result) 2148f9f38e33SHelen Koike dev_warn(dev->dev, 2149f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2150f9f38e33SHelen Koike } 2151f9f38e33SHelen Koike 215287ad72a5SChristoph Hellwig if (dev->ctrl.hmpre) 215387ad72a5SChristoph Hellwig nvme_setup_host_mem(dev); 215487ad72a5SChristoph Hellwig 215557dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 215657dacad5SJay Sternberg if (result) 2157f58944e2SKeith Busch goto out; 215857dacad5SJay Sternberg 215921f033f7SKeith Busch /* 216057dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 216157dacad5SJay Sternberg * any working I/O queue. 216257dacad5SJay Sternberg */ 216357dacad5SJay Sternberg if (dev->online_queues < 2) { 21641b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 21653b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 21665bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 216757dacad5SJay Sternberg } else { 216825646264SKeith Busch nvme_start_queues(&dev->ctrl); 2169302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 217057dacad5SJay Sternberg nvme_dev_add(dev); 2171302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 217257dacad5SJay Sternberg } 217357dacad5SJay Sternberg 2174bb8d261eSChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2175bb8d261eSChristoph Hellwig dev_warn(dev->ctrl.device, "failed to mark controller live\n"); 2176bb8d261eSChristoph Hellwig goto out; 2177bb8d261eSChristoph Hellwig } 217892911a55SChristoph Hellwig 2179d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 218057dacad5SJay Sternberg return; 218157dacad5SJay Sternberg 218257dacad5SJay Sternberg out: 2183f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 218457dacad5SJay Sternberg } 218557dacad5SJay Sternberg 21865c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 218757dacad5SJay Sternberg { 21885c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 218957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 219057dacad5SJay Sternberg 219169d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 219257dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2193921920abSKeith Busch device_release_driver(&pdev->dev); 21941673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 219557dacad5SJay Sternberg } 219657dacad5SJay Sternberg 21971c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 219857dacad5SJay Sternberg { 21991c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 22001c63dc66SChristoph Hellwig return 0; 220157dacad5SJay Sternberg } 22021c63dc66SChristoph Hellwig 22035fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 22045fd4ce1bSChristoph Hellwig { 22055fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 22065fd4ce1bSChristoph Hellwig return 0; 22075fd4ce1bSChristoph Hellwig } 22085fd4ce1bSChristoph Hellwig 22097fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 22107fd8930fSChristoph Hellwig { 22117fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 22127fd8930fSChristoph Hellwig return 0; 22137fd8930fSChristoph Hellwig } 22147fd8930fSChristoph Hellwig 22151c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 22161a353d85SMing Lin .name = "pcie", 2217e439bb12SSagi Grimberg .module = THIS_MODULE, 2218c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 22191c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 22205fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 22217fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 22221673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2223f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 22241c63dc66SChristoph Hellwig }; 222557dacad5SJay Sternberg 2226b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2227b00a726aSKeith Busch { 2228b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2229b00a726aSKeith Busch 2230a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2231b00a726aSKeith Busch return -ENODEV; 2232b00a726aSKeith Busch 223397f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2234b00a726aSKeith Busch goto release; 2235b00a726aSKeith Busch 2236b00a726aSKeith Busch return 0; 2237b00a726aSKeith Busch release: 2238a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2239b00a726aSKeith Busch return -ENODEV; 2240b00a726aSKeith Busch } 2241b00a726aSKeith Busch 2242ff5350a8SAndy Lutomirski static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) 2243ff5350a8SAndy Lutomirski { 2244ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2245ff5350a8SAndy Lutomirski /* 2246ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2247ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2248ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2249ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2250ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2251ff5350a8SAndy Lutomirski * laptops. 2252ff5350a8SAndy Lutomirski */ 2253ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2254ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2255ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2256ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 2257ff5350a8SAndy Lutomirski } 2258ff5350a8SAndy Lutomirski 2259ff5350a8SAndy Lutomirski return 0; 2260ff5350a8SAndy Lutomirski } 2261ff5350a8SAndy Lutomirski 226257dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 226357dacad5SJay Sternberg { 226457dacad5SJay Sternberg int node, result = -ENOMEM; 226557dacad5SJay Sternberg struct nvme_dev *dev; 2266ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 226757dacad5SJay Sternberg 226857dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 226957dacad5SJay Sternberg if (node == NUMA_NO_NODE) 22702fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 227157dacad5SJay Sternberg 227257dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 227357dacad5SJay Sternberg if (!dev) 227457dacad5SJay Sternberg return -ENOMEM; 227557dacad5SJay Sternberg dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 227657dacad5SJay Sternberg GFP_KERNEL, node); 227757dacad5SJay Sternberg if (!dev->queues) 227857dacad5SJay Sternberg goto free; 227957dacad5SJay Sternberg 228057dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 228157dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 228257dacad5SJay Sternberg 2283b00a726aSKeith Busch result = nvme_dev_map(dev); 2284b00a726aSKeith Busch if (result) 2285b00a726aSKeith Busch goto free; 2286b00a726aSKeith Busch 2287d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 22885c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 228977bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2290db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2291f3ca80fcSChristoph Hellwig 2292f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2293f3ca80fcSChristoph Hellwig if (result) 2294f3ca80fcSChristoph Hellwig goto put_pci; 2295f3ca80fcSChristoph Hellwig 2296ff5350a8SAndy Lutomirski quirks |= check_dell_samsung_bug(pdev); 2297ff5350a8SAndy Lutomirski 2298f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2299ff5350a8SAndy Lutomirski quirks); 2300f3ca80fcSChristoph Hellwig if (result) 2301f3ca80fcSChristoph Hellwig goto release_pools; 2302f3ca80fcSChristoph Hellwig 230382b057caSRakesh Pandit nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); 23041b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 23051b3c47c1SSagi Grimberg 2306d86c4d8eSChristoph Hellwig queue_work(nvme_wq, &dev->ctrl.reset_work); 230757dacad5SJay Sternberg return 0; 230857dacad5SJay Sternberg 230957dacad5SJay Sternberg release_pools: 231057dacad5SJay Sternberg nvme_release_prp_pools(dev); 231157dacad5SJay Sternberg put_pci: 231257dacad5SJay Sternberg put_device(dev->dev); 2313b00a726aSKeith Busch nvme_dev_unmap(dev); 231457dacad5SJay Sternberg free: 231557dacad5SJay Sternberg kfree(dev->queues); 231657dacad5SJay Sternberg kfree(dev); 231757dacad5SJay Sternberg return result; 231857dacad5SJay Sternberg } 231957dacad5SJay Sternberg 2320775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 232157dacad5SJay Sternberg { 232257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2323a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2324775755edSChristoph Hellwig } 232557dacad5SJay Sternberg 2326775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2327775755edSChristoph Hellwig { 2328f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2329d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 233057dacad5SJay Sternberg } 233157dacad5SJay Sternberg 233257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 233357dacad5SJay Sternberg { 233457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2335a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 233657dacad5SJay Sternberg } 233757dacad5SJay Sternberg 2338f58944e2SKeith Busch /* 2339f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2340f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2341f58944e2SKeith Busch * order to proceed. 2342f58944e2SKeith Busch */ 234357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 234457dacad5SJay Sternberg { 234557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 234657dacad5SJay Sternberg 2347bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2348bb8d261eSChristoph Hellwig 2349d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 235057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 23510ff9d4e1SKeith Busch 23526db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 23530ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 23546db28edaSKeith Busch nvme_dev_disable(dev, false); 23556db28edaSKeith Busch } 23560ff9d4e1SKeith Busch 2357d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2358d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2359d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2360a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 236187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 236257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 236357dacad5SJay Sternberg nvme_free_queues(dev, 0); 2364d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 236557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2366b00a726aSKeith Busch nvme_dev_unmap(dev); 23671673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 236857dacad5SJay Sternberg } 236957dacad5SJay Sternberg 237013880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 237113880f5bSKeith Busch { 237213880f5bSKeith Busch int ret = 0; 237313880f5bSKeith Busch 237413880f5bSKeith Busch if (numvfs == 0) { 237513880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 237613880f5bSKeith Busch dev_warn(&pdev->dev, 237713880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 237813880f5bSKeith Busch return -EPERM; 237913880f5bSKeith Busch } 238013880f5bSKeith Busch pci_disable_sriov(pdev); 238113880f5bSKeith Busch return 0; 238213880f5bSKeith Busch } 238313880f5bSKeith Busch 238413880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 238513880f5bSKeith Busch return ret ? ret : numvfs; 238613880f5bSKeith Busch } 238713880f5bSKeith Busch 238857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 238957dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 239057dacad5SJay Sternberg { 239157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 239257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 239357dacad5SJay Sternberg 2394a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 239557dacad5SJay Sternberg return 0; 239657dacad5SJay Sternberg } 239757dacad5SJay Sternberg 239857dacad5SJay Sternberg static int nvme_resume(struct device *dev) 239957dacad5SJay Sternberg { 240057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 240157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 240257dacad5SJay Sternberg 2403d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 240457dacad5SJay Sternberg return 0; 240557dacad5SJay Sternberg } 240657dacad5SJay Sternberg #endif 240757dacad5SJay Sternberg 240857dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 240957dacad5SJay Sternberg 2410a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2411a0a3408eSKeith Busch pci_channel_state_t state) 2412a0a3408eSKeith Busch { 2413a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2414a0a3408eSKeith Busch 2415a0a3408eSKeith Busch /* 2416a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2417a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2418a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2419a0a3408eSKeith Busch */ 2420a0a3408eSKeith Busch switch (state) { 2421a0a3408eSKeith Busch case pci_channel_io_normal: 2422a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2423a0a3408eSKeith Busch case pci_channel_io_frozen: 2424d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2425d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2426a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2427a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2428a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2429d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2430d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2431a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2432a0a3408eSKeith Busch } 2433a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2434a0a3408eSKeith Busch } 2435a0a3408eSKeith Busch 2436a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2437a0a3408eSKeith Busch { 2438a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2439a0a3408eSKeith Busch 24401b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2441a0a3408eSKeith Busch pci_restore_state(pdev); 2442d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2443a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2444a0a3408eSKeith Busch } 2445a0a3408eSKeith Busch 2446a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2447a0a3408eSKeith Busch { 2448a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2449a0a3408eSKeith Busch } 2450a0a3408eSKeith Busch 245157dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 245257dacad5SJay Sternberg .error_detected = nvme_error_detected, 245357dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 245457dacad5SJay Sternberg .resume = nvme_error_resume, 2455775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2456775755edSChristoph Hellwig .reset_done = nvme_reset_done, 245757dacad5SJay Sternberg }; 245857dacad5SJay Sternberg 245957dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2460106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 246108095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2462e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 246399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 246499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2465e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 246699466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 246799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2468e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2469f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2470f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2471f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 247250af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 247350af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2474540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2475540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 247654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 247754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2478015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2479015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2480d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2481d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2482d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2483d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 248457dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2485c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2486124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 248757dacad5SJay Sternberg { 0, } 248857dacad5SJay Sternberg }; 248957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 249057dacad5SJay Sternberg 249157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 249257dacad5SJay Sternberg .name = "nvme", 249357dacad5SJay Sternberg .id_table = nvme_id_table, 249457dacad5SJay Sternberg .probe = nvme_probe, 249557dacad5SJay Sternberg .remove = nvme_remove, 249657dacad5SJay Sternberg .shutdown = nvme_shutdown, 249757dacad5SJay Sternberg .driver = { 249857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 249957dacad5SJay Sternberg }, 250013880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 250157dacad5SJay Sternberg .err_handler = &nvme_err_handler, 250257dacad5SJay Sternberg }; 250357dacad5SJay Sternberg 250457dacad5SJay Sternberg static int __init nvme_init(void) 250557dacad5SJay Sternberg { 25069a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 250757dacad5SJay Sternberg } 250857dacad5SJay Sternberg 250957dacad5SJay Sternberg static void __exit nvme_exit(void) 251057dacad5SJay Sternberg { 251157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 251257dacad5SJay Sternberg _nvme_check_size(); 251357dacad5SJay Sternberg } 251457dacad5SJay Sternberg 251557dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 251657dacad5SJay Sternberg MODULE_LICENSE("GPL"); 251757dacad5SJay Sternberg MODULE_VERSION("1.0"); 251857dacad5SJay Sternberg module_init(nvme_init); 251957dacad5SJay Sternberg module_exit(nvme_exit); 2520