xref: /openbmc/linux/drivers/nvme/host/pci.c (revision f1ed3df2)
157dacad5SJay Sternberg /*
257dacad5SJay Sternberg  * NVM Express device driver
357dacad5SJay Sternberg  * Copyright (c) 2011-2014, Intel Corporation.
457dacad5SJay Sternberg  *
557dacad5SJay Sternberg  * This program is free software; you can redistribute it and/or modify it
657dacad5SJay Sternberg  * under the terms and conditions of the GNU General Public License,
757dacad5SJay Sternberg  * version 2, as published by the Free Software Foundation.
857dacad5SJay Sternberg  *
957dacad5SJay Sternberg  * This program is distributed in the hope it will be useful, but WITHOUT
1057dacad5SJay Sternberg  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1157dacad5SJay Sternberg  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1257dacad5SJay Sternberg  * more details.
1357dacad5SJay Sternberg  */
1457dacad5SJay Sternberg 
15a0a3408eSKeith Busch #include <linux/aer.h>
1618119775SKeith Busch #include <linux/async.h>
1757dacad5SJay Sternberg #include <linux/blkdev.h>
1857dacad5SJay Sternberg #include <linux/blk-mq.h>
19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h>
20ff5350a8SAndy Lutomirski #include <linux/dmi.h>
2157dacad5SJay Sternberg #include <linux/init.h>
2257dacad5SJay Sternberg #include <linux/interrupt.h>
2357dacad5SJay Sternberg #include <linux/io.h>
2457dacad5SJay Sternberg #include <linux/mm.h>
2557dacad5SJay Sternberg #include <linux/module.h>
2677bf25eaSKeith Busch #include <linux/mutex.h>
27d0877473SKeith Busch #include <linux/once.h>
2857dacad5SJay Sternberg #include <linux/pci.h>
2957dacad5SJay Sternberg #include <linux/t10-pi.h>
3057dacad5SJay Sternberg #include <linux/types.h>
319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h>
32a98e58e5SScott Bauer #include <linux/sed-opal.h>
3357dacad5SJay Sternberg 
3457dacad5SJay Sternberg #include "nvme.h"
3557dacad5SJay Sternberg 
3657dacad5SJay Sternberg #define SQ_SIZE(depth)		(depth * sizeof(struct nvme_command))
3757dacad5SJay Sternberg #define CQ_SIZE(depth)		(depth * sizeof(struct nvme_completion))
3857dacad5SJay Sternberg 
39a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE	(PAGE_SIZE / sizeof(struct nvme_sgl_desc))
40adf68f21SChristoph Hellwig 
41943e942eSJens Axboe /*
42943e942eSJens Axboe  * These can be higher, but we need to ensure that any command doesn't
43943e942eSJens Axboe  * require an sg allocation that needs more than a page of data.
44943e942eSJens Axboe  */
45943e942eSJens Axboe #define NVME_MAX_KB_SZ	4096
46943e942eSJens Axboe #define NVME_MAX_SEGS	127
47943e942eSJens Axboe 
4857dacad5SJay Sternberg static int use_threaded_interrupts;
4957dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0);
5057dacad5SJay Sternberg 
5157dacad5SJay Sternberg static bool use_cmb_sqes = true;
5269f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444);
5357dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
5457dacad5SJay Sternberg 
5587ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128;
5687ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444);
5787ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb,
5887ad72a5SChristoph Hellwig 	"Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
5957dacad5SJay Sternberg 
60a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K;
61a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644);
62a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold,
63a7a7cbe3SChaitanya Kulkarni 		"Use SGLs when average request segment size is larger or equal to "
64a7a7cbe3SChaitanya Kulkarni 		"this size. Use 0 to disable SGLs.");
65a7a7cbe3SChaitanya Kulkarni 
66b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
67b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = {
68b27c1e68Sweiping zhang 	.set = io_queue_depth_set,
69b27c1e68Sweiping zhang 	.get = param_get_int,
70b27c1e68Sweiping zhang };
71b27c1e68Sweiping zhang 
72b27c1e68Sweiping zhang static int io_queue_depth = 1024;
73b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
74b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
75b27c1e68Sweiping zhang 
761c63dc66SChristoph Hellwig struct nvme_dev;
771c63dc66SChristoph Hellwig struct nvme_queue;
7857dacad5SJay Sternberg 
79a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
8057dacad5SJay Sternberg 
8157dacad5SJay Sternberg /*
821c63dc66SChristoph Hellwig  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
831c63dc66SChristoph Hellwig  */
841c63dc66SChristoph Hellwig struct nvme_dev {
85147b27e4SSagi Grimberg 	struct nvme_queue *queues;
861c63dc66SChristoph Hellwig 	struct blk_mq_tag_set tagset;
871c63dc66SChristoph Hellwig 	struct blk_mq_tag_set admin_tagset;
881c63dc66SChristoph Hellwig 	u32 __iomem *dbs;
891c63dc66SChristoph Hellwig 	struct device *dev;
901c63dc66SChristoph Hellwig 	struct dma_pool *prp_page_pool;
911c63dc66SChristoph Hellwig 	struct dma_pool *prp_small_pool;
921c63dc66SChristoph Hellwig 	unsigned online_queues;
931c63dc66SChristoph Hellwig 	unsigned max_qid;
9422b55601SKeith Busch 	unsigned int num_vecs;
951c63dc66SChristoph Hellwig 	int q_depth;
961c63dc66SChristoph Hellwig 	u32 db_stride;
971c63dc66SChristoph Hellwig 	void __iomem *bar;
9897f6ef64SXu Yu 	unsigned long bar_mapped_size;
995c8809e6SChristoph Hellwig 	struct work_struct remove_work;
10077bf25eaSKeith Busch 	struct mutex shutdown_lock;
1011c63dc66SChristoph Hellwig 	bool subsystem;
1021c63dc66SChristoph Hellwig 	void __iomem *cmb;
1038969f1f8SChristoph Hellwig 	pci_bus_addr_t cmb_bus_addr;
1041c63dc66SChristoph Hellwig 	u64 cmb_size;
1051c63dc66SChristoph Hellwig 	u32 cmbsz;
106202021c1SStephen Bates 	u32 cmbloc;
1071c63dc66SChristoph Hellwig 	struct nvme_ctrl ctrl;
108db3cbfffSKeith Busch 	struct completion ioq_wait;
10987ad72a5SChristoph Hellwig 
110943e942eSJens Axboe 	mempool_t *iod_mempool;
111943e942eSJens Axboe 
11287ad72a5SChristoph Hellwig 	/* shadow doorbell buffer support: */
113f9f38e33SHelen Koike 	u32 *dbbuf_dbs;
114f9f38e33SHelen Koike 	dma_addr_t dbbuf_dbs_dma_addr;
115f9f38e33SHelen Koike 	u32 *dbbuf_eis;
116f9f38e33SHelen Koike 	dma_addr_t dbbuf_eis_dma_addr;
11787ad72a5SChristoph Hellwig 
11887ad72a5SChristoph Hellwig 	/* host memory buffer support: */
11987ad72a5SChristoph Hellwig 	u64 host_mem_size;
12087ad72a5SChristoph Hellwig 	u32 nr_host_mem_descs;
1214033f35dSChristoph Hellwig 	dma_addr_t host_mem_descs_dma;
12287ad72a5SChristoph Hellwig 	struct nvme_host_mem_buf_desc *host_mem_descs;
12387ad72a5SChristoph Hellwig 	void **host_mem_desc_bufs;
12457dacad5SJay Sternberg };
12557dacad5SJay Sternberg 
126b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
127b27c1e68Sweiping zhang {
128b27c1e68Sweiping zhang 	int n = 0, ret;
129b27c1e68Sweiping zhang 
130b27c1e68Sweiping zhang 	ret = kstrtoint(val, 10, &n);
131b27c1e68Sweiping zhang 	if (ret != 0 || n < 2)
132b27c1e68Sweiping zhang 		return -EINVAL;
133b27c1e68Sweiping zhang 
134b27c1e68Sweiping zhang 	return param_set_int(val, kp);
135b27c1e68Sweiping zhang }
136b27c1e68Sweiping zhang 
137f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride)
138f9f38e33SHelen Koike {
139f9f38e33SHelen Koike 	return qid * 2 * stride;
140f9f38e33SHelen Koike }
141f9f38e33SHelen Koike 
142f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride)
143f9f38e33SHelen Koike {
144f9f38e33SHelen Koike 	return (qid * 2 + 1) * stride;
145f9f38e33SHelen Koike }
146f9f38e33SHelen Koike 
1471c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
1481c63dc66SChristoph Hellwig {
1491c63dc66SChristoph Hellwig 	return container_of(ctrl, struct nvme_dev, ctrl);
1501c63dc66SChristoph Hellwig }
1511c63dc66SChristoph Hellwig 
15257dacad5SJay Sternberg /*
15357dacad5SJay Sternberg  * An NVM Express queue.  Each device has at least two (one for admin
15457dacad5SJay Sternberg  * commands and one for I/O commands).
15557dacad5SJay Sternberg  */
15657dacad5SJay Sternberg struct nvme_queue {
15757dacad5SJay Sternberg 	struct device *q_dmadev;
15857dacad5SJay Sternberg 	struct nvme_dev *dev;
1591ab0cd69SJens Axboe 	spinlock_t sq_lock;
16057dacad5SJay Sternberg 	struct nvme_command *sq_cmds;
16157dacad5SJay Sternberg 	struct nvme_command __iomem *sq_cmds_io;
1621ab0cd69SJens Axboe 	spinlock_t cq_lock ____cacheline_aligned_in_smp;
16357dacad5SJay Sternberg 	volatile struct nvme_completion *cqes;
16457dacad5SJay Sternberg 	struct blk_mq_tags **tags;
16557dacad5SJay Sternberg 	dma_addr_t sq_dma_addr;
16657dacad5SJay Sternberg 	dma_addr_t cq_dma_addr;
16757dacad5SJay Sternberg 	u32 __iomem *q_db;
16857dacad5SJay Sternberg 	u16 q_depth;
16957dacad5SJay Sternberg 	s16 cq_vector;
17057dacad5SJay Sternberg 	u16 sq_tail;
17157dacad5SJay Sternberg 	u16 cq_head;
17268fa9dbeSJens Axboe 	u16 last_cq_head;
17357dacad5SJay Sternberg 	u16 qid;
17457dacad5SJay Sternberg 	u8 cq_phase;
175f9f38e33SHelen Koike 	u32 *dbbuf_sq_db;
176f9f38e33SHelen Koike 	u32 *dbbuf_cq_db;
177f9f38e33SHelen Koike 	u32 *dbbuf_sq_ei;
178f9f38e33SHelen Koike 	u32 *dbbuf_cq_ei;
17957dacad5SJay Sternberg };
18057dacad5SJay Sternberg 
18157dacad5SJay Sternberg /*
18271bd150cSChristoph Hellwig  * The nvme_iod describes the data in an I/O, including the list of PRP
18371bd150cSChristoph Hellwig  * entries.  You can't see it in this data structure because C doesn't let
184f4800d6dSChristoph Hellwig  * me express that.  Use nvme_init_iod to ensure there's enough space
18571bd150cSChristoph Hellwig  * allocated to store the PRP list.
18671bd150cSChristoph Hellwig  */
18771bd150cSChristoph Hellwig struct nvme_iod {
188d49187e9SChristoph Hellwig 	struct nvme_request req;
189f4800d6dSChristoph Hellwig 	struct nvme_queue *nvmeq;
190a7a7cbe3SChaitanya Kulkarni 	bool use_sgl;
191f4800d6dSChristoph Hellwig 	int aborted;
19271bd150cSChristoph Hellwig 	int npages;		/* In the PRP list. 0 means small pool in use */
19371bd150cSChristoph Hellwig 	int nents;		/* Used in scatterlist */
19471bd150cSChristoph Hellwig 	int length;		/* Of data, in bytes */
19571bd150cSChristoph Hellwig 	dma_addr_t first_dma;
196bf684057SChristoph Hellwig 	struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
197f4800d6dSChristoph Hellwig 	struct scatterlist *sg;
198f4800d6dSChristoph Hellwig 	struct scatterlist inline_sg[0];
19957dacad5SJay Sternberg };
20057dacad5SJay Sternberg 
20157dacad5SJay Sternberg /*
20257dacad5SJay Sternberg  * Check we didin't inadvertently grow the command struct
20357dacad5SJay Sternberg  */
20457dacad5SJay Sternberg static inline void _nvme_check_size(void)
20557dacad5SJay Sternberg {
20657dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
20757dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
20857dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
20957dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
21057dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
21157dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
21257dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
21357dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
2140add5e8eSJohannes Thumshirn 	BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
2150add5e8eSJohannes Thumshirn 	BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
21657dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
21757dacad5SJay Sternberg 	BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
218f9f38e33SHelen Koike 	BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
219f9f38e33SHelen Koike }
220f9f38e33SHelen Koike 
221f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride)
222f9f38e33SHelen Koike {
223f9f38e33SHelen Koike 	return ((num_possible_cpus() + 1) * 8 * stride);
224f9f38e33SHelen Koike }
225f9f38e33SHelen Koike 
226f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
227f9f38e33SHelen Koike {
228f9f38e33SHelen Koike 	unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
229f9f38e33SHelen Koike 
230f9f38e33SHelen Koike 	if (dev->dbbuf_dbs)
231f9f38e33SHelen Koike 		return 0;
232f9f38e33SHelen Koike 
233f9f38e33SHelen Koike 	dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
234f9f38e33SHelen Koike 					    &dev->dbbuf_dbs_dma_addr,
235f9f38e33SHelen Koike 					    GFP_KERNEL);
236f9f38e33SHelen Koike 	if (!dev->dbbuf_dbs)
237f9f38e33SHelen Koike 		return -ENOMEM;
238f9f38e33SHelen Koike 	dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
239f9f38e33SHelen Koike 					    &dev->dbbuf_eis_dma_addr,
240f9f38e33SHelen Koike 					    GFP_KERNEL);
241f9f38e33SHelen Koike 	if (!dev->dbbuf_eis) {
242f9f38e33SHelen Koike 		dma_free_coherent(dev->dev, mem_size,
243f9f38e33SHelen Koike 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
244f9f38e33SHelen Koike 		dev->dbbuf_dbs = NULL;
245f9f38e33SHelen Koike 		return -ENOMEM;
246f9f38e33SHelen Koike 	}
247f9f38e33SHelen Koike 
248f9f38e33SHelen Koike 	return 0;
249f9f38e33SHelen Koike }
250f9f38e33SHelen Koike 
251f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
252f9f38e33SHelen Koike {
253f9f38e33SHelen Koike 	unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
254f9f38e33SHelen Koike 
255f9f38e33SHelen Koike 	if (dev->dbbuf_dbs) {
256f9f38e33SHelen Koike 		dma_free_coherent(dev->dev, mem_size,
257f9f38e33SHelen Koike 				  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
258f9f38e33SHelen Koike 		dev->dbbuf_dbs = NULL;
259f9f38e33SHelen Koike 	}
260f9f38e33SHelen Koike 	if (dev->dbbuf_eis) {
261f9f38e33SHelen Koike 		dma_free_coherent(dev->dev, mem_size,
262f9f38e33SHelen Koike 				  dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
263f9f38e33SHelen Koike 		dev->dbbuf_eis = NULL;
264f9f38e33SHelen Koike 	}
265f9f38e33SHelen Koike }
266f9f38e33SHelen Koike 
267f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev,
268f9f38e33SHelen Koike 			    struct nvme_queue *nvmeq, int qid)
269f9f38e33SHelen Koike {
270f9f38e33SHelen Koike 	if (!dev->dbbuf_dbs || !qid)
271f9f38e33SHelen Koike 		return;
272f9f38e33SHelen Koike 
273f9f38e33SHelen Koike 	nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
274f9f38e33SHelen Koike 	nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
275f9f38e33SHelen Koike 	nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
276f9f38e33SHelen Koike 	nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
277f9f38e33SHelen Koike }
278f9f38e33SHelen Koike 
279f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev)
280f9f38e33SHelen Koike {
281f9f38e33SHelen Koike 	struct nvme_command c;
282f9f38e33SHelen Koike 
283f9f38e33SHelen Koike 	if (!dev->dbbuf_dbs)
284f9f38e33SHelen Koike 		return;
285f9f38e33SHelen Koike 
286f9f38e33SHelen Koike 	memset(&c, 0, sizeof(c));
287f9f38e33SHelen Koike 	c.dbbuf.opcode = nvme_admin_dbbuf;
288f9f38e33SHelen Koike 	c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
289f9f38e33SHelen Koike 	c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
290f9f38e33SHelen Koike 
291f9f38e33SHelen Koike 	if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
2929bdcfb10SChristoph Hellwig 		dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
293f9f38e33SHelen Koike 		/* Free memory and continue on */
294f9f38e33SHelen Koike 		nvme_dbbuf_dma_free(dev);
295f9f38e33SHelen Koike 	}
296f9f38e33SHelen Koike }
297f9f38e33SHelen Koike 
298f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
299f9f38e33SHelen Koike {
300f9f38e33SHelen Koike 	return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
301f9f38e33SHelen Koike }
302f9f38e33SHelen Koike 
303f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */
304f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
305f9f38e33SHelen Koike 					      volatile u32 *dbbuf_ei)
306f9f38e33SHelen Koike {
307f9f38e33SHelen Koike 	if (dbbuf_db) {
308f9f38e33SHelen Koike 		u16 old_value;
309f9f38e33SHelen Koike 
310f9f38e33SHelen Koike 		/*
311f9f38e33SHelen Koike 		 * Ensure that the queue is written before updating
312f9f38e33SHelen Koike 		 * the doorbell in memory
313f9f38e33SHelen Koike 		 */
314f9f38e33SHelen Koike 		wmb();
315f9f38e33SHelen Koike 
316f9f38e33SHelen Koike 		old_value = *dbbuf_db;
317f9f38e33SHelen Koike 		*dbbuf_db = value;
318f9f38e33SHelen Koike 
319f1ed3df2SMichal Wnukowski 		/*
320f1ed3df2SMichal Wnukowski 		 * Ensure that the doorbell is updated before reading the event
321f1ed3df2SMichal Wnukowski 		 * index from memory.  The controller needs to provide similar
322f1ed3df2SMichal Wnukowski 		 * ordering to ensure the envent index is updated before reading
323f1ed3df2SMichal Wnukowski 		 * the doorbell.
324f1ed3df2SMichal Wnukowski 		 */
325f1ed3df2SMichal Wnukowski 		mb();
326f1ed3df2SMichal Wnukowski 
327f9f38e33SHelen Koike 		if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
328f9f38e33SHelen Koike 			return false;
329f9f38e33SHelen Koike 	}
330f9f38e33SHelen Koike 
331f9f38e33SHelen Koike 	return true;
33257dacad5SJay Sternberg }
33357dacad5SJay Sternberg 
33457dacad5SJay Sternberg /*
33557dacad5SJay Sternberg  * Max size of iod being embedded in the request payload
33657dacad5SJay Sternberg  */
33757dacad5SJay Sternberg #define NVME_INT_PAGES		2
3385fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev)	(NVME_INT_PAGES * (dev)->ctrl.page_size)
33957dacad5SJay Sternberg 
34057dacad5SJay Sternberg /*
34157dacad5SJay Sternberg  * Will slightly overestimate the number of pages needed.  This is OK
34257dacad5SJay Sternberg  * as it only leads to a small amount of wasted memory for the lifetime of
34357dacad5SJay Sternberg  * the I/O.
34457dacad5SJay Sternberg  */
34557dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev)
34657dacad5SJay Sternberg {
3475fd4ce1bSChristoph Hellwig 	unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
3485fd4ce1bSChristoph Hellwig 				      dev->ctrl.page_size);
34957dacad5SJay Sternberg 	return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
35057dacad5SJay Sternberg }
35157dacad5SJay Sternberg 
352a7a7cbe3SChaitanya Kulkarni /*
353a7a7cbe3SChaitanya Kulkarni  * Calculates the number of pages needed for the SGL segments. For example a 4k
354a7a7cbe3SChaitanya Kulkarni  * page can accommodate 256 SGL descriptors.
355a7a7cbe3SChaitanya Kulkarni  */
356a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg)
357f4800d6dSChristoph Hellwig {
358a7a7cbe3SChaitanya Kulkarni 	return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE);
359f4800d6dSChristoph Hellwig }
360f4800d6dSChristoph Hellwig 
361a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev,
362a7a7cbe3SChaitanya Kulkarni 		unsigned int size, unsigned int nseg, bool use_sgl)
36357dacad5SJay Sternberg {
364a7a7cbe3SChaitanya Kulkarni 	size_t alloc_size;
365a7a7cbe3SChaitanya Kulkarni 
366a7a7cbe3SChaitanya Kulkarni 	if (use_sgl)
367a7a7cbe3SChaitanya Kulkarni 		alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg);
368a7a7cbe3SChaitanya Kulkarni 	else
369a7a7cbe3SChaitanya Kulkarni 		alloc_size = sizeof(__le64 *) * nvme_npages(size, dev);
370a7a7cbe3SChaitanya Kulkarni 
371a7a7cbe3SChaitanya Kulkarni 	return alloc_size + sizeof(struct scatterlist) * nseg;
372a7a7cbe3SChaitanya Kulkarni }
373a7a7cbe3SChaitanya Kulkarni 
374a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl)
375a7a7cbe3SChaitanya Kulkarni {
376a7a7cbe3SChaitanya Kulkarni 	unsigned int alloc_size = nvme_pci_iod_alloc_size(dev,
377a7a7cbe3SChaitanya Kulkarni 				    NVME_INT_BYTES(dev), NVME_INT_PAGES,
378a7a7cbe3SChaitanya Kulkarni 				    use_sgl);
379a7a7cbe3SChaitanya Kulkarni 
380a7a7cbe3SChaitanya Kulkarni 	return sizeof(struct nvme_iod) + alloc_size;
38157dacad5SJay Sternberg }
38257dacad5SJay Sternberg 
38357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
38457dacad5SJay Sternberg 				unsigned int hctx_idx)
38557dacad5SJay Sternberg {
38657dacad5SJay Sternberg 	struct nvme_dev *dev = data;
387147b27e4SSagi Grimberg 	struct nvme_queue *nvmeq = &dev->queues[0];
38857dacad5SJay Sternberg 
38957dacad5SJay Sternberg 	WARN_ON(hctx_idx != 0);
39057dacad5SJay Sternberg 	WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
39157dacad5SJay Sternberg 	WARN_ON(nvmeq->tags);
39257dacad5SJay Sternberg 
39357dacad5SJay Sternberg 	hctx->driver_data = nvmeq;
39457dacad5SJay Sternberg 	nvmeq->tags = &dev->admin_tagset.tags[0];
39557dacad5SJay Sternberg 	return 0;
39657dacad5SJay Sternberg }
39757dacad5SJay Sternberg 
39857dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
39957dacad5SJay Sternberg {
40057dacad5SJay Sternberg 	struct nvme_queue *nvmeq = hctx->driver_data;
40157dacad5SJay Sternberg 
40257dacad5SJay Sternberg 	nvmeq->tags = NULL;
40357dacad5SJay Sternberg }
40457dacad5SJay Sternberg 
40557dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
40657dacad5SJay Sternberg 			  unsigned int hctx_idx)
40757dacad5SJay Sternberg {
40857dacad5SJay Sternberg 	struct nvme_dev *dev = data;
409147b27e4SSagi Grimberg 	struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
41057dacad5SJay Sternberg 
41157dacad5SJay Sternberg 	if (!nvmeq->tags)
41257dacad5SJay Sternberg 		nvmeq->tags = &dev->tagset.tags[hctx_idx];
41357dacad5SJay Sternberg 
41457dacad5SJay Sternberg 	WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
41557dacad5SJay Sternberg 	hctx->driver_data = nvmeq;
41657dacad5SJay Sternberg 	return 0;
41757dacad5SJay Sternberg }
41857dacad5SJay Sternberg 
419d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
420d6296d39SChristoph Hellwig 		unsigned int hctx_idx, unsigned int numa_node)
42157dacad5SJay Sternberg {
422d6296d39SChristoph Hellwig 	struct nvme_dev *dev = set->driver_data;
423f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
4240350815aSChristoph Hellwig 	int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
425147b27e4SSagi Grimberg 	struct nvme_queue *nvmeq = &dev->queues[queue_idx];
42657dacad5SJay Sternberg 
42757dacad5SJay Sternberg 	BUG_ON(!nvmeq);
428f4800d6dSChristoph Hellwig 	iod->nvmeq = nvmeq;
42959e29ce6SSagi Grimberg 
43059e29ce6SSagi Grimberg 	nvme_req(req)->ctrl = &dev->ctrl;
43157dacad5SJay Sternberg 	return 0;
43257dacad5SJay Sternberg }
43357dacad5SJay Sternberg 
434dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
435dca51e78SChristoph Hellwig {
436dca51e78SChristoph Hellwig 	struct nvme_dev *dev = set->driver_data;
437dca51e78SChristoph Hellwig 
43822b55601SKeith Busch 	return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev),
43922b55601SKeith Busch 			dev->num_vecs > 1 ? 1 /* admin queue */ : 0);
440dca51e78SChristoph Hellwig }
441dca51e78SChristoph Hellwig 
44257dacad5SJay Sternberg /**
44390ea5ca4SChristoph Hellwig  * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
44457dacad5SJay Sternberg  * @nvmeq: The queue to use
44557dacad5SJay Sternberg  * @cmd: The command to send
44657dacad5SJay Sternberg  */
44790ea5ca4SChristoph Hellwig static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
44857dacad5SJay Sternberg {
44990ea5ca4SChristoph Hellwig 	spin_lock(&nvmeq->sq_lock);
45057dacad5SJay Sternberg 	if (nvmeq->sq_cmds_io)
45190ea5ca4SChristoph Hellwig 		memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd,
45290ea5ca4SChristoph Hellwig 				sizeof(*cmd));
45357dacad5SJay Sternberg 	else
45490ea5ca4SChristoph Hellwig 		memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd));
45557dacad5SJay Sternberg 
45690ea5ca4SChristoph Hellwig 	if (++nvmeq->sq_tail == nvmeq->q_depth)
45790ea5ca4SChristoph Hellwig 		nvmeq->sq_tail = 0;
45890ea5ca4SChristoph Hellwig 	if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
45990ea5ca4SChristoph Hellwig 			nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
46090ea5ca4SChristoph Hellwig 		writel(nvmeq->sq_tail, nvmeq->q_db);
46190ea5ca4SChristoph Hellwig 	spin_unlock(&nvmeq->sq_lock);
46257dacad5SJay Sternberg }
46357dacad5SJay Sternberg 
464a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req)
46557dacad5SJay Sternberg {
466f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
467a7a7cbe3SChaitanya Kulkarni 	return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
46857dacad5SJay Sternberg }
46957dacad5SJay Sternberg 
470955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
471955b1b5aSMinwoo Im {
472955b1b5aSMinwoo Im 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
47320469a37SKeith Busch 	int nseg = blk_rq_nr_phys_segments(req);
474955b1b5aSMinwoo Im 	unsigned int avg_seg_size;
475955b1b5aSMinwoo Im 
47620469a37SKeith Busch 	if (nseg == 0)
47720469a37SKeith Busch 		return false;
47820469a37SKeith Busch 
47920469a37SKeith Busch 	avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
480955b1b5aSMinwoo Im 
481955b1b5aSMinwoo Im 	if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1))))
482955b1b5aSMinwoo Im 		return false;
483955b1b5aSMinwoo Im 	if (!iod->nvmeq->qid)
484955b1b5aSMinwoo Im 		return false;
485955b1b5aSMinwoo Im 	if (!sgl_threshold || avg_seg_size < sgl_threshold)
486955b1b5aSMinwoo Im 		return false;
487955b1b5aSMinwoo Im 	return true;
488955b1b5aSMinwoo Im }
489955b1b5aSMinwoo Im 
490fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
49157dacad5SJay Sternberg {
492f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
493f9d03f96SChristoph Hellwig 	int nseg = blk_rq_nr_phys_segments(rq);
494b131c61dSChristoph Hellwig 	unsigned int size = blk_rq_payload_bytes(rq);
495f4800d6dSChristoph Hellwig 
496955b1b5aSMinwoo Im 	iod->use_sgl = nvme_pci_use_sgls(dev, rq);
497955b1b5aSMinwoo Im 
498f4800d6dSChristoph Hellwig 	if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
499943e942eSJens Axboe 		iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
500f4800d6dSChristoph Hellwig 		if (!iod->sg)
501fc17b653SChristoph Hellwig 			return BLK_STS_RESOURCE;
502f4800d6dSChristoph Hellwig 	} else {
503f4800d6dSChristoph Hellwig 		iod->sg = iod->inline_sg;
50457dacad5SJay Sternberg 	}
50557dacad5SJay Sternberg 
506f4800d6dSChristoph Hellwig 	iod->aborted = 0;
50757dacad5SJay Sternberg 	iod->npages = -1;
50857dacad5SJay Sternberg 	iod->nents = 0;
509f4800d6dSChristoph Hellwig 	iod->length = size;
510f80ec966SKeith Busch 
511fc17b653SChristoph Hellwig 	return BLK_STS_OK;
51257dacad5SJay Sternberg }
51357dacad5SJay Sternberg 
514f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
51557dacad5SJay Sternberg {
516f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
517a7a7cbe3SChaitanya Kulkarni 	const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1;
518a7a7cbe3SChaitanya Kulkarni 	dma_addr_t dma_addr = iod->first_dma, next_dma_addr;
519a7a7cbe3SChaitanya Kulkarni 
52057dacad5SJay Sternberg 	int i;
52157dacad5SJay Sternberg 
52257dacad5SJay Sternberg 	if (iod->npages == 0)
523a7a7cbe3SChaitanya Kulkarni 		dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
524a7a7cbe3SChaitanya Kulkarni 			dma_addr);
525a7a7cbe3SChaitanya Kulkarni 
52657dacad5SJay Sternberg 	for (i = 0; i < iod->npages; i++) {
527a7a7cbe3SChaitanya Kulkarni 		void *addr = nvme_pci_iod_list(req)[i];
528a7a7cbe3SChaitanya Kulkarni 
529a7a7cbe3SChaitanya Kulkarni 		if (iod->use_sgl) {
530a7a7cbe3SChaitanya Kulkarni 			struct nvme_sgl_desc *sg_list = addr;
531a7a7cbe3SChaitanya Kulkarni 
532a7a7cbe3SChaitanya Kulkarni 			next_dma_addr =
533a7a7cbe3SChaitanya Kulkarni 			    le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr);
534a7a7cbe3SChaitanya Kulkarni 		} else {
535a7a7cbe3SChaitanya Kulkarni 			__le64 *prp_list = addr;
536a7a7cbe3SChaitanya Kulkarni 
537a7a7cbe3SChaitanya Kulkarni 			next_dma_addr = le64_to_cpu(prp_list[last_prp]);
538a7a7cbe3SChaitanya Kulkarni 		}
539a7a7cbe3SChaitanya Kulkarni 
540a7a7cbe3SChaitanya Kulkarni 		dma_pool_free(dev->prp_page_pool, addr, dma_addr);
541a7a7cbe3SChaitanya Kulkarni 		dma_addr = next_dma_addr;
54257dacad5SJay Sternberg 	}
54357dacad5SJay Sternberg 
544f4800d6dSChristoph Hellwig 	if (iod->sg != iod->inline_sg)
545943e942eSJens Axboe 		mempool_free(iod->sg, dev->iod_mempool);
54657dacad5SJay Sternberg }
54757dacad5SJay Sternberg 
548d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents)
549d0877473SKeith Busch {
550d0877473SKeith Busch 	int i;
551d0877473SKeith Busch 	struct scatterlist *sg;
552d0877473SKeith Busch 
553d0877473SKeith Busch 	for_each_sg(sgl, sg, nents, i) {
554d0877473SKeith Busch 		dma_addr_t phys = sg_phys(sg);
555d0877473SKeith Busch 		pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
556d0877473SKeith Busch 			"dma_address:%pad dma_length:%d\n",
557d0877473SKeith Busch 			i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
558d0877473SKeith Busch 			sg_dma_len(sg));
559d0877473SKeith Busch 	}
560d0877473SKeith Busch }
561d0877473SKeith Busch 
562a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
563a7a7cbe3SChaitanya Kulkarni 		struct request *req, struct nvme_rw_command *cmnd)
56457dacad5SJay Sternberg {
565f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
56657dacad5SJay Sternberg 	struct dma_pool *pool;
567b131c61dSChristoph Hellwig 	int length = blk_rq_payload_bytes(req);
56857dacad5SJay Sternberg 	struct scatterlist *sg = iod->sg;
56957dacad5SJay Sternberg 	int dma_len = sg_dma_len(sg);
57057dacad5SJay Sternberg 	u64 dma_addr = sg_dma_address(sg);
5715fd4ce1bSChristoph Hellwig 	u32 page_size = dev->ctrl.page_size;
57257dacad5SJay Sternberg 	int offset = dma_addr & (page_size - 1);
57357dacad5SJay Sternberg 	__le64 *prp_list;
574a7a7cbe3SChaitanya Kulkarni 	void **list = nvme_pci_iod_list(req);
57557dacad5SJay Sternberg 	dma_addr_t prp_dma;
57657dacad5SJay Sternberg 	int nprps, i;
57757dacad5SJay Sternberg 
57857dacad5SJay Sternberg 	length -= (page_size - offset);
5795228b328SJan H. Schönherr 	if (length <= 0) {
5805228b328SJan H. Schönherr 		iod->first_dma = 0;
581a7a7cbe3SChaitanya Kulkarni 		goto done;
5825228b328SJan H. Schönherr 	}
58357dacad5SJay Sternberg 
58457dacad5SJay Sternberg 	dma_len -= (page_size - offset);
58557dacad5SJay Sternberg 	if (dma_len) {
58657dacad5SJay Sternberg 		dma_addr += (page_size - offset);
58757dacad5SJay Sternberg 	} else {
58857dacad5SJay Sternberg 		sg = sg_next(sg);
58957dacad5SJay Sternberg 		dma_addr = sg_dma_address(sg);
59057dacad5SJay Sternberg 		dma_len = sg_dma_len(sg);
59157dacad5SJay Sternberg 	}
59257dacad5SJay Sternberg 
59357dacad5SJay Sternberg 	if (length <= page_size) {
59457dacad5SJay Sternberg 		iod->first_dma = dma_addr;
595a7a7cbe3SChaitanya Kulkarni 		goto done;
59657dacad5SJay Sternberg 	}
59757dacad5SJay Sternberg 
59857dacad5SJay Sternberg 	nprps = DIV_ROUND_UP(length, page_size);
59957dacad5SJay Sternberg 	if (nprps <= (256 / 8)) {
60057dacad5SJay Sternberg 		pool = dev->prp_small_pool;
60157dacad5SJay Sternberg 		iod->npages = 0;
60257dacad5SJay Sternberg 	} else {
60357dacad5SJay Sternberg 		pool = dev->prp_page_pool;
60457dacad5SJay Sternberg 		iod->npages = 1;
60557dacad5SJay Sternberg 	}
60657dacad5SJay Sternberg 
60769d2b571SChristoph Hellwig 	prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
60857dacad5SJay Sternberg 	if (!prp_list) {
60957dacad5SJay Sternberg 		iod->first_dma = dma_addr;
61057dacad5SJay Sternberg 		iod->npages = -1;
61186eea289SKeith Busch 		return BLK_STS_RESOURCE;
61257dacad5SJay Sternberg 	}
61357dacad5SJay Sternberg 	list[0] = prp_list;
61457dacad5SJay Sternberg 	iod->first_dma = prp_dma;
61557dacad5SJay Sternberg 	i = 0;
61657dacad5SJay Sternberg 	for (;;) {
61757dacad5SJay Sternberg 		if (i == page_size >> 3) {
61857dacad5SJay Sternberg 			__le64 *old_prp_list = prp_list;
61969d2b571SChristoph Hellwig 			prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
62057dacad5SJay Sternberg 			if (!prp_list)
62186eea289SKeith Busch 				return BLK_STS_RESOURCE;
62257dacad5SJay Sternberg 			list[iod->npages++] = prp_list;
62357dacad5SJay Sternberg 			prp_list[0] = old_prp_list[i - 1];
62457dacad5SJay Sternberg 			old_prp_list[i - 1] = cpu_to_le64(prp_dma);
62557dacad5SJay Sternberg 			i = 1;
62657dacad5SJay Sternberg 		}
62757dacad5SJay Sternberg 		prp_list[i++] = cpu_to_le64(dma_addr);
62857dacad5SJay Sternberg 		dma_len -= page_size;
62957dacad5SJay Sternberg 		dma_addr += page_size;
63057dacad5SJay Sternberg 		length -= page_size;
63157dacad5SJay Sternberg 		if (length <= 0)
63257dacad5SJay Sternberg 			break;
63357dacad5SJay Sternberg 		if (dma_len > 0)
63457dacad5SJay Sternberg 			continue;
63586eea289SKeith Busch 		if (unlikely(dma_len < 0))
63686eea289SKeith Busch 			goto bad_sgl;
63757dacad5SJay Sternberg 		sg = sg_next(sg);
63857dacad5SJay Sternberg 		dma_addr = sg_dma_address(sg);
63957dacad5SJay Sternberg 		dma_len = sg_dma_len(sg);
64057dacad5SJay Sternberg 	}
64157dacad5SJay Sternberg 
642a7a7cbe3SChaitanya Kulkarni done:
643a7a7cbe3SChaitanya Kulkarni 	cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
644a7a7cbe3SChaitanya Kulkarni 	cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
645a7a7cbe3SChaitanya Kulkarni 
64686eea289SKeith Busch 	return BLK_STS_OK;
64786eea289SKeith Busch 
64886eea289SKeith Busch  bad_sgl:
649d0877473SKeith Busch 	WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
650d0877473SKeith Busch 			"Invalid SGL for payload:%d nents:%d\n",
651d0877473SKeith Busch 			blk_rq_payload_bytes(req), iod->nents);
65286eea289SKeith Busch 	return BLK_STS_IOERR;
65357dacad5SJay Sternberg }
65457dacad5SJay Sternberg 
655a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
656a7a7cbe3SChaitanya Kulkarni 		struct scatterlist *sg)
657a7a7cbe3SChaitanya Kulkarni {
658a7a7cbe3SChaitanya Kulkarni 	sge->addr = cpu_to_le64(sg_dma_address(sg));
659a7a7cbe3SChaitanya Kulkarni 	sge->length = cpu_to_le32(sg_dma_len(sg));
660a7a7cbe3SChaitanya Kulkarni 	sge->type = NVME_SGL_FMT_DATA_DESC << 4;
661a7a7cbe3SChaitanya Kulkarni }
662a7a7cbe3SChaitanya Kulkarni 
663a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
664a7a7cbe3SChaitanya Kulkarni 		dma_addr_t dma_addr, int entries)
665a7a7cbe3SChaitanya Kulkarni {
666a7a7cbe3SChaitanya Kulkarni 	sge->addr = cpu_to_le64(dma_addr);
667a7a7cbe3SChaitanya Kulkarni 	if (entries < SGES_PER_PAGE) {
668a7a7cbe3SChaitanya Kulkarni 		sge->length = cpu_to_le32(entries * sizeof(*sge));
669a7a7cbe3SChaitanya Kulkarni 		sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
670a7a7cbe3SChaitanya Kulkarni 	} else {
671a7a7cbe3SChaitanya Kulkarni 		sge->length = cpu_to_le32(PAGE_SIZE);
672a7a7cbe3SChaitanya Kulkarni 		sge->type = NVME_SGL_FMT_SEG_DESC << 4;
673a7a7cbe3SChaitanya Kulkarni 	}
674a7a7cbe3SChaitanya Kulkarni }
675a7a7cbe3SChaitanya Kulkarni 
676a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
677b0f2853bSChristoph Hellwig 		struct request *req, struct nvme_rw_command *cmd, int entries)
678a7a7cbe3SChaitanya Kulkarni {
679a7a7cbe3SChaitanya Kulkarni 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
680a7a7cbe3SChaitanya Kulkarni 	struct dma_pool *pool;
681a7a7cbe3SChaitanya Kulkarni 	struct nvme_sgl_desc *sg_list;
682a7a7cbe3SChaitanya Kulkarni 	struct scatterlist *sg = iod->sg;
683a7a7cbe3SChaitanya Kulkarni 	dma_addr_t sgl_dma;
684b0f2853bSChristoph Hellwig 	int i = 0;
685a7a7cbe3SChaitanya Kulkarni 
686a7a7cbe3SChaitanya Kulkarni 	/* setting the transfer type as SGL */
687a7a7cbe3SChaitanya Kulkarni 	cmd->flags = NVME_CMD_SGL_METABUF;
688a7a7cbe3SChaitanya Kulkarni 
689b0f2853bSChristoph Hellwig 	if (entries == 1) {
690a7a7cbe3SChaitanya Kulkarni 		nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
691a7a7cbe3SChaitanya Kulkarni 		return BLK_STS_OK;
692a7a7cbe3SChaitanya Kulkarni 	}
693a7a7cbe3SChaitanya Kulkarni 
694a7a7cbe3SChaitanya Kulkarni 	if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
695a7a7cbe3SChaitanya Kulkarni 		pool = dev->prp_small_pool;
696a7a7cbe3SChaitanya Kulkarni 		iod->npages = 0;
697a7a7cbe3SChaitanya Kulkarni 	} else {
698a7a7cbe3SChaitanya Kulkarni 		pool = dev->prp_page_pool;
699a7a7cbe3SChaitanya Kulkarni 		iod->npages = 1;
700a7a7cbe3SChaitanya Kulkarni 	}
701a7a7cbe3SChaitanya Kulkarni 
702a7a7cbe3SChaitanya Kulkarni 	sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
703a7a7cbe3SChaitanya Kulkarni 	if (!sg_list) {
704a7a7cbe3SChaitanya Kulkarni 		iod->npages = -1;
705a7a7cbe3SChaitanya Kulkarni 		return BLK_STS_RESOURCE;
706a7a7cbe3SChaitanya Kulkarni 	}
707a7a7cbe3SChaitanya Kulkarni 
708a7a7cbe3SChaitanya Kulkarni 	nvme_pci_iod_list(req)[0] = sg_list;
709a7a7cbe3SChaitanya Kulkarni 	iod->first_dma = sgl_dma;
710a7a7cbe3SChaitanya Kulkarni 
711a7a7cbe3SChaitanya Kulkarni 	nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
712a7a7cbe3SChaitanya Kulkarni 
713a7a7cbe3SChaitanya Kulkarni 	do {
714a7a7cbe3SChaitanya Kulkarni 		if (i == SGES_PER_PAGE) {
715a7a7cbe3SChaitanya Kulkarni 			struct nvme_sgl_desc *old_sg_desc = sg_list;
716a7a7cbe3SChaitanya Kulkarni 			struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
717a7a7cbe3SChaitanya Kulkarni 
718a7a7cbe3SChaitanya Kulkarni 			sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
719a7a7cbe3SChaitanya Kulkarni 			if (!sg_list)
720a7a7cbe3SChaitanya Kulkarni 				return BLK_STS_RESOURCE;
721a7a7cbe3SChaitanya Kulkarni 
722a7a7cbe3SChaitanya Kulkarni 			i = 0;
723a7a7cbe3SChaitanya Kulkarni 			nvme_pci_iod_list(req)[iod->npages++] = sg_list;
724a7a7cbe3SChaitanya Kulkarni 			sg_list[i++] = *link;
725a7a7cbe3SChaitanya Kulkarni 			nvme_pci_sgl_set_seg(link, sgl_dma, entries);
726a7a7cbe3SChaitanya Kulkarni 		}
727a7a7cbe3SChaitanya Kulkarni 
728a7a7cbe3SChaitanya Kulkarni 		nvme_pci_sgl_set_data(&sg_list[i++], sg);
729a7a7cbe3SChaitanya Kulkarni 		sg = sg_next(sg);
730b0f2853bSChristoph Hellwig 	} while (--entries > 0);
731a7a7cbe3SChaitanya Kulkarni 
732a7a7cbe3SChaitanya Kulkarni 	return BLK_STS_OK;
733a7a7cbe3SChaitanya Kulkarni }
734a7a7cbe3SChaitanya Kulkarni 
735fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
736b131c61dSChristoph Hellwig 		struct nvme_command *cmnd)
73757dacad5SJay Sternberg {
738f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
739ba1ca37eSChristoph Hellwig 	struct request_queue *q = req->q;
740ba1ca37eSChristoph Hellwig 	enum dma_data_direction dma_dir = rq_data_dir(req) ?
741ba1ca37eSChristoph Hellwig 			DMA_TO_DEVICE : DMA_FROM_DEVICE;
742fc17b653SChristoph Hellwig 	blk_status_t ret = BLK_STS_IOERR;
743b0f2853bSChristoph Hellwig 	int nr_mapped;
74457dacad5SJay Sternberg 
745f9d03f96SChristoph Hellwig 	sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
746ba1ca37eSChristoph Hellwig 	iod->nents = blk_rq_map_sg(q, req, iod->sg);
747ba1ca37eSChristoph Hellwig 	if (!iod->nents)
748ba1ca37eSChristoph Hellwig 		goto out;
749ba1ca37eSChristoph Hellwig 
750fc17b653SChristoph Hellwig 	ret = BLK_STS_RESOURCE;
751b0f2853bSChristoph Hellwig 	nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
752b0f2853bSChristoph Hellwig 			DMA_ATTR_NO_WARN);
753b0f2853bSChristoph Hellwig 	if (!nr_mapped)
754ba1ca37eSChristoph Hellwig 		goto out;
755ba1ca37eSChristoph Hellwig 
756955b1b5aSMinwoo Im 	if (iod->use_sgl)
757b0f2853bSChristoph Hellwig 		ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
758a7a7cbe3SChaitanya Kulkarni 	else
759a7a7cbe3SChaitanya Kulkarni 		ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
760a7a7cbe3SChaitanya Kulkarni 
76186eea289SKeith Busch 	if (ret != BLK_STS_OK)
762ba1ca37eSChristoph Hellwig 		goto out_unmap;
763ba1ca37eSChristoph Hellwig 
764fc17b653SChristoph Hellwig 	ret = BLK_STS_IOERR;
765ba1ca37eSChristoph Hellwig 	if (blk_integrity_rq(req)) {
766ba1ca37eSChristoph Hellwig 		if (blk_rq_count_integrity_sg(q, req->bio) != 1)
767ba1ca37eSChristoph Hellwig 			goto out_unmap;
768ba1ca37eSChristoph Hellwig 
769bf684057SChristoph Hellwig 		sg_init_table(&iod->meta_sg, 1);
770bf684057SChristoph Hellwig 		if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
771ba1ca37eSChristoph Hellwig 			goto out_unmap;
772ba1ca37eSChristoph Hellwig 
773bf684057SChristoph Hellwig 		if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
774ba1ca37eSChristoph Hellwig 			goto out_unmap;
77557dacad5SJay Sternberg 	}
77657dacad5SJay Sternberg 
777ba1ca37eSChristoph Hellwig 	if (blk_integrity_rq(req))
778bf684057SChristoph Hellwig 		cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
779fc17b653SChristoph Hellwig 	return BLK_STS_OK;
780ba1ca37eSChristoph Hellwig 
781ba1ca37eSChristoph Hellwig out_unmap:
782ba1ca37eSChristoph Hellwig 	dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
783ba1ca37eSChristoph Hellwig out:
784ba1ca37eSChristoph Hellwig 	return ret;
78557dacad5SJay Sternberg }
78657dacad5SJay Sternberg 
787f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
788d4f6c3abSChristoph Hellwig {
789f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
790d4f6c3abSChristoph Hellwig 	enum dma_data_direction dma_dir = rq_data_dir(req) ?
791d4f6c3abSChristoph Hellwig 			DMA_TO_DEVICE : DMA_FROM_DEVICE;
792d4f6c3abSChristoph Hellwig 
793d4f6c3abSChristoph Hellwig 	if (iod->nents) {
794d4f6c3abSChristoph Hellwig 		dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
795f7f1fc36SMax Gurtovoy 		if (blk_integrity_rq(req))
796bf684057SChristoph Hellwig 			dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
797d4f6c3abSChristoph Hellwig 	}
798d4f6c3abSChristoph Hellwig 
799f9d03f96SChristoph Hellwig 	nvme_cleanup_cmd(req);
800f4800d6dSChristoph Hellwig 	nvme_free_iod(dev, req);
80157dacad5SJay Sternberg }
80257dacad5SJay Sternberg 
80357dacad5SJay Sternberg /*
80457dacad5SJay Sternberg  * NOTE: ns is NULL when called on the admin queue.
80557dacad5SJay Sternberg  */
806fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
80757dacad5SJay Sternberg 			 const struct blk_mq_queue_data *bd)
80857dacad5SJay Sternberg {
80957dacad5SJay Sternberg 	struct nvme_ns *ns = hctx->queue->queuedata;
81057dacad5SJay Sternberg 	struct nvme_queue *nvmeq = hctx->driver_data;
81157dacad5SJay Sternberg 	struct nvme_dev *dev = nvmeq->dev;
81257dacad5SJay Sternberg 	struct request *req = bd->rq;
813ba1ca37eSChristoph Hellwig 	struct nvme_command cmnd;
814ebe6d874SChristoph Hellwig 	blk_status_t ret;
81557dacad5SJay Sternberg 
816d1f06f4aSJens Axboe 	/*
817d1f06f4aSJens Axboe 	 * We should not need to do this, but we're still using this to
818d1f06f4aSJens Axboe 	 * ensure we can drain requests on a dying queue.
819d1f06f4aSJens Axboe 	 */
820d1f06f4aSJens Axboe 	if (unlikely(nvmeq->cq_vector < 0))
821d1f06f4aSJens Axboe 		return BLK_STS_IOERR;
822d1f06f4aSJens Axboe 
823f9d03f96SChristoph Hellwig 	ret = nvme_setup_cmd(ns, req, &cmnd);
824fc17b653SChristoph Hellwig 	if (ret)
825f4800d6dSChristoph Hellwig 		return ret;
82657dacad5SJay Sternberg 
827b131c61dSChristoph Hellwig 	ret = nvme_init_iod(req, dev);
828fc17b653SChristoph Hellwig 	if (ret)
829f9d03f96SChristoph Hellwig 		goto out_free_cmd;
83057dacad5SJay Sternberg 
831fc17b653SChristoph Hellwig 	if (blk_rq_nr_phys_segments(req)) {
832b131c61dSChristoph Hellwig 		ret = nvme_map_data(dev, req, &cmnd);
833fc17b653SChristoph Hellwig 		if (ret)
834f9d03f96SChristoph Hellwig 			goto out_cleanup_iod;
835fc17b653SChristoph Hellwig 	}
836ba1ca37eSChristoph Hellwig 
837aae239e1SChristoph Hellwig 	blk_mq_start_request(req);
83890ea5ca4SChristoph Hellwig 	nvme_submit_cmd(nvmeq, &cmnd);
839fc17b653SChristoph Hellwig 	return BLK_STS_OK;
840f9d03f96SChristoph Hellwig out_cleanup_iod:
841f4800d6dSChristoph Hellwig 	nvme_free_iod(dev, req);
842f9d03f96SChristoph Hellwig out_free_cmd:
843f9d03f96SChristoph Hellwig 	nvme_cleanup_cmd(req);
844ba1ca37eSChristoph Hellwig 	return ret;
84557dacad5SJay Sternberg }
84657dacad5SJay Sternberg 
84777f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req)
848eee417b0SChristoph Hellwig {
849f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
850eee417b0SChristoph Hellwig 
85177f02a7aSChristoph Hellwig 	nvme_unmap_data(iod->nvmeq->dev, req);
85277f02a7aSChristoph Hellwig 	nvme_complete_rq(req);
85357dacad5SJay Sternberg }
85457dacad5SJay Sternberg 
855d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */
856750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
857d783e0bdSMarta Rybczynska {
858750dde44SChristoph Hellwig 	return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) ==
859750dde44SChristoph Hellwig 			nvmeq->cq_phase;
860d783e0bdSMarta Rybczynska }
861d783e0bdSMarta Rybczynska 
862eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
86357dacad5SJay Sternberg {
864eb281c82SSagi Grimberg 	u16 head = nvmeq->cq_head;
86557dacad5SJay Sternberg 
866eb281c82SSagi Grimberg 	if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
867eb281c82SSagi Grimberg 					      nvmeq->dbbuf_cq_ei))
868eb281c82SSagi Grimberg 		writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
869eb281c82SSagi Grimberg }
870adf68f21SChristoph Hellwig 
8715cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
87257dacad5SJay Sternberg {
8735cb525c8SJens Axboe 	volatile struct nvme_completion *cqe = &nvmeq->cqes[idx];
87457dacad5SJay Sternberg 	struct request *req;
875adf68f21SChristoph Hellwig 
87683a12fb7SSagi Grimberg 	if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
8771b3c47c1SSagi Grimberg 		dev_warn(nvmeq->dev->ctrl.device,
878aae239e1SChristoph Hellwig 			"invalid id %d completed on queue %d\n",
87983a12fb7SSagi Grimberg 			cqe->command_id, le16_to_cpu(cqe->sq_id));
88083a12fb7SSagi Grimberg 		return;
881aae239e1SChristoph Hellwig 	}
882aae239e1SChristoph Hellwig 
883adf68f21SChristoph Hellwig 	/*
884adf68f21SChristoph Hellwig 	 * AEN requests are special as they don't time out and can
885adf68f21SChristoph Hellwig 	 * survive any kind of queue freeze and often don't respond to
886adf68f21SChristoph Hellwig 	 * aborts.  We don't even bother to allocate a struct request
887adf68f21SChristoph Hellwig 	 * for them but rather special case them here.
888adf68f21SChristoph Hellwig 	 */
889adf68f21SChristoph Hellwig 	if (unlikely(nvmeq->qid == 0 &&
89038dabe21SKeith Busch 			cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) {
8917bf58533SChristoph Hellwig 		nvme_complete_async_event(&nvmeq->dev->ctrl,
89283a12fb7SSagi Grimberg 				cqe->status, &cqe->result);
893a0fa9647SJens Axboe 		return;
89457dacad5SJay Sternberg 	}
89557dacad5SJay Sternberg 
89683a12fb7SSagi Grimberg 	req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
89783a12fb7SSagi Grimberg 	nvme_end_request(req, cqe->status, cqe->result);
89883a12fb7SSagi Grimberg }
89957dacad5SJay Sternberg 
9005cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end)
90183a12fb7SSagi Grimberg {
9025cb525c8SJens Axboe 	while (start != end) {
9035cb525c8SJens Axboe 		nvme_handle_cqe(nvmeq, start);
9045cb525c8SJens Axboe 		if (++start == nvmeq->q_depth)
9055cb525c8SJens Axboe 			start = 0;
9065cb525c8SJens Axboe 	}
9075cb525c8SJens Axboe }
90883a12fb7SSagi Grimberg 
9095cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
9105cb525c8SJens Axboe {
911920d13a8SSagi Grimberg 	if (++nvmeq->cq_head == nvmeq->q_depth) {
912920d13a8SSagi Grimberg 		nvmeq->cq_head = 0;
913920d13a8SSagi Grimberg 		nvmeq->cq_phase = !nvmeq->cq_phase;
914920d13a8SSagi Grimberg 	}
915a0fa9647SJens Axboe }
916a0fa9647SJens Axboe 
9175cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start,
9185cb525c8SJens Axboe 		u16 *end, int tag)
919a0fa9647SJens Axboe {
9205cb525c8SJens Axboe 	bool found = false;
92183a12fb7SSagi Grimberg 
9225cb525c8SJens Axboe 	*start = nvmeq->cq_head;
9235cb525c8SJens Axboe 	while (!found && nvme_cqe_pending(nvmeq)) {
9245cb525c8SJens Axboe 		if (nvmeq->cqes[nvmeq->cq_head].command_id == tag)
9255cb525c8SJens Axboe 			found = true;
9265cb525c8SJens Axboe 		nvme_update_cq_head(nvmeq);
92757dacad5SJay Sternberg 	}
9285cb525c8SJens Axboe 	*end = nvmeq->cq_head;
92957dacad5SJay Sternberg 
9305cb525c8SJens Axboe 	if (*start != *end)
931eb281c82SSagi Grimberg 		nvme_ring_cq_doorbell(nvmeq);
9325cb525c8SJens Axboe 	return found;
93357dacad5SJay Sternberg }
93457dacad5SJay Sternberg 
93557dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data)
93657dacad5SJay Sternberg {
93757dacad5SJay Sternberg 	struct nvme_queue *nvmeq = data;
93868fa9dbeSJens Axboe 	irqreturn_t ret = IRQ_NONE;
9395cb525c8SJens Axboe 	u16 start, end;
9405cb525c8SJens Axboe 
9411ab0cd69SJens Axboe 	spin_lock(&nvmeq->cq_lock);
94268fa9dbeSJens Axboe 	if (nvmeq->cq_head != nvmeq->last_cq_head)
94368fa9dbeSJens Axboe 		ret = IRQ_HANDLED;
9445cb525c8SJens Axboe 	nvme_process_cq(nvmeq, &start, &end, -1);
94568fa9dbeSJens Axboe 	nvmeq->last_cq_head = nvmeq->cq_head;
9461ab0cd69SJens Axboe 	spin_unlock(&nvmeq->cq_lock);
9475cb525c8SJens Axboe 
94868fa9dbeSJens Axboe 	if (start != end) {
9495cb525c8SJens Axboe 		nvme_complete_cqes(nvmeq, start, end);
9505cb525c8SJens Axboe 		return IRQ_HANDLED;
95157dacad5SJay Sternberg 	}
95257dacad5SJay Sternberg 
95368fa9dbeSJens Axboe 	return ret;
95457dacad5SJay Sternberg }
95557dacad5SJay Sternberg 
95657dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data)
95757dacad5SJay Sternberg {
95857dacad5SJay Sternberg 	struct nvme_queue *nvmeq = data;
959750dde44SChristoph Hellwig 	if (nvme_cqe_pending(nvmeq))
96057dacad5SJay Sternberg 		return IRQ_WAKE_THREAD;
961d783e0bdSMarta Rybczynska 	return IRQ_NONE;
96257dacad5SJay Sternberg }
96357dacad5SJay Sternberg 
9647776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
965a0fa9647SJens Axboe {
9665cb525c8SJens Axboe 	u16 start, end;
9675cb525c8SJens Axboe 	bool found;
968a0fa9647SJens Axboe 
969750dde44SChristoph Hellwig 	if (!nvme_cqe_pending(nvmeq))
970442e19b7SSagi Grimberg 		return 0;
971442e19b7SSagi Grimberg 
9721ab0cd69SJens Axboe 	spin_lock_irq(&nvmeq->cq_lock);
9735cb525c8SJens Axboe 	found = nvme_process_cq(nvmeq, &start, &end, tag);
9741ab0cd69SJens Axboe 	spin_unlock_irq(&nvmeq->cq_lock);
975442e19b7SSagi Grimberg 
9765cb525c8SJens Axboe 	nvme_complete_cqes(nvmeq, start, end);
977442e19b7SSagi Grimberg 	return found;
978a0fa9647SJens Axboe }
979a0fa9647SJens Axboe 
9807776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
9817776db1cSKeith Busch {
9827776db1cSKeith Busch 	struct nvme_queue *nvmeq = hctx->driver_data;
9837776db1cSKeith Busch 
9847776db1cSKeith Busch 	return __nvme_poll(nvmeq, tag);
9857776db1cSKeith Busch }
9867776db1cSKeith Busch 
987ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
98857dacad5SJay Sternberg {
989f866fc42SChristoph Hellwig 	struct nvme_dev *dev = to_nvme_dev(ctrl);
990147b27e4SSagi Grimberg 	struct nvme_queue *nvmeq = &dev->queues[0];
99157dacad5SJay Sternberg 	struct nvme_command c;
99257dacad5SJay Sternberg 
99357dacad5SJay Sternberg 	memset(&c, 0, sizeof(c));
99457dacad5SJay Sternberg 	c.common.opcode = nvme_admin_async_event;
995ad22c355SKeith Busch 	c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
99690ea5ca4SChristoph Hellwig 	nvme_submit_cmd(nvmeq, &c);
99757dacad5SJay Sternberg }
99857dacad5SJay Sternberg 
99957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
100057dacad5SJay Sternberg {
100157dacad5SJay Sternberg 	struct nvme_command c;
100257dacad5SJay Sternberg 
100357dacad5SJay Sternberg 	memset(&c, 0, sizeof(c));
100457dacad5SJay Sternberg 	c.delete_queue.opcode = opcode;
100557dacad5SJay Sternberg 	c.delete_queue.qid = cpu_to_le16(id);
100657dacad5SJay Sternberg 
10071c63dc66SChristoph Hellwig 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
100857dacad5SJay Sternberg }
100957dacad5SJay Sternberg 
101057dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1011a8e3e0bbSJianchao Wang 		struct nvme_queue *nvmeq, s16 vector)
101257dacad5SJay Sternberg {
101357dacad5SJay Sternberg 	struct nvme_command c;
101457dacad5SJay Sternberg 	int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
101557dacad5SJay Sternberg 
101657dacad5SJay Sternberg 	/*
101716772ae6SMinwoo Im 	 * Note: we (ab)use the fact that the prp fields survive if no data
101857dacad5SJay Sternberg 	 * is attached to the request.
101957dacad5SJay Sternberg 	 */
102057dacad5SJay Sternberg 	memset(&c, 0, sizeof(c));
102157dacad5SJay Sternberg 	c.create_cq.opcode = nvme_admin_create_cq;
102257dacad5SJay Sternberg 	c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
102357dacad5SJay Sternberg 	c.create_cq.cqid = cpu_to_le16(qid);
102457dacad5SJay Sternberg 	c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
102557dacad5SJay Sternberg 	c.create_cq.cq_flags = cpu_to_le16(flags);
1026a8e3e0bbSJianchao Wang 	c.create_cq.irq_vector = cpu_to_le16(vector);
102757dacad5SJay Sternberg 
10281c63dc66SChristoph Hellwig 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
102957dacad5SJay Sternberg }
103057dacad5SJay Sternberg 
103157dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
103257dacad5SJay Sternberg 						struct nvme_queue *nvmeq)
103357dacad5SJay Sternberg {
10349abd68efSJens Axboe 	struct nvme_ctrl *ctrl = &dev->ctrl;
103557dacad5SJay Sternberg 	struct nvme_command c;
103681c1cd98SKeith Busch 	int flags = NVME_QUEUE_PHYS_CONTIG;
103757dacad5SJay Sternberg 
103857dacad5SJay Sternberg 	/*
10399abd68efSJens Axboe 	 * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
10409abd68efSJens Axboe 	 * set. Since URGENT priority is zeroes, it makes all queues
10419abd68efSJens Axboe 	 * URGENT.
10429abd68efSJens Axboe 	 */
10439abd68efSJens Axboe 	if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
10449abd68efSJens Axboe 		flags |= NVME_SQ_PRIO_MEDIUM;
10459abd68efSJens Axboe 
10469abd68efSJens Axboe 	/*
104716772ae6SMinwoo Im 	 * Note: we (ab)use the fact that the prp fields survive if no data
104857dacad5SJay Sternberg 	 * is attached to the request.
104957dacad5SJay Sternberg 	 */
105057dacad5SJay Sternberg 	memset(&c, 0, sizeof(c));
105157dacad5SJay Sternberg 	c.create_sq.opcode = nvme_admin_create_sq;
105257dacad5SJay Sternberg 	c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
105357dacad5SJay Sternberg 	c.create_sq.sqid = cpu_to_le16(qid);
105457dacad5SJay Sternberg 	c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
105557dacad5SJay Sternberg 	c.create_sq.sq_flags = cpu_to_le16(flags);
105657dacad5SJay Sternberg 	c.create_sq.cqid = cpu_to_le16(qid);
105757dacad5SJay Sternberg 
10581c63dc66SChristoph Hellwig 	return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
105957dacad5SJay Sternberg }
106057dacad5SJay Sternberg 
106157dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
106257dacad5SJay Sternberg {
106357dacad5SJay Sternberg 	return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
106457dacad5SJay Sternberg }
106557dacad5SJay Sternberg 
106657dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
106757dacad5SJay Sternberg {
106857dacad5SJay Sternberg 	return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
106957dacad5SJay Sternberg }
107057dacad5SJay Sternberg 
10712a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error)
107257dacad5SJay Sternberg {
1073f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1074f4800d6dSChristoph Hellwig 	struct nvme_queue *nvmeq = iod->nvmeq;
107557dacad5SJay Sternberg 
107627fa9bc5SChristoph Hellwig 	dev_warn(nvmeq->dev->ctrl.device,
107727fa9bc5SChristoph Hellwig 		 "Abort status: 0x%x", nvme_req(req)->status);
1078e7a2a87dSChristoph Hellwig 	atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1079e7a2a87dSChristoph Hellwig 	blk_mq_free_request(req);
108057dacad5SJay Sternberg }
108157dacad5SJay Sternberg 
1082b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1083b2a0eb1aSKeith Busch {
1084b2a0eb1aSKeith Busch 
1085b2a0eb1aSKeith Busch 	/* If true, indicates loss of adapter communication, possibly by a
1086b2a0eb1aSKeith Busch 	 * NVMe Subsystem reset.
1087b2a0eb1aSKeith Busch 	 */
1088b2a0eb1aSKeith Busch 	bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1089b2a0eb1aSKeith Busch 
1090ad70062cSJianchao Wang 	/* If there is a reset/reinit ongoing, we shouldn't reset again. */
1091ad70062cSJianchao Wang 	switch (dev->ctrl.state) {
1092ad70062cSJianchao Wang 	case NVME_CTRL_RESETTING:
1093ad6a0a52SMax Gurtovoy 	case NVME_CTRL_CONNECTING:
1094b2a0eb1aSKeith Busch 		return false;
1095ad70062cSJianchao Wang 	default:
1096ad70062cSJianchao Wang 		break;
1097ad70062cSJianchao Wang 	}
1098b2a0eb1aSKeith Busch 
1099b2a0eb1aSKeith Busch 	/* We shouldn't reset unless the controller is on fatal error state
1100b2a0eb1aSKeith Busch 	 * _or_ if we lost the communication with it.
1101b2a0eb1aSKeith Busch 	 */
1102b2a0eb1aSKeith Busch 	if (!(csts & NVME_CSTS_CFS) && !nssro)
1103b2a0eb1aSKeith Busch 		return false;
1104b2a0eb1aSKeith Busch 
1105b2a0eb1aSKeith Busch 	return true;
1106b2a0eb1aSKeith Busch }
1107b2a0eb1aSKeith Busch 
1108b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1109b2a0eb1aSKeith Busch {
1110b2a0eb1aSKeith Busch 	/* Read a config register to help see what died. */
1111b2a0eb1aSKeith Busch 	u16 pci_status;
1112b2a0eb1aSKeith Busch 	int result;
1113b2a0eb1aSKeith Busch 
1114b2a0eb1aSKeith Busch 	result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1115b2a0eb1aSKeith Busch 				      &pci_status);
1116b2a0eb1aSKeith Busch 	if (result == PCIBIOS_SUCCESSFUL)
1117b2a0eb1aSKeith Busch 		dev_warn(dev->ctrl.device,
1118b2a0eb1aSKeith Busch 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1119b2a0eb1aSKeith Busch 			 csts, pci_status);
1120b2a0eb1aSKeith Busch 	else
1121b2a0eb1aSKeith Busch 		dev_warn(dev->ctrl.device,
1122b2a0eb1aSKeith Busch 			 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1123b2a0eb1aSKeith Busch 			 csts, result);
1124b2a0eb1aSKeith Busch }
1125b2a0eb1aSKeith Busch 
112631c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
112757dacad5SJay Sternberg {
1128f4800d6dSChristoph Hellwig 	struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1129f4800d6dSChristoph Hellwig 	struct nvme_queue *nvmeq = iod->nvmeq;
113057dacad5SJay Sternberg 	struct nvme_dev *dev = nvmeq->dev;
113157dacad5SJay Sternberg 	struct request *abort_req;
113257dacad5SJay Sternberg 	struct nvme_command cmd;
1133b2a0eb1aSKeith Busch 	u32 csts = readl(dev->bar + NVME_REG_CSTS);
1134b2a0eb1aSKeith Busch 
1135651438bbSWen Xiong 	/* If PCI error recovery process is happening, we cannot reset or
1136651438bbSWen Xiong 	 * the recovery mechanism will surely fail.
1137651438bbSWen Xiong 	 */
1138651438bbSWen Xiong 	mb();
1139651438bbSWen Xiong 	if (pci_channel_offline(to_pci_dev(dev->dev)))
1140651438bbSWen Xiong 		return BLK_EH_RESET_TIMER;
1141651438bbSWen Xiong 
1142b2a0eb1aSKeith Busch 	/*
1143b2a0eb1aSKeith Busch 	 * Reset immediately if the controller is failed
1144b2a0eb1aSKeith Busch 	 */
1145b2a0eb1aSKeith Busch 	if (nvme_should_reset(dev, csts)) {
1146b2a0eb1aSKeith Busch 		nvme_warn_reset(dev, csts);
1147b2a0eb1aSKeith Busch 		nvme_dev_disable(dev, false);
1148d86c4d8eSChristoph Hellwig 		nvme_reset_ctrl(&dev->ctrl);
1149db8c48e4SChristoph Hellwig 		return BLK_EH_DONE;
1150b2a0eb1aSKeith Busch 	}
115157dacad5SJay Sternberg 
115231c7c7d2SChristoph Hellwig 	/*
11537776db1cSKeith Busch 	 * Did we miss an interrupt?
11547776db1cSKeith Busch 	 */
11557776db1cSKeith Busch 	if (__nvme_poll(nvmeq, req->tag)) {
11567776db1cSKeith Busch 		dev_warn(dev->ctrl.device,
11577776db1cSKeith Busch 			 "I/O %d QID %d timeout, completion polled\n",
11587776db1cSKeith Busch 			 req->tag, nvmeq->qid);
1159db8c48e4SChristoph Hellwig 		return BLK_EH_DONE;
11607776db1cSKeith Busch 	}
11617776db1cSKeith Busch 
11627776db1cSKeith Busch 	/*
1163fd634f41SChristoph Hellwig 	 * Shutdown immediately if controller times out while starting. The
1164fd634f41SChristoph Hellwig 	 * reset work will see the pci device disabled when it gets the forced
1165fd634f41SChristoph Hellwig 	 * cancellation error. All outstanding requests are completed on
1166db8c48e4SChristoph Hellwig 	 * shutdown, so we return BLK_EH_DONE.
1167fd634f41SChristoph Hellwig 	 */
11684244140dSKeith Busch 	switch (dev->ctrl.state) {
11694244140dSKeith Busch 	case NVME_CTRL_CONNECTING:
11704244140dSKeith Busch 	case NVME_CTRL_RESETTING:
1171b9cac43cSKeith Busch 		dev_warn_ratelimited(dev->ctrl.device,
1172fd634f41SChristoph Hellwig 			 "I/O %d QID %d timeout, disable controller\n",
1173fd634f41SChristoph Hellwig 			 req->tag, nvmeq->qid);
1174a5cdb68cSKeith Busch 		nvme_dev_disable(dev, false);
117527fa9bc5SChristoph Hellwig 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1176db8c48e4SChristoph Hellwig 		return BLK_EH_DONE;
11774244140dSKeith Busch 	default:
11784244140dSKeith Busch 		break;
1179fd634f41SChristoph Hellwig 	}
1180fd634f41SChristoph Hellwig 
1181fd634f41SChristoph Hellwig 	/*
1182e1569a16SKeith Busch  	 * Shutdown the controller immediately and schedule a reset if the
1183e1569a16SKeith Busch  	 * command was already aborted once before and still hasn't been
1184e1569a16SKeith Busch  	 * returned to the driver, or if this is the admin queue.
118531c7c7d2SChristoph Hellwig 	 */
1186f4800d6dSChristoph Hellwig 	if (!nvmeq->qid || iod->aborted) {
11871b3c47c1SSagi Grimberg 		dev_warn(dev->ctrl.device,
118857dacad5SJay Sternberg 			 "I/O %d QID %d timeout, reset controller\n",
118957dacad5SJay Sternberg 			 req->tag, nvmeq->qid);
1190a5cdb68cSKeith Busch 		nvme_dev_disable(dev, false);
1191d86c4d8eSChristoph Hellwig 		nvme_reset_ctrl(&dev->ctrl);
1192e1569a16SKeith Busch 
119327fa9bc5SChristoph Hellwig 		nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1194db8c48e4SChristoph Hellwig 		return BLK_EH_DONE;
119557dacad5SJay Sternberg 	}
119657dacad5SJay Sternberg 
1197e7a2a87dSChristoph Hellwig 	if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1198e7a2a87dSChristoph Hellwig 		atomic_inc(&dev->ctrl.abort_limit);
1199e7a2a87dSChristoph Hellwig 		return BLK_EH_RESET_TIMER;
1200e7a2a87dSChristoph Hellwig 	}
12017bf7d778SKeith Busch 	iod->aborted = 1;
120257dacad5SJay Sternberg 
120357dacad5SJay Sternberg 	memset(&cmd, 0, sizeof(cmd));
120457dacad5SJay Sternberg 	cmd.abort.opcode = nvme_admin_abort_cmd;
120557dacad5SJay Sternberg 	cmd.abort.cid = req->tag;
120657dacad5SJay Sternberg 	cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
120757dacad5SJay Sternberg 
12081b3c47c1SSagi Grimberg 	dev_warn(nvmeq->dev->ctrl.device,
12091b3c47c1SSagi Grimberg 		"I/O %d QID %d timeout, aborting\n",
121057dacad5SJay Sternberg 		 req->tag, nvmeq->qid);
1211e7a2a87dSChristoph Hellwig 
1212e7a2a87dSChristoph Hellwig 	abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1213eb71f435SChristoph Hellwig 			BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
12146bf25d16SChristoph Hellwig 	if (IS_ERR(abort_req)) {
12156bf25d16SChristoph Hellwig 		atomic_inc(&dev->ctrl.abort_limit);
121631c7c7d2SChristoph Hellwig 		return BLK_EH_RESET_TIMER;
121757dacad5SJay Sternberg 	}
121857dacad5SJay Sternberg 
1219e7a2a87dSChristoph Hellwig 	abort_req->timeout = ADMIN_TIMEOUT;
1220e7a2a87dSChristoph Hellwig 	abort_req->end_io_data = NULL;
1221e7a2a87dSChristoph Hellwig 	blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
122257dacad5SJay Sternberg 
122357dacad5SJay Sternberg 	/*
122457dacad5SJay Sternberg 	 * The aborted req will be completed on receiving the abort req.
122557dacad5SJay Sternberg 	 * We enable the timer again. If hit twice, it'll cause a device reset,
122657dacad5SJay Sternberg 	 * as the device then is in a faulty state.
122757dacad5SJay Sternberg 	 */
122857dacad5SJay Sternberg 	return BLK_EH_RESET_TIMER;
122957dacad5SJay Sternberg }
123057dacad5SJay Sternberg 
123157dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq)
123257dacad5SJay Sternberg {
123357dacad5SJay Sternberg 	dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
123457dacad5SJay Sternberg 				(void *)nvmeq->cqes, nvmeq->cq_dma_addr);
123557dacad5SJay Sternberg 	if (nvmeq->sq_cmds)
123657dacad5SJay Sternberg 		dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
123757dacad5SJay Sternberg 					nvmeq->sq_cmds, nvmeq->sq_dma_addr);
123857dacad5SJay Sternberg }
123957dacad5SJay Sternberg 
124057dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest)
124157dacad5SJay Sternberg {
124257dacad5SJay Sternberg 	int i;
124357dacad5SJay Sternberg 
1244d858e5f0SSagi Grimberg 	for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1245d858e5f0SSagi Grimberg 		dev->ctrl.queue_count--;
1246147b27e4SSagi Grimberg 		nvme_free_queue(&dev->queues[i]);
124757dacad5SJay Sternberg 	}
124857dacad5SJay Sternberg }
124957dacad5SJay Sternberg 
125057dacad5SJay Sternberg /**
125157dacad5SJay Sternberg  * nvme_suspend_queue - put queue into suspended state
125257dacad5SJay Sternberg  * @nvmeq - queue to suspend
125357dacad5SJay Sternberg  */
125457dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq)
125557dacad5SJay Sternberg {
125657dacad5SJay Sternberg 	int vector;
125757dacad5SJay Sternberg 
12581ab0cd69SJens Axboe 	spin_lock_irq(&nvmeq->cq_lock);
125957dacad5SJay Sternberg 	if (nvmeq->cq_vector == -1) {
12601ab0cd69SJens Axboe 		spin_unlock_irq(&nvmeq->cq_lock);
126157dacad5SJay Sternberg 		return 1;
126257dacad5SJay Sternberg 	}
12630ff199cbSChristoph Hellwig 	vector = nvmeq->cq_vector;
126457dacad5SJay Sternberg 	nvmeq->dev->online_queues--;
126557dacad5SJay Sternberg 	nvmeq->cq_vector = -1;
12661ab0cd69SJens Axboe 	spin_unlock_irq(&nvmeq->cq_lock);
126757dacad5SJay Sternberg 
1268d1f06f4aSJens Axboe 	/*
1269d1f06f4aSJens Axboe 	 * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without
1270d1f06f4aSJens Axboe 	 * having to grab the lock.
1271d1f06f4aSJens Axboe 	 */
1272d1f06f4aSJens Axboe 	mb();
127357dacad5SJay Sternberg 
12741c63dc66SChristoph Hellwig 	if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1275c81545f9SSagi Grimberg 		blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
127657dacad5SJay Sternberg 
12770ff199cbSChristoph Hellwig 	pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
127857dacad5SJay Sternberg 
127957dacad5SJay Sternberg 	return 0;
128057dacad5SJay Sternberg }
128157dacad5SJay Sternberg 
1282a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
128357dacad5SJay Sternberg {
1284147b27e4SSagi Grimberg 	struct nvme_queue *nvmeq = &dev->queues[0];
12855cb525c8SJens Axboe 	u16 start, end;
128657dacad5SJay Sternberg 
1287a5cdb68cSKeith Busch 	if (shutdown)
1288a5cdb68cSKeith Busch 		nvme_shutdown_ctrl(&dev->ctrl);
1289a5cdb68cSKeith Busch 	else
129020d0dfe6SSagi Grimberg 		nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
129157dacad5SJay Sternberg 
12921ab0cd69SJens Axboe 	spin_lock_irq(&nvmeq->cq_lock);
12935cb525c8SJens Axboe 	nvme_process_cq(nvmeq, &start, &end, -1);
12941ab0cd69SJens Axboe 	spin_unlock_irq(&nvmeq->cq_lock);
12955cb525c8SJens Axboe 
12965cb525c8SJens Axboe 	nvme_complete_cqes(nvmeq, start, end);
129757dacad5SJay Sternberg }
129857dacad5SJay Sternberg 
129957dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
130057dacad5SJay Sternberg 				int entry_size)
130157dacad5SJay Sternberg {
130257dacad5SJay Sternberg 	int q_depth = dev->q_depth;
13035fd4ce1bSChristoph Hellwig 	unsigned q_size_aligned = roundup(q_depth * entry_size,
13045fd4ce1bSChristoph Hellwig 					  dev->ctrl.page_size);
130557dacad5SJay Sternberg 
130657dacad5SJay Sternberg 	if (q_size_aligned * nr_io_queues > dev->cmb_size) {
130757dacad5SJay Sternberg 		u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
13085fd4ce1bSChristoph Hellwig 		mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
130957dacad5SJay Sternberg 		q_depth = div_u64(mem_per_q, entry_size);
131057dacad5SJay Sternberg 
131157dacad5SJay Sternberg 		/*
131257dacad5SJay Sternberg 		 * Ensure the reduced q_depth is above some threshold where it
131357dacad5SJay Sternberg 		 * would be better to map queues in system memory with the
131457dacad5SJay Sternberg 		 * original depth
131557dacad5SJay Sternberg 		 */
131657dacad5SJay Sternberg 		if (q_depth < 64)
131757dacad5SJay Sternberg 			return -ENOMEM;
131857dacad5SJay Sternberg 	}
131957dacad5SJay Sternberg 
132057dacad5SJay Sternberg 	return q_depth;
132157dacad5SJay Sternberg }
132257dacad5SJay Sternberg 
132357dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
132457dacad5SJay Sternberg 				int qid, int depth)
132557dacad5SJay Sternberg {
1326815c6704SKeith Busch 	/* CMB SQEs will be mapped before creation */
1327815c6704SKeith Busch 	if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS))
1328815c6704SKeith Busch 		return 0;
1329815c6704SKeith Busch 
133057dacad5SJay Sternberg 	nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
133157dacad5SJay Sternberg 					    &nvmeq->sq_dma_addr, GFP_KERNEL);
133257dacad5SJay Sternberg 	if (!nvmeq->sq_cmds)
133357dacad5SJay Sternberg 		return -ENOMEM;
133457dacad5SJay Sternberg 	return 0;
133557dacad5SJay Sternberg }
133657dacad5SJay Sternberg 
1337a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
133857dacad5SJay Sternberg {
1339147b27e4SSagi Grimberg 	struct nvme_queue *nvmeq = &dev->queues[qid];
134057dacad5SJay Sternberg 
134162314e40SKeith Busch 	if (dev->ctrl.queue_count > qid)
134262314e40SKeith Busch 		return 0;
134357dacad5SJay Sternberg 
134457dacad5SJay Sternberg 	nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
134557dacad5SJay Sternberg 					  &nvmeq->cq_dma_addr, GFP_KERNEL);
134657dacad5SJay Sternberg 	if (!nvmeq->cqes)
134757dacad5SJay Sternberg 		goto free_nvmeq;
134857dacad5SJay Sternberg 
134957dacad5SJay Sternberg 	if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
135057dacad5SJay Sternberg 		goto free_cqdma;
135157dacad5SJay Sternberg 
135257dacad5SJay Sternberg 	nvmeq->q_dmadev = dev->dev;
135357dacad5SJay Sternberg 	nvmeq->dev = dev;
13541ab0cd69SJens Axboe 	spin_lock_init(&nvmeq->sq_lock);
13551ab0cd69SJens Axboe 	spin_lock_init(&nvmeq->cq_lock);
135657dacad5SJay Sternberg 	nvmeq->cq_head = 0;
135757dacad5SJay Sternberg 	nvmeq->cq_phase = 1;
135857dacad5SJay Sternberg 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
135957dacad5SJay Sternberg 	nvmeq->q_depth = depth;
136057dacad5SJay Sternberg 	nvmeq->qid = qid;
136157dacad5SJay Sternberg 	nvmeq->cq_vector = -1;
1362d858e5f0SSagi Grimberg 	dev->ctrl.queue_count++;
136357dacad5SJay Sternberg 
1364147b27e4SSagi Grimberg 	return 0;
136557dacad5SJay Sternberg 
136657dacad5SJay Sternberg  free_cqdma:
136757dacad5SJay Sternberg 	dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
136857dacad5SJay Sternberg 							nvmeq->cq_dma_addr);
136957dacad5SJay Sternberg  free_nvmeq:
1370147b27e4SSagi Grimberg 	return -ENOMEM;
137157dacad5SJay Sternberg }
137257dacad5SJay Sternberg 
1373dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq)
137457dacad5SJay Sternberg {
13750ff199cbSChristoph Hellwig 	struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
13760ff199cbSChristoph Hellwig 	int nr = nvmeq->dev->ctrl.instance;
13770ff199cbSChristoph Hellwig 
13780ff199cbSChristoph Hellwig 	if (use_threaded_interrupts) {
13790ff199cbSChristoph Hellwig 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
13800ff199cbSChristoph Hellwig 				nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
13810ff199cbSChristoph Hellwig 	} else {
13820ff199cbSChristoph Hellwig 		return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
13830ff199cbSChristoph Hellwig 				NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
13840ff199cbSChristoph Hellwig 	}
138557dacad5SJay Sternberg }
138657dacad5SJay Sternberg 
138757dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
138857dacad5SJay Sternberg {
138957dacad5SJay Sternberg 	struct nvme_dev *dev = nvmeq->dev;
139057dacad5SJay Sternberg 
13911ab0cd69SJens Axboe 	spin_lock_irq(&nvmeq->cq_lock);
139257dacad5SJay Sternberg 	nvmeq->sq_tail = 0;
139357dacad5SJay Sternberg 	nvmeq->cq_head = 0;
139457dacad5SJay Sternberg 	nvmeq->cq_phase = 1;
139557dacad5SJay Sternberg 	nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
139657dacad5SJay Sternberg 	memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1397f9f38e33SHelen Koike 	nvme_dbbuf_init(dev, nvmeq, qid);
139857dacad5SJay Sternberg 	dev->online_queues++;
13991ab0cd69SJens Axboe 	spin_unlock_irq(&nvmeq->cq_lock);
140057dacad5SJay Sternberg }
140157dacad5SJay Sternberg 
140257dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
140357dacad5SJay Sternberg {
140457dacad5SJay Sternberg 	struct nvme_dev *dev = nvmeq->dev;
140557dacad5SJay Sternberg 	int result;
1406a8e3e0bbSJianchao Wang 	s16 vector;
140757dacad5SJay Sternberg 
1408815c6704SKeith Busch 	if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1409815c6704SKeith Busch 		unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth),
1410815c6704SKeith Busch 						      dev->ctrl.page_size);
1411815c6704SKeith Busch 		nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset;
1412815c6704SKeith Busch 		nvmeq->sq_cmds_io = dev->cmb + offset;
1413815c6704SKeith Busch 	}
1414815c6704SKeith Busch 
141522b55601SKeith Busch 	/*
141622b55601SKeith Busch 	 * A queue's vector matches the queue identifier unless the controller
141722b55601SKeith Busch 	 * has only one vector available.
141822b55601SKeith Busch 	 */
1419a8e3e0bbSJianchao Wang 	vector = dev->num_vecs == 1 ? 0 : qid;
1420a8e3e0bbSJianchao Wang 	result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1421ded45505SKeith Busch 	if (result)
1422ded45505SKeith Busch 		return result;
142357dacad5SJay Sternberg 
142457dacad5SJay Sternberg 	result = adapter_alloc_sq(dev, qid, nvmeq);
142557dacad5SJay Sternberg 	if (result < 0)
1426ded45505SKeith Busch 		return result;
1427ded45505SKeith Busch 	else if (result)
142857dacad5SJay Sternberg 		goto release_cq;
142957dacad5SJay Sternberg 
1430a8e3e0bbSJianchao Wang 	/*
1431a8e3e0bbSJianchao Wang 	 * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will
1432a8e3e0bbSJianchao Wang 	 * invoke free_irq for it and cause a 'Trying to free already-free IRQ
1433a8e3e0bbSJianchao Wang 	 * xxx' warning if the create CQ/SQ command times out.
1434a8e3e0bbSJianchao Wang 	 */
1435a8e3e0bbSJianchao Wang 	nvmeq->cq_vector = vector;
1436161b8be2SKeith Busch 	nvme_init_queue(nvmeq, qid);
1437dca51e78SChristoph Hellwig 	result = queue_request_irq(nvmeq);
143857dacad5SJay Sternberg 	if (result < 0)
143957dacad5SJay Sternberg 		goto release_sq;
144057dacad5SJay Sternberg 
144157dacad5SJay Sternberg 	return result;
144257dacad5SJay Sternberg 
144357dacad5SJay Sternberg release_sq:
1444a8e3e0bbSJianchao Wang 	nvmeq->cq_vector = -1;
1445f25a2dfcSJianchao Wang 	dev->online_queues--;
144657dacad5SJay Sternberg 	adapter_delete_sq(dev, qid);
144757dacad5SJay Sternberg release_cq:
144857dacad5SJay Sternberg 	adapter_delete_cq(dev, qid);
144957dacad5SJay Sternberg 	return result;
145057dacad5SJay Sternberg }
145157dacad5SJay Sternberg 
1452f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = {
145357dacad5SJay Sternberg 	.queue_rq	= nvme_queue_rq,
145477f02a7aSChristoph Hellwig 	.complete	= nvme_pci_complete_rq,
145557dacad5SJay Sternberg 	.init_hctx	= nvme_admin_init_hctx,
145657dacad5SJay Sternberg 	.exit_hctx      = nvme_admin_exit_hctx,
14570350815aSChristoph Hellwig 	.init_request	= nvme_init_request,
145857dacad5SJay Sternberg 	.timeout	= nvme_timeout,
145957dacad5SJay Sternberg };
146057dacad5SJay Sternberg 
1461f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = {
146257dacad5SJay Sternberg 	.queue_rq	= nvme_queue_rq,
146377f02a7aSChristoph Hellwig 	.complete	= nvme_pci_complete_rq,
146457dacad5SJay Sternberg 	.init_hctx	= nvme_init_hctx,
146557dacad5SJay Sternberg 	.init_request	= nvme_init_request,
1466dca51e78SChristoph Hellwig 	.map_queues	= nvme_pci_map_queues,
146757dacad5SJay Sternberg 	.timeout	= nvme_timeout,
1468a0fa9647SJens Axboe 	.poll		= nvme_poll,
146957dacad5SJay Sternberg };
147057dacad5SJay Sternberg 
147157dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev)
147257dacad5SJay Sternberg {
14731c63dc66SChristoph Hellwig 	if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
147469d9a99cSKeith Busch 		/*
147569d9a99cSKeith Busch 		 * If the controller was reset during removal, it's possible
147669d9a99cSKeith Busch 		 * user requests may be waiting on a stopped queue. Start the
147769d9a99cSKeith Busch 		 * queue to flush these to completion.
147869d9a99cSKeith Busch 		 */
1479c81545f9SSagi Grimberg 		blk_mq_unquiesce_queue(dev->ctrl.admin_q);
14801c63dc66SChristoph Hellwig 		blk_cleanup_queue(dev->ctrl.admin_q);
148157dacad5SJay Sternberg 		blk_mq_free_tag_set(&dev->admin_tagset);
148257dacad5SJay Sternberg 	}
148357dacad5SJay Sternberg }
148457dacad5SJay Sternberg 
148557dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev)
148657dacad5SJay Sternberg {
14871c63dc66SChristoph Hellwig 	if (!dev->ctrl.admin_q) {
148857dacad5SJay Sternberg 		dev->admin_tagset.ops = &nvme_mq_admin_ops;
148957dacad5SJay Sternberg 		dev->admin_tagset.nr_hw_queues = 1;
1490e3e9d50cSKeith Busch 
149138dabe21SKeith Busch 		dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
149257dacad5SJay Sternberg 		dev->admin_tagset.timeout = ADMIN_TIMEOUT;
149357dacad5SJay Sternberg 		dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1494a7a7cbe3SChaitanya Kulkarni 		dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false);
1495d3484991SJens Axboe 		dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
149657dacad5SJay Sternberg 		dev->admin_tagset.driver_data = dev;
149757dacad5SJay Sternberg 
149857dacad5SJay Sternberg 		if (blk_mq_alloc_tag_set(&dev->admin_tagset))
149957dacad5SJay Sternberg 			return -ENOMEM;
150034b6c231SSagi Grimberg 		dev->ctrl.admin_tagset = &dev->admin_tagset;
150157dacad5SJay Sternberg 
15021c63dc66SChristoph Hellwig 		dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
15031c63dc66SChristoph Hellwig 		if (IS_ERR(dev->ctrl.admin_q)) {
150457dacad5SJay Sternberg 			blk_mq_free_tag_set(&dev->admin_tagset);
150557dacad5SJay Sternberg 			return -ENOMEM;
150657dacad5SJay Sternberg 		}
15071c63dc66SChristoph Hellwig 		if (!blk_get_queue(dev->ctrl.admin_q)) {
150857dacad5SJay Sternberg 			nvme_dev_remove_admin(dev);
15091c63dc66SChristoph Hellwig 			dev->ctrl.admin_q = NULL;
151057dacad5SJay Sternberg 			return -ENODEV;
151157dacad5SJay Sternberg 		}
151257dacad5SJay Sternberg 	} else
1513c81545f9SSagi Grimberg 		blk_mq_unquiesce_queue(dev->ctrl.admin_q);
151457dacad5SJay Sternberg 
151557dacad5SJay Sternberg 	return 0;
151657dacad5SJay Sternberg }
151757dacad5SJay Sternberg 
151897f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
151997f6ef64SXu Yu {
152097f6ef64SXu Yu 	return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
152197f6ef64SXu Yu }
152297f6ef64SXu Yu 
152397f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
152497f6ef64SXu Yu {
152597f6ef64SXu Yu 	struct pci_dev *pdev = to_pci_dev(dev->dev);
152697f6ef64SXu Yu 
152797f6ef64SXu Yu 	if (size <= dev->bar_mapped_size)
152897f6ef64SXu Yu 		return 0;
152997f6ef64SXu Yu 	if (size > pci_resource_len(pdev, 0))
153097f6ef64SXu Yu 		return -ENOMEM;
153197f6ef64SXu Yu 	if (dev->bar)
153297f6ef64SXu Yu 		iounmap(dev->bar);
153397f6ef64SXu Yu 	dev->bar = ioremap(pci_resource_start(pdev, 0), size);
153497f6ef64SXu Yu 	if (!dev->bar) {
153597f6ef64SXu Yu 		dev->bar_mapped_size = 0;
153697f6ef64SXu Yu 		return -ENOMEM;
153797f6ef64SXu Yu 	}
153897f6ef64SXu Yu 	dev->bar_mapped_size = size;
153997f6ef64SXu Yu 	dev->dbs = dev->bar + NVME_REG_DBS;
154097f6ef64SXu Yu 
154197f6ef64SXu Yu 	return 0;
154297f6ef64SXu Yu }
154397f6ef64SXu Yu 
154401ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
154557dacad5SJay Sternberg {
154657dacad5SJay Sternberg 	int result;
154757dacad5SJay Sternberg 	u32 aqa;
154857dacad5SJay Sternberg 	struct nvme_queue *nvmeq;
154957dacad5SJay Sternberg 
155097f6ef64SXu Yu 	result = nvme_remap_bar(dev, db_bar_size(dev, 0));
155197f6ef64SXu Yu 	if (result < 0)
155297f6ef64SXu Yu 		return result;
155397f6ef64SXu Yu 
15548ef2074dSGabriel Krisman Bertazi 	dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
155520d0dfe6SSagi Grimberg 				NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
155657dacad5SJay Sternberg 
15577a67cbeaSChristoph Hellwig 	if (dev->subsystem &&
15587a67cbeaSChristoph Hellwig 	    (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
15597a67cbeaSChristoph Hellwig 		writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
156057dacad5SJay Sternberg 
156120d0dfe6SSagi Grimberg 	result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap);
156257dacad5SJay Sternberg 	if (result < 0)
156357dacad5SJay Sternberg 		return result;
156457dacad5SJay Sternberg 
1565a6ff7262SKeith Busch 	result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1566147b27e4SSagi Grimberg 	if (result)
1567147b27e4SSagi Grimberg 		return result;
156857dacad5SJay Sternberg 
1569147b27e4SSagi Grimberg 	nvmeq = &dev->queues[0];
157057dacad5SJay Sternberg 	aqa = nvmeq->q_depth - 1;
157157dacad5SJay Sternberg 	aqa |= aqa << 16;
157257dacad5SJay Sternberg 
15737a67cbeaSChristoph Hellwig 	writel(aqa, dev->bar + NVME_REG_AQA);
15747a67cbeaSChristoph Hellwig 	lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
15757a67cbeaSChristoph Hellwig 	lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
157657dacad5SJay Sternberg 
157720d0dfe6SSagi Grimberg 	result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap);
157857dacad5SJay Sternberg 	if (result)
1579d4875622SKeith Busch 		return result;
158057dacad5SJay Sternberg 
158157dacad5SJay Sternberg 	nvmeq->cq_vector = 0;
1582161b8be2SKeith Busch 	nvme_init_queue(nvmeq, 0);
1583dca51e78SChristoph Hellwig 	result = queue_request_irq(nvmeq);
158457dacad5SJay Sternberg 	if (result) {
158557dacad5SJay Sternberg 		nvmeq->cq_vector = -1;
1586d4875622SKeith Busch 		return result;
158757dacad5SJay Sternberg 	}
158857dacad5SJay Sternberg 
158957dacad5SJay Sternberg 	return result;
159057dacad5SJay Sternberg }
159157dacad5SJay Sternberg 
1592749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev)
159357dacad5SJay Sternberg {
1594949928c1SKeith Busch 	unsigned i, max;
1595749941f2SChristoph Hellwig 	int ret = 0;
159657dacad5SJay Sternberg 
1597d858e5f0SSagi Grimberg 	for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1598a6ff7262SKeith Busch 		if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1599749941f2SChristoph Hellwig 			ret = -ENOMEM;
160057dacad5SJay Sternberg 			break;
1601749941f2SChristoph Hellwig 		}
1602749941f2SChristoph Hellwig 	}
160357dacad5SJay Sternberg 
1604d858e5f0SSagi Grimberg 	max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1605949928c1SKeith Busch 	for (i = dev->online_queues; i <= max; i++) {
1606147b27e4SSagi Grimberg 		ret = nvme_create_queue(&dev->queues[i], i);
1607d4875622SKeith Busch 		if (ret)
160857dacad5SJay Sternberg 			break;
160957dacad5SJay Sternberg 	}
161057dacad5SJay Sternberg 
1611749941f2SChristoph Hellwig 	/*
1612749941f2SChristoph Hellwig 	 * Ignore failing Create SQ/CQ commands, we can continue with less
16138adb8c14SMinwoo Im 	 * than the desired amount of queues, and even a controller without
16148adb8c14SMinwoo Im 	 * I/O queues can still be used to issue admin commands.  This might
1615749941f2SChristoph Hellwig 	 * be useful to upgrade a buggy firmware for example.
1616749941f2SChristoph Hellwig 	 */
1617749941f2SChristoph Hellwig 	return ret >= 0 ? 0 : ret;
161857dacad5SJay Sternberg }
161957dacad5SJay Sternberg 
1620202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev,
1621202021c1SStephen Bates 			     struct device_attribute *attr,
1622202021c1SStephen Bates 			     char *buf)
1623202021c1SStephen Bates {
1624202021c1SStephen Bates 	struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1625202021c1SStephen Bates 
1626c965809cSStephen Bates 	return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1627202021c1SStephen Bates 		       ndev->cmbloc, ndev->cmbsz);
1628202021c1SStephen Bates }
1629202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1630202021c1SStephen Bates 
163188de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
163257dacad5SJay Sternberg {
163388de4598SChristoph Hellwig 	u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
163488de4598SChristoph Hellwig 
163588de4598SChristoph Hellwig 	return 1ULL << (12 + 4 * szu);
163688de4598SChristoph Hellwig }
163788de4598SChristoph Hellwig 
163888de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev)
163988de4598SChristoph Hellwig {
164088de4598SChristoph Hellwig 	return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
164188de4598SChristoph Hellwig }
164288de4598SChristoph Hellwig 
1643f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev)
164457dacad5SJay Sternberg {
164588de4598SChristoph Hellwig 	u64 size, offset;
164657dacad5SJay Sternberg 	resource_size_t bar_size;
164757dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev->dev);
16488969f1f8SChristoph Hellwig 	int bar;
164957dacad5SJay Sternberg 
16507a67cbeaSChristoph Hellwig 	dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1651f65efd6dSChristoph Hellwig 	if (!dev->cmbsz)
1652f65efd6dSChristoph Hellwig 		return;
1653202021c1SStephen Bates 	dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
165457dacad5SJay Sternberg 
1655202021c1SStephen Bates 	if (!use_cmb_sqes)
1656f65efd6dSChristoph Hellwig 		return;
165757dacad5SJay Sternberg 
165888de4598SChristoph Hellwig 	size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
165988de4598SChristoph Hellwig 	offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
16608969f1f8SChristoph Hellwig 	bar = NVME_CMB_BIR(dev->cmbloc);
16618969f1f8SChristoph Hellwig 	bar_size = pci_resource_len(pdev, bar);
166257dacad5SJay Sternberg 
166357dacad5SJay Sternberg 	if (offset > bar_size)
1664f65efd6dSChristoph Hellwig 		return;
166557dacad5SJay Sternberg 
166657dacad5SJay Sternberg 	/*
166757dacad5SJay Sternberg 	 * Controllers may support a CMB size larger than their BAR,
166857dacad5SJay Sternberg 	 * for example, due to being behind a bridge. Reduce the CMB to
166957dacad5SJay Sternberg 	 * the reported size of the BAR
167057dacad5SJay Sternberg 	 */
167157dacad5SJay Sternberg 	if (size > bar_size - offset)
167257dacad5SJay Sternberg 		size = bar_size - offset;
167357dacad5SJay Sternberg 
1674f65efd6dSChristoph Hellwig 	dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size);
1675f65efd6dSChristoph Hellwig 	if (!dev->cmb)
1676f65efd6dSChristoph Hellwig 		return;
16778969f1f8SChristoph Hellwig 	dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset;
167857dacad5SJay Sternberg 	dev->cmb_size = size;
1679f65efd6dSChristoph Hellwig 
1680f65efd6dSChristoph Hellwig 	if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1681f65efd6dSChristoph Hellwig 				    &dev_attr_cmb.attr, NULL))
1682f65efd6dSChristoph Hellwig 		dev_warn(dev->ctrl.device,
1683f65efd6dSChristoph Hellwig 			 "failed to add sysfs attribute for CMB\n");
168457dacad5SJay Sternberg }
168557dacad5SJay Sternberg 
168657dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev)
168757dacad5SJay Sternberg {
168857dacad5SJay Sternberg 	if (dev->cmb) {
168957dacad5SJay Sternberg 		iounmap(dev->cmb);
169057dacad5SJay Sternberg 		dev->cmb = NULL;
1691f63572dfSJon Derrick 		sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1692f63572dfSJon Derrick 					     &dev_attr_cmb.attr, NULL);
1693f63572dfSJon Derrick 		dev->cmbsz = 0;
1694f63572dfSJon Derrick 	}
169557dacad5SJay Sternberg }
169657dacad5SJay Sternberg 
169787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
169857dacad5SJay Sternberg {
16994033f35dSChristoph Hellwig 	u64 dma_addr = dev->host_mem_descs_dma;
170087ad72a5SChristoph Hellwig 	struct nvme_command c;
170187ad72a5SChristoph Hellwig 	int ret;
170287ad72a5SChristoph Hellwig 
170387ad72a5SChristoph Hellwig 	memset(&c, 0, sizeof(c));
170487ad72a5SChristoph Hellwig 	c.features.opcode	= nvme_admin_set_features;
170587ad72a5SChristoph Hellwig 	c.features.fid		= cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
170687ad72a5SChristoph Hellwig 	c.features.dword11	= cpu_to_le32(bits);
170787ad72a5SChristoph Hellwig 	c.features.dword12	= cpu_to_le32(dev->host_mem_size >>
170887ad72a5SChristoph Hellwig 					      ilog2(dev->ctrl.page_size));
170987ad72a5SChristoph Hellwig 	c.features.dword13	= cpu_to_le32(lower_32_bits(dma_addr));
171087ad72a5SChristoph Hellwig 	c.features.dword14	= cpu_to_le32(upper_32_bits(dma_addr));
171187ad72a5SChristoph Hellwig 	c.features.dword15	= cpu_to_le32(dev->nr_host_mem_descs);
171287ad72a5SChristoph Hellwig 
171387ad72a5SChristoph Hellwig 	ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
171487ad72a5SChristoph Hellwig 	if (ret) {
171587ad72a5SChristoph Hellwig 		dev_warn(dev->ctrl.device,
171687ad72a5SChristoph Hellwig 			 "failed to set host mem (err %d, flags %#x).\n",
171787ad72a5SChristoph Hellwig 			 ret, bits);
171887ad72a5SChristoph Hellwig 	}
171987ad72a5SChristoph Hellwig 	return ret;
172087ad72a5SChristoph Hellwig }
172187ad72a5SChristoph Hellwig 
172287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev)
172387ad72a5SChristoph Hellwig {
172487ad72a5SChristoph Hellwig 	int i;
172587ad72a5SChristoph Hellwig 
172687ad72a5SChristoph Hellwig 	for (i = 0; i < dev->nr_host_mem_descs; i++) {
172787ad72a5SChristoph Hellwig 		struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
172887ad72a5SChristoph Hellwig 		size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
172987ad72a5SChristoph Hellwig 
173087ad72a5SChristoph Hellwig 		dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
173187ad72a5SChristoph Hellwig 				le64_to_cpu(desc->addr));
173287ad72a5SChristoph Hellwig 	}
173387ad72a5SChristoph Hellwig 
173487ad72a5SChristoph Hellwig 	kfree(dev->host_mem_desc_bufs);
173587ad72a5SChristoph Hellwig 	dev->host_mem_desc_bufs = NULL;
17364033f35dSChristoph Hellwig 	dma_free_coherent(dev->dev,
17374033f35dSChristoph Hellwig 			dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
17384033f35dSChristoph Hellwig 			dev->host_mem_descs, dev->host_mem_descs_dma);
173987ad72a5SChristoph Hellwig 	dev->host_mem_descs = NULL;
17407e5dd57eSMinwoo Im 	dev->nr_host_mem_descs = 0;
174187ad72a5SChristoph Hellwig }
174287ad72a5SChristoph Hellwig 
174392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
174492dc6895SChristoph Hellwig 		u32 chunk_size)
174587ad72a5SChristoph Hellwig {
174687ad72a5SChristoph Hellwig 	struct nvme_host_mem_buf_desc *descs;
174792dc6895SChristoph Hellwig 	u32 max_entries, len;
17484033f35dSChristoph Hellwig 	dma_addr_t descs_dma;
17492ee0e4edSDan Carpenter 	int i = 0;
175087ad72a5SChristoph Hellwig 	void **bufs;
17516fbcde66SMinwoo Im 	u64 size, tmp;
175287ad72a5SChristoph Hellwig 
175387ad72a5SChristoph Hellwig 	tmp = (preferred + chunk_size - 1);
175487ad72a5SChristoph Hellwig 	do_div(tmp, chunk_size);
175587ad72a5SChristoph Hellwig 	max_entries = tmp;
1756044a9df1SChristoph Hellwig 
1757044a9df1SChristoph Hellwig 	if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1758044a9df1SChristoph Hellwig 		max_entries = dev->ctrl.hmmaxd;
1759044a9df1SChristoph Hellwig 
17604033f35dSChristoph Hellwig 	descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs),
17614033f35dSChristoph Hellwig 			&descs_dma, GFP_KERNEL);
176287ad72a5SChristoph Hellwig 	if (!descs)
176387ad72a5SChristoph Hellwig 		goto out;
176487ad72a5SChristoph Hellwig 
176587ad72a5SChristoph Hellwig 	bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
176687ad72a5SChristoph Hellwig 	if (!bufs)
176787ad72a5SChristoph Hellwig 		goto out_free_descs;
176887ad72a5SChristoph Hellwig 
1769244a8fe4SMinwoo Im 	for (size = 0; size < preferred && i < max_entries; size += len) {
177087ad72a5SChristoph Hellwig 		dma_addr_t dma_addr;
177187ad72a5SChristoph Hellwig 
177250cdb7c6SChristoph Hellwig 		len = min_t(u64, chunk_size, preferred - size);
177387ad72a5SChristoph Hellwig 		bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
177487ad72a5SChristoph Hellwig 				DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
177587ad72a5SChristoph Hellwig 		if (!bufs[i])
177687ad72a5SChristoph Hellwig 			break;
177787ad72a5SChristoph Hellwig 
177887ad72a5SChristoph Hellwig 		descs[i].addr = cpu_to_le64(dma_addr);
177987ad72a5SChristoph Hellwig 		descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
178087ad72a5SChristoph Hellwig 		i++;
178187ad72a5SChristoph Hellwig 	}
178287ad72a5SChristoph Hellwig 
178392dc6895SChristoph Hellwig 	if (!size)
178487ad72a5SChristoph Hellwig 		goto out_free_bufs;
178587ad72a5SChristoph Hellwig 
178687ad72a5SChristoph Hellwig 	dev->nr_host_mem_descs = i;
178787ad72a5SChristoph Hellwig 	dev->host_mem_size = size;
178887ad72a5SChristoph Hellwig 	dev->host_mem_descs = descs;
17894033f35dSChristoph Hellwig 	dev->host_mem_descs_dma = descs_dma;
179087ad72a5SChristoph Hellwig 	dev->host_mem_desc_bufs = bufs;
179187ad72a5SChristoph Hellwig 	return 0;
179287ad72a5SChristoph Hellwig 
179387ad72a5SChristoph Hellwig out_free_bufs:
179487ad72a5SChristoph Hellwig 	while (--i >= 0) {
179587ad72a5SChristoph Hellwig 		size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
179687ad72a5SChristoph Hellwig 
179787ad72a5SChristoph Hellwig 		dma_free_coherent(dev->dev, size, bufs[i],
179887ad72a5SChristoph Hellwig 				le64_to_cpu(descs[i].addr));
179987ad72a5SChristoph Hellwig 	}
180087ad72a5SChristoph Hellwig 
180187ad72a5SChristoph Hellwig 	kfree(bufs);
180287ad72a5SChristoph Hellwig out_free_descs:
18034033f35dSChristoph Hellwig 	dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
18044033f35dSChristoph Hellwig 			descs_dma);
180587ad72a5SChristoph Hellwig out:
180687ad72a5SChristoph Hellwig 	dev->host_mem_descs = NULL;
180787ad72a5SChristoph Hellwig 	return -ENOMEM;
180887ad72a5SChristoph Hellwig }
180987ad72a5SChristoph Hellwig 
181092dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
181192dc6895SChristoph Hellwig {
181292dc6895SChristoph Hellwig 	u32 chunk_size;
181392dc6895SChristoph Hellwig 
181492dc6895SChristoph Hellwig 	/* start big and work our way down */
181530f92d62SAkinobu Mita 	for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
1816044a9df1SChristoph Hellwig 	     chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
181792dc6895SChristoph Hellwig 	     chunk_size /= 2) {
181892dc6895SChristoph Hellwig 		if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
181992dc6895SChristoph Hellwig 			if (!min || dev->host_mem_size >= min)
182092dc6895SChristoph Hellwig 				return 0;
182192dc6895SChristoph Hellwig 			nvme_free_host_mem(dev);
182292dc6895SChristoph Hellwig 		}
182392dc6895SChristoph Hellwig 	}
182492dc6895SChristoph Hellwig 
182592dc6895SChristoph Hellwig 	return -ENOMEM;
182692dc6895SChristoph Hellwig }
182792dc6895SChristoph Hellwig 
18289620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev)
182987ad72a5SChristoph Hellwig {
183087ad72a5SChristoph Hellwig 	u64 max = (u64)max_host_mem_size_mb * SZ_1M;
183187ad72a5SChristoph Hellwig 	u64 preferred = (u64)dev->ctrl.hmpre * 4096;
183287ad72a5SChristoph Hellwig 	u64 min = (u64)dev->ctrl.hmmin * 4096;
183387ad72a5SChristoph Hellwig 	u32 enable_bits = NVME_HOST_MEM_ENABLE;
18346fbcde66SMinwoo Im 	int ret;
183587ad72a5SChristoph Hellwig 
183687ad72a5SChristoph Hellwig 	preferred = min(preferred, max);
183787ad72a5SChristoph Hellwig 	if (min > max) {
183887ad72a5SChristoph Hellwig 		dev_warn(dev->ctrl.device,
183987ad72a5SChristoph Hellwig 			"min host memory (%lld MiB) above limit (%d MiB).\n",
184087ad72a5SChristoph Hellwig 			min >> ilog2(SZ_1M), max_host_mem_size_mb);
184187ad72a5SChristoph Hellwig 		nvme_free_host_mem(dev);
18429620cfbaSChristoph Hellwig 		return 0;
184387ad72a5SChristoph Hellwig 	}
184487ad72a5SChristoph Hellwig 
184587ad72a5SChristoph Hellwig 	/*
184687ad72a5SChristoph Hellwig 	 * If we already have a buffer allocated check if we can reuse it.
184787ad72a5SChristoph Hellwig 	 */
184887ad72a5SChristoph Hellwig 	if (dev->host_mem_descs) {
184987ad72a5SChristoph Hellwig 		if (dev->host_mem_size >= min)
185087ad72a5SChristoph Hellwig 			enable_bits |= NVME_HOST_MEM_RETURN;
185187ad72a5SChristoph Hellwig 		else
185287ad72a5SChristoph Hellwig 			nvme_free_host_mem(dev);
185387ad72a5SChristoph Hellwig 	}
185487ad72a5SChristoph Hellwig 
185587ad72a5SChristoph Hellwig 	if (!dev->host_mem_descs) {
185692dc6895SChristoph Hellwig 		if (nvme_alloc_host_mem(dev, min, preferred)) {
185792dc6895SChristoph Hellwig 			dev_warn(dev->ctrl.device,
185892dc6895SChristoph Hellwig 				"failed to allocate host memory buffer.\n");
18599620cfbaSChristoph Hellwig 			return 0; /* controller must work without HMB */
186087ad72a5SChristoph Hellwig 		}
186187ad72a5SChristoph Hellwig 
186292dc6895SChristoph Hellwig 		dev_info(dev->ctrl.device,
186392dc6895SChristoph Hellwig 			"allocated %lld MiB host memory buffer.\n",
186492dc6895SChristoph Hellwig 			dev->host_mem_size >> ilog2(SZ_1M));
186592dc6895SChristoph Hellwig 	}
186692dc6895SChristoph Hellwig 
18679620cfbaSChristoph Hellwig 	ret = nvme_set_host_mem(dev, enable_bits);
18689620cfbaSChristoph Hellwig 	if (ret)
186987ad72a5SChristoph Hellwig 		nvme_free_host_mem(dev);
18709620cfbaSChristoph Hellwig 	return ret;
187157dacad5SJay Sternberg }
187257dacad5SJay Sternberg 
187357dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev)
187457dacad5SJay Sternberg {
1875147b27e4SSagi Grimberg 	struct nvme_queue *adminq = &dev->queues[0];
187657dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev->dev);
187797f6ef64SXu Yu 	int result, nr_io_queues;
187897f6ef64SXu Yu 	unsigned long size;
187957dacad5SJay Sternberg 
188022b55601SKeith Busch 	struct irq_affinity affd = {
188122b55601SKeith Busch 		.pre_vectors = 1
188222b55601SKeith Busch 	};
188322b55601SKeith Busch 
188416ccfff2SMing Lei 	nr_io_queues = num_possible_cpus();
18859a0be7abSChristoph Hellwig 	result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
18869a0be7abSChristoph Hellwig 	if (result < 0)
188757dacad5SJay Sternberg 		return result;
18889a0be7abSChristoph Hellwig 
1889f5fa90dcSChristoph Hellwig 	if (nr_io_queues == 0)
1890a5229050SKeith Busch 		return 0;
189157dacad5SJay Sternberg 
189288de4598SChristoph Hellwig 	if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) {
189357dacad5SJay Sternberg 		result = nvme_cmb_qdepth(dev, nr_io_queues,
189457dacad5SJay Sternberg 				sizeof(struct nvme_command));
189557dacad5SJay Sternberg 		if (result > 0)
189657dacad5SJay Sternberg 			dev->q_depth = result;
189757dacad5SJay Sternberg 		else
189857dacad5SJay Sternberg 			nvme_release_cmb(dev);
189957dacad5SJay Sternberg 	}
190057dacad5SJay Sternberg 
190157dacad5SJay Sternberg 	do {
190297f6ef64SXu Yu 		size = db_bar_size(dev, nr_io_queues);
190397f6ef64SXu Yu 		result = nvme_remap_bar(dev, size);
190497f6ef64SXu Yu 		if (!result)
190557dacad5SJay Sternberg 			break;
190657dacad5SJay Sternberg 		if (!--nr_io_queues)
190757dacad5SJay Sternberg 			return -ENOMEM;
190857dacad5SJay Sternberg 	} while (1);
190957dacad5SJay Sternberg 	adminq->q_db = dev->dbs;
191057dacad5SJay Sternberg 
191157dacad5SJay Sternberg 	/* Deregister the admin queue's interrupt */
19120ff199cbSChristoph Hellwig 	pci_free_irq(pdev, 0, adminq);
191357dacad5SJay Sternberg 
191457dacad5SJay Sternberg 	/*
191557dacad5SJay Sternberg 	 * If we enable msix early due to not intx, disable it again before
191657dacad5SJay Sternberg 	 * setting up the full range we need.
191757dacad5SJay Sternberg 	 */
1918dca51e78SChristoph Hellwig 	pci_free_irq_vectors(pdev);
191922b55601SKeith Busch 	result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1,
192022b55601SKeith Busch 			PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
192122b55601SKeith Busch 	if (result <= 0)
1922dca51e78SChristoph Hellwig 		return -EIO;
192322b55601SKeith Busch 	dev->num_vecs = result;
192422b55601SKeith Busch 	dev->max_qid = max(result - 1, 1);
192557dacad5SJay Sternberg 
192657dacad5SJay Sternberg 	/*
192757dacad5SJay Sternberg 	 * Should investigate if there's a performance win from allocating
192857dacad5SJay Sternberg 	 * more queues than interrupt vectors; it might allow the submission
192957dacad5SJay Sternberg 	 * path to scale better, even if the receive path is limited by the
193057dacad5SJay Sternberg 	 * number of interrupts.
193157dacad5SJay Sternberg 	 */
193257dacad5SJay Sternberg 
1933dca51e78SChristoph Hellwig 	result = queue_request_irq(adminq);
193457dacad5SJay Sternberg 	if (result) {
193557dacad5SJay Sternberg 		adminq->cq_vector = -1;
1936d4875622SKeith Busch 		return result;
193757dacad5SJay Sternberg 	}
1938749941f2SChristoph Hellwig 	return nvme_create_io_queues(dev);
193957dacad5SJay Sternberg }
194057dacad5SJay Sternberg 
19412a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error)
1942db3cbfffSKeith Busch {
1943db3cbfffSKeith Busch 	struct nvme_queue *nvmeq = req->end_io_data;
1944db3cbfffSKeith Busch 
1945db3cbfffSKeith Busch 	blk_mq_free_request(req);
1946db3cbfffSKeith Busch 	complete(&nvmeq->dev->ioq_wait);
1947db3cbfffSKeith Busch }
1948db3cbfffSKeith Busch 
19492a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error)
1950db3cbfffSKeith Busch {
1951db3cbfffSKeith Busch 	struct nvme_queue *nvmeq = req->end_io_data;
19525cb525c8SJens Axboe 	u16 start, end;
1953db3cbfffSKeith Busch 
1954db3cbfffSKeith Busch 	if (!error) {
1955db3cbfffSKeith Busch 		unsigned long flags;
1956db3cbfffSKeith Busch 
19570bc88192SKeith Busch 		spin_lock_irqsave(&nvmeq->cq_lock, flags);
19585cb525c8SJens Axboe 		nvme_process_cq(nvmeq, &start, &end, -1);
19591ab0cd69SJens Axboe 		spin_unlock_irqrestore(&nvmeq->cq_lock, flags);
19605cb525c8SJens Axboe 
19615cb525c8SJens Axboe 		nvme_complete_cqes(nvmeq, start, end);
1962db3cbfffSKeith Busch 	}
1963db3cbfffSKeith Busch 
1964db3cbfffSKeith Busch 	nvme_del_queue_end(req, error);
1965db3cbfffSKeith Busch }
1966db3cbfffSKeith Busch 
1967db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1968db3cbfffSKeith Busch {
1969db3cbfffSKeith Busch 	struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1970db3cbfffSKeith Busch 	struct request *req;
1971db3cbfffSKeith Busch 	struct nvme_command cmd;
1972db3cbfffSKeith Busch 
1973db3cbfffSKeith Busch 	memset(&cmd, 0, sizeof(cmd));
1974db3cbfffSKeith Busch 	cmd.delete_queue.opcode = opcode;
1975db3cbfffSKeith Busch 	cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1976db3cbfffSKeith Busch 
1977eb71f435SChristoph Hellwig 	req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1978db3cbfffSKeith Busch 	if (IS_ERR(req))
1979db3cbfffSKeith Busch 		return PTR_ERR(req);
1980db3cbfffSKeith Busch 
1981db3cbfffSKeith Busch 	req->timeout = ADMIN_TIMEOUT;
1982db3cbfffSKeith Busch 	req->end_io_data = nvmeq;
1983db3cbfffSKeith Busch 
1984db3cbfffSKeith Busch 	blk_execute_rq_nowait(q, NULL, req, false,
1985db3cbfffSKeith Busch 			opcode == nvme_admin_delete_cq ?
1986db3cbfffSKeith Busch 				nvme_del_cq_end : nvme_del_queue_end);
1987db3cbfffSKeith Busch 	return 0;
1988db3cbfffSKeith Busch }
1989db3cbfffSKeith Busch 
1990ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev)
1991db3cbfffSKeith Busch {
1992ee9aebb2SKeith Busch 	int pass, queues = dev->online_queues - 1;
1993db3cbfffSKeith Busch 	unsigned long timeout;
1994db3cbfffSKeith Busch 	u8 opcode = nvme_admin_delete_sq;
1995db3cbfffSKeith Busch 
1996db3cbfffSKeith Busch 	for (pass = 0; pass < 2; pass++) {
1997014a0d60SKeith Busch 		int sent = 0, i = queues;
1998db3cbfffSKeith Busch 
1999db3cbfffSKeith Busch 		reinit_completion(&dev->ioq_wait);
2000db3cbfffSKeith Busch  retry:
2001db3cbfffSKeith Busch 		timeout = ADMIN_TIMEOUT;
2002c21377f8SGabriel Krisman Bertazi 		for (; i > 0; i--, sent++)
2003147b27e4SSagi Grimberg 			if (nvme_delete_queue(&dev->queues[i], opcode))
2004db3cbfffSKeith Busch 				break;
2005c21377f8SGabriel Krisman Bertazi 
2006db3cbfffSKeith Busch 		while (sent--) {
2007db3cbfffSKeith Busch 			timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
2008db3cbfffSKeith Busch 			if (timeout == 0)
2009db3cbfffSKeith Busch 				return;
2010db3cbfffSKeith Busch 			if (i)
2011db3cbfffSKeith Busch 				goto retry;
2012db3cbfffSKeith Busch 		}
2013db3cbfffSKeith Busch 		opcode = nvme_admin_delete_cq;
2014db3cbfffSKeith Busch 	}
2015db3cbfffSKeith Busch }
2016db3cbfffSKeith Busch 
201757dacad5SJay Sternberg /*
20182b1b7e78SJianchao Wang  * return error value only when tagset allocation failed
201957dacad5SJay Sternberg  */
202057dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev)
202157dacad5SJay Sternberg {
20222b1b7e78SJianchao Wang 	int ret;
20232b1b7e78SJianchao Wang 
20245bae7f73SChristoph Hellwig 	if (!dev->ctrl.tagset) {
202557dacad5SJay Sternberg 		dev->tagset.ops = &nvme_mq_ops;
202657dacad5SJay Sternberg 		dev->tagset.nr_hw_queues = dev->online_queues - 1;
202757dacad5SJay Sternberg 		dev->tagset.timeout = NVME_IO_TIMEOUT;
202857dacad5SJay Sternberg 		dev->tagset.numa_node = dev_to_node(dev->dev);
202957dacad5SJay Sternberg 		dev->tagset.queue_depth =
203057dacad5SJay Sternberg 				min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
2031a7a7cbe3SChaitanya Kulkarni 		dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false);
2032a7a7cbe3SChaitanya Kulkarni 		if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) {
2033a7a7cbe3SChaitanya Kulkarni 			dev->tagset.cmd_size = max(dev->tagset.cmd_size,
2034a7a7cbe3SChaitanya Kulkarni 					nvme_pci_cmd_size(dev, true));
2035a7a7cbe3SChaitanya Kulkarni 		}
203657dacad5SJay Sternberg 		dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
203757dacad5SJay Sternberg 		dev->tagset.driver_data = dev;
203857dacad5SJay Sternberg 
20392b1b7e78SJianchao Wang 		ret = blk_mq_alloc_tag_set(&dev->tagset);
20402b1b7e78SJianchao Wang 		if (ret) {
20412b1b7e78SJianchao Wang 			dev_warn(dev->ctrl.device,
20422b1b7e78SJianchao Wang 				"IO queues tagset allocation failed %d\n", ret);
20432b1b7e78SJianchao Wang 			return ret;
20442b1b7e78SJianchao Wang 		}
20455bae7f73SChristoph Hellwig 		dev->ctrl.tagset = &dev->tagset;
2046f9f38e33SHelen Koike 
2047f9f38e33SHelen Koike 		nvme_dbbuf_set(dev);
2048949928c1SKeith Busch 	} else {
2049949928c1SKeith Busch 		blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2050949928c1SKeith Busch 
2051949928c1SKeith Busch 		/* Free previously allocated queues that are no longer usable */
2052949928c1SKeith Busch 		nvme_free_queues(dev, dev->online_queues);
205357dacad5SJay Sternberg 	}
2054949928c1SKeith Busch 
205557dacad5SJay Sternberg 	return 0;
205657dacad5SJay Sternberg }
205757dacad5SJay Sternberg 
2058b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev)
205957dacad5SJay Sternberg {
2060b00a726aSKeith Busch 	int result = -ENOMEM;
206157dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev->dev);
206257dacad5SJay Sternberg 
206357dacad5SJay Sternberg 	if (pci_enable_device_mem(pdev))
206457dacad5SJay Sternberg 		return result;
206557dacad5SJay Sternberg 
206657dacad5SJay Sternberg 	pci_set_master(pdev);
206757dacad5SJay Sternberg 
206857dacad5SJay Sternberg 	if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
206957dacad5SJay Sternberg 	    dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
207057dacad5SJay Sternberg 		goto disable;
207157dacad5SJay Sternberg 
20727a67cbeaSChristoph Hellwig 	if (readl(dev->bar + NVME_REG_CSTS) == -1) {
207357dacad5SJay Sternberg 		result = -ENODEV;
2074b00a726aSKeith Busch 		goto disable;
207557dacad5SJay Sternberg 	}
207657dacad5SJay Sternberg 
207757dacad5SJay Sternberg 	/*
2078a5229050SKeith Busch 	 * Some devices and/or platforms don't advertise or work with INTx
2079a5229050SKeith Busch 	 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2080a5229050SKeith Busch 	 * adjust this later.
208157dacad5SJay Sternberg 	 */
2082dca51e78SChristoph Hellwig 	result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2083dca51e78SChristoph Hellwig 	if (result < 0)
2084dca51e78SChristoph Hellwig 		return result;
208557dacad5SJay Sternberg 
208620d0dfe6SSagi Grimberg 	dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
20877a67cbeaSChristoph Hellwig 
208820d0dfe6SSagi Grimberg 	dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2089b27c1e68Sweiping zhang 				io_queue_depth);
209020d0dfe6SSagi Grimberg 	dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
20917a67cbeaSChristoph Hellwig 	dev->dbs = dev->bar + 4096;
20921f390c1fSStephan Günther 
20931f390c1fSStephan Günther 	/*
20941f390c1fSStephan Günther 	 * Temporary fix for the Apple controller found in the MacBook8,1 and
20951f390c1fSStephan Günther 	 * some MacBook7,1 to avoid controller resets and data loss.
20961f390c1fSStephan Günther 	 */
20971f390c1fSStephan Günther 	if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
20981f390c1fSStephan Günther 		dev->q_depth = 2;
20999bdcfb10SChristoph Hellwig 		dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
21009bdcfb10SChristoph Hellwig 			"set queue depth=%u to work around controller resets\n",
21011f390c1fSStephan Günther 			dev->q_depth);
2102d554b5e1SMartin K. Petersen 	} else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2103d554b5e1SMartin K. Petersen 		   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
210420d0dfe6SSagi Grimberg 		   NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2105d554b5e1SMartin K. Petersen 		dev->q_depth = 64;
2106d554b5e1SMartin K. Petersen 		dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2107d554b5e1SMartin K. Petersen                         "set queue depth=%u\n", dev->q_depth);
21081f390c1fSStephan Günther 	}
21091f390c1fSStephan Günther 
2110f65efd6dSChristoph Hellwig 	nvme_map_cmb(dev);
2111202021c1SStephen Bates 
2112a0a3408eSKeith Busch 	pci_enable_pcie_error_reporting(pdev);
2113a0a3408eSKeith Busch 	pci_save_state(pdev);
211457dacad5SJay Sternberg 	return 0;
211557dacad5SJay Sternberg 
211657dacad5SJay Sternberg  disable:
211757dacad5SJay Sternberg 	pci_disable_device(pdev);
211857dacad5SJay Sternberg 	return result;
211957dacad5SJay Sternberg }
212057dacad5SJay Sternberg 
212157dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev)
212257dacad5SJay Sternberg {
2123b00a726aSKeith Busch 	if (dev->bar)
2124b00a726aSKeith Busch 		iounmap(dev->bar);
2125a1f447b3SJohannes Thumshirn 	pci_release_mem_regions(to_pci_dev(dev->dev));
2126b00a726aSKeith Busch }
2127b00a726aSKeith Busch 
2128b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev)
2129b00a726aSKeith Busch {
213057dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev->dev);
213157dacad5SJay Sternberg 
2132f63572dfSJon Derrick 	nvme_release_cmb(dev);
2133dca51e78SChristoph Hellwig 	pci_free_irq_vectors(pdev);
213457dacad5SJay Sternberg 
2135a0a3408eSKeith Busch 	if (pci_is_enabled(pdev)) {
2136a0a3408eSKeith Busch 		pci_disable_pcie_error_reporting(pdev);
213757dacad5SJay Sternberg 		pci_disable_device(pdev);
213857dacad5SJay Sternberg 	}
2139a0a3408eSKeith Busch }
214057dacad5SJay Sternberg 
2141a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
214257dacad5SJay Sternberg {
2143ee9aebb2SKeith Busch 	int i;
2144302ad8ccSKeith Busch 	bool dead = true;
2145302ad8ccSKeith Busch 	struct pci_dev *pdev = to_pci_dev(dev->dev);
214657dacad5SJay Sternberg 
214777bf25eaSKeith Busch 	mutex_lock(&dev->shutdown_lock);
2148302ad8ccSKeith Busch 	if (pci_is_enabled(pdev)) {
2149302ad8ccSKeith Busch 		u32 csts = readl(dev->bar + NVME_REG_CSTS);
2150302ad8ccSKeith Busch 
2151ebef7368SKeith Busch 		if (dev->ctrl.state == NVME_CTRL_LIVE ||
2152ebef7368SKeith Busch 		    dev->ctrl.state == NVME_CTRL_RESETTING)
2153302ad8ccSKeith Busch 			nvme_start_freeze(&dev->ctrl);
2154302ad8ccSKeith Busch 		dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2155302ad8ccSKeith Busch 			pdev->error_state  != pci_channel_io_normal);
215657dacad5SJay Sternberg 	}
2157c21377f8SGabriel Krisman Bertazi 
2158302ad8ccSKeith Busch 	/*
2159302ad8ccSKeith Busch 	 * Give the controller a chance to complete all entered requests if
2160302ad8ccSKeith Busch 	 * doing a safe shutdown.
2161302ad8ccSKeith Busch 	 */
216287ad72a5SChristoph Hellwig 	if (!dead) {
216387ad72a5SChristoph Hellwig 		if (shutdown)
2164302ad8ccSKeith Busch 			nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
21659a915a5bSJianchao Wang 	}
216687ad72a5SChristoph Hellwig 
21679a915a5bSJianchao Wang 	nvme_stop_queues(&dev->ctrl);
21689a915a5bSJianchao Wang 
216964ee0ac0SKeith Busch 	if (!dead && dev->ctrl.queue_count > 0) {
2170ee9aebb2SKeith Busch 		nvme_disable_io_queues(dev);
2171a5cdb68cSKeith Busch 		nvme_disable_admin_queue(dev, shutdown);
217257dacad5SJay Sternberg 	}
2173ee9aebb2SKeith Busch 	for (i = dev->ctrl.queue_count - 1; i >= 0; i--)
2174ee9aebb2SKeith Busch 		nvme_suspend_queue(&dev->queues[i]);
2175ee9aebb2SKeith Busch 
2176b00a726aSKeith Busch 	nvme_pci_disable(dev);
217757dacad5SJay Sternberg 
2178e1958e65SMing Lin 	blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2179e1958e65SMing Lin 	blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2180302ad8ccSKeith Busch 
2181302ad8ccSKeith Busch 	/*
2182302ad8ccSKeith Busch 	 * The driver will not be starting up queues again if shutting down so
2183302ad8ccSKeith Busch 	 * must flush all entered requests to their failed completion to avoid
2184302ad8ccSKeith Busch 	 * deadlocking blk-mq hot-cpu notifier.
2185302ad8ccSKeith Busch 	 */
2186302ad8ccSKeith Busch 	if (shutdown)
2187302ad8ccSKeith Busch 		nvme_start_queues(&dev->ctrl);
218877bf25eaSKeith Busch 	mutex_unlock(&dev->shutdown_lock);
218957dacad5SJay Sternberg }
219057dacad5SJay Sternberg 
219157dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev)
219257dacad5SJay Sternberg {
219357dacad5SJay Sternberg 	dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
219457dacad5SJay Sternberg 						PAGE_SIZE, PAGE_SIZE, 0);
219557dacad5SJay Sternberg 	if (!dev->prp_page_pool)
219657dacad5SJay Sternberg 		return -ENOMEM;
219757dacad5SJay Sternberg 
219857dacad5SJay Sternberg 	/* Optimisation for I/Os between 4k and 128k */
219957dacad5SJay Sternberg 	dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
220057dacad5SJay Sternberg 						256, 256, 0);
220157dacad5SJay Sternberg 	if (!dev->prp_small_pool) {
220257dacad5SJay Sternberg 		dma_pool_destroy(dev->prp_page_pool);
220357dacad5SJay Sternberg 		return -ENOMEM;
220457dacad5SJay Sternberg 	}
220557dacad5SJay Sternberg 	return 0;
220657dacad5SJay Sternberg }
220757dacad5SJay Sternberg 
220857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev)
220957dacad5SJay Sternberg {
221057dacad5SJay Sternberg 	dma_pool_destroy(dev->prp_page_pool);
221157dacad5SJay Sternberg 	dma_pool_destroy(dev->prp_small_pool);
221257dacad5SJay Sternberg }
221357dacad5SJay Sternberg 
22141673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
221557dacad5SJay Sternberg {
22161673f1f0SChristoph Hellwig 	struct nvme_dev *dev = to_nvme_dev(ctrl);
221757dacad5SJay Sternberg 
2218f9f38e33SHelen Koike 	nvme_dbbuf_dma_free(dev);
221957dacad5SJay Sternberg 	put_device(dev->dev);
222057dacad5SJay Sternberg 	if (dev->tagset.tags)
222157dacad5SJay Sternberg 		blk_mq_free_tag_set(&dev->tagset);
22221c63dc66SChristoph Hellwig 	if (dev->ctrl.admin_q)
22231c63dc66SChristoph Hellwig 		blk_put_queue(dev->ctrl.admin_q);
222457dacad5SJay Sternberg 	kfree(dev->queues);
2225e286bcfcSScott Bauer 	free_opal_dev(dev->ctrl.opal_dev);
2226943e942eSJens Axboe 	mempool_destroy(dev->iod_mempool);
222757dacad5SJay Sternberg 	kfree(dev);
222857dacad5SJay Sternberg }
222957dacad5SJay Sternberg 
2230f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2231f58944e2SKeith Busch {
2232237045fcSLinus Torvalds 	dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2233f58944e2SKeith Busch 
2234d22524a4SChristoph Hellwig 	nvme_get_ctrl(&dev->ctrl);
223569d9a99cSKeith Busch 	nvme_dev_disable(dev, false);
22369f9cafc1SJianchao Wang 	nvme_kill_queues(&dev->ctrl);
223703e0f3a6SMing Lei 	if (!queue_work(nvme_wq, &dev->remove_work))
2238f58944e2SKeith Busch 		nvme_put_ctrl(&dev->ctrl);
2239f58944e2SKeith Busch }
2240f58944e2SKeith Busch 
2241fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work)
224257dacad5SJay Sternberg {
2243d86c4d8eSChristoph Hellwig 	struct nvme_dev *dev =
2244d86c4d8eSChristoph Hellwig 		container_of(work, struct nvme_dev, ctrl.reset_work);
2245a98e58e5SScott Bauer 	bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2246f58944e2SKeith Busch 	int result = -ENODEV;
22472b1b7e78SJianchao Wang 	enum nvme_ctrl_state new_state = NVME_CTRL_LIVE;
224857dacad5SJay Sternberg 
224982b057caSRakesh Pandit 	if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2250fd634f41SChristoph Hellwig 		goto out;
2251fd634f41SChristoph Hellwig 
2252fd634f41SChristoph Hellwig 	/*
2253fd634f41SChristoph Hellwig 	 * If we're called to reset a live controller first shut it down before
2254fd634f41SChristoph Hellwig 	 * moving on.
2255fd634f41SChristoph Hellwig 	 */
2256b00a726aSKeith Busch 	if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2257a5cdb68cSKeith Busch 		nvme_dev_disable(dev, false);
2258fd634f41SChristoph Hellwig 
2259ad70062cSJianchao Wang 	/*
2260ad6a0a52SMax Gurtovoy 	 * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2261ad70062cSJianchao Wang 	 * initializing procedure here.
2262ad70062cSJianchao Wang 	 */
2263ad6a0a52SMax Gurtovoy 	if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2264ad70062cSJianchao Wang 		dev_warn(dev->ctrl.device,
2265ad6a0a52SMax Gurtovoy 			"failed to mark controller CONNECTING\n");
2266ad70062cSJianchao Wang 		goto out;
2267ad70062cSJianchao Wang 	}
2268ad70062cSJianchao Wang 
2269b00a726aSKeith Busch 	result = nvme_pci_enable(dev);
227057dacad5SJay Sternberg 	if (result)
227157dacad5SJay Sternberg 		goto out;
227257dacad5SJay Sternberg 
227301ad0990SSagi Grimberg 	result = nvme_pci_configure_admin_queue(dev);
227457dacad5SJay Sternberg 	if (result)
2275f58944e2SKeith Busch 		goto out;
227657dacad5SJay Sternberg 
227757dacad5SJay Sternberg 	result = nvme_alloc_admin_tags(dev);
227857dacad5SJay Sternberg 	if (result)
2279f58944e2SKeith Busch 		goto out;
228057dacad5SJay Sternberg 
2281943e942eSJens Axboe 	/*
2282943e942eSJens Axboe 	 * Limit the max command size to prevent iod->sg allocations going
2283943e942eSJens Axboe 	 * over a single page.
2284943e942eSJens Axboe 	 */
2285943e942eSJens Axboe 	dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1;
2286943e942eSJens Axboe 	dev->ctrl.max_segments = NVME_MAX_SEGS;
2287943e942eSJens Axboe 
2288ce4541f4SChristoph Hellwig 	result = nvme_init_identify(&dev->ctrl);
2289ce4541f4SChristoph Hellwig 	if (result)
2290f58944e2SKeith Busch 		goto out;
2291ce4541f4SChristoph Hellwig 
2292e286bcfcSScott Bauer 	if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2293e286bcfcSScott Bauer 		if (!dev->ctrl.opal_dev)
22944f1244c8SChristoph Hellwig 			dev->ctrl.opal_dev =
22954f1244c8SChristoph Hellwig 				init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2296e286bcfcSScott Bauer 		else if (was_suspend)
22974f1244c8SChristoph Hellwig 			opal_unlock_from_suspend(dev->ctrl.opal_dev);
2298e286bcfcSScott Bauer 	} else {
2299e286bcfcSScott Bauer 		free_opal_dev(dev->ctrl.opal_dev);
2300e286bcfcSScott Bauer 		dev->ctrl.opal_dev = NULL;
2301e286bcfcSScott Bauer 	}
2302a98e58e5SScott Bauer 
2303f9f38e33SHelen Koike 	if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2304f9f38e33SHelen Koike 		result = nvme_dbbuf_dma_alloc(dev);
2305f9f38e33SHelen Koike 		if (result)
2306f9f38e33SHelen Koike 			dev_warn(dev->dev,
2307f9f38e33SHelen Koike 				 "unable to allocate dma for dbbuf\n");
2308f9f38e33SHelen Koike 	}
2309f9f38e33SHelen Koike 
23109620cfbaSChristoph Hellwig 	if (dev->ctrl.hmpre) {
23119620cfbaSChristoph Hellwig 		result = nvme_setup_host_mem(dev);
23129620cfbaSChristoph Hellwig 		if (result < 0)
23139620cfbaSChristoph Hellwig 			goto out;
23149620cfbaSChristoph Hellwig 	}
231587ad72a5SChristoph Hellwig 
231657dacad5SJay Sternberg 	result = nvme_setup_io_queues(dev);
231757dacad5SJay Sternberg 	if (result)
2318f58944e2SKeith Busch 		goto out;
231957dacad5SJay Sternberg 
232021f033f7SKeith Busch 	/*
232157dacad5SJay Sternberg 	 * Keep the controller around but remove all namespaces if we don't have
232257dacad5SJay Sternberg 	 * any working I/O queue.
232357dacad5SJay Sternberg 	 */
232457dacad5SJay Sternberg 	if (dev->online_queues < 2) {
23251b3c47c1SSagi Grimberg 		dev_warn(dev->ctrl.device, "IO queues not created\n");
23263b24774eSKeith Busch 		nvme_kill_queues(&dev->ctrl);
23275bae7f73SChristoph Hellwig 		nvme_remove_namespaces(&dev->ctrl);
23282b1b7e78SJianchao Wang 		new_state = NVME_CTRL_ADMIN_ONLY;
232957dacad5SJay Sternberg 	} else {
233025646264SKeith Busch 		nvme_start_queues(&dev->ctrl);
2331302ad8ccSKeith Busch 		nvme_wait_freeze(&dev->ctrl);
23322b1b7e78SJianchao Wang 		/* hit this only when allocate tagset fails */
23332b1b7e78SJianchao Wang 		if (nvme_dev_add(dev))
23342b1b7e78SJianchao Wang 			new_state = NVME_CTRL_ADMIN_ONLY;
2335302ad8ccSKeith Busch 		nvme_unfreeze(&dev->ctrl);
233657dacad5SJay Sternberg 	}
233757dacad5SJay Sternberg 
23382b1b7e78SJianchao Wang 	/*
23392b1b7e78SJianchao Wang 	 * If only admin queue live, keep it to do further investigation or
23402b1b7e78SJianchao Wang 	 * recovery.
23412b1b7e78SJianchao Wang 	 */
23422b1b7e78SJianchao Wang 	if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) {
23432b1b7e78SJianchao Wang 		dev_warn(dev->ctrl.device,
23442b1b7e78SJianchao Wang 			"failed to mark controller state %d\n", new_state);
2345bb8d261eSChristoph Hellwig 		goto out;
2346bb8d261eSChristoph Hellwig 	}
234792911a55SChristoph Hellwig 
2348d09f2b45SSagi Grimberg 	nvme_start_ctrl(&dev->ctrl);
234957dacad5SJay Sternberg 	return;
235057dacad5SJay Sternberg 
235157dacad5SJay Sternberg  out:
2352f58944e2SKeith Busch 	nvme_remove_dead_ctrl(dev, result);
235357dacad5SJay Sternberg }
235457dacad5SJay Sternberg 
23555c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work)
235657dacad5SJay Sternberg {
23575c8809e6SChristoph Hellwig 	struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
235857dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev->dev);
235957dacad5SJay Sternberg 
236057dacad5SJay Sternberg 	if (pci_get_drvdata(pdev))
2361921920abSKeith Busch 		device_release_driver(&pdev->dev);
23621673f1f0SChristoph Hellwig 	nvme_put_ctrl(&dev->ctrl);
236357dacad5SJay Sternberg }
236457dacad5SJay Sternberg 
23651c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
236657dacad5SJay Sternberg {
23671c63dc66SChristoph Hellwig 	*val = readl(to_nvme_dev(ctrl)->bar + off);
23681c63dc66SChristoph Hellwig 	return 0;
236957dacad5SJay Sternberg }
23701c63dc66SChristoph Hellwig 
23715fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
23725fd4ce1bSChristoph Hellwig {
23735fd4ce1bSChristoph Hellwig 	writel(val, to_nvme_dev(ctrl)->bar + off);
23745fd4ce1bSChristoph Hellwig 	return 0;
23755fd4ce1bSChristoph Hellwig }
23765fd4ce1bSChristoph Hellwig 
23777fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
23787fd8930fSChristoph Hellwig {
23797fd8930fSChristoph Hellwig 	*val = readq(to_nvme_dev(ctrl)->bar + off);
23807fd8930fSChristoph Hellwig 	return 0;
23817fd8930fSChristoph Hellwig }
23827fd8930fSChristoph Hellwig 
238397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
238497c12223SKeith Busch {
238597c12223SKeith Busch 	struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
238697c12223SKeith Busch 
238797c12223SKeith Busch 	return snprintf(buf, size, "%s", dev_name(&pdev->dev));
238897c12223SKeith Busch }
238997c12223SKeith Busch 
23901c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
23911a353d85SMing Lin 	.name			= "pcie",
2392e439bb12SSagi Grimberg 	.module			= THIS_MODULE,
2393c81bfba9SChristoph Hellwig 	.flags			= NVME_F_METADATA_SUPPORTED,
23941c63dc66SChristoph Hellwig 	.reg_read32		= nvme_pci_reg_read32,
23955fd4ce1bSChristoph Hellwig 	.reg_write32		= nvme_pci_reg_write32,
23967fd8930fSChristoph Hellwig 	.reg_read64		= nvme_pci_reg_read64,
23971673f1f0SChristoph Hellwig 	.free_ctrl		= nvme_pci_free_ctrl,
2398f866fc42SChristoph Hellwig 	.submit_async_event	= nvme_pci_submit_async_event,
239997c12223SKeith Busch 	.get_address		= nvme_pci_get_address,
24001c63dc66SChristoph Hellwig };
240157dacad5SJay Sternberg 
2402b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev)
2403b00a726aSKeith Busch {
2404b00a726aSKeith Busch 	struct pci_dev *pdev = to_pci_dev(dev->dev);
2405b00a726aSKeith Busch 
2406a1f447b3SJohannes Thumshirn 	if (pci_request_mem_regions(pdev, "nvme"))
2407b00a726aSKeith Busch 		return -ENODEV;
2408b00a726aSKeith Busch 
240997f6ef64SXu Yu 	if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2410b00a726aSKeith Busch 		goto release;
2411b00a726aSKeith Busch 
2412b00a726aSKeith Busch 	return 0;
2413b00a726aSKeith Busch   release:
2414a1f447b3SJohannes Thumshirn 	pci_release_mem_regions(pdev);
2415b00a726aSKeith Busch 	return -ENODEV;
2416b00a726aSKeith Busch }
2417b00a726aSKeith Busch 
24188427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2419ff5350a8SAndy Lutomirski {
2420ff5350a8SAndy Lutomirski 	if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2421ff5350a8SAndy Lutomirski 		/*
2422ff5350a8SAndy Lutomirski 		 * Several Samsung devices seem to drop off the PCIe bus
2423ff5350a8SAndy Lutomirski 		 * randomly when APST is on and uses the deepest sleep state.
2424ff5350a8SAndy Lutomirski 		 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2425ff5350a8SAndy Lutomirski 		 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2426ff5350a8SAndy Lutomirski 		 * 950 PRO 256GB", but it seems to be restricted to two Dell
2427ff5350a8SAndy Lutomirski 		 * laptops.
2428ff5350a8SAndy Lutomirski 		 */
2429ff5350a8SAndy Lutomirski 		if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2430ff5350a8SAndy Lutomirski 		    (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2431ff5350a8SAndy Lutomirski 		     dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2432ff5350a8SAndy Lutomirski 			return NVME_QUIRK_NO_DEEPEST_PS;
24338427bbc2SKai-Heng Feng 	} else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
24348427bbc2SKai-Heng Feng 		/*
24358427bbc2SKai-Heng Feng 		 * Samsung SSD 960 EVO drops off the PCIe bus after system
2436467c77d4SJarosław Janik 		 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2437467c77d4SJarosław Janik 		 * within few minutes after bootup on a Coffee Lake board -
2438467c77d4SJarosław Janik 		 * ASUS PRIME Z370-A
24398427bbc2SKai-Heng Feng 		 */
24408427bbc2SKai-Heng Feng 		if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2441467c77d4SJarosław Janik 		    (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2442467c77d4SJarosław Janik 		     dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
24438427bbc2SKai-Heng Feng 			return NVME_QUIRK_NO_APST;
2444ff5350a8SAndy Lutomirski 	}
2445ff5350a8SAndy Lutomirski 
2446ff5350a8SAndy Lutomirski 	return 0;
2447ff5350a8SAndy Lutomirski }
2448ff5350a8SAndy Lutomirski 
244918119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie)
245018119775SKeith Busch {
245118119775SKeith Busch 	struct nvme_dev *dev = data;
245280f513b5SKeith Busch 
245318119775SKeith Busch 	nvme_reset_ctrl_sync(&dev->ctrl);
245418119775SKeith Busch 	flush_work(&dev->ctrl.scan_work);
245580f513b5SKeith Busch 	nvme_put_ctrl(&dev->ctrl);
245618119775SKeith Busch }
245718119775SKeith Busch 
245857dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
245957dacad5SJay Sternberg {
246057dacad5SJay Sternberg 	int node, result = -ENOMEM;
246157dacad5SJay Sternberg 	struct nvme_dev *dev;
2462ff5350a8SAndy Lutomirski 	unsigned long quirks = id->driver_data;
2463943e942eSJens Axboe 	size_t alloc_size;
246457dacad5SJay Sternberg 
246557dacad5SJay Sternberg 	node = dev_to_node(&pdev->dev);
246657dacad5SJay Sternberg 	if (node == NUMA_NO_NODE)
24672fa84351SMasayoshi Mizuma 		set_dev_node(&pdev->dev, first_memory_node);
246857dacad5SJay Sternberg 
246957dacad5SJay Sternberg 	dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
247057dacad5SJay Sternberg 	if (!dev)
247157dacad5SJay Sternberg 		return -ENOMEM;
2472147b27e4SSagi Grimberg 
2473147b27e4SSagi Grimberg 	dev->queues = kcalloc_node(num_possible_cpus() + 1,
2474147b27e4SSagi Grimberg 			sizeof(struct nvme_queue), GFP_KERNEL, node);
247557dacad5SJay Sternberg 	if (!dev->queues)
247657dacad5SJay Sternberg 		goto free;
247757dacad5SJay Sternberg 
247857dacad5SJay Sternberg 	dev->dev = get_device(&pdev->dev);
247957dacad5SJay Sternberg 	pci_set_drvdata(pdev, dev);
248057dacad5SJay Sternberg 
2481b00a726aSKeith Busch 	result = nvme_dev_map(dev);
2482b00a726aSKeith Busch 	if (result)
2483b00c9b7aSChristophe JAILLET 		goto put_pci;
2484b00a726aSKeith Busch 
2485d86c4d8eSChristoph Hellwig 	INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
24865c8809e6SChristoph Hellwig 	INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
248777bf25eaSKeith Busch 	mutex_init(&dev->shutdown_lock);
2488db3cbfffSKeith Busch 	init_completion(&dev->ioq_wait);
2489f3ca80fcSChristoph Hellwig 
2490f3ca80fcSChristoph Hellwig 	result = nvme_setup_prp_pools(dev);
2491f3ca80fcSChristoph Hellwig 	if (result)
2492b00c9b7aSChristophe JAILLET 		goto unmap;
2493f3ca80fcSChristoph Hellwig 
24948427bbc2SKai-Heng Feng 	quirks |= check_vendor_combination_bug(pdev);
2495ff5350a8SAndy Lutomirski 
2496943e942eSJens Axboe 	/*
2497943e942eSJens Axboe 	 * Double check that our mempool alloc size will cover the biggest
2498943e942eSJens Axboe 	 * command we support.
2499943e942eSJens Axboe 	 */
2500943e942eSJens Axboe 	alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ,
2501943e942eSJens Axboe 						NVME_MAX_SEGS, true);
2502943e942eSJens Axboe 	WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2503943e942eSJens Axboe 
2504943e942eSJens Axboe 	dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2505943e942eSJens Axboe 						mempool_kfree,
2506943e942eSJens Axboe 						(void *) alloc_size,
2507943e942eSJens Axboe 						GFP_KERNEL, node);
2508943e942eSJens Axboe 	if (!dev->iod_mempool) {
2509943e942eSJens Axboe 		result = -ENOMEM;
2510943e942eSJens Axboe 		goto release_pools;
2511943e942eSJens Axboe 	}
2512943e942eSJens Axboe 
2513b6e44b4cSKeith Busch 	result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2514b6e44b4cSKeith Busch 			quirks);
2515b6e44b4cSKeith Busch 	if (result)
2516b6e44b4cSKeith Busch 		goto release_mempool;
2517b6e44b4cSKeith Busch 
25181b3c47c1SSagi Grimberg 	dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
25191b3c47c1SSagi Grimberg 
252080f513b5SKeith Busch 	nvme_get_ctrl(&dev->ctrl);
252118119775SKeith Busch 	async_schedule(nvme_async_probe, dev);
25224caff8fcSSagi Grimberg 
252357dacad5SJay Sternberg 	return 0;
252457dacad5SJay Sternberg 
2525b6e44b4cSKeith Busch  release_mempool:
2526b6e44b4cSKeith Busch 	mempool_destroy(dev->iod_mempool);
252757dacad5SJay Sternberg  release_pools:
252857dacad5SJay Sternberg 	nvme_release_prp_pools(dev);
2529b00c9b7aSChristophe JAILLET  unmap:
2530b00c9b7aSChristophe JAILLET 	nvme_dev_unmap(dev);
253157dacad5SJay Sternberg  put_pci:
253257dacad5SJay Sternberg 	put_device(dev->dev);
253357dacad5SJay Sternberg  free:
253457dacad5SJay Sternberg 	kfree(dev->queues);
253557dacad5SJay Sternberg 	kfree(dev);
253657dacad5SJay Sternberg 	return result;
253757dacad5SJay Sternberg }
253857dacad5SJay Sternberg 
2539775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev)
254057dacad5SJay Sternberg {
254157dacad5SJay Sternberg 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2542a5cdb68cSKeith Busch 	nvme_dev_disable(dev, false);
2543775755edSChristoph Hellwig }
254457dacad5SJay Sternberg 
2545775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev)
2546775755edSChristoph Hellwig {
2547f263fbb8SLinus Torvalds 	struct nvme_dev *dev = pci_get_drvdata(pdev);
254879c48ccfSSagi Grimberg 	nvme_reset_ctrl_sync(&dev->ctrl);
254957dacad5SJay Sternberg }
255057dacad5SJay Sternberg 
255157dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev)
255257dacad5SJay Sternberg {
255357dacad5SJay Sternberg 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2554a5cdb68cSKeith Busch 	nvme_dev_disable(dev, true);
255557dacad5SJay Sternberg }
255657dacad5SJay Sternberg 
2557f58944e2SKeith Busch /*
2558f58944e2SKeith Busch  * The driver's remove may be called on a device in a partially initialized
2559f58944e2SKeith Busch  * state. This function must not have any dependencies on the device state in
2560f58944e2SKeith Busch  * order to proceed.
2561f58944e2SKeith Busch  */
256257dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev)
256357dacad5SJay Sternberg {
256457dacad5SJay Sternberg 	struct nvme_dev *dev = pci_get_drvdata(pdev);
256557dacad5SJay Sternberg 
2566bb8d261eSChristoph Hellwig 	nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2567bb8d261eSChristoph Hellwig 
2568d86c4d8eSChristoph Hellwig 	cancel_work_sync(&dev->ctrl.reset_work);
256957dacad5SJay Sternberg 	pci_set_drvdata(pdev, NULL);
25700ff9d4e1SKeith Busch 
25716db28edaSKeith Busch 	if (!pci_device_is_present(pdev)) {
25720ff9d4e1SKeith Busch 		nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
25731d39e692SKeith Busch 		nvme_dev_disable(dev, true);
25746db28edaSKeith Busch 	}
25750ff9d4e1SKeith Busch 
2576d86c4d8eSChristoph Hellwig 	flush_work(&dev->ctrl.reset_work);
2577d09f2b45SSagi Grimberg 	nvme_stop_ctrl(&dev->ctrl);
2578d09f2b45SSagi Grimberg 	nvme_remove_namespaces(&dev->ctrl);
2579a5cdb68cSKeith Busch 	nvme_dev_disable(dev, true);
258087ad72a5SChristoph Hellwig 	nvme_free_host_mem(dev);
258157dacad5SJay Sternberg 	nvme_dev_remove_admin(dev);
258257dacad5SJay Sternberg 	nvme_free_queues(dev, 0);
2583d09f2b45SSagi Grimberg 	nvme_uninit_ctrl(&dev->ctrl);
258457dacad5SJay Sternberg 	nvme_release_prp_pools(dev);
2585b00a726aSKeith Busch 	nvme_dev_unmap(dev);
25861673f1f0SChristoph Hellwig 	nvme_put_ctrl(&dev->ctrl);
258757dacad5SJay Sternberg }
258857dacad5SJay Sternberg 
258957dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP
259057dacad5SJay Sternberg static int nvme_suspend(struct device *dev)
259157dacad5SJay Sternberg {
259257dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev);
259357dacad5SJay Sternberg 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
259457dacad5SJay Sternberg 
2595a5cdb68cSKeith Busch 	nvme_dev_disable(ndev, true);
259657dacad5SJay Sternberg 	return 0;
259757dacad5SJay Sternberg }
259857dacad5SJay Sternberg 
259957dacad5SJay Sternberg static int nvme_resume(struct device *dev)
260057dacad5SJay Sternberg {
260157dacad5SJay Sternberg 	struct pci_dev *pdev = to_pci_dev(dev);
260257dacad5SJay Sternberg 	struct nvme_dev *ndev = pci_get_drvdata(pdev);
260357dacad5SJay Sternberg 
2604d86c4d8eSChristoph Hellwig 	nvme_reset_ctrl(&ndev->ctrl);
260557dacad5SJay Sternberg 	return 0;
260657dacad5SJay Sternberg }
260757dacad5SJay Sternberg #endif
260857dacad5SJay Sternberg 
260957dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
261057dacad5SJay Sternberg 
2611a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2612a0a3408eSKeith Busch 						pci_channel_state_t state)
2613a0a3408eSKeith Busch {
2614a0a3408eSKeith Busch 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2615a0a3408eSKeith Busch 
2616a0a3408eSKeith Busch 	/*
2617a0a3408eSKeith Busch 	 * A frozen channel requires a reset. When detected, this method will
2618a0a3408eSKeith Busch 	 * shutdown the controller to quiesce. The controller will be restarted
2619a0a3408eSKeith Busch 	 * after the slot reset through driver's slot_reset callback.
2620a0a3408eSKeith Busch 	 */
2621a0a3408eSKeith Busch 	switch (state) {
2622a0a3408eSKeith Busch 	case pci_channel_io_normal:
2623a0a3408eSKeith Busch 		return PCI_ERS_RESULT_CAN_RECOVER;
2624a0a3408eSKeith Busch 	case pci_channel_io_frozen:
2625d011fb31SKeith Busch 		dev_warn(dev->ctrl.device,
2626d011fb31SKeith Busch 			"frozen state error detected, reset controller\n");
2627a5cdb68cSKeith Busch 		nvme_dev_disable(dev, false);
2628a0a3408eSKeith Busch 		return PCI_ERS_RESULT_NEED_RESET;
2629a0a3408eSKeith Busch 	case pci_channel_io_perm_failure:
2630d011fb31SKeith Busch 		dev_warn(dev->ctrl.device,
2631d011fb31SKeith Busch 			"failure state error detected, request disconnect\n");
2632a0a3408eSKeith Busch 		return PCI_ERS_RESULT_DISCONNECT;
2633a0a3408eSKeith Busch 	}
2634a0a3408eSKeith Busch 	return PCI_ERS_RESULT_NEED_RESET;
2635a0a3408eSKeith Busch }
2636a0a3408eSKeith Busch 
2637a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2638a0a3408eSKeith Busch {
2639a0a3408eSKeith Busch 	struct nvme_dev *dev = pci_get_drvdata(pdev);
2640a0a3408eSKeith Busch 
26411b3c47c1SSagi Grimberg 	dev_info(dev->ctrl.device, "restart after slot reset\n");
2642a0a3408eSKeith Busch 	pci_restore_state(pdev);
2643d86c4d8eSChristoph Hellwig 	nvme_reset_ctrl(&dev->ctrl);
2644a0a3408eSKeith Busch 	return PCI_ERS_RESULT_RECOVERED;
2645a0a3408eSKeith Busch }
2646a0a3408eSKeith Busch 
2647a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev)
2648a0a3408eSKeith Busch {
264972cd4cc2SKeith Busch 	struct nvme_dev *dev = pci_get_drvdata(pdev);
265072cd4cc2SKeith Busch 
265172cd4cc2SKeith Busch 	flush_work(&dev->ctrl.reset_work);
2652a0a3408eSKeith Busch 	pci_cleanup_aer_uncorrect_error_status(pdev);
2653a0a3408eSKeith Busch }
2654a0a3408eSKeith Busch 
265557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = {
265657dacad5SJay Sternberg 	.error_detected	= nvme_error_detected,
265757dacad5SJay Sternberg 	.slot_reset	= nvme_slot_reset,
265857dacad5SJay Sternberg 	.resume		= nvme_error_resume,
2659775755edSChristoph Hellwig 	.reset_prepare	= nvme_reset_prepare,
2660775755edSChristoph Hellwig 	.reset_done	= nvme_reset_done,
266157dacad5SJay Sternberg };
266257dacad5SJay Sternberg 
266357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = {
2664106198edSChristoph Hellwig 	{ PCI_VDEVICE(INTEL, 0x0953),
266508095e70SKeith Busch 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2666e850fd16SChristoph Hellwig 				NVME_QUIRK_DEALLOCATE_ZEROES, },
266799466e70SKeith Busch 	{ PCI_VDEVICE(INTEL, 0x0a53),
266899466e70SKeith Busch 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2669e850fd16SChristoph Hellwig 				NVME_QUIRK_DEALLOCATE_ZEROES, },
267099466e70SKeith Busch 	{ PCI_VDEVICE(INTEL, 0x0a54),
267199466e70SKeith Busch 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2672e850fd16SChristoph Hellwig 				NVME_QUIRK_DEALLOCATE_ZEROES, },
2673f99cb7afSDavid Wayne Fugate 	{ PCI_VDEVICE(INTEL, 0x0a55),
2674f99cb7afSDavid Wayne Fugate 		.driver_data = NVME_QUIRK_STRIPE_SIZE |
2675f99cb7afSDavid Wayne Fugate 				NVME_QUIRK_DEALLOCATE_ZEROES, },
267650af47d0SAndy Lutomirski 	{ PCI_VDEVICE(INTEL, 0xf1a5),	/* Intel 600P/P3100 */
26779abd68efSJens Axboe 		.driver_data = NVME_QUIRK_NO_DEEPEST_PS |
26789abd68efSJens Axboe 				NVME_QUIRK_MEDIUM_PRIO_SQ },
2679540c801cSKeith Busch 	{ PCI_VDEVICE(INTEL, 0x5845),	/* Qemu emulated controller */
2680540c801cSKeith Busch 		.driver_data = NVME_QUIRK_IDENTIFY_CNS, },
26810302ae60SMicah Parrish 	{ PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
26820302ae60SMicah Parrish 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
268354adc010SGuilherme G. Piccoli 	{ PCI_DEVICE(0x1c58, 0x0003),	/* HGST adapter */
268454adc010SGuilherme G. Piccoli 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
26858c97eeccSJeff Lien 	{ PCI_DEVICE(0x1c58, 0x0023),	/* WDC SN200 adapter */
26868c97eeccSJeff Lien 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2687015282c9SWenbo Wang 	{ PCI_DEVICE(0x1c5f, 0x0540),	/* Memblaze Pblaze4 adapter */
2688015282c9SWenbo Wang 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2689d554b5e1SMartin K. Petersen 	{ PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
2690d554b5e1SMartin K. Petersen 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2691d554b5e1SMartin K. Petersen 	{ PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
2692d554b5e1SMartin K. Petersen 		.driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2693608cc4b1SChristoph Hellwig 	{ PCI_DEVICE(0x1d1d, 0x1f1f),	/* LighNVM qemu device */
2694608cc4b1SChristoph Hellwig 		.driver_data = NVME_QUIRK_LIGHTNVM, },
2695608cc4b1SChristoph Hellwig 	{ PCI_DEVICE(0x1d1d, 0x2807),	/* CNEX WL */
2696608cc4b1SChristoph Hellwig 		.driver_data = NVME_QUIRK_LIGHTNVM, },
2697ea48e877SWei Xu 	{ PCI_DEVICE(0x1d1d, 0x2601),	/* CNEX Granby */
2698ea48e877SWei Xu 		.driver_data = NVME_QUIRK_LIGHTNVM, },
269957dacad5SJay Sternberg 	{ PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2700c74dc780SStephan Günther 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2701124298bdSDaniel Roschka 	{ PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
270257dacad5SJay Sternberg 	{ 0, }
270357dacad5SJay Sternberg };
270457dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table);
270557dacad5SJay Sternberg 
270657dacad5SJay Sternberg static struct pci_driver nvme_driver = {
270757dacad5SJay Sternberg 	.name		= "nvme",
270857dacad5SJay Sternberg 	.id_table	= nvme_id_table,
270957dacad5SJay Sternberg 	.probe		= nvme_probe,
271057dacad5SJay Sternberg 	.remove		= nvme_remove,
271157dacad5SJay Sternberg 	.shutdown	= nvme_shutdown,
271257dacad5SJay Sternberg 	.driver		= {
271357dacad5SJay Sternberg 		.pm	= &nvme_dev_pm_ops,
271457dacad5SJay Sternberg 	},
271574d986abSAlexander Duyck 	.sriov_configure = pci_sriov_configure_simple,
271657dacad5SJay Sternberg 	.err_handler	= &nvme_err_handler,
271757dacad5SJay Sternberg };
271857dacad5SJay Sternberg 
271957dacad5SJay Sternberg static int __init nvme_init(void)
272057dacad5SJay Sternberg {
27219a6327d2SSagi Grimberg 	return pci_register_driver(&nvme_driver);
272257dacad5SJay Sternberg }
272357dacad5SJay Sternberg 
272457dacad5SJay Sternberg static void __exit nvme_exit(void)
272557dacad5SJay Sternberg {
272657dacad5SJay Sternberg 	pci_unregister_driver(&nvme_driver);
272703e0f3a6SMing Lei 	flush_workqueue(nvme_wq);
272857dacad5SJay Sternberg 	_nvme_check_size();
272957dacad5SJay Sternberg }
273057dacad5SJay Sternberg 
273157dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
273257dacad5SJay Sternberg MODULE_LICENSE("GPL");
273357dacad5SJay Sternberg MODULE_VERSION("1.0");
273457dacad5SJay Sternberg module_init(nvme_init);
273557dacad5SJay Sternberg module_exit(nvme_exit);
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