15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 21d916b1beSKeith Busch #include <linux/suspend.h> 2257dacad5SJay Sternberg #include <linux/t10-pi.h> 2357dacad5SJay Sternberg #include <linux/types.h> 249cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 25a98e58e5SScott Bauer #include <linux/sed-opal.h> 260f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2757dacad5SJay Sternberg 28604c01d5Syupeng #include "trace.h" 2957dacad5SJay Sternberg #include "nvme.h" 3057dacad5SJay Sternberg 31c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 328a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3357dacad5SJay Sternberg 34a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35adf68f21SChristoph Hellwig 36943e942eSJens Axboe /* 37943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 38943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 39943e942eSJens Axboe */ 40943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 41943e942eSJens Axboe #define NVME_MAX_SEGS 127 42943e942eSJens Axboe 4357dacad5SJay Sternberg static int use_threaded_interrupts; 4457dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4557dacad5SJay Sternberg 4657dacad5SJay Sternberg static bool use_cmb_sqes = true; 4769f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4857dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4957dacad5SJay Sternberg 5087ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5187ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5287ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5387ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5457dacad5SJay Sternberg 55a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 56a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 57a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 58a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 59a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 60a7a7cbe3SChaitanya Kulkarni 61b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 63b27c1e68Sweiping zhang .set = io_queue_depth_set, 64b27c1e68Sweiping zhang .get = param_get_int, 65b27c1e68Sweiping zhang }; 66b27c1e68Sweiping zhang 67b27c1e68Sweiping zhang static int io_queue_depth = 1024; 68b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70b27c1e68Sweiping zhang 713b6592f7SJens Axboe static int write_queues; 72483178f3SMinwoo Im module_param(write_queues, int, 0644); 733b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 743b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 753b6592f7SJens Axboe "will share a queue set."); 763b6592f7SJens Axboe 77a232ea0eSMinwoo Im static int poll_queues; 78483178f3SMinwoo Im module_param(poll_queues, int, 0644); 794b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 804b04cc6aSJens Axboe 811c63dc66SChristoph Hellwig struct nvme_dev; 821c63dc66SChristoph Hellwig struct nvme_queue; 8357dacad5SJay Sternberg 84a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 858fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 8657dacad5SJay Sternberg 8757dacad5SJay Sternberg /* 881c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 891c63dc66SChristoph Hellwig */ 901c63dc66SChristoph Hellwig struct nvme_dev { 91147b27e4SSagi Grimberg struct nvme_queue *queues; 921c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 931c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 941c63dc66SChristoph Hellwig u32 __iomem *dbs; 951c63dc66SChristoph Hellwig struct device *dev; 961c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 971c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 981c63dc66SChristoph Hellwig unsigned online_queues; 991c63dc66SChristoph Hellwig unsigned max_qid; 100e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10122b55601SKeith Busch unsigned int num_vecs; 1021c63dc66SChristoph Hellwig int q_depth; 103c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1041c63dc66SChristoph Hellwig u32 db_stride; 1051c63dc66SChristoph Hellwig void __iomem *bar; 10697f6ef64SXu Yu unsigned long bar_mapped_size; 1075c8809e6SChristoph Hellwig struct work_struct remove_work; 10877bf25eaSKeith Busch struct mutex shutdown_lock; 1091c63dc66SChristoph Hellwig bool subsystem; 1101c63dc66SChristoph Hellwig u64 cmb_size; 1110f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1121c63dc66SChristoph Hellwig u32 cmbsz; 113202021c1SStephen Bates u32 cmbloc; 1141c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 115d916b1beSKeith Busch u32 last_ps; 11687ad72a5SChristoph Hellwig 117943e942eSJens Axboe mempool_t *iod_mempool; 118943e942eSJens Axboe 11987ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 120f9f38e33SHelen Koike u32 *dbbuf_dbs; 121f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 122f9f38e33SHelen Koike u32 *dbbuf_eis; 123f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12487ad72a5SChristoph Hellwig 12587ad72a5SChristoph Hellwig /* host memory buffer support: */ 12687ad72a5SChristoph Hellwig u64 host_mem_size; 12787ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1284033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13087ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13157dacad5SJay Sternberg }; 13257dacad5SJay Sternberg 133b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134b27c1e68Sweiping zhang { 135b27c1e68Sweiping zhang int n = 0, ret; 136b27c1e68Sweiping zhang 137b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 138b27c1e68Sweiping zhang if (ret != 0 || n < 2) 139b27c1e68Sweiping zhang return -EINVAL; 140b27c1e68Sweiping zhang 141b27c1e68Sweiping zhang return param_set_int(val, kp); 142b27c1e68Sweiping zhang } 143b27c1e68Sweiping zhang 144f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145f9f38e33SHelen Koike { 146f9f38e33SHelen Koike return qid * 2 * stride; 147f9f38e33SHelen Koike } 148f9f38e33SHelen Koike 149f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150f9f38e33SHelen Koike { 151f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 152f9f38e33SHelen Koike } 153f9f38e33SHelen Koike 1541c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1551c63dc66SChristoph Hellwig { 1561c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1571c63dc66SChristoph Hellwig } 1581c63dc66SChristoph Hellwig 15957dacad5SJay Sternberg /* 16057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 16157dacad5SJay Sternberg * commands and one for I/O commands). 16257dacad5SJay Sternberg */ 16357dacad5SJay Sternberg struct nvme_queue { 16457dacad5SJay Sternberg struct nvme_dev *dev; 1651ab0cd69SJens Axboe spinlock_t sq_lock; 166c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1673a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1683a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 16957dacad5SJay Sternberg volatile struct nvme_completion *cqes; 17057dacad5SJay Sternberg struct blk_mq_tags **tags; 17157dacad5SJay Sternberg dma_addr_t sq_dma_addr; 17257dacad5SJay Sternberg dma_addr_t cq_dma_addr; 17357dacad5SJay Sternberg u32 __iomem *q_db; 17457dacad5SJay Sternberg u16 q_depth; 1757c349ddeSKeith Busch u16 cq_vector; 17657dacad5SJay Sternberg u16 sq_tail; 17704f3eafdSJens Axboe u16 last_sq_tail; 17857dacad5SJay Sternberg u16 cq_head; 17968fa9dbeSJens Axboe u16 last_cq_head; 18057dacad5SJay Sternberg u16 qid; 18157dacad5SJay Sternberg u8 cq_phase; 182c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 1834e224106SChristoph Hellwig unsigned long flags; 1844e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 18563223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 186d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 1877c349ddeSKeith Busch #define NVMEQ_POLLED 3 188f9f38e33SHelen Koike u32 *dbbuf_sq_db; 189f9f38e33SHelen Koike u32 *dbbuf_cq_db; 190f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 191f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 192d1ed6aa1SChristoph Hellwig struct completion delete_done; 19357dacad5SJay Sternberg }; 19457dacad5SJay Sternberg 19557dacad5SJay Sternberg /* 1969b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 1979b048119SChristoph Hellwig * 1989b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 1999b048119SChristoph Hellwig * to the actual struct scatterlist. 20071bd150cSChristoph Hellwig */ 20171bd150cSChristoph Hellwig struct nvme_iod { 202d49187e9SChristoph Hellwig struct nvme_request req; 203f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 204a7a7cbe3SChaitanya Kulkarni bool use_sgl; 205f4800d6dSChristoph Hellwig int aborted; 20671bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 20771bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 20871bd150cSChristoph Hellwig dma_addr_t first_dma; 209dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 210783b94bdSChristoph Hellwig dma_addr_t meta_dma; 211f4800d6dSChristoph Hellwig struct scatterlist *sg; 21257dacad5SJay Sternberg }; 21357dacad5SJay Sternberg 2143b6592f7SJens Axboe static unsigned int max_io_queues(void) 2153b6592f7SJens Axboe { 2164b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2173b6592f7SJens Axboe } 2183b6592f7SJens Axboe 2193b6592f7SJens Axboe static unsigned int max_queue_count(void) 2203b6592f7SJens Axboe { 2213b6592f7SJens Axboe /* IO queues + admin queue */ 2223b6592f7SJens Axboe return 1 + max_io_queues(); 2233b6592f7SJens Axboe } 2243b6592f7SJens Axboe 225f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 226f9f38e33SHelen Koike { 2273b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 228f9f38e33SHelen Koike } 229f9f38e33SHelen Koike 230f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 231f9f38e33SHelen Koike { 232f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 233f9f38e33SHelen Koike 234f9f38e33SHelen Koike if (dev->dbbuf_dbs) 235f9f38e33SHelen Koike return 0; 236f9f38e33SHelen Koike 237f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 238f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 239f9f38e33SHelen Koike GFP_KERNEL); 240f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 241f9f38e33SHelen Koike return -ENOMEM; 242f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 243f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 244f9f38e33SHelen Koike GFP_KERNEL); 245f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 246f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 247f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 248f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 249f9f38e33SHelen Koike return -ENOMEM; 250f9f38e33SHelen Koike } 251f9f38e33SHelen Koike 252f9f38e33SHelen Koike return 0; 253f9f38e33SHelen Koike } 254f9f38e33SHelen Koike 255f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 256f9f38e33SHelen Koike { 257f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 258f9f38e33SHelen Koike 259f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 260f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 261f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 262f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike if (dev->dbbuf_eis) { 265f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 266f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 267f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 268f9f38e33SHelen Koike } 269f9f38e33SHelen Koike } 270f9f38e33SHelen Koike 271f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 272f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 273f9f38e33SHelen Koike { 274f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 275f9f38e33SHelen Koike return; 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 278f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 279f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 280f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 281f9f38e33SHelen Koike } 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 284f9f38e33SHelen Koike { 285f9f38e33SHelen Koike struct nvme_command c; 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 288f9f38e33SHelen Koike return; 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 291f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 292f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 293f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2969bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 297f9f38e33SHelen Koike /* Free memory and continue on */ 298f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 299f9f38e33SHelen Koike } 300f9f38e33SHelen Koike } 301f9f38e33SHelen Koike 302f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 303f9f38e33SHelen Koike { 304f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 305f9f38e33SHelen Koike } 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 308f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 309f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 310f9f38e33SHelen Koike { 311f9f38e33SHelen Koike if (dbbuf_db) { 312f9f38e33SHelen Koike u16 old_value; 313f9f38e33SHelen Koike 314f9f38e33SHelen Koike /* 315f9f38e33SHelen Koike * Ensure that the queue is written before updating 316f9f38e33SHelen Koike * the doorbell in memory 317f9f38e33SHelen Koike */ 318f9f38e33SHelen Koike wmb(); 319f9f38e33SHelen Koike 320f9f38e33SHelen Koike old_value = *dbbuf_db; 321f9f38e33SHelen Koike *dbbuf_db = value; 322f9f38e33SHelen Koike 323f1ed3df2SMichal Wnukowski /* 324f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 325f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 326f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 327f1ed3df2SMichal Wnukowski * the doorbell. 328f1ed3df2SMichal Wnukowski */ 329f1ed3df2SMichal Wnukowski mb(); 330f1ed3df2SMichal Wnukowski 331f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 332f9f38e33SHelen Koike return false; 333f9f38e33SHelen Koike } 334f9f38e33SHelen Koike 335f9f38e33SHelen Koike return true; 33657dacad5SJay Sternberg } 33757dacad5SJay Sternberg 33857dacad5SJay Sternberg /* 33957dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 34057dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 34157dacad5SJay Sternberg * the I/O. 34257dacad5SJay Sternberg */ 34357dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 34457dacad5SJay Sternberg { 3455fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3465fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34757dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 34857dacad5SJay Sternberg } 34957dacad5SJay Sternberg 350a7a7cbe3SChaitanya Kulkarni /* 351a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 352a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 353a7a7cbe3SChaitanya Kulkarni */ 354a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 355f4800d6dSChristoph Hellwig { 356a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 357f4800d6dSChristoph Hellwig } 358f4800d6dSChristoph Hellwig 359a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 360a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 36157dacad5SJay Sternberg { 362a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 363a7a7cbe3SChaitanya Kulkarni 364a7a7cbe3SChaitanya Kulkarni if (use_sgl) 365a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 366a7a7cbe3SChaitanya Kulkarni else 367a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 368a7a7cbe3SChaitanya Kulkarni 369a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 370a7a7cbe3SChaitanya Kulkarni } 371a7a7cbe3SChaitanya Kulkarni 37257dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37357dacad5SJay Sternberg unsigned int hctx_idx) 37457dacad5SJay Sternberg { 37557dacad5SJay Sternberg struct nvme_dev *dev = data; 376147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37757dacad5SJay Sternberg 37857dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37957dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 38057dacad5SJay Sternberg WARN_ON(nvmeq->tags); 38157dacad5SJay Sternberg 38257dacad5SJay Sternberg hctx->driver_data = nvmeq; 38357dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 38457dacad5SJay Sternberg return 0; 38557dacad5SJay Sternberg } 38657dacad5SJay Sternberg 38757dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38857dacad5SJay Sternberg { 38957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 39057dacad5SJay Sternberg 39157dacad5SJay Sternberg nvmeq->tags = NULL; 39257dacad5SJay Sternberg } 39357dacad5SJay Sternberg 39457dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39557dacad5SJay Sternberg unsigned int hctx_idx) 39657dacad5SJay Sternberg { 39757dacad5SJay Sternberg struct nvme_dev *dev = data; 398147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39957dacad5SJay Sternberg 40057dacad5SJay Sternberg if (!nvmeq->tags) 40157dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 40257dacad5SJay Sternberg 40357dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 40457dacad5SJay Sternberg hctx->driver_data = nvmeq; 40557dacad5SJay Sternberg return 0; 40657dacad5SJay Sternberg } 40757dacad5SJay Sternberg 408d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 409d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 41057dacad5SJay Sternberg { 411d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 412f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4130350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 414147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 41557dacad5SJay Sternberg 41657dacad5SJay Sternberg BUG_ON(!nvmeq); 417f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41859e29ce6SSagi Grimberg 41959e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 42057dacad5SJay Sternberg return 0; 42157dacad5SJay Sternberg } 42257dacad5SJay Sternberg 4233b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4243b6592f7SJens Axboe { 4253b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4263b6592f7SJens Axboe if (dev->num_vecs > 1) 4273b6592f7SJens Axboe return 1; 4283b6592f7SJens Axboe 4293b6592f7SJens Axboe return 0; 4303b6592f7SJens Axboe } 4313b6592f7SJens Axboe 432dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 433dca51e78SChristoph Hellwig { 434dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4353b6592f7SJens Axboe int i, qoff, offset; 436dca51e78SChristoph Hellwig 4373b6592f7SJens Axboe offset = queue_irq_offset(dev); 4383b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4393b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4403b6592f7SJens Axboe 4413b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4423b6592f7SJens Axboe if (!map->nr_queues) { 443e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4447e849dd9SChristoph Hellwig continue; 4453b6592f7SJens Axboe } 4463b6592f7SJens Axboe 4474b04cc6aSJens Axboe /* 4484b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4494b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4504b04cc6aSJens Axboe */ 4513b6592f7SJens Axboe map->queue_offset = qoff; 452cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4533b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4544b04cc6aSJens Axboe else 4554b04cc6aSJens Axboe blk_mq_map_queues(map); 4563b6592f7SJens Axboe qoff += map->nr_queues; 4573b6592f7SJens Axboe offset += map->nr_queues; 4583b6592f7SJens Axboe } 4593b6592f7SJens Axboe 4603b6592f7SJens Axboe return 0; 461dca51e78SChristoph Hellwig } 462dca51e78SChristoph Hellwig 46304f3eafdSJens Axboe /* 46404f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 46504f3eafdSJens Axboe */ 46604f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 46704f3eafdSJens Axboe { 46804f3eafdSJens Axboe if (!write_sq) { 46904f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 47004f3eafdSJens Axboe 47104f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 47204f3eafdSJens Axboe next_tail = 0; 47304f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 47404f3eafdSJens Axboe return; 47504f3eafdSJens Axboe } 47604f3eafdSJens Axboe 47704f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 47804f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 47904f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48004f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 48104f3eafdSJens Axboe } 48204f3eafdSJens Axboe 48357dacad5SJay Sternberg /** 48490ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 48557dacad5SJay Sternberg * @nvmeq: The queue to use 48657dacad5SJay Sternberg * @cmd: The command to send 48704f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 48857dacad5SJay Sternberg */ 48904f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 49004f3eafdSJens Axboe bool write_sq) 49157dacad5SJay Sternberg { 49290ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 493c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 494c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 49590ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49690ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49704f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 49804f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 49904f3eafdSJens Axboe } 50004f3eafdSJens Axboe 50104f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 50204f3eafdSJens Axboe { 50304f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50404f3eafdSJens Axboe 50504f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50604f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50704f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 50890ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50957dacad5SJay Sternberg } 51057dacad5SJay Sternberg 511a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 51257dacad5SJay Sternberg { 513f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 51557dacad5SJay Sternberg } 51657dacad5SJay Sternberg 517955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518955b1b5aSMinwoo Im { 519955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 52020469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 521955b1b5aSMinwoo Im unsigned int avg_seg_size; 522955b1b5aSMinwoo Im 52320469a37SKeith Busch if (nseg == 0) 52420469a37SKeith Busch return false; 52520469a37SKeith Busch 52620469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 527955b1b5aSMinwoo Im 528955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 529955b1b5aSMinwoo Im return false; 530955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 531955b1b5aSMinwoo Im return false; 532955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 533955b1b5aSMinwoo Im return false; 534955b1b5aSMinwoo Im return true; 535955b1b5aSMinwoo Im } 536955b1b5aSMinwoo Im 5377fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 53857dacad5SJay Sternberg { 539f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 540a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 541a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 54257dacad5SJay Sternberg int i; 54357dacad5SJay Sternberg 544dff824b2SChristoph Hellwig if (iod->dma_len) { 545f2fa006fSIsrael Rukshin dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 546f2fa006fSIsrael Rukshin rq_dma_dir(req)); 547dff824b2SChristoph Hellwig return; 548dff824b2SChristoph Hellwig } 549dff824b2SChristoph Hellwig 550dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 551dff824b2SChristoph Hellwig 5527fe07d14SChristoph Hellwig /* P2PDMA requests do not need to be unmapped */ 5537fe07d14SChristoph Hellwig if (!is_pci_p2pdma_page(sg_page(iod->sg))) 554dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5557fe07d14SChristoph Hellwig 5567fe07d14SChristoph Hellwig 55757dacad5SJay Sternberg if (iod->npages == 0) 558a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 559a7a7cbe3SChaitanya Kulkarni dma_addr); 560a7a7cbe3SChaitanya Kulkarni 56157dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 562a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 563a7a7cbe3SChaitanya Kulkarni 564a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 565a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 566a7a7cbe3SChaitanya Kulkarni 567a7a7cbe3SChaitanya Kulkarni next_dma_addr = 568a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 569a7a7cbe3SChaitanya Kulkarni } else { 570a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 571a7a7cbe3SChaitanya Kulkarni 572a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 573a7a7cbe3SChaitanya Kulkarni } 574a7a7cbe3SChaitanya Kulkarni 575a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 576a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 57757dacad5SJay Sternberg } 57857dacad5SJay Sternberg 579943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 58057dacad5SJay Sternberg } 58157dacad5SJay Sternberg 582d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 583d0877473SKeith Busch { 584d0877473SKeith Busch int i; 585d0877473SKeith Busch struct scatterlist *sg; 586d0877473SKeith Busch 587d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 588d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 589d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 590d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 591d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 592d0877473SKeith Busch sg_dma_len(sg)); 593d0877473SKeith Busch } 594d0877473SKeith Busch } 595d0877473SKeith Busch 596a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 597a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 59857dacad5SJay Sternberg { 599f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 60057dacad5SJay Sternberg struct dma_pool *pool; 601b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 60257dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 60357dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 60457dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6055fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 60657dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 60757dacad5SJay Sternberg __le64 *prp_list; 608a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 60957dacad5SJay Sternberg dma_addr_t prp_dma; 61057dacad5SJay Sternberg int nprps, i; 61157dacad5SJay Sternberg 61257dacad5SJay Sternberg length -= (page_size - offset); 6135228b328SJan H. Schönherr if (length <= 0) { 6145228b328SJan H. Schönherr iod->first_dma = 0; 615a7a7cbe3SChaitanya Kulkarni goto done; 6165228b328SJan H. Schönherr } 61757dacad5SJay Sternberg 61857dacad5SJay Sternberg dma_len -= (page_size - offset); 61957dacad5SJay Sternberg if (dma_len) { 62057dacad5SJay Sternberg dma_addr += (page_size - offset); 62157dacad5SJay Sternberg } else { 62257dacad5SJay Sternberg sg = sg_next(sg); 62357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 62457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62557dacad5SJay Sternberg } 62657dacad5SJay Sternberg 62757dacad5SJay Sternberg if (length <= page_size) { 62857dacad5SJay Sternberg iod->first_dma = dma_addr; 629a7a7cbe3SChaitanya Kulkarni goto done; 63057dacad5SJay Sternberg } 63157dacad5SJay Sternberg 63257dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 63357dacad5SJay Sternberg if (nprps <= (256 / 8)) { 63457dacad5SJay Sternberg pool = dev->prp_small_pool; 63557dacad5SJay Sternberg iod->npages = 0; 63657dacad5SJay Sternberg } else { 63757dacad5SJay Sternberg pool = dev->prp_page_pool; 63857dacad5SJay Sternberg iod->npages = 1; 63957dacad5SJay Sternberg } 64057dacad5SJay Sternberg 64169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64257dacad5SJay Sternberg if (!prp_list) { 64357dacad5SJay Sternberg iod->first_dma = dma_addr; 64457dacad5SJay Sternberg iod->npages = -1; 64586eea289SKeith Busch return BLK_STS_RESOURCE; 64657dacad5SJay Sternberg } 64757dacad5SJay Sternberg list[0] = prp_list; 64857dacad5SJay Sternberg iod->first_dma = prp_dma; 64957dacad5SJay Sternberg i = 0; 65057dacad5SJay Sternberg for (;;) { 65157dacad5SJay Sternberg if (i == page_size >> 3) { 65257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65457dacad5SJay Sternberg if (!prp_list) 65586eea289SKeith Busch return BLK_STS_RESOURCE; 65657dacad5SJay Sternberg list[iod->npages++] = prp_list; 65757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 65857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 65957dacad5SJay Sternberg i = 1; 66057dacad5SJay Sternberg } 66157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 66257dacad5SJay Sternberg dma_len -= page_size; 66357dacad5SJay Sternberg dma_addr += page_size; 66457dacad5SJay Sternberg length -= page_size; 66557dacad5SJay Sternberg if (length <= 0) 66657dacad5SJay Sternberg break; 66757dacad5SJay Sternberg if (dma_len > 0) 66857dacad5SJay Sternberg continue; 66986eea289SKeith Busch if (unlikely(dma_len < 0)) 67086eea289SKeith Busch goto bad_sgl; 67157dacad5SJay Sternberg sg = sg_next(sg); 67257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 67457dacad5SJay Sternberg } 67557dacad5SJay Sternberg 676a7a7cbe3SChaitanya Kulkarni done: 677a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 678a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 679a7a7cbe3SChaitanya Kulkarni 68086eea289SKeith Busch return BLK_STS_OK; 68186eea289SKeith Busch 68286eea289SKeith Busch bad_sgl: 683d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 684d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 685d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 68686eea289SKeith Busch return BLK_STS_IOERR; 68757dacad5SJay Sternberg } 68857dacad5SJay Sternberg 689a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 690a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 691a7a7cbe3SChaitanya Kulkarni { 692a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 693a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 694a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 695a7a7cbe3SChaitanya Kulkarni } 696a7a7cbe3SChaitanya Kulkarni 697a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 698a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 699a7a7cbe3SChaitanya Kulkarni { 700a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 701a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 702a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 703a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 704a7a7cbe3SChaitanya Kulkarni } else { 705a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 706a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 707a7a7cbe3SChaitanya Kulkarni } 708a7a7cbe3SChaitanya Kulkarni } 709a7a7cbe3SChaitanya Kulkarni 710a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 711b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 712a7a7cbe3SChaitanya Kulkarni { 713a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 714a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 715a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 716a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 717a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 718b0f2853bSChristoph Hellwig int i = 0; 719a7a7cbe3SChaitanya Kulkarni 720a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 721a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 722a7a7cbe3SChaitanya Kulkarni 723b0f2853bSChristoph Hellwig if (entries == 1) { 724a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 725a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 726a7a7cbe3SChaitanya Kulkarni } 727a7a7cbe3SChaitanya Kulkarni 728a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 729a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 730a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 731a7a7cbe3SChaitanya Kulkarni } else { 732a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 733a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 734a7a7cbe3SChaitanya Kulkarni } 735a7a7cbe3SChaitanya Kulkarni 736a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 737a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 738a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 739a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 740a7a7cbe3SChaitanya Kulkarni } 741a7a7cbe3SChaitanya Kulkarni 742a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 743a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 746a7a7cbe3SChaitanya Kulkarni 747a7a7cbe3SChaitanya Kulkarni do { 748a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 749a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 750a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 751a7a7cbe3SChaitanya Kulkarni 752a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 753a7a7cbe3SChaitanya Kulkarni if (!sg_list) 754a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni i = 0; 757a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 758a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 759a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 760a7a7cbe3SChaitanya Kulkarni } 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 763a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 764b0f2853bSChristoph Hellwig } while (--entries > 0); 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 767a7a7cbe3SChaitanya Kulkarni } 768a7a7cbe3SChaitanya Kulkarni 769dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 770dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 771dff824b2SChristoph Hellwig struct bio_vec *bv) 772dff824b2SChristoph Hellwig { 773dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 774dff824b2SChristoph Hellwig unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 775dff824b2SChristoph Hellwig 776dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 777dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 778dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 779dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 780dff824b2SChristoph Hellwig 781dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 782dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 783dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 784dff824b2SChristoph Hellwig return 0; 785dff824b2SChristoph Hellwig } 786dff824b2SChristoph Hellwig 78729791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 78829791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 78929791057SChristoph Hellwig struct bio_vec *bv) 79029791057SChristoph Hellwig { 79129791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 79229791057SChristoph Hellwig 79329791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 79429791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 79529791057SChristoph Hellwig return BLK_STS_RESOURCE; 79629791057SChristoph Hellwig iod->dma_len = bv->bv_len; 79729791057SChristoph Hellwig 798049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 79929791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 80029791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 80129791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 80229791057SChristoph Hellwig return 0; 80329791057SChristoph Hellwig } 80429791057SChristoph Hellwig 805fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 806b131c61dSChristoph Hellwig struct nvme_command *cmnd) 80757dacad5SJay Sternberg { 808f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80970479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 810b0f2853bSChristoph Hellwig int nr_mapped; 81157dacad5SJay Sternberg 812dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 813dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 814dff824b2SChristoph Hellwig 815dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 816dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 817dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 818dff824b2SChristoph Hellwig &cmnd->rw, &bv); 81929791057SChristoph Hellwig 82029791057SChristoph Hellwig if (iod->nvmeq->qid && 82129791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 82229791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 82329791057SChristoph Hellwig &cmnd->rw, &bv); 824dff824b2SChristoph Hellwig } 825dff824b2SChristoph Hellwig } 826dff824b2SChristoph Hellwig 827dff824b2SChristoph Hellwig iod->dma_len = 0; 8289b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8299b048119SChristoph Hellwig if (!iod->sg) 8309b048119SChristoph Hellwig return BLK_STS_RESOURCE; 831f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 83270479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 833ba1ca37eSChristoph Hellwig if (!iod->nents) 834ba1ca37eSChristoph Hellwig goto out; 835ba1ca37eSChristoph Hellwig 836e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 837e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 83870479b71SChristoph Hellwig rq_dma_dir(req)); 839e0596ab2SLogan Gunthorpe else 840e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 84170479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 842b0f2853bSChristoph Hellwig if (!nr_mapped) 843ba1ca37eSChristoph Hellwig goto out; 844ba1ca37eSChristoph Hellwig 84570479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 846955b1b5aSMinwoo Im if (iod->use_sgl) 847b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 848a7a7cbe3SChaitanya Kulkarni else 849a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 850ba1ca37eSChristoph Hellwig out: 8514aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8527fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 853ba1ca37eSChristoph Hellwig return ret; 85457dacad5SJay Sternberg } 85557dacad5SJay Sternberg 8564aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8574aedb705SChristoph Hellwig struct nvme_command *cmnd) 8584aedb705SChristoph Hellwig { 8594aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8604aedb705SChristoph Hellwig 8614aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8624aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8634aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8644aedb705SChristoph Hellwig return BLK_STS_IOERR; 8654aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 8664aedb705SChristoph Hellwig return 0; 8674aedb705SChristoph Hellwig } 8684aedb705SChristoph Hellwig 86957dacad5SJay Sternberg /* 87057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 87157dacad5SJay Sternberg */ 872fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 87357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 87457dacad5SJay Sternberg { 87557dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 87657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87857dacad5SJay Sternberg struct request *req = bd->rq; 8799b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 880ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 881ebe6d874SChristoph Hellwig blk_status_t ret; 88257dacad5SJay Sternberg 8839b048119SChristoph Hellwig iod->aborted = 0; 8849b048119SChristoph Hellwig iod->npages = -1; 8859b048119SChristoph Hellwig iod->nents = 0; 8869b048119SChristoph Hellwig 887d1f06f4aSJens Axboe /* 888d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 889d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 890d1f06f4aSJens Axboe */ 8914e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 892d1f06f4aSJens Axboe return BLK_STS_IOERR; 893d1f06f4aSJens Axboe 894f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 895fc17b653SChristoph Hellwig if (ret) 896f4800d6dSChristoph Hellwig return ret; 89757dacad5SJay Sternberg 898fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 899b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 900fc17b653SChristoph Hellwig if (ret) 9019b048119SChristoph Hellwig goto out_free_cmd; 902fc17b653SChristoph Hellwig } 903ba1ca37eSChristoph Hellwig 9044aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9054aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9064aedb705SChristoph Hellwig if (ret) 9074aedb705SChristoph Hellwig goto out_unmap_data; 9084aedb705SChristoph Hellwig } 9094aedb705SChristoph Hellwig 910aae239e1SChristoph Hellwig blk_mq_start_request(req); 91104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 912fc17b653SChristoph Hellwig return BLK_STS_OK; 9134aedb705SChristoph Hellwig out_unmap_data: 9144aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 915f9d03f96SChristoph Hellwig out_free_cmd: 916f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 917ba1ca37eSChristoph Hellwig return ret; 91857dacad5SJay Sternberg } 91957dacad5SJay Sternberg 92077f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 921eee417b0SChristoph Hellwig { 922f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9234aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 924eee417b0SChristoph Hellwig 925915f04c9SChristoph Hellwig nvme_cleanup_cmd(req); 9264aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9274aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9284aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 929b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9304aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 93177f02a7aSChristoph Hellwig nvme_complete_rq(req); 93257dacad5SJay Sternberg } 93357dacad5SJay Sternberg 934d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 935750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 936d783e0bdSMarta Rybczynska { 937750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 938750dde44SChristoph Hellwig nvmeq->cq_phase; 939d783e0bdSMarta Rybczynska } 940d783e0bdSMarta Rybczynska 941eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 94257dacad5SJay Sternberg { 943eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 94457dacad5SJay Sternberg 945eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 946eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 947eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 948eb281c82SSagi Grimberg } 949adf68f21SChristoph Hellwig 9505cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 95157dacad5SJay Sternberg { 9525cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 95357dacad5SJay Sternberg struct request *req; 954adf68f21SChristoph Hellwig 95583a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9561b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 957aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 95883a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 95983a12fb7SSagi Grimberg return; 960aae239e1SChristoph Hellwig } 961aae239e1SChristoph Hellwig 962adf68f21SChristoph Hellwig /* 963adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 964adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 965adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 966adf68f21SChristoph Hellwig * for them but rather special case them here. 967adf68f21SChristoph Hellwig */ 968adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 96938dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9707bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 97183a12fb7SSagi Grimberg cqe->status, &cqe->result); 972a0fa9647SJens Axboe return; 97357dacad5SJay Sternberg } 97457dacad5SJay Sternberg 97583a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 976604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 97783a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 97883a12fb7SSagi Grimberg } 97957dacad5SJay Sternberg 9805cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 98183a12fb7SSagi Grimberg { 9825cb525c8SJens Axboe while (start != end) { 9835cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9845cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9855cb525c8SJens Axboe start = 0; 9865cb525c8SJens Axboe } 9875cb525c8SJens Axboe } 98883a12fb7SSagi Grimberg 9895cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9905cb525c8SJens Axboe { 991dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 992920d13a8SSagi Grimberg nvmeq->cq_head = 0; 993920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 994dcca1662SHongbo Yao } else { 995dcca1662SHongbo Yao nvmeq->cq_head++; 996920d13a8SSagi Grimberg } 997a0fa9647SJens Axboe } 998a0fa9647SJens Axboe 9991052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10001052b8acSJens Axboe u16 *end, unsigned int tag) 1001a0fa9647SJens Axboe { 10021052b8acSJens Axboe int found = 0; 100383a12fb7SSagi Grimberg 10045cb525c8SJens Axboe *start = nvmeq->cq_head; 10051052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10061052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10071052b8acSJens Axboe found++; 10085cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 100957dacad5SJay Sternberg } 10105cb525c8SJens Axboe *end = nvmeq->cq_head; 101157dacad5SJay Sternberg 10125cb525c8SJens Axboe if (*start != *end) 1013eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10145cb525c8SJens Axboe return found; 101557dacad5SJay Sternberg } 101657dacad5SJay Sternberg 101757dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 101857dacad5SJay Sternberg { 101957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 102068fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10215cb525c8SJens Axboe u16 start, end; 10225cb525c8SJens Axboe 10233a7afd8eSChristoph Hellwig /* 10243a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10253a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10263a7afd8eSChristoph Hellwig */ 10273a7afd8eSChristoph Hellwig rmb(); 102868fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 102968fa9dbeSJens Axboe ret = IRQ_HANDLED; 10305cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 103168fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10323a7afd8eSChristoph Hellwig wmb(); 10335cb525c8SJens Axboe 103468fa9dbeSJens Axboe if (start != end) { 10355cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10365cb525c8SJens Axboe return IRQ_HANDLED; 103757dacad5SJay Sternberg } 103857dacad5SJay Sternberg 103968fa9dbeSJens Axboe return ret; 104057dacad5SJay Sternberg } 104157dacad5SJay Sternberg 104257dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 104357dacad5SJay Sternberg { 104457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1045750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 104657dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1047d783e0bdSMarta Rybczynska return IRQ_NONE; 104857dacad5SJay Sternberg } 104957dacad5SJay Sternberg 10500b2a8a9fSChristoph Hellwig /* 10510b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10520b2a8a9fSChristoph Hellwig * Can be called from any context. 10530b2a8a9fSChristoph Hellwig */ 10540b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1055a0fa9647SJens Axboe { 10563a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10575cb525c8SJens Axboe u16 start, end; 10581052b8acSJens Axboe int found; 1059a0fa9647SJens Axboe 10603a7afd8eSChristoph Hellwig /* 10613a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10623a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10633a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10643a7afd8eSChristoph Hellwig */ 10657c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10663a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 106791a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 106891a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 106991a509f8SChristoph Hellwig } else { 10703a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10715cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10723a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 107391a509f8SChristoph Hellwig } 1074442e19b7SSagi Grimberg 10755cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1076442e19b7SSagi Grimberg return found; 1077a0fa9647SJens Axboe } 1078a0fa9647SJens Axboe 10799743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10807776db1cSKeith Busch { 10817776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1082dabcefabSJens Axboe u16 start, end; 1083dabcefabSJens Axboe bool found; 1084dabcefabSJens Axboe 1085dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1086dabcefabSJens Axboe return 0; 1087dabcefabSJens Axboe 10883a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 10899743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 10903a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1091dabcefabSJens Axboe 1092dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1093dabcefabSJens Axboe return found; 1094dabcefabSJens Axboe } 1095dabcefabSJens Axboe 1096ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 109757dacad5SJay Sternberg { 1098f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1099147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 110057dacad5SJay Sternberg struct nvme_command c; 110157dacad5SJay Sternberg 110257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110357dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1104ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 110504f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 110657dacad5SJay Sternberg } 110757dacad5SJay Sternberg 110857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 110957dacad5SJay Sternberg { 111057dacad5SJay Sternberg struct nvme_command c; 111157dacad5SJay Sternberg 111257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 111457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 111557dacad5SJay Sternberg 11161c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 111757dacad5SJay Sternberg } 111857dacad5SJay Sternberg 111957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1120a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 112157dacad5SJay Sternberg { 112257dacad5SJay Sternberg struct nvme_command c; 11234b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11244b04cc6aSJens Axboe 11257c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11264b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 112757dacad5SJay Sternberg 112857dacad5SJay Sternberg /* 112916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 113057dacad5SJay Sternberg * is attached to the request. 113157dacad5SJay Sternberg */ 113257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 113457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 113557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 113657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 113757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1138a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 113957dacad5SJay Sternberg 11401c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 114157dacad5SJay Sternberg } 114257dacad5SJay Sternberg 114357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 114457dacad5SJay Sternberg struct nvme_queue *nvmeq) 114557dacad5SJay Sternberg { 11469abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 114757dacad5SJay Sternberg struct nvme_command c; 114881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 114957dacad5SJay Sternberg 115057dacad5SJay Sternberg /* 11519abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11529abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11539abd68efSJens Axboe * URGENT. 11549abd68efSJens Axboe */ 11559abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11569abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11579abd68efSJens Axboe 11589abd68efSJens Axboe /* 115916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 116057dacad5SJay Sternberg * is attached to the request. 116157dacad5SJay Sternberg */ 116257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 116357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 116457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 116557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 116657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 116757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 116857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 116957dacad5SJay Sternberg 11701c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117157dacad5SJay Sternberg } 117257dacad5SJay Sternberg 117357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 117457dacad5SJay Sternberg { 117557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 117657dacad5SJay Sternberg } 117757dacad5SJay Sternberg 117857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 117957dacad5SJay Sternberg { 118057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 118157dacad5SJay Sternberg } 118257dacad5SJay Sternberg 11832a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 118457dacad5SJay Sternberg { 1185f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1186f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 118757dacad5SJay Sternberg 118827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 118927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1190e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1191e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 119257dacad5SJay Sternberg } 119357dacad5SJay Sternberg 1194b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1195b2a0eb1aSKeith Busch { 1196b2a0eb1aSKeith Busch 1197b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1198b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1199b2a0eb1aSKeith Busch */ 1200b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1201b2a0eb1aSKeith Busch 1202ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1203ad70062cSJianchao Wang switch (dev->ctrl.state) { 1204ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1205ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1206b2a0eb1aSKeith Busch return false; 1207ad70062cSJianchao Wang default: 1208ad70062cSJianchao Wang break; 1209ad70062cSJianchao Wang } 1210b2a0eb1aSKeith Busch 1211b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1212b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1213b2a0eb1aSKeith Busch */ 1214b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1215b2a0eb1aSKeith Busch return false; 1216b2a0eb1aSKeith Busch 1217b2a0eb1aSKeith Busch return true; 1218b2a0eb1aSKeith Busch } 1219b2a0eb1aSKeith Busch 1220b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1221b2a0eb1aSKeith Busch { 1222b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1223b2a0eb1aSKeith Busch u16 pci_status; 1224b2a0eb1aSKeith Busch int result; 1225b2a0eb1aSKeith Busch 1226b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1227b2a0eb1aSKeith Busch &pci_status); 1228b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1229b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1230b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1231b2a0eb1aSKeith Busch csts, pci_status); 1232b2a0eb1aSKeith Busch else 1233b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1234b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1235b2a0eb1aSKeith Busch csts, result); 1236b2a0eb1aSKeith Busch } 1237b2a0eb1aSKeith Busch 123831c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 123957dacad5SJay Sternberg { 1240f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1241f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 124257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 124357dacad5SJay Sternberg struct request *abort_req; 124457dacad5SJay Sternberg struct nvme_command cmd; 1245b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1246b2a0eb1aSKeith Busch 1247651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1248651438bbSWen Xiong * the recovery mechanism will surely fail. 1249651438bbSWen Xiong */ 1250651438bbSWen Xiong mb(); 1251651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1252651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1253651438bbSWen Xiong 1254b2a0eb1aSKeith Busch /* 1255b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1256b2a0eb1aSKeith Busch */ 1257b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1258b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1259b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1260d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1261db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1262b2a0eb1aSKeith Busch } 126357dacad5SJay Sternberg 126431c7c7d2SChristoph Hellwig /* 12657776db1cSKeith Busch * Did we miss an interrupt? 12667776db1cSKeith Busch */ 12670b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12687776db1cSKeith Busch dev_warn(dev->ctrl.device, 12697776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12707776db1cSKeith Busch req->tag, nvmeq->qid); 1271db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12727776db1cSKeith Busch } 12737776db1cSKeith Busch 12747776db1cSKeith Busch /* 1275fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1276fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1277fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1278db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1279fd634f41SChristoph Hellwig */ 12804244140dSKeith Busch switch (dev->ctrl.state) { 12814244140dSKeith Busch case NVME_CTRL_CONNECTING: 12822036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 12832036f726SKeith Busch /* fall through */ 12842036f726SKeith Busch case NVME_CTRL_DELETING: 1285b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1286fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1287fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 12882036f726SKeith Busch nvme_dev_disable(dev, true); 128927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1290db8c48e4SChristoph Hellwig return BLK_EH_DONE; 129139a9dd81SKeith Busch case NVME_CTRL_RESETTING: 129239a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12934244140dSKeith Busch default: 12944244140dSKeith Busch break; 1295fd634f41SChristoph Hellwig } 1296fd634f41SChristoph Hellwig 1297fd634f41SChristoph Hellwig /* 1298e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1299e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1300e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 130131c7c7d2SChristoph Hellwig */ 1302f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13031b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 130457dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 130557dacad5SJay Sternberg req->tag, nvmeq->qid); 1306a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1307d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1308e1569a16SKeith Busch 130927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1310db8c48e4SChristoph Hellwig return BLK_EH_DONE; 131157dacad5SJay Sternberg } 131257dacad5SJay Sternberg 1313e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1314e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1315e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1316e7a2a87dSChristoph Hellwig } 13177bf7d778SKeith Busch iod->aborted = 1; 131857dacad5SJay Sternberg 131957dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 132057dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 132157dacad5SJay Sternberg cmd.abort.cid = req->tag; 132257dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 132357dacad5SJay Sternberg 13241b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13251b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 132657dacad5SJay Sternberg req->tag, nvmeq->qid); 1327e7a2a87dSChristoph Hellwig 1328e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1329eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13306bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13316bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 133231c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 133357dacad5SJay Sternberg } 133457dacad5SJay Sternberg 1335e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1336e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1337e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 133857dacad5SJay Sternberg 133957dacad5SJay Sternberg /* 134057dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 134157dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 134257dacad5SJay Sternberg * as the device then is in a faulty state. 134357dacad5SJay Sternberg */ 134457dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 134557dacad5SJay Sternberg } 134657dacad5SJay Sternberg 134757dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 134857dacad5SJay Sternberg { 13498a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 135057dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 135163223078SChristoph Hellwig if (!nvmeq->sq_cmds) 135263223078SChristoph Hellwig return; 13530f238ff5SLogan Gunthorpe 135463223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 135588a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13568a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 135763223078SChristoph Hellwig } else { 13588a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 135963223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13600f238ff5SLogan Gunthorpe } 136157dacad5SJay Sternberg } 136257dacad5SJay Sternberg 136357dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 136457dacad5SJay Sternberg { 136557dacad5SJay Sternberg int i; 136657dacad5SJay Sternberg 1367d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1368d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1369147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 137057dacad5SJay Sternberg } 137157dacad5SJay Sternberg } 137257dacad5SJay Sternberg 137357dacad5SJay Sternberg /** 137457dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 137540581d1aSBart Van Assche * @nvmeq: queue to suspend 137657dacad5SJay Sternberg */ 137757dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 137857dacad5SJay Sternberg { 13794e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 138057dacad5SJay Sternberg return 1; 138157dacad5SJay Sternberg 13824e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1383d1f06f4aSJens Axboe mb(); 138457dacad5SJay Sternberg 13854e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13861c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1387c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13887c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13894e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 139057dacad5SJay Sternberg return 0; 139157dacad5SJay Sternberg } 139257dacad5SJay Sternberg 13938fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13948fae268bSKeith Busch { 13958fae268bSKeith Busch int i; 13968fae268bSKeith Busch 13978fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13988fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13998fae268bSKeith Busch } 14008fae268bSKeith Busch 1401a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 140257dacad5SJay Sternberg { 1403147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 140457dacad5SJay Sternberg 1405a5cdb68cSKeith Busch if (shutdown) 1406a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1407a5cdb68cSKeith Busch else 1408b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 140957dacad5SJay Sternberg 14100b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 141157dacad5SJay Sternberg } 141257dacad5SJay Sternberg 141357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 141457dacad5SJay Sternberg int entry_size) 141557dacad5SJay Sternberg { 141657dacad5SJay Sternberg int q_depth = dev->q_depth; 14175fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14185fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 141957dacad5SJay Sternberg 142057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 142157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14225fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 142357dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 142457dacad5SJay Sternberg 142557dacad5SJay Sternberg /* 142657dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 142757dacad5SJay Sternberg * would be better to map queues in system memory with the 142857dacad5SJay Sternberg * original depth 142957dacad5SJay Sternberg */ 143057dacad5SJay Sternberg if (q_depth < 64) 143157dacad5SJay Sternberg return -ENOMEM; 143257dacad5SJay Sternberg } 143357dacad5SJay Sternberg 143457dacad5SJay Sternberg return q_depth; 143557dacad5SJay Sternberg } 143657dacad5SJay Sternberg 143757dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14388a1d09a6SBenjamin Herrenschmidt int qid) 143957dacad5SJay Sternberg { 14400f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1441815c6704SKeith Busch 14420f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14438a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1444bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14450f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14460f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 144763223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 144863223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 144963223078SChristoph Hellwig return 0; 145063223078SChristoph Hellwig } 1451bfac8e9fSAlan Mikhak 14528a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1453bfac8e9fSAlan Mikhak } 14540f238ff5SLogan Gunthorpe } 14550f238ff5SLogan Gunthorpe 14568a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 145757dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 145857dacad5SJay Sternberg if (!nvmeq->sq_cmds) 145957dacad5SJay Sternberg return -ENOMEM; 146057dacad5SJay Sternberg return 0; 146157dacad5SJay Sternberg } 146257dacad5SJay Sternberg 1463a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 146457dacad5SJay Sternberg { 1465147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 146657dacad5SJay Sternberg 146762314e40SKeith Busch if (dev->ctrl.queue_count > qid) 146862314e40SKeith Busch return 0; 146957dacad5SJay Sternberg 1470c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14718a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14728a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 147357dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 147457dacad5SJay Sternberg if (!nvmeq->cqes) 147557dacad5SJay Sternberg goto free_nvmeq; 147657dacad5SJay Sternberg 14778a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 147857dacad5SJay Sternberg goto free_cqdma; 147957dacad5SJay Sternberg 148057dacad5SJay Sternberg nvmeq->dev = dev; 14811ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14823a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 148357dacad5SJay Sternberg nvmeq->cq_head = 0; 148457dacad5SJay Sternberg nvmeq->cq_phase = 1; 148557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 148657dacad5SJay Sternberg nvmeq->qid = qid; 1487d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 148857dacad5SJay Sternberg 1489147b27e4SSagi Grimberg return 0; 149057dacad5SJay Sternberg 149157dacad5SJay Sternberg free_cqdma: 14928a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 149357dacad5SJay Sternberg nvmeq->cq_dma_addr); 149457dacad5SJay Sternberg free_nvmeq: 1495147b27e4SSagi Grimberg return -ENOMEM; 149657dacad5SJay Sternberg } 149757dacad5SJay Sternberg 1498dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 149957dacad5SJay Sternberg { 15000ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15010ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15020ff199cbSChristoph Hellwig 15030ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15040ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15050ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15060ff199cbSChristoph Hellwig } else { 15070ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15080ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15090ff199cbSChristoph Hellwig } 151057dacad5SJay Sternberg } 151157dacad5SJay Sternberg 151257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 151357dacad5SJay Sternberg { 151457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 151557dacad5SJay Sternberg 151657dacad5SJay Sternberg nvmeq->sq_tail = 0; 151704f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 151857dacad5SJay Sternberg nvmeq->cq_head = 0; 151957dacad5SJay Sternberg nvmeq->cq_phase = 1; 152057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15218a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1522f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 152357dacad5SJay Sternberg dev->online_queues++; 15243a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 152557dacad5SJay Sternberg } 152657dacad5SJay Sternberg 15274b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 152857dacad5SJay Sternberg { 152957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153057dacad5SJay Sternberg int result; 15317c349ddeSKeith Busch u16 vector = 0; 153257dacad5SJay Sternberg 1533d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1534d1ed6aa1SChristoph Hellwig 153522b55601SKeith Busch /* 153622b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 153722b55601SKeith Busch * has only one vector available. 153822b55601SKeith Busch */ 15394b04cc6aSJens Axboe if (!polled) 1540a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15414b04cc6aSJens Axboe else 15427c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15434b04cc6aSJens Axboe 1544a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1545ded45505SKeith Busch if (result) 1546ded45505SKeith Busch return result; 154757dacad5SJay Sternberg 154857dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 154957dacad5SJay Sternberg if (result < 0) 1550ded45505SKeith Busch return result; 1551ded45505SKeith Busch else if (result) 155257dacad5SJay Sternberg goto release_cq; 155357dacad5SJay Sternberg 1554a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1555161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15564b04cc6aSJens Axboe 15577c349ddeSKeith Busch if (!polled) { 1558dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 155957dacad5SJay Sternberg if (result < 0) 156057dacad5SJay Sternberg goto release_sq; 15614b04cc6aSJens Axboe } 156257dacad5SJay Sternberg 15634e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 156457dacad5SJay Sternberg return result; 156557dacad5SJay Sternberg 156657dacad5SJay Sternberg release_sq: 1567f25a2dfcSJianchao Wang dev->online_queues--; 156857dacad5SJay Sternberg adapter_delete_sq(dev, qid); 156957dacad5SJay Sternberg release_cq: 157057dacad5SJay Sternberg adapter_delete_cq(dev, qid); 157157dacad5SJay Sternberg return result; 157257dacad5SJay Sternberg } 157357dacad5SJay Sternberg 1574f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 157557dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 157677f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 157757dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 157857dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15790350815aSChristoph Hellwig .init_request = nvme_init_request, 158057dacad5SJay Sternberg .timeout = nvme_timeout, 158157dacad5SJay Sternberg }; 158257dacad5SJay Sternberg 1583f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1584376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1585376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1586376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1587376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1588376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1589376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1590376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1591c6d962aeSChristoph Hellwig .poll = nvme_poll, 1592dabcefabSJens Axboe }; 1593dabcefabSJens Axboe 159457dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 159557dacad5SJay Sternberg { 15961c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 159769d9a99cSKeith Busch /* 159869d9a99cSKeith Busch * If the controller was reset during removal, it's possible 159969d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 160069d9a99cSKeith Busch * queue to flush these to completion. 160169d9a99cSKeith Busch */ 1602c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16031c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 160457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 160557dacad5SJay Sternberg } 160657dacad5SJay Sternberg } 160757dacad5SJay Sternberg 160857dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 160957dacad5SJay Sternberg { 16101c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 161157dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 161257dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1613e3e9d50cSKeith Busch 161438dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 161557dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 161657dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1617d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1618d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 161957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 162057dacad5SJay Sternberg 162157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 162257dacad5SJay Sternberg return -ENOMEM; 162334b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 162457dacad5SJay Sternberg 16251c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16261c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 162757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 162857dacad5SJay Sternberg return -ENOMEM; 162957dacad5SJay Sternberg } 16301c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 163157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16321c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 163357dacad5SJay Sternberg return -ENODEV; 163457dacad5SJay Sternberg } 163557dacad5SJay Sternberg } else 1636c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 163757dacad5SJay Sternberg 163857dacad5SJay Sternberg return 0; 163957dacad5SJay Sternberg } 164057dacad5SJay Sternberg 164197f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 164297f6ef64SXu Yu { 164397f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 164497f6ef64SXu Yu } 164597f6ef64SXu Yu 164697f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 164797f6ef64SXu Yu { 164897f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 164997f6ef64SXu Yu 165097f6ef64SXu Yu if (size <= dev->bar_mapped_size) 165197f6ef64SXu Yu return 0; 165297f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 165397f6ef64SXu Yu return -ENOMEM; 165497f6ef64SXu Yu if (dev->bar) 165597f6ef64SXu Yu iounmap(dev->bar); 165697f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 165797f6ef64SXu Yu if (!dev->bar) { 165897f6ef64SXu Yu dev->bar_mapped_size = 0; 165997f6ef64SXu Yu return -ENOMEM; 166097f6ef64SXu Yu } 166197f6ef64SXu Yu dev->bar_mapped_size = size; 166297f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 166397f6ef64SXu Yu 166497f6ef64SXu Yu return 0; 166597f6ef64SXu Yu } 166697f6ef64SXu Yu 166701ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 166857dacad5SJay Sternberg { 166957dacad5SJay Sternberg int result; 167057dacad5SJay Sternberg u32 aqa; 167157dacad5SJay Sternberg struct nvme_queue *nvmeq; 167257dacad5SJay Sternberg 167397f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 167497f6ef64SXu Yu if (result < 0) 167597f6ef64SXu Yu return result; 167697f6ef64SXu Yu 16778ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 167820d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 167957dacad5SJay Sternberg 16807a67cbeaSChristoph Hellwig if (dev->subsystem && 16817a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16827a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 168357dacad5SJay Sternberg 1684b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 168557dacad5SJay Sternberg if (result < 0) 168657dacad5SJay Sternberg return result; 168757dacad5SJay Sternberg 1688a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1689147b27e4SSagi Grimberg if (result) 1690147b27e4SSagi Grimberg return result; 169157dacad5SJay Sternberg 1692147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 169357dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 169457dacad5SJay Sternberg aqa |= aqa << 16; 169557dacad5SJay Sternberg 16967a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16977a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16987a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 169957dacad5SJay Sternberg 1700c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 170157dacad5SJay Sternberg if (result) 1702d4875622SKeith Busch return result; 170357dacad5SJay Sternberg 170457dacad5SJay Sternberg nvmeq->cq_vector = 0; 1705161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1706dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 170757dacad5SJay Sternberg if (result) { 17087c349ddeSKeith Busch dev->online_queues--; 1709d4875622SKeith Busch return result; 171057dacad5SJay Sternberg } 171157dacad5SJay Sternberg 17124e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 171357dacad5SJay Sternberg return result; 171457dacad5SJay Sternberg } 171557dacad5SJay Sternberg 1716749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 171757dacad5SJay Sternberg { 17184b04cc6aSJens Axboe unsigned i, max, rw_queues; 1719749941f2SChristoph Hellwig int ret = 0; 172057dacad5SJay Sternberg 1721d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1722a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1723749941f2SChristoph Hellwig ret = -ENOMEM; 172457dacad5SJay Sternberg break; 1725749941f2SChristoph Hellwig } 1726749941f2SChristoph Hellwig } 172757dacad5SJay Sternberg 1728d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1729e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1730e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1731e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17324b04cc6aSJens Axboe } else { 17334b04cc6aSJens Axboe rw_queues = max; 17344b04cc6aSJens Axboe } 17354b04cc6aSJens Axboe 1736949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17374b04cc6aSJens Axboe bool polled = i > rw_queues; 17384b04cc6aSJens Axboe 17394b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1740d4875622SKeith Busch if (ret) 174157dacad5SJay Sternberg break; 174257dacad5SJay Sternberg } 174357dacad5SJay Sternberg 1744749941f2SChristoph Hellwig /* 1745749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17468adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17478adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1748749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1749749941f2SChristoph Hellwig */ 1750749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 175157dacad5SJay Sternberg } 175257dacad5SJay Sternberg 1753202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1754202021c1SStephen Bates struct device_attribute *attr, 1755202021c1SStephen Bates char *buf) 1756202021c1SStephen Bates { 1757202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1758202021c1SStephen Bates 1759c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1760202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1761202021c1SStephen Bates } 1762202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1763202021c1SStephen Bates 176488de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 176557dacad5SJay Sternberg { 176688de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 176788de4598SChristoph Hellwig 176888de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 176988de4598SChristoph Hellwig } 177088de4598SChristoph Hellwig 177188de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 177288de4598SChristoph Hellwig { 177388de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 177488de4598SChristoph Hellwig } 177588de4598SChristoph Hellwig 1776f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 177757dacad5SJay Sternberg { 177888de4598SChristoph Hellwig u64 size, offset; 177957dacad5SJay Sternberg resource_size_t bar_size; 178057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17818969f1f8SChristoph Hellwig int bar; 178257dacad5SJay Sternberg 17839fe5c59fSKeith Busch if (dev->cmb_size) 17849fe5c59fSKeith Busch return; 17859fe5c59fSKeith Busch 17867a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1787f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1788f65efd6dSChristoph Hellwig return; 1789202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 179057dacad5SJay Sternberg 179188de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 179288de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17938969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17948969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 179557dacad5SJay Sternberg 179657dacad5SJay Sternberg if (offset > bar_size) 1797f65efd6dSChristoph Hellwig return; 179857dacad5SJay Sternberg 179957dacad5SJay Sternberg /* 180057dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 180157dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 180257dacad5SJay Sternberg * the reported size of the BAR 180357dacad5SJay Sternberg */ 180457dacad5SJay Sternberg if (size > bar_size - offset) 180557dacad5SJay Sternberg size = bar_size - offset; 180657dacad5SJay Sternberg 18070f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18080f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18090f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1810f65efd6dSChristoph Hellwig return; 18110f238ff5SLogan Gunthorpe } 18120f238ff5SLogan Gunthorpe 181357dacad5SJay Sternberg dev->cmb_size = size; 18140f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18150f238ff5SLogan Gunthorpe 18160f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18170f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18180f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1819f65efd6dSChristoph Hellwig 1820f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1821f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1822f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1823f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 182457dacad5SJay Sternberg } 182557dacad5SJay Sternberg 182657dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 182757dacad5SJay Sternberg { 18280f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1829f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1830f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18310f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1832f63572dfSJon Derrick } 183357dacad5SJay Sternberg } 183457dacad5SJay Sternberg 183587ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 183657dacad5SJay Sternberg { 18374033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 183887ad72a5SChristoph Hellwig struct nvme_command c; 183987ad72a5SChristoph Hellwig int ret; 184087ad72a5SChristoph Hellwig 184187ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 184287ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 184387ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 184487ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 184587ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 184687ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 184787ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 184887ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 184987ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 185087ad72a5SChristoph Hellwig 185187ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 185287ad72a5SChristoph Hellwig if (ret) { 185387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 185487ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 185587ad72a5SChristoph Hellwig ret, bits); 185687ad72a5SChristoph Hellwig } 185787ad72a5SChristoph Hellwig return ret; 185887ad72a5SChristoph Hellwig } 185987ad72a5SChristoph Hellwig 186087ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 186187ad72a5SChristoph Hellwig { 186287ad72a5SChristoph Hellwig int i; 186387ad72a5SChristoph Hellwig 186487ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 186587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 186687ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 186787ad72a5SChristoph Hellwig 1868cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1869cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1870cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 187187ad72a5SChristoph Hellwig } 187287ad72a5SChristoph Hellwig 187387ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 187487ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18754033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18764033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18774033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 187887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18797e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 188087ad72a5SChristoph Hellwig } 188187ad72a5SChristoph Hellwig 188292dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 188392dc6895SChristoph Hellwig u32 chunk_size) 188487ad72a5SChristoph Hellwig { 188587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 188692dc6895SChristoph Hellwig u32 max_entries, len; 18874033f35dSChristoph Hellwig dma_addr_t descs_dma; 18882ee0e4edSDan Carpenter int i = 0; 188987ad72a5SChristoph Hellwig void **bufs; 18906fbcde66SMinwoo Im u64 size, tmp; 189187ad72a5SChristoph Hellwig 189287ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 189387ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 189487ad72a5SChristoph Hellwig max_entries = tmp; 1895044a9df1SChristoph Hellwig 1896044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1897044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1898044a9df1SChristoph Hellwig 1899750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19004033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 190187ad72a5SChristoph Hellwig if (!descs) 190287ad72a5SChristoph Hellwig goto out; 190387ad72a5SChristoph Hellwig 190487ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 190587ad72a5SChristoph Hellwig if (!bufs) 190687ad72a5SChristoph Hellwig goto out_free_descs; 190787ad72a5SChristoph Hellwig 1908244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 190987ad72a5SChristoph Hellwig dma_addr_t dma_addr; 191087ad72a5SChristoph Hellwig 191150cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 191287ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 191387ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191487ad72a5SChristoph Hellwig if (!bufs[i]) 191587ad72a5SChristoph Hellwig break; 191687ad72a5SChristoph Hellwig 191787ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 191887ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 191987ad72a5SChristoph Hellwig i++; 192087ad72a5SChristoph Hellwig } 192187ad72a5SChristoph Hellwig 192292dc6895SChristoph Hellwig if (!size) 192387ad72a5SChristoph Hellwig goto out_free_bufs; 192487ad72a5SChristoph Hellwig 192587ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 192687ad72a5SChristoph Hellwig dev->host_mem_size = size; 192787ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19284033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 192987ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 193087ad72a5SChristoph Hellwig return 0; 193187ad72a5SChristoph Hellwig 193287ad72a5SChristoph Hellwig out_free_bufs: 193387ad72a5SChristoph Hellwig while (--i >= 0) { 193487ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 193587ad72a5SChristoph Hellwig 1936cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1937cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1938cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 193987ad72a5SChristoph Hellwig } 194087ad72a5SChristoph Hellwig 194187ad72a5SChristoph Hellwig kfree(bufs); 194287ad72a5SChristoph Hellwig out_free_descs: 19434033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19444033f35dSChristoph Hellwig descs_dma); 194587ad72a5SChristoph Hellwig out: 194687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 194787ad72a5SChristoph Hellwig return -ENOMEM; 194887ad72a5SChristoph Hellwig } 194987ad72a5SChristoph Hellwig 195092dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 195192dc6895SChristoph Hellwig { 195292dc6895SChristoph Hellwig u32 chunk_size; 195392dc6895SChristoph Hellwig 195492dc6895SChristoph Hellwig /* start big and work our way down */ 195530f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1956044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 195792dc6895SChristoph Hellwig chunk_size /= 2) { 195892dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 195992dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 196092dc6895SChristoph Hellwig return 0; 196192dc6895SChristoph Hellwig nvme_free_host_mem(dev); 196292dc6895SChristoph Hellwig } 196392dc6895SChristoph Hellwig } 196492dc6895SChristoph Hellwig 196592dc6895SChristoph Hellwig return -ENOMEM; 196692dc6895SChristoph Hellwig } 196792dc6895SChristoph Hellwig 19689620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 196987ad72a5SChristoph Hellwig { 197087ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 197187ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 197287ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 197387ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19746fbcde66SMinwoo Im int ret; 197587ad72a5SChristoph Hellwig 197687ad72a5SChristoph Hellwig preferred = min(preferred, max); 197787ad72a5SChristoph Hellwig if (min > max) { 197887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 197987ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 198087ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 198187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19829620cfbaSChristoph Hellwig return 0; 198387ad72a5SChristoph Hellwig } 198487ad72a5SChristoph Hellwig 198587ad72a5SChristoph Hellwig /* 198687ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 198787ad72a5SChristoph Hellwig */ 198887ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 198987ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 199087ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 199187ad72a5SChristoph Hellwig else 199287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 199387ad72a5SChristoph Hellwig } 199487ad72a5SChristoph Hellwig 199587ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 199692dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 199792dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 199892dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19999620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 200087ad72a5SChristoph Hellwig } 200187ad72a5SChristoph Hellwig 200292dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 200392dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 200492dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 200592dc6895SChristoph Hellwig } 200692dc6895SChristoph Hellwig 20079620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20089620cfbaSChristoph Hellwig if (ret) 200987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20109620cfbaSChristoph Hellwig return ret; 201157dacad5SJay Sternberg } 201257dacad5SJay Sternberg 2013612b7286SMing Lei /* 2014612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2015612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2016612b7286SMing Lei */ 2017612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20183b6592f7SJens Axboe { 2019612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2020612b7286SMing Lei unsigned int nr_read_queues; 2021c45b1fa2SMing Lei 20223b6592f7SJens Axboe /* 2023612b7286SMing Lei * If there is no interupt available for queues, ensure that 2024612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2025612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2026612b7286SMing Lei * 2027612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2028612b7286SMing Lei * write and read queues. 2029612b7286SMing Lei * 2030612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2031612b7286SMing Lei * queue. 20323b6592f7SJens Axboe */ 2033612b7286SMing Lei if (!nrirqs) { 2034612b7286SMing Lei nrirqs = 1; 2035612b7286SMing Lei nr_read_queues = 0; 2036612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2037612b7286SMing Lei nr_read_queues = 0; 2038612b7286SMing Lei } else if (write_queues >= nrirqs) { 2039612b7286SMing Lei nr_read_queues = 1; 20403b6592f7SJens Axboe } else { 2041612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20423b6592f7SJens Axboe } 2043612b7286SMing Lei 2044612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2045612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2046612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2047612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2048612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20493b6592f7SJens Axboe } 20503b6592f7SJens Axboe 20516451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20523b6592f7SJens Axboe { 20533b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20543b6592f7SJens Axboe struct irq_affinity affd = { 20553b6592f7SJens Axboe .pre_vectors = 1, 2056612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2057612b7286SMing Lei .priv = dev, 20583b6592f7SJens Axboe }; 20596451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 2060dad77d63SMinwoo Im unsigned int nr_cpus = num_possible_cpus(); 20616451fe73SJens Axboe 20626451fe73SJens Axboe /* 20636451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20646451fe73SJens Axboe * queue left over for non-polled IO. 20656451fe73SJens Axboe */ 20666451fe73SJens Axboe this_p_queues = poll_queues; 20676451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20686451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20696451fe73SJens Axboe irq_queues = 1; 20706451fe73SJens Axboe } else { 2071dad77d63SMinwoo Im if (nr_cpus < nr_io_queues - this_p_queues) 2072dad77d63SMinwoo Im irq_queues = nr_cpus + 1; 2073dad77d63SMinwoo Im else 2074c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20756451fe73SJens Axboe } 20766451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20773b6592f7SJens Axboe 2078612b7286SMing Lei /* Initialize for the single interrupt case */ 2079612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2080612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20813b6592f7SJens Axboe 208266341331SBenjamin Herrenschmidt /* 208366341331SBenjamin Herrenschmidt * Some Apple controllers require all queues to use the 208466341331SBenjamin Herrenschmidt * first vector. 208566341331SBenjamin Herrenschmidt */ 208666341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 208766341331SBenjamin Herrenschmidt irq_queues = 1; 208866341331SBenjamin Herrenschmidt 2089612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20903b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20913b6592f7SJens Axboe } 20923b6592f7SJens Axboe 20938fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20948fae268bSKeith Busch { 20958fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20968fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20978fae268bSKeith Busch } 20988fae268bSKeith Busch 209957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 210057dacad5SJay Sternberg { 2101147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 210257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 210397f6ef64SXu Yu int result, nr_io_queues; 210497f6ef64SXu Yu unsigned long size; 210557dacad5SJay Sternberg 21063b6592f7SJens Axboe nr_io_queues = max_io_queues(); 2107d38e9f04SBenjamin Herrenschmidt 2108d38e9f04SBenjamin Herrenschmidt /* 2109d38e9f04SBenjamin Herrenschmidt * If tags are shared with admin queue (Apple bug), then 2110d38e9f04SBenjamin Herrenschmidt * make sure we only use one IO queue. 2111d38e9f04SBenjamin Herrenschmidt */ 2112d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2113d38e9f04SBenjamin Herrenschmidt nr_io_queues = 1; 2114d38e9f04SBenjamin Herrenschmidt 21159a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21169a0be7abSChristoph Hellwig if (result < 0) 211757dacad5SJay Sternberg return result; 21189a0be7abSChristoph Hellwig 2119f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2120a5229050SKeith Busch return 0; 212157dacad5SJay Sternberg 21224e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21234e224106SChristoph Hellwig 21240f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 212557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 212657dacad5SJay Sternberg sizeof(struct nvme_command)); 212757dacad5SJay Sternberg if (result > 0) 212857dacad5SJay Sternberg dev->q_depth = result; 212957dacad5SJay Sternberg else 21300f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 213157dacad5SJay Sternberg } 213257dacad5SJay Sternberg 213357dacad5SJay Sternberg do { 213497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 213597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 213697f6ef64SXu Yu if (!result) 213757dacad5SJay Sternberg break; 213857dacad5SJay Sternberg if (!--nr_io_queues) 213957dacad5SJay Sternberg return -ENOMEM; 214057dacad5SJay Sternberg } while (1); 214157dacad5SJay Sternberg adminq->q_db = dev->dbs; 214257dacad5SJay Sternberg 21438fae268bSKeith Busch retry: 214457dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21450ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 214657dacad5SJay Sternberg 214757dacad5SJay Sternberg /* 214857dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 214957dacad5SJay Sternberg * setting up the full range we need. 215057dacad5SJay Sternberg */ 2151dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21523b6592f7SJens Axboe 21533b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 215422b55601SKeith Busch if (result <= 0) 2155dca51e78SChristoph Hellwig return -EIO; 21563b6592f7SJens Axboe 215722b55601SKeith Busch dev->num_vecs = result; 21584b04cc6aSJens Axboe result = max(result - 1, 1); 2159e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 216057dacad5SJay Sternberg 216157dacad5SJay Sternberg /* 216257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 216357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 216457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 216557dacad5SJay Sternberg * number of interrupts. 216657dacad5SJay Sternberg */ 2167dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21687c349ddeSKeith Busch if (result) 2169d4875622SKeith Busch return result; 21704e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21718fae268bSKeith Busch 21728fae268bSKeith Busch result = nvme_create_io_queues(dev); 21738fae268bSKeith Busch if (result || dev->online_queues < 2) 21748fae268bSKeith Busch return result; 21758fae268bSKeith Busch 21768fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21778fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21788fae268bSKeith Busch nvme_disable_io_queues(dev); 21798fae268bSKeith Busch nvme_suspend_io_queues(dev); 21808fae268bSKeith Busch goto retry; 21818fae268bSKeith Busch } 21828fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21838fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21848fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21858fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21868fae268bSKeith Busch return 0; 218757dacad5SJay Sternberg } 218857dacad5SJay Sternberg 21892a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2190db3cbfffSKeith Busch { 2191db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2192db3cbfffSKeith Busch 2193db3cbfffSKeith Busch blk_mq_free_request(req); 2194d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2195db3cbfffSKeith Busch } 2196db3cbfffSKeith Busch 21972a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2198db3cbfffSKeith Busch { 2199db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2200db3cbfffSKeith Busch 2201d1ed6aa1SChristoph Hellwig if (error) 2202d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2203db3cbfffSKeith Busch 2204db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2205db3cbfffSKeith Busch } 2206db3cbfffSKeith Busch 2207db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2208db3cbfffSKeith Busch { 2209db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2210db3cbfffSKeith Busch struct request *req; 2211db3cbfffSKeith Busch struct nvme_command cmd; 2212db3cbfffSKeith Busch 2213db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2214db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2215db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2216db3cbfffSKeith Busch 2217eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2218db3cbfffSKeith Busch if (IS_ERR(req)) 2219db3cbfffSKeith Busch return PTR_ERR(req); 2220db3cbfffSKeith Busch 2221db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2222db3cbfffSKeith Busch req->end_io_data = nvmeq; 2223db3cbfffSKeith Busch 2224d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2225db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2226db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2227db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2228db3cbfffSKeith Busch return 0; 2229db3cbfffSKeith Busch } 2230db3cbfffSKeith Busch 22318fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2232db3cbfffSKeith Busch { 22335271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2234db3cbfffSKeith Busch unsigned long timeout; 2235db3cbfffSKeith Busch 2236db3cbfffSKeith Busch retry: 2237db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22385271edd4SChristoph Hellwig while (nr_queues > 0) { 22395271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2240db3cbfffSKeith Busch break; 22415271edd4SChristoph Hellwig nr_queues--; 22425271edd4SChristoph Hellwig sent++; 22435271edd4SChristoph Hellwig } 2244d1ed6aa1SChristoph Hellwig while (sent) { 2245d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2246d1ed6aa1SChristoph Hellwig 2247d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22485271edd4SChristoph Hellwig timeout); 2249db3cbfffSKeith Busch if (timeout == 0) 22505271edd4SChristoph Hellwig return false; 2251d1ed6aa1SChristoph Hellwig 2252d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2253d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2254d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2255d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2256d1ed6aa1SChristoph Hellwig 2257d1ed6aa1SChristoph Hellwig sent--; 22585271edd4SChristoph Hellwig if (nr_queues) 2259db3cbfffSKeith Busch goto retry; 2260db3cbfffSKeith Busch } 22615271edd4SChristoph Hellwig return true; 2262db3cbfffSKeith Busch } 2263db3cbfffSKeith Busch 226457dacad5SJay Sternberg /* 22652b1b7e78SJianchao Wang * return error value only when tagset allocation failed 226657dacad5SJay Sternberg */ 226757dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 226857dacad5SJay Sternberg { 22692b1b7e78SJianchao Wang int ret; 22702b1b7e78SJianchao Wang 22715bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2272c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 227357dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22748fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2275ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2276ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 227757dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 227857dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 227957dacad5SJay Sternberg dev->tagset.queue_depth = 228057dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2281d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 228257dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 228357dacad5SJay Sternberg dev->tagset.driver_data = dev; 228457dacad5SJay Sternberg 2285d38e9f04SBenjamin Herrenschmidt /* 2286d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2287d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2288d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2289d38e9f04SBenjamin Herrenschmidt */ 2290d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2291d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2292d38e9f04SBenjamin Herrenschmidt 22932b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22942b1b7e78SJianchao Wang if (ret) { 22952b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22962b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22972b1b7e78SJianchao Wang return ret; 22982b1b7e78SJianchao Wang } 22995bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2300949928c1SKeith Busch } else { 2301949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2302949928c1SKeith Busch 2303949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2304949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 230557dacad5SJay Sternberg } 2306949928c1SKeith Busch 2307e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 230857dacad5SJay Sternberg return 0; 230957dacad5SJay Sternberg } 231057dacad5SJay Sternberg 2311b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 231257dacad5SJay Sternberg { 2313b00a726aSKeith Busch int result = -ENOMEM; 231457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 231557dacad5SJay Sternberg 231657dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 231757dacad5SJay Sternberg return result; 231857dacad5SJay Sternberg 231957dacad5SJay Sternberg pci_set_master(pdev); 232057dacad5SJay Sternberg 23214fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 232257dacad5SJay Sternberg goto disable; 232357dacad5SJay Sternberg 23247a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 232557dacad5SJay Sternberg result = -ENODEV; 2326b00a726aSKeith Busch goto disable; 232757dacad5SJay Sternberg } 232857dacad5SJay Sternberg 232957dacad5SJay Sternberg /* 2330a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2331a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2332a5229050SKeith Busch * adjust this later. 233357dacad5SJay Sternberg */ 2334dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2335dca51e78SChristoph Hellwig if (result < 0) 2336dca51e78SChristoph Hellwig return result; 233757dacad5SJay Sternberg 233820d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23397a67cbeaSChristoph Hellwig 234020d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2341b27c1e68Sweiping zhang io_queue_depth); 2342aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 234320d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23447a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23451f390c1fSStephan Günther 23461f390c1fSStephan Günther /* 234766341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 234866341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 234966341331SBenjamin Herrenschmidt * so we don't bother updating it here. 235066341331SBenjamin Herrenschmidt */ 235166341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 235266341331SBenjamin Herrenschmidt dev->io_sqes = 7; 235366341331SBenjamin Herrenschmidt else 2354c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 23551f390c1fSStephan Günther 23561f390c1fSStephan Günther /* 23571f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23581f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23591f390c1fSStephan Günther */ 23601f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23611f390c1fSStephan Günther dev->q_depth = 2; 23629bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23639bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23641f390c1fSStephan Günther dev->q_depth); 2365d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2366d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 236720d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2368d554b5e1SMartin K. Petersen dev->q_depth = 64; 2369d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2370d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23711f390c1fSStephan Günther } 23721f390c1fSStephan Günther 2373d38e9f04SBenjamin Herrenschmidt /* 2374d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2375d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2376d38e9f04SBenjamin Herrenschmidt */ 2377d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2378d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2379d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2380d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2381d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2382d38e9f04SBenjamin Herrenschmidt } 2383d38e9f04SBenjamin Herrenschmidt 2384d38e9f04SBenjamin Herrenschmidt 2385f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2386202021c1SStephen Bates 2387a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2388a0a3408eSKeith Busch pci_save_state(pdev); 238957dacad5SJay Sternberg return 0; 239057dacad5SJay Sternberg 239157dacad5SJay Sternberg disable: 239257dacad5SJay Sternberg pci_disable_device(pdev); 239357dacad5SJay Sternberg return result; 239457dacad5SJay Sternberg } 239557dacad5SJay Sternberg 239657dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 239757dacad5SJay Sternberg { 2398b00a726aSKeith Busch if (dev->bar) 2399b00a726aSKeith Busch iounmap(dev->bar); 2400a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2401b00a726aSKeith Busch } 2402b00a726aSKeith Busch 2403b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2404b00a726aSKeith Busch { 240557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 240657dacad5SJay Sternberg 2407dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 240857dacad5SJay Sternberg 2409a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2410a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 241157dacad5SJay Sternberg pci_disable_device(pdev); 241257dacad5SJay Sternberg } 2413a0a3408eSKeith Busch } 241457dacad5SJay Sternberg 2415a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 241657dacad5SJay Sternberg { 2417e43269e6SKeith Busch bool dead = true, freeze = false; 2418302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 241957dacad5SJay Sternberg 242077bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2421302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2422302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2423302ad8ccSKeith Busch 2424ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2425e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2426e43269e6SKeith Busch freeze = true; 2427302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2428e43269e6SKeith Busch } 2429302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2430302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 243157dacad5SJay Sternberg } 2432c21377f8SGabriel Krisman Bertazi 2433302ad8ccSKeith Busch /* 2434302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2435302ad8ccSKeith Busch * doing a safe shutdown. 2436302ad8ccSKeith Busch */ 2437e43269e6SKeith Busch if (!dead && shutdown && freeze) 2438302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 243987ad72a5SChristoph Hellwig 24409a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24419a915a5bSJianchao Wang 244264ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24438fae268bSKeith Busch nvme_disable_io_queues(dev); 2444a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 244557dacad5SJay Sternberg } 24468fae268bSKeith Busch nvme_suspend_io_queues(dev); 24478fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2448b00a726aSKeith Busch nvme_pci_disable(dev); 244957dacad5SJay Sternberg 2450e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2451e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2452622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2453622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2454302ad8ccSKeith Busch 2455302ad8ccSKeith Busch /* 2456302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2457302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2458302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2459302ad8ccSKeith Busch */ 2460c8e9e9b7SKeith Busch if (shutdown) { 2461302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2462c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2463c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2464c8e9e9b7SKeith Busch } 246577bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 246657dacad5SJay Sternberg } 246757dacad5SJay Sternberg 246857dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 246957dacad5SJay Sternberg { 247057dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 247157dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 247257dacad5SJay Sternberg if (!dev->prp_page_pool) 247357dacad5SJay Sternberg return -ENOMEM; 247457dacad5SJay Sternberg 247557dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 247657dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 247757dacad5SJay Sternberg 256, 256, 0); 247857dacad5SJay Sternberg if (!dev->prp_small_pool) { 247957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248057dacad5SJay Sternberg return -ENOMEM; 248157dacad5SJay Sternberg } 248257dacad5SJay Sternberg return 0; 248357dacad5SJay Sternberg } 248457dacad5SJay Sternberg 248557dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 248657dacad5SJay Sternberg { 248757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248857dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 248957dacad5SJay Sternberg } 249057dacad5SJay Sternberg 24911673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 249257dacad5SJay Sternberg { 24931673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 249457dacad5SJay Sternberg 2495f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 249657dacad5SJay Sternberg put_device(dev->dev); 249757dacad5SJay Sternberg if (dev->tagset.tags) 249857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24991c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 25001c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 250157dacad5SJay Sternberg kfree(dev->queues); 2502e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2503943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 250457dacad5SJay Sternberg kfree(dev); 250557dacad5SJay Sternberg } 250657dacad5SJay Sternberg 25077c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2508f58944e2SKeith Busch { 2509d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 251069d9a99cSKeith Busch nvme_dev_disable(dev, false); 25119f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 251203e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2513f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2514f58944e2SKeith Busch } 2515f58944e2SKeith Busch 2516fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 251757dacad5SJay Sternberg { 2518d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2519d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2520a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2521e71afda4SChaitanya Kulkarni int result; 25222b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 252357dacad5SJay Sternberg 2524e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2525e71afda4SChaitanya Kulkarni result = -ENODEV; 2526fd634f41SChristoph Hellwig goto out; 2527e71afda4SChaitanya Kulkarni } 2528fd634f41SChristoph Hellwig 2529fd634f41SChristoph Hellwig /* 2530fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2531fd634f41SChristoph Hellwig * moving on. 2532fd634f41SChristoph Hellwig */ 2533b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2534a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2535d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2536fd634f41SChristoph Hellwig 25375c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2538b00a726aSKeith Busch result = nvme_pci_enable(dev); 253957dacad5SJay Sternberg if (result) 25404726bcf3SKeith Busch goto out_unlock; 254157dacad5SJay Sternberg 254201ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 254357dacad5SJay Sternberg if (result) 25444726bcf3SKeith Busch goto out_unlock; 254557dacad5SJay Sternberg 254657dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 254757dacad5SJay Sternberg if (result) 25484726bcf3SKeith Busch goto out_unlock; 254957dacad5SJay Sternberg 2550943e942eSJens Axboe /* 2551943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2552943e942eSJens Axboe * over a single page. 2553943e942eSJens Axboe */ 25547637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 25557637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2556943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2557a48bc520SChristoph Hellwig 2558a48bc520SChristoph Hellwig /* 2559a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2560a48bc520SChristoph Hellwig */ 2561a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2562a48bc520SChristoph Hellwig 25635c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25645c959d73SKeith Busch 25655c959d73SKeith Busch /* 25665c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25675c959d73SKeith Busch * initializing procedure here. 25685c959d73SKeith Busch */ 25695c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25705c959d73SKeith Busch dev_warn(dev->ctrl.device, 25715c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2572cee6c269SMinwoo Im result = -EBUSY; 25735c959d73SKeith Busch goto out; 25745c959d73SKeith Busch } 2575943e942eSJens Axboe 2576ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2577ce4541f4SChristoph Hellwig if (result) 2578f58944e2SKeith Busch goto out; 2579ce4541f4SChristoph Hellwig 2580e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2581e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25824f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25834f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2584e286bcfcSScott Bauer else if (was_suspend) 25854f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2586e286bcfcSScott Bauer } else { 2587e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2588e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2589e286bcfcSScott Bauer } 2590a98e58e5SScott Bauer 2591f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2592f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2593f9f38e33SHelen Koike if (result) 2594f9f38e33SHelen Koike dev_warn(dev->dev, 2595f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2596f9f38e33SHelen Koike } 2597f9f38e33SHelen Koike 25989620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25999620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26009620cfbaSChristoph Hellwig if (result < 0) 26019620cfbaSChristoph Hellwig goto out; 26029620cfbaSChristoph Hellwig } 260387ad72a5SChristoph Hellwig 260457dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 260557dacad5SJay Sternberg if (result) 2606f58944e2SKeith Busch goto out; 260757dacad5SJay Sternberg 260821f033f7SKeith Busch /* 260957dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 261057dacad5SJay Sternberg * any working I/O queue. 261157dacad5SJay Sternberg */ 261257dacad5SJay Sternberg if (dev->online_queues < 2) { 26131b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26143b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26155bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 26162b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 261757dacad5SJay Sternberg } else { 261825646264SKeith Busch nvme_start_queues(&dev->ctrl); 2619302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26202b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 26212b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 26222b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2623302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 262457dacad5SJay Sternberg } 262557dacad5SJay Sternberg 26262b1b7e78SJianchao Wang /* 26272b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26282b1b7e78SJianchao Wang * recovery. 26292b1b7e78SJianchao Wang */ 26302b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 26312b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26322b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2633e71afda4SChaitanya Kulkarni result = -ENODEV; 2634bb8d261eSChristoph Hellwig goto out; 2635bb8d261eSChristoph Hellwig } 263692911a55SChristoph Hellwig 2637d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 263857dacad5SJay Sternberg return; 263957dacad5SJay Sternberg 26404726bcf3SKeith Busch out_unlock: 26414726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 264257dacad5SJay Sternberg out: 26437c1ce408SChaitanya Kulkarni if (result) 26447c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 26457c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 26467c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 264757dacad5SJay Sternberg } 264857dacad5SJay Sternberg 26495c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 265057dacad5SJay Sternberg { 26515c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 265257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 265357dacad5SJay Sternberg 265457dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2655921920abSKeith Busch device_release_driver(&pdev->dev); 26561673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 265757dacad5SJay Sternberg } 265857dacad5SJay Sternberg 26591c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 266057dacad5SJay Sternberg { 26611c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26621c63dc66SChristoph Hellwig return 0; 266357dacad5SJay Sternberg } 26641c63dc66SChristoph Hellwig 26655fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26665fd4ce1bSChristoph Hellwig { 26675fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26685fd4ce1bSChristoph Hellwig return 0; 26695fd4ce1bSChristoph Hellwig } 26705fd4ce1bSChristoph Hellwig 26717fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26727fd8930fSChristoph Hellwig { 26737fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26747fd8930fSChristoph Hellwig return 0; 26757fd8930fSChristoph Hellwig } 26767fd8930fSChristoph Hellwig 267797c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 267897c12223SKeith Busch { 267997c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 268097c12223SKeith Busch 268197c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 268297c12223SKeith Busch } 268397c12223SKeith Busch 26841c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26851a353d85SMing Lin .name = "pcie", 2686e439bb12SSagi Grimberg .module = THIS_MODULE, 2687e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2688e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26891c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26905fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26917fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26921673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2693f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 269497c12223SKeith Busch .get_address = nvme_pci_get_address, 26951c63dc66SChristoph Hellwig }; 269657dacad5SJay Sternberg 2697b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2698b00a726aSKeith Busch { 2699b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2700b00a726aSKeith Busch 2701a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2702b00a726aSKeith Busch return -ENODEV; 2703b00a726aSKeith Busch 270497f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2705b00a726aSKeith Busch goto release; 2706b00a726aSKeith Busch 2707b00a726aSKeith Busch return 0; 2708b00a726aSKeith Busch release: 2709a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2710b00a726aSKeith Busch return -ENODEV; 2711b00a726aSKeith Busch } 2712b00a726aSKeith Busch 27138427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2714ff5350a8SAndy Lutomirski { 2715ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2716ff5350a8SAndy Lutomirski /* 2717ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2718ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2719ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2720ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2721ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2722ff5350a8SAndy Lutomirski * laptops. 2723ff5350a8SAndy Lutomirski */ 2724ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2725ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2726ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2727ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27288427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27298427bbc2SKai-Heng Feng /* 27308427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2731467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2732467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2733467c77d4SJarosław Janik * ASUS PRIME Z370-A 27348427bbc2SKai-Heng Feng */ 27358427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2736467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2737467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27388427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2739ff5350a8SAndy Lutomirski } 2740ff5350a8SAndy Lutomirski 2741ff5350a8SAndy Lutomirski return 0; 2742ff5350a8SAndy Lutomirski } 2743ff5350a8SAndy Lutomirski 274418119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 274518119775SKeith Busch { 274618119775SKeith Busch struct nvme_dev *dev = data; 274780f513b5SKeith Busch 2748bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 274918119775SKeith Busch flush_work(&dev->ctrl.scan_work); 275080f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 275118119775SKeith Busch } 275218119775SKeith Busch 275357dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 275457dacad5SJay Sternberg { 275557dacad5SJay Sternberg int node, result = -ENOMEM; 275657dacad5SJay Sternberg struct nvme_dev *dev; 2757ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2758943e942eSJens Axboe size_t alloc_size; 275957dacad5SJay Sternberg 276057dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 276157dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27622fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 276357dacad5SJay Sternberg 276457dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 276557dacad5SJay Sternberg if (!dev) 276657dacad5SJay Sternberg return -ENOMEM; 2767147b27e4SSagi Grimberg 27683b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27693b6592f7SJens Axboe GFP_KERNEL, node); 277057dacad5SJay Sternberg if (!dev->queues) 277157dacad5SJay Sternberg goto free; 277257dacad5SJay Sternberg 277357dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 277457dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 277557dacad5SJay Sternberg 2776b00a726aSKeith Busch result = nvme_dev_map(dev); 2777b00a726aSKeith Busch if (result) 2778b00c9b7aSChristophe JAILLET goto put_pci; 2779b00a726aSKeith Busch 2780d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27815c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 278277bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2783f3ca80fcSChristoph Hellwig 2784f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2785f3ca80fcSChristoph Hellwig if (result) 2786b00c9b7aSChristophe JAILLET goto unmap; 2787f3ca80fcSChristoph Hellwig 27888427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2789ff5350a8SAndy Lutomirski 2790943e942eSJens Axboe /* 2791943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2792943e942eSJens Axboe * command we support. 2793943e942eSJens Axboe */ 2794943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2795943e942eSJens Axboe NVME_MAX_SEGS, true); 2796943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2797943e942eSJens Axboe 2798943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2799943e942eSJens Axboe mempool_kfree, 2800943e942eSJens Axboe (void *) alloc_size, 2801943e942eSJens Axboe GFP_KERNEL, node); 2802943e942eSJens Axboe if (!dev->iod_mempool) { 2803943e942eSJens Axboe result = -ENOMEM; 2804943e942eSJens Axboe goto release_pools; 2805943e942eSJens Axboe } 2806943e942eSJens Axboe 2807b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2808b6e44b4cSKeith Busch quirks); 2809b6e44b4cSKeith Busch if (result) 2810b6e44b4cSKeith Busch goto release_mempool; 2811b6e44b4cSKeith Busch 28121b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 28131b3c47c1SSagi Grimberg 2814bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 281580f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 281618119775SKeith Busch async_schedule(nvme_async_probe, dev); 28174caff8fcSSagi Grimberg 281857dacad5SJay Sternberg return 0; 281957dacad5SJay Sternberg 2820b6e44b4cSKeith Busch release_mempool: 2821b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 282257dacad5SJay Sternberg release_pools: 282357dacad5SJay Sternberg nvme_release_prp_pools(dev); 2824b00c9b7aSChristophe JAILLET unmap: 2825b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 282657dacad5SJay Sternberg put_pci: 282757dacad5SJay Sternberg put_device(dev->dev); 282857dacad5SJay Sternberg free: 282957dacad5SJay Sternberg kfree(dev->queues); 283057dacad5SJay Sternberg kfree(dev); 283157dacad5SJay Sternberg return result; 283257dacad5SJay Sternberg } 283357dacad5SJay Sternberg 2834775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 283557dacad5SJay Sternberg { 283657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2837a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2838775755edSChristoph Hellwig } 283957dacad5SJay Sternberg 2840775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2841775755edSChristoph Hellwig { 2842f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 284379c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 284457dacad5SJay Sternberg } 284557dacad5SJay Sternberg 284657dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 284757dacad5SJay Sternberg { 284857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2849a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 285057dacad5SJay Sternberg } 285157dacad5SJay Sternberg 2852f58944e2SKeith Busch /* 2853f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2854f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2855f58944e2SKeith Busch * order to proceed. 2856f58944e2SKeith Busch */ 285757dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 285857dacad5SJay Sternberg { 285957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 286057dacad5SJay Sternberg 2861bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 286257dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28630ff9d4e1SKeith Busch 28646db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28650ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28661d39e692SKeith Busch nvme_dev_disable(dev, true); 2867cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28686db28edaSKeith Busch } 28690ff9d4e1SKeith Busch 2870d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2871d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2872d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2873a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28749fe5c59fSKeith Busch nvme_release_cmb(dev); 287587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 287657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 287757dacad5SJay Sternberg nvme_free_queues(dev, 0); 2878d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 287957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2880b00a726aSKeith Busch nvme_dev_unmap(dev); 28811673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 288257dacad5SJay Sternberg } 288357dacad5SJay Sternberg 288457dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2885d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2886d916b1beSKeith Busch { 2887d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2888d916b1beSKeith Busch } 2889d916b1beSKeith Busch 2890d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2891d916b1beSKeith Busch { 2892d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2893d916b1beSKeith Busch } 2894d916b1beSKeith Busch 2895d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2896d916b1beSKeith Busch { 2897d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2898d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2899d916b1beSKeith Busch 29004eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 2901d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2902d916b1beSKeith Busch nvme_reset_ctrl(ctrl); 2903d916b1beSKeith Busch return 0; 2904d916b1beSKeith Busch } 2905d916b1beSKeith Busch 290657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 290757dacad5SJay Sternberg { 290857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 290957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2910d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2911d916b1beSKeith Busch int ret = -EBUSY; 2912d916b1beSKeith Busch 29134eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 29144eaefe8cSRafael J. Wysocki 2915d916b1beSKeith Busch /* 2916d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 2917d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 2918d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 2919d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 2920d916b1beSKeith Busch * device does not support any non-default power states, shut down the 2921d916b1beSKeith Busch * device fully. 29224eaefe8cSRafael J. Wysocki * 29234eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 29244eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 29254eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 29264eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 2927d916b1beSKeith Busch */ 29284eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 2929cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 2930cb32de1bSMario Limonciello (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) { 2931d916b1beSKeith Busch nvme_dev_disable(ndev, true); 2932d916b1beSKeith Busch return 0; 2933d916b1beSKeith Busch } 2934d916b1beSKeith Busch 2935d916b1beSKeith Busch nvme_start_freeze(ctrl); 2936d916b1beSKeith Busch nvme_wait_freeze(ctrl); 2937d916b1beSKeith Busch nvme_sync_queues(ctrl); 2938d916b1beSKeith Busch 2939d916b1beSKeith Busch if (ctrl->state != NVME_CTRL_LIVE && 2940d916b1beSKeith Busch ctrl->state != NVME_CTRL_ADMIN_ONLY) 2941d916b1beSKeith Busch goto unfreeze; 2942d916b1beSKeith Busch 2943d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2944d916b1beSKeith Busch if (ret < 0) 2945d916b1beSKeith Busch goto unfreeze; 2946d916b1beSKeith Busch 29477cbb5c6fSMario Limonciello /* 29487cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 29497cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 29507cbb5c6fSMario Limonciello * want pci interfering. 29517cbb5c6fSMario Limonciello */ 29527cbb5c6fSMario Limonciello pci_save_state(pdev); 29537cbb5c6fSMario Limonciello 2954d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 2955d916b1beSKeith Busch if (ret < 0) 2956d916b1beSKeith Busch goto unfreeze; 2957d916b1beSKeith Busch 2958d916b1beSKeith Busch if (ret) { 29597cbb5c6fSMario Limonciello /* discard the saved state */ 29607cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 29617cbb5c6fSMario Limonciello 2962d916b1beSKeith Busch /* 2963d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 2964d916b1beSKeith Busch * correct value will be resdicovered then. 2965d916b1beSKeith Busch */ 2966d916b1beSKeith Busch nvme_dev_disable(ndev, true); 2967d916b1beSKeith Busch ctrl->npss = 0; 2968d916b1beSKeith Busch ret = 0; 2969d916b1beSKeith Busch } 2970d916b1beSKeith Busch unfreeze: 2971d916b1beSKeith Busch nvme_unfreeze(ctrl); 2972d916b1beSKeith Busch return ret; 2973d916b1beSKeith Busch } 2974d916b1beSKeith Busch 2975d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 2976d916b1beSKeith Busch { 2977d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 297857dacad5SJay Sternberg 2979a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 298057dacad5SJay Sternberg return 0; 298157dacad5SJay Sternberg } 298257dacad5SJay Sternberg 2983d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 298457dacad5SJay Sternberg { 298557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 298657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 298757dacad5SJay Sternberg 2988d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 298957dacad5SJay Sternberg return 0; 299057dacad5SJay Sternberg } 299157dacad5SJay Sternberg 299221774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 2993d916b1beSKeith Busch .suspend = nvme_suspend, 2994d916b1beSKeith Busch .resume = nvme_resume, 2995d916b1beSKeith Busch .freeze = nvme_simple_suspend, 2996d916b1beSKeith Busch .thaw = nvme_simple_resume, 2997d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 2998d916b1beSKeith Busch .restore = nvme_simple_resume, 2999d916b1beSKeith Busch }; 3000d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 300157dacad5SJay Sternberg 3002a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3003a0a3408eSKeith Busch pci_channel_state_t state) 3004a0a3408eSKeith Busch { 3005a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3006a0a3408eSKeith Busch 3007a0a3408eSKeith Busch /* 3008a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3009a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3010a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3011a0a3408eSKeith Busch */ 3012a0a3408eSKeith Busch switch (state) { 3013a0a3408eSKeith Busch case pci_channel_io_normal: 3014a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3015a0a3408eSKeith Busch case pci_channel_io_frozen: 3016d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3017d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3018a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3019a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3020a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3021d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3022d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3023a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3024a0a3408eSKeith Busch } 3025a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3026a0a3408eSKeith Busch } 3027a0a3408eSKeith Busch 3028a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3029a0a3408eSKeith Busch { 3030a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3031a0a3408eSKeith Busch 30321b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3033a0a3408eSKeith Busch pci_restore_state(pdev); 3034d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3035a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3036a0a3408eSKeith Busch } 3037a0a3408eSKeith Busch 3038a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3039a0a3408eSKeith Busch { 304072cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 304172cd4cc2SKeith Busch 304272cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3043a0a3408eSKeith Busch } 3044a0a3408eSKeith Busch 304557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 304657dacad5SJay Sternberg .error_detected = nvme_error_detected, 304757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 304857dacad5SJay Sternberg .resume = nvme_error_resume, 3049775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3050775755edSChristoph Hellwig .reset_done = nvme_reset_done, 305157dacad5SJay Sternberg }; 305257dacad5SJay Sternberg 305357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3054106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 305508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3056e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 305799466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 305899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3059e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 306099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 306199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3062e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3063f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 3064f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3065f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 306650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 30679abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 30689abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 30696299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 30706299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3071540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 30727b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 30737b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 30740302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 30750302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 307654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 307754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 30788c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 30798c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3080015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3081015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3082d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3083d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3084d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3085d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3086608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3087608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3088608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3089608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3090ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3091ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 309208b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 309308b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3094f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3095f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3096f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 309757dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3098c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3099124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 310066341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 310166341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3102d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3103d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 310457dacad5SJay Sternberg { 0, } 310557dacad5SJay Sternberg }; 310657dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 310757dacad5SJay Sternberg 310857dacad5SJay Sternberg static struct pci_driver nvme_driver = { 310957dacad5SJay Sternberg .name = "nvme", 311057dacad5SJay Sternberg .id_table = nvme_id_table, 311157dacad5SJay Sternberg .probe = nvme_probe, 311257dacad5SJay Sternberg .remove = nvme_remove, 311357dacad5SJay Sternberg .shutdown = nvme_shutdown, 3114d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 311557dacad5SJay Sternberg .driver = { 311657dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 311757dacad5SJay Sternberg }, 3118d916b1beSKeith Busch #endif 311974d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 312057dacad5SJay Sternberg .err_handler = &nvme_err_handler, 312157dacad5SJay Sternberg }; 312257dacad5SJay Sternberg 312357dacad5SJay Sternberg static int __init nvme_init(void) 312457dacad5SJay Sternberg { 312581101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 312681101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 312781101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3128612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 31299a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 313057dacad5SJay Sternberg } 313157dacad5SJay Sternberg 313257dacad5SJay Sternberg static void __exit nvme_exit(void) 313357dacad5SJay Sternberg { 313457dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 313503e0f3a6SMing Lei flush_workqueue(nvme_wq); 313657dacad5SJay Sternberg } 313757dacad5SJay Sternberg 313857dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 313957dacad5SJay Sternberg MODULE_LICENSE("GPL"); 314057dacad5SJay Sternberg MODULE_VERSION("1.0"); 314157dacad5SJay Sternberg module_init(nvme_init); 314257dacad5SJay Sternberg module_exit(nvme_exit); 3143