15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 21d916b1beSKeith Busch #include <linux/suspend.h> 2257dacad5SJay Sternberg #include <linux/t10-pi.h> 2357dacad5SJay Sternberg #include <linux/types.h> 249cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 25a98e58e5SScott Bauer #include <linux/sed-opal.h> 260f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2757dacad5SJay Sternberg 28604c01d5Syupeng #include "trace.h" 2957dacad5SJay Sternberg #include "nvme.h" 3057dacad5SJay Sternberg 31c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 328a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3357dacad5SJay Sternberg 34a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35adf68f21SChristoph Hellwig 36943e942eSJens Axboe /* 37943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 38943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 39943e942eSJens Axboe */ 40943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 41943e942eSJens Axboe #define NVME_MAX_SEGS 127 42943e942eSJens Axboe 4357dacad5SJay Sternberg static int use_threaded_interrupts; 4457dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4557dacad5SJay Sternberg 4657dacad5SJay Sternberg static bool use_cmb_sqes = true; 4769f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4857dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4957dacad5SJay Sternberg 5087ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5187ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5287ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5387ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5457dacad5SJay Sternberg 55a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 56a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 57a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 58a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 59a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 60a7a7cbe3SChaitanya Kulkarni 61b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 63b27c1e68Sweiping zhang .set = io_queue_depth_set, 64b27c1e68Sweiping zhang .get = param_get_int, 65b27c1e68Sweiping zhang }; 66b27c1e68Sweiping zhang 67b27c1e68Sweiping zhang static int io_queue_depth = 1024; 68b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70b27c1e68Sweiping zhang 713f68baf7SKeith Busch static unsigned int write_queues; 723f68baf7SKeith Busch module_param(write_queues, uint, 0644); 733b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 743b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 753b6592f7SJens Axboe "will share a queue set."); 763b6592f7SJens Axboe 773f68baf7SKeith Busch static unsigned int poll_queues; 783f68baf7SKeith Busch module_param(poll_queues, uint, 0644); 794b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 804b04cc6aSJens Axboe 811c63dc66SChristoph Hellwig struct nvme_dev; 821c63dc66SChristoph Hellwig struct nvme_queue; 8357dacad5SJay Sternberg 84a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 858fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 8657dacad5SJay Sternberg 8757dacad5SJay Sternberg /* 881c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 891c63dc66SChristoph Hellwig */ 901c63dc66SChristoph Hellwig struct nvme_dev { 91147b27e4SSagi Grimberg struct nvme_queue *queues; 921c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 931c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 941c63dc66SChristoph Hellwig u32 __iomem *dbs; 951c63dc66SChristoph Hellwig struct device *dev; 961c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 971c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 981c63dc66SChristoph Hellwig unsigned online_queues; 991c63dc66SChristoph Hellwig unsigned max_qid; 100e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10122b55601SKeith Busch unsigned int num_vecs; 1021c63dc66SChristoph Hellwig int q_depth; 103c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1041c63dc66SChristoph Hellwig u32 db_stride; 1051c63dc66SChristoph Hellwig void __iomem *bar; 10697f6ef64SXu Yu unsigned long bar_mapped_size; 1075c8809e6SChristoph Hellwig struct work_struct remove_work; 10877bf25eaSKeith Busch struct mutex shutdown_lock; 1091c63dc66SChristoph Hellwig bool subsystem; 1101c63dc66SChristoph Hellwig u64 cmb_size; 1110f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1121c63dc66SChristoph Hellwig u32 cmbsz; 113202021c1SStephen Bates u32 cmbloc; 1141c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 115d916b1beSKeith Busch u32 last_ps; 11687ad72a5SChristoph Hellwig 117943e942eSJens Axboe mempool_t *iod_mempool; 118943e942eSJens Axboe 11987ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 120f9f38e33SHelen Koike u32 *dbbuf_dbs; 121f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 122f9f38e33SHelen Koike u32 *dbbuf_eis; 123f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12487ad72a5SChristoph Hellwig 12587ad72a5SChristoph Hellwig /* host memory buffer support: */ 12687ad72a5SChristoph Hellwig u64 host_mem_size; 12787ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1284033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13087ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13157dacad5SJay Sternberg }; 13257dacad5SJay Sternberg 133b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 134b27c1e68Sweiping zhang { 135b27c1e68Sweiping zhang int n = 0, ret; 136b27c1e68Sweiping zhang 137b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 138b27c1e68Sweiping zhang if (ret != 0 || n < 2) 139b27c1e68Sweiping zhang return -EINVAL; 140b27c1e68Sweiping zhang 141b27c1e68Sweiping zhang return param_set_int(val, kp); 142b27c1e68Sweiping zhang } 143b27c1e68Sweiping zhang 144f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 145f9f38e33SHelen Koike { 146f9f38e33SHelen Koike return qid * 2 * stride; 147f9f38e33SHelen Koike } 148f9f38e33SHelen Koike 149f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 150f9f38e33SHelen Koike { 151f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 152f9f38e33SHelen Koike } 153f9f38e33SHelen Koike 1541c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1551c63dc66SChristoph Hellwig { 1561c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1571c63dc66SChristoph Hellwig } 1581c63dc66SChristoph Hellwig 15957dacad5SJay Sternberg /* 16057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 16157dacad5SJay Sternberg * commands and one for I/O commands). 16257dacad5SJay Sternberg */ 16357dacad5SJay Sternberg struct nvme_queue { 16457dacad5SJay Sternberg struct nvme_dev *dev; 1651ab0cd69SJens Axboe spinlock_t sq_lock; 166c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1673a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1683a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 16957dacad5SJay Sternberg volatile struct nvme_completion *cqes; 17057dacad5SJay Sternberg dma_addr_t sq_dma_addr; 17157dacad5SJay Sternberg dma_addr_t cq_dma_addr; 17257dacad5SJay Sternberg u32 __iomem *q_db; 17357dacad5SJay Sternberg u16 q_depth; 1747c349ddeSKeith Busch u16 cq_vector; 17557dacad5SJay Sternberg u16 sq_tail; 17604f3eafdSJens Axboe u16 last_sq_tail; 17757dacad5SJay Sternberg u16 cq_head; 17857dacad5SJay Sternberg u16 qid; 17957dacad5SJay Sternberg u8 cq_phase; 180c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 1814e224106SChristoph Hellwig unsigned long flags; 1824e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 18363223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 184d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 1857c349ddeSKeith Busch #define NVMEQ_POLLED 3 186f9f38e33SHelen Koike u32 *dbbuf_sq_db; 187f9f38e33SHelen Koike u32 *dbbuf_cq_db; 188f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 189f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 190d1ed6aa1SChristoph Hellwig struct completion delete_done; 19157dacad5SJay Sternberg }; 19257dacad5SJay Sternberg 19357dacad5SJay Sternberg /* 1949b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 1959b048119SChristoph Hellwig * 1969b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 1979b048119SChristoph Hellwig * to the actual struct scatterlist. 19871bd150cSChristoph Hellwig */ 19971bd150cSChristoph Hellwig struct nvme_iod { 200d49187e9SChristoph Hellwig struct nvme_request req; 201f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 202a7a7cbe3SChaitanya Kulkarni bool use_sgl; 203f4800d6dSChristoph Hellwig int aborted; 20471bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 20571bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 20671bd150cSChristoph Hellwig dma_addr_t first_dma; 207dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 208783b94bdSChristoph Hellwig dma_addr_t meta_dma; 209f4800d6dSChristoph Hellwig struct scatterlist *sg; 21057dacad5SJay Sternberg }; 21157dacad5SJay Sternberg 2123b6592f7SJens Axboe static unsigned int max_io_queues(void) 2133b6592f7SJens Axboe { 2144b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2153b6592f7SJens Axboe } 2163b6592f7SJens Axboe 2173b6592f7SJens Axboe static unsigned int max_queue_count(void) 2183b6592f7SJens Axboe { 2193b6592f7SJens Axboe /* IO queues + admin queue */ 2203b6592f7SJens Axboe return 1 + max_io_queues(); 2213b6592f7SJens Axboe } 2223b6592f7SJens Axboe 223f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 224f9f38e33SHelen Koike { 2253b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 226f9f38e33SHelen Koike } 227f9f38e33SHelen Koike 228f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229f9f38e33SHelen Koike { 230f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231f9f38e33SHelen Koike 232f9f38e33SHelen Koike if (dev->dbbuf_dbs) 233f9f38e33SHelen Koike return 0; 234f9f38e33SHelen Koike 235f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 237f9f38e33SHelen Koike GFP_KERNEL); 238f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 239f9f38e33SHelen Koike return -ENOMEM; 240f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 242f9f38e33SHelen Koike GFP_KERNEL); 243f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 244f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 245f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 247f9f38e33SHelen Koike return -ENOMEM; 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike 250f9f38e33SHelen Koike return 0; 251f9f38e33SHelen Koike } 252f9f38e33SHelen Koike 253f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254f9f38e33SHelen Koike { 255f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256f9f38e33SHelen Koike 257f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 258f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 261f9f38e33SHelen Koike } 262f9f38e33SHelen Koike if (dev->dbbuf_eis) { 263f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike } 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 270f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 273f9f38e33SHelen Koike return; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279f9f38e33SHelen Koike } 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 282f9f38e33SHelen Koike { 283f9f38e33SHelen Koike struct nvme_command c; 284f9f38e33SHelen Koike 285f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 286f9f38e33SHelen Koike return; 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 289f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 290f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2949bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295f9f38e33SHelen Koike /* Free memory and continue on */ 296f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 297f9f38e33SHelen Koike } 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike 300f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301f9f38e33SHelen Koike { 302f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike 305f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 306f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike if (dbbuf_db) { 310f9f38e33SHelen Koike u16 old_value; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike /* 313f9f38e33SHelen Koike * Ensure that the queue is written before updating 314f9f38e33SHelen Koike * the doorbell in memory 315f9f38e33SHelen Koike */ 316f9f38e33SHelen Koike wmb(); 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike old_value = *dbbuf_db; 319f9f38e33SHelen Koike *dbbuf_db = value; 320f9f38e33SHelen Koike 321f1ed3df2SMichal Wnukowski /* 322f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 323f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 324f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 325f1ed3df2SMichal Wnukowski * the doorbell. 326f1ed3df2SMichal Wnukowski */ 327f1ed3df2SMichal Wnukowski mb(); 328f1ed3df2SMichal Wnukowski 329f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330f9f38e33SHelen Koike return false; 331f9f38e33SHelen Koike } 332f9f38e33SHelen Koike 333f9f38e33SHelen Koike return true; 33457dacad5SJay Sternberg } 33557dacad5SJay Sternberg 33657dacad5SJay Sternberg /* 33757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 33857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 33957dacad5SJay Sternberg * the I/O. 34057dacad5SJay Sternberg */ 34157dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 34257dacad5SJay Sternberg { 3435fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3445fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 34657dacad5SJay Sternberg } 34757dacad5SJay Sternberg 348a7a7cbe3SChaitanya Kulkarni /* 349a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 350a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 351a7a7cbe3SChaitanya Kulkarni */ 352a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 353f4800d6dSChristoph Hellwig { 354a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355f4800d6dSChristoph Hellwig } 356f4800d6dSChristoph Hellwig 357a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 35957dacad5SJay Sternberg { 360a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 361a7a7cbe3SChaitanya Kulkarni 362a7a7cbe3SChaitanya Kulkarni if (use_sgl) 363a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364a7a7cbe3SChaitanya Kulkarni else 365a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366a7a7cbe3SChaitanya Kulkarni 367a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 368a7a7cbe3SChaitanya Kulkarni } 369a7a7cbe3SChaitanya Kulkarni 37057dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37157dacad5SJay Sternberg unsigned int hctx_idx) 37257dacad5SJay Sternberg { 37357dacad5SJay Sternberg struct nvme_dev *dev = data; 374147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37757dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37857dacad5SJay Sternberg 37957dacad5SJay Sternberg hctx->driver_data = nvmeq; 38057dacad5SJay Sternberg return 0; 38157dacad5SJay Sternberg } 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38457dacad5SJay Sternberg unsigned int hctx_idx) 38557dacad5SJay Sternberg { 38657dacad5SJay Sternberg struct nvme_dev *dev = data; 387147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39057dacad5SJay Sternberg hctx->driver_data = nvmeq; 39157dacad5SJay Sternberg return 0; 39257dacad5SJay Sternberg } 39357dacad5SJay Sternberg 394d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 395d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 39657dacad5SJay Sternberg { 397d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 398f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 3990350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 400147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg BUG_ON(!nvmeq); 403f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 40459e29ce6SSagi Grimberg 40559e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 40657dacad5SJay Sternberg return 0; 40757dacad5SJay Sternberg } 40857dacad5SJay Sternberg 4093b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4103b6592f7SJens Axboe { 4113b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4123b6592f7SJens Axboe if (dev->num_vecs > 1) 4133b6592f7SJens Axboe return 1; 4143b6592f7SJens Axboe 4153b6592f7SJens Axboe return 0; 4163b6592f7SJens Axboe } 4173b6592f7SJens Axboe 418dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 419dca51e78SChristoph Hellwig { 420dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4213b6592f7SJens Axboe int i, qoff, offset; 422dca51e78SChristoph Hellwig 4233b6592f7SJens Axboe offset = queue_irq_offset(dev); 4243b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4253b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4263b6592f7SJens Axboe 4273b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4283b6592f7SJens Axboe if (!map->nr_queues) { 429e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4307e849dd9SChristoph Hellwig continue; 4313b6592f7SJens Axboe } 4323b6592f7SJens Axboe 4334b04cc6aSJens Axboe /* 4344b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4354b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4364b04cc6aSJens Axboe */ 4373b6592f7SJens Axboe map->queue_offset = qoff; 438cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4393b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4404b04cc6aSJens Axboe else 4414b04cc6aSJens Axboe blk_mq_map_queues(map); 4423b6592f7SJens Axboe qoff += map->nr_queues; 4433b6592f7SJens Axboe offset += map->nr_queues; 4443b6592f7SJens Axboe } 4453b6592f7SJens Axboe 4463b6592f7SJens Axboe return 0; 447dca51e78SChristoph Hellwig } 448dca51e78SChristoph Hellwig 44904f3eafdSJens Axboe /* 45004f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 45104f3eafdSJens Axboe */ 45204f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 45304f3eafdSJens Axboe { 45404f3eafdSJens Axboe if (!write_sq) { 45504f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 45604f3eafdSJens Axboe 45704f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 45804f3eafdSJens Axboe next_tail = 0; 45904f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 46004f3eafdSJens Axboe return; 46104f3eafdSJens Axboe } 46204f3eafdSJens Axboe 46304f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 46404f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 46504f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 46604f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 46704f3eafdSJens Axboe } 46804f3eafdSJens Axboe 46957dacad5SJay Sternberg /** 47090ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 47157dacad5SJay Sternberg * @nvmeq: The queue to use 47257dacad5SJay Sternberg * @cmd: The command to send 47304f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 47457dacad5SJay Sternberg */ 47504f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 47604f3eafdSJens Axboe bool write_sq) 47757dacad5SJay Sternberg { 47890ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 479c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 480c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 48190ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 48290ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 48304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 48404f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 48504f3eafdSJens Axboe } 48604f3eafdSJens Axboe 48704f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 48804f3eafdSJens Axboe { 48904f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 49004f3eafdSJens Axboe 49104f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 49204f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 49304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 49490ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 49557dacad5SJay Sternberg } 49657dacad5SJay Sternberg 497a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 49857dacad5SJay Sternberg { 499f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 500a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 50157dacad5SJay Sternberg } 50257dacad5SJay Sternberg 503955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 504955b1b5aSMinwoo Im { 505955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 50620469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 507955b1b5aSMinwoo Im unsigned int avg_seg_size; 508955b1b5aSMinwoo Im 50920469a37SKeith Busch if (nseg == 0) 51020469a37SKeith Busch return false; 51120469a37SKeith Busch 51220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 513955b1b5aSMinwoo Im 514955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 515955b1b5aSMinwoo Im return false; 516955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 517955b1b5aSMinwoo Im return false; 518955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 519955b1b5aSMinwoo Im return false; 520955b1b5aSMinwoo Im return true; 521955b1b5aSMinwoo Im } 522955b1b5aSMinwoo Im 5237fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 52457dacad5SJay Sternberg { 525f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 527a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 52857dacad5SJay Sternberg int i; 52957dacad5SJay Sternberg 530dff824b2SChristoph Hellwig if (iod->dma_len) { 531f2fa006fSIsrael Rukshin dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 532f2fa006fSIsrael Rukshin rq_dma_dir(req)); 533dff824b2SChristoph Hellwig return; 534dff824b2SChristoph Hellwig } 535dff824b2SChristoph Hellwig 536dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 537dff824b2SChristoph Hellwig 5387f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5397f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5407f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5417f73eac3SLogan Gunthorpe else 542dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5437fe07d14SChristoph Hellwig 5447fe07d14SChristoph Hellwig 54557dacad5SJay Sternberg if (iod->npages == 0) 546a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 547a7a7cbe3SChaitanya Kulkarni dma_addr); 548a7a7cbe3SChaitanya Kulkarni 54957dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 550a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 551a7a7cbe3SChaitanya Kulkarni 552a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 553a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 554a7a7cbe3SChaitanya Kulkarni 555a7a7cbe3SChaitanya Kulkarni next_dma_addr = 556a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 557a7a7cbe3SChaitanya Kulkarni } else { 558a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 559a7a7cbe3SChaitanya Kulkarni 560a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 561a7a7cbe3SChaitanya Kulkarni } 562a7a7cbe3SChaitanya Kulkarni 563a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 564a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 56557dacad5SJay Sternberg } 56657dacad5SJay Sternberg 567943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 56857dacad5SJay Sternberg } 56957dacad5SJay Sternberg 570d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 571d0877473SKeith Busch { 572d0877473SKeith Busch int i; 573d0877473SKeith Busch struct scatterlist *sg; 574d0877473SKeith Busch 575d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 576d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 577d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 578d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 579d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 580d0877473SKeith Busch sg_dma_len(sg)); 581d0877473SKeith Busch } 582d0877473SKeith Busch } 583d0877473SKeith Busch 584a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 585a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 58657dacad5SJay Sternberg { 587f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 58857dacad5SJay Sternberg struct dma_pool *pool; 589b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 59057dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 59157dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 59257dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5935fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 59457dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 59557dacad5SJay Sternberg __le64 *prp_list; 596a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 59757dacad5SJay Sternberg dma_addr_t prp_dma; 59857dacad5SJay Sternberg int nprps, i; 59957dacad5SJay Sternberg 60057dacad5SJay Sternberg length -= (page_size - offset); 6015228b328SJan H. Schönherr if (length <= 0) { 6025228b328SJan H. Schönherr iod->first_dma = 0; 603a7a7cbe3SChaitanya Kulkarni goto done; 6045228b328SJan H. Schönherr } 60557dacad5SJay Sternberg 60657dacad5SJay Sternberg dma_len -= (page_size - offset); 60757dacad5SJay Sternberg if (dma_len) { 60857dacad5SJay Sternberg dma_addr += (page_size - offset); 60957dacad5SJay Sternberg } else { 61057dacad5SJay Sternberg sg = sg_next(sg); 61157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 61257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 61357dacad5SJay Sternberg } 61457dacad5SJay Sternberg 61557dacad5SJay Sternberg if (length <= page_size) { 61657dacad5SJay Sternberg iod->first_dma = dma_addr; 617a7a7cbe3SChaitanya Kulkarni goto done; 61857dacad5SJay Sternberg } 61957dacad5SJay Sternberg 62057dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 62157dacad5SJay Sternberg if (nprps <= (256 / 8)) { 62257dacad5SJay Sternberg pool = dev->prp_small_pool; 62357dacad5SJay Sternberg iod->npages = 0; 62457dacad5SJay Sternberg } else { 62557dacad5SJay Sternberg pool = dev->prp_page_pool; 62657dacad5SJay Sternberg iod->npages = 1; 62757dacad5SJay Sternberg } 62857dacad5SJay Sternberg 62969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 63057dacad5SJay Sternberg if (!prp_list) { 63157dacad5SJay Sternberg iod->first_dma = dma_addr; 63257dacad5SJay Sternberg iod->npages = -1; 63386eea289SKeith Busch return BLK_STS_RESOURCE; 63457dacad5SJay Sternberg } 63557dacad5SJay Sternberg list[0] = prp_list; 63657dacad5SJay Sternberg iod->first_dma = prp_dma; 63757dacad5SJay Sternberg i = 0; 63857dacad5SJay Sternberg for (;;) { 63957dacad5SJay Sternberg if (i == page_size >> 3) { 64057dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 64169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64257dacad5SJay Sternberg if (!prp_list) 64386eea289SKeith Busch return BLK_STS_RESOURCE; 64457dacad5SJay Sternberg list[iod->npages++] = prp_list; 64557dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 64657dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 64757dacad5SJay Sternberg i = 1; 64857dacad5SJay Sternberg } 64957dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 65057dacad5SJay Sternberg dma_len -= page_size; 65157dacad5SJay Sternberg dma_addr += page_size; 65257dacad5SJay Sternberg length -= page_size; 65357dacad5SJay Sternberg if (length <= 0) 65457dacad5SJay Sternberg break; 65557dacad5SJay Sternberg if (dma_len > 0) 65657dacad5SJay Sternberg continue; 65786eea289SKeith Busch if (unlikely(dma_len < 0)) 65886eea289SKeith Busch goto bad_sgl; 65957dacad5SJay Sternberg sg = sg_next(sg); 66057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 66157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 66257dacad5SJay Sternberg } 66357dacad5SJay Sternberg 664a7a7cbe3SChaitanya Kulkarni done: 665a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 666a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 667a7a7cbe3SChaitanya Kulkarni 66886eea289SKeith Busch return BLK_STS_OK; 66986eea289SKeith Busch 67086eea289SKeith Busch bad_sgl: 671d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 672d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 673d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 67486eea289SKeith Busch return BLK_STS_IOERR; 67557dacad5SJay Sternberg } 67657dacad5SJay Sternberg 677a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 678a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 679a7a7cbe3SChaitanya Kulkarni { 680a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 681a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 682a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 683a7a7cbe3SChaitanya Kulkarni } 684a7a7cbe3SChaitanya Kulkarni 685a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 686a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 687a7a7cbe3SChaitanya Kulkarni { 688a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 689a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 690a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 691a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 692a7a7cbe3SChaitanya Kulkarni } else { 693a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 694a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 695a7a7cbe3SChaitanya Kulkarni } 696a7a7cbe3SChaitanya Kulkarni } 697a7a7cbe3SChaitanya Kulkarni 698a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 699b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 700a7a7cbe3SChaitanya Kulkarni { 701a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 702a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 703a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 704a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 705a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 706b0f2853bSChristoph Hellwig int i = 0; 707a7a7cbe3SChaitanya Kulkarni 708a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 709a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 710a7a7cbe3SChaitanya Kulkarni 711b0f2853bSChristoph Hellwig if (entries == 1) { 712a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 713a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 714a7a7cbe3SChaitanya Kulkarni } 715a7a7cbe3SChaitanya Kulkarni 716a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 717a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 718a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 719a7a7cbe3SChaitanya Kulkarni } else { 720a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 721a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 722a7a7cbe3SChaitanya Kulkarni } 723a7a7cbe3SChaitanya Kulkarni 724a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 725a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 726a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 727a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 728a7a7cbe3SChaitanya Kulkarni } 729a7a7cbe3SChaitanya Kulkarni 730a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 731a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 732a7a7cbe3SChaitanya Kulkarni 733a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 734a7a7cbe3SChaitanya Kulkarni 735a7a7cbe3SChaitanya Kulkarni do { 736a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 737a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 738a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 739a7a7cbe3SChaitanya Kulkarni 740a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 741a7a7cbe3SChaitanya Kulkarni if (!sg_list) 742a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 743a7a7cbe3SChaitanya Kulkarni 744a7a7cbe3SChaitanya Kulkarni i = 0; 745a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 746a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 747a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 748a7a7cbe3SChaitanya Kulkarni } 749a7a7cbe3SChaitanya Kulkarni 750a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 751a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 752b0f2853bSChristoph Hellwig } while (--entries > 0); 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 755a7a7cbe3SChaitanya Kulkarni } 756a7a7cbe3SChaitanya Kulkarni 757dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 758dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 759dff824b2SChristoph Hellwig struct bio_vec *bv) 760dff824b2SChristoph Hellwig { 761dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 762a4f40484SKevin Hao unsigned int offset = bv->bv_offset & (dev->ctrl.page_size - 1); 763a4f40484SKevin Hao unsigned int first_prp_len = dev->ctrl.page_size - offset; 764dff824b2SChristoph Hellwig 765dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 766dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 767dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 768dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 769dff824b2SChristoph Hellwig 770dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 771dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 772dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 773dff824b2SChristoph Hellwig return 0; 774dff824b2SChristoph Hellwig } 775dff824b2SChristoph Hellwig 77629791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 77729791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 77829791057SChristoph Hellwig struct bio_vec *bv) 77929791057SChristoph Hellwig { 78029791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 78129791057SChristoph Hellwig 78229791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 78329791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 78429791057SChristoph Hellwig return BLK_STS_RESOURCE; 78529791057SChristoph Hellwig iod->dma_len = bv->bv_len; 78629791057SChristoph Hellwig 787049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 78829791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 78929791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 79029791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 79129791057SChristoph Hellwig return 0; 79229791057SChristoph Hellwig } 79329791057SChristoph Hellwig 794fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 795b131c61dSChristoph Hellwig struct nvme_command *cmnd) 79657dacad5SJay Sternberg { 797f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 79870479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 799b0f2853bSChristoph Hellwig int nr_mapped; 80057dacad5SJay Sternberg 801dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 802dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 803dff824b2SChristoph Hellwig 804dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 805dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 806dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 807dff824b2SChristoph Hellwig &cmnd->rw, &bv); 80829791057SChristoph Hellwig 80929791057SChristoph Hellwig if (iod->nvmeq->qid && 81029791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 81129791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 81229791057SChristoph Hellwig &cmnd->rw, &bv); 813dff824b2SChristoph Hellwig } 814dff824b2SChristoph Hellwig } 815dff824b2SChristoph Hellwig 816dff824b2SChristoph Hellwig iod->dma_len = 0; 8179b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8189b048119SChristoph Hellwig if (!iod->sg) 8199b048119SChristoph Hellwig return BLK_STS_RESOURCE; 820f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 82170479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 822ba1ca37eSChristoph Hellwig if (!iod->nents) 823ba1ca37eSChristoph Hellwig goto out; 824ba1ca37eSChristoph Hellwig 825e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8262b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8272b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 828e0596ab2SLogan Gunthorpe else 829e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 83070479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 831b0f2853bSChristoph Hellwig if (!nr_mapped) 832ba1ca37eSChristoph Hellwig goto out; 833ba1ca37eSChristoph Hellwig 83470479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 835955b1b5aSMinwoo Im if (iod->use_sgl) 836b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 837a7a7cbe3SChaitanya Kulkarni else 838a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 839ba1ca37eSChristoph Hellwig out: 8404aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8417fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 842ba1ca37eSChristoph Hellwig return ret; 84357dacad5SJay Sternberg } 84457dacad5SJay Sternberg 8454aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8464aedb705SChristoph Hellwig struct nvme_command *cmnd) 8474aedb705SChristoph Hellwig { 8484aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8494aedb705SChristoph Hellwig 8504aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8514aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8524aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8534aedb705SChristoph Hellwig return BLK_STS_IOERR; 8544aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 8554aedb705SChristoph Hellwig return 0; 8564aedb705SChristoph Hellwig } 8574aedb705SChristoph Hellwig 85857dacad5SJay Sternberg /* 85957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86057dacad5SJay Sternberg */ 861fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86357dacad5SJay Sternberg { 86457dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 86557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 86657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 86757dacad5SJay Sternberg struct request *req = bd->rq; 8689b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 869ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 870ebe6d874SChristoph Hellwig blk_status_t ret; 87157dacad5SJay Sternberg 8729b048119SChristoph Hellwig iod->aborted = 0; 8739b048119SChristoph Hellwig iod->npages = -1; 8749b048119SChristoph Hellwig iod->nents = 0; 8759b048119SChristoph Hellwig 876d1f06f4aSJens Axboe /* 877d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 878d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 879d1f06f4aSJens Axboe */ 8804e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 881d1f06f4aSJens Axboe return BLK_STS_IOERR; 882d1f06f4aSJens Axboe 883f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 884fc17b653SChristoph Hellwig if (ret) 885f4800d6dSChristoph Hellwig return ret; 88657dacad5SJay Sternberg 887fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 888b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 889fc17b653SChristoph Hellwig if (ret) 8909b048119SChristoph Hellwig goto out_free_cmd; 891fc17b653SChristoph Hellwig } 892ba1ca37eSChristoph Hellwig 8934aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 8944aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 8954aedb705SChristoph Hellwig if (ret) 8964aedb705SChristoph Hellwig goto out_unmap_data; 8974aedb705SChristoph Hellwig } 8984aedb705SChristoph Hellwig 899aae239e1SChristoph Hellwig blk_mq_start_request(req); 90004f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 901fc17b653SChristoph Hellwig return BLK_STS_OK; 9024aedb705SChristoph Hellwig out_unmap_data: 9034aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 904f9d03f96SChristoph Hellwig out_free_cmd: 905f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 906ba1ca37eSChristoph Hellwig return ret; 90757dacad5SJay Sternberg } 90857dacad5SJay Sternberg 90977f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 910eee417b0SChristoph Hellwig { 911f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9124aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 913eee417b0SChristoph Hellwig 9144aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9154aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9164aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 917b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9184aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 91977f02a7aSChristoph Hellwig nvme_complete_rq(req); 92057dacad5SJay Sternberg } 92157dacad5SJay Sternberg 922d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 923750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 924d783e0bdSMarta Rybczynska { 925750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 926750dde44SChristoph Hellwig nvmeq->cq_phase; 927d783e0bdSMarta Rybczynska } 928d783e0bdSMarta Rybczynska 929eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 93057dacad5SJay Sternberg { 931eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 93257dacad5SJay Sternberg 933eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 934eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 935eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 936eb281c82SSagi Grimberg } 937adf68f21SChristoph Hellwig 938cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 939cfa27356SChristoph Hellwig { 940cfa27356SChristoph Hellwig if (!nvmeq->qid) 941cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 942cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 943cfa27356SChristoph Hellwig } 944cfa27356SChristoph Hellwig 9455cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 94657dacad5SJay Sternberg { 9475cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 94857dacad5SJay Sternberg struct request *req; 949adf68f21SChristoph Hellwig 95083a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9511b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 952aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 95383a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 95483a12fb7SSagi Grimberg return; 955aae239e1SChristoph Hellwig } 956aae239e1SChristoph Hellwig 957adf68f21SChristoph Hellwig /* 958adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 959adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 960adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 961adf68f21SChristoph Hellwig * for them but rather special case them here. 962adf68f21SChristoph Hellwig */ 96358a8df67SIsrael Rukshin if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 9647bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 96583a12fb7SSagi Grimberg cqe->status, &cqe->result); 966a0fa9647SJens Axboe return; 96757dacad5SJay Sternberg } 96857dacad5SJay Sternberg 969cfa27356SChristoph Hellwig req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 970604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 97183a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 97283a12fb7SSagi Grimberg } 97357dacad5SJay Sternberg 9745cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 97583a12fb7SSagi Grimberg { 9765cb525c8SJens Axboe while (start != end) { 9775cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9785cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9795cb525c8SJens Axboe start = 0; 9805cb525c8SJens Axboe } 9815cb525c8SJens Axboe } 98283a12fb7SSagi Grimberg 9835cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9845cb525c8SJens Axboe { 985e2a366a4SAlexey Dobriyan if (++nvmeq->cq_head == nvmeq->q_depth) { 986920d13a8SSagi Grimberg nvmeq->cq_head = 0; 987e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 988920d13a8SSagi Grimberg } 989a0fa9647SJens Axboe } 990a0fa9647SJens Axboe 9911052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9921052b8acSJens Axboe u16 *end, unsigned int tag) 993a0fa9647SJens Axboe { 9941052b8acSJens Axboe int found = 0; 99583a12fb7SSagi Grimberg 9965cb525c8SJens Axboe *start = nvmeq->cq_head; 9971052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 9981052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 9991052b8acSJens Axboe found++; 10005cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 100157dacad5SJay Sternberg } 10025cb525c8SJens Axboe *end = nvmeq->cq_head; 100357dacad5SJay Sternberg 10045cb525c8SJens Axboe if (*start != *end) 1005eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10065cb525c8SJens Axboe return found; 100757dacad5SJay Sternberg } 100857dacad5SJay Sternberg 100957dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 101057dacad5SJay Sternberg { 101157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 101268fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10135cb525c8SJens Axboe u16 start, end; 10145cb525c8SJens Axboe 10153a7afd8eSChristoph Hellwig /* 10163a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10173a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10183a7afd8eSChristoph Hellwig */ 10193a7afd8eSChristoph Hellwig rmb(); 10205cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 10213a7afd8eSChristoph Hellwig wmb(); 10225cb525c8SJens Axboe 102368fa9dbeSJens Axboe if (start != end) { 10245cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10255cb525c8SJens Axboe return IRQ_HANDLED; 102657dacad5SJay Sternberg } 102757dacad5SJay Sternberg 102868fa9dbeSJens Axboe return ret; 102957dacad5SJay Sternberg } 103057dacad5SJay Sternberg 103157dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 103257dacad5SJay Sternberg { 103357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1034750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 103557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1036d783e0bdSMarta Rybczynska return IRQ_NONE; 103757dacad5SJay Sternberg } 103857dacad5SJay Sternberg 10390b2a8a9fSChristoph Hellwig /* 10400b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10410b2a8a9fSChristoph Hellwig * Can be called from any context. 10420b2a8a9fSChristoph Hellwig */ 10430b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1044a0fa9647SJens Axboe { 10453a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10465cb525c8SJens Axboe u16 start, end; 10471052b8acSJens Axboe int found; 1048a0fa9647SJens Axboe 10493a7afd8eSChristoph Hellwig /* 10503a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10513a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10523a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10533a7afd8eSChristoph Hellwig */ 10547c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10553a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 105691a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 105791a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 105891a509f8SChristoph Hellwig } else { 10593a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10605cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10613a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 106291a509f8SChristoph Hellwig } 1063442e19b7SSagi Grimberg 10645cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1065442e19b7SSagi Grimberg return found; 1066a0fa9647SJens Axboe } 1067a0fa9647SJens Axboe 10689743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10697776db1cSKeith Busch { 10707776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1071dabcefabSJens Axboe u16 start, end; 1072dabcefabSJens Axboe bool found; 1073dabcefabSJens Axboe 1074dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1075dabcefabSJens Axboe return 0; 1076dabcefabSJens Axboe 10773a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 10789743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 10799515743bSBijan Mottahedeh nvme_complete_cqes(nvmeq, start, end); 10803a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1081dabcefabSJens Axboe 1082dabcefabSJens Axboe return found; 1083dabcefabSJens Axboe } 1084dabcefabSJens Axboe 1085ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 108657dacad5SJay Sternberg { 1087f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1088147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 108957dacad5SJay Sternberg struct nvme_command c; 109057dacad5SJay Sternberg 109157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 109257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1093ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 109404f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 109557dacad5SJay Sternberg } 109657dacad5SJay Sternberg 109757dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 109857dacad5SJay Sternberg { 109957dacad5SJay Sternberg struct nvme_command c; 110057dacad5SJay Sternberg 110157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110257dacad5SJay Sternberg c.delete_queue.opcode = opcode; 110357dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 110457dacad5SJay Sternberg 11051c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 110657dacad5SJay Sternberg } 110757dacad5SJay Sternberg 110857dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1109a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 111057dacad5SJay Sternberg { 111157dacad5SJay Sternberg struct nvme_command c; 11124b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11134b04cc6aSJens Axboe 11147c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11154b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg /* 111816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 111957dacad5SJay Sternberg * is attached to the request. 112057dacad5SJay Sternberg */ 112157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 112357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 112457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 112557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1127a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 112857dacad5SJay Sternberg 11291c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113057dacad5SJay Sternberg } 113157dacad5SJay Sternberg 113257dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 113357dacad5SJay Sternberg struct nvme_queue *nvmeq) 113457dacad5SJay Sternberg { 11359abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 113657dacad5SJay Sternberg struct nvme_command c; 113781c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 113857dacad5SJay Sternberg 113957dacad5SJay Sternberg /* 11409abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11419abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11429abd68efSJens Axboe * URGENT. 11439abd68efSJens Axboe */ 11449abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11459abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11469abd68efSJens Axboe 11479abd68efSJens Axboe /* 114816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 114957dacad5SJay Sternberg * is attached to the request. 115057dacad5SJay Sternberg */ 115157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115257dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 115357dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 115457dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 115557dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 115657dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 115757dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 115857dacad5SJay Sternberg 11591c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116057dacad5SJay Sternberg } 116157dacad5SJay Sternberg 116257dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 116357dacad5SJay Sternberg { 116457dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 116557dacad5SJay Sternberg } 116657dacad5SJay Sternberg 116757dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 116857dacad5SJay Sternberg { 116957dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 117057dacad5SJay Sternberg } 117157dacad5SJay Sternberg 11722a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 117357dacad5SJay Sternberg { 1174f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1175f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 117657dacad5SJay Sternberg 117727fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 117827fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1179e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1180e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 118157dacad5SJay Sternberg } 118257dacad5SJay Sternberg 1183b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1184b2a0eb1aSKeith Busch { 1185b2a0eb1aSKeith Busch 1186b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1187b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1188b2a0eb1aSKeith Busch */ 1189b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1190b2a0eb1aSKeith Busch 1191ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1192ad70062cSJianchao Wang switch (dev->ctrl.state) { 1193ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1194ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1195b2a0eb1aSKeith Busch return false; 1196ad70062cSJianchao Wang default: 1197ad70062cSJianchao Wang break; 1198ad70062cSJianchao Wang } 1199b2a0eb1aSKeith Busch 1200b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1201b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1202b2a0eb1aSKeith Busch */ 1203b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1204b2a0eb1aSKeith Busch return false; 1205b2a0eb1aSKeith Busch 1206b2a0eb1aSKeith Busch return true; 1207b2a0eb1aSKeith Busch } 1208b2a0eb1aSKeith Busch 1209b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1210b2a0eb1aSKeith Busch { 1211b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1212b2a0eb1aSKeith Busch u16 pci_status; 1213b2a0eb1aSKeith Busch int result; 1214b2a0eb1aSKeith Busch 1215b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1216b2a0eb1aSKeith Busch &pci_status); 1217b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1218b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1219b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1220b2a0eb1aSKeith Busch csts, pci_status); 1221b2a0eb1aSKeith Busch else 1222b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1223b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1224b2a0eb1aSKeith Busch csts, result); 1225b2a0eb1aSKeith Busch } 1226b2a0eb1aSKeith Busch 122731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 122857dacad5SJay Sternberg { 1229f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1230f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 123157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 123257dacad5SJay Sternberg struct request *abort_req; 123357dacad5SJay Sternberg struct nvme_command cmd; 1234b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1235b2a0eb1aSKeith Busch 1236651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1237651438bbSWen Xiong * the recovery mechanism will surely fail. 1238651438bbSWen Xiong */ 1239651438bbSWen Xiong mb(); 1240651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1241651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1242651438bbSWen Xiong 1243b2a0eb1aSKeith Busch /* 1244b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1245b2a0eb1aSKeith Busch */ 1246b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1247b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1248b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1249d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1250db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1251b2a0eb1aSKeith Busch } 125257dacad5SJay Sternberg 125331c7c7d2SChristoph Hellwig /* 12547776db1cSKeith Busch * Did we miss an interrupt? 12557776db1cSKeith Busch */ 12560b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12577776db1cSKeith Busch dev_warn(dev->ctrl.device, 12587776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12597776db1cSKeith Busch req->tag, nvmeq->qid); 1260db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12617776db1cSKeith Busch } 12627776db1cSKeith Busch 12637776db1cSKeith Busch /* 1264fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1265fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1266fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1267db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1268fd634f41SChristoph Hellwig */ 12694244140dSKeith Busch switch (dev->ctrl.state) { 12704244140dSKeith Busch case NVME_CTRL_CONNECTING: 12712036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 12722036f726SKeith Busch /* fall through */ 12732036f726SKeith Busch case NVME_CTRL_DELETING: 1274b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1275fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1276fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 12772036f726SKeith Busch nvme_dev_disable(dev, true); 127827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1279db8c48e4SChristoph Hellwig return BLK_EH_DONE; 128039a9dd81SKeith Busch case NVME_CTRL_RESETTING: 128139a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12824244140dSKeith Busch default: 12834244140dSKeith Busch break; 1284fd634f41SChristoph Hellwig } 1285fd634f41SChristoph Hellwig 1286fd634f41SChristoph Hellwig /* 1287e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1288e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1289e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 129031c7c7d2SChristoph Hellwig */ 1291f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12921b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 129357dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 129457dacad5SJay Sternberg req->tag, nvmeq->qid); 1295a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1296d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1297e1569a16SKeith Busch 129827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1299db8c48e4SChristoph Hellwig return BLK_EH_DONE; 130057dacad5SJay Sternberg } 130157dacad5SJay Sternberg 1302e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1303e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1304e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1305e7a2a87dSChristoph Hellwig } 13067bf7d778SKeith Busch iod->aborted = 1; 130757dacad5SJay Sternberg 130857dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 130957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 131057dacad5SJay Sternberg cmd.abort.cid = req->tag; 131157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 131257dacad5SJay Sternberg 13131b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13141b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 131557dacad5SJay Sternberg req->tag, nvmeq->qid); 1316e7a2a87dSChristoph Hellwig 1317e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1318eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13196bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13206bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 132131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 132257dacad5SJay Sternberg } 132357dacad5SJay Sternberg 1324e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1325e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1326e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 132757dacad5SJay Sternberg 132857dacad5SJay Sternberg /* 132957dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 133057dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 133157dacad5SJay Sternberg * as the device then is in a faulty state. 133257dacad5SJay Sternberg */ 133357dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 133457dacad5SJay Sternberg } 133557dacad5SJay Sternberg 133657dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 133757dacad5SJay Sternberg { 13388a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 133957dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 134063223078SChristoph Hellwig if (!nvmeq->sq_cmds) 134163223078SChristoph Hellwig return; 13420f238ff5SLogan Gunthorpe 134363223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 134488a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13458a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 134663223078SChristoph Hellwig } else { 13478a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 134863223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13490f238ff5SLogan Gunthorpe } 135057dacad5SJay Sternberg } 135157dacad5SJay Sternberg 135257dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 135357dacad5SJay Sternberg { 135457dacad5SJay Sternberg int i; 135557dacad5SJay Sternberg 1356d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1357d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1358147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 135957dacad5SJay Sternberg } 136057dacad5SJay Sternberg } 136157dacad5SJay Sternberg 136257dacad5SJay Sternberg /** 136357dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 136440581d1aSBart Van Assche * @nvmeq: queue to suspend 136557dacad5SJay Sternberg */ 136657dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 136757dacad5SJay Sternberg { 13684e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 136957dacad5SJay Sternberg return 1; 137057dacad5SJay Sternberg 13714e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1372d1f06f4aSJens Axboe mb(); 137357dacad5SJay Sternberg 13744e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13751c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1376c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13777c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13784e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 137957dacad5SJay Sternberg return 0; 138057dacad5SJay Sternberg } 138157dacad5SJay Sternberg 13828fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13838fae268bSKeith Busch { 13848fae268bSKeith Busch int i; 13858fae268bSKeith Busch 13868fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13878fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13888fae268bSKeith Busch } 13898fae268bSKeith Busch 1390a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 139157dacad5SJay Sternberg { 1392147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 139357dacad5SJay Sternberg 1394a5cdb68cSKeith Busch if (shutdown) 1395a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1396a5cdb68cSKeith Busch else 1397b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 139857dacad5SJay Sternberg 13990b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 140057dacad5SJay Sternberg } 140157dacad5SJay Sternberg 1402fa46c6fbSKeith Busch /* 1403fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 1404fa46c6fbSKeith Busch * that can check this device's completion queues have synced. This is the 1405fa46c6fbSKeith Busch * last chance for the driver to see a natural completion before 1406fa46c6fbSKeith Busch * nvme_cancel_request() terminates all incomplete requests. 1407fa46c6fbSKeith Busch */ 1408fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1409fa46c6fbSKeith Busch { 1410fa46c6fbSKeith Busch u16 start, end; 1411fa46c6fbSKeith Busch int i; 1412fa46c6fbSKeith Busch 1413fa46c6fbSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 1414fa46c6fbSKeith Busch nvme_process_cq(&dev->queues[i], &start, &end, -1); 1415fa46c6fbSKeith Busch nvme_complete_cqes(&dev->queues[i], start, end); 1416fa46c6fbSKeith Busch } 1417fa46c6fbSKeith Busch } 1418fa46c6fbSKeith Busch 141957dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 142057dacad5SJay Sternberg int entry_size) 142157dacad5SJay Sternberg { 142257dacad5SJay Sternberg int q_depth = dev->q_depth; 14235fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14245fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 142557dacad5SJay Sternberg 142657dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 142757dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14285fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 142957dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 143057dacad5SJay Sternberg 143157dacad5SJay Sternberg /* 143257dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 143357dacad5SJay Sternberg * would be better to map queues in system memory with the 143457dacad5SJay Sternberg * original depth 143557dacad5SJay Sternberg */ 143657dacad5SJay Sternberg if (q_depth < 64) 143757dacad5SJay Sternberg return -ENOMEM; 143857dacad5SJay Sternberg } 143957dacad5SJay Sternberg 144057dacad5SJay Sternberg return q_depth; 144157dacad5SJay Sternberg } 144257dacad5SJay Sternberg 144357dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14448a1d09a6SBenjamin Herrenschmidt int qid) 144557dacad5SJay Sternberg { 14460f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1447815c6704SKeith Busch 14480f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14498a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1450bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14510f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14520f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 145363223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 145463223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 145563223078SChristoph Hellwig return 0; 145663223078SChristoph Hellwig } 1457bfac8e9fSAlan Mikhak 14588a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1459bfac8e9fSAlan Mikhak } 14600f238ff5SLogan Gunthorpe } 14610f238ff5SLogan Gunthorpe 14628a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 146357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 146457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 146557dacad5SJay Sternberg return -ENOMEM; 146657dacad5SJay Sternberg return 0; 146757dacad5SJay Sternberg } 146857dacad5SJay Sternberg 1469a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 147057dacad5SJay Sternberg { 1471147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 147257dacad5SJay Sternberg 147362314e40SKeith Busch if (dev->ctrl.queue_count > qid) 147462314e40SKeith Busch return 0; 147557dacad5SJay Sternberg 1476c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14778a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14788a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 147957dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 148057dacad5SJay Sternberg if (!nvmeq->cqes) 148157dacad5SJay Sternberg goto free_nvmeq; 148257dacad5SJay Sternberg 14838a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 148457dacad5SJay Sternberg goto free_cqdma; 148557dacad5SJay Sternberg 148657dacad5SJay Sternberg nvmeq->dev = dev; 14871ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14883a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 148957dacad5SJay Sternberg nvmeq->cq_head = 0; 149057dacad5SJay Sternberg nvmeq->cq_phase = 1; 149157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 149257dacad5SJay Sternberg nvmeq->qid = qid; 1493d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 149457dacad5SJay Sternberg 1495147b27e4SSagi Grimberg return 0; 149657dacad5SJay Sternberg 149757dacad5SJay Sternberg free_cqdma: 14988a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 149957dacad5SJay Sternberg nvmeq->cq_dma_addr); 150057dacad5SJay Sternberg free_nvmeq: 1501147b27e4SSagi Grimberg return -ENOMEM; 150257dacad5SJay Sternberg } 150357dacad5SJay Sternberg 1504dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 150557dacad5SJay Sternberg { 15060ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15070ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15080ff199cbSChristoph Hellwig 15090ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15100ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15110ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15120ff199cbSChristoph Hellwig } else { 15130ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15140ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15150ff199cbSChristoph Hellwig } 151657dacad5SJay Sternberg } 151757dacad5SJay Sternberg 151857dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 151957dacad5SJay Sternberg { 152057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152157dacad5SJay Sternberg 152257dacad5SJay Sternberg nvmeq->sq_tail = 0; 152304f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 152457dacad5SJay Sternberg nvmeq->cq_head = 0; 152557dacad5SJay Sternberg nvmeq->cq_phase = 1; 152657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15278a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1528f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 152957dacad5SJay Sternberg dev->online_queues++; 15303a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 153157dacad5SJay Sternberg } 153257dacad5SJay Sternberg 15334b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 153457dacad5SJay Sternberg { 153557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153657dacad5SJay Sternberg int result; 15377c349ddeSKeith Busch u16 vector = 0; 153857dacad5SJay Sternberg 1539d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1540d1ed6aa1SChristoph Hellwig 154122b55601SKeith Busch /* 154222b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 154322b55601SKeith Busch * has only one vector available. 154422b55601SKeith Busch */ 15454b04cc6aSJens Axboe if (!polled) 1546a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15474b04cc6aSJens Axboe else 15487c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15494b04cc6aSJens Axboe 1550a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1551ded45505SKeith Busch if (result) 1552ded45505SKeith Busch return result; 155357dacad5SJay Sternberg 155457dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 155557dacad5SJay Sternberg if (result < 0) 1556ded45505SKeith Busch return result; 1557c80b36cdSEdmund Nadolski if (result) 155857dacad5SJay Sternberg goto release_cq; 155957dacad5SJay Sternberg 1560a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1561161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15624b04cc6aSJens Axboe 15637c349ddeSKeith Busch if (!polled) { 1564dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 156557dacad5SJay Sternberg if (result < 0) 156657dacad5SJay Sternberg goto release_sq; 15674b04cc6aSJens Axboe } 156857dacad5SJay Sternberg 15694e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 157057dacad5SJay Sternberg return result; 157157dacad5SJay Sternberg 157257dacad5SJay Sternberg release_sq: 1573f25a2dfcSJianchao Wang dev->online_queues--; 157457dacad5SJay Sternberg adapter_delete_sq(dev, qid); 157557dacad5SJay Sternberg release_cq: 157657dacad5SJay Sternberg adapter_delete_cq(dev, qid); 157757dacad5SJay Sternberg return result; 157857dacad5SJay Sternberg } 157957dacad5SJay Sternberg 1580f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 158157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 158357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 15840350815aSChristoph Hellwig .init_request = nvme_init_request, 158557dacad5SJay Sternberg .timeout = nvme_timeout, 158657dacad5SJay Sternberg }; 158757dacad5SJay Sternberg 1588f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1589376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1590376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1591376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1592376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1593376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1594376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1595376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1596c6d962aeSChristoph Hellwig .poll = nvme_poll, 1597dabcefabSJens Axboe }; 1598dabcefabSJens Axboe 159957dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 160057dacad5SJay Sternberg { 16011c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 160269d9a99cSKeith Busch /* 160369d9a99cSKeith Busch * If the controller was reset during removal, it's possible 160469d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 160569d9a99cSKeith Busch * queue to flush these to completion. 160669d9a99cSKeith Busch */ 1607c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16081c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 160957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 161057dacad5SJay Sternberg } 161157dacad5SJay Sternberg } 161257dacad5SJay Sternberg 161357dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 161457dacad5SJay Sternberg { 16151c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 161657dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 161757dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1618e3e9d50cSKeith Busch 161938dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 162057dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 162157dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1622d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1623d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 162457dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 162557dacad5SJay Sternberg 162657dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 162757dacad5SJay Sternberg return -ENOMEM; 162834b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 162957dacad5SJay Sternberg 16301c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16311c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 163257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163357dacad5SJay Sternberg return -ENOMEM; 163457dacad5SJay Sternberg } 16351c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 163657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16371c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 163857dacad5SJay Sternberg return -ENODEV; 163957dacad5SJay Sternberg } 164057dacad5SJay Sternberg } else 1641c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 164257dacad5SJay Sternberg 164357dacad5SJay Sternberg return 0; 164457dacad5SJay Sternberg } 164557dacad5SJay Sternberg 164697f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 164797f6ef64SXu Yu { 164897f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 164997f6ef64SXu Yu } 165097f6ef64SXu Yu 165197f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 165297f6ef64SXu Yu { 165397f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 165497f6ef64SXu Yu 165597f6ef64SXu Yu if (size <= dev->bar_mapped_size) 165697f6ef64SXu Yu return 0; 165797f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 165897f6ef64SXu Yu return -ENOMEM; 165997f6ef64SXu Yu if (dev->bar) 166097f6ef64SXu Yu iounmap(dev->bar); 166197f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 166297f6ef64SXu Yu if (!dev->bar) { 166397f6ef64SXu Yu dev->bar_mapped_size = 0; 166497f6ef64SXu Yu return -ENOMEM; 166597f6ef64SXu Yu } 166697f6ef64SXu Yu dev->bar_mapped_size = size; 166797f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 166897f6ef64SXu Yu 166997f6ef64SXu Yu return 0; 167097f6ef64SXu Yu } 167197f6ef64SXu Yu 167201ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 167357dacad5SJay Sternberg { 167457dacad5SJay Sternberg int result; 167557dacad5SJay Sternberg u32 aqa; 167657dacad5SJay Sternberg struct nvme_queue *nvmeq; 167757dacad5SJay Sternberg 167897f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 167997f6ef64SXu Yu if (result < 0) 168097f6ef64SXu Yu return result; 168197f6ef64SXu Yu 16828ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 168320d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 168457dacad5SJay Sternberg 16857a67cbeaSChristoph Hellwig if (dev->subsystem && 16867a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16877a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 168857dacad5SJay Sternberg 1689b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 169057dacad5SJay Sternberg if (result < 0) 169157dacad5SJay Sternberg return result; 169257dacad5SJay Sternberg 1693a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1694147b27e4SSagi Grimberg if (result) 1695147b27e4SSagi Grimberg return result; 169657dacad5SJay Sternberg 1697147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 169857dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 169957dacad5SJay Sternberg aqa |= aqa << 16; 170057dacad5SJay Sternberg 17017a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17027a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17037a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 170457dacad5SJay Sternberg 1705c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 170657dacad5SJay Sternberg if (result) 1707d4875622SKeith Busch return result; 170857dacad5SJay Sternberg 170957dacad5SJay Sternberg nvmeq->cq_vector = 0; 1710161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1711dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 171257dacad5SJay Sternberg if (result) { 17137c349ddeSKeith Busch dev->online_queues--; 1714d4875622SKeith Busch return result; 171557dacad5SJay Sternberg } 171657dacad5SJay Sternberg 17174e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 171857dacad5SJay Sternberg return result; 171957dacad5SJay Sternberg } 172057dacad5SJay Sternberg 1721749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 172257dacad5SJay Sternberg { 17234b04cc6aSJens Axboe unsigned i, max, rw_queues; 1724749941f2SChristoph Hellwig int ret = 0; 172557dacad5SJay Sternberg 1726d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1727a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1728749941f2SChristoph Hellwig ret = -ENOMEM; 172957dacad5SJay Sternberg break; 1730749941f2SChristoph Hellwig } 1731749941f2SChristoph Hellwig } 173257dacad5SJay Sternberg 1733d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1734e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1735e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1736e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17374b04cc6aSJens Axboe } else { 17384b04cc6aSJens Axboe rw_queues = max; 17394b04cc6aSJens Axboe } 17404b04cc6aSJens Axboe 1741949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17424b04cc6aSJens Axboe bool polled = i > rw_queues; 17434b04cc6aSJens Axboe 17444b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1745d4875622SKeith Busch if (ret) 174657dacad5SJay Sternberg break; 174757dacad5SJay Sternberg } 174857dacad5SJay Sternberg 1749749941f2SChristoph Hellwig /* 1750749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17518adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17528adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1753749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1754749941f2SChristoph Hellwig */ 1755749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 175657dacad5SJay Sternberg } 175757dacad5SJay Sternberg 1758202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1759202021c1SStephen Bates struct device_attribute *attr, 1760202021c1SStephen Bates char *buf) 1761202021c1SStephen Bates { 1762202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1763202021c1SStephen Bates 1764c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1765202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1766202021c1SStephen Bates } 1767202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1768202021c1SStephen Bates 176988de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 177057dacad5SJay Sternberg { 177188de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 177288de4598SChristoph Hellwig 177388de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 177488de4598SChristoph Hellwig } 177588de4598SChristoph Hellwig 177688de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 177788de4598SChristoph Hellwig { 177888de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 177988de4598SChristoph Hellwig } 178088de4598SChristoph Hellwig 1781f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 178257dacad5SJay Sternberg { 178388de4598SChristoph Hellwig u64 size, offset; 178457dacad5SJay Sternberg resource_size_t bar_size; 178557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17868969f1f8SChristoph Hellwig int bar; 178757dacad5SJay Sternberg 17889fe5c59fSKeith Busch if (dev->cmb_size) 17899fe5c59fSKeith Busch return; 17909fe5c59fSKeith Busch 17917a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1792f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1793f65efd6dSChristoph Hellwig return; 1794202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 179557dacad5SJay Sternberg 179688de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 179788de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17988969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17998969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 180057dacad5SJay Sternberg 180157dacad5SJay Sternberg if (offset > bar_size) 1802f65efd6dSChristoph Hellwig return; 180357dacad5SJay Sternberg 180457dacad5SJay Sternberg /* 180557dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 180657dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 180757dacad5SJay Sternberg * the reported size of the BAR 180857dacad5SJay Sternberg */ 180957dacad5SJay Sternberg if (size > bar_size - offset) 181057dacad5SJay Sternberg size = bar_size - offset; 181157dacad5SJay Sternberg 18120f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18130f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18140f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1815f65efd6dSChristoph Hellwig return; 18160f238ff5SLogan Gunthorpe } 18170f238ff5SLogan Gunthorpe 181857dacad5SJay Sternberg dev->cmb_size = size; 18190f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18200f238ff5SLogan Gunthorpe 18210f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18220f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18230f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1824f65efd6dSChristoph Hellwig 1825f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1826f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1827f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1828f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 182957dacad5SJay Sternberg } 183057dacad5SJay Sternberg 183157dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 183257dacad5SJay Sternberg { 18330f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1834f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1835f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18360f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1837f63572dfSJon Derrick } 183857dacad5SJay Sternberg } 183957dacad5SJay Sternberg 184087ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 184157dacad5SJay Sternberg { 18424033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 184387ad72a5SChristoph Hellwig struct nvme_command c; 184487ad72a5SChristoph Hellwig int ret; 184587ad72a5SChristoph Hellwig 184687ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 184787ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 184887ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 184987ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 185087ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 185187ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 185287ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 185387ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 185487ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 185587ad72a5SChristoph Hellwig 185687ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 185787ad72a5SChristoph Hellwig if (ret) { 185887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 185987ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 186087ad72a5SChristoph Hellwig ret, bits); 186187ad72a5SChristoph Hellwig } 186287ad72a5SChristoph Hellwig return ret; 186387ad72a5SChristoph Hellwig } 186487ad72a5SChristoph Hellwig 186587ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 186687ad72a5SChristoph Hellwig { 186787ad72a5SChristoph Hellwig int i; 186887ad72a5SChristoph Hellwig 186987ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 187087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 187187ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 187287ad72a5SChristoph Hellwig 1873cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1874cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1875cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 187687ad72a5SChristoph Hellwig } 187787ad72a5SChristoph Hellwig 187887ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 187987ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18804033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18814033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18824033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 188387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18847e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 188587ad72a5SChristoph Hellwig } 188687ad72a5SChristoph Hellwig 188792dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 188892dc6895SChristoph Hellwig u32 chunk_size) 188987ad72a5SChristoph Hellwig { 189087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 189192dc6895SChristoph Hellwig u32 max_entries, len; 18924033f35dSChristoph Hellwig dma_addr_t descs_dma; 18932ee0e4edSDan Carpenter int i = 0; 189487ad72a5SChristoph Hellwig void **bufs; 18956fbcde66SMinwoo Im u64 size, tmp; 189687ad72a5SChristoph Hellwig 189787ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 189887ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 189987ad72a5SChristoph Hellwig max_entries = tmp; 1900044a9df1SChristoph Hellwig 1901044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1902044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1903044a9df1SChristoph Hellwig 1904750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19054033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 190687ad72a5SChristoph Hellwig if (!descs) 190787ad72a5SChristoph Hellwig goto out; 190887ad72a5SChristoph Hellwig 190987ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 191087ad72a5SChristoph Hellwig if (!bufs) 191187ad72a5SChristoph Hellwig goto out_free_descs; 191287ad72a5SChristoph Hellwig 1913244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 191487ad72a5SChristoph Hellwig dma_addr_t dma_addr; 191587ad72a5SChristoph Hellwig 191650cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 191787ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 191887ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191987ad72a5SChristoph Hellwig if (!bufs[i]) 192087ad72a5SChristoph Hellwig break; 192187ad72a5SChristoph Hellwig 192287ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 192387ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 192487ad72a5SChristoph Hellwig i++; 192587ad72a5SChristoph Hellwig } 192687ad72a5SChristoph Hellwig 192792dc6895SChristoph Hellwig if (!size) 192887ad72a5SChristoph Hellwig goto out_free_bufs; 192987ad72a5SChristoph Hellwig 193087ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 193187ad72a5SChristoph Hellwig dev->host_mem_size = size; 193287ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19334033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 193487ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 193587ad72a5SChristoph Hellwig return 0; 193687ad72a5SChristoph Hellwig 193787ad72a5SChristoph Hellwig out_free_bufs: 193887ad72a5SChristoph Hellwig while (--i >= 0) { 193987ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 194087ad72a5SChristoph Hellwig 1941cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1942cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1943cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 194487ad72a5SChristoph Hellwig } 194587ad72a5SChristoph Hellwig 194687ad72a5SChristoph Hellwig kfree(bufs); 194787ad72a5SChristoph Hellwig out_free_descs: 19484033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19494033f35dSChristoph Hellwig descs_dma); 195087ad72a5SChristoph Hellwig out: 195187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 195287ad72a5SChristoph Hellwig return -ENOMEM; 195387ad72a5SChristoph Hellwig } 195487ad72a5SChristoph Hellwig 195592dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 195692dc6895SChristoph Hellwig { 195792dc6895SChristoph Hellwig u32 chunk_size; 195892dc6895SChristoph Hellwig 195992dc6895SChristoph Hellwig /* start big and work our way down */ 196030f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1961044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 196292dc6895SChristoph Hellwig chunk_size /= 2) { 196392dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 196492dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 196592dc6895SChristoph Hellwig return 0; 196692dc6895SChristoph Hellwig nvme_free_host_mem(dev); 196792dc6895SChristoph Hellwig } 196892dc6895SChristoph Hellwig } 196992dc6895SChristoph Hellwig 197092dc6895SChristoph Hellwig return -ENOMEM; 197192dc6895SChristoph Hellwig } 197292dc6895SChristoph Hellwig 19739620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 197487ad72a5SChristoph Hellwig { 197587ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 197687ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 197787ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 197887ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19796fbcde66SMinwoo Im int ret; 198087ad72a5SChristoph Hellwig 198187ad72a5SChristoph Hellwig preferred = min(preferred, max); 198287ad72a5SChristoph Hellwig if (min > max) { 198387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 198487ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 198587ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 198687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19879620cfbaSChristoph Hellwig return 0; 198887ad72a5SChristoph Hellwig } 198987ad72a5SChristoph Hellwig 199087ad72a5SChristoph Hellwig /* 199187ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 199287ad72a5SChristoph Hellwig */ 199387ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 199487ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 199587ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 199687ad72a5SChristoph Hellwig else 199787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 199887ad72a5SChristoph Hellwig } 199987ad72a5SChristoph Hellwig 200087ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 200192dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 200292dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 200392dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20049620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 200587ad72a5SChristoph Hellwig } 200687ad72a5SChristoph Hellwig 200792dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 200892dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 200992dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 201092dc6895SChristoph Hellwig } 201192dc6895SChristoph Hellwig 20129620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20139620cfbaSChristoph Hellwig if (ret) 201487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20159620cfbaSChristoph Hellwig return ret; 201657dacad5SJay Sternberg } 201757dacad5SJay Sternberg 2018612b7286SMing Lei /* 2019612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2020612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2021612b7286SMing Lei */ 2022612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20233b6592f7SJens Axboe { 2024612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2025612b7286SMing Lei unsigned int nr_read_queues; 2026c45b1fa2SMing Lei 20273b6592f7SJens Axboe /* 2028612b7286SMing Lei * If there is no interupt available for queues, ensure that 2029612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2030612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2031612b7286SMing Lei * 2032612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2033612b7286SMing Lei * write and read queues. 2034612b7286SMing Lei * 2035612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2036612b7286SMing Lei * queue. 20373b6592f7SJens Axboe */ 2038612b7286SMing Lei if (!nrirqs) { 2039612b7286SMing Lei nrirqs = 1; 2040612b7286SMing Lei nr_read_queues = 0; 2041612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2042612b7286SMing Lei nr_read_queues = 0; 2043612b7286SMing Lei } else if (write_queues >= nrirqs) { 2044612b7286SMing Lei nr_read_queues = 1; 20453b6592f7SJens Axboe } else { 2046612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20473b6592f7SJens Axboe } 2048612b7286SMing Lei 2049612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2050612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2051612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2052612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2053612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20543b6592f7SJens Axboe } 20553b6592f7SJens Axboe 20566451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20573b6592f7SJens Axboe { 20583b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20593b6592f7SJens Axboe struct irq_affinity affd = { 20603b6592f7SJens Axboe .pre_vectors = 1, 2061612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2062612b7286SMing Lei .priv = dev, 20633b6592f7SJens Axboe }; 20646451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20656451fe73SJens Axboe 20666451fe73SJens Axboe /* 20676451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20686451fe73SJens Axboe * queue left over for non-polled IO. 20696451fe73SJens Axboe */ 20706451fe73SJens Axboe this_p_queues = poll_queues; 20716451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20726451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20736451fe73SJens Axboe irq_queues = 1; 20746451fe73SJens Axboe } else { 2075c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20766451fe73SJens Axboe } 20776451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20783b6592f7SJens Axboe 2079612b7286SMing Lei /* Initialize for the single interrupt case */ 2080612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2081612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20823b6592f7SJens Axboe 208366341331SBenjamin Herrenschmidt /* 208466341331SBenjamin Herrenschmidt * Some Apple controllers require all queues to use the 208566341331SBenjamin Herrenschmidt * first vector. 208666341331SBenjamin Herrenschmidt */ 208766341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 208866341331SBenjamin Herrenschmidt irq_queues = 1; 208966341331SBenjamin Herrenschmidt 2090612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20913b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20923b6592f7SJens Axboe } 20933b6592f7SJens Axboe 20948fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20958fae268bSKeith Busch { 20968fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20978fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20988fae268bSKeith Busch } 20998fae268bSKeith Busch 210057dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 210157dacad5SJay Sternberg { 2102147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 210357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 210497f6ef64SXu Yu int result, nr_io_queues; 210597f6ef64SXu Yu unsigned long size; 210657dacad5SJay Sternberg 21073b6592f7SJens Axboe nr_io_queues = max_io_queues(); 2108d38e9f04SBenjamin Herrenschmidt 2109d38e9f04SBenjamin Herrenschmidt /* 2110d38e9f04SBenjamin Herrenschmidt * If tags are shared with admin queue (Apple bug), then 2111d38e9f04SBenjamin Herrenschmidt * make sure we only use one IO queue. 2112d38e9f04SBenjamin Herrenschmidt */ 2113d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2114d38e9f04SBenjamin Herrenschmidt nr_io_queues = 1; 2115d38e9f04SBenjamin Herrenschmidt 21169a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21179a0be7abSChristoph Hellwig if (result < 0) 211857dacad5SJay Sternberg return result; 21199a0be7abSChristoph Hellwig 2120f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2121a5229050SKeith Busch return 0; 212257dacad5SJay Sternberg 21234e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21244e224106SChristoph Hellwig 21250f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 212657dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 212757dacad5SJay Sternberg sizeof(struct nvme_command)); 212857dacad5SJay Sternberg if (result > 0) 212957dacad5SJay Sternberg dev->q_depth = result; 213057dacad5SJay Sternberg else 21310f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 213257dacad5SJay Sternberg } 213357dacad5SJay Sternberg 213457dacad5SJay Sternberg do { 213597f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 213697f6ef64SXu Yu result = nvme_remap_bar(dev, size); 213797f6ef64SXu Yu if (!result) 213857dacad5SJay Sternberg break; 213957dacad5SJay Sternberg if (!--nr_io_queues) 214057dacad5SJay Sternberg return -ENOMEM; 214157dacad5SJay Sternberg } while (1); 214257dacad5SJay Sternberg adminq->q_db = dev->dbs; 214357dacad5SJay Sternberg 21448fae268bSKeith Busch retry: 214557dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21460ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 214757dacad5SJay Sternberg 214857dacad5SJay Sternberg /* 214957dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 215057dacad5SJay Sternberg * setting up the full range we need. 215157dacad5SJay Sternberg */ 2152dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21533b6592f7SJens Axboe 21543b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 215522b55601SKeith Busch if (result <= 0) 2156dca51e78SChristoph Hellwig return -EIO; 21573b6592f7SJens Axboe 215822b55601SKeith Busch dev->num_vecs = result; 21594b04cc6aSJens Axboe result = max(result - 1, 1); 2160e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 216157dacad5SJay Sternberg 216257dacad5SJay Sternberg /* 216357dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 216457dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 216557dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 216657dacad5SJay Sternberg * number of interrupts. 216757dacad5SJay Sternberg */ 2168dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21697c349ddeSKeith Busch if (result) 2170d4875622SKeith Busch return result; 21714e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21728fae268bSKeith Busch 21738fae268bSKeith Busch result = nvme_create_io_queues(dev); 21748fae268bSKeith Busch if (result || dev->online_queues < 2) 21758fae268bSKeith Busch return result; 21768fae268bSKeith Busch 21778fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21788fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21798fae268bSKeith Busch nvme_disable_io_queues(dev); 21808fae268bSKeith Busch nvme_suspend_io_queues(dev); 21818fae268bSKeith Busch goto retry; 21828fae268bSKeith Busch } 21838fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21848fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21858fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21868fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21878fae268bSKeith Busch return 0; 218857dacad5SJay Sternberg } 218957dacad5SJay Sternberg 21902a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2191db3cbfffSKeith Busch { 2192db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2193db3cbfffSKeith Busch 2194db3cbfffSKeith Busch blk_mq_free_request(req); 2195d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2196db3cbfffSKeith Busch } 2197db3cbfffSKeith Busch 21982a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2199db3cbfffSKeith Busch { 2200db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2201db3cbfffSKeith Busch 2202d1ed6aa1SChristoph Hellwig if (error) 2203d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2204db3cbfffSKeith Busch 2205db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2206db3cbfffSKeith Busch } 2207db3cbfffSKeith Busch 2208db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2209db3cbfffSKeith Busch { 2210db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2211db3cbfffSKeith Busch struct request *req; 2212db3cbfffSKeith Busch struct nvme_command cmd; 2213db3cbfffSKeith Busch 2214db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2215db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2216db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2217db3cbfffSKeith Busch 2218eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2219db3cbfffSKeith Busch if (IS_ERR(req)) 2220db3cbfffSKeith Busch return PTR_ERR(req); 2221db3cbfffSKeith Busch 2222db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2223db3cbfffSKeith Busch req->end_io_data = nvmeq; 2224db3cbfffSKeith Busch 2225d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2226db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2227db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2228db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2229db3cbfffSKeith Busch return 0; 2230db3cbfffSKeith Busch } 2231db3cbfffSKeith Busch 22328fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2233db3cbfffSKeith Busch { 22345271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2235db3cbfffSKeith Busch unsigned long timeout; 2236db3cbfffSKeith Busch 2237db3cbfffSKeith Busch retry: 2238db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22395271edd4SChristoph Hellwig while (nr_queues > 0) { 22405271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2241db3cbfffSKeith Busch break; 22425271edd4SChristoph Hellwig nr_queues--; 22435271edd4SChristoph Hellwig sent++; 22445271edd4SChristoph Hellwig } 2245d1ed6aa1SChristoph Hellwig while (sent) { 2246d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2247d1ed6aa1SChristoph Hellwig 2248d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22495271edd4SChristoph Hellwig timeout); 2250db3cbfffSKeith Busch if (timeout == 0) 22515271edd4SChristoph Hellwig return false; 2252d1ed6aa1SChristoph Hellwig 2253d1ed6aa1SChristoph Hellwig sent--; 22545271edd4SChristoph Hellwig if (nr_queues) 2255db3cbfffSKeith Busch goto retry; 2256db3cbfffSKeith Busch } 22575271edd4SChristoph Hellwig return true; 2258db3cbfffSKeith Busch } 2259db3cbfffSKeith Busch 22605d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 226157dacad5SJay Sternberg { 22622b1b7e78SJianchao Wang int ret; 22632b1b7e78SJianchao Wang 22645bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2265c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 226657dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22678fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2268ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2269ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 227057dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 227157dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 227257dacad5SJay Sternberg dev->tagset.queue_depth = 227357dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2274d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 227557dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 227657dacad5SJay Sternberg dev->tagset.driver_data = dev; 227757dacad5SJay Sternberg 2278d38e9f04SBenjamin Herrenschmidt /* 2279d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2280d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2281d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2282d38e9f04SBenjamin Herrenschmidt */ 2283d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2284d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2285d38e9f04SBenjamin Herrenschmidt 22862b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22872b1b7e78SJianchao Wang if (ret) { 22882b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22892b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22905d02a5c1SKeith Busch return; 22912b1b7e78SJianchao Wang } 22925bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2293949928c1SKeith Busch } else { 2294949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2295949928c1SKeith Busch 2296949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2297949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 229857dacad5SJay Sternberg } 2299949928c1SKeith Busch 2300e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 230157dacad5SJay Sternberg } 230257dacad5SJay Sternberg 2303b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 230457dacad5SJay Sternberg { 2305b00a726aSKeith Busch int result = -ENOMEM; 230657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 230757dacad5SJay Sternberg 230857dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 230957dacad5SJay Sternberg return result; 231057dacad5SJay Sternberg 231157dacad5SJay Sternberg pci_set_master(pdev); 231257dacad5SJay Sternberg 23134fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 231457dacad5SJay Sternberg goto disable; 231557dacad5SJay Sternberg 23167a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 231757dacad5SJay Sternberg result = -ENODEV; 2318b00a726aSKeith Busch goto disable; 231957dacad5SJay Sternberg } 232057dacad5SJay Sternberg 232157dacad5SJay Sternberg /* 2322a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2323a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2324a5229050SKeith Busch * adjust this later. 232557dacad5SJay Sternberg */ 2326dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2327dca51e78SChristoph Hellwig if (result < 0) 2328dca51e78SChristoph Hellwig return result; 232957dacad5SJay Sternberg 233020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23317a67cbeaSChristoph Hellwig 233220d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2333b27c1e68Sweiping zhang io_queue_depth); 2334aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 233520d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23367a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23371f390c1fSStephan Günther 23381f390c1fSStephan Günther /* 233966341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 234066341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 234166341331SBenjamin Herrenschmidt * so we don't bother updating it here. 234266341331SBenjamin Herrenschmidt */ 234366341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 234466341331SBenjamin Herrenschmidt dev->io_sqes = 7; 234566341331SBenjamin Herrenschmidt else 2346c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 23471f390c1fSStephan Günther 23481f390c1fSStephan Günther /* 23491f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23501f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23511f390c1fSStephan Günther */ 23521f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23531f390c1fSStephan Günther dev->q_depth = 2; 23549bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23559bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23561f390c1fSStephan Günther dev->q_depth); 2357d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2358d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 235920d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2360d554b5e1SMartin K. Petersen dev->q_depth = 64; 2361d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2362d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23631f390c1fSStephan Günther } 23641f390c1fSStephan Günther 2365d38e9f04SBenjamin Herrenschmidt /* 2366d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2367d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2368d38e9f04SBenjamin Herrenschmidt */ 2369d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2370d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2371d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2372d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2373d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2374d38e9f04SBenjamin Herrenschmidt } 2375d38e9f04SBenjamin Herrenschmidt 2376d38e9f04SBenjamin Herrenschmidt 2377f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2378202021c1SStephen Bates 2379a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2380a0a3408eSKeith Busch pci_save_state(pdev); 238157dacad5SJay Sternberg return 0; 238257dacad5SJay Sternberg 238357dacad5SJay Sternberg disable: 238457dacad5SJay Sternberg pci_disable_device(pdev); 238557dacad5SJay Sternberg return result; 238657dacad5SJay Sternberg } 238757dacad5SJay Sternberg 238857dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 238957dacad5SJay Sternberg { 2390b00a726aSKeith Busch if (dev->bar) 2391b00a726aSKeith Busch iounmap(dev->bar); 2392a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2393b00a726aSKeith Busch } 2394b00a726aSKeith Busch 2395b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2396b00a726aSKeith Busch { 239757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 239857dacad5SJay Sternberg 2399dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 240057dacad5SJay Sternberg 2401a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2402a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 240357dacad5SJay Sternberg pci_disable_device(pdev); 240457dacad5SJay Sternberg } 2405a0a3408eSKeith Busch } 240657dacad5SJay Sternberg 2407a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 240857dacad5SJay Sternberg { 2409e43269e6SKeith Busch bool dead = true, freeze = false; 2410302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 241157dacad5SJay Sternberg 241277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2413302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2414302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2415302ad8ccSKeith Busch 2416ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2417e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2418e43269e6SKeith Busch freeze = true; 2419302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2420e43269e6SKeith Busch } 2421302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2422302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 242357dacad5SJay Sternberg } 2424c21377f8SGabriel Krisman Bertazi 2425302ad8ccSKeith Busch /* 2426302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2427302ad8ccSKeith Busch * doing a safe shutdown. 2428302ad8ccSKeith Busch */ 2429e43269e6SKeith Busch if (!dead && shutdown && freeze) 2430302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 243187ad72a5SChristoph Hellwig 24329a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24339a915a5bSJianchao Wang 243464ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24358fae268bSKeith Busch nvme_disable_io_queues(dev); 2436a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 243757dacad5SJay Sternberg } 24388fae268bSKeith Busch nvme_suspend_io_queues(dev); 24398fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2440b00a726aSKeith Busch nvme_pci_disable(dev); 2441fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 244257dacad5SJay Sternberg 2443e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2444e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2445622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2446622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2447302ad8ccSKeith Busch 2448302ad8ccSKeith Busch /* 2449302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2450302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2451302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2452302ad8ccSKeith Busch */ 2453c8e9e9b7SKeith Busch if (shutdown) { 2454302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2455c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2456c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2457c8e9e9b7SKeith Busch } 245877bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 245957dacad5SJay Sternberg } 246057dacad5SJay Sternberg 2461c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2462c1ac9a4bSKeith Busch { 2463c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2464c1ac9a4bSKeith Busch return -EBUSY; 2465c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2466c1ac9a4bSKeith Busch return 0; 2467c1ac9a4bSKeith Busch } 2468c1ac9a4bSKeith Busch 246957dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 247057dacad5SJay Sternberg { 247157dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 247257dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 247357dacad5SJay Sternberg if (!dev->prp_page_pool) 247457dacad5SJay Sternberg return -ENOMEM; 247557dacad5SJay Sternberg 247657dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 247757dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 247857dacad5SJay Sternberg 256, 256, 0); 247957dacad5SJay Sternberg if (!dev->prp_small_pool) { 248057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248157dacad5SJay Sternberg return -ENOMEM; 248257dacad5SJay Sternberg } 248357dacad5SJay Sternberg return 0; 248457dacad5SJay Sternberg } 248557dacad5SJay Sternberg 248657dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 248757dacad5SJay Sternberg { 248857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248957dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 249057dacad5SJay Sternberg } 249157dacad5SJay Sternberg 2492770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2493770597ecSKeith Busch { 2494770597ecSKeith Busch if (dev->tagset.tags) 2495770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2496770597ecSKeith Busch dev->ctrl.tagset = NULL; 2497770597ecSKeith Busch } 2498770597ecSKeith Busch 24991673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 250057dacad5SJay Sternberg { 25011673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 250257dacad5SJay Sternberg 2503f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 250457dacad5SJay Sternberg put_device(dev->dev); 2505770597ecSKeith Busch nvme_free_tagset(dev); 25061c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 25071c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 250857dacad5SJay Sternberg kfree(dev->queues); 2509e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2510943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 251157dacad5SJay Sternberg kfree(dev); 251257dacad5SJay Sternberg } 251357dacad5SJay Sternberg 25147c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2515f58944e2SKeith Busch { 2516c1ac9a4bSKeith Busch /* 2517c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2518c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2519c1ac9a4bSKeith Busch */ 2520c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2521d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 252269d9a99cSKeith Busch nvme_dev_disable(dev, false); 25239f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 252403e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2525f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2526f58944e2SKeith Busch } 2527f58944e2SKeith Busch 2528fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 252957dacad5SJay Sternberg { 2530d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2531d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2532a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2533e71afda4SChaitanya Kulkarni int result; 253457dacad5SJay Sternberg 2535e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2536e71afda4SChaitanya Kulkarni result = -ENODEV; 2537fd634f41SChristoph Hellwig goto out; 2538e71afda4SChaitanya Kulkarni } 2539fd634f41SChristoph Hellwig 2540fd634f41SChristoph Hellwig /* 2541fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2542fd634f41SChristoph Hellwig * moving on. 2543fd634f41SChristoph Hellwig */ 2544b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2545a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2546d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2547fd634f41SChristoph Hellwig 25485c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2549b00a726aSKeith Busch result = nvme_pci_enable(dev); 255057dacad5SJay Sternberg if (result) 25514726bcf3SKeith Busch goto out_unlock; 255257dacad5SJay Sternberg 255301ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 255457dacad5SJay Sternberg if (result) 25554726bcf3SKeith Busch goto out_unlock; 255657dacad5SJay Sternberg 255757dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 255857dacad5SJay Sternberg if (result) 25594726bcf3SKeith Busch goto out_unlock; 256057dacad5SJay Sternberg 2561943e942eSJens Axboe /* 2562943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2563943e942eSJens Axboe * over a single page. 2564943e942eSJens Axboe */ 25657637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 25667637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2567943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2568a48bc520SChristoph Hellwig 2569a48bc520SChristoph Hellwig /* 2570a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2571a48bc520SChristoph Hellwig */ 2572a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2573a48bc520SChristoph Hellwig 25745c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25755c959d73SKeith Busch 25765c959d73SKeith Busch /* 25775c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25785c959d73SKeith Busch * initializing procedure here. 25795c959d73SKeith Busch */ 25805c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25815c959d73SKeith Busch dev_warn(dev->ctrl.device, 25825c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2583cee6c269SMinwoo Im result = -EBUSY; 25845c959d73SKeith Busch goto out; 25855c959d73SKeith Busch } 2586943e942eSJens Axboe 2587ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2588ce4541f4SChristoph Hellwig if (result) 2589f58944e2SKeith Busch goto out; 2590ce4541f4SChristoph Hellwig 2591e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2592e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25934f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25944f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2595e286bcfcSScott Bauer else if (was_suspend) 25964f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2597e286bcfcSScott Bauer } else { 2598e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2599e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2600e286bcfcSScott Bauer } 2601a98e58e5SScott Bauer 2602f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2603f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2604f9f38e33SHelen Koike if (result) 2605f9f38e33SHelen Koike dev_warn(dev->dev, 2606f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2607f9f38e33SHelen Koike } 2608f9f38e33SHelen Koike 26099620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 26109620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26119620cfbaSChristoph Hellwig if (result < 0) 26129620cfbaSChristoph Hellwig goto out; 26139620cfbaSChristoph Hellwig } 261487ad72a5SChristoph Hellwig 261557dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 261657dacad5SJay Sternberg if (result) 2617f58944e2SKeith Busch goto out; 261857dacad5SJay Sternberg 261921f033f7SKeith Busch /* 262057dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 262157dacad5SJay Sternberg * any working I/O queue. 262257dacad5SJay Sternberg */ 262357dacad5SJay Sternberg if (dev->online_queues < 2) { 26241b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26253b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26265bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2627770597ecSKeith Busch nvme_free_tagset(dev); 262857dacad5SJay Sternberg } else { 262925646264SKeith Busch nvme_start_queues(&dev->ctrl); 2630302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26315d02a5c1SKeith Busch nvme_dev_add(dev); 2632302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 263357dacad5SJay Sternberg } 263457dacad5SJay Sternberg 26352b1b7e78SJianchao Wang /* 26362b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26372b1b7e78SJianchao Wang * recovery. 26382b1b7e78SJianchao Wang */ 26395d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 26402b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26415d02a5c1SKeith Busch "failed to mark controller live state\n"); 2642e71afda4SChaitanya Kulkarni result = -ENODEV; 2643bb8d261eSChristoph Hellwig goto out; 2644bb8d261eSChristoph Hellwig } 264592911a55SChristoph Hellwig 2646d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 264757dacad5SJay Sternberg return; 264857dacad5SJay Sternberg 26494726bcf3SKeith Busch out_unlock: 26504726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 265157dacad5SJay Sternberg out: 26527c1ce408SChaitanya Kulkarni if (result) 26537c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 26547c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 26557c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 265657dacad5SJay Sternberg } 265757dacad5SJay Sternberg 26585c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 265957dacad5SJay Sternberg { 26605c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 266157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266257dacad5SJay Sternberg 266357dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2664921920abSKeith Busch device_release_driver(&pdev->dev); 26651673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 266657dacad5SJay Sternberg } 266757dacad5SJay Sternberg 26681c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 266957dacad5SJay Sternberg { 26701c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26711c63dc66SChristoph Hellwig return 0; 267257dacad5SJay Sternberg } 26731c63dc66SChristoph Hellwig 26745fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26755fd4ce1bSChristoph Hellwig { 26765fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26775fd4ce1bSChristoph Hellwig return 0; 26785fd4ce1bSChristoph Hellwig } 26795fd4ce1bSChristoph Hellwig 26807fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26817fd8930fSChristoph Hellwig { 26823a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 26837fd8930fSChristoph Hellwig return 0; 26847fd8930fSChristoph Hellwig } 26857fd8930fSChristoph Hellwig 268697c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 268797c12223SKeith Busch { 268897c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 268997c12223SKeith Busch 269097c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 269197c12223SKeith Busch } 269297c12223SKeith Busch 26931c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26941a353d85SMing Lin .name = "pcie", 2695e439bb12SSagi Grimberg .module = THIS_MODULE, 2696e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2697e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26981c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26995fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 27007fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 27011673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2702f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 270397c12223SKeith Busch .get_address = nvme_pci_get_address, 27041c63dc66SChristoph Hellwig }; 270557dacad5SJay Sternberg 2706b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2707b00a726aSKeith Busch { 2708b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2709b00a726aSKeith Busch 2710a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2711b00a726aSKeith Busch return -ENODEV; 2712b00a726aSKeith Busch 271397f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2714b00a726aSKeith Busch goto release; 2715b00a726aSKeith Busch 2716b00a726aSKeith Busch return 0; 2717b00a726aSKeith Busch release: 2718a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2719b00a726aSKeith Busch return -ENODEV; 2720b00a726aSKeith Busch } 2721b00a726aSKeith Busch 27228427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2723ff5350a8SAndy Lutomirski { 2724ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2725ff5350a8SAndy Lutomirski /* 2726ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2727ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2728ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2729ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2730ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2731ff5350a8SAndy Lutomirski * laptops. 2732ff5350a8SAndy Lutomirski */ 2733ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2734ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2735ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2736ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27378427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27388427bbc2SKai-Heng Feng /* 27398427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2740467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2741467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2742467c77d4SJarosław Janik * ASUS PRIME Z370-A 27438427bbc2SKai-Heng Feng */ 27448427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2745467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2746467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27478427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 27481fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 27491fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 27501fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 27511fae37acSShyjumon N /* 27521fae37acSShyjumon N * Forcing to use host managed nvme power settings for 27531fae37acSShyjumon N * lowest idle power with quick resume latency on 27541fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 27551fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 27561fae37acSShyjumon N */ 27571fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 27581fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 27591fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2760ff5350a8SAndy Lutomirski } 2761ff5350a8SAndy Lutomirski 2762ff5350a8SAndy Lutomirski return 0; 2763ff5350a8SAndy Lutomirski } 2764ff5350a8SAndy Lutomirski 276518119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 276618119775SKeith Busch { 276718119775SKeith Busch struct nvme_dev *dev = data; 276880f513b5SKeith Busch 2769bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 277018119775SKeith Busch flush_work(&dev->ctrl.scan_work); 277180f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 277218119775SKeith Busch } 277318119775SKeith Busch 277457dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 277557dacad5SJay Sternberg { 277657dacad5SJay Sternberg int node, result = -ENOMEM; 277757dacad5SJay Sternberg struct nvme_dev *dev; 2778ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2779943e942eSJens Axboe size_t alloc_size; 278057dacad5SJay Sternberg 278157dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 278257dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27832fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 278457dacad5SJay Sternberg 278557dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 278657dacad5SJay Sternberg if (!dev) 278757dacad5SJay Sternberg return -ENOMEM; 2788147b27e4SSagi Grimberg 27893b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27903b6592f7SJens Axboe GFP_KERNEL, node); 279157dacad5SJay Sternberg if (!dev->queues) 279257dacad5SJay Sternberg goto free; 279357dacad5SJay Sternberg 279457dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 279557dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 279657dacad5SJay Sternberg 2797b00a726aSKeith Busch result = nvme_dev_map(dev); 2798b00a726aSKeith Busch if (result) 2799b00c9b7aSChristophe JAILLET goto put_pci; 2800b00a726aSKeith Busch 2801d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 28025c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 280377bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2804f3ca80fcSChristoph Hellwig 2805f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2806f3ca80fcSChristoph Hellwig if (result) 2807b00c9b7aSChristophe JAILLET goto unmap; 2808f3ca80fcSChristoph Hellwig 28098427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2810ff5350a8SAndy Lutomirski 2811943e942eSJens Axboe /* 2812943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2813943e942eSJens Axboe * command we support. 2814943e942eSJens Axboe */ 2815943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2816943e942eSJens Axboe NVME_MAX_SEGS, true); 2817943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2818943e942eSJens Axboe 2819943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2820943e942eSJens Axboe mempool_kfree, 2821943e942eSJens Axboe (void *) alloc_size, 2822943e942eSJens Axboe GFP_KERNEL, node); 2823943e942eSJens Axboe if (!dev->iod_mempool) { 2824943e942eSJens Axboe result = -ENOMEM; 2825943e942eSJens Axboe goto release_pools; 2826943e942eSJens Axboe } 2827943e942eSJens Axboe 2828b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2829b6e44b4cSKeith Busch quirks); 2830b6e44b4cSKeith Busch if (result) 2831b6e44b4cSKeith Busch goto release_mempool; 2832b6e44b4cSKeith Busch 28331b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 28341b3c47c1SSagi Grimberg 2835bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 283680f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 283718119775SKeith Busch async_schedule(nvme_async_probe, dev); 28384caff8fcSSagi Grimberg 283957dacad5SJay Sternberg return 0; 284057dacad5SJay Sternberg 2841b6e44b4cSKeith Busch release_mempool: 2842b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 284357dacad5SJay Sternberg release_pools: 284457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2845b00c9b7aSChristophe JAILLET unmap: 2846b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 284757dacad5SJay Sternberg put_pci: 284857dacad5SJay Sternberg put_device(dev->dev); 284957dacad5SJay Sternberg free: 285057dacad5SJay Sternberg kfree(dev->queues); 285157dacad5SJay Sternberg kfree(dev); 285257dacad5SJay Sternberg return result; 285357dacad5SJay Sternberg } 285457dacad5SJay Sternberg 2855775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 285657dacad5SJay Sternberg { 285757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2858c1ac9a4bSKeith Busch 2859c1ac9a4bSKeith Busch /* 2860c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2861c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2862c1ac9a4bSKeith Busch * with ->remove(). 2863c1ac9a4bSKeith Busch */ 2864c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2865c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2866775755edSChristoph Hellwig } 286757dacad5SJay Sternberg 2868775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2869775755edSChristoph Hellwig { 2870f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2871c1ac9a4bSKeith Busch 2872c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2873c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 287457dacad5SJay Sternberg } 287557dacad5SJay Sternberg 287657dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 287757dacad5SJay Sternberg { 287857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2879c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 288057dacad5SJay Sternberg } 288157dacad5SJay Sternberg 2882f58944e2SKeith Busch /* 2883f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2884f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2885f58944e2SKeith Busch * order to proceed. 2886f58944e2SKeith Busch */ 288757dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 288857dacad5SJay Sternberg { 288957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 289057dacad5SJay Sternberg 2891bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 289257dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28930ff9d4e1SKeith Busch 28946db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28950ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28961d39e692SKeith Busch nvme_dev_disable(dev, true); 2897cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28986db28edaSKeith Busch } 28990ff9d4e1SKeith Busch 2900d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2901d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2902d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2903a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 29049fe5c59fSKeith Busch nvme_release_cmb(dev); 290587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 290657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 290757dacad5SJay Sternberg nvme_free_queues(dev, 0); 2908d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 290957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2910b00a726aSKeith Busch nvme_dev_unmap(dev); 29111673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 291257dacad5SJay Sternberg } 291357dacad5SJay Sternberg 291457dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2915d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2916d916b1beSKeith Busch { 2917d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2918d916b1beSKeith Busch } 2919d916b1beSKeith Busch 2920d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2921d916b1beSKeith Busch { 2922d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2923d916b1beSKeith Busch } 2924d916b1beSKeith Busch 2925d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2926d916b1beSKeith Busch { 2927d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2928d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2929d916b1beSKeith Busch 29304eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 2931d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2932c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 2933d916b1beSKeith Busch return 0; 2934d916b1beSKeith Busch } 2935d916b1beSKeith Busch 293657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 293757dacad5SJay Sternberg { 293857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 293957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2940d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2941d916b1beSKeith Busch int ret = -EBUSY; 2942d916b1beSKeith Busch 29434eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 29444eaefe8cSRafael J. Wysocki 2945d916b1beSKeith Busch /* 2946d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 2947d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 2948d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 2949d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 2950d916b1beSKeith Busch * device does not support any non-default power states, shut down the 2951d916b1beSKeith Busch * device fully. 29524eaefe8cSRafael J. Wysocki * 29534eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 29544eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 29554eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 29564eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 2957d916b1beSKeith Busch */ 29584eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 2959cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 2960c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2961c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 2962d916b1beSKeith Busch 2963d916b1beSKeith Busch nvme_start_freeze(ctrl); 2964d916b1beSKeith Busch nvme_wait_freeze(ctrl); 2965d916b1beSKeith Busch nvme_sync_queues(ctrl); 2966d916b1beSKeith Busch 29675d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 2968d916b1beSKeith Busch goto unfreeze; 2969d916b1beSKeith Busch 2970d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2971d916b1beSKeith Busch if (ret < 0) 2972d916b1beSKeith Busch goto unfreeze; 2973d916b1beSKeith Busch 29747cbb5c6fSMario Limonciello /* 29757cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 29767cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 29777cbb5c6fSMario Limonciello * want pci interfering. 29787cbb5c6fSMario Limonciello */ 29797cbb5c6fSMario Limonciello pci_save_state(pdev); 29807cbb5c6fSMario Limonciello 2981d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 2982d916b1beSKeith Busch if (ret < 0) 2983d916b1beSKeith Busch goto unfreeze; 2984d916b1beSKeith Busch 2985d916b1beSKeith Busch if (ret) { 29867cbb5c6fSMario Limonciello /* discard the saved state */ 29877cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 29887cbb5c6fSMario Limonciello 2989d916b1beSKeith Busch /* 2990d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 299105d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 2992d916b1beSKeith Busch */ 2993c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 2994d916b1beSKeith Busch ctrl->npss = 0; 2995d916b1beSKeith Busch } 2996d916b1beSKeith Busch unfreeze: 2997d916b1beSKeith Busch nvme_unfreeze(ctrl); 2998d916b1beSKeith Busch return ret; 2999d916b1beSKeith Busch } 3000d916b1beSKeith Busch 3001d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3002d916b1beSKeith Busch { 3003d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3004c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 300557dacad5SJay Sternberg } 300657dacad5SJay Sternberg 3007d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 300857dacad5SJay Sternberg { 300957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 301057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 301157dacad5SJay Sternberg 3012c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 301357dacad5SJay Sternberg } 301457dacad5SJay Sternberg 301521774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3016d916b1beSKeith Busch .suspend = nvme_suspend, 3017d916b1beSKeith Busch .resume = nvme_resume, 3018d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3019d916b1beSKeith Busch .thaw = nvme_simple_resume, 3020d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3021d916b1beSKeith Busch .restore = nvme_simple_resume, 3022d916b1beSKeith Busch }; 3023d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 302457dacad5SJay Sternberg 3025a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3026a0a3408eSKeith Busch pci_channel_state_t state) 3027a0a3408eSKeith Busch { 3028a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3029a0a3408eSKeith Busch 3030a0a3408eSKeith Busch /* 3031a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3032a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3033a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3034a0a3408eSKeith Busch */ 3035a0a3408eSKeith Busch switch (state) { 3036a0a3408eSKeith Busch case pci_channel_io_normal: 3037a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3038a0a3408eSKeith Busch case pci_channel_io_frozen: 3039d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3040d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3041a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3042a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3043a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3044d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3045d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3046a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3047a0a3408eSKeith Busch } 3048a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3049a0a3408eSKeith Busch } 3050a0a3408eSKeith Busch 3051a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3052a0a3408eSKeith Busch { 3053a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3054a0a3408eSKeith Busch 30551b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3056a0a3408eSKeith Busch pci_restore_state(pdev); 3057d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3058a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3059a0a3408eSKeith Busch } 3060a0a3408eSKeith Busch 3061a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3062a0a3408eSKeith Busch { 306372cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 306472cd4cc2SKeith Busch 306572cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3066a0a3408eSKeith Busch } 3067a0a3408eSKeith Busch 306857dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 306957dacad5SJay Sternberg .error_detected = nvme_error_detected, 307057dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 307157dacad5SJay Sternberg .resume = nvme_error_resume, 3072775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3073775755edSChristoph Hellwig .reset_done = nvme_reset_done, 307457dacad5SJay Sternberg }; 307557dacad5SJay Sternberg 307657dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3077106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 307808095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3079e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 308099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 308199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3082e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 308399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 308499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3085e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3086f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 3087f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3088f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 308950af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 30909abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 30916c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 30926c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 30936299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 30946299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3095540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 30967b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 30977b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 30980302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 30990302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 310054adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 310154adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 31028c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 31038c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3104015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3105015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3106d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3107d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3108d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3109d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3110608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3111608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3112608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3113608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3114ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3115ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 311608b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 311708b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3118f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3119f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3120f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 312157dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 312298f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 312398f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3124124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 312566341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 312666341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3127d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3128d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 312957dacad5SJay Sternberg { 0, } 313057dacad5SJay Sternberg }; 313157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 313257dacad5SJay Sternberg 313357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 313457dacad5SJay Sternberg .name = "nvme", 313557dacad5SJay Sternberg .id_table = nvme_id_table, 313657dacad5SJay Sternberg .probe = nvme_probe, 313757dacad5SJay Sternberg .remove = nvme_remove, 313857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3139d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 314057dacad5SJay Sternberg .driver = { 314157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 314257dacad5SJay Sternberg }, 3143d916b1beSKeith Busch #endif 314474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 314557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 314657dacad5SJay Sternberg }; 314757dacad5SJay Sternberg 314857dacad5SJay Sternberg static int __init nvme_init(void) 314957dacad5SJay Sternberg { 315081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 315181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 315281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3153612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 315417c33167SKeith Busch 315517c33167SKeith Busch write_queues = min(write_queues, num_possible_cpus()); 315617c33167SKeith Busch poll_queues = min(poll_queues, num_possible_cpus()); 31579a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 315857dacad5SJay Sternberg } 315957dacad5SJay Sternberg 316057dacad5SJay Sternberg static void __exit nvme_exit(void) 316157dacad5SJay Sternberg { 316257dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 316303e0f3a6SMing Lei flush_workqueue(nvme_wq); 316457dacad5SJay Sternberg } 316557dacad5SJay Sternberg 316657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 316757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 316857dacad5SJay Sternberg MODULE_VERSION("1.0"); 316957dacad5SJay Sternberg module_init(nvme_init); 317057dacad5SJay Sternberg module_exit(nvme_exit); 3171