15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 2157dacad5SJay Sternberg #include <linux/t10-pi.h> 2257dacad5SJay Sternberg #include <linux/types.h> 239cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 24a98e58e5SScott Bauer #include <linux/sed-opal.h> 250f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2657dacad5SJay Sternberg 27604c01d5Syupeng #include "trace.h" 2857dacad5SJay Sternberg #include "nvme.h" 2957dacad5SJay Sternberg 3057dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3157dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3257dacad5SJay Sternberg 33a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 34adf68f21SChristoph Hellwig 35943e942eSJens Axboe /* 36943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 37943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 38943e942eSJens Axboe */ 39943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 40943e942eSJens Axboe #define NVME_MAX_SEGS 127 41943e942eSJens Axboe 4257dacad5SJay Sternberg static int use_threaded_interrupts; 4357dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4457dacad5SJay Sternberg 4557dacad5SJay Sternberg static bool use_cmb_sqes = true; 4669f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4757dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4857dacad5SJay Sternberg 4987ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5087ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5187ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5287ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5357dacad5SJay Sternberg 54a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 55a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 56a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 57a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 58a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 59a7a7cbe3SChaitanya Kulkarni 60b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 61b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 62b27c1e68Sweiping zhang .set = io_queue_depth_set, 63b27c1e68Sweiping zhang .get = param_get_int, 64b27c1e68Sweiping zhang }; 65b27c1e68Sweiping zhang 66b27c1e68Sweiping zhang static int io_queue_depth = 1024; 67b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 68b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 69b27c1e68Sweiping zhang 703b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 713b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 723b6592f7SJens Axboe .set = queue_count_set, 733b6592f7SJens Axboe .get = param_get_int, 743b6592f7SJens Axboe }; 753b6592f7SJens Axboe 763b6592f7SJens Axboe static int write_queues; 773b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 783b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 793b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 803b6592f7SJens Axboe "will share a queue set."); 813b6592f7SJens Axboe 82a4668d9bSJens Axboe static int poll_queues = 0; 834b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 844b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 854b04cc6aSJens Axboe 861c63dc66SChristoph Hellwig struct nvme_dev; 871c63dc66SChristoph Hellwig struct nvme_queue; 8857dacad5SJay Sternberg 89a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 9157dacad5SJay Sternberg 9257dacad5SJay Sternberg /* 931c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 941c63dc66SChristoph Hellwig */ 951c63dc66SChristoph Hellwig struct nvme_dev { 96147b27e4SSagi Grimberg struct nvme_queue *queues; 971c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 981c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 991c63dc66SChristoph Hellwig u32 __iomem *dbs; 1001c63dc66SChristoph Hellwig struct device *dev; 1011c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1021c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1031c63dc66SChristoph Hellwig unsigned online_queues; 1041c63dc66SChristoph Hellwig unsigned max_qid; 105e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10622b55601SKeith Busch unsigned int num_vecs; 1071c63dc66SChristoph Hellwig int q_depth; 1081c63dc66SChristoph Hellwig u32 db_stride; 1091c63dc66SChristoph Hellwig void __iomem *bar; 11097f6ef64SXu Yu unsigned long bar_mapped_size; 1115c8809e6SChristoph Hellwig struct work_struct remove_work; 11277bf25eaSKeith Busch struct mutex shutdown_lock; 1131c63dc66SChristoph Hellwig bool subsystem; 1141c63dc66SChristoph Hellwig u64 cmb_size; 1150f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1161c63dc66SChristoph Hellwig u32 cmbsz; 117202021c1SStephen Bates u32 cmbloc; 1181c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 11987ad72a5SChristoph Hellwig 120943e942eSJens Axboe mempool_t *iod_mempool; 121943e942eSJens Axboe 12287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 123f9f38e33SHelen Koike u32 *dbbuf_dbs; 124f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 125f9f38e33SHelen Koike u32 *dbbuf_eis; 126f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12787ad72a5SChristoph Hellwig 12887ad72a5SChristoph Hellwig /* host memory buffer support: */ 12987ad72a5SChristoph Hellwig u64 host_mem_size; 13087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1314033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13457dacad5SJay Sternberg }; 13557dacad5SJay Sternberg 136b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 137b27c1e68Sweiping zhang { 138b27c1e68Sweiping zhang int n = 0, ret; 139b27c1e68Sweiping zhang 140b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 141b27c1e68Sweiping zhang if (ret != 0 || n < 2) 142b27c1e68Sweiping zhang return -EINVAL; 143b27c1e68Sweiping zhang 144b27c1e68Sweiping zhang return param_set_int(val, kp); 145b27c1e68Sweiping zhang } 146b27c1e68Sweiping zhang 1473b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1483b6592f7SJens Axboe { 1493b6592f7SJens Axboe int n = 0, ret; 1503b6592f7SJens Axboe 1513b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 152e895fedfSBart Van Assche if (ret) 153e895fedfSBart Van Assche return ret; 1543b6592f7SJens Axboe if (n > num_possible_cpus()) 1553b6592f7SJens Axboe n = num_possible_cpus(); 1563b6592f7SJens Axboe 1573b6592f7SJens Axboe return param_set_int(val, kp); 1583b6592f7SJens Axboe } 1593b6592f7SJens Axboe 160f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 161f9f38e33SHelen Koike { 162f9f38e33SHelen Koike return qid * 2 * stride; 163f9f38e33SHelen Koike } 164f9f38e33SHelen Koike 165f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 166f9f38e33SHelen Koike { 167f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 168f9f38e33SHelen Koike } 169f9f38e33SHelen Koike 1701c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1711c63dc66SChristoph Hellwig { 1721c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1731c63dc66SChristoph Hellwig } 1741c63dc66SChristoph Hellwig 17557dacad5SJay Sternberg /* 17657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 17757dacad5SJay Sternberg * commands and one for I/O commands). 17857dacad5SJay Sternberg */ 17957dacad5SJay Sternberg struct nvme_queue { 18057dacad5SJay Sternberg struct nvme_dev *dev; 1811ab0cd69SJens Axboe spinlock_t sq_lock; 18257dacad5SJay Sternberg struct nvme_command *sq_cmds; 1833a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1843a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 18557dacad5SJay Sternberg volatile struct nvme_completion *cqes; 18657dacad5SJay Sternberg struct blk_mq_tags **tags; 18757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 18857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 18957dacad5SJay Sternberg u32 __iomem *q_db; 19057dacad5SJay Sternberg u16 q_depth; 1917c349ddeSKeith Busch u16 cq_vector; 19257dacad5SJay Sternberg u16 sq_tail; 19304f3eafdSJens Axboe u16 last_sq_tail; 19457dacad5SJay Sternberg u16 cq_head; 19568fa9dbeSJens Axboe u16 last_cq_head; 19657dacad5SJay Sternberg u16 qid; 19757dacad5SJay Sternberg u8 cq_phase; 1984e224106SChristoph Hellwig unsigned long flags; 1994e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 201d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2027c349ddeSKeith Busch #define NVMEQ_POLLED 3 203f9f38e33SHelen Koike u32 *dbbuf_sq_db; 204f9f38e33SHelen Koike u32 *dbbuf_cq_db; 205f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 206f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 207d1ed6aa1SChristoph Hellwig struct completion delete_done; 20857dacad5SJay Sternberg }; 20957dacad5SJay Sternberg 21057dacad5SJay Sternberg /* 2119b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2129b048119SChristoph Hellwig * 2139b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2149b048119SChristoph Hellwig * to the actual struct scatterlist. 21571bd150cSChristoph Hellwig */ 21671bd150cSChristoph Hellwig struct nvme_iod { 217d49187e9SChristoph Hellwig struct nvme_request req; 218f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 219a7a7cbe3SChaitanya Kulkarni bool use_sgl; 220f4800d6dSChristoph Hellwig int aborted; 22171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22371bd150cSChristoph Hellwig dma_addr_t first_dma; 224dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 225783b94bdSChristoph Hellwig dma_addr_t meta_dma; 226f4800d6dSChristoph Hellwig struct scatterlist *sg; 22757dacad5SJay Sternberg }; 22857dacad5SJay Sternberg 22957dacad5SJay Sternberg /* 23057dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23157dacad5SJay Sternberg */ 23257dacad5SJay Sternberg static inline void _nvme_check_size(void) 23357dacad5SJay Sternberg { 23457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 23557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 23657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 23757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 23857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2420add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2430add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 246f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 247f9f38e33SHelen Koike } 248f9f38e33SHelen Koike 2493b6592f7SJens Axboe static unsigned int max_io_queues(void) 2503b6592f7SJens Axboe { 2514b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2523b6592f7SJens Axboe } 2533b6592f7SJens Axboe 2543b6592f7SJens Axboe static unsigned int max_queue_count(void) 2553b6592f7SJens Axboe { 2563b6592f7SJens Axboe /* IO queues + admin queue */ 2573b6592f7SJens Axboe return 1 + max_io_queues(); 2583b6592f7SJens Axboe } 2593b6592f7SJens Axboe 260f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 261f9f38e33SHelen Koike { 2623b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 266f9f38e33SHelen Koike { 267f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike if (dev->dbbuf_dbs) 270f9f38e33SHelen Koike return 0; 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 273f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 274f9f38e33SHelen Koike GFP_KERNEL); 275f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 276f9f38e33SHelen Koike return -ENOMEM; 277f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 279f9f38e33SHelen Koike GFP_KERNEL); 280f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 281f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 282f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 283f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 284f9f38e33SHelen Koike return -ENOMEM; 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike return 0; 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 291f9f38e33SHelen Koike { 292f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 295f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 296f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 297f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike if (dev->dbbuf_eis) { 300f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 301f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 302f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike } 305f9f38e33SHelen Koike 306f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 307f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 310f9f38e33SHelen Koike return; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 313f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 314f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 315f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 316f9f38e33SHelen Koike } 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 319f9f38e33SHelen Koike { 320f9f38e33SHelen Koike struct nvme_command c; 321f9f38e33SHelen Koike 322f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 323f9f38e33SHelen Koike return; 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 326f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 327f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 328f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3319bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 332f9f38e33SHelen Koike /* Free memory and continue on */ 333f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 334f9f38e33SHelen Koike } 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 338f9f38e33SHelen Koike { 339f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 343f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 344f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 345f9f38e33SHelen Koike { 346f9f38e33SHelen Koike if (dbbuf_db) { 347f9f38e33SHelen Koike u16 old_value; 348f9f38e33SHelen Koike 349f9f38e33SHelen Koike /* 350f9f38e33SHelen Koike * Ensure that the queue is written before updating 351f9f38e33SHelen Koike * the doorbell in memory 352f9f38e33SHelen Koike */ 353f9f38e33SHelen Koike wmb(); 354f9f38e33SHelen Koike 355f9f38e33SHelen Koike old_value = *dbbuf_db; 356f9f38e33SHelen Koike *dbbuf_db = value; 357f9f38e33SHelen Koike 358f1ed3df2SMichal Wnukowski /* 359f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 360f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 361f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 362f1ed3df2SMichal Wnukowski * the doorbell. 363f1ed3df2SMichal Wnukowski */ 364f1ed3df2SMichal Wnukowski mb(); 365f1ed3df2SMichal Wnukowski 366f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 367f9f38e33SHelen Koike return false; 368f9f38e33SHelen Koike } 369f9f38e33SHelen Koike 370f9f38e33SHelen Koike return true; 37157dacad5SJay Sternberg } 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg /* 37457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37657dacad5SJay Sternberg * the I/O. 37757dacad5SJay Sternberg */ 37857dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 37957dacad5SJay Sternberg { 3805fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3815fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 38257dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38357dacad5SJay Sternberg } 38457dacad5SJay Sternberg 385a7a7cbe3SChaitanya Kulkarni /* 386a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 387a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 388a7a7cbe3SChaitanya Kulkarni */ 389a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 390f4800d6dSChristoph Hellwig { 391a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 392f4800d6dSChristoph Hellwig } 393f4800d6dSChristoph Hellwig 394a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 395a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 39657dacad5SJay Sternberg { 397a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 398a7a7cbe3SChaitanya Kulkarni 399a7a7cbe3SChaitanya Kulkarni if (use_sgl) 400a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 401a7a7cbe3SChaitanya Kulkarni else 402a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 403a7a7cbe3SChaitanya Kulkarni 404a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 405a7a7cbe3SChaitanya Kulkarni } 406a7a7cbe3SChaitanya Kulkarni 40757dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40857dacad5SJay Sternberg unsigned int hctx_idx) 40957dacad5SJay Sternberg { 41057dacad5SJay Sternberg struct nvme_dev *dev = data; 411147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 41257dacad5SJay Sternberg 41357dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 41457dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41557dacad5SJay Sternberg WARN_ON(nvmeq->tags); 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg hctx->driver_data = nvmeq; 41857dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 41957dacad5SJay Sternberg return 0; 42057dacad5SJay Sternberg } 42157dacad5SJay Sternberg 42257dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 42357dacad5SJay Sternberg { 42457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 42557dacad5SJay Sternberg 42657dacad5SJay Sternberg nvmeq->tags = NULL; 42757dacad5SJay Sternberg } 42857dacad5SJay Sternberg 42957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 43057dacad5SJay Sternberg unsigned int hctx_idx) 43157dacad5SJay Sternberg { 43257dacad5SJay Sternberg struct nvme_dev *dev = data; 433147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg if (!nvmeq->tags) 43657dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 43757dacad5SJay Sternberg 43857dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 43957dacad5SJay Sternberg hctx->driver_data = nvmeq; 44057dacad5SJay Sternberg return 0; 44157dacad5SJay Sternberg } 44257dacad5SJay Sternberg 443d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 444d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 44557dacad5SJay Sternberg { 446d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 447f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4480350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 449147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 45057dacad5SJay Sternberg 45157dacad5SJay Sternberg BUG_ON(!nvmeq); 452f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 45359e29ce6SSagi Grimberg 45459e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 45557dacad5SJay Sternberg return 0; 45657dacad5SJay Sternberg } 45757dacad5SJay Sternberg 4583b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4593b6592f7SJens Axboe { 4603b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4613b6592f7SJens Axboe if (dev->num_vecs > 1) 4623b6592f7SJens Axboe return 1; 4633b6592f7SJens Axboe 4643b6592f7SJens Axboe return 0; 4653b6592f7SJens Axboe } 4663b6592f7SJens Axboe 467dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 468dca51e78SChristoph Hellwig { 469dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4703b6592f7SJens Axboe int i, qoff, offset; 471dca51e78SChristoph Hellwig 4723b6592f7SJens Axboe offset = queue_irq_offset(dev); 4733b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4743b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4753b6592f7SJens Axboe 4763b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4773b6592f7SJens Axboe if (!map->nr_queues) { 478e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4797e849dd9SChristoph Hellwig continue; 4803b6592f7SJens Axboe } 4813b6592f7SJens Axboe 4824b04cc6aSJens Axboe /* 4834b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4844b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4854b04cc6aSJens Axboe */ 4863b6592f7SJens Axboe map->queue_offset = qoff; 487e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 4883b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4894b04cc6aSJens Axboe else 4904b04cc6aSJens Axboe blk_mq_map_queues(map); 4913b6592f7SJens Axboe qoff += map->nr_queues; 4923b6592f7SJens Axboe offset += map->nr_queues; 4933b6592f7SJens Axboe } 4943b6592f7SJens Axboe 4953b6592f7SJens Axboe return 0; 496dca51e78SChristoph Hellwig } 497dca51e78SChristoph Hellwig 49804f3eafdSJens Axboe /* 49904f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 50004f3eafdSJens Axboe */ 50104f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 50204f3eafdSJens Axboe { 50304f3eafdSJens Axboe if (!write_sq) { 50404f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 50504f3eafdSJens Axboe 50604f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 50704f3eafdSJens Axboe next_tail = 0; 50804f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 50904f3eafdSJens Axboe return; 51004f3eafdSJens Axboe } 51104f3eafdSJens Axboe 51204f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 51304f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 51404f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 51504f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 51604f3eafdSJens Axboe } 51704f3eafdSJens Axboe 51857dacad5SJay Sternberg /** 51990ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 52057dacad5SJay Sternberg * @nvmeq: The queue to use 52157dacad5SJay Sternberg * @cmd: The command to send 52204f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 52357dacad5SJay Sternberg */ 52404f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 52504f3eafdSJens Axboe bool write_sq) 52657dacad5SJay Sternberg { 52790ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 52890ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 52990ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 53090ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 53104f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 53204f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 53304f3eafdSJens Axboe } 53404f3eafdSJens Axboe 53504f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 53604f3eafdSJens Axboe { 53704f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 53804f3eafdSJens Axboe 53904f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 54004f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 54104f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 54290ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 54357dacad5SJay Sternberg } 54457dacad5SJay Sternberg 545a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 54657dacad5SJay Sternberg { 547f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 548a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 54957dacad5SJay Sternberg } 55057dacad5SJay Sternberg 551955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 552955b1b5aSMinwoo Im { 553955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 55420469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 555955b1b5aSMinwoo Im unsigned int avg_seg_size; 556955b1b5aSMinwoo Im 55720469a37SKeith Busch if (nseg == 0) 55820469a37SKeith Busch return false; 55920469a37SKeith Busch 56020469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 561955b1b5aSMinwoo Im 562955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 563955b1b5aSMinwoo Im return false; 564955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 565955b1b5aSMinwoo Im return false; 566955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 567955b1b5aSMinwoo Im return false; 568955b1b5aSMinwoo Im return true; 569955b1b5aSMinwoo Im } 570955b1b5aSMinwoo Im 5717fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 57257dacad5SJay Sternberg { 573f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5747fe07d14SChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 5757fe07d14SChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 576a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 577a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 57857dacad5SJay Sternberg int i; 57957dacad5SJay Sternberg 580dff824b2SChristoph Hellwig if (iod->dma_len) { 581dff824b2SChristoph Hellwig dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); 582dff824b2SChristoph Hellwig return; 583dff824b2SChristoph Hellwig } 584dff824b2SChristoph Hellwig 585dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 586dff824b2SChristoph Hellwig 5877fe07d14SChristoph Hellwig /* P2PDMA requests do not need to be unmapped */ 5887fe07d14SChristoph Hellwig if (!is_pci_p2pdma_page(sg_page(iod->sg))) 589dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5907fe07d14SChristoph Hellwig 5917fe07d14SChristoph Hellwig 59257dacad5SJay Sternberg if (iod->npages == 0) 593a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 594a7a7cbe3SChaitanya Kulkarni dma_addr); 595a7a7cbe3SChaitanya Kulkarni 59657dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 597a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 598a7a7cbe3SChaitanya Kulkarni 599a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 600a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 601a7a7cbe3SChaitanya Kulkarni 602a7a7cbe3SChaitanya Kulkarni next_dma_addr = 603a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 604a7a7cbe3SChaitanya Kulkarni } else { 605a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 606a7a7cbe3SChaitanya Kulkarni 607a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 608a7a7cbe3SChaitanya Kulkarni } 609a7a7cbe3SChaitanya Kulkarni 610a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 611a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 61257dacad5SJay Sternberg } 61357dacad5SJay Sternberg 614943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61557dacad5SJay Sternberg } 61657dacad5SJay Sternberg 617d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 618d0877473SKeith Busch { 619d0877473SKeith Busch int i; 620d0877473SKeith Busch struct scatterlist *sg; 621d0877473SKeith Busch 622d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 623d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 624d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 625d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 626d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 627d0877473SKeith Busch sg_dma_len(sg)); 628d0877473SKeith Busch } 629d0877473SKeith Busch } 630d0877473SKeith Busch 631a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 632a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 63357dacad5SJay Sternberg { 634f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63557dacad5SJay Sternberg struct dma_pool *pool; 636b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63757dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6405fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 64157dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 64257dacad5SJay Sternberg __le64 *prp_list; 643a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 64457dacad5SJay Sternberg dma_addr_t prp_dma; 64557dacad5SJay Sternberg int nprps, i; 64657dacad5SJay Sternberg 64757dacad5SJay Sternberg length -= (page_size - offset); 6485228b328SJan H. Schönherr if (length <= 0) { 6495228b328SJan H. Schönherr iod->first_dma = 0; 650a7a7cbe3SChaitanya Kulkarni goto done; 6515228b328SJan H. Schönherr } 65257dacad5SJay Sternberg 65357dacad5SJay Sternberg dma_len -= (page_size - offset); 65457dacad5SJay Sternberg if (dma_len) { 65557dacad5SJay Sternberg dma_addr += (page_size - offset); 65657dacad5SJay Sternberg } else { 65757dacad5SJay Sternberg sg = sg_next(sg); 65857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 66057dacad5SJay Sternberg } 66157dacad5SJay Sternberg 66257dacad5SJay Sternberg if (length <= page_size) { 66357dacad5SJay Sternberg iod->first_dma = dma_addr; 664a7a7cbe3SChaitanya Kulkarni goto done; 66557dacad5SJay Sternberg } 66657dacad5SJay Sternberg 66757dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 66857dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66957dacad5SJay Sternberg pool = dev->prp_small_pool; 67057dacad5SJay Sternberg iod->npages = 0; 67157dacad5SJay Sternberg } else { 67257dacad5SJay Sternberg pool = dev->prp_page_pool; 67357dacad5SJay Sternberg iod->npages = 1; 67457dacad5SJay Sternberg } 67557dacad5SJay Sternberg 67669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67757dacad5SJay Sternberg if (!prp_list) { 67857dacad5SJay Sternberg iod->first_dma = dma_addr; 67957dacad5SJay Sternberg iod->npages = -1; 68086eea289SKeith Busch return BLK_STS_RESOURCE; 68157dacad5SJay Sternberg } 68257dacad5SJay Sternberg list[0] = prp_list; 68357dacad5SJay Sternberg iod->first_dma = prp_dma; 68457dacad5SJay Sternberg i = 0; 68557dacad5SJay Sternberg for (;;) { 68657dacad5SJay Sternberg if (i == page_size >> 3) { 68757dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68957dacad5SJay Sternberg if (!prp_list) 69086eea289SKeith Busch return BLK_STS_RESOURCE; 69157dacad5SJay Sternberg list[iod->npages++] = prp_list; 69257dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 69357dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 69457dacad5SJay Sternberg i = 1; 69557dacad5SJay Sternberg } 69657dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 69757dacad5SJay Sternberg dma_len -= page_size; 69857dacad5SJay Sternberg dma_addr += page_size; 69957dacad5SJay Sternberg length -= page_size; 70057dacad5SJay Sternberg if (length <= 0) 70157dacad5SJay Sternberg break; 70257dacad5SJay Sternberg if (dma_len > 0) 70357dacad5SJay Sternberg continue; 70486eea289SKeith Busch if (unlikely(dma_len < 0)) 70586eea289SKeith Busch goto bad_sgl; 70657dacad5SJay Sternberg sg = sg_next(sg); 70757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70957dacad5SJay Sternberg } 71057dacad5SJay Sternberg 711a7a7cbe3SChaitanya Kulkarni done: 712a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 713a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 714a7a7cbe3SChaitanya Kulkarni 71586eea289SKeith Busch return BLK_STS_OK; 71686eea289SKeith Busch 71786eea289SKeith Busch bad_sgl: 718d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 719d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 720d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 72186eea289SKeith Busch return BLK_STS_IOERR; 72257dacad5SJay Sternberg } 72357dacad5SJay Sternberg 724a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 725a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 726a7a7cbe3SChaitanya Kulkarni { 727a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 728a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 729a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 730a7a7cbe3SChaitanya Kulkarni } 731a7a7cbe3SChaitanya Kulkarni 732a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 733a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 734a7a7cbe3SChaitanya Kulkarni { 735a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 736a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 737a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 738a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 739a7a7cbe3SChaitanya Kulkarni } else { 740a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 741a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 742a7a7cbe3SChaitanya Kulkarni } 743a7a7cbe3SChaitanya Kulkarni } 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 746b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 747a7a7cbe3SChaitanya Kulkarni { 748a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 749a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 750a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 751a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 752a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 753b0f2853bSChristoph Hellwig int i = 0; 754a7a7cbe3SChaitanya Kulkarni 755a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 756a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 757a7a7cbe3SChaitanya Kulkarni 758b0f2853bSChristoph Hellwig if (entries == 1) { 759a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 760a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 761a7a7cbe3SChaitanya Kulkarni } 762a7a7cbe3SChaitanya Kulkarni 763a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 764a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 765a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 766a7a7cbe3SChaitanya Kulkarni } else { 767a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 768a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 769a7a7cbe3SChaitanya Kulkarni } 770a7a7cbe3SChaitanya Kulkarni 771a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 772a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 773a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 774a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 775a7a7cbe3SChaitanya Kulkarni } 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 778a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 779a7a7cbe3SChaitanya Kulkarni 780a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni do { 783a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 784a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 785a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 786a7a7cbe3SChaitanya Kulkarni 787a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 788a7a7cbe3SChaitanya Kulkarni if (!sg_list) 789a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni i = 0; 792a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 793a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 794a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 795a7a7cbe3SChaitanya Kulkarni } 796a7a7cbe3SChaitanya Kulkarni 797a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 798a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 799b0f2853bSChristoph Hellwig } while (--entries > 0); 800a7a7cbe3SChaitanya Kulkarni 801a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 802a7a7cbe3SChaitanya Kulkarni } 803a7a7cbe3SChaitanya Kulkarni 804dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 805dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 806dff824b2SChristoph Hellwig struct bio_vec *bv) 807dff824b2SChristoph Hellwig { 808dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 809dff824b2SChristoph Hellwig unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 810dff824b2SChristoph Hellwig 811dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 812dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 813dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 814dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 815dff824b2SChristoph Hellwig 816dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 817dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 818dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 819dff824b2SChristoph Hellwig return 0; 820dff824b2SChristoph Hellwig } 821dff824b2SChristoph Hellwig 822fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 823b131c61dSChristoph Hellwig struct nvme_command *cmnd) 82457dacad5SJay Sternberg { 825f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 826ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 827ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 828ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 829fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 830b0f2853bSChristoph Hellwig int nr_mapped; 83157dacad5SJay Sternberg 832dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 833dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 834dff824b2SChristoph Hellwig 835dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 836dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 837dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 838dff824b2SChristoph Hellwig &cmnd->rw, &bv); 839dff824b2SChristoph Hellwig } 840dff824b2SChristoph Hellwig } 841dff824b2SChristoph Hellwig 842dff824b2SChristoph Hellwig iod->dma_len = 0; 8439b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8449b048119SChristoph Hellwig if (!iod->sg) 8459b048119SChristoph Hellwig return BLK_STS_RESOURCE; 8469b048119SChristoph Hellwig 8479b048119SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 8489b048119SChristoph Hellwig 849f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 850ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 851ba1ca37eSChristoph Hellwig if (!iod->nents) 852ba1ca37eSChristoph Hellwig goto out; 853ba1ca37eSChristoph Hellwig 854fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 855e0596ab2SLogan Gunthorpe 856e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 857e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 858e0596ab2SLogan Gunthorpe dma_dir); 859e0596ab2SLogan Gunthorpe else 860e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 861e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 862b0f2853bSChristoph Hellwig if (!nr_mapped) 863ba1ca37eSChristoph Hellwig goto out; 864ba1ca37eSChristoph Hellwig 865955b1b5aSMinwoo Im if (iod->use_sgl) 866b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 867a7a7cbe3SChaitanya Kulkarni else 868a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 869ba1ca37eSChristoph Hellwig out: 8704aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8717fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 872ba1ca37eSChristoph Hellwig return ret; 87357dacad5SJay Sternberg } 87457dacad5SJay Sternberg 8754aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8764aedb705SChristoph Hellwig struct nvme_command *cmnd) 8774aedb705SChristoph Hellwig { 8784aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8794aedb705SChristoph Hellwig 8804aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8814aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8824aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8834aedb705SChristoph Hellwig return BLK_STS_IOERR; 8844aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 8854aedb705SChristoph Hellwig return 0; 8864aedb705SChristoph Hellwig } 8874aedb705SChristoph Hellwig 88857dacad5SJay Sternberg /* 88957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 89057dacad5SJay Sternberg */ 891fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 89257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 89357dacad5SJay Sternberg { 89457dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 89557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 89657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 89757dacad5SJay Sternberg struct request *req = bd->rq; 8989b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 899ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 900ebe6d874SChristoph Hellwig blk_status_t ret; 90157dacad5SJay Sternberg 9029b048119SChristoph Hellwig iod->aborted = 0; 9039b048119SChristoph Hellwig iod->npages = -1; 9049b048119SChristoph Hellwig iod->nents = 0; 9059b048119SChristoph Hellwig 906d1f06f4aSJens Axboe /* 907d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 908d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 909d1f06f4aSJens Axboe */ 9104e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 911d1f06f4aSJens Axboe return BLK_STS_IOERR; 912d1f06f4aSJens Axboe 913f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 914fc17b653SChristoph Hellwig if (ret) 915f4800d6dSChristoph Hellwig return ret; 91657dacad5SJay Sternberg 917fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 918b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 919fc17b653SChristoph Hellwig if (ret) 9209b048119SChristoph Hellwig goto out_free_cmd; 921fc17b653SChristoph Hellwig } 922ba1ca37eSChristoph Hellwig 9234aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9244aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9254aedb705SChristoph Hellwig if (ret) 9264aedb705SChristoph Hellwig goto out_unmap_data; 9274aedb705SChristoph Hellwig } 9284aedb705SChristoph Hellwig 929aae239e1SChristoph Hellwig blk_mq_start_request(req); 93004f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 931fc17b653SChristoph Hellwig return BLK_STS_OK; 9324aedb705SChristoph Hellwig out_unmap_data: 9334aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 934f9d03f96SChristoph Hellwig out_free_cmd: 935f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 936ba1ca37eSChristoph Hellwig return ret; 93757dacad5SJay Sternberg } 93857dacad5SJay Sternberg 93977f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 940eee417b0SChristoph Hellwig { 941f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9424aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 943eee417b0SChristoph Hellwig 944915f04c9SChristoph Hellwig nvme_cleanup_cmd(req); 9454aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9464aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9474aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 948b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9494aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 95077f02a7aSChristoph Hellwig nvme_complete_rq(req); 95157dacad5SJay Sternberg } 95257dacad5SJay Sternberg 953d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 954750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 955d783e0bdSMarta Rybczynska { 956750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 957750dde44SChristoph Hellwig nvmeq->cq_phase; 958d783e0bdSMarta Rybczynska } 959d783e0bdSMarta Rybczynska 960eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 96157dacad5SJay Sternberg { 962eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 96357dacad5SJay Sternberg 964eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 965eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 966eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 967eb281c82SSagi Grimberg } 968adf68f21SChristoph Hellwig 9695cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 97057dacad5SJay Sternberg { 9715cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 97257dacad5SJay Sternberg struct request *req; 973adf68f21SChristoph Hellwig 97483a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9751b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 976aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 97783a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 97883a12fb7SSagi Grimberg return; 979aae239e1SChristoph Hellwig } 980aae239e1SChristoph Hellwig 981adf68f21SChristoph Hellwig /* 982adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 983adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 984adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 985adf68f21SChristoph Hellwig * for them but rather special case them here. 986adf68f21SChristoph Hellwig */ 987adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 98838dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9897bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 99083a12fb7SSagi Grimberg cqe->status, &cqe->result); 991a0fa9647SJens Axboe return; 99257dacad5SJay Sternberg } 99357dacad5SJay Sternberg 99483a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 995604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 99683a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 99783a12fb7SSagi Grimberg } 99857dacad5SJay Sternberg 9995cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 100083a12fb7SSagi Grimberg { 10015cb525c8SJens Axboe while (start != end) { 10025cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10035cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10045cb525c8SJens Axboe start = 0; 10055cb525c8SJens Axboe } 10065cb525c8SJens Axboe } 100783a12fb7SSagi Grimberg 10085cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10095cb525c8SJens Axboe { 1010dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1011920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1012920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1013dcca1662SHongbo Yao } else { 1014dcca1662SHongbo Yao nvmeq->cq_head++; 1015920d13a8SSagi Grimberg } 1016a0fa9647SJens Axboe } 1017a0fa9647SJens Axboe 10181052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10191052b8acSJens Axboe u16 *end, unsigned int tag) 1020a0fa9647SJens Axboe { 10211052b8acSJens Axboe int found = 0; 102283a12fb7SSagi Grimberg 10235cb525c8SJens Axboe *start = nvmeq->cq_head; 10241052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10251052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10261052b8acSJens Axboe found++; 10275cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 102857dacad5SJay Sternberg } 10295cb525c8SJens Axboe *end = nvmeq->cq_head; 103057dacad5SJay Sternberg 10315cb525c8SJens Axboe if (*start != *end) 1032eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10335cb525c8SJens Axboe return found; 103457dacad5SJay Sternberg } 103557dacad5SJay Sternberg 103657dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 103757dacad5SJay Sternberg { 103857dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 103968fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10405cb525c8SJens Axboe u16 start, end; 10415cb525c8SJens Axboe 10423a7afd8eSChristoph Hellwig /* 10433a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10443a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10453a7afd8eSChristoph Hellwig */ 10463a7afd8eSChristoph Hellwig rmb(); 104768fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 104868fa9dbeSJens Axboe ret = IRQ_HANDLED; 10495cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 105068fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10513a7afd8eSChristoph Hellwig wmb(); 10525cb525c8SJens Axboe 105368fa9dbeSJens Axboe if (start != end) { 10545cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10555cb525c8SJens Axboe return IRQ_HANDLED; 105657dacad5SJay Sternberg } 105757dacad5SJay Sternberg 105868fa9dbeSJens Axboe return ret; 105957dacad5SJay Sternberg } 106057dacad5SJay Sternberg 106157dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 106257dacad5SJay Sternberg { 106357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1064750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 106557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1066d783e0bdSMarta Rybczynska return IRQ_NONE; 106757dacad5SJay Sternberg } 106857dacad5SJay Sternberg 10690b2a8a9fSChristoph Hellwig /* 10700b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10710b2a8a9fSChristoph Hellwig * Can be called from any context. 10720b2a8a9fSChristoph Hellwig */ 10730b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1074a0fa9647SJens Axboe { 10753a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10765cb525c8SJens Axboe u16 start, end; 10771052b8acSJens Axboe int found; 1078a0fa9647SJens Axboe 10793a7afd8eSChristoph Hellwig /* 10803a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10813a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10823a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10833a7afd8eSChristoph Hellwig */ 10847c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10853a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 108691a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 108791a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 108891a509f8SChristoph Hellwig } else { 10893a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10905cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10913a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 109291a509f8SChristoph Hellwig } 1093442e19b7SSagi Grimberg 10945cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1095442e19b7SSagi Grimberg return found; 1096a0fa9647SJens Axboe } 1097a0fa9647SJens Axboe 10989743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10997776db1cSKeith Busch { 11007776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1101dabcefabSJens Axboe u16 start, end; 1102dabcefabSJens Axboe bool found; 1103dabcefabSJens Axboe 1104dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1105dabcefabSJens Axboe return 0; 1106dabcefabSJens Axboe 11073a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11089743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11093a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1110dabcefabSJens Axboe 1111dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1112dabcefabSJens Axboe return found; 1113dabcefabSJens Axboe } 1114dabcefabSJens Axboe 1115ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 111657dacad5SJay Sternberg { 1117f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1118147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 111957dacad5SJay Sternberg struct nvme_command c; 112057dacad5SJay Sternberg 112157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1123ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 112404f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 112557dacad5SJay Sternberg } 112657dacad5SJay Sternberg 112757dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 112857dacad5SJay Sternberg { 112957dacad5SJay Sternberg struct nvme_command c; 113057dacad5SJay Sternberg 113157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113257dacad5SJay Sternberg c.delete_queue.opcode = opcode; 113357dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 113457dacad5SJay Sternberg 11351c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113657dacad5SJay Sternberg } 113757dacad5SJay Sternberg 113857dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1139a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 114057dacad5SJay Sternberg { 114157dacad5SJay Sternberg struct nvme_command c; 11424b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11434b04cc6aSJens Axboe 11447c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11454b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 114657dacad5SJay Sternberg 114757dacad5SJay Sternberg /* 114816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 114957dacad5SJay Sternberg * is attached to the request. 115057dacad5SJay Sternberg */ 115157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 115357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 115457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 115557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 115657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1157a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 115857dacad5SJay Sternberg 11591c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116057dacad5SJay Sternberg } 116157dacad5SJay Sternberg 116257dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 116357dacad5SJay Sternberg struct nvme_queue *nvmeq) 116457dacad5SJay Sternberg { 11659abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 116657dacad5SJay Sternberg struct nvme_command c; 116781c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 116857dacad5SJay Sternberg 116957dacad5SJay Sternberg /* 11709abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11719abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11729abd68efSJens Axboe * URGENT. 11739abd68efSJens Axboe */ 11749abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11759abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11769abd68efSJens Axboe 11779abd68efSJens Axboe /* 117816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117957dacad5SJay Sternberg * is attached to the request. 118057dacad5SJay Sternberg */ 118157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 118257dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 118357dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 118457dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 118557dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 118657dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 118757dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 118857dacad5SJay Sternberg 11891c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 119057dacad5SJay Sternberg } 119157dacad5SJay Sternberg 119257dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 119357dacad5SJay Sternberg { 119457dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 119557dacad5SJay Sternberg } 119657dacad5SJay Sternberg 119757dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 119857dacad5SJay Sternberg { 119957dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 120057dacad5SJay Sternberg } 120157dacad5SJay Sternberg 12022a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 120357dacad5SJay Sternberg { 1204f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1205f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 120657dacad5SJay Sternberg 120727fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 120827fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1209e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1210e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 1213b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1214b2a0eb1aSKeith Busch { 1215b2a0eb1aSKeith Busch 1216b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1217b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1218b2a0eb1aSKeith Busch */ 1219b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1220b2a0eb1aSKeith Busch 1221ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1222ad70062cSJianchao Wang switch (dev->ctrl.state) { 1223ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1224ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1225b2a0eb1aSKeith Busch return false; 1226ad70062cSJianchao Wang default: 1227ad70062cSJianchao Wang break; 1228ad70062cSJianchao Wang } 1229b2a0eb1aSKeith Busch 1230b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1231b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1232b2a0eb1aSKeith Busch */ 1233b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1234b2a0eb1aSKeith Busch return false; 1235b2a0eb1aSKeith Busch 1236b2a0eb1aSKeith Busch return true; 1237b2a0eb1aSKeith Busch } 1238b2a0eb1aSKeith Busch 1239b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1240b2a0eb1aSKeith Busch { 1241b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1242b2a0eb1aSKeith Busch u16 pci_status; 1243b2a0eb1aSKeith Busch int result; 1244b2a0eb1aSKeith Busch 1245b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1246b2a0eb1aSKeith Busch &pci_status); 1247b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1248b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1249b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1250b2a0eb1aSKeith Busch csts, pci_status); 1251b2a0eb1aSKeith Busch else 1252b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1253b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1254b2a0eb1aSKeith Busch csts, result); 1255b2a0eb1aSKeith Busch } 1256b2a0eb1aSKeith Busch 125731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 125857dacad5SJay Sternberg { 1259f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1260f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 126157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 126257dacad5SJay Sternberg struct request *abort_req; 126357dacad5SJay Sternberg struct nvme_command cmd; 1264b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1265b2a0eb1aSKeith Busch 1266651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1267651438bbSWen Xiong * the recovery mechanism will surely fail. 1268651438bbSWen Xiong */ 1269651438bbSWen Xiong mb(); 1270651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1271651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1272651438bbSWen Xiong 1273b2a0eb1aSKeith Busch /* 1274b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1275b2a0eb1aSKeith Busch */ 1276b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1277b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1278b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1279d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1280db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1281b2a0eb1aSKeith Busch } 128257dacad5SJay Sternberg 128331c7c7d2SChristoph Hellwig /* 12847776db1cSKeith Busch * Did we miss an interrupt? 12857776db1cSKeith Busch */ 12860b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12877776db1cSKeith Busch dev_warn(dev->ctrl.device, 12887776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12897776db1cSKeith Busch req->tag, nvmeq->qid); 1290db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12917776db1cSKeith Busch } 12927776db1cSKeith Busch 12937776db1cSKeith Busch /* 1294fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1295fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1296fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1297db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1298fd634f41SChristoph Hellwig */ 12994244140dSKeith Busch switch (dev->ctrl.state) { 13004244140dSKeith Busch case NVME_CTRL_CONNECTING: 13014244140dSKeith Busch case NVME_CTRL_RESETTING: 1302b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1303fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1304fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1305a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 130627fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1307db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13084244140dSKeith Busch default: 13094244140dSKeith Busch break; 1310fd634f41SChristoph Hellwig } 1311fd634f41SChristoph Hellwig 1312fd634f41SChristoph Hellwig /* 1313e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1314e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1315e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 131631c7c7d2SChristoph Hellwig */ 1317f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13181b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 131957dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 132057dacad5SJay Sternberg req->tag, nvmeq->qid); 1321a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1322d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1323e1569a16SKeith Busch 132427fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1325db8c48e4SChristoph Hellwig return BLK_EH_DONE; 132657dacad5SJay Sternberg } 132757dacad5SJay Sternberg 1328e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1329e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1330e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1331e7a2a87dSChristoph Hellwig } 13327bf7d778SKeith Busch iod->aborted = 1; 133357dacad5SJay Sternberg 133457dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 133557dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 133657dacad5SJay Sternberg cmd.abort.cid = req->tag; 133757dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 133857dacad5SJay Sternberg 13391b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13401b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 134157dacad5SJay Sternberg req->tag, nvmeq->qid); 1342e7a2a87dSChristoph Hellwig 1343e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1344eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13456bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13466bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 134731c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 134857dacad5SJay Sternberg } 134957dacad5SJay Sternberg 1350e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1351e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1352e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 135357dacad5SJay Sternberg 135457dacad5SJay Sternberg /* 135557dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 135657dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 135757dacad5SJay Sternberg * as the device then is in a faulty state. 135857dacad5SJay Sternberg */ 135957dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 136057dacad5SJay Sternberg } 136157dacad5SJay Sternberg 136257dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 136357dacad5SJay Sternberg { 136488a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 136557dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 136663223078SChristoph Hellwig if (!nvmeq->sq_cmds) 136763223078SChristoph Hellwig return; 13680f238ff5SLogan Gunthorpe 136963223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 137088a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 137163223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 137263223078SChristoph Hellwig } else { 137388a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 137463223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13750f238ff5SLogan Gunthorpe } 137657dacad5SJay Sternberg } 137757dacad5SJay Sternberg 137857dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 137957dacad5SJay Sternberg { 138057dacad5SJay Sternberg int i; 138157dacad5SJay Sternberg 1382d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1383d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1384147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 138557dacad5SJay Sternberg } 138657dacad5SJay Sternberg } 138757dacad5SJay Sternberg 138857dacad5SJay Sternberg /** 138957dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 139040581d1aSBart Van Assche * @nvmeq: queue to suspend 139157dacad5SJay Sternberg */ 139257dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 139357dacad5SJay Sternberg { 13944e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 139557dacad5SJay Sternberg return 1; 139657dacad5SJay Sternberg 13974e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1398d1f06f4aSJens Axboe mb(); 139957dacad5SJay Sternberg 14004e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14011c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1402c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14037c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14044e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 140557dacad5SJay Sternberg return 0; 140657dacad5SJay Sternberg } 140757dacad5SJay Sternberg 14088fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14098fae268bSKeith Busch { 14108fae268bSKeith Busch int i; 14118fae268bSKeith Busch 14128fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14138fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14148fae268bSKeith Busch } 14158fae268bSKeith Busch 1416a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 141757dacad5SJay Sternberg { 1418147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 141957dacad5SJay Sternberg 1420a5cdb68cSKeith Busch if (shutdown) 1421a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1422a5cdb68cSKeith Busch else 142320d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 142457dacad5SJay Sternberg 14250b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 142657dacad5SJay Sternberg } 142757dacad5SJay Sternberg 142857dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 142957dacad5SJay Sternberg int entry_size) 143057dacad5SJay Sternberg { 143157dacad5SJay Sternberg int q_depth = dev->q_depth; 14325fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14335fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 143457dacad5SJay Sternberg 143557dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 143657dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14375fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 143857dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 143957dacad5SJay Sternberg 144057dacad5SJay Sternberg /* 144157dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 144257dacad5SJay Sternberg * would be better to map queues in system memory with the 144357dacad5SJay Sternberg * original depth 144457dacad5SJay Sternberg */ 144557dacad5SJay Sternberg if (q_depth < 64) 144657dacad5SJay Sternberg return -ENOMEM; 144757dacad5SJay Sternberg } 144857dacad5SJay Sternberg 144957dacad5SJay Sternberg return q_depth; 145057dacad5SJay Sternberg } 145157dacad5SJay Sternberg 145257dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 145357dacad5SJay Sternberg int qid, int depth) 145457dacad5SJay Sternberg { 14550f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1456815c6704SKeith Busch 14570f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14580f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14590f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14600f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 146163223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 146263223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 146363223078SChristoph Hellwig return 0; 146463223078SChristoph Hellwig } 14650f238ff5SLogan Gunthorpe } 14660f238ff5SLogan Gunthorpe 146757dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 146857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 146957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 147057dacad5SJay Sternberg return -ENOMEM; 147157dacad5SJay Sternberg return 0; 147257dacad5SJay Sternberg } 147357dacad5SJay Sternberg 1474a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 147557dacad5SJay Sternberg { 1476147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 147757dacad5SJay Sternberg 147862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 147962314e40SKeith Busch return 0; 148057dacad5SJay Sternberg 1481750afb08SLuis Chamberlain nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 148257dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 148357dacad5SJay Sternberg if (!nvmeq->cqes) 148457dacad5SJay Sternberg goto free_nvmeq; 148557dacad5SJay Sternberg 148657dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 148757dacad5SJay Sternberg goto free_cqdma; 148857dacad5SJay Sternberg 148957dacad5SJay Sternberg nvmeq->dev = dev; 14901ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14913a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 149257dacad5SJay Sternberg nvmeq->cq_head = 0; 149357dacad5SJay Sternberg nvmeq->cq_phase = 1; 149457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 149557dacad5SJay Sternberg nvmeq->q_depth = depth; 149657dacad5SJay Sternberg nvmeq->qid = qid; 1497d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 149857dacad5SJay Sternberg 1499147b27e4SSagi Grimberg return 0; 150057dacad5SJay Sternberg 150157dacad5SJay Sternberg free_cqdma: 150257dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 150357dacad5SJay Sternberg nvmeq->cq_dma_addr); 150457dacad5SJay Sternberg free_nvmeq: 1505147b27e4SSagi Grimberg return -ENOMEM; 150657dacad5SJay Sternberg } 150757dacad5SJay Sternberg 1508dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 150957dacad5SJay Sternberg { 15100ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15110ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15120ff199cbSChristoph Hellwig 15130ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15140ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15150ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15160ff199cbSChristoph Hellwig } else { 15170ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15180ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15190ff199cbSChristoph Hellwig } 152057dacad5SJay Sternberg } 152157dacad5SJay Sternberg 152257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 152357dacad5SJay Sternberg { 152457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152557dacad5SJay Sternberg 152657dacad5SJay Sternberg nvmeq->sq_tail = 0; 152704f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 152857dacad5SJay Sternberg nvmeq->cq_head = 0; 152957dacad5SJay Sternberg nvmeq->cq_phase = 1; 153057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 153157dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1532f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 153357dacad5SJay Sternberg dev->online_queues++; 15343a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 153557dacad5SJay Sternberg } 153657dacad5SJay Sternberg 15374b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 153857dacad5SJay Sternberg { 153957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154057dacad5SJay Sternberg int result; 15417c349ddeSKeith Busch u16 vector = 0; 154257dacad5SJay Sternberg 1543d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1544d1ed6aa1SChristoph Hellwig 154522b55601SKeith Busch /* 154622b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 154722b55601SKeith Busch * has only one vector available. 154822b55601SKeith Busch */ 15494b04cc6aSJens Axboe if (!polled) 1550a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15514b04cc6aSJens Axboe else 15527c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15534b04cc6aSJens Axboe 1554a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1555ded45505SKeith Busch if (result) 1556ded45505SKeith Busch return result; 155757dacad5SJay Sternberg 155857dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 155957dacad5SJay Sternberg if (result < 0) 1560ded45505SKeith Busch return result; 1561ded45505SKeith Busch else if (result) 156257dacad5SJay Sternberg goto release_cq; 156357dacad5SJay Sternberg 1564a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1565161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15664b04cc6aSJens Axboe 15677c349ddeSKeith Busch if (!polled) { 15687c349ddeSKeith Busch nvmeq->cq_vector = vector; 1569dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 157057dacad5SJay Sternberg if (result < 0) 157157dacad5SJay Sternberg goto release_sq; 15724b04cc6aSJens Axboe } 157357dacad5SJay Sternberg 15744e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 157557dacad5SJay Sternberg return result; 157657dacad5SJay Sternberg 157757dacad5SJay Sternberg release_sq: 1578f25a2dfcSJianchao Wang dev->online_queues--; 157957dacad5SJay Sternberg adapter_delete_sq(dev, qid); 158057dacad5SJay Sternberg release_cq: 158157dacad5SJay Sternberg adapter_delete_cq(dev, qid); 158257dacad5SJay Sternberg return result; 158357dacad5SJay Sternberg } 158457dacad5SJay Sternberg 1585f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 158657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 158857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 158957dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15900350815aSChristoph Hellwig .init_request = nvme_init_request, 159157dacad5SJay Sternberg .timeout = nvme_timeout, 159257dacad5SJay Sternberg }; 159357dacad5SJay Sternberg 1594f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1595376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1596376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1597376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1598376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1599376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1600376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1601376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1602c6d962aeSChristoph Hellwig .poll = nvme_poll, 1603dabcefabSJens Axboe }; 1604dabcefabSJens Axboe 160557dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 160657dacad5SJay Sternberg { 16071c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 160869d9a99cSKeith Busch /* 160969d9a99cSKeith Busch * If the controller was reset during removal, it's possible 161069d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 161169d9a99cSKeith Busch * queue to flush these to completion. 161269d9a99cSKeith Busch */ 1613c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16141c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 161557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 161657dacad5SJay Sternberg } 161757dacad5SJay Sternberg } 161857dacad5SJay Sternberg 161957dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 162057dacad5SJay Sternberg { 16211c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 162257dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 162357dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1624e3e9d50cSKeith Busch 162538dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 162657dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 162757dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1628d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1629d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 163057dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 163157dacad5SJay Sternberg 163257dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 163357dacad5SJay Sternberg return -ENOMEM; 163434b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 163557dacad5SJay Sternberg 16361c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16371c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 163857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163957dacad5SJay Sternberg return -ENOMEM; 164057dacad5SJay Sternberg } 16411c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 164257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16431c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 164457dacad5SJay Sternberg return -ENODEV; 164557dacad5SJay Sternberg } 164657dacad5SJay Sternberg } else 1647c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 164857dacad5SJay Sternberg 164957dacad5SJay Sternberg return 0; 165057dacad5SJay Sternberg } 165157dacad5SJay Sternberg 165297f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 165397f6ef64SXu Yu { 165497f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 165597f6ef64SXu Yu } 165697f6ef64SXu Yu 165797f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 165897f6ef64SXu Yu { 165997f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 166097f6ef64SXu Yu 166197f6ef64SXu Yu if (size <= dev->bar_mapped_size) 166297f6ef64SXu Yu return 0; 166397f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 166497f6ef64SXu Yu return -ENOMEM; 166597f6ef64SXu Yu if (dev->bar) 166697f6ef64SXu Yu iounmap(dev->bar); 166797f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 166897f6ef64SXu Yu if (!dev->bar) { 166997f6ef64SXu Yu dev->bar_mapped_size = 0; 167097f6ef64SXu Yu return -ENOMEM; 167197f6ef64SXu Yu } 167297f6ef64SXu Yu dev->bar_mapped_size = size; 167397f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 167497f6ef64SXu Yu 167597f6ef64SXu Yu return 0; 167697f6ef64SXu Yu } 167797f6ef64SXu Yu 167801ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 167957dacad5SJay Sternberg { 168057dacad5SJay Sternberg int result; 168157dacad5SJay Sternberg u32 aqa; 168257dacad5SJay Sternberg struct nvme_queue *nvmeq; 168357dacad5SJay Sternberg 168497f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 168597f6ef64SXu Yu if (result < 0) 168697f6ef64SXu Yu return result; 168797f6ef64SXu Yu 16888ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 168920d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 169057dacad5SJay Sternberg 16917a67cbeaSChristoph Hellwig if (dev->subsystem && 16927a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16937a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 169457dacad5SJay Sternberg 169520d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 169657dacad5SJay Sternberg if (result < 0) 169757dacad5SJay Sternberg return result; 169857dacad5SJay Sternberg 1699a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1700147b27e4SSagi Grimberg if (result) 1701147b27e4SSagi Grimberg return result; 170257dacad5SJay Sternberg 1703147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 170457dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 170557dacad5SJay Sternberg aqa |= aqa << 16; 170657dacad5SJay Sternberg 17077a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17087a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17097a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 171057dacad5SJay Sternberg 171120d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 171257dacad5SJay Sternberg if (result) 1713d4875622SKeith Busch return result; 171457dacad5SJay Sternberg 171557dacad5SJay Sternberg nvmeq->cq_vector = 0; 1716161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1717dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 171857dacad5SJay Sternberg if (result) { 17197c349ddeSKeith Busch dev->online_queues--; 1720d4875622SKeith Busch return result; 172157dacad5SJay Sternberg } 172257dacad5SJay Sternberg 17234e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 172457dacad5SJay Sternberg return result; 172557dacad5SJay Sternberg } 172657dacad5SJay Sternberg 1727749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 172857dacad5SJay Sternberg { 17294b04cc6aSJens Axboe unsigned i, max, rw_queues; 1730749941f2SChristoph Hellwig int ret = 0; 173157dacad5SJay Sternberg 1732d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1733a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1734749941f2SChristoph Hellwig ret = -ENOMEM; 173557dacad5SJay Sternberg break; 1736749941f2SChristoph Hellwig } 1737749941f2SChristoph Hellwig } 173857dacad5SJay Sternberg 1739d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1740e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1741e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1742e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17434b04cc6aSJens Axboe } else { 17444b04cc6aSJens Axboe rw_queues = max; 17454b04cc6aSJens Axboe } 17464b04cc6aSJens Axboe 1747949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17484b04cc6aSJens Axboe bool polled = i > rw_queues; 17494b04cc6aSJens Axboe 17504b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1751d4875622SKeith Busch if (ret) 175257dacad5SJay Sternberg break; 175357dacad5SJay Sternberg } 175457dacad5SJay Sternberg 1755749941f2SChristoph Hellwig /* 1756749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17578adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17588adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1759749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1760749941f2SChristoph Hellwig */ 1761749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 176257dacad5SJay Sternberg } 176357dacad5SJay Sternberg 1764202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1765202021c1SStephen Bates struct device_attribute *attr, 1766202021c1SStephen Bates char *buf) 1767202021c1SStephen Bates { 1768202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1769202021c1SStephen Bates 1770c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1771202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1772202021c1SStephen Bates } 1773202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1774202021c1SStephen Bates 177588de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 177657dacad5SJay Sternberg { 177788de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 177888de4598SChristoph Hellwig 177988de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 178088de4598SChristoph Hellwig } 178188de4598SChristoph Hellwig 178288de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 178388de4598SChristoph Hellwig { 178488de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 178588de4598SChristoph Hellwig } 178688de4598SChristoph Hellwig 1787f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 178857dacad5SJay Sternberg { 178988de4598SChristoph Hellwig u64 size, offset; 179057dacad5SJay Sternberg resource_size_t bar_size; 179157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17928969f1f8SChristoph Hellwig int bar; 179357dacad5SJay Sternberg 17949fe5c59fSKeith Busch if (dev->cmb_size) 17959fe5c59fSKeith Busch return; 17969fe5c59fSKeith Busch 17977a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1798f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1799f65efd6dSChristoph Hellwig return; 1800202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 180157dacad5SJay Sternberg 180288de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 180388de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18048969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18058969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 180657dacad5SJay Sternberg 180757dacad5SJay Sternberg if (offset > bar_size) 1808f65efd6dSChristoph Hellwig return; 180957dacad5SJay Sternberg 181057dacad5SJay Sternberg /* 181157dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 181257dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 181357dacad5SJay Sternberg * the reported size of the BAR 181457dacad5SJay Sternberg */ 181557dacad5SJay Sternberg if (size > bar_size - offset) 181657dacad5SJay Sternberg size = bar_size - offset; 181757dacad5SJay Sternberg 18180f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18190f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18200f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1821f65efd6dSChristoph Hellwig return; 18220f238ff5SLogan Gunthorpe } 18230f238ff5SLogan Gunthorpe 182457dacad5SJay Sternberg dev->cmb_size = size; 18250f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18260f238ff5SLogan Gunthorpe 18270f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18280f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18290f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1830f65efd6dSChristoph Hellwig 1831f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1832f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1833f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1834f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 183557dacad5SJay Sternberg } 183657dacad5SJay Sternberg 183757dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 183857dacad5SJay Sternberg { 18390f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1840f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1841f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18420f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1843f63572dfSJon Derrick } 184457dacad5SJay Sternberg } 184557dacad5SJay Sternberg 184687ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 184757dacad5SJay Sternberg { 18484033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 184987ad72a5SChristoph Hellwig struct nvme_command c; 185087ad72a5SChristoph Hellwig int ret; 185187ad72a5SChristoph Hellwig 185287ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 185387ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 185487ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 185587ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 185687ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 185787ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 185887ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 185987ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 186087ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 186187ad72a5SChristoph Hellwig 186287ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 186387ad72a5SChristoph Hellwig if (ret) { 186487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 186587ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 186687ad72a5SChristoph Hellwig ret, bits); 186787ad72a5SChristoph Hellwig } 186887ad72a5SChristoph Hellwig return ret; 186987ad72a5SChristoph Hellwig } 187087ad72a5SChristoph Hellwig 187187ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 187287ad72a5SChristoph Hellwig { 187387ad72a5SChristoph Hellwig int i; 187487ad72a5SChristoph Hellwig 187587ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 187687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 187787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 187887ad72a5SChristoph Hellwig 1879cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1880cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1881cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 188287ad72a5SChristoph Hellwig } 188387ad72a5SChristoph Hellwig 188487ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 188587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18864033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18874033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18884033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 188987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18907e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 189187ad72a5SChristoph Hellwig } 189287ad72a5SChristoph Hellwig 189392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 189492dc6895SChristoph Hellwig u32 chunk_size) 189587ad72a5SChristoph Hellwig { 189687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 189792dc6895SChristoph Hellwig u32 max_entries, len; 18984033f35dSChristoph Hellwig dma_addr_t descs_dma; 18992ee0e4edSDan Carpenter int i = 0; 190087ad72a5SChristoph Hellwig void **bufs; 19016fbcde66SMinwoo Im u64 size, tmp; 190287ad72a5SChristoph Hellwig 190387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 190487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 190587ad72a5SChristoph Hellwig max_entries = tmp; 1906044a9df1SChristoph Hellwig 1907044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1908044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1909044a9df1SChristoph Hellwig 1910750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19114033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 191287ad72a5SChristoph Hellwig if (!descs) 191387ad72a5SChristoph Hellwig goto out; 191487ad72a5SChristoph Hellwig 191587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 191687ad72a5SChristoph Hellwig if (!bufs) 191787ad72a5SChristoph Hellwig goto out_free_descs; 191887ad72a5SChristoph Hellwig 1919244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 192087ad72a5SChristoph Hellwig dma_addr_t dma_addr; 192187ad72a5SChristoph Hellwig 192250cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 192387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 192487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192587ad72a5SChristoph Hellwig if (!bufs[i]) 192687ad72a5SChristoph Hellwig break; 192787ad72a5SChristoph Hellwig 192887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 192987ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 193087ad72a5SChristoph Hellwig i++; 193187ad72a5SChristoph Hellwig } 193287ad72a5SChristoph Hellwig 193392dc6895SChristoph Hellwig if (!size) 193487ad72a5SChristoph Hellwig goto out_free_bufs; 193587ad72a5SChristoph Hellwig 193687ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 193787ad72a5SChristoph Hellwig dev->host_mem_size = size; 193887ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19394033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 194087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 194187ad72a5SChristoph Hellwig return 0; 194287ad72a5SChristoph Hellwig 194387ad72a5SChristoph Hellwig out_free_bufs: 194487ad72a5SChristoph Hellwig while (--i >= 0) { 194587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 194687ad72a5SChristoph Hellwig 1947cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1948cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1949cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 195087ad72a5SChristoph Hellwig } 195187ad72a5SChristoph Hellwig 195287ad72a5SChristoph Hellwig kfree(bufs); 195387ad72a5SChristoph Hellwig out_free_descs: 19544033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19554033f35dSChristoph Hellwig descs_dma); 195687ad72a5SChristoph Hellwig out: 195787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 195887ad72a5SChristoph Hellwig return -ENOMEM; 195987ad72a5SChristoph Hellwig } 196087ad72a5SChristoph Hellwig 196192dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 196292dc6895SChristoph Hellwig { 196392dc6895SChristoph Hellwig u32 chunk_size; 196492dc6895SChristoph Hellwig 196592dc6895SChristoph Hellwig /* start big and work our way down */ 196630f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1967044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 196892dc6895SChristoph Hellwig chunk_size /= 2) { 196992dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197092dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 197192dc6895SChristoph Hellwig return 0; 197292dc6895SChristoph Hellwig nvme_free_host_mem(dev); 197392dc6895SChristoph Hellwig } 197492dc6895SChristoph Hellwig } 197592dc6895SChristoph Hellwig 197692dc6895SChristoph Hellwig return -ENOMEM; 197792dc6895SChristoph Hellwig } 197892dc6895SChristoph Hellwig 19799620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198087ad72a5SChristoph Hellwig { 198187ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 198287ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 198387ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 198487ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19856fbcde66SMinwoo Im int ret; 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig preferred = min(preferred, max); 198887ad72a5SChristoph Hellwig if (min > max) { 198987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199087ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 199187ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 199287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19939620cfbaSChristoph Hellwig return 0; 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199687ad72a5SChristoph Hellwig /* 199787ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 199887ad72a5SChristoph Hellwig */ 199987ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200087ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 200187ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 200287ad72a5SChristoph Hellwig else 200387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 200487ad72a5SChristoph Hellwig } 200587ad72a5SChristoph Hellwig 200687ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 200792dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 200892dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 200992dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20109620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 201187ad72a5SChristoph Hellwig } 201287ad72a5SChristoph Hellwig 201392dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 201492dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 201592dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 201692dc6895SChristoph Hellwig } 201792dc6895SChristoph Hellwig 20189620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20199620cfbaSChristoph Hellwig if (ret) 202087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20219620cfbaSChristoph Hellwig return ret; 202257dacad5SJay Sternberg } 202357dacad5SJay Sternberg 2024612b7286SMing Lei /* 2025612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2026612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2027612b7286SMing Lei */ 2028612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20293b6592f7SJens Axboe { 2030612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2031612b7286SMing Lei unsigned int nr_read_queues; 2032c45b1fa2SMing Lei 20333b6592f7SJens Axboe /* 2034612b7286SMing Lei * If there is no interupt available for queues, ensure that 2035612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2036612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2037612b7286SMing Lei * 2038612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2039612b7286SMing Lei * write and read queues. 2040612b7286SMing Lei * 2041612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2042612b7286SMing Lei * queue. 20433b6592f7SJens Axboe */ 2044612b7286SMing Lei if (!nrirqs) { 2045612b7286SMing Lei nrirqs = 1; 2046612b7286SMing Lei nr_read_queues = 0; 2047612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2048612b7286SMing Lei nr_read_queues = 0; 2049612b7286SMing Lei } else if (write_queues >= nrirqs) { 2050612b7286SMing Lei nr_read_queues = 1; 20513b6592f7SJens Axboe } else { 2052612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20533b6592f7SJens Axboe } 2054612b7286SMing Lei 2055612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2056612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2057612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2058612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2059612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20603b6592f7SJens Axboe } 20613b6592f7SJens Axboe 20626451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20633b6592f7SJens Axboe { 20643b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20653b6592f7SJens Axboe struct irq_affinity affd = { 20663b6592f7SJens Axboe .pre_vectors = 1, 2067612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2068612b7286SMing Lei .priv = dev, 20693b6592f7SJens Axboe }; 20706451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20716451fe73SJens Axboe 20726451fe73SJens Axboe /* 20736451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20746451fe73SJens Axboe * queue left over for non-polled IO. 20756451fe73SJens Axboe */ 20766451fe73SJens Axboe this_p_queues = poll_queues; 20776451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20786451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20796451fe73SJens Axboe irq_queues = 1; 20806451fe73SJens Axboe } else { 2081c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20826451fe73SJens Axboe } 20836451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20843b6592f7SJens Axboe 2085612b7286SMing Lei /* Initialize for the single interrupt case */ 2086612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2087612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20883b6592f7SJens Axboe 2089612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20903b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20913b6592f7SJens Axboe } 20923b6592f7SJens Axboe 20938fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20948fae268bSKeith Busch { 20958fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20968fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20978fae268bSKeith Busch } 20988fae268bSKeith Busch 209957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 210057dacad5SJay Sternberg { 2101147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 210257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 210397f6ef64SXu Yu int result, nr_io_queues; 210497f6ef64SXu Yu unsigned long size; 210557dacad5SJay Sternberg 21063b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21079a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21089a0be7abSChristoph Hellwig if (result < 0) 210957dacad5SJay Sternberg return result; 21109a0be7abSChristoph Hellwig 2111f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2112a5229050SKeith Busch return 0; 211357dacad5SJay Sternberg 21144e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21154e224106SChristoph Hellwig 21160f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 211757dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 211857dacad5SJay Sternberg sizeof(struct nvme_command)); 211957dacad5SJay Sternberg if (result > 0) 212057dacad5SJay Sternberg dev->q_depth = result; 212157dacad5SJay Sternberg else 21220f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 212357dacad5SJay Sternberg } 212457dacad5SJay Sternberg 212557dacad5SJay Sternberg do { 212697f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 212797f6ef64SXu Yu result = nvme_remap_bar(dev, size); 212897f6ef64SXu Yu if (!result) 212957dacad5SJay Sternberg break; 213057dacad5SJay Sternberg if (!--nr_io_queues) 213157dacad5SJay Sternberg return -ENOMEM; 213257dacad5SJay Sternberg } while (1); 213357dacad5SJay Sternberg adminq->q_db = dev->dbs; 213457dacad5SJay Sternberg 21358fae268bSKeith Busch retry: 213657dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21370ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 213857dacad5SJay Sternberg 213957dacad5SJay Sternberg /* 214057dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 214157dacad5SJay Sternberg * setting up the full range we need. 214257dacad5SJay Sternberg */ 2143dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21443b6592f7SJens Axboe 21453b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 214622b55601SKeith Busch if (result <= 0) 2147dca51e78SChristoph Hellwig return -EIO; 21483b6592f7SJens Axboe 214922b55601SKeith Busch dev->num_vecs = result; 21504b04cc6aSJens Axboe result = max(result - 1, 1); 2151e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 215257dacad5SJay Sternberg 215357dacad5SJay Sternberg /* 215457dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 215557dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 215657dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 215757dacad5SJay Sternberg * number of interrupts. 215857dacad5SJay Sternberg */ 2159dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21607c349ddeSKeith Busch if (result) 2161d4875622SKeith Busch return result; 21624e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21638fae268bSKeith Busch 21648fae268bSKeith Busch result = nvme_create_io_queues(dev); 21658fae268bSKeith Busch if (result || dev->online_queues < 2) 21668fae268bSKeith Busch return result; 21678fae268bSKeith Busch 21688fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21698fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21708fae268bSKeith Busch nvme_disable_io_queues(dev); 21718fae268bSKeith Busch nvme_suspend_io_queues(dev); 21728fae268bSKeith Busch goto retry; 21738fae268bSKeith Busch } 21748fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21758fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21768fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21778fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21788fae268bSKeith Busch return 0; 217957dacad5SJay Sternberg } 218057dacad5SJay Sternberg 21812a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2182db3cbfffSKeith Busch { 2183db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2184db3cbfffSKeith Busch 2185db3cbfffSKeith Busch blk_mq_free_request(req); 2186d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2187db3cbfffSKeith Busch } 2188db3cbfffSKeith Busch 21892a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2190db3cbfffSKeith Busch { 2191db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2192db3cbfffSKeith Busch 2193d1ed6aa1SChristoph Hellwig if (error) 2194d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2195db3cbfffSKeith Busch 2196db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2197db3cbfffSKeith Busch } 2198db3cbfffSKeith Busch 2199db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2200db3cbfffSKeith Busch { 2201db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2202db3cbfffSKeith Busch struct request *req; 2203db3cbfffSKeith Busch struct nvme_command cmd; 2204db3cbfffSKeith Busch 2205db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2206db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2207db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2208db3cbfffSKeith Busch 2209eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2210db3cbfffSKeith Busch if (IS_ERR(req)) 2211db3cbfffSKeith Busch return PTR_ERR(req); 2212db3cbfffSKeith Busch 2213db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2214db3cbfffSKeith Busch req->end_io_data = nvmeq; 2215db3cbfffSKeith Busch 2216d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2217db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2218db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2219db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2220db3cbfffSKeith Busch return 0; 2221db3cbfffSKeith Busch } 2222db3cbfffSKeith Busch 22238fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2224db3cbfffSKeith Busch { 22255271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2226db3cbfffSKeith Busch unsigned long timeout; 2227db3cbfffSKeith Busch 2228db3cbfffSKeith Busch retry: 2229db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22305271edd4SChristoph Hellwig while (nr_queues > 0) { 22315271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2232db3cbfffSKeith Busch break; 22335271edd4SChristoph Hellwig nr_queues--; 22345271edd4SChristoph Hellwig sent++; 22355271edd4SChristoph Hellwig } 2236d1ed6aa1SChristoph Hellwig while (sent) { 2237d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2238d1ed6aa1SChristoph Hellwig 2239d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22405271edd4SChristoph Hellwig timeout); 2241db3cbfffSKeith Busch if (timeout == 0) 22425271edd4SChristoph Hellwig return false; 2243d1ed6aa1SChristoph Hellwig 2244d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2245d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2246d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2247d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2248d1ed6aa1SChristoph Hellwig 2249d1ed6aa1SChristoph Hellwig sent--; 22505271edd4SChristoph Hellwig if (nr_queues) 2251db3cbfffSKeith Busch goto retry; 2252db3cbfffSKeith Busch } 22535271edd4SChristoph Hellwig return true; 2254db3cbfffSKeith Busch } 2255db3cbfffSKeith Busch 225657dacad5SJay Sternberg /* 22572b1b7e78SJianchao Wang * return error value only when tagset allocation failed 225857dacad5SJay Sternberg */ 225957dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 226057dacad5SJay Sternberg { 22612b1b7e78SJianchao Wang int ret; 22622b1b7e78SJianchao Wang 22635bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2264c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 226557dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2266ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2267ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2268ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 226957dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 227057dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 227157dacad5SJay Sternberg dev->tagset.queue_depth = 227257dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2273d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 227457dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 227557dacad5SJay Sternberg dev->tagset.driver_data = dev; 227657dacad5SJay Sternberg 22772b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22782b1b7e78SJianchao Wang if (ret) { 22792b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22802b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22812b1b7e78SJianchao Wang return ret; 22822b1b7e78SJianchao Wang } 22835bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2284f9f38e33SHelen Koike 2285f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2286949928c1SKeith Busch } else { 2287949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2288949928c1SKeith Busch 2289949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2290949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 229157dacad5SJay Sternberg } 2292949928c1SKeith Busch 229357dacad5SJay Sternberg return 0; 229457dacad5SJay Sternberg } 229557dacad5SJay Sternberg 2296b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 229757dacad5SJay Sternberg { 2298b00a726aSKeith Busch int result = -ENOMEM; 229957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 230057dacad5SJay Sternberg 230157dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 230257dacad5SJay Sternberg return result; 230357dacad5SJay Sternberg 230457dacad5SJay Sternberg pci_set_master(pdev); 230557dacad5SJay Sternberg 230657dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 230757dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 230857dacad5SJay Sternberg goto disable; 230957dacad5SJay Sternberg 23107a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 231157dacad5SJay Sternberg result = -ENODEV; 2312b00a726aSKeith Busch goto disable; 231357dacad5SJay Sternberg } 231457dacad5SJay Sternberg 231557dacad5SJay Sternberg /* 2316a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2317a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2318a5229050SKeith Busch * adjust this later. 231957dacad5SJay Sternberg */ 2320dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2321dca51e78SChristoph Hellwig if (result < 0) 2322dca51e78SChristoph Hellwig return result; 232357dacad5SJay Sternberg 232420d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23257a67cbeaSChristoph Hellwig 232620d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2327b27c1e68Sweiping zhang io_queue_depth); 232820d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23297a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23301f390c1fSStephan Günther 23311f390c1fSStephan Günther /* 23321f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23331f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23341f390c1fSStephan Günther */ 23351f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23361f390c1fSStephan Günther dev->q_depth = 2; 23379bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23389bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23391f390c1fSStephan Günther dev->q_depth); 2340d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2341d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 234220d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2343d554b5e1SMartin K. Petersen dev->q_depth = 64; 2344d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2345d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23461f390c1fSStephan Günther } 23471f390c1fSStephan Günther 2348f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2349202021c1SStephen Bates 2350a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2351a0a3408eSKeith Busch pci_save_state(pdev); 235257dacad5SJay Sternberg return 0; 235357dacad5SJay Sternberg 235457dacad5SJay Sternberg disable: 235557dacad5SJay Sternberg pci_disable_device(pdev); 235657dacad5SJay Sternberg return result; 235757dacad5SJay Sternberg } 235857dacad5SJay Sternberg 235957dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 236057dacad5SJay Sternberg { 2361b00a726aSKeith Busch if (dev->bar) 2362b00a726aSKeith Busch iounmap(dev->bar); 2363a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2364b00a726aSKeith Busch } 2365b00a726aSKeith Busch 2366b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2367b00a726aSKeith Busch { 236857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 236957dacad5SJay Sternberg 2370dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 237157dacad5SJay Sternberg 2372a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2373a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 237457dacad5SJay Sternberg pci_disable_device(pdev); 237557dacad5SJay Sternberg } 2376a0a3408eSKeith Busch } 237757dacad5SJay Sternberg 2378a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 237957dacad5SJay Sternberg { 2380302ad8ccSKeith Busch bool dead = true; 2381302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 238257dacad5SJay Sternberg 238377bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2384302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2385302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2386302ad8ccSKeith Busch 2387ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2388ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2389302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2390302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2391302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 239257dacad5SJay Sternberg } 2393c21377f8SGabriel Krisman Bertazi 2394302ad8ccSKeith Busch /* 2395302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2396302ad8ccSKeith Busch * doing a safe shutdown. 2397302ad8ccSKeith Busch */ 239887ad72a5SChristoph Hellwig if (!dead) { 239987ad72a5SChristoph Hellwig if (shutdown) 2400302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24019a915a5bSJianchao Wang } 240287ad72a5SChristoph Hellwig 24039a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24049a915a5bSJianchao Wang 240564ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24068fae268bSKeith Busch nvme_disable_io_queues(dev); 2407a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 240857dacad5SJay Sternberg } 24098fae268bSKeith Busch nvme_suspend_io_queues(dev); 24108fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2411b00a726aSKeith Busch nvme_pci_disable(dev); 241257dacad5SJay Sternberg 2413e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2414e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2415302ad8ccSKeith Busch 2416302ad8ccSKeith Busch /* 2417302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2418302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2419302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2420302ad8ccSKeith Busch */ 2421302ad8ccSKeith Busch if (shutdown) 2422302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 242377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 242457dacad5SJay Sternberg } 242557dacad5SJay Sternberg 242657dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 242757dacad5SJay Sternberg { 242857dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 242957dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 243057dacad5SJay Sternberg if (!dev->prp_page_pool) 243157dacad5SJay Sternberg return -ENOMEM; 243257dacad5SJay Sternberg 243357dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 243457dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 243557dacad5SJay Sternberg 256, 256, 0); 243657dacad5SJay Sternberg if (!dev->prp_small_pool) { 243757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 243857dacad5SJay Sternberg return -ENOMEM; 243957dacad5SJay Sternberg } 244057dacad5SJay Sternberg return 0; 244157dacad5SJay Sternberg } 244257dacad5SJay Sternberg 244357dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 244457dacad5SJay Sternberg { 244557dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 244657dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 244757dacad5SJay Sternberg } 244857dacad5SJay Sternberg 24491673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 245057dacad5SJay Sternberg { 24511673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 245257dacad5SJay Sternberg 2453f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 245457dacad5SJay Sternberg put_device(dev->dev); 245557dacad5SJay Sternberg if (dev->tagset.tags) 245657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24571c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24581c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 245957dacad5SJay Sternberg kfree(dev->queues); 2460e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2461943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 246257dacad5SJay Sternberg kfree(dev); 246357dacad5SJay Sternberg } 246457dacad5SJay Sternberg 2465f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2466f58944e2SKeith Busch { 2467237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2468f58944e2SKeith Busch 2469d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 247069d9a99cSKeith Busch nvme_dev_disable(dev, false); 24719f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 247203e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2473f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2474f58944e2SKeith Busch } 2475f58944e2SKeith Busch 2476fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 247757dacad5SJay Sternberg { 2478d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2479d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2480a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2481f58944e2SKeith Busch int result = -ENODEV; 24822b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 248357dacad5SJay Sternberg 248482b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2485fd634f41SChristoph Hellwig goto out; 2486fd634f41SChristoph Hellwig 2487fd634f41SChristoph Hellwig /* 2488fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2489fd634f41SChristoph Hellwig * moving on. 2490fd634f41SChristoph Hellwig */ 2491b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2492a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2493fd634f41SChristoph Hellwig 24945c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2495b00a726aSKeith Busch result = nvme_pci_enable(dev); 249657dacad5SJay Sternberg if (result) 24974726bcf3SKeith Busch goto out_unlock; 249857dacad5SJay Sternberg 249901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 250057dacad5SJay Sternberg if (result) 25014726bcf3SKeith Busch goto out_unlock; 250257dacad5SJay Sternberg 250357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 250457dacad5SJay Sternberg if (result) 25054726bcf3SKeith Busch goto out_unlock; 250657dacad5SJay Sternberg 2507943e942eSJens Axboe /* 2508943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2509943e942eSJens Axboe * over a single page. 2510943e942eSJens Axboe */ 2511943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2512943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 25135c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25145c959d73SKeith Busch 25155c959d73SKeith Busch /* 25165c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25175c959d73SKeith Busch * initializing procedure here. 25185c959d73SKeith Busch */ 25195c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25205c959d73SKeith Busch dev_warn(dev->ctrl.device, 25215c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 25225c959d73SKeith Busch goto out; 25235c959d73SKeith Busch } 2524943e942eSJens Axboe 2525ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2526ce4541f4SChristoph Hellwig if (result) 2527f58944e2SKeith Busch goto out; 2528ce4541f4SChristoph Hellwig 2529e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2530e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25314f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25324f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2533e286bcfcSScott Bauer else if (was_suspend) 25344f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2535e286bcfcSScott Bauer } else { 2536e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2537e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2538e286bcfcSScott Bauer } 2539a98e58e5SScott Bauer 2540f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2541f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2542f9f38e33SHelen Koike if (result) 2543f9f38e33SHelen Koike dev_warn(dev->dev, 2544f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2545f9f38e33SHelen Koike } 2546f9f38e33SHelen Koike 25479620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25489620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25499620cfbaSChristoph Hellwig if (result < 0) 25509620cfbaSChristoph Hellwig goto out; 25519620cfbaSChristoph Hellwig } 255287ad72a5SChristoph Hellwig 255357dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 255457dacad5SJay Sternberg if (result) 2555f58944e2SKeith Busch goto out; 255657dacad5SJay Sternberg 255721f033f7SKeith Busch /* 255857dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 255957dacad5SJay Sternberg * any working I/O queue. 256057dacad5SJay Sternberg */ 256157dacad5SJay Sternberg if (dev->online_queues < 2) { 25621b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25633b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25645bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25652b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 256657dacad5SJay Sternberg } else { 256725646264SKeith Busch nvme_start_queues(&dev->ctrl); 2568302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25692b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25702b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25712b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2572302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 257357dacad5SJay Sternberg } 257457dacad5SJay Sternberg 25752b1b7e78SJianchao Wang /* 25762b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25772b1b7e78SJianchao Wang * recovery. 25782b1b7e78SJianchao Wang */ 25792b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 25802b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25812b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2582bb8d261eSChristoph Hellwig goto out; 2583bb8d261eSChristoph Hellwig } 258492911a55SChristoph Hellwig 2585d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 258657dacad5SJay Sternberg return; 258757dacad5SJay Sternberg 25884726bcf3SKeith Busch out_unlock: 25894726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 259057dacad5SJay Sternberg out: 2591f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 259257dacad5SJay Sternberg } 259357dacad5SJay Sternberg 25945c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 259557dacad5SJay Sternberg { 25965c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 259757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 259857dacad5SJay Sternberg 259957dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2600921920abSKeith Busch device_release_driver(&pdev->dev); 26011673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 260257dacad5SJay Sternberg } 260357dacad5SJay Sternberg 26041c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 260557dacad5SJay Sternberg { 26061c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26071c63dc66SChristoph Hellwig return 0; 260857dacad5SJay Sternberg } 26091c63dc66SChristoph Hellwig 26105fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26115fd4ce1bSChristoph Hellwig { 26125fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26135fd4ce1bSChristoph Hellwig return 0; 26145fd4ce1bSChristoph Hellwig } 26155fd4ce1bSChristoph Hellwig 26167fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26177fd8930fSChristoph Hellwig { 26187fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26197fd8930fSChristoph Hellwig return 0; 26207fd8930fSChristoph Hellwig } 26217fd8930fSChristoph Hellwig 262297c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 262397c12223SKeith Busch { 262497c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 262597c12223SKeith Busch 262697c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 262797c12223SKeith Busch } 262897c12223SKeith Busch 26291c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26301a353d85SMing Lin .name = "pcie", 2631e439bb12SSagi Grimberg .module = THIS_MODULE, 2632e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2633e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26341c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26355fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26367fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26371673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2638f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 263997c12223SKeith Busch .get_address = nvme_pci_get_address, 26401c63dc66SChristoph Hellwig }; 264157dacad5SJay Sternberg 2642b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2643b00a726aSKeith Busch { 2644b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2645b00a726aSKeith Busch 2646a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2647b00a726aSKeith Busch return -ENODEV; 2648b00a726aSKeith Busch 264997f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2650b00a726aSKeith Busch goto release; 2651b00a726aSKeith Busch 2652b00a726aSKeith Busch return 0; 2653b00a726aSKeith Busch release: 2654a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2655b00a726aSKeith Busch return -ENODEV; 2656b00a726aSKeith Busch } 2657b00a726aSKeith Busch 26588427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2659ff5350a8SAndy Lutomirski { 2660ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2661ff5350a8SAndy Lutomirski /* 2662ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2663ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2664ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2665ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2666ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2667ff5350a8SAndy Lutomirski * laptops. 2668ff5350a8SAndy Lutomirski */ 2669ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2670ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2671ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2672ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26738427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26748427bbc2SKai-Heng Feng /* 26758427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2676467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2677467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2678467c77d4SJarosław Janik * ASUS PRIME Z370-A 26798427bbc2SKai-Heng Feng */ 26808427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2681467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2682467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 26838427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2684ff5350a8SAndy Lutomirski } 2685ff5350a8SAndy Lutomirski 2686ff5350a8SAndy Lutomirski return 0; 2687ff5350a8SAndy Lutomirski } 2688ff5350a8SAndy Lutomirski 268918119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 269018119775SKeith Busch { 269118119775SKeith Busch struct nvme_dev *dev = data; 269280f513b5SKeith Busch 269318119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 269418119775SKeith Busch flush_work(&dev->ctrl.scan_work); 269580f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 269618119775SKeith Busch } 269718119775SKeith Busch 269857dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 269957dacad5SJay Sternberg { 270057dacad5SJay Sternberg int node, result = -ENOMEM; 270157dacad5SJay Sternberg struct nvme_dev *dev; 2702ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2703943e942eSJens Axboe size_t alloc_size; 270457dacad5SJay Sternberg 270557dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 270657dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27072fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 270857dacad5SJay Sternberg 270957dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 271057dacad5SJay Sternberg if (!dev) 271157dacad5SJay Sternberg return -ENOMEM; 2712147b27e4SSagi Grimberg 27133b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27143b6592f7SJens Axboe GFP_KERNEL, node); 271557dacad5SJay Sternberg if (!dev->queues) 271657dacad5SJay Sternberg goto free; 271757dacad5SJay Sternberg 271857dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 271957dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 272057dacad5SJay Sternberg 2721b00a726aSKeith Busch result = nvme_dev_map(dev); 2722b00a726aSKeith Busch if (result) 2723b00c9b7aSChristophe JAILLET goto put_pci; 2724b00a726aSKeith Busch 2725d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27265c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 272777bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2728f3ca80fcSChristoph Hellwig 2729f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2730f3ca80fcSChristoph Hellwig if (result) 2731b00c9b7aSChristophe JAILLET goto unmap; 2732f3ca80fcSChristoph Hellwig 27338427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2734ff5350a8SAndy Lutomirski 2735943e942eSJens Axboe /* 2736943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2737943e942eSJens Axboe * command we support. 2738943e942eSJens Axboe */ 2739943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2740943e942eSJens Axboe NVME_MAX_SEGS, true); 2741943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2742943e942eSJens Axboe 2743943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2744943e942eSJens Axboe mempool_kfree, 2745943e942eSJens Axboe (void *) alloc_size, 2746943e942eSJens Axboe GFP_KERNEL, node); 2747943e942eSJens Axboe if (!dev->iod_mempool) { 2748943e942eSJens Axboe result = -ENOMEM; 2749943e942eSJens Axboe goto release_pools; 2750943e942eSJens Axboe } 2751943e942eSJens Axboe 2752b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2753b6e44b4cSKeith Busch quirks); 2754b6e44b4cSKeith Busch if (result) 2755b6e44b4cSKeith Busch goto release_mempool; 2756b6e44b4cSKeith Busch 27571b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27581b3c47c1SSagi Grimberg 275980f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 276018119775SKeith Busch async_schedule(nvme_async_probe, dev); 27614caff8fcSSagi Grimberg 276257dacad5SJay Sternberg return 0; 276357dacad5SJay Sternberg 2764b6e44b4cSKeith Busch release_mempool: 2765b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 276657dacad5SJay Sternberg release_pools: 276757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2768b00c9b7aSChristophe JAILLET unmap: 2769b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 277057dacad5SJay Sternberg put_pci: 277157dacad5SJay Sternberg put_device(dev->dev); 277257dacad5SJay Sternberg free: 277357dacad5SJay Sternberg kfree(dev->queues); 277457dacad5SJay Sternberg kfree(dev); 277557dacad5SJay Sternberg return result; 277657dacad5SJay Sternberg } 277757dacad5SJay Sternberg 2778775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 277957dacad5SJay Sternberg { 278057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2781a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2782775755edSChristoph Hellwig } 278357dacad5SJay Sternberg 2784775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2785775755edSChristoph Hellwig { 2786f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 278779c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 278857dacad5SJay Sternberg } 278957dacad5SJay Sternberg 279057dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 279157dacad5SJay Sternberg { 279257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2793a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 279457dacad5SJay Sternberg } 279557dacad5SJay Sternberg 2796f58944e2SKeith Busch /* 2797f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2798f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2799f58944e2SKeith Busch * order to proceed. 2800f58944e2SKeith Busch */ 280157dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 280257dacad5SJay Sternberg { 280357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 280457dacad5SJay Sternberg 2805bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 280657dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28070ff9d4e1SKeith Busch 28086db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28090ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28101d39e692SKeith Busch nvme_dev_disable(dev, true); 2811cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28126db28edaSKeith Busch } 28130ff9d4e1SKeith Busch 2814d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2815d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2816d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2817a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28189fe5c59fSKeith Busch nvme_release_cmb(dev); 281987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 282057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 282157dacad5SJay Sternberg nvme_free_queues(dev, 0); 2822d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 282357dacad5SJay Sternberg nvme_release_prp_pools(dev); 2824b00a726aSKeith Busch nvme_dev_unmap(dev); 28251673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 282657dacad5SJay Sternberg } 282757dacad5SJay Sternberg 282857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 282957dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 283057dacad5SJay Sternberg { 283157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 283257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 283357dacad5SJay Sternberg 2834a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 283557dacad5SJay Sternberg return 0; 283657dacad5SJay Sternberg } 283757dacad5SJay Sternberg 283857dacad5SJay Sternberg static int nvme_resume(struct device *dev) 283957dacad5SJay Sternberg { 284057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 284157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 284257dacad5SJay Sternberg 2843d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 284457dacad5SJay Sternberg return 0; 284557dacad5SJay Sternberg } 284657dacad5SJay Sternberg #endif 284757dacad5SJay Sternberg 284857dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 284957dacad5SJay Sternberg 2850a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2851a0a3408eSKeith Busch pci_channel_state_t state) 2852a0a3408eSKeith Busch { 2853a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2854a0a3408eSKeith Busch 2855a0a3408eSKeith Busch /* 2856a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2857a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2858a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2859a0a3408eSKeith Busch */ 2860a0a3408eSKeith Busch switch (state) { 2861a0a3408eSKeith Busch case pci_channel_io_normal: 2862a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2863a0a3408eSKeith Busch case pci_channel_io_frozen: 2864d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2865d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2866a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2867a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2868a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2869d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2870d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2871a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2872a0a3408eSKeith Busch } 2873a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2874a0a3408eSKeith Busch } 2875a0a3408eSKeith Busch 2876a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2877a0a3408eSKeith Busch { 2878a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2879a0a3408eSKeith Busch 28801b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2881a0a3408eSKeith Busch pci_restore_state(pdev); 2882d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2883a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2884a0a3408eSKeith Busch } 2885a0a3408eSKeith Busch 2886a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2887a0a3408eSKeith Busch { 288872cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 288972cd4cc2SKeith Busch 289072cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2891a0a3408eSKeith Busch } 2892a0a3408eSKeith Busch 289357dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 289457dacad5SJay Sternberg .error_detected = nvme_error_detected, 289557dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 289657dacad5SJay Sternberg .resume = nvme_error_resume, 2897775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2898775755edSChristoph Hellwig .reset_done = nvme_reset_done, 289957dacad5SJay Sternberg }; 290057dacad5SJay Sternberg 290157dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2902106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 290308095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2904e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 290599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 290699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2907e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 290899466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 290999466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2910e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2911f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2912f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2913f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 291450af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29159abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29169abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 29176299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 29186299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2919540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 29207b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 29217b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 29220302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29230302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 292454adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 292554adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29268c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29278c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2928015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2929015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2930d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2931d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2932d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2933d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2934608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2935608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2936608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2937608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2938ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2939ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 294057dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2941c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2942124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 294357dacad5SJay Sternberg { 0, } 294457dacad5SJay Sternberg }; 294557dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 294657dacad5SJay Sternberg 294757dacad5SJay Sternberg static struct pci_driver nvme_driver = { 294857dacad5SJay Sternberg .name = "nvme", 294957dacad5SJay Sternberg .id_table = nvme_id_table, 295057dacad5SJay Sternberg .probe = nvme_probe, 295157dacad5SJay Sternberg .remove = nvme_remove, 295257dacad5SJay Sternberg .shutdown = nvme_shutdown, 295357dacad5SJay Sternberg .driver = { 295457dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 295557dacad5SJay Sternberg }, 295674d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 295757dacad5SJay Sternberg .err_handler = &nvme_err_handler, 295857dacad5SJay Sternberg }; 295957dacad5SJay Sternberg 296057dacad5SJay Sternberg static int __init nvme_init(void) 296157dacad5SJay Sternberg { 2962612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 29639a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 296457dacad5SJay Sternberg } 296557dacad5SJay Sternberg 296657dacad5SJay Sternberg static void __exit nvme_exit(void) 296757dacad5SJay Sternberg { 296857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 296903e0f3a6SMing Lei flush_workqueue(nvme_wq); 297057dacad5SJay Sternberg _nvme_check_size(); 297157dacad5SJay Sternberg } 297257dacad5SJay Sternberg 297357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 297457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 297557dacad5SJay Sternberg MODULE_VERSION("1.0"); 297657dacad5SJay Sternberg module_init(nvme_init); 297757dacad5SJay Sternberg module_exit(nvme_exit); 2978