157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 3357dacad5SJay Sternberg 3457dacad5SJay Sternberg #include "nvme.h" 3557dacad5SJay Sternberg 3657dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3757dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3857dacad5SJay Sternberg 39a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40adf68f21SChristoph Hellwig 4157dacad5SJay Sternberg static int use_threaded_interrupts; 4257dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4357dacad5SJay Sternberg 4457dacad5SJay Sternberg static bool use_cmb_sqes = true; 4557dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 4657dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4757dacad5SJay Sternberg 4887ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 4987ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5087ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5187ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5257dacad5SJay Sternberg 53a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 54a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 55a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 56a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 57a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 58a7a7cbe3SChaitanya Kulkarni 59b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 60b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 61b27c1e68Sweiping zhang .set = io_queue_depth_set, 62b27c1e68Sweiping zhang .get = param_get_int, 63b27c1e68Sweiping zhang }; 64b27c1e68Sweiping zhang 65b27c1e68Sweiping zhang static int io_queue_depth = 1024; 66b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 67b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 68b27c1e68Sweiping zhang 691c63dc66SChristoph Hellwig struct nvme_dev; 701c63dc66SChristoph Hellwig struct nvme_queue; 7157dacad5SJay Sternberg 72a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7357dacad5SJay Sternberg 7457dacad5SJay Sternberg /* 751c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 761c63dc66SChristoph Hellwig */ 771c63dc66SChristoph Hellwig struct nvme_dev { 78147b27e4SSagi Grimberg struct nvme_queue *queues; 791c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 811c63dc66SChristoph Hellwig u32 __iomem *dbs; 821c63dc66SChristoph Hellwig struct device *dev; 831c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 841c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 851c63dc66SChristoph Hellwig unsigned online_queues; 861c63dc66SChristoph Hellwig unsigned max_qid; 8722b55601SKeith Busch unsigned int num_vecs; 881c63dc66SChristoph Hellwig int q_depth; 891c63dc66SChristoph Hellwig u32 db_stride; 901c63dc66SChristoph Hellwig void __iomem *bar; 9197f6ef64SXu Yu unsigned long bar_mapped_size; 925c8809e6SChristoph Hellwig struct work_struct remove_work; 9377bf25eaSKeith Busch struct mutex shutdown_lock; 941c63dc66SChristoph Hellwig bool subsystem; 951c63dc66SChristoph Hellwig void __iomem *cmb; 968969f1f8SChristoph Hellwig pci_bus_addr_t cmb_bus_addr; 971c63dc66SChristoph Hellwig u64 cmb_size; 981c63dc66SChristoph Hellwig u32 cmbsz; 99202021c1SStephen Bates u32 cmbloc; 1001c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 101db3cbfffSKeith Busch struct completion ioq_wait; 10287ad72a5SChristoph Hellwig 10387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 104f9f38e33SHelen Koike u32 *dbbuf_dbs; 105f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 106f9f38e33SHelen Koike u32 *dbbuf_eis; 107f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10887ad72a5SChristoph Hellwig 10987ad72a5SChristoph Hellwig /* host memory buffer support: */ 11087ad72a5SChristoph Hellwig u64 host_mem_size; 11187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1124033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 11387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11487ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11557dacad5SJay Sternberg }; 11657dacad5SJay Sternberg 117b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 118b27c1e68Sweiping zhang { 119b27c1e68Sweiping zhang int n = 0, ret; 120b27c1e68Sweiping zhang 121b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 122b27c1e68Sweiping zhang if (ret != 0 || n < 2) 123b27c1e68Sweiping zhang return -EINVAL; 124b27c1e68Sweiping zhang 125b27c1e68Sweiping zhang return param_set_int(val, kp); 126b27c1e68Sweiping zhang } 127b27c1e68Sweiping zhang 128f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 129f9f38e33SHelen Koike { 130f9f38e33SHelen Koike return qid * 2 * stride; 131f9f38e33SHelen Koike } 132f9f38e33SHelen Koike 133f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 134f9f38e33SHelen Koike { 135f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 136f9f38e33SHelen Koike } 137f9f38e33SHelen Koike 1381c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1391c63dc66SChristoph Hellwig { 1401c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1411c63dc66SChristoph Hellwig } 1421c63dc66SChristoph Hellwig 14357dacad5SJay Sternberg /* 14457dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14557dacad5SJay Sternberg * commands and one for I/O commands). 14657dacad5SJay Sternberg */ 14757dacad5SJay Sternberg struct nvme_queue { 14857dacad5SJay Sternberg struct device *q_dmadev; 14957dacad5SJay Sternberg struct nvme_dev *dev; 1501ab0cd69SJens Axboe spinlock_t sq_lock; 15157dacad5SJay Sternberg struct nvme_command *sq_cmds; 15257dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 1531ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 15457dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15557dacad5SJay Sternberg struct blk_mq_tags **tags; 15657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15857dacad5SJay Sternberg u32 __iomem *q_db; 15957dacad5SJay Sternberg u16 q_depth; 16057dacad5SJay Sternberg s16 cq_vector; 16157dacad5SJay Sternberg u16 sq_tail; 16257dacad5SJay Sternberg u16 cq_head; 16368fa9dbeSJens Axboe u16 last_cq_head; 16457dacad5SJay Sternberg u16 qid; 16557dacad5SJay Sternberg u8 cq_phase; 166f9f38e33SHelen Koike u32 *dbbuf_sq_db; 167f9f38e33SHelen Koike u32 *dbbuf_cq_db; 168f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 169f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 17057dacad5SJay Sternberg }; 17157dacad5SJay Sternberg 17257dacad5SJay Sternberg /* 17371bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17471bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 175f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17671bd150cSChristoph Hellwig * allocated to store the PRP list. 17771bd150cSChristoph Hellwig */ 17871bd150cSChristoph Hellwig struct nvme_iod { 179d49187e9SChristoph Hellwig struct nvme_request req; 180f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 181a7a7cbe3SChaitanya Kulkarni bool use_sgl; 182f4800d6dSChristoph Hellwig int aborted; 18371bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18471bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18571bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18671bd150cSChristoph Hellwig dma_addr_t first_dma; 187bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 188f4800d6dSChristoph Hellwig struct scatterlist *sg; 189f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 19057dacad5SJay Sternberg }; 19157dacad5SJay Sternberg 19257dacad5SJay Sternberg /* 19357dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19457dacad5SJay Sternberg */ 19557dacad5SJay Sternberg static inline void _nvme_check_size(void) 19657dacad5SJay Sternberg { 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2050add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2060add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 209f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 210f9f38e33SHelen Koike } 211f9f38e33SHelen Koike 212f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 213f9f38e33SHelen Koike { 214f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 215f9f38e33SHelen Koike } 216f9f38e33SHelen Koike 217f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 218f9f38e33SHelen Koike { 219f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike if (dev->dbbuf_dbs) 222f9f38e33SHelen Koike return 0; 223f9f38e33SHelen Koike 224f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 225f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 226f9f38e33SHelen Koike GFP_KERNEL); 227f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 228f9f38e33SHelen Koike return -ENOMEM; 229f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 230f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 231f9f38e33SHelen Koike GFP_KERNEL); 232f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 233f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 234f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 235f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 236f9f38e33SHelen Koike return -ENOMEM; 237f9f38e33SHelen Koike } 238f9f38e33SHelen Koike 239f9f38e33SHelen Koike return 0; 240f9f38e33SHelen Koike } 241f9f38e33SHelen Koike 242f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 243f9f38e33SHelen Koike { 244f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 245f9f38e33SHelen Koike 246f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 247f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 248f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 249f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 250f9f38e33SHelen Koike } 251f9f38e33SHelen Koike if (dev->dbbuf_eis) { 252f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 253f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 254f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 255f9f38e33SHelen Koike } 256f9f38e33SHelen Koike } 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 259f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 260f9f38e33SHelen Koike { 261f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 262f9f38e33SHelen Koike return; 263f9f38e33SHelen Koike 264f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 266f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 267f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 268f9f38e33SHelen Koike } 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike struct nvme_command c; 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 275f9f38e33SHelen Koike return; 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 278f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 279f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 280f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 281f9f38e33SHelen Koike 282f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2839bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 284f9f38e33SHelen Koike /* Free memory and continue on */ 285f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike } 288f9f38e33SHelen Koike 289f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 290f9f38e33SHelen Koike { 291f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 295f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 296f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 297f9f38e33SHelen Koike { 298f9f38e33SHelen Koike if (dbbuf_db) { 299f9f38e33SHelen Koike u16 old_value; 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike /* 302f9f38e33SHelen Koike * Ensure that the queue is written before updating 303f9f38e33SHelen Koike * the doorbell in memory 304f9f38e33SHelen Koike */ 305f9f38e33SHelen Koike wmb(); 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike old_value = *dbbuf_db; 308f9f38e33SHelen Koike *dbbuf_db = value; 309f9f38e33SHelen Koike 310f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 311f9f38e33SHelen Koike return false; 312f9f38e33SHelen Koike } 313f9f38e33SHelen Koike 314f9f38e33SHelen Koike return true; 31557dacad5SJay Sternberg } 31657dacad5SJay Sternberg 31757dacad5SJay Sternberg /* 31857dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31957dacad5SJay Sternberg */ 32057dacad5SJay Sternberg #define NVME_INT_PAGES 2 3215fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 32257dacad5SJay Sternberg 32357dacad5SJay Sternberg /* 32457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32657dacad5SJay Sternberg * the I/O. 32757dacad5SJay Sternberg */ 32857dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32957dacad5SJay Sternberg { 3305fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3315fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 33257dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33357dacad5SJay Sternberg } 33457dacad5SJay Sternberg 335a7a7cbe3SChaitanya Kulkarni /* 336a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 337a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 338a7a7cbe3SChaitanya Kulkarni */ 339a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 340f4800d6dSChristoph Hellwig { 341a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 342f4800d6dSChristoph Hellwig } 343f4800d6dSChristoph Hellwig 344a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 345a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 34657dacad5SJay Sternberg { 347a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 348a7a7cbe3SChaitanya Kulkarni 349a7a7cbe3SChaitanya Kulkarni if (use_sgl) 350a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 351a7a7cbe3SChaitanya Kulkarni else 352a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 353a7a7cbe3SChaitanya Kulkarni 354a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 355a7a7cbe3SChaitanya Kulkarni } 356a7a7cbe3SChaitanya Kulkarni 357a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 358a7a7cbe3SChaitanya Kulkarni { 359a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 360a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 361a7a7cbe3SChaitanya Kulkarni use_sgl); 362a7a7cbe3SChaitanya Kulkarni 363a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 36457dacad5SJay Sternberg } 36557dacad5SJay Sternberg 36657dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36757dacad5SJay Sternberg unsigned int hctx_idx) 36857dacad5SJay Sternberg { 36957dacad5SJay Sternberg struct nvme_dev *dev = data; 370147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37157dacad5SJay Sternberg 37257dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37357dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37457dacad5SJay Sternberg WARN_ON(nvmeq->tags); 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg hctx->driver_data = nvmeq; 37757dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 37857dacad5SJay Sternberg return 0; 37957dacad5SJay Sternberg } 38057dacad5SJay Sternberg 38157dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38257dacad5SJay Sternberg { 38357dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 38457dacad5SJay Sternberg 38557dacad5SJay Sternberg nvmeq->tags = NULL; 38657dacad5SJay Sternberg } 38757dacad5SJay Sternberg 38857dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38957dacad5SJay Sternberg unsigned int hctx_idx) 39057dacad5SJay Sternberg { 39157dacad5SJay Sternberg struct nvme_dev *dev = data; 392147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39357dacad5SJay Sternberg 39457dacad5SJay Sternberg if (!nvmeq->tags) 39557dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 39657dacad5SJay Sternberg 39757dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39857dacad5SJay Sternberg hctx->driver_data = nvmeq; 39957dacad5SJay Sternberg return 0; 40057dacad5SJay Sternberg } 40157dacad5SJay Sternberg 402d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 403d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40457dacad5SJay Sternberg { 405d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 406f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4070350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 408147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40957dacad5SJay Sternberg 41057dacad5SJay Sternberg BUG_ON(!nvmeq); 411f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41257dacad5SJay Sternberg return 0; 41357dacad5SJay Sternberg } 41457dacad5SJay Sternberg 415dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 416dca51e78SChristoph Hellwig { 417dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 418dca51e78SChristoph Hellwig 41922b55601SKeith Busch return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 42022b55601SKeith Busch dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 421dca51e78SChristoph Hellwig } 422dca51e78SChristoph Hellwig 42357dacad5SJay Sternberg /** 42490ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 42557dacad5SJay Sternberg * @nvmeq: The queue to use 42657dacad5SJay Sternberg * @cmd: The command to send 42757dacad5SJay Sternberg */ 42890ea5ca4SChristoph Hellwig static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 42957dacad5SJay Sternberg { 43090ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 43157dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 43290ea5ca4SChristoph Hellwig memcpy_toio(&nvmeq->sq_cmds_io[nvmeq->sq_tail], cmd, 43390ea5ca4SChristoph Hellwig sizeof(*cmd)); 43457dacad5SJay Sternberg else 43590ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 43657dacad5SJay Sternberg 43790ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 43890ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 43990ea5ca4SChristoph Hellwig if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 44090ea5ca4SChristoph Hellwig nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 44190ea5ca4SChristoph Hellwig writel(nvmeq->sq_tail, nvmeq->q_db); 44290ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 445a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 44657dacad5SJay Sternberg { 447f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 448a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 44957dacad5SJay Sternberg } 45057dacad5SJay Sternberg 451955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 452955b1b5aSMinwoo Im { 453955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 45420469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 455955b1b5aSMinwoo Im unsigned int avg_seg_size; 456955b1b5aSMinwoo Im 45720469a37SKeith Busch if (nseg == 0) 45820469a37SKeith Busch return false; 45920469a37SKeith Busch 46020469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 461955b1b5aSMinwoo Im 462955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 463955b1b5aSMinwoo Im return false; 464955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 465955b1b5aSMinwoo Im return false; 466955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 467955b1b5aSMinwoo Im return false; 468955b1b5aSMinwoo Im return true; 469955b1b5aSMinwoo Im } 470955b1b5aSMinwoo Im 471fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 47257dacad5SJay Sternberg { 473f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 474f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 475b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 476f4800d6dSChristoph Hellwig 477955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 478955b1b5aSMinwoo Im 479f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 480a7a7cbe3SChaitanya Kulkarni size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, 481a7a7cbe3SChaitanya Kulkarni iod->use_sgl); 482a7a7cbe3SChaitanya Kulkarni 483a7a7cbe3SChaitanya Kulkarni iod->sg = kmalloc(alloc_size, GFP_ATOMIC); 484f4800d6dSChristoph Hellwig if (!iod->sg) 485fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 486f4800d6dSChristoph Hellwig } else { 487f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 48857dacad5SJay Sternberg } 48957dacad5SJay Sternberg 490f4800d6dSChristoph Hellwig iod->aborted = 0; 49157dacad5SJay Sternberg iod->npages = -1; 49257dacad5SJay Sternberg iod->nents = 0; 493f4800d6dSChristoph Hellwig iod->length = size; 494f80ec966SKeith Busch 495fc17b653SChristoph Hellwig return BLK_STS_OK; 49657dacad5SJay Sternberg } 49757dacad5SJay Sternberg 498f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 49957dacad5SJay Sternberg { 500f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 501a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 502a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 503a7a7cbe3SChaitanya Kulkarni 50457dacad5SJay Sternberg int i; 50557dacad5SJay Sternberg 50657dacad5SJay Sternberg if (iod->npages == 0) 507a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 508a7a7cbe3SChaitanya Kulkarni dma_addr); 509a7a7cbe3SChaitanya Kulkarni 51057dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 511a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 512a7a7cbe3SChaitanya Kulkarni 513a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 514a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 515a7a7cbe3SChaitanya Kulkarni 516a7a7cbe3SChaitanya Kulkarni next_dma_addr = 517a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 518a7a7cbe3SChaitanya Kulkarni } else { 519a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 520a7a7cbe3SChaitanya Kulkarni 521a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 522a7a7cbe3SChaitanya Kulkarni } 523a7a7cbe3SChaitanya Kulkarni 524a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 525a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg 528f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 529f4800d6dSChristoph Hellwig kfree(iod->sg); 53057dacad5SJay Sternberg } 53157dacad5SJay Sternberg 53257dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 53357dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53457dacad5SJay Sternberg { 53557dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 53657dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 53757dacad5SJay Sternberg } 53857dacad5SJay Sternberg 53957dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54057dacad5SJay Sternberg { 54157dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 54257dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 54357dacad5SJay Sternberg } 54457dacad5SJay Sternberg 54557dacad5SJay Sternberg /** 54657dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 54757dacad5SJay Sternberg * 54857dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 54957dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 55057dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 55157dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 55257dacad5SJay Sternberg * 55357dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 55457dacad5SJay Sternberg */ 55557dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 55657dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 55757dacad5SJay Sternberg { 55857dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 55957dacad5SJay Sternberg struct bio_integrity_payload *bip; 56057dacad5SJay Sternberg struct t10_pi_tuple *pi; 56157dacad5SJay Sternberg void *p, *pmap; 56257dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 56357dacad5SJay Sternberg 56457dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 56557dacad5SJay Sternberg return; 56657dacad5SJay Sternberg 56757dacad5SJay Sternberg bip = bio_integrity(req->bio); 56857dacad5SJay Sternberg if (!bip) 56957dacad5SJay Sternberg return; 57057dacad5SJay Sternberg 57157dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 57257dacad5SJay Sternberg 57357dacad5SJay Sternberg p = pmap; 57457dacad5SJay Sternberg virt = bip_get_seed(bip); 57557dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 57657dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 577ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 57857dacad5SJay Sternberg 57957dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 58057dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 58157dacad5SJay Sternberg dif_swap(phys, virt, pi); 58257dacad5SJay Sternberg p += ts; 58357dacad5SJay Sternberg } 58457dacad5SJay Sternberg kunmap_atomic(pmap); 58557dacad5SJay Sternberg } 58657dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 58757dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 58857dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 58957dacad5SJay Sternberg { 59057dacad5SJay Sternberg } 59157dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 59257dacad5SJay Sternberg { 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 59557dacad5SJay Sternberg { 59657dacad5SJay Sternberg } 59757dacad5SJay Sternberg #endif 59857dacad5SJay Sternberg 599d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 600d0877473SKeith Busch { 601d0877473SKeith Busch int i; 602d0877473SKeith Busch struct scatterlist *sg; 603d0877473SKeith Busch 604d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 605d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 606d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 607d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 608d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 609d0877473SKeith Busch sg_dma_len(sg)); 610d0877473SKeith Busch } 611d0877473SKeith Busch } 612d0877473SKeith Busch 613a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 614a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 61557dacad5SJay Sternberg { 616f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 61757dacad5SJay Sternberg struct dma_pool *pool; 618b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61957dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 62057dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 62157dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6225fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 62357dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 62457dacad5SJay Sternberg __le64 *prp_list; 625a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 62657dacad5SJay Sternberg dma_addr_t prp_dma; 62757dacad5SJay Sternberg int nprps, i; 62857dacad5SJay Sternberg 62957dacad5SJay Sternberg length -= (page_size - offset); 6305228b328SJan H. Schönherr if (length <= 0) { 6315228b328SJan H. Schönherr iod->first_dma = 0; 632a7a7cbe3SChaitanya Kulkarni goto done; 6335228b328SJan H. Schönherr } 63457dacad5SJay Sternberg 63557dacad5SJay Sternberg dma_len -= (page_size - offset); 63657dacad5SJay Sternberg if (dma_len) { 63757dacad5SJay Sternberg dma_addr += (page_size - offset); 63857dacad5SJay Sternberg } else { 63957dacad5SJay Sternberg sg = sg_next(sg); 64057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 64257dacad5SJay Sternberg } 64357dacad5SJay Sternberg 64457dacad5SJay Sternberg if (length <= page_size) { 64557dacad5SJay Sternberg iod->first_dma = dma_addr; 646a7a7cbe3SChaitanya Kulkarni goto done; 64757dacad5SJay Sternberg } 64857dacad5SJay Sternberg 64957dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 65057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 65157dacad5SJay Sternberg pool = dev->prp_small_pool; 65257dacad5SJay Sternberg iod->npages = 0; 65357dacad5SJay Sternberg } else { 65457dacad5SJay Sternberg pool = dev->prp_page_pool; 65557dacad5SJay Sternberg iod->npages = 1; 65657dacad5SJay Sternberg } 65757dacad5SJay Sternberg 65869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65957dacad5SJay Sternberg if (!prp_list) { 66057dacad5SJay Sternberg iod->first_dma = dma_addr; 66157dacad5SJay Sternberg iod->npages = -1; 66286eea289SKeith Busch return BLK_STS_RESOURCE; 66357dacad5SJay Sternberg } 66457dacad5SJay Sternberg list[0] = prp_list; 66557dacad5SJay Sternberg iod->first_dma = prp_dma; 66657dacad5SJay Sternberg i = 0; 66757dacad5SJay Sternberg for (;;) { 66857dacad5SJay Sternberg if (i == page_size >> 3) { 66957dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67157dacad5SJay Sternberg if (!prp_list) 67286eea289SKeith Busch return BLK_STS_RESOURCE; 67357dacad5SJay Sternberg list[iod->npages++] = prp_list; 67457dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 67557dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 67657dacad5SJay Sternberg i = 1; 67757dacad5SJay Sternberg } 67857dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 67957dacad5SJay Sternberg dma_len -= page_size; 68057dacad5SJay Sternberg dma_addr += page_size; 68157dacad5SJay Sternberg length -= page_size; 68257dacad5SJay Sternberg if (length <= 0) 68357dacad5SJay Sternberg break; 68457dacad5SJay Sternberg if (dma_len > 0) 68557dacad5SJay Sternberg continue; 68686eea289SKeith Busch if (unlikely(dma_len < 0)) 68786eea289SKeith Busch goto bad_sgl; 68857dacad5SJay Sternberg sg = sg_next(sg); 68957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69157dacad5SJay Sternberg } 69257dacad5SJay Sternberg 693a7a7cbe3SChaitanya Kulkarni done: 694a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 695a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 696a7a7cbe3SChaitanya Kulkarni 69786eea289SKeith Busch return BLK_STS_OK; 69886eea289SKeith Busch 69986eea289SKeith Busch bad_sgl: 700d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 701d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 702d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 70386eea289SKeith Busch return BLK_STS_IOERR; 70457dacad5SJay Sternberg } 70557dacad5SJay Sternberg 706a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 707a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 708a7a7cbe3SChaitanya Kulkarni { 709a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 710a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 711a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 712a7a7cbe3SChaitanya Kulkarni } 713a7a7cbe3SChaitanya Kulkarni 714a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 715a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 716a7a7cbe3SChaitanya Kulkarni { 717a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 718a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 719a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 720a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 721a7a7cbe3SChaitanya Kulkarni } else { 722a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 723a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 724a7a7cbe3SChaitanya Kulkarni } 725a7a7cbe3SChaitanya Kulkarni } 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 728b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 729a7a7cbe3SChaitanya Kulkarni { 730a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 731a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 732a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 733a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 734a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 735b0f2853bSChristoph Hellwig int i = 0; 736a7a7cbe3SChaitanya Kulkarni 737a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 738a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 739a7a7cbe3SChaitanya Kulkarni 740b0f2853bSChristoph Hellwig if (entries == 1) { 741a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 742a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 743a7a7cbe3SChaitanya Kulkarni } 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 746a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 747a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 748a7a7cbe3SChaitanya Kulkarni } else { 749a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 750a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 751a7a7cbe3SChaitanya Kulkarni } 752a7a7cbe3SChaitanya Kulkarni 753a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 754a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 755a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 756a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 757a7a7cbe3SChaitanya Kulkarni } 758a7a7cbe3SChaitanya Kulkarni 759a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 760a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni do { 765a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 766a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 767a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 768a7a7cbe3SChaitanya Kulkarni 769a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 770a7a7cbe3SChaitanya Kulkarni if (!sg_list) 771a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni i = 0; 774a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 775a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 776a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 780a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 781b0f2853bSChristoph Hellwig } while (--entries > 0); 782a7a7cbe3SChaitanya Kulkarni 783a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 784a7a7cbe3SChaitanya Kulkarni } 785a7a7cbe3SChaitanya Kulkarni 786fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 787b131c61dSChristoph Hellwig struct nvme_command *cmnd) 78857dacad5SJay Sternberg { 789f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 790ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 791ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 792ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 793fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 794b0f2853bSChristoph Hellwig int nr_mapped; 79557dacad5SJay Sternberg 796f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 797ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 798ba1ca37eSChristoph Hellwig if (!iod->nents) 799ba1ca37eSChristoph Hellwig goto out; 800ba1ca37eSChristoph Hellwig 801fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 802b0f2853bSChristoph Hellwig nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 803b0f2853bSChristoph Hellwig DMA_ATTR_NO_WARN); 804b0f2853bSChristoph Hellwig if (!nr_mapped) 805ba1ca37eSChristoph Hellwig goto out; 806ba1ca37eSChristoph Hellwig 807955b1b5aSMinwoo Im if (iod->use_sgl) 808b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 809a7a7cbe3SChaitanya Kulkarni else 810a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 811a7a7cbe3SChaitanya Kulkarni 81286eea289SKeith Busch if (ret != BLK_STS_OK) 813ba1ca37eSChristoph Hellwig goto out_unmap; 814ba1ca37eSChristoph Hellwig 815fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 816ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 817ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 818ba1ca37eSChristoph Hellwig goto out_unmap; 819ba1ca37eSChristoph Hellwig 820bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 821bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 822ba1ca37eSChristoph Hellwig goto out_unmap; 823ba1ca37eSChristoph Hellwig 824b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 825ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 826ba1ca37eSChristoph Hellwig 827bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 828ba1ca37eSChristoph Hellwig goto out_unmap; 82957dacad5SJay Sternberg } 83057dacad5SJay Sternberg 831ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 832bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 833fc17b653SChristoph Hellwig return BLK_STS_OK; 834ba1ca37eSChristoph Hellwig 835ba1ca37eSChristoph Hellwig out_unmap: 836ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 837ba1ca37eSChristoph Hellwig out: 838ba1ca37eSChristoph Hellwig return ret; 83957dacad5SJay Sternberg } 84057dacad5SJay Sternberg 841f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 842d4f6c3abSChristoph Hellwig { 843f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 844d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 845d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 846d4f6c3abSChristoph Hellwig 847d4f6c3abSChristoph Hellwig if (iod->nents) { 848d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 849d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 850b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 851d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 852bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 853d4f6c3abSChristoph Hellwig } 854d4f6c3abSChristoph Hellwig } 855d4f6c3abSChristoph Hellwig 856f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 857f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 85857dacad5SJay Sternberg } 85957dacad5SJay Sternberg 86057dacad5SJay Sternberg /* 86157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86257dacad5SJay Sternberg */ 863fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86557dacad5SJay Sternberg { 86657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 86757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 86857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 86957dacad5SJay Sternberg struct request *req = bd->rq; 870ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 871ebe6d874SChristoph Hellwig blk_status_t ret; 87257dacad5SJay Sternberg 873d1f06f4aSJens Axboe /* 874d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 875d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 876d1f06f4aSJens Axboe */ 877d1f06f4aSJens Axboe if (unlikely(nvmeq->cq_vector < 0)) 878d1f06f4aSJens Axboe return BLK_STS_IOERR; 879d1f06f4aSJens Axboe 880f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 881fc17b653SChristoph Hellwig if (ret) 882f4800d6dSChristoph Hellwig return ret; 88357dacad5SJay Sternberg 884b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 885fc17b653SChristoph Hellwig if (ret) 886f9d03f96SChristoph Hellwig goto out_free_cmd; 88757dacad5SJay Sternberg 888fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 889b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 890fc17b653SChristoph Hellwig if (ret) 891f9d03f96SChristoph Hellwig goto out_cleanup_iod; 892fc17b653SChristoph Hellwig } 893ba1ca37eSChristoph Hellwig 894aae239e1SChristoph Hellwig blk_mq_start_request(req); 89590ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &cmnd); 896fc17b653SChristoph Hellwig return BLK_STS_OK; 897f9d03f96SChristoph Hellwig out_cleanup_iod: 898f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 899f9d03f96SChristoph Hellwig out_free_cmd: 900f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 901ba1ca37eSChristoph Hellwig return ret; 90257dacad5SJay Sternberg } 90357dacad5SJay Sternberg 90477f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 905eee417b0SChristoph Hellwig { 906f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 907eee417b0SChristoph Hellwig 90877f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 90977f02a7aSChristoph Hellwig nvme_complete_rq(req); 91057dacad5SJay Sternberg } 91157dacad5SJay Sternberg 912d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 913750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 914d783e0bdSMarta Rybczynska { 915750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 916750dde44SChristoph Hellwig nvmeq->cq_phase; 917d783e0bdSMarta Rybczynska } 918d783e0bdSMarta Rybczynska 919eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92057dacad5SJay Sternberg { 921eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92257dacad5SJay Sternberg 923eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 924eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 925eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 926eb281c82SSagi Grimberg } 927adf68f21SChristoph Hellwig 9285cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 92957dacad5SJay Sternberg { 9305cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 93157dacad5SJay Sternberg struct request *req; 932adf68f21SChristoph Hellwig 93383a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9341b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 935aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 93683a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 93783a12fb7SSagi Grimberg return; 938aae239e1SChristoph Hellwig } 939aae239e1SChristoph Hellwig 940adf68f21SChristoph Hellwig /* 941adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 942adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 943adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 944adf68f21SChristoph Hellwig * for them but rather special case them here. 945adf68f21SChristoph Hellwig */ 946adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 94738dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9487bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 94983a12fb7SSagi Grimberg cqe->status, &cqe->result); 950a0fa9647SJens Axboe return; 95157dacad5SJay Sternberg } 95257dacad5SJay Sternberg 95383a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 95483a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 95583a12fb7SSagi Grimberg } 95657dacad5SJay Sternberg 9575cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 95883a12fb7SSagi Grimberg { 9595cb525c8SJens Axboe while (start != end) { 9605cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9615cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9625cb525c8SJens Axboe start = 0; 9635cb525c8SJens Axboe } 9645cb525c8SJens Axboe } 96583a12fb7SSagi Grimberg 9665cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9675cb525c8SJens Axboe { 968920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 969920d13a8SSagi Grimberg nvmeq->cq_head = 0; 970920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 971920d13a8SSagi Grimberg } 972a0fa9647SJens Axboe } 973a0fa9647SJens Axboe 9745cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9755cb525c8SJens Axboe u16 *end, int tag) 976a0fa9647SJens Axboe { 9775cb525c8SJens Axboe bool found = false; 97883a12fb7SSagi Grimberg 9795cb525c8SJens Axboe *start = nvmeq->cq_head; 9805cb525c8SJens Axboe while (!found && nvme_cqe_pending(nvmeq)) { 9815cb525c8SJens Axboe if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 9825cb525c8SJens Axboe found = true; 9835cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 98457dacad5SJay Sternberg } 9855cb525c8SJens Axboe *end = nvmeq->cq_head; 98657dacad5SJay Sternberg 9875cb525c8SJens Axboe if (*start != *end) 988eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9895cb525c8SJens Axboe return found; 99057dacad5SJay Sternberg } 99157dacad5SJay Sternberg 99257dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 99357dacad5SJay Sternberg { 99457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 99568fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 9965cb525c8SJens Axboe u16 start, end; 9975cb525c8SJens Axboe 9981ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 99968fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 100068fa9dbeSJens Axboe ret = IRQ_HANDLED; 10015cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 100268fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10031ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 10045cb525c8SJens Axboe 100568fa9dbeSJens Axboe if (start != end) { 10065cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10075cb525c8SJens Axboe return IRQ_HANDLED; 100857dacad5SJay Sternberg } 100957dacad5SJay Sternberg 101068fa9dbeSJens Axboe return ret; 101157dacad5SJay Sternberg } 101257dacad5SJay Sternberg 101357dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 101457dacad5SJay Sternberg { 101557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1016750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 101757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1018d783e0bdSMarta Rybczynska return IRQ_NONE; 101957dacad5SJay Sternberg } 102057dacad5SJay Sternberg 10217776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1022a0fa9647SJens Axboe { 10235cb525c8SJens Axboe u16 start, end; 10245cb525c8SJens Axboe bool found; 1025a0fa9647SJens Axboe 1026750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 1027442e19b7SSagi Grimberg return 0; 1028442e19b7SSagi Grimberg 10291ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 10305cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10311ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 1032442e19b7SSagi Grimberg 10335cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1034442e19b7SSagi Grimberg return found; 1035a0fa9647SJens Axboe } 1036a0fa9647SJens Axboe 10377776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10387776db1cSKeith Busch { 10397776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10407776db1cSKeith Busch 10417776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10427776db1cSKeith Busch } 10437776db1cSKeith Busch 1044ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 104557dacad5SJay Sternberg { 1046f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1047147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 104857dacad5SJay Sternberg struct nvme_command c; 104957dacad5SJay Sternberg 105057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105157dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1052ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 105390ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &c); 105457dacad5SJay Sternberg } 105557dacad5SJay Sternberg 105657dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 105757dacad5SJay Sternberg { 105857dacad5SJay Sternberg struct nvme_command c; 105957dacad5SJay Sternberg 106057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106157dacad5SJay Sternberg c.delete_queue.opcode = opcode; 106257dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 106357dacad5SJay Sternberg 10641c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 106557dacad5SJay Sternberg } 106657dacad5SJay Sternberg 106757dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1068a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 106957dacad5SJay Sternberg { 107057dacad5SJay Sternberg struct nvme_command c; 107157dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 107257dacad5SJay Sternberg 107357dacad5SJay Sternberg /* 107416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 107557dacad5SJay Sternberg * is attached to the request. 107657dacad5SJay Sternberg */ 107757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 107857dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 107957dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 108057dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 108157dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 108257dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1083a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 108457dacad5SJay Sternberg 10851c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 108657dacad5SJay Sternberg } 108757dacad5SJay Sternberg 108857dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 108957dacad5SJay Sternberg struct nvme_queue *nvmeq) 109057dacad5SJay Sternberg { 10919abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 109257dacad5SJay Sternberg struct nvme_command c; 109381c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 109457dacad5SJay Sternberg 109557dacad5SJay Sternberg /* 10969abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 10979abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 10989abd68efSJens Axboe * URGENT. 10999abd68efSJens Axboe */ 11009abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11019abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11029abd68efSJens Axboe 11039abd68efSJens Axboe /* 110416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 110557dacad5SJay Sternberg * is attached to the request. 110657dacad5SJay Sternberg */ 110757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110857dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 110957dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 111057dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 111157dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 111257dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 111357dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 111457dacad5SJay Sternberg 11151c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 111657dacad5SJay Sternberg } 111757dacad5SJay Sternberg 111857dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 111957dacad5SJay Sternberg { 112057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 112157dacad5SJay Sternberg } 112257dacad5SJay Sternberg 112357dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 112457dacad5SJay Sternberg { 112557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 112657dacad5SJay Sternberg } 112757dacad5SJay Sternberg 11282a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 112957dacad5SJay Sternberg { 1130f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1131f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 113257dacad5SJay Sternberg 113327fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 113427fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1135e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1136e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 113757dacad5SJay Sternberg } 113857dacad5SJay Sternberg 1139b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1140b2a0eb1aSKeith Busch { 1141b2a0eb1aSKeith Busch 1142b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1143b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1144b2a0eb1aSKeith Busch */ 1145b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1146b2a0eb1aSKeith Busch 1147ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1148ad70062cSJianchao Wang switch (dev->ctrl.state) { 1149ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1150ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1151b2a0eb1aSKeith Busch return false; 1152ad70062cSJianchao Wang default: 1153ad70062cSJianchao Wang break; 1154ad70062cSJianchao Wang } 1155b2a0eb1aSKeith Busch 1156b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1157b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1158b2a0eb1aSKeith Busch */ 1159b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1160b2a0eb1aSKeith Busch return false; 1161b2a0eb1aSKeith Busch 1162b2a0eb1aSKeith Busch return true; 1163b2a0eb1aSKeith Busch } 1164b2a0eb1aSKeith Busch 1165b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1166b2a0eb1aSKeith Busch { 1167b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1168b2a0eb1aSKeith Busch u16 pci_status; 1169b2a0eb1aSKeith Busch int result; 1170b2a0eb1aSKeith Busch 1171b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1172b2a0eb1aSKeith Busch &pci_status); 1173b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1174b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1175b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1176b2a0eb1aSKeith Busch csts, pci_status); 1177b2a0eb1aSKeith Busch else 1178b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1179b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1180b2a0eb1aSKeith Busch csts, result); 1181b2a0eb1aSKeith Busch } 1182b2a0eb1aSKeith Busch 118331c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 118457dacad5SJay Sternberg { 1185f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1186f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 118757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 118857dacad5SJay Sternberg struct request *abort_req; 118957dacad5SJay Sternberg struct nvme_command cmd; 1190b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1191b2a0eb1aSKeith Busch 1192651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1193651438bbSWen Xiong * the recovery mechanism will surely fail. 1194651438bbSWen Xiong */ 1195651438bbSWen Xiong mb(); 1196651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1197651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1198651438bbSWen Xiong 1199b2a0eb1aSKeith Busch /* 1200b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1201b2a0eb1aSKeith Busch */ 1202b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1203b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1204b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1205d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1206db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1207b2a0eb1aSKeith Busch } 120857dacad5SJay Sternberg 120931c7c7d2SChristoph Hellwig /* 12107776db1cSKeith Busch * Did we miss an interrupt? 12117776db1cSKeith Busch */ 12127776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12137776db1cSKeith Busch dev_warn(dev->ctrl.device, 12147776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12157776db1cSKeith Busch req->tag, nvmeq->qid); 1216db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12177776db1cSKeith Busch } 12187776db1cSKeith Busch 12197776db1cSKeith Busch /* 1220fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1221fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1222fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1223db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1224fd634f41SChristoph Hellwig */ 12254244140dSKeith Busch switch (dev->ctrl.state) { 12264244140dSKeith Busch case NVME_CTRL_CONNECTING: 12274244140dSKeith Busch case NVME_CTRL_RESETTING: 1228b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1229fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1230fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1231a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 123227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1233db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12344244140dSKeith Busch default: 12354244140dSKeith Busch break; 1236fd634f41SChristoph Hellwig } 1237fd634f41SChristoph Hellwig 1238fd634f41SChristoph Hellwig /* 1239e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1240e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1241e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 124231c7c7d2SChristoph Hellwig */ 1243f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12441b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 124557dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 124657dacad5SJay Sternberg req->tag, nvmeq->qid); 1247a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1248d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1249e1569a16SKeith Busch 125027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1251db8c48e4SChristoph Hellwig return BLK_EH_DONE; 125257dacad5SJay Sternberg } 125357dacad5SJay Sternberg 1254e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1255e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1256e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1257e7a2a87dSChristoph Hellwig } 12587bf7d778SKeith Busch iod->aborted = 1; 125957dacad5SJay Sternberg 126057dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 126157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 126257dacad5SJay Sternberg cmd.abort.cid = req->tag; 126357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 126457dacad5SJay Sternberg 12651b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12661b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 126757dacad5SJay Sternberg req->tag, nvmeq->qid); 1268e7a2a87dSChristoph Hellwig 1269e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1270eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12716bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12726bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 127331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 127457dacad5SJay Sternberg } 127557dacad5SJay Sternberg 1276e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1277e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1278e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 127957dacad5SJay Sternberg 128057dacad5SJay Sternberg /* 128157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 128257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 128357dacad5SJay Sternberg * as the device then is in a faulty state. 128457dacad5SJay Sternberg */ 128557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 128657dacad5SJay Sternberg } 128757dacad5SJay Sternberg 128857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 128957dacad5SJay Sternberg { 129057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 129157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 129257dacad5SJay Sternberg if (nvmeq->sq_cmds) 129357dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 129457dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 129557dacad5SJay Sternberg } 129657dacad5SJay Sternberg 129757dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 129857dacad5SJay Sternberg { 129957dacad5SJay Sternberg int i; 130057dacad5SJay Sternberg 1301d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1302d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1303147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 130457dacad5SJay Sternberg } 130557dacad5SJay Sternberg } 130657dacad5SJay Sternberg 130757dacad5SJay Sternberg /** 130857dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 130957dacad5SJay Sternberg * @nvmeq - queue to suspend 131057dacad5SJay Sternberg */ 131157dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 131257dacad5SJay Sternberg { 131357dacad5SJay Sternberg int vector; 131457dacad5SJay Sternberg 13151ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 131657dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 13171ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 131857dacad5SJay Sternberg return 1; 131957dacad5SJay Sternberg } 13200ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 132157dacad5SJay Sternberg nvmeq->dev->online_queues--; 132257dacad5SJay Sternberg nvmeq->cq_vector = -1; 13231ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 132457dacad5SJay Sternberg 1325d1f06f4aSJens Axboe /* 1326d1f06f4aSJens Axboe * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1327d1f06f4aSJens Axboe * having to grab the lock. 1328d1f06f4aSJens Axboe */ 1329d1f06f4aSJens Axboe mb(); 133057dacad5SJay Sternberg 13311c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1332c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 133357dacad5SJay Sternberg 13340ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 133557dacad5SJay Sternberg 133657dacad5SJay Sternberg return 0; 133757dacad5SJay Sternberg } 133857dacad5SJay Sternberg 1339a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 134057dacad5SJay Sternberg { 1341147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 13425cb525c8SJens Axboe u16 start, end; 134357dacad5SJay Sternberg 1344a5cdb68cSKeith Busch if (shutdown) 1345a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1346a5cdb68cSKeith Busch else 134720d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 134857dacad5SJay Sternberg 13491ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 13505cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 13511ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 13525cb525c8SJens Axboe 13535cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 135457dacad5SJay Sternberg } 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 135757dacad5SJay Sternberg int entry_size) 135857dacad5SJay Sternberg { 135957dacad5SJay Sternberg int q_depth = dev->q_depth; 13605fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13615fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 136257dacad5SJay Sternberg 136357dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 136457dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13655fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 136657dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 136757dacad5SJay Sternberg 136857dacad5SJay Sternberg /* 136957dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 137057dacad5SJay Sternberg * would be better to map queues in system memory with the 137157dacad5SJay Sternberg * original depth 137257dacad5SJay Sternberg */ 137357dacad5SJay Sternberg if (q_depth < 64) 137457dacad5SJay Sternberg return -ENOMEM; 137557dacad5SJay Sternberg } 137657dacad5SJay Sternberg 137757dacad5SJay Sternberg return q_depth; 137857dacad5SJay Sternberg } 137957dacad5SJay Sternberg 138057dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 138157dacad5SJay Sternberg int qid, int depth) 138257dacad5SJay Sternberg { 1383815c6704SKeith Busch /* CMB SQEs will be mapped before creation */ 1384815c6704SKeith Busch if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1385815c6704SKeith Busch return 0; 1386815c6704SKeith Busch 138757dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 138857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 138957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 139057dacad5SJay Sternberg return -ENOMEM; 139157dacad5SJay Sternberg return 0; 139257dacad5SJay Sternberg } 139357dacad5SJay Sternberg 1394a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 139557dacad5SJay Sternberg { 1396147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 139757dacad5SJay Sternberg 139862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 139962314e40SKeith Busch return 0; 140057dacad5SJay Sternberg 140157dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 140257dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 140357dacad5SJay Sternberg if (!nvmeq->cqes) 140457dacad5SJay Sternberg goto free_nvmeq; 140557dacad5SJay Sternberg 140657dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 140757dacad5SJay Sternberg goto free_cqdma; 140857dacad5SJay Sternberg 140957dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 141057dacad5SJay Sternberg nvmeq->dev = dev; 14111ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14121ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 141357dacad5SJay Sternberg nvmeq->cq_head = 0; 141457dacad5SJay Sternberg nvmeq->cq_phase = 1; 141557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 141657dacad5SJay Sternberg nvmeq->q_depth = depth; 141757dacad5SJay Sternberg nvmeq->qid = qid; 141857dacad5SJay Sternberg nvmeq->cq_vector = -1; 1419d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 142057dacad5SJay Sternberg 1421147b27e4SSagi Grimberg return 0; 142257dacad5SJay Sternberg 142357dacad5SJay Sternberg free_cqdma: 142457dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 142557dacad5SJay Sternberg nvmeq->cq_dma_addr); 142657dacad5SJay Sternberg free_nvmeq: 1427147b27e4SSagi Grimberg return -ENOMEM; 142857dacad5SJay Sternberg } 142957dacad5SJay Sternberg 1430dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 143157dacad5SJay Sternberg { 14320ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14330ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14340ff199cbSChristoph Hellwig 14350ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14360ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14370ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14380ff199cbSChristoph Hellwig } else { 14390ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14400ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14410ff199cbSChristoph Hellwig } 144257dacad5SJay Sternberg } 144357dacad5SJay Sternberg 144457dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 144557dacad5SJay Sternberg { 144657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 144757dacad5SJay Sternberg 14481ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 144957dacad5SJay Sternberg nvmeq->sq_tail = 0; 145057dacad5SJay Sternberg nvmeq->cq_head = 0; 145157dacad5SJay Sternberg nvmeq->cq_phase = 1; 145257dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 145357dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1454f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 145557dacad5SJay Sternberg dev->online_queues++; 14561ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 145757dacad5SJay Sternberg } 145857dacad5SJay Sternberg 145957dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 146057dacad5SJay Sternberg { 146157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 146257dacad5SJay Sternberg int result; 1463a8e3e0bbSJianchao Wang s16 vector; 146457dacad5SJay Sternberg 1465815c6704SKeith Busch if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1466815c6704SKeith Busch unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1467815c6704SKeith Busch dev->ctrl.page_size); 1468815c6704SKeith Busch nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1469815c6704SKeith Busch nvmeq->sq_cmds_io = dev->cmb + offset; 1470815c6704SKeith Busch } 1471815c6704SKeith Busch 147222b55601SKeith Busch /* 147322b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 147422b55601SKeith Busch * has only one vector available. 147522b55601SKeith Busch */ 1476a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 1477a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1478ded45505SKeith Busch if (result) 1479ded45505SKeith Busch return result; 148057dacad5SJay Sternberg 148157dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 148257dacad5SJay Sternberg if (result < 0) 1483ded45505SKeith Busch return result; 1484ded45505SKeith Busch else if (result) 148557dacad5SJay Sternberg goto release_cq; 148657dacad5SJay Sternberg 1487a8e3e0bbSJianchao Wang /* 1488a8e3e0bbSJianchao Wang * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1489a8e3e0bbSJianchao Wang * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1490a8e3e0bbSJianchao Wang * xxx' warning if the create CQ/SQ command times out. 1491a8e3e0bbSJianchao Wang */ 1492a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1493161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1494dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 149557dacad5SJay Sternberg if (result < 0) 149657dacad5SJay Sternberg goto release_sq; 149757dacad5SJay Sternberg 149857dacad5SJay Sternberg return result; 149957dacad5SJay Sternberg 150057dacad5SJay Sternberg release_sq: 1501a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1502f25a2dfcSJianchao Wang dev->online_queues--; 150357dacad5SJay Sternberg adapter_delete_sq(dev, qid); 150457dacad5SJay Sternberg release_cq: 150557dacad5SJay Sternberg adapter_delete_cq(dev, qid); 150657dacad5SJay Sternberg return result; 150757dacad5SJay Sternberg } 150857dacad5SJay Sternberg 1509f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 151057dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 151177f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 151257dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 151357dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15140350815aSChristoph Hellwig .init_request = nvme_init_request, 151557dacad5SJay Sternberg .timeout = nvme_timeout, 151657dacad5SJay Sternberg }; 151757dacad5SJay Sternberg 1518f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 151957dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 152077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 152157dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 152257dacad5SJay Sternberg .init_request = nvme_init_request, 1523dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 152457dacad5SJay Sternberg .timeout = nvme_timeout, 1525a0fa9647SJens Axboe .poll = nvme_poll, 152657dacad5SJay Sternberg }; 152757dacad5SJay Sternberg 152857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 152957dacad5SJay Sternberg { 15301c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 153169d9a99cSKeith Busch /* 153269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 153369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 153469d9a99cSKeith Busch * queue to flush these to completion. 153569d9a99cSKeith Busch */ 1536c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15371c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 153857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 153957dacad5SJay Sternberg } 154057dacad5SJay Sternberg } 154157dacad5SJay Sternberg 154257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 154357dacad5SJay Sternberg { 15441c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 154557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 154657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1547e3e9d50cSKeith Busch 154838dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 154957dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 155057dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1551a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1552d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 155357dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 155457dacad5SJay Sternberg 155557dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 155657dacad5SJay Sternberg return -ENOMEM; 155734b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 155857dacad5SJay Sternberg 15591c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15601c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 156157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 156257dacad5SJay Sternberg return -ENOMEM; 156357dacad5SJay Sternberg } 15641c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 156557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15661c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 156757dacad5SJay Sternberg return -ENODEV; 156857dacad5SJay Sternberg } 156957dacad5SJay Sternberg } else 1570c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 157157dacad5SJay Sternberg 157257dacad5SJay Sternberg return 0; 157357dacad5SJay Sternberg } 157457dacad5SJay Sternberg 157597f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 157697f6ef64SXu Yu { 157797f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 157897f6ef64SXu Yu } 157997f6ef64SXu Yu 158097f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 158197f6ef64SXu Yu { 158297f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 158397f6ef64SXu Yu 158497f6ef64SXu Yu if (size <= dev->bar_mapped_size) 158597f6ef64SXu Yu return 0; 158697f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 158797f6ef64SXu Yu return -ENOMEM; 158897f6ef64SXu Yu if (dev->bar) 158997f6ef64SXu Yu iounmap(dev->bar); 159097f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 159197f6ef64SXu Yu if (!dev->bar) { 159297f6ef64SXu Yu dev->bar_mapped_size = 0; 159397f6ef64SXu Yu return -ENOMEM; 159497f6ef64SXu Yu } 159597f6ef64SXu Yu dev->bar_mapped_size = size; 159697f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 159797f6ef64SXu Yu 159897f6ef64SXu Yu return 0; 159997f6ef64SXu Yu } 160097f6ef64SXu Yu 160101ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 160257dacad5SJay Sternberg { 160357dacad5SJay Sternberg int result; 160457dacad5SJay Sternberg u32 aqa; 160557dacad5SJay Sternberg struct nvme_queue *nvmeq; 160657dacad5SJay Sternberg 160797f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 160897f6ef64SXu Yu if (result < 0) 160997f6ef64SXu Yu return result; 161097f6ef64SXu Yu 16118ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 161220d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 161357dacad5SJay Sternberg 16147a67cbeaSChristoph Hellwig if (dev->subsystem && 16157a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16167a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 161757dacad5SJay Sternberg 161820d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 161957dacad5SJay Sternberg if (result < 0) 162057dacad5SJay Sternberg return result; 162157dacad5SJay Sternberg 1622a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1623147b27e4SSagi Grimberg if (result) 1624147b27e4SSagi Grimberg return result; 162557dacad5SJay Sternberg 1626147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 162757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 162857dacad5SJay Sternberg aqa |= aqa << 16; 162957dacad5SJay Sternberg 16307a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16317a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16327a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 163357dacad5SJay Sternberg 163420d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 163557dacad5SJay Sternberg if (result) 1636d4875622SKeith Busch return result; 163757dacad5SJay Sternberg 163857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1639161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1640dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 164157dacad5SJay Sternberg if (result) { 164257dacad5SJay Sternberg nvmeq->cq_vector = -1; 1643d4875622SKeith Busch return result; 164457dacad5SJay Sternberg } 164557dacad5SJay Sternberg 164657dacad5SJay Sternberg return result; 164757dacad5SJay Sternberg } 164857dacad5SJay Sternberg 1649749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 165057dacad5SJay Sternberg { 1651949928c1SKeith Busch unsigned i, max; 1652749941f2SChristoph Hellwig int ret = 0; 165357dacad5SJay Sternberg 1654d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1655a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1656749941f2SChristoph Hellwig ret = -ENOMEM; 165757dacad5SJay Sternberg break; 1658749941f2SChristoph Hellwig } 1659749941f2SChristoph Hellwig } 166057dacad5SJay Sternberg 1661d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1662949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1663147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1664d4875622SKeith Busch if (ret) 166557dacad5SJay Sternberg break; 166657dacad5SJay Sternberg } 166757dacad5SJay Sternberg 1668749941f2SChristoph Hellwig /* 1669749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16708adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16718adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1672749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1673749941f2SChristoph Hellwig */ 1674749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 167557dacad5SJay Sternberg } 167657dacad5SJay Sternberg 1677202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1678202021c1SStephen Bates struct device_attribute *attr, 1679202021c1SStephen Bates char *buf) 1680202021c1SStephen Bates { 1681202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1682202021c1SStephen Bates 1683c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1684202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1685202021c1SStephen Bates } 1686202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1687202021c1SStephen Bates 168888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 168957dacad5SJay Sternberg { 169088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 169188de4598SChristoph Hellwig 169288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 169388de4598SChristoph Hellwig } 169488de4598SChristoph Hellwig 169588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 169688de4598SChristoph Hellwig { 169788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 169888de4598SChristoph Hellwig } 169988de4598SChristoph Hellwig 1700f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 170157dacad5SJay Sternberg { 170288de4598SChristoph Hellwig u64 size, offset; 170357dacad5SJay Sternberg resource_size_t bar_size; 170457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17058969f1f8SChristoph Hellwig int bar; 170657dacad5SJay Sternberg 17077a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1708f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1709f65efd6dSChristoph Hellwig return; 1710202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 171157dacad5SJay Sternberg 1712202021c1SStephen Bates if (!use_cmb_sqes) 1713f65efd6dSChristoph Hellwig return; 171457dacad5SJay Sternberg 171588de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 171688de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17178969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17188969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 171957dacad5SJay Sternberg 172057dacad5SJay Sternberg if (offset > bar_size) 1721f65efd6dSChristoph Hellwig return; 172257dacad5SJay Sternberg 172357dacad5SJay Sternberg /* 172457dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 172557dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 172657dacad5SJay Sternberg * the reported size of the BAR 172757dacad5SJay Sternberg */ 172857dacad5SJay Sternberg if (size > bar_size - offset) 172957dacad5SJay Sternberg size = bar_size - offset; 173057dacad5SJay Sternberg 1731f65efd6dSChristoph Hellwig dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1732f65efd6dSChristoph Hellwig if (!dev->cmb) 1733f65efd6dSChristoph Hellwig return; 17348969f1f8SChristoph Hellwig dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 173557dacad5SJay Sternberg dev->cmb_size = size; 1736f65efd6dSChristoph Hellwig 1737f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1738f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1739f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1740f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 174157dacad5SJay Sternberg } 174257dacad5SJay Sternberg 174357dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 174457dacad5SJay Sternberg { 174557dacad5SJay Sternberg if (dev->cmb) { 174657dacad5SJay Sternberg iounmap(dev->cmb); 174757dacad5SJay Sternberg dev->cmb = NULL; 1748f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1749f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1750f63572dfSJon Derrick dev->cmbsz = 0; 1751f63572dfSJon Derrick } 175257dacad5SJay Sternberg } 175357dacad5SJay Sternberg 175487ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 175557dacad5SJay Sternberg { 17564033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 175787ad72a5SChristoph Hellwig struct nvme_command c; 175887ad72a5SChristoph Hellwig int ret; 175987ad72a5SChristoph Hellwig 176087ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 176187ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 176287ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 176387ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 176487ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 176587ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 176687ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 176787ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 176887ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 176987ad72a5SChristoph Hellwig 177087ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 177187ad72a5SChristoph Hellwig if (ret) { 177287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 177387ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 177487ad72a5SChristoph Hellwig ret, bits); 177587ad72a5SChristoph Hellwig } 177687ad72a5SChristoph Hellwig return ret; 177787ad72a5SChristoph Hellwig } 177887ad72a5SChristoph Hellwig 177987ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 178087ad72a5SChristoph Hellwig { 178187ad72a5SChristoph Hellwig int i; 178287ad72a5SChristoph Hellwig 178387ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 178487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 178587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 178687ad72a5SChristoph Hellwig 178787ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 178887ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 178987ad72a5SChristoph Hellwig } 179087ad72a5SChristoph Hellwig 179187ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 179287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17934033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17944033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 17954033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 179687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 17977e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 179887ad72a5SChristoph Hellwig } 179987ad72a5SChristoph Hellwig 180092dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 180192dc6895SChristoph Hellwig u32 chunk_size) 180287ad72a5SChristoph Hellwig { 180387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 180492dc6895SChristoph Hellwig u32 max_entries, len; 18054033f35dSChristoph Hellwig dma_addr_t descs_dma; 18062ee0e4edSDan Carpenter int i = 0; 180787ad72a5SChristoph Hellwig void **bufs; 18086fbcde66SMinwoo Im u64 size, tmp; 180987ad72a5SChristoph Hellwig 181087ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 181187ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 181287ad72a5SChristoph Hellwig max_entries = tmp; 1813044a9df1SChristoph Hellwig 1814044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1815044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1816044a9df1SChristoph Hellwig 18174033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 18184033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 181987ad72a5SChristoph Hellwig if (!descs) 182087ad72a5SChristoph Hellwig goto out; 182187ad72a5SChristoph Hellwig 182287ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 182387ad72a5SChristoph Hellwig if (!bufs) 182487ad72a5SChristoph Hellwig goto out_free_descs; 182587ad72a5SChristoph Hellwig 1826244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 182787ad72a5SChristoph Hellwig dma_addr_t dma_addr; 182887ad72a5SChristoph Hellwig 182950cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 183087ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 183187ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 183287ad72a5SChristoph Hellwig if (!bufs[i]) 183387ad72a5SChristoph Hellwig break; 183487ad72a5SChristoph Hellwig 183587ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 183687ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 183787ad72a5SChristoph Hellwig i++; 183887ad72a5SChristoph Hellwig } 183987ad72a5SChristoph Hellwig 184092dc6895SChristoph Hellwig if (!size) 184187ad72a5SChristoph Hellwig goto out_free_bufs; 184287ad72a5SChristoph Hellwig 184387ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 184487ad72a5SChristoph Hellwig dev->host_mem_size = size; 184587ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 18464033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 184787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 184887ad72a5SChristoph Hellwig return 0; 184987ad72a5SChristoph Hellwig 185087ad72a5SChristoph Hellwig out_free_bufs: 185187ad72a5SChristoph Hellwig while (--i >= 0) { 185287ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 185387ad72a5SChristoph Hellwig 185487ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 185587ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 185687ad72a5SChristoph Hellwig } 185787ad72a5SChristoph Hellwig 185887ad72a5SChristoph Hellwig kfree(bufs); 185987ad72a5SChristoph Hellwig out_free_descs: 18604033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18614033f35dSChristoph Hellwig descs_dma); 186287ad72a5SChristoph Hellwig out: 186387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 186487ad72a5SChristoph Hellwig return -ENOMEM; 186587ad72a5SChristoph Hellwig } 186687ad72a5SChristoph Hellwig 186792dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 186892dc6895SChristoph Hellwig { 186992dc6895SChristoph Hellwig u32 chunk_size; 187092dc6895SChristoph Hellwig 187192dc6895SChristoph Hellwig /* start big and work our way down */ 187230f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1873044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 187492dc6895SChristoph Hellwig chunk_size /= 2) { 187592dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 187692dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 187792dc6895SChristoph Hellwig return 0; 187892dc6895SChristoph Hellwig nvme_free_host_mem(dev); 187992dc6895SChristoph Hellwig } 188092dc6895SChristoph Hellwig } 188192dc6895SChristoph Hellwig 188292dc6895SChristoph Hellwig return -ENOMEM; 188392dc6895SChristoph Hellwig } 188492dc6895SChristoph Hellwig 18859620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 188687ad72a5SChristoph Hellwig { 188787ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 188887ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 188987ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 189087ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18916fbcde66SMinwoo Im int ret; 189287ad72a5SChristoph Hellwig 189387ad72a5SChristoph Hellwig preferred = min(preferred, max); 189487ad72a5SChristoph Hellwig if (min > max) { 189587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 189687ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 189787ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 189887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18999620cfbaSChristoph Hellwig return 0; 190087ad72a5SChristoph Hellwig } 190187ad72a5SChristoph Hellwig 190287ad72a5SChristoph Hellwig /* 190387ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 190487ad72a5SChristoph Hellwig */ 190587ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 190687ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 190787ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 190887ad72a5SChristoph Hellwig else 190987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 191087ad72a5SChristoph Hellwig } 191187ad72a5SChristoph Hellwig 191287ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 191392dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 191492dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 191592dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19169620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 191787ad72a5SChristoph Hellwig } 191887ad72a5SChristoph Hellwig 191992dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 192092dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 192192dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 192292dc6895SChristoph Hellwig } 192392dc6895SChristoph Hellwig 19249620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19259620cfbaSChristoph Hellwig if (ret) 192687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19279620cfbaSChristoph Hellwig return ret; 192857dacad5SJay Sternberg } 192957dacad5SJay Sternberg 193057dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 193157dacad5SJay Sternberg { 1932147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 193357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 193497f6ef64SXu Yu int result, nr_io_queues; 193597f6ef64SXu Yu unsigned long size; 193657dacad5SJay Sternberg 193722b55601SKeith Busch struct irq_affinity affd = { 193822b55601SKeith Busch .pre_vectors = 1 193922b55601SKeith Busch }; 194022b55601SKeith Busch 194116ccfff2SMing Lei nr_io_queues = num_possible_cpus(); 19429a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 19439a0be7abSChristoph Hellwig if (result < 0) 194457dacad5SJay Sternberg return result; 19459a0be7abSChristoph Hellwig 1946f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1947a5229050SKeith Busch return 0; 194857dacad5SJay Sternberg 194988de4598SChristoph Hellwig if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 195057dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 195157dacad5SJay Sternberg sizeof(struct nvme_command)); 195257dacad5SJay Sternberg if (result > 0) 195357dacad5SJay Sternberg dev->q_depth = result; 195457dacad5SJay Sternberg else 195557dacad5SJay Sternberg nvme_release_cmb(dev); 195657dacad5SJay Sternberg } 195757dacad5SJay Sternberg 195857dacad5SJay Sternberg do { 195997f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 196097f6ef64SXu Yu result = nvme_remap_bar(dev, size); 196197f6ef64SXu Yu if (!result) 196257dacad5SJay Sternberg break; 196357dacad5SJay Sternberg if (!--nr_io_queues) 196457dacad5SJay Sternberg return -ENOMEM; 196557dacad5SJay Sternberg } while (1); 196657dacad5SJay Sternberg adminq->q_db = dev->dbs; 196757dacad5SJay Sternberg 196857dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19690ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 197057dacad5SJay Sternberg 197157dacad5SJay Sternberg /* 197257dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 197357dacad5SJay Sternberg * setting up the full range we need. 197457dacad5SJay Sternberg */ 1975dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 197622b55601SKeith Busch result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 197722b55601SKeith Busch PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 197822b55601SKeith Busch if (result <= 0) 1979dca51e78SChristoph Hellwig return -EIO; 198022b55601SKeith Busch dev->num_vecs = result; 198122b55601SKeith Busch dev->max_qid = max(result - 1, 1); 198257dacad5SJay Sternberg 198357dacad5SJay Sternberg /* 198457dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 198557dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 198657dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 198757dacad5SJay Sternberg * number of interrupts. 198857dacad5SJay Sternberg */ 198957dacad5SJay Sternberg 1990dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 199157dacad5SJay Sternberg if (result) { 199257dacad5SJay Sternberg adminq->cq_vector = -1; 1993d4875622SKeith Busch return result; 199457dacad5SJay Sternberg } 1995749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 199657dacad5SJay Sternberg } 199757dacad5SJay Sternberg 19982a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1999db3cbfffSKeith Busch { 2000db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2001db3cbfffSKeith Busch 2002db3cbfffSKeith Busch blk_mq_free_request(req); 2003db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 2004db3cbfffSKeith Busch } 2005db3cbfffSKeith Busch 20062a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2007db3cbfffSKeith Busch { 2008db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 20095cb525c8SJens Axboe u16 start, end; 2010db3cbfffSKeith Busch 2011db3cbfffSKeith Busch if (!error) { 2012db3cbfffSKeith Busch unsigned long flags; 2013db3cbfffSKeith Busch 20140bc88192SKeith Busch spin_lock_irqsave(&nvmeq->cq_lock, flags); 20155cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 20161ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 20175cb525c8SJens Axboe 20185cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 2019db3cbfffSKeith Busch } 2020db3cbfffSKeith Busch 2021db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2022db3cbfffSKeith Busch } 2023db3cbfffSKeith Busch 2024db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2025db3cbfffSKeith Busch { 2026db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2027db3cbfffSKeith Busch struct request *req; 2028db3cbfffSKeith Busch struct nvme_command cmd; 2029db3cbfffSKeith Busch 2030db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2031db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2032db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2033db3cbfffSKeith Busch 2034eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2035db3cbfffSKeith Busch if (IS_ERR(req)) 2036db3cbfffSKeith Busch return PTR_ERR(req); 2037db3cbfffSKeith Busch 2038db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2039db3cbfffSKeith Busch req->end_io_data = nvmeq; 2040db3cbfffSKeith Busch 2041db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2042db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2043db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2044db3cbfffSKeith Busch return 0; 2045db3cbfffSKeith Busch } 2046db3cbfffSKeith Busch 2047ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2048db3cbfffSKeith Busch { 2049ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2050db3cbfffSKeith Busch unsigned long timeout; 2051db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2052db3cbfffSKeith Busch 2053db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2054014a0d60SKeith Busch int sent = 0, i = queues; 2055db3cbfffSKeith Busch 2056db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2057db3cbfffSKeith Busch retry: 2058db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2059c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2060147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2061db3cbfffSKeith Busch break; 2062c21377f8SGabriel Krisman Bertazi 2063db3cbfffSKeith Busch while (sent--) { 2064db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2065db3cbfffSKeith Busch if (timeout == 0) 2066db3cbfffSKeith Busch return; 2067db3cbfffSKeith Busch if (i) 2068db3cbfffSKeith Busch goto retry; 2069db3cbfffSKeith Busch } 2070db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2071db3cbfffSKeith Busch } 2072db3cbfffSKeith Busch } 2073db3cbfffSKeith Busch 207457dacad5SJay Sternberg /* 20752b1b7e78SJianchao Wang * return error value only when tagset allocation failed 207657dacad5SJay Sternberg */ 207757dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 207857dacad5SJay Sternberg { 20792b1b7e78SJianchao Wang int ret; 20802b1b7e78SJianchao Wang 20815bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 208257dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 208357dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 208457dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 208557dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 208657dacad5SJay Sternberg dev->tagset.queue_depth = 208757dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2088a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2089a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2090a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2091a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2092a7a7cbe3SChaitanya Kulkarni } 209357dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 209457dacad5SJay Sternberg dev->tagset.driver_data = dev; 209557dacad5SJay Sternberg 20962b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 20972b1b7e78SJianchao Wang if (ret) { 20982b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 20992b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 21002b1b7e78SJianchao Wang return ret; 21012b1b7e78SJianchao Wang } 21025bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2103f9f38e33SHelen Koike 2104f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2105949928c1SKeith Busch } else { 2106949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2107949928c1SKeith Busch 2108949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2109949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 211057dacad5SJay Sternberg } 2111949928c1SKeith Busch 211257dacad5SJay Sternberg return 0; 211357dacad5SJay Sternberg } 211457dacad5SJay Sternberg 2115b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 211657dacad5SJay Sternberg { 2117b00a726aSKeith Busch int result = -ENOMEM; 211857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 211957dacad5SJay Sternberg 212057dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 212157dacad5SJay Sternberg return result; 212257dacad5SJay Sternberg 212357dacad5SJay Sternberg pci_set_master(pdev); 212457dacad5SJay Sternberg 212557dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 212657dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 212757dacad5SJay Sternberg goto disable; 212857dacad5SJay Sternberg 21297a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 213057dacad5SJay Sternberg result = -ENODEV; 2131b00a726aSKeith Busch goto disable; 213257dacad5SJay Sternberg } 213357dacad5SJay Sternberg 213457dacad5SJay Sternberg /* 2135a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2136a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2137a5229050SKeith Busch * adjust this later. 213857dacad5SJay Sternberg */ 2139dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2140dca51e78SChristoph Hellwig if (result < 0) 2141dca51e78SChristoph Hellwig return result; 214257dacad5SJay Sternberg 214320d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 21447a67cbeaSChristoph Hellwig 214520d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2146b27c1e68Sweiping zhang io_queue_depth); 214720d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21487a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21491f390c1fSStephan Günther 21501f390c1fSStephan Günther /* 21511f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21521f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21531f390c1fSStephan Günther */ 21541f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21551f390c1fSStephan Günther dev->q_depth = 2; 21569bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21579bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21581f390c1fSStephan Günther dev->q_depth); 2159d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2160d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 216120d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2162d554b5e1SMartin K. Petersen dev->q_depth = 64; 2163d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2164d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21651f390c1fSStephan Günther } 21661f390c1fSStephan Günther 2167f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2168202021c1SStephen Bates 2169a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2170a0a3408eSKeith Busch pci_save_state(pdev); 217157dacad5SJay Sternberg return 0; 217257dacad5SJay Sternberg 217357dacad5SJay Sternberg disable: 217457dacad5SJay Sternberg pci_disable_device(pdev); 217557dacad5SJay Sternberg return result; 217657dacad5SJay Sternberg } 217757dacad5SJay Sternberg 217857dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 217957dacad5SJay Sternberg { 2180b00a726aSKeith Busch if (dev->bar) 2181b00a726aSKeith Busch iounmap(dev->bar); 2182a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2183b00a726aSKeith Busch } 2184b00a726aSKeith Busch 2185b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2186b00a726aSKeith Busch { 218757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 218857dacad5SJay Sternberg 2189f63572dfSJon Derrick nvme_release_cmb(dev); 2190dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 219157dacad5SJay Sternberg 2192a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2193a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 219457dacad5SJay Sternberg pci_disable_device(pdev); 219557dacad5SJay Sternberg } 2196a0a3408eSKeith Busch } 219757dacad5SJay Sternberg 2198a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 219957dacad5SJay Sternberg { 2200ee9aebb2SKeith Busch int i; 2201302ad8ccSKeith Busch bool dead = true; 2202302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 220357dacad5SJay Sternberg 220477bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2205302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2206302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2207302ad8ccSKeith Busch 2208ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2209ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2210302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2211302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2212302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 221357dacad5SJay Sternberg } 2214c21377f8SGabriel Krisman Bertazi 2215302ad8ccSKeith Busch /* 2216302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2217302ad8ccSKeith Busch * doing a safe shutdown. 2218302ad8ccSKeith Busch */ 221987ad72a5SChristoph Hellwig if (!dead) { 222087ad72a5SChristoph Hellwig if (shutdown) 2221302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 22229a915a5bSJianchao Wang } 222387ad72a5SChristoph Hellwig 22249a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 22259a915a5bSJianchao Wang 222664ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 222787ad72a5SChristoph Hellwig /* 222887ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 222987ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 223087ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 223187ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 223287ad72a5SChristoph Hellwig */ 223387ad72a5SChristoph Hellwig if (dev->host_mem_descs) 223487ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 2235ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2236a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 223757dacad5SJay Sternberg } 2238ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2239ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2240ee9aebb2SKeith Busch 2241b00a726aSKeith Busch nvme_pci_disable(dev); 224257dacad5SJay Sternberg 2243e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2244e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2245302ad8ccSKeith Busch 2246302ad8ccSKeith Busch /* 2247302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2248302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2249302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2250302ad8ccSKeith Busch */ 2251302ad8ccSKeith Busch if (shutdown) 2252302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 225377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 225457dacad5SJay Sternberg } 225557dacad5SJay Sternberg 225657dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 225757dacad5SJay Sternberg { 225857dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 225957dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 226057dacad5SJay Sternberg if (!dev->prp_page_pool) 226157dacad5SJay Sternberg return -ENOMEM; 226257dacad5SJay Sternberg 226357dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 226457dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 226557dacad5SJay Sternberg 256, 256, 0); 226657dacad5SJay Sternberg if (!dev->prp_small_pool) { 226757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 226857dacad5SJay Sternberg return -ENOMEM; 226957dacad5SJay Sternberg } 227057dacad5SJay Sternberg return 0; 227157dacad5SJay Sternberg } 227257dacad5SJay Sternberg 227357dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 227457dacad5SJay Sternberg { 227557dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 227657dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 227757dacad5SJay Sternberg } 227857dacad5SJay Sternberg 22791673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 228057dacad5SJay Sternberg { 22811673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 228257dacad5SJay Sternberg 2283f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 228457dacad5SJay Sternberg put_device(dev->dev); 228557dacad5SJay Sternberg if (dev->tagset.tags) 228657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22871c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22881c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 228957dacad5SJay Sternberg kfree(dev->queues); 2290e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 229157dacad5SJay Sternberg kfree(dev); 229257dacad5SJay Sternberg } 229357dacad5SJay Sternberg 2294f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2295f58944e2SKeith Busch { 2296237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2297f58944e2SKeith Busch 2298d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 229969d9a99cSKeith Busch nvme_dev_disable(dev, false); 230003e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2301f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2302f58944e2SKeith Busch } 2303f58944e2SKeith Busch 2304fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 230557dacad5SJay Sternberg { 2306d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2307d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2308a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2309f58944e2SKeith Busch int result = -ENODEV; 23102b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 231157dacad5SJay Sternberg 231282b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2313fd634f41SChristoph Hellwig goto out; 2314fd634f41SChristoph Hellwig 2315fd634f41SChristoph Hellwig /* 2316fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2317fd634f41SChristoph Hellwig * moving on. 2318fd634f41SChristoph Hellwig */ 2319b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2320a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2321fd634f41SChristoph Hellwig 2322ad70062cSJianchao Wang /* 2323ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2324ad70062cSJianchao Wang * initializing procedure here. 2325ad70062cSJianchao Wang */ 2326ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2327ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2328ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2329ad70062cSJianchao Wang goto out; 2330ad70062cSJianchao Wang } 2331ad70062cSJianchao Wang 2332b00a726aSKeith Busch result = nvme_pci_enable(dev); 233357dacad5SJay Sternberg if (result) 233457dacad5SJay Sternberg goto out; 233557dacad5SJay Sternberg 233601ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 233757dacad5SJay Sternberg if (result) 2338f58944e2SKeith Busch goto out; 233957dacad5SJay Sternberg 234057dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 234157dacad5SJay Sternberg if (result) 2342f58944e2SKeith Busch goto out; 234357dacad5SJay Sternberg 2344ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2345ce4541f4SChristoph Hellwig if (result) 2346f58944e2SKeith Busch goto out; 2347ce4541f4SChristoph Hellwig 2348e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2349e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23504f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23514f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2352e286bcfcSScott Bauer else if (was_suspend) 23534f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2354e286bcfcSScott Bauer } else { 2355e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2356e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2357e286bcfcSScott Bauer } 2358a98e58e5SScott Bauer 2359f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2360f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2361f9f38e33SHelen Koike if (result) 2362f9f38e33SHelen Koike dev_warn(dev->dev, 2363f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2364f9f38e33SHelen Koike } 2365f9f38e33SHelen Koike 23669620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23679620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23689620cfbaSChristoph Hellwig if (result < 0) 23699620cfbaSChristoph Hellwig goto out; 23709620cfbaSChristoph Hellwig } 237187ad72a5SChristoph Hellwig 237257dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 237357dacad5SJay Sternberg if (result) 2374f58944e2SKeith Busch goto out; 237557dacad5SJay Sternberg 237621f033f7SKeith Busch /* 237757dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 237857dacad5SJay Sternberg * any working I/O queue. 237957dacad5SJay Sternberg */ 238057dacad5SJay Sternberg if (dev->online_queues < 2) { 23811b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23823b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23835bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23842b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 238557dacad5SJay Sternberg } else { 238625646264SKeith Busch nvme_start_queues(&dev->ctrl); 2387302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23882b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23892b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23902b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2391302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 239257dacad5SJay Sternberg } 239357dacad5SJay Sternberg 23942b1b7e78SJianchao Wang /* 23952b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 23962b1b7e78SJianchao Wang * recovery. 23972b1b7e78SJianchao Wang */ 23982b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 23992b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 24002b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2401bb8d261eSChristoph Hellwig goto out; 2402bb8d261eSChristoph Hellwig } 240392911a55SChristoph Hellwig 2404d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 240557dacad5SJay Sternberg return; 240657dacad5SJay Sternberg 240757dacad5SJay Sternberg out: 2408f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 240957dacad5SJay Sternberg } 241057dacad5SJay Sternberg 24115c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 241257dacad5SJay Sternberg { 24135c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 241457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 241557dacad5SJay Sternberg 241669d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 241757dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2418921920abSKeith Busch device_release_driver(&pdev->dev); 24191673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 242057dacad5SJay Sternberg } 242157dacad5SJay Sternberg 24221c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 242357dacad5SJay Sternberg { 24241c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 24251c63dc66SChristoph Hellwig return 0; 242657dacad5SJay Sternberg } 24271c63dc66SChristoph Hellwig 24285fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 24295fd4ce1bSChristoph Hellwig { 24305fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 24315fd4ce1bSChristoph Hellwig return 0; 24325fd4ce1bSChristoph Hellwig } 24335fd4ce1bSChristoph Hellwig 24347fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 24357fd8930fSChristoph Hellwig { 24367fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24377fd8930fSChristoph Hellwig return 0; 24387fd8930fSChristoph Hellwig } 24397fd8930fSChristoph Hellwig 244097c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 244197c12223SKeith Busch { 244297c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 244397c12223SKeith Busch 244497c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 244597c12223SKeith Busch } 244697c12223SKeith Busch 24471c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24481a353d85SMing Lin .name = "pcie", 2449e439bb12SSagi Grimberg .module = THIS_MODULE, 2450c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24511c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24525fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24537fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24541673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2455f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 245697c12223SKeith Busch .get_address = nvme_pci_get_address, 24571c63dc66SChristoph Hellwig }; 245857dacad5SJay Sternberg 2459b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2460b00a726aSKeith Busch { 2461b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2462b00a726aSKeith Busch 2463a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2464b00a726aSKeith Busch return -ENODEV; 2465b00a726aSKeith Busch 246697f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2467b00a726aSKeith Busch goto release; 2468b00a726aSKeith Busch 2469b00a726aSKeith Busch return 0; 2470b00a726aSKeith Busch release: 2471a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2472b00a726aSKeith Busch return -ENODEV; 2473b00a726aSKeith Busch } 2474b00a726aSKeith Busch 24758427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2476ff5350a8SAndy Lutomirski { 2477ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2478ff5350a8SAndy Lutomirski /* 2479ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2480ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2481ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2482ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2483ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2484ff5350a8SAndy Lutomirski * laptops. 2485ff5350a8SAndy Lutomirski */ 2486ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2487ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2488ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2489ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24908427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24918427bbc2SKai-Heng Feng /* 24928427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2493467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2494467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2495467c77d4SJarosław Janik * ASUS PRIME Z370-A 24968427bbc2SKai-Heng Feng */ 24978427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2498467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2499467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 25008427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2501ff5350a8SAndy Lutomirski } 2502ff5350a8SAndy Lutomirski 2503ff5350a8SAndy Lutomirski return 0; 2504ff5350a8SAndy Lutomirski } 2505ff5350a8SAndy Lutomirski 250618119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 250718119775SKeith Busch { 250818119775SKeith Busch struct nvme_dev *dev = data; 250980f513b5SKeith Busch 251018119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 251118119775SKeith Busch flush_work(&dev->ctrl.scan_work); 251280f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 251318119775SKeith Busch } 251418119775SKeith Busch 251557dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 251657dacad5SJay Sternberg { 251757dacad5SJay Sternberg int node, result = -ENOMEM; 251857dacad5SJay Sternberg struct nvme_dev *dev; 2519ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 252057dacad5SJay Sternberg 252157dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 252257dacad5SJay Sternberg if (node == NUMA_NO_NODE) 25232fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 252457dacad5SJay Sternberg 252557dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 252657dacad5SJay Sternberg if (!dev) 252757dacad5SJay Sternberg return -ENOMEM; 2528147b27e4SSagi Grimberg 2529147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2530147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 253157dacad5SJay Sternberg if (!dev->queues) 253257dacad5SJay Sternberg goto free; 253357dacad5SJay Sternberg 253457dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 253557dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 253657dacad5SJay Sternberg 2537b00a726aSKeith Busch result = nvme_dev_map(dev); 2538b00a726aSKeith Busch if (result) 2539b00c9b7aSChristophe JAILLET goto put_pci; 2540b00a726aSKeith Busch 2541d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 25425c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 254377bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2544db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2545f3ca80fcSChristoph Hellwig 2546f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2547f3ca80fcSChristoph Hellwig if (result) 2548b00c9b7aSChristophe JAILLET goto unmap; 2549f3ca80fcSChristoph Hellwig 25508427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2551ff5350a8SAndy Lutomirski 2552f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2553ff5350a8SAndy Lutomirski quirks); 2554f3ca80fcSChristoph Hellwig if (result) 2555f3ca80fcSChristoph Hellwig goto release_pools; 2556f3ca80fcSChristoph Hellwig 25571b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25581b3c47c1SSagi Grimberg 255980f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 256018119775SKeith Busch async_schedule(nvme_async_probe, dev); 25614caff8fcSSagi Grimberg 256257dacad5SJay Sternberg return 0; 256357dacad5SJay Sternberg 256457dacad5SJay Sternberg release_pools: 256557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2566b00c9b7aSChristophe JAILLET unmap: 2567b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 256857dacad5SJay Sternberg put_pci: 256957dacad5SJay Sternberg put_device(dev->dev); 257057dacad5SJay Sternberg free: 257157dacad5SJay Sternberg kfree(dev->queues); 257257dacad5SJay Sternberg kfree(dev); 257357dacad5SJay Sternberg return result; 257457dacad5SJay Sternberg } 257557dacad5SJay Sternberg 2576775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 257757dacad5SJay Sternberg { 257857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2579a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2580775755edSChristoph Hellwig } 258157dacad5SJay Sternberg 2582775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2583775755edSChristoph Hellwig { 2584f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 258579c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 258657dacad5SJay Sternberg } 258757dacad5SJay Sternberg 258857dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 258957dacad5SJay Sternberg { 259057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2591a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 259257dacad5SJay Sternberg } 259357dacad5SJay Sternberg 2594f58944e2SKeith Busch /* 2595f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2596f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2597f58944e2SKeith Busch * order to proceed. 2598f58944e2SKeith Busch */ 259957dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 260057dacad5SJay Sternberg { 260157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 260257dacad5SJay Sternberg 2603bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2604bb8d261eSChristoph Hellwig 2605d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 260657dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 26070ff9d4e1SKeith Busch 26086db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 26090ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 26106db28edaSKeith Busch nvme_dev_disable(dev, false); 26116db28edaSKeith Busch } 26120ff9d4e1SKeith Busch 2613d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2614d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2615d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2616a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 261787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 261857dacad5SJay Sternberg nvme_dev_remove_admin(dev); 261957dacad5SJay Sternberg nvme_free_queues(dev, 0); 2620d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 262157dacad5SJay Sternberg nvme_release_prp_pools(dev); 2622b00a726aSKeith Busch nvme_dev_unmap(dev); 26231673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 262457dacad5SJay Sternberg } 262557dacad5SJay Sternberg 262613880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 262713880f5bSKeith Busch { 262813880f5bSKeith Busch int ret = 0; 262913880f5bSKeith Busch 263013880f5bSKeith Busch if (numvfs == 0) { 263113880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 263213880f5bSKeith Busch dev_warn(&pdev->dev, 263313880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 263413880f5bSKeith Busch return -EPERM; 263513880f5bSKeith Busch } 263613880f5bSKeith Busch pci_disable_sriov(pdev); 263713880f5bSKeith Busch return 0; 263813880f5bSKeith Busch } 263913880f5bSKeith Busch 264013880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 264113880f5bSKeith Busch return ret ? ret : numvfs; 264213880f5bSKeith Busch } 264313880f5bSKeith Busch 264457dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 264557dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 264657dacad5SJay Sternberg { 264757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 264857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 264957dacad5SJay Sternberg 2650a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 265157dacad5SJay Sternberg return 0; 265257dacad5SJay Sternberg } 265357dacad5SJay Sternberg 265457dacad5SJay Sternberg static int nvme_resume(struct device *dev) 265557dacad5SJay Sternberg { 265657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 265757dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 265857dacad5SJay Sternberg 2659d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 266057dacad5SJay Sternberg return 0; 266157dacad5SJay Sternberg } 266257dacad5SJay Sternberg #endif 266357dacad5SJay Sternberg 266457dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 266557dacad5SJay Sternberg 2666a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2667a0a3408eSKeith Busch pci_channel_state_t state) 2668a0a3408eSKeith Busch { 2669a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2670a0a3408eSKeith Busch 2671a0a3408eSKeith Busch /* 2672a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2673a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2674a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2675a0a3408eSKeith Busch */ 2676a0a3408eSKeith Busch switch (state) { 2677a0a3408eSKeith Busch case pci_channel_io_normal: 2678a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2679a0a3408eSKeith Busch case pci_channel_io_frozen: 2680d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2681d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2682a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2683a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2684a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2685d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2686d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2687a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2688a0a3408eSKeith Busch } 2689a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2690a0a3408eSKeith Busch } 2691a0a3408eSKeith Busch 2692a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2693a0a3408eSKeith Busch { 2694a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2695a0a3408eSKeith Busch 26961b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2697a0a3408eSKeith Busch pci_restore_state(pdev); 2698d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2699a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2700a0a3408eSKeith Busch } 2701a0a3408eSKeith Busch 2702a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2703a0a3408eSKeith Busch { 270472cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 270572cd4cc2SKeith Busch 270672cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2707a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2708a0a3408eSKeith Busch } 2709a0a3408eSKeith Busch 271057dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 271157dacad5SJay Sternberg .error_detected = nvme_error_detected, 271257dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 271357dacad5SJay Sternberg .resume = nvme_error_resume, 2714775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2715775755edSChristoph Hellwig .reset_done = nvme_reset_done, 271657dacad5SJay Sternberg }; 271757dacad5SJay Sternberg 271857dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2719106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 272008095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2721e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 272299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 272399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2724e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 272599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 272699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2727e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2728f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2729f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2730f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 273150af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 27329abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 27339abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2734540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2735540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 27360302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 27370302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 273854adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 273954adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 27408c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 27418c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2742015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2743015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2744d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2745d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2746d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2747d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2748608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2749608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2750608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2751608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2752ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2753ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 275457dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2755c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2756124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 275757dacad5SJay Sternberg { 0, } 275857dacad5SJay Sternberg }; 275957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 276057dacad5SJay Sternberg 276157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 276257dacad5SJay Sternberg .name = "nvme", 276357dacad5SJay Sternberg .id_table = nvme_id_table, 276457dacad5SJay Sternberg .probe = nvme_probe, 276557dacad5SJay Sternberg .remove = nvme_remove, 276657dacad5SJay Sternberg .shutdown = nvme_shutdown, 276757dacad5SJay Sternberg .driver = { 276857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 276957dacad5SJay Sternberg }, 277013880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 277157dacad5SJay Sternberg .err_handler = &nvme_err_handler, 277257dacad5SJay Sternberg }; 277357dacad5SJay Sternberg 277457dacad5SJay Sternberg static int __init nvme_init(void) 277557dacad5SJay Sternberg { 27769a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 277757dacad5SJay Sternberg } 277857dacad5SJay Sternberg 277957dacad5SJay Sternberg static void __exit nvme_exit(void) 278057dacad5SJay Sternberg { 278157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 278203e0f3a6SMing Lei flush_workqueue(nvme_wq); 278357dacad5SJay Sternberg _nvme_check_size(); 278457dacad5SJay Sternberg } 278557dacad5SJay Sternberg 278657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 278757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 278857dacad5SJay Sternberg MODULE_VERSION("1.0"); 278957dacad5SJay Sternberg module_init(nvme_init); 279057dacad5SJay Sternberg module_exit(nvme_exit); 2791