15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 21d916b1beSKeith Busch #include <linux/suspend.h> 2257dacad5SJay Sternberg #include <linux/t10-pi.h> 2357dacad5SJay Sternberg #include <linux/types.h> 249cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 25a98e58e5SScott Bauer #include <linux/sed-opal.h> 260f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2757dacad5SJay Sternberg 28604c01d5Syupeng #include "trace.h" 2957dacad5SJay Sternberg #include "nvme.h" 3057dacad5SJay Sternberg 3157dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3257dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3357dacad5SJay Sternberg 34a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35adf68f21SChristoph Hellwig 36943e942eSJens Axboe /* 37943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 38943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 39943e942eSJens Axboe */ 40943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 41943e942eSJens Axboe #define NVME_MAX_SEGS 127 42943e942eSJens Axboe 4357dacad5SJay Sternberg static int use_threaded_interrupts; 4457dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4557dacad5SJay Sternberg 4657dacad5SJay Sternberg static bool use_cmb_sqes = true; 4769f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4857dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4957dacad5SJay Sternberg 5087ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5187ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5287ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5387ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5457dacad5SJay Sternberg 55a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 56a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 57a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 58a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 59a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 60a7a7cbe3SChaitanya Kulkarni 61b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 63b27c1e68Sweiping zhang .set = io_queue_depth_set, 64b27c1e68Sweiping zhang .get = param_get_int, 65b27c1e68Sweiping zhang }; 66b27c1e68Sweiping zhang 67b27c1e68Sweiping zhang static int io_queue_depth = 1024; 68b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70b27c1e68Sweiping zhang 713b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 723b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 733b6592f7SJens Axboe .set = queue_count_set, 743b6592f7SJens Axboe .get = param_get_int, 753b6592f7SJens Axboe }; 763b6592f7SJens Axboe 773b6592f7SJens Axboe static int write_queues; 783b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 793b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 803b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 813b6592f7SJens Axboe "will share a queue set."); 823b6592f7SJens Axboe 83a4668d9bSJens Axboe static int poll_queues = 0; 844b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 854b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 864b04cc6aSJens Axboe 871c63dc66SChristoph Hellwig struct nvme_dev; 881c63dc66SChristoph Hellwig struct nvme_queue; 8957dacad5SJay Sternberg 90a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 918fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 9257dacad5SJay Sternberg 9357dacad5SJay Sternberg /* 941c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 951c63dc66SChristoph Hellwig */ 961c63dc66SChristoph Hellwig struct nvme_dev { 97147b27e4SSagi Grimberg struct nvme_queue *queues; 981c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 991c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1001c63dc66SChristoph Hellwig u32 __iomem *dbs; 1011c63dc66SChristoph Hellwig struct device *dev; 1021c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1031c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1041c63dc66SChristoph Hellwig unsigned online_queues; 1051c63dc66SChristoph Hellwig unsigned max_qid; 106e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10722b55601SKeith Busch unsigned int num_vecs; 1081c63dc66SChristoph Hellwig int q_depth; 1091c63dc66SChristoph Hellwig u32 db_stride; 1101c63dc66SChristoph Hellwig void __iomem *bar; 11197f6ef64SXu Yu unsigned long bar_mapped_size; 1125c8809e6SChristoph Hellwig struct work_struct remove_work; 11377bf25eaSKeith Busch struct mutex shutdown_lock; 1141c63dc66SChristoph Hellwig bool subsystem; 1151c63dc66SChristoph Hellwig u64 cmb_size; 1160f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1171c63dc66SChristoph Hellwig u32 cmbsz; 118202021c1SStephen Bates u32 cmbloc; 1191c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 120d916b1beSKeith Busch u32 last_ps; 12187ad72a5SChristoph Hellwig 122943e942eSJens Axboe mempool_t *iod_mempool; 123943e942eSJens Axboe 12487ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 125f9f38e33SHelen Koike u32 *dbbuf_dbs; 126f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 127f9f38e33SHelen Koike u32 *dbbuf_eis; 128f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12987ad72a5SChristoph Hellwig 13087ad72a5SChristoph Hellwig /* host memory buffer support: */ 13187ad72a5SChristoph Hellwig u64 host_mem_size; 13287ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1334033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13587ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13657dacad5SJay Sternberg }; 13757dacad5SJay Sternberg 138b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 139b27c1e68Sweiping zhang { 140b27c1e68Sweiping zhang int n = 0, ret; 141b27c1e68Sweiping zhang 142b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 143b27c1e68Sweiping zhang if (ret != 0 || n < 2) 144b27c1e68Sweiping zhang return -EINVAL; 145b27c1e68Sweiping zhang 146b27c1e68Sweiping zhang return param_set_int(val, kp); 147b27c1e68Sweiping zhang } 148b27c1e68Sweiping zhang 1493b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1503b6592f7SJens Axboe { 15166564867SMinwoo Im int n, ret; 1523b6592f7SJens Axboe 1533b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 154e895fedfSBart Van Assche if (ret) 155e895fedfSBart Van Assche return ret; 1563b6592f7SJens Axboe if (n > num_possible_cpus()) 1573b6592f7SJens Axboe n = num_possible_cpus(); 1583b6592f7SJens Axboe 1593b6592f7SJens Axboe return param_set_int(val, kp); 1603b6592f7SJens Axboe } 1613b6592f7SJens Axboe 162f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 163f9f38e33SHelen Koike { 164f9f38e33SHelen Koike return qid * 2 * stride; 165f9f38e33SHelen Koike } 166f9f38e33SHelen Koike 167f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 168f9f38e33SHelen Koike { 169f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 170f9f38e33SHelen Koike } 171f9f38e33SHelen Koike 1721c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1731c63dc66SChristoph Hellwig { 1741c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1751c63dc66SChristoph Hellwig } 1761c63dc66SChristoph Hellwig 17757dacad5SJay Sternberg /* 17857dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 17957dacad5SJay Sternberg * commands and one for I/O commands). 18057dacad5SJay Sternberg */ 18157dacad5SJay Sternberg struct nvme_queue { 18257dacad5SJay Sternberg struct nvme_dev *dev; 1831ab0cd69SJens Axboe spinlock_t sq_lock; 18457dacad5SJay Sternberg struct nvme_command *sq_cmds; 1853a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1863a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 18757dacad5SJay Sternberg volatile struct nvme_completion *cqes; 18857dacad5SJay Sternberg struct blk_mq_tags **tags; 18957dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19057dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19157dacad5SJay Sternberg u32 __iomem *q_db; 19257dacad5SJay Sternberg u16 q_depth; 1937c349ddeSKeith Busch u16 cq_vector; 19457dacad5SJay Sternberg u16 sq_tail; 19504f3eafdSJens Axboe u16 last_sq_tail; 19657dacad5SJay Sternberg u16 cq_head; 19768fa9dbeSJens Axboe u16 last_cq_head; 19857dacad5SJay Sternberg u16 qid; 19957dacad5SJay Sternberg u8 cq_phase; 2004e224106SChristoph Hellwig unsigned long flags; 2014e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20263223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 203d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2047c349ddeSKeith Busch #define NVMEQ_POLLED 3 205f9f38e33SHelen Koike u32 *dbbuf_sq_db; 206f9f38e33SHelen Koike u32 *dbbuf_cq_db; 207f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 208f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 209d1ed6aa1SChristoph Hellwig struct completion delete_done; 21057dacad5SJay Sternberg }; 21157dacad5SJay Sternberg 21257dacad5SJay Sternberg /* 2139b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2149b048119SChristoph Hellwig * 2159b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2169b048119SChristoph Hellwig * to the actual struct scatterlist. 21771bd150cSChristoph Hellwig */ 21871bd150cSChristoph Hellwig struct nvme_iod { 219d49187e9SChristoph Hellwig struct nvme_request req; 220f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 221a7a7cbe3SChaitanya Kulkarni bool use_sgl; 222f4800d6dSChristoph Hellwig int aborted; 22371bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22471bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22571bd150cSChristoph Hellwig dma_addr_t first_dma; 226dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 227783b94bdSChristoph Hellwig dma_addr_t meta_dma; 228f4800d6dSChristoph Hellwig struct scatterlist *sg; 22957dacad5SJay Sternberg }; 23057dacad5SJay Sternberg 2313b6592f7SJens Axboe static unsigned int max_io_queues(void) 2323b6592f7SJens Axboe { 2334b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2343b6592f7SJens Axboe } 2353b6592f7SJens Axboe 2363b6592f7SJens Axboe static unsigned int max_queue_count(void) 2373b6592f7SJens Axboe { 2383b6592f7SJens Axboe /* IO queues + admin queue */ 2393b6592f7SJens Axboe return 1 + max_io_queues(); 2403b6592f7SJens Axboe } 2413b6592f7SJens Axboe 242f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 243f9f38e33SHelen Koike { 2443b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 245f9f38e33SHelen Koike } 246f9f38e33SHelen Koike 247f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 248f9f38e33SHelen Koike { 249f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 250f9f38e33SHelen Koike 251f9f38e33SHelen Koike if (dev->dbbuf_dbs) 252f9f38e33SHelen Koike return 0; 253f9f38e33SHelen Koike 254f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 255f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 256f9f38e33SHelen Koike GFP_KERNEL); 257f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 258f9f38e33SHelen Koike return -ENOMEM; 259f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 261f9f38e33SHelen Koike GFP_KERNEL); 262f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 263f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 265f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 266f9f38e33SHelen Koike return -ENOMEM; 267f9f38e33SHelen Koike } 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike return 0; 270f9f38e33SHelen Koike } 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 273f9f38e33SHelen Koike { 274f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 275f9f38e33SHelen Koike 276f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 277f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 279f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 280f9f38e33SHelen Koike } 281f9f38e33SHelen Koike if (dev->dbbuf_eis) { 282f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 283f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 284f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 289f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 290f9f38e33SHelen Koike { 291f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 292f9f38e33SHelen Koike return; 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 295f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 296f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 297f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike 300f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 301f9f38e33SHelen Koike { 302f9f38e33SHelen Koike struct nvme_command c; 303f9f38e33SHelen Koike 304f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 305f9f38e33SHelen Koike return; 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 308f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 309f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 310f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3139bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 314f9f38e33SHelen Koike /* Free memory and continue on */ 315f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 316f9f38e33SHelen Koike } 317f9f38e33SHelen Koike } 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 320f9f38e33SHelen Koike { 321f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 322f9f38e33SHelen Koike } 323f9f38e33SHelen Koike 324f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 325f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 326f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 327f9f38e33SHelen Koike { 328f9f38e33SHelen Koike if (dbbuf_db) { 329f9f38e33SHelen Koike u16 old_value; 330f9f38e33SHelen Koike 331f9f38e33SHelen Koike /* 332f9f38e33SHelen Koike * Ensure that the queue is written before updating 333f9f38e33SHelen Koike * the doorbell in memory 334f9f38e33SHelen Koike */ 335f9f38e33SHelen Koike wmb(); 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike old_value = *dbbuf_db; 338f9f38e33SHelen Koike *dbbuf_db = value; 339f9f38e33SHelen Koike 340f1ed3df2SMichal Wnukowski /* 341f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 342f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 343f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 344f1ed3df2SMichal Wnukowski * the doorbell. 345f1ed3df2SMichal Wnukowski */ 346f1ed3df2SMichal Wnukowski mb(); 347f1ed3df2SMichal Wnukowski 348f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 349f9f38e33SHelen Koike return false; 350f9f38e33SHelen Koike } 351f9f38e33SHelen Koike 352f9f38e33SHelen Koike return true; 35357dacad5SJay Sternberg } 35457dacad5SJay Sternberg 35557dacad5SJay Sternberg /* 35657dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 35757dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 35857dacad5SJay Sternberg * the I/O. 35957dacad5SJay Sternberg */ 36057dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 36157dacad5SJay Sternberg { 3625fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3635fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 36457dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 36557dacad5SJay Sternberg } 36657dacad5SJay Sternberg 367a7a7cbe3SChaitanya Kulkarni /* 368a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 369a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 370a7a7cbe3SChaitanya Kulkarni */ 371a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 372f4800d6dSChristoph Hellwig { 373a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 374f4800d6dSChristoph Hellwig } 375f4800d6dSChristoph Hellwig 376a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 377a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 37857dacad5SJay Sternberg { 379a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 380a7a7cbe3SChaitanya Kulkarni 381a7a7cbe3SChaitanya Kulkarni if (use_sgl) 382a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 383a7a7cbe3SChaitanya Kulkarni else 384a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 385a7a7cbe3SChaitanya Kulkarni 386a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 387a7a7cbe3SChaitanya Kulkarni } 388a7a7cbe3SChaitanya Kulkarni 38957dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39057dacad5SJay Sternberg unsigned int hctx_idx) 39157dacad5SJay Sternberg { 39257dacad5SJay Sternberg struct nvme_dev *dev = data; 393147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 39457dacad5SJay Sternberg 39557dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 39657dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 39757dacad5SJay Sternberg WARN_ON(nvmeq->tags); 39857dacad5SJay Sternberg 39957dacad5SJay Sternberg hctx->driver_data = nvmeq; 40057dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 40157dacad5SJay Sternberg return 0; 40257dacad5SJay Sternberg } 40357dacad5SJay Sternberg 40457dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 40557dacad5SJay Sternberg { 40657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg nvmeq->tags = NULL; 40957dacad5SJay Sternberg } 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41257dacad5SJay Sternberg unsigned int hctx_idx) 41357dacad5SJay Sternberg { 41457dacad5SJay Sternberg struct nvme_dev *dev = data; 415147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg if (!nvmeq->tags) 41857dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 41957dacad5SJay Sternberg 42057dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 42157dacad5SJay Sternberg hctx->driver_data = nvmeq; 42257dacad5SJay Sternberg return 0; 42357dacad5SJay Sternberg } 42457dacad5SJay Sternberg 425d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 426d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42757dacad5SJay Sternberg { 428d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 429f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4300350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 431147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 43257dacad5SJay Sternberg 43357dacad5SJay Sternberg BUG_ON(!nvmeq); 434f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 43559e29ce6SSagi Grimberg 43659e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 43757dacad5SJay Sternberg return 0; 43857dacad5SJay Sternberg } 43957dacad5SJay Sternberg 4403b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4413b6592f7SJens Axboe { 4423b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4433b6592f7SJens Axboe if (dev->num_vecs > 1) 4443b6592f7SJens Axboe return 1; 4453b6592f7SJens Axboe 4463b6592f7SJens Axboe return 0; 4473b6592f7SJens Axboe } 4483b6592f7SJens Axboe 449dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 450dca51e78SChristoph Hellwig { 451dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4523b6592f7SJens Axboe int i, qoff, offset; 453dca51e78SChristoph Hellwig 4543b6592f7SJens Axboe offset = queue_irq_offset(dev); 4553b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4563b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4573b6592f7SJens Axboe 4583b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4593b6592f7SJens Axboe if (!map->nr_queues) { 460e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4617e849dd9SChristoph Hellwig continue; 4623b6592f7SJens Axboe } 4633b6592f7SJens Axboe 4644b04cc6aSJens Axboe /* 4654b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4664b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4674b04cc6aSJens Axboe */ 4683b6592f7SJens Axboe map->queue_offset = qoff; 469cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4703b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4714b04cc6aSJens Axboe else 4724b04cc6aSJens Axboe blk_mq_map_queues(map); 4733b6592f7SJens Axboe qoff += map->nr_queues; 4743b6592f7SJens Axboe offset += map->nr_queues; 4753b6592f7SJens Axboe } 4763b6592f7SJens Axboe 4773b6592f7SJens Axboe return 0; 478dca51e78SChristoph Hellwig } 479dca51e78SChristoph Hellwig 48004f3eafdSJens Axboe /* 48104f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 48204f3eafdSJens Axboe */ 48304f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 48404f3eafdSJens Axboe { 48504f3eafdSJens Axboe if (!write_sq) { 48604f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 48704f3eafdSJens Axboe 48804f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 48904f3eafdSJens Axboe next_tail = 0; 49004f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 49104f3eafdSJens Axboe return; 49204f3eafdSJens Axboe } 49304f3eafdSJens Axboe 49404f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 49504f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49604f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 49704f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 49804f3eafdSJens Axboe } 49904f3eafdSJens Axboe 50057dacad5SJay Sternberg /** 50190ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 50257dacad5SJay Sternberg * @nvmeq: The queue to use 50357dacad5SJay Sternberg * @cmd: The command to send 50404f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 50557dacad5SJay Sternberg */ 50604f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 50704f3eafdSJens Axboe bool write_sq) 50857dacad5SJay Sternberg { 50990ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 51090ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 51190ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 51290ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 51304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 51404f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 51504f3eafdSJens Axboe } 51604f3eafdSJens Axboe 51704f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51804f3eafdSJens Axboe { 51904f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 52004f3eafdSJens Axboe 52104f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 52204f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 52304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 52490ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52557dacad5SJay Sternberg } 52657dacad5SJay Sternberg 527a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52857dacad5SJay Sternberg { 529f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 530a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 53157dacad5SJay Sternberg } 53257dacad5SJay Sternberg 533955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 534955b1b5aSMinwoo Im { 535955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53620469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 537955b1b5aSMinwoo Im unsigned int avg_seg_size; 538955b1b5aSMinwoo Im 53920469a37SKeith Busch if (nseg == 0) 54020469a37SKeith Busch return false; 54120469a37SKeith Busch 54220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 543955b1b5aSMinwoo Im 544955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 545955b1b5aSMinwoo Im return false; 546955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 547955b1b5aSMinwoo Im return false; 548955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 549955b1b5aSMinwoo Im return false; 550955b1b5aSMinwoo Im return true; 551955b1b5aSMinwoo Im } 552955b1b5aSMinwoo Im 5537fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 55457dacad5SJay Sternberg { 555f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5567fe07d14SChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 5577fe07d14SChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 558a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 559a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 56057dacad5SJay Sternberg int i; 56157dacad5SJay Sternberg 562dff824b2SChristoph Hellwig if (iod->dma_len) { 563dff824b2SChristoph Hellwig dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); 564dff824b2SChristoph Hellwig return; 565dff824b2SChristoph Hellwig } 566dff824b2SChristoph Hellwig 567dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 568dff824b2SChristoph Hellwig 5697fe07d14SChristoph Hellwig /* P2PDMA requests do not need to be unmapped */ 5707fe07d14SChristoph Hellwig if (!is_pci_p2pdma_page(sg_page(iod->sg))) 571dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5727fe07d14SChristoph Hellwig 5737fe07d14SChristoph Hellwig 57457dacad5SJay Sternberg if (iod->npages == 0) 575a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 576a7a7cbe3SChaitanya Kulkarni dma_addr); 577a7a7cbe3SChaitanya Kulkarni 57857dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 579a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 580a7a7cbe3SChaitanya Kulkarni 581a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 582a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 583a7a7cbe3SChaitanya Kulkarni 584a7a7cbe3SChaitanya Kulkarni next_dma_addr = 585a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 586a7a7cbe3SChaitanya Kulkarni } else { 587a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 588a7a7cbe3SChaitanya Kulkarni 589a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 590a7a7cbe3SChaitanya Kulkarni } 591a7a7cbe3SChaitanya Kulkarni 592a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 593a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 59457dacad5SJay Sternberg } 59557dacad5SJay Sternberg 596943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 59757dacad5SJay Sternberg } 59857dacad5SJay Sternberg 599d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 600d0877473SKeith Busch { 601d0877473SKeith Busch int i; 602d0877473SKeith Busch struct scatterlist *sg; 603d0877473SKeith Busch 604d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 605d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 606d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 607d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 608d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 609d0877473SKeith Busch sg_dma_len(sg)); 610d0877473SKeith Busch } 611d0877473SKeith Busch } 612d0877473SKeith Busch 613a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 614a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 61557dacad5SJay Sternberg { 616f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 61757dacad5SJay Sternberg struct dma_pool *pool; 618b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61957dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 62057dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 62157dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6225fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 62357dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 62457dacad5SJay Sternberg __le64 *prp_list; 625a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 62657dacad5SJay Sternberg dma_addr_t prp_dma; 62757dacad5SJay Sternberg int nprps, i; 62857dacad5SJay Sternberg 62957dacad5SJay Sternberg length -= (page_size - offset); 6305228b328SJan H. Schönherr if (length <= 0) { 6315228b328SJan H. Schönherr iod->first_dma = 0; 632a7a7cbe3SChaitanya Kulkarni goto done; 6335228b328SJan H. Schönherr } 63457dacad5SJay Sternberg 63557dacad5SJay Sternberg dma_len -= (page_size - offset); 63657dacad5SJay Sternberg if (dma_len) { 63757dacad5SJay Sternberg dma_addr += (page_size - offset); 63857dacad5SJay Sternberg } else { 63957dacad5SJay Sternberg sg = sg_next(sg); 64057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 64257dacad5SJay Sternberg } 64357dacad5SJay Sternberg 64457dacad5SJay Sternberg if (length <= page_size) { 64557dacad5SJay Sternberg iod->first_dma = dma_addr; 646a7a7cbe3SChaitanya Kulkarni goto done; 64757dacad5SJay Sternberg } 64857dacad5SJay Sternberg 64957dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 65057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 65157dacad5SJay Sternberg pool = dev->prp_small_pool; 65257dacad5SJay Sternberg iod->npages = 0; 65357dacad5SJay Sternberg } else { 65457dacad5SJay Sternberg pool = dev->prp_page_pool; 65557dacad5SJay Sternberg iod->npages = 1; 65657dacad5SJay Sternberg } 65757dacad5SJay Sternberg 65869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65957dacad5SJay Sternberg if (!prp_list) { 66057dacad5SJay Sternberg iod->first_dma = dma_addr; 66157dacad5SJay Sternberg iod->npages = -1; 66286eea289SKeith Busch return BLK_STS_RESOURCE; 66357dacad5SJay Sternberg } 66457dacad5SJay Sternberg list[0] = prp_list; 66557dacad5SJay Sternberg iod->first_dma = prp_dma; 66657dacad5SJay Sternberg i = 0; 66757dacad5SJay Sternberg for (;;) { 66857dacad5SJay Sternberg if (i == page_size >> 3) { 66957dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67157dacad5SJay Sternberg if (!prp_list) 67286eea289SKeith Busch return BLK_STS_RESOURCE; 67357dacad5SJay Sternberg list[iod->npages++] = prp_list; 67457dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 67557dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 67657dacad5SJay Sternberg i = 1; 67757dacad5SJay Sternberg } 67857dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 67957dacad5SJay Sternberg dma_len -= page_size; 68057dacad5SJay Sternberg dma_addr += page_size; 68157dacad5SJay Sternberg length -= page_size; 68257dacad5SJay Sternberg if (length <= 0) 68357dacad5SJay Sternberg break; 68457dacad5SJay Sternberg if (dma_len > 0) 68557dacad5SJay Sternberg continue; 68686eea289SKeith Busch if (unlikely(dma_len < 0)) 68786eea289SKeith Busch goto bad_sgl; 68857dacad5SJay Sternberg sg = sg_next(sg); 68957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69157dacad5SJay Sternberg } 69257dacad5SJay Sternberg 693a7a7cbe3SChaitanya Kulkarni done: 694a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 695a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 696a7a7cbe3SChaitanya Kulkarni 69786eea289SKeith Busch return BLK_STS_OK; 69886eea289SKeith Busch 69986eea289SKeith Busch bad_sgl: 700d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 701d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 702d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 70386eea289SKeith Busch return BLK_STS_IOERR; 70457dacad5SJay Sternberg } 70557dacad5SJay Sternberg 706a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 707a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 708a7a7cbe3SChaitanya Kulkarni { 709a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 710a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 711a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 712a7a7cbe3SChaitanya Kulkarni } 713a7a7cbe3SChaitanya Kulkarni 714a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 715a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 716a7a7cbe3SChaitanya Kulkarni { 717a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 718a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 719a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 720a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 721a7a7cbe3SChaitanya Kulkarni } else { 722a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 723a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 724a7a7cbe3SChaitanya Kulkarni } 725a7a7cbe3SChaitanya Kulkarni } 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 728b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 729a7a7cbe3SChaitanya Kulkarni { 730a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 731a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 732a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 733a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 734a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 735b0f2853bSChristoph Hellwig int i = 0; 736a7a7cbe3SChaitanya Kulkarni 737a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 738a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 739a7a7cbe3SChaitanya Kulkarni 740b0f2853bSChristoph Hellwig if (entries == 1) { 741a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 742a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 743a7a7cbe3SChaitanya Kulkarni } 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 746a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 747a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 748a7a7cbe3SChaitanya Kulkarni } else { 749a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 750a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 751a7a7cbe3SChaitanya Kulkarni } 752a7a7cbe3SChaitanya Kulkarni 753a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 754a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 755a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 756a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 757a7a7cbe3SChaitanya Kulkarni } 758a7a7cbe3SChaitanya Kulkarni 759a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 760a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni do { 765a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 766a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 767a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 768a7a7cbe3SChaitanya Kulkarni 769a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 770a7a7cbe3SChaitanya Kulkarni if (!sg_list) 771a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni i = 0; 774a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 775a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 776a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 780a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 781b0f2853bSChristoph Hellwig } while (--entries > 0); 782a7a7cbe3SChaitanya Kulkarni 783a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 784a7a7cbe3SChaitanya Kulkarni } 785a7a7cbe3SChaitanya Kulkarni 786dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 787dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 788dff824b2SChristoph Hellwig struct bio_vec *bv) 789dff824b2SChristoph Hellwig { 790dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 791dff824b2SChristoph Hellwig unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 792dff824b2SChristoph Hellwig 793dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 794dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 795dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 796dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 797dff824b2SChristoph Hellwig 798dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 799dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 800dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 801dff824b2SChristoph Hellwig return 0; 802dff824b2SChristoph Hellwig } 803dff824b2SChristoph Hellwig 80429791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 80529791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 80629791057SChristoph Hellwig struct bio_vec *bv) 80729791057SChristoph Hellwig { 80829791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80929791057SChristoph Hellwig 81029791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 81129791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 81229791057SChristoph Hellwig return BLK_STS_RESOURCE; 81329791057SChristoph Hellwig iod->dma_len = bv->bv_len; 81429791057SChristoph Hellwig 815049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 81629791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 81729791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 81829791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 81929791057SChristoph Hellwig return 0; 82029791057SChristoph Hellwig } 82129791057SChristoph Hellwig 822fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 823b131c61dSChristoph Hellwig struct nvme_command *cmnd) 82457dacad5SJay Sternberg { 825f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82670479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 827b0f2853bSChristoph Hellwig int nr_mapped; 82857dacad5SJay Sternberg 829dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 830dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 831dff824b2SChristoph Hellwig 832dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 833dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 834dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 835dff824b2SChristoph Hellwig &cmnd->rw, &bv); 83629791057SChristoph Hellwig 83729791057SChristoph Hellwig if (iod->nvmeq->qid && 83829791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 83929791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 84029791057SChristoph Hellwig &cmnd->rw, &bv); 841dff824b2SChristoph Hellwig } 842dff824b2SChristoph Hellwig } 843dff824b2SChristoph Hellwig 844dff824b2SChristoph Hellwig iod->dma_len = 0; 8459b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8469b048119SChristoph Hellwig if (!iod->sg) 8479b048119SChristoph Hellwig return BLK_STS_RESOURCE; 848f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 84970479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 850ba1ca37eSChristoph Hellwig if (!iod->nents) 851ba1ca37eSChristoph Hellwig goto out; 852ba1ca37eSChristoph Hellwig 853e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 854e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 85570479b71SChristoph Hellwig rq_dma_dir(req)); 856e0596ab2SLogan Gunthorpe else 857e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 85870479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 859b0f2853bSChristoph Hellwig if (!nr_mapped) 860ba1ca37eSChristoph Hellwig goto out; 861ba1ca37eSChristoph Hellwig 86270479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 863955b1b5aSMinwoo Im if (iod->use_sgl) 864b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 865a7a7cbe3SChaitanya Kulkarni else 866a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 867ba1ca37eSChristoph Hellwig out: 8684aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8697fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 870ba1ca37eSChristoph Hellwig return ret; 87157dacad5SJay Sternberg } 87257dacad5SJay Sternberg 8734aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8744aedb705SChristoph Hellwig struct nvme_command *cmnd) 8754aedb705SChristoph Hellwig { 8764aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8774aedb705SChristoph Hellwig 8784aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8794aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8804aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8814aedb705SChristoph Hellwig return BLK_STS_IOERR; 8824aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 8834aedb705SChristoph Hellwig return 0; 8844aedb705SChristoph Hellwig } 8854aedb705SChristoph Hellwig 88657dacad5SJay Sternberg /* 88757dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 88857dacad5SJay Sternberg */ 889fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 89057dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 89157dacad5SJay Sternberg { 89257dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 89357dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 89457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 89557dacad5SJay Sternberg struct request *req = bd->rq; 8969b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 897ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 898ebe6d874SChristoph Hellwig blk_status_t ret; 89957dacad5SJay Sternberg 9009b048119SChristoph Hellwig iod->aborted = 0; 9019b048119SChristoph Hellwig iod->npages = -1; 9029b048119SChristoph Hellwig iod->nents = 0; 9039b048119SChristoph Hellwig 904d1f06f4aSJens Axboe /* 905d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 906d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 907d1f06f4aSJens Axboe */ 9084e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 909d1f06f4aSJens Axboe return BLK_STS_IOERR; 910d1f06f4aSJens Axboe 911f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 912fc17b653SChristoph Hellwig if (ret) 913f4800d6dSChristoph Hellwig return ret; 91457dacad5SJay Sternberg 915fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 916b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 917fc17b653SChristoph Hellwig if (ret) 9189b048119SChristoph Hellwig goto out_free_cmd; 919fc17b653SChristoph Hellwig } 920ba1ca37eSChristoph Hellwig 9214aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9224aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9234aedb705SChristoph Hellwig if (ret) 9244aedb705SChristoph Hellwig goto out_unmap_data; 9254aedb705SChristoph Hellwig } 9264aedb705SChristoph Hellwig 927aae239e1SChristoph Hellwig blk_mq_start_request(req); 92804f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 929fc17b653SChristoph Hellwig return BLK_STS_OK; 9304aedb705SChristoph Hellwig out_unmap_data: 9314aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 932f9d03f96SChristoph Hellwig out_free_cmd: 933f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 934ba1ca37eSChristoph Hellwig return ret; 93557dacad5SJay Sternberg } 93657dacad5SJay Sternberg 93777f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 938eee417b0SChristoph Hellwig { 939f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9404aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 941eee417b0SChristoph Hellwig 942915f04c9SChristoph Hellwig nvme_cleanup_cmd(req); 9434aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9444aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9454aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 946b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9474aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 94877f02a7aSChristoph Hellwig nvme_complete_rq(req); 94957dacad5SJay Sternberg } 95057dacad5SJay Sternberg 951d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 952750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 953d783e0bdSMarta Rybczynska { 954750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 955750dde44SChristoph Hellwig nvmeq->cq_phase; 956d783e0bdSMarta Rybczynska } 957d783e0bdSMarta Rybczynska 958eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 95957dacad5SJay Sternberg { 960eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 96157dacad5SJay Sternberg 962eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 963eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 964eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 965eb281c82SSagi Grimberg } 966adf68f21SChristoph Hellwig 9675cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 96857dacad5SJay Sternberg { 9695cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 97057dacad5SJay Sternberg struct request *req; 971adf68f21SChristoph Hellwig 97283a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9731b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 974aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 97583a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 97683a12fb7SSagi Grimberg return; 977aae239e1SChristoph Hellwig } 978aae239e1SChristoph Hellwig 979adf68f21SChristoph Hellwig /* 980adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 981adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 982adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 983adf68f21SChristoph Hellwig * for them but rather special case them here. 984adf68f21SChristoph Hellwig */ 985adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 98638dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9877bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 98883a12fb7SSagi Grimberg cqe->status, &cqe->result); 989a0fa9647SJens Axboe return; 99057dacad5SJay Sternberg } 99157dacad5SJay Sternberg 99283a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 993604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 99483a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 99583a12fb7SSagi Grimberg } 99657dacad5SJay Sternberg 9975cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 99883a12fb7SSagi Grimberg { 9995cb525c8SJens Axboe while (start != end) { 10005cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10015cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10025cb525c8SJens Axboe start = 0; 10035cb525c8SJens Axboe } 10045cb525c8SJens Axboe } 100583a12fb7SSagi Grimberg 10065cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10075cb525c8SJens Axboe { 1008dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1009920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1010920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1011dcca1662SHongbo Yao } else { 1012dcca1662SHongbo Yao nvmeq->cq_head++; 1013920d13a8SSagi Grimberg } 1014a0fa9647SJens Axboe } 1015a0fa9647SJens Axboe 10161052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10171052b8acSJens Axboe u16 *end, unsigned int tag) 1018a0fa9647SJens Axboe { 10191052b8acSJens Axboe int found = 0; 102083a12fb7SSagi Grimberg 10215cb525c8SJens Axboe *start = nvmeq->cq_head; 10221052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10231052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10241052b8acSJens Axboe found++; 10255cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 102657dacad5SJay Sternberg } 10275cb525c8SJens Axboe *end = nvmeq->cq_head; 102857dacad5SJay Sternberg 10295cb525c8SJens Axboe if (*start != *end) 1030eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10315cb525c8SJens Axboe return found; 103257dacad5SJay Sternberg } 103357dacad5SJay Sternberg 103457dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 103557dacad5SJay Sternberg { 103657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 103768fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10385cb525c8SJens Axboe u16 start, end; 10395cb525c8SJens Axboe 10403a7afd8eSChristoph Hellwig /* 10413a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10423a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10433a7afd8eSChristoph Hellwig */ 10443a7afd8eSChristoph Hellwig rmb(); 104568fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 104668fa9dbeSJens Axboe ret = IRQ_HANDLED; 10475cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 104868fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10493a7afd8eSChristoph Hellwig wmb(); 10505cb525c8SJens Axboe 105168fa9dbeSJens Axboe if (start != end) { 10525cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10535cb525c8SJens Axboe return IRQ_HANDLED; 105457dacad5SJay Sternberg } 105557dacad5SJay Sternberg 105668fa9dbeSJens Axboe return ret; 105757dacad5SJay Sternberg } 105857dacad5SJay Sternberg 105957dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 106057dacad5SJay Sternberg { 106157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1062750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 106357dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1064d783e0bdSMarta Rybczynska return IRQ_NONE; 106557dacad5SJay Sternberg } 106657dacad5SJay Sternberg 10670b2a8a9fSChristoph Hellwig /* 10680b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10690b2a8a9fSChristoph Hellwig * Can be called from any context. 10700b2a8a9fSChristoph Hellwig */ 10710b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1072a0fa9647SJens Axboe { 10733a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10745cb525c8SJens Axboe u16 start, end; 10751052b8acSJens Axboe int found; 1076a0fa9647SJens Axboe 10773a7afd8eSChristoph Hellwig /* 10783a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10793a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10803a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10813a7afd8eSChristoph Hellwig */ 10827c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10833a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 108491a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 108591a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 108691a509f8SChristoph Hellwig } else { 10873a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10885cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10893a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 109091a509f8SChristoph Hellwig } 1091442e19b7SSagi Grimberg 10925cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1093442e19b7SSagi Grimberg return found; 1094a0fa9647SJens Axboe } 1095a0fa9647SJens Axboe 10969743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10977776db1cSKeith Busch { 10987776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1099dabcefabSJens Axboe u16 start, end; 1100dabcefabSJens Axboe bool found; 1101dabcefabSJens Axboe 1102dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1103dabcefabSJens Axboe return 0; 1104dabcefabSJens Axboe 11053a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11069743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11073a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1108dabcefabSJens Axboe 1109dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1110dabcefabSJens Axboe return found; 1111dabcefabSJens Axboe } 1112dabcefabSJens Axboe 1113ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 111457dacad5SJay Sternberg { 1115f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1116147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 111757dacad5SJay Sternberg struct nvme_command c; 111857dacad5SJay Sternberg 111957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112057dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1121ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 112204f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 112357dacad5SJay Sternberg } 112457dacad5SJay Sternberg 112557dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 112657dacad5SJay Sternberg { 112757dacad5SJay Sternberg struct nvme_command c; 112857dacad5SJay Sternberg 112957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113057dacad5SJay Sternberg c.delete_queue.opcode = opcode; 113157dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 113257dacad5SJay Sternberg 11331c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113457dacad5SJay Sternberg } 113557dacad5SJay Sternberg 113657dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1137a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 113857dacad5SJay Sternberg { 113957dacad5SJay Sternberg struct nvme_command c; 11404b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11414b04cc6aSJens Axboe 11427c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11434b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 114457dacad5SJay Sternberg 114557dacad5SJay Sternberg /* 114616772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 114757dacad5SJay Sternberg * is attached to the request. 114857dacad5SJay Sternberg */ 114957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115057dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 115157dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 115257dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 115357dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 115457dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1155a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 115657dacad5SJay Sternberg 11571c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115857dacad5SJay Sternberg } 115957dacad5SJay Sternberg 116057dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 116157dacad5SJay Sternberg struct nvme_queue *nvmeq) 116257dacad5SJay Sternberg { 11639abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 116457dacad5SJay Sternberg struct nvme_command c; 116581c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 116657dacad5SJay Sternberg 116757dacad5SJay Sternberg /* 11689abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11699abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11709abd68efSJens Axboe * URGENT. 11719abd68efSJens Axboe */ 11729abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11739abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11749abd68efSJens Axboe 11759abd68efSJens Axboe /* 117616772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117757dacad5SJay Sternberg * is attached to the request. 117857dacad5SJay Sternberg */ 117957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 118057dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 118157dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 118257dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 118357dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 118457dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 118557dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 118657dacad5SJay Sternberg 11871c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 118857dacad5SJay Sternberg } 118957dacad5SJay Sternberg 119057dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 119157dacad5SJay Sternberg { 119257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 119357dacad5SJay Sternberg } 119457dacad5SJay Sternberg 119557dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 119657dacad5SJay Sternberg { 119757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 119857dacad5SJay Sternberg } 119957dacad5SJay Sternberg 12002a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 120157dacad5SJay Sternberg { 1202f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1203f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 120457dacad5SJay Sternberg 120527fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 120627fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1207e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1208e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 120957dacad5SJay Sternberg } 121057dacad5SJay Sternberg 1211b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1212b2a0eb1aSKeith Busch { 1213b2a0eb1aSKeith Busch 1214b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1215b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1216b2a0eb1aSKeith Busch */ 1217b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1218b2a0eb1aSKeith Busch 1219ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1220ad70062cSJianchao Wang switch (dev->ctrl.state) { 1221ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1222ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1223b2a0eb1aSKeith Busch return false; 1224ad70062cSJianchao Wang default: 1225ad70062cSJianchao Wang break; 1226ad70062cSJianchao Wang } 1227b2a0eb1aSKeith Busch 1228b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1229b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1230b2a0eb1aSKeith Busch */ 1231b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1232b2a0eb1aSKeith Busch return false; 1233b2a0eb1aSKeith Busch 1234b2a0eb1aSKeith Busch return true; 1235b2a0eb1aSKeith Busch } 1236b2a0eb1aSKeith Busch 1237b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1238b2a0eb1aSKeith Busch { 1239b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1240b2a0eb1aSKeith Busch u16 pci_status; 1241b2a0eb1aSKeith Busch int result; 1242b2a0eb1aSKeith Busch 1243b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1244b2a0eb1aSKeith Busch &pci_status); 1245b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1246b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1247b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1248b2a0eb1aSKeith Busch csts, pci_status); 1249b2a0eb1aSKeith Busch else 1250b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1251b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1252b2a0eb1aSKeith Busch csts, result); 1253b2a0eb1aSKeith Busch } 1254b2a0eb1aSKeith Busch 125531c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 125657dacad5SJay Sternberg { 1257f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1258f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 125957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 126057dacad5SJay Sternberg struct request *abort_req; 126157dacad5SJay Sternberg struct nvme_command cmd; 1262b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1263b2a0eb1aSKeith Busch 1264651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1265651438bbSWen Xiong * the recovery mechanism will surely fail. 1266651438bbSWen Xiong */ 1267651438bbSWen Xiong mb(); 1268651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1269651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1270651438bbSWen Xiong 1271b2a0eb1aSKeith Busch /* 1272b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1273b2a0eb1aSKeith Busch */ 1274b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1275b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1276b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1277d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1278db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1279b2a0eb1aSKeith Busch } 128057dacad5SJay Sternberg 128131c7c7d2SChristoph Hellwig /* 12827776db1cSKeith Busch * Did we miss an interrupt? 12837776db1cSKeith Busch */ 12840b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12857776db1cSKeith Busch dev_warn(dev->ctrl.device, 12867776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12877776db1cSKeith Busch req->tag, nvmeq->qid); 1288db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12897776db1cSKeith Busch } 12907776db1cSKeith Busch 12917776db1cSKeith Busch /* 1292fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1293fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1294fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1295db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1296fd634f41SChristoph Hellwig */ 12974244140dSKeith Busch switch (dev->ctrl.state) { 12984244140dSKeith Busch case NVME_CTRL_CONNECTING: 12992036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 13002036f726SKeith Busch /* fall through */ 13012036f726SKeith Busch case NVME_CTRL_DELETING: 1302b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1303fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1304fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 13052036f726SKeith Busch nvme_dev_disable(dev, true); 130627fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1307db8c48e4SChristoph Hellwig return BLK_EH_DONE; 130839a9dd81SKeith Busch case NVME_CTRL_RESETTING: 130939a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13104244140dSKeith Busch default: 13114244140dSKeith Busch break; 1312fd634f41SChristoph Hellwig } 1313fd634f41SChristoph Hellwig 1314fd634f41SChristoph Hellwig /* 1315e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1316e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1317e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 131831c7c7d2SChristoph Hellwig */ 1319f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13201b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 132157dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 132257dacad5SJay Sternberg req->tag, nvmeq->qid); 1323a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1324d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1325e1569a16SKeith Busch 132627fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1327db8c48e4SChristoph Hellwig return BLK_EH_DONE; 132857dacad5SJay Sternberg } 132957dacad5SJay Sternberg 1330e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1331e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1332e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1333e7a2a87dSChristoph Hellwig } 13347bf7d778SKeith Busch iod->aborted = 1; 133557dacad5SJay Sternberg 133657dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 133757dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 133857dacad5SJay Sternberg cmd.abort.cid = req->tag; 133957dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 134057dacad5SJay Sternberg 13411b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13421b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 134357dacad5SJay Sternberg req->tag, nvmeq->qid); 1344e7a2a87dSChristoph Hellwig 1345e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1346eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13476bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13486bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 134931c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 135057dacad5SJay Sternberg } 135157dacad5SJay Sternberg 1352e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1353e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1354e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg /* 135757dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 135857dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 135957dacad5SJay Sternberg * as the device then is in a faulty state. 136057dacad5SJay Sternberg */ 136157dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 136257dacad5SJay Sternberg } 136357dacad5SJay Sternberg 136457dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 136557dacad5SJay Sternberg { 136688a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 136757dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 136863223078SChristoph Hellwig if (!nvmeq->sq_cmds) 136963223078SChristoph Hellwig return; 13700f238ff5SLogan Gunthorpe 137163223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 137288a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 137363223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 137463223078SChristoph Hellwig } else { 137588a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 137663223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13770f238ff5SLogan Gunthorpe } 137857dacad5SJay Sternberg } 137957dacad5SJay Sternberg 138057dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 138157dacad5SJay Sternberg { 138257dacad5SJay Sternberg int i; 138357dacad5SJay Sternberg 1384d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1385d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1386147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 138757dacad5SJay Sternberg } 138857dacad5SJay Sternberg } 138957dacad5SJay Sternberg 139057dacad5SJay Sternberg /** 139157dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 139240581d1aSBart Van Assche * @nvmeq: queue to suspend 139357dacad5SJay Sternberg */ 139457dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 139557dacad5SJay Sternberg { 13964e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 139757dacad5SJay Sternberg return 1; 139857dacad5SJay Sternberg 13994e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1400d1f06f4aSJens Axboe mb(); 140157dacad5SJay Sternberg 14024e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14031c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1404c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14057c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14064e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 140757dacad5SJay Sternberg return 0; 140857dacad5SJay Sternberg } 140957dacad5SJay Sternberg 14108fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14118fae268bSKeith Busch { 14128fae268bSKeith Busch int i; 14138fae268bSKeith Busch 14148fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14158fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14168fae268bSKeith Busch } 14178fae268bSKeith Busch 1418a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 141957dacad5SJay Sternberg { 1420147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 142157dacad5SJay Sternberg 1422a5cdb68cSKeith Busch if (shutdown) 1423a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1424a5cdb68cSKeith Busch else 142520d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 142657dacad5SJay Sternberg 14270b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 142857dacad5SJay Sternberg } 142957dacad5SJay Sternberg 143057dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 143157dacad5SJay Sternberg int entry_size) 143257dacad5SJay Sternberg { 143357dacad5SJay Sternberg int q_depth = dev->q_depth; 14345fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14355fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 143657dacad5SJay Sternberg 143757dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 143857dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14395fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 144057dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 144157dacad5SJay Sternberg 144257dacad5SJay Sternberg /* 144357dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 144457dacad5SJay Sternberg * would be better to map queues in system memory with the 144557dacad5SJay Sternberg * original depth 144657dacad5SJay Sternberg */ 144757dacad5SJay Sternberg if (q_depth < 64) 144857dacad5SJay Sternberg return -ENOMEM; 144957dacad5SJay Sternberg } 145057dacad5SJay Sternberg 145157dacad5SJay Sternberg return q_depth; 145257dacad5SJay Sternberg } 145357dacad5SJay Sternberg 145457dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 145557dacad5SJay Sternberg int qid, int depth) 145657dacad5SJay Sternberg { 14570f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1458815c6704SKeith Busch 14590f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14600f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14610f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14620f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 146363223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 146463223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 146563223078SChristoph Hellwig return 0; 146663223078SChristoph Hellwig } 14670f238ff5SLogan Gunthorpe } 14680f238ff5SLogan Gunthorpe 146957dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 147057dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 147157dacad5SJay Sternberg if (!nvmeq->sq_cmds) 147257dacad5SJay Sternberg return -ENOMEM; 147357dacad5SJay Sternberg return 0; 147457dacad5SJay Sternberg } 147557dacad5SJay Sternberg 1476a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 147757dacad5SJay Sternberg { 1478147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 147957dacad5SJay Sternberg 148062314e40SKeith Busch if (dev->ctrl.queue_count > qid) 148162314e40SKeith Busch return 0; 148257dacad5SJay Sternberg 1483750afb08SLuis Chamberlain nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 148457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 148557dacad5SJay Sternberg if (!nvmeq->cqes) 148657dacad5SJay Sternberg goto free_nvmeq; 148757dacad5SJay Sternberg 148857dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 148957dacad5SJay Sternberg goto free_cqdma; 149057dacad5SJay Sternberg 149157dacad5SJay Sternberg nvmeq->dev = dev; 14921ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14933a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 149457dacad5SJay Sternberg nvmeq->cq_head = 0; 149557dacad5SJay Sternberg nvmeq->cq_phase = 1; 149657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 149757dacad5SJay Sternberg nvmeq->q_depth = depth; 149857dacad5SJay Sternberg nvmeq->qid = qid; 1499d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 150057dacad5SJay Sternberg 1501147b27e4SSagi Grimberg return 0; 150257dacad5SJay Sternberg 150357dacad5SJay Sternberg free_cqdma: 150457dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 150557dacad5SJay Sternberg nvmeq->cq_dma_addr); 150657dacad5SJay Sternberg free_nvmeq: 1507147b27e4SSagi Grimberg return -ENOMEM; 150857dacad5SJay Sternberg } 150957dacad5SJay Sternberg 1510dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 151157dacad5SJay Sternberg { 15120ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15130ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15140ff199cbSChristoph Hellwig 15150ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15160ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15170ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15180ff199cbSChristoph Hellwig } else { 15190ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15200ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15210ff199cbSChristoph Hellwig } 152257dacad5SJay Sternberg } 152357dacad5SJay Sternberg 152457dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 152557dacad5SJay Sternberg { 152657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152757dacad5SJay Sternberg 152857dacad5SJay Sternberg nvmeq->sq_tail = 0; 152904f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 153057dacad5SJay Sternberg nvmeq->cq_head = 0; 153157dacad5SJay Sternberg nvmeq->cq_phase = 1; 153257dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 153357dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1534f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 153557dacad5SJay Sternberg dev->online_queues++; 15363a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 153757dacad5SJay Sternberg } 153857dacad5SJay Sternberg 15394b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 154057dacad5SJay Sternberg { 154157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154257dacad5SJay Sternberg int result; 15437c349ddeSKeith Busch u16 vector = 0; 154457dacad5SJay Sternberg 1545d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1546d1ed6aa1SChristoph Hellwig 154722b55601SKeith Busch /* 154822b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 154922b55601SKeith Busch * has only one vector available. 155022b55601SKeith Busch */ 15514b04cc6aSJens Axboe if (!polled) 1552a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15534b04cc6aSJens Axboe else 15547c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15554b04cc6aSJens Axboe 1556a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1557ded45505SKeith Busch if (result) 1558ded45505SKeith Busch return result; 155957dacad5SJay Sternberg 156057dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 156157dacad5SJay Sternberg if (result < 0) 1562ded45505SKeith Busch return result; 1563ded45505SKeith Busch else if (result) 156457dacad5SJay Sternberg goto release_cq; 156557dacad5SJay Sternberg 1566a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1567161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15684b04cc6aSJens Axboe 15697c349ddeSKeith Busch if (!polled) { 15707c349ddeSKeith Busch nvmeq->cq_vector = vector; 1571dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 157257dacad5SJay Sternberg if (result < 0) 157357dacad5SJay Sternberg goto release_sq; 15744b04cc6aSJens Axboe } 157557dacad5SJay Sternberg 15764e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 157757dacad5SJay Sternberg return result; 157857dacad5SJay Sternberg 157957dacad5SJay Sternberg release_sq: 1580f25a2dfcSJianchao Wang dev->online_queues--; 158157dacad5SJay Sternberg adapter_delete_sq(dev, qid); 158257dacad5SJay Sternberg release_cq: 158357dacad5SJay Sternberg adapter_delete_cq(dev, qid); 158457dacad5SJay Sternberg return result; 158557dacad5SJay Sternberg } 158657dacad5SJay Sternberg 1587f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 158857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 159057dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 159157dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15920350815aSChristoph Hellwig .init_request = nvme_init_request, 159357dacad5SJay Sternberg .timeout = nvme_timeout, 159457dacad5SJay Sternberg }; 159557dacad5SJay Sternberg 1596f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1597376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1598376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1599376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1600376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1601376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1602376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1603376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1604c6d962aeSChristoph Hellwig .poll = nvme_poll, 1605dabcefabSJens Axboe }; 1606dabcefabSJens Axboe 160757dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 160857dacad5SJay Sternberg { 16091c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 161069d9a99cSKeith Busch /* 161169d9a99cSKeith Busch * If the controller was reset during removal, it's possible 161269d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 161369d9a99cSKeith Busch * queue to flush these to completion. 161469d9a99cSKeith Busch */ 1615c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16161c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 161757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 161857dacad5SJay Sternberg } 161957dacad5SJay Sternberg } 162057dacad5SJay Sternberg 162157dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 162257dacad5SJay Sternberg { 16231c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 162457dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 162557dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1626e3e9d50cSKeith Busch 162738dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 162857dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 162957dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1630d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1631d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 163257dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 163357dacad5SJay Sternberg 163457dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 163557dacad5SJay Sternberg return -ENOMEM; 163634b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 163757dacad5SJay Sternberg 16381c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16391c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 164057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 164157dacad5SJay Sternberg return -ENOMEM; 164257dacad5SJay Sternberg } 16431c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 164457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16451c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 164657dacad5SJay Sternberg return -ENODEV; 164757dacad5SJay Sternberg } 164857dacad5SJay Sternberg } else 1649c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 165057dacad5SJay Sternberg 165157dacad5SJay Sternberg return 0; 165257dacad5SJay Sternberg } 165357dacad5SJay Sternberg 165497f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 165597f6ef64SXu Yu { 165697f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 165797f6ef64SXu Yu } 165897f6ef64SXu Yu 165997f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 166097f6ef64SXu Yu { 166197f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 166297f6ef64SXu Yu 166397f6ef64SXu Yu if (size <= dev->bar_mapped_size) 166497f6ef64SXu Yu return 0; 166597f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 166697f6ef64SXu Yu return -ENOMEM; 166797f6ef64SXu Yu if (dev->bar) 166897f6ef64SXu Yu iounmap(dev->bar); 166997f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 167097f6ef64SXu Yu if (!dev->bar) { 167197f6ef64SXu Yu dev->bar_mapped_size = 0; 167297f6ef64SXu Yu return -ENOMEM; 167397f6ef64SXu Yu } 167497f6ef64SXu Yu dev->bar_mapped_size = size; 167597f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 167697f6ef64SXu Yu 167797f6ef64SXu Yu return 0; 167897f6ef64SXu Yu } 167997f6ef64SXu Yu 168001ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 168157dacad5SJay Sternberg { 168257dacad5SJay Sternberg int result; 168357dacad5SJay Sternberg u32 aqa; 168457dacad5SJay Sternberg struct nvme_queue *nvmeq; 168557dacad5SJay Sternberg 168697f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 168797f6ef64SXu Yu if (result < 0) 168897f6ef64SXu Yu return result; 168997f6ef64SXu Yu 16908ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 169120d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 169257dacad5SJay Sternberg 16937a67cbeaSChristoph Hellwig if (dev->subsystem && 16947a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16957a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 169657dacad5SJay Sternberg 169720d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 169857dacad5SJay Sternberg if (result < 0) 169957dacad5SJay Sternberg return result; 170057dacad5SJay Sternberg 1701a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1702147b27e4SSagi Grimberg if (result) 1703147b27e4SSagi Grimberg return result; 170457dacad5SJay Sternberg 1705147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 170657dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 170757dacad5SJay Sternberg aqa |= aqa << 16; 170857dacad5SJay Sternberg 17097a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17107a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17117a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 171257dacad5SJay Sternberg 171320d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 171457dacad5SJay Sternberg if (result) 1715d4875622SKeith Busch return result; 171657dacad5SJay Sternberg 171757dacad5SJay Sternberg nvmeq->cq_vector = 0; 1718161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1719dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 172057dacad5SJay Sternberg if (result) { 17217c349ddeSKeith Busch dev->online_queues--; 1722d4875622SKeith Busch return result; 172357dacad5SJay Sternberg } 172457dacad5SJay Sternberg 17254e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 172657dacad5SJay Sternberg return result; 172757dacad5SJay Sternberg } 172857dacad5SJay Sternberg 1729749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 173057dacad5SJay Sternberg { 17314b04cc6aSJens Axboe unsigned i, max, rw_queues; 1732749941f2SChristoph Hellwig int ret = 0; 173357dacad5SJay Sternberg 1734d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1735a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1736749941f2SChristoph Hellwig ret = -ENOMEM; 173757dacad5SJay Sternberg break; 1738749941f2SChristoph Hellwig } 1739749941f2SChristoph Hellwig } 174057dacad5SJay Sternberg 1741d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1742e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1743e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1744e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17454b04cc6aSJens Axboe } else { 17464b04cc6aSJens Axboe rw_queues = max; 17474b04cc6aSJens Axboe } 17484b04cc6aSJens Axboe 1749949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17504b04cc6aSJens Axboe bool polled = i > rw_queues; 17514b04cc6aSJens Axboe 17524b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1753d4875622SKeith Busch if (ret) 175457dacad5SJay Sternberg break; 175557dacad5SJay Sternberg } 175657dacad5SJay Sternberg 1757749941f2SChristoph Hellwig /* 1758749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17598adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17608adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1761749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1762749941f2SChristoph Hellwig */ 1763749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 176457dacad5SJay Sternberg } 176557dacad5SJay Sternberg 1766202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1767202021c1SStephen Bates struct device_attribute *attr, 1768202021c1SStephen Bates char *buf) 1769202021c1SStephen Bates { 1770202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1771202021c1SStephen Bates 1772c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1773202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1774202021c1SStephen Bates } 1775202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1776202021c1SStephen Bates 177788de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 177857dacad5SJay Sternberg { 177988de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 178088de4598SChristoph Hellwig 178188de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 178288de4598SChristoph Hellwig } 178388de4598SChristoph Hellwig 178488de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 178588de4598SChristoph Hellwig { 178688de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 178788de4598SChristoph Hellwig } 178888de4598SChristoph Hellwig 1789f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 179057dacad5SJay Sternberg { 179188de4598SChristoph Hellwig u64 size, offset; 179257dacad5SJay Sternberg resource_size_t bar_size; 179357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17948969f1f8SChristoph Hellwig int bar; 179557dacad5SJay Sternberg 17969fe5c59fSKeith Busch if (dev->cmb_size) 17979fe5c59fSKeith Busch return; 17989fe5c59fSKeith Busch 17997a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1800f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1801f65efd6dSChristoph Hellwig return; 1802202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 180357dacad5SJay Sternberg 180488de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 180588de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18068969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18078969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 180857dacad5SJay Sternberg 180957dacad5SJay Sternberg if (offset > bar_size) 1810f65efd6dSChristoph Hellwig return; 181157dacad5SJay Sternberg 181257dacad5SJay Sternberg /* 181357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 181457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 181557dacad5SJay Sternberg * the reported size of the BAR 181657dacad5SJay Sternberg */ 181757dacad5SJay Sternberg if (size > bar_size - offset) 181857dacad5SJay Sternberg size = bar_size - offset; 181957dacad5SJay Sternberg 18200f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18210f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18220f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1823f65efd6dSChristoph Hellwig return; 18240f238ff5SLogan Gunthorpe } 18250f238ff5SLogan Gunthorpe 182657dacad5SJay Sternberg dev->cmb_size = size; 18270f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18280f238ff5SLogan Gunthorpe 18290f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18300f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18310f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1832f65efd6dSChristoph Hellwig 1833f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1834f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1835f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1836f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 183757dacad5SJay Sternberg } 183857dacad5SJay Sternberg 183957dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 184057dacad5SJay Sternberg { 18410f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1842f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1843f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18440f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1845f63572dfSJon Derrick } 184657dacad5SJay Sternberg } 184757dacad5SJay Sternberg 184887ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 184957dacad5SJay Sternberg { 18504033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 185187ad72a5SChristoph Hellwig struct nvme_command c; 185287ad72a5SChristoph Hellwig int ret; 185387ad72a5SChristoph Hellwig 185487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 185587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 185687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 185787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 185887ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 185987ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 186087ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 186187ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 186287ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 186387ad72a5SChristoph Hellwig 186487ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 186587ad72a5SChristoph Hellwig if (ret) { 186687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 186787ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 186887ad72a5SChristoph Hellwig ret, bits); 186987ad72a5SChristoph Hellwig } 187087ad72a5SChristoph Hellwig return ret; 187187ad72a5SChristoph Hellwig } 187287ad72a5SChristoph Hellwig 187387ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 187487ad72a5SChristoph Hellwig { 187587ad72a5SChristoph Hellwig int i; 187687ad72a5SChristoph Hellwig 187787ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 187887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 187987ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 188087ad72a5SChristoph Hellwig 1881cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1882cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1883cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 188487ad72a5SChristoph Hellwig } 188587ad72a5SChristoph Hellwig 188687ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 188787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18884033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18894033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18904033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 189187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18927e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 189387ad72a5SChristoph Hellwig } 189487ad72a5SChristoph Hellwig 189592dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 189692dc6895SChristoph Hellwig u32 chunk_size) 189787ad72a5SChristoph Hellwig { 189887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 189992dc6895SChristoph Hellwig u32 max_entries, len; 19004033f35dSChristoph Hellwig dma_addr_t descs_dma; 19012ee0e4edSDan Carpenter int i = 0; 190287ad72a5SChristoph Hellwig void **bufs; 19036fbcde66SMinwoo Im u64 size, tmp; 190487ad72a5SChristoph Hellwig 190587ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 190687ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 190787ad72a5SChristoph Hellwig max_entries = tmp; 1908044a9df1SChristoph Hellwig 1909044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1910044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1911044a9df1SChristoph Hellwig 1912750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19134033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 191487ad72a5SChristoph Hellwig if (!descs) 191587ad72a5SChristoph Hellwig goto out; 191687ad72a5SChristoph Hellwig 191787ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 191887ad72a5SChristoph Hellwig if (!bufs) 191987ad72a5SChristoph Hellwig goto out_free_descs; 192087ad72a5SChristoph Hellwig 1921244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 192287ad72a5SChristoph Hellwig dma_addr_t dma_addr; 192387ad72a5SChristoph Hellwig 192450cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 192587ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 192687ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192787ad72a5SChristoph Hellwig if (!bufs[i]) 192887ad72a5SChristoph Hellwig break; 192987ad72a5SChristoph Hellwig 193087ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 193187ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 193287ad72a5SChristoph Hellwig i++; 193387ad72a5SChristoph Hellwig } 193487ad72a5SChristoph Hellwig 193592dc6895SChristoph Hellwig if (!size) 193687ad72a5SChristoph Hellwig goto out_free_bufs; 193787ad72a5SChristoph Hellwig 193887ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 193987ad72a5SChristoph Hellwig dev->host_mem_size = size; 194087ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19414033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 194287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 194387ad72a5SChristoph Hellwig return 0; 194487ad72a5SChristoph Hellwig 194587ad72a5SChristoph Hellwig out_free_bufs: 194687ad72a5SChristoph Hellwig while (--i >= 0) { 194787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 194887ad72a5SChristoph Hellwig 1949cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1950cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1951cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 195287ad72a5SChristoph Hellwig } 195387ad72a5SChristoph Hellwig 195487ad72a5SChristoph Hellwig kfree(bufs); 195587ad72a5SChristoph Hellwig out_free_descs: 19564033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19574033f35dSChristoph Hellwig descs_dma); 195887ad72a5SChristoph Hellwig out: 195987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 196087ad72a5SChristoph Hellwig return -ENOMEM; 196187ad72a5SChristoph Hellwig } 196287ad72a5SChristoph Hellwig 196392dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 196492dc6895SChristoph Hellwig { 196592dc6895SChristoph Hellwig u32 chunk_size; 196692dc6895SChristoph Hellwig 196792dc6895SChristoph Hellwig /* start big and work our way down */ 196830f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1969044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 197092dc6895SChristoph Hellwig chunk_size /= 2) { 197192dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197292dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 197392dc6895SChristoph Hellwig return 0; 197492dc6895SChristoph Hellwig nvme_free_host_mem(dev); 197592dc6895SChristoph Hellwig } 197692dc6895SChristoph Hellwig } 197792dc6895SChristoph Hellwig 197892dc6895SChristoph Hellwig return -ENOMEM; 197992dc6895SChristoph Hellwig } 198092dc6895SChristoph Hellwig 19819620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198287ad72a5SChristoph Hellwig { 198387ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 198487ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 198587ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 198687ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19876fbcde66SMinwoo Im int ret; 198887ad72a5SChristoph Hellwig 198987ad72a5SChristoph Hellwig preferred = min(preferred, max); 199087ad72a5SChristoph Hellwig if (min > max) { 199187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199287ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 199387ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 199487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19959620cfbaSChristoph Hellwig return 0; 199687ad72a5SChristoph Hellwig } 199787ad72a5SChristoph Hellwig 199887ad72a5SChristoph Hellwig /* 199987ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 200087ad72a5SChristoph Hellwig */ 200187ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200287ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 200387ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 200487ad72a5SChristoph Hellwig else 200587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 200687ad72a5SChristoph Hellwig } 200787ad72a5SChristoph Hellwig 200887ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 200992dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 201092dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 201192dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20129620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 201387ad72a5SChristoph Hellwig } 201487ad72a5SChristoph Hellwig 201592dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 201692dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 201792dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 201892dc6895SChristoph Hellwig } 201992dc6895SChristoph Hellwig 20209620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20219620cfbaSChristoph Hellwig if (ret) 202287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20239620cfbaSChristoph Hellwig return ret; 202457dacad5SJay Sternberg } 202557dacad5SJay Sternberg 2026612b7286SMing Lei /* 2027612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2028612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2029612b7286SMing Lei */ 2030612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20313b6592f7SJens Axboe { 2032612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2033612b7286SMing Lei unsigned int nr_read_queues; 2034c45b1fa2SMing Lei 20353b6592f7SJens Axboe /* 2036612b7286SMing Lei * If there is no interupt available for queues, ensure that 2037612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2038612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2039612b7286SMing Lei * 2040612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2041612b7286SMing Lei * write and read queues. 2042612b7286SMing Lei * 2043612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2044612b7286SMing Lei * queue. 20453b6592f7SJens Axboe */ 2046612b7286SMing Lei if (!nrirqs) { 2047612b7286SMing Lei nrirqs = 1; 2048612b7286SMing Lei nr_read_queues = 0; 2049612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2050612b7286SMing Lei nr_read_queues = 0; 2051612b7286SMing Lei } else if (write_queues >= nrirqs) { 2052612b7286SMing Lei nr_read_queues = 1; 20533b6592f7SJens Axboe } else { 2054612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20553b6592f7SJens Axboe } 2056612b7286SMing Lei 2057612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2058612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2059612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2060612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2061612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20623b6592f7SJens Axboe } 20633b6592f7SJens Axboe 20646451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20653b6592f7SJens Axboe { 20663b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20673b6592f7SJens Axboe struct irq_affinity affd = { 20683b6592f7SJens Axboe .pre_vectors = 1, 2069612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2070612b7286SMing Lei .priv = dev, 20713b6592f7SJens Axboe }; 20726451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20736451fe73SJens Axboe 20746451fe73SJens Axboe /* 20756451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20766451fe73SJens Axboe * queue left over for non-polled IO. 20776451fe73SJens Axboe */ 20786451fe73SJens Axboe this_p_queues = poll_queues; 20796451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20806451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20816451fe73SJens Axboe irq_queues = 1; 20826451fe73SJens Axboe } else { 2083c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20846451fe73SJens Axboe } 20856451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20863b6592f7SJens Axboe 2087612b7286SMing Lei /* Initialize for the single interrupt case */ 2088612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2089612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20903b6592f7SJens Axboe 2091612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20923b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20933b6592f7SJens Axboe } 20943b6592f7SJens Axboe 20958fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20968fae268bSKeith Busch { 20978fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20988fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20998fae268bSKeith Busch } 21008fae268bSKeith Busch 210157dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 210257dacad5SJay Sternberg { 2103147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 210457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 210597f6ef64SXu Yu int result, nr_io_queues; 210697f6ef64SXu Yu unsigned long size; 210757dacad5SJay Sternberg 21083b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21099a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21109a0be7abSChristoph Hellwig if (result < 0) 211157dacad5SJay Sternberg return result; 21129a0be7abSChristoph Hellwig 2113f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2114a5229050SKeith Busch return 0; 211557dacad5SJay Sternberg 21164e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21174e224106SChristoph Hellwig 21180f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 211957dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 212057dacad5SJay Sternberg sizeof(struct nvme_command)); 212157dacad5SJay Sternberg if (result > 0) 212257dacad5SJay Sternberg dev->q_depth = result; 212357dacad5SJay Sternberg else 21240f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 212557dacad5SJay Sternberg } 212657dacad5SJay Sternberg 212757dacad5SJay Sternberg do { 212897f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 212997f6ef64SXu Yu result = nvme_remap_bar(dev, size); 213097f6ef64SXu Yu if (!result) 213157dacad5SJay Sternberg break; 213257dacad5SJay Sternberg if (!--nr_io_queues) 213357dacad5SJay Sternberg return -ENOMEM; 213457dacad5SJay Sternberg } while (1); 213557dacad5SJay Sternberg adminq->q_db = dev->dbs; 213657dacad5SJay Sternberg 21378fae268bSKeith Busch retry: 213857dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21390ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 214057dacad5SJay Sternberg 214157dacad5SJay Sternberg /* 214257dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 214357dacad5SJay Sternberg * setting up the full range we need. 214457dacad5SJay Sternberg */ 2145dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21463b6592f7SJens Axboe 21473b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 214822b55601SKeith Busch if (result <= 0) 2149dca51e78SChristoph Hellwig return -EIO; 21503b6592f7SJens Axboe 215122b55601SKeith Busch dev->num_vecs = result; 21524b04cc6aSJens Axboe result = max(result - 1, 1); 2153e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 215457dacad5SJay Sternberg 215557dacad5SJay Sternberg /* 215657dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 215757dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 215857dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 215957dacad5SJay Sternberg * number of interrupts. 216057dacad5SJay Sternberg */ 2161dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21627c349ddeSKeith Busch if (result) 2163d4875622SKeith Busch return result; 21644e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21658fae268bSKeith Busch 21668fae268bSKeith Busch result = nvme_create_io_queues(dev); 21678fae268bSKeith Busch if (result || dev->online_queues < 2) 21688fae268bSKeith Busch return result; 21698fae268bSKeith Busch 21708fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21718fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21728fae268bSKeith Busch nvme_disable_io_queues(dev); 21738fae268bSKeith Busch nvme_suspend_io_queues(dev); 21748fae268bSKeith Busch goto retry; 21758fae268bSKeith Busch } 21768fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21778fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21788fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21798fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21808fae268bSKeith Busch return 0; 218157dacad5SJay Sternberg } 218257dacad5SJay Sternberg 21832a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2184db3cbfffSKeith Busch { 2185db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2186db3cbfffSKeith Busch 2187db3cbfffSKeith Busch blk_mq_free_request(req); 2188d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2189db3cbfffSKeith Busch } 2190db3cbfffSKeith Busch 21912a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2192db3cbfffSKeith Busch { 2193db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2194db3cbfffSKeith Busch 2195d1ed6aa1SChristoph Hellwig if (error) 2196d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2197db3cbfffSKeith Busch 2198db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2199db3cbfffSKeith Busch } 2200db3cbfffSKeith Busch 2201db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2202db3cbfffSKeith Busch { 2203db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2204db3cbfffSKeith Busch struct request *req; 2205db3cbfffSKeith Busch struct nvme_command cmd; 2206db3cbfffSKeith Busch 2207db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2208db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2209db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2210db3cbfffSKeith Busch 2211eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2212db3cbfffSKeith Busch if (IS_ERR(req)) 2213db3cbfffSKeith Busch return PTR_ERR(req); 2214db3cbfffSKeith Busch 2215db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2216db3cbfffSKeith Busch req->end_io_data = nvmeq; 2217db3cbfffSKeith Busch 2218d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2219db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2220db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2221db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2222db3cbfffSKeith Busch return 0; 2223db3cbfffSKeith Busch } 2224db3cbfffSKeith Busch 22258fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2226db3cbfffSKeith Busch { 22275271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2228db3cbfffSKeith Busch unsigned long timeout; 2229db3cbfffSKeith Busch 2230db3cbfffSKeith Busch retry: 2231db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22325271edd4SChristoph Hellwig while (nr_queues > 0) { 22335271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2234db3cbfffSKeith Busch break; 22355271edd4SChristoph Hellwig nr_queues--; 22365271edd4SChristoph Hellwig sent++; 22375271edd4SChristoph Hellwig } 2238d1ed6aa1SChristoph Hellwig while (sent) { 2239d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2240d1ed6aa1SChristoph Hellwig 2241d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22425271edd4SChristoph Hellwig timeout); 2243db3cbfffSKeith Busch if (timeout == 0) 22445271edd4SChristoph Hellwig return false; 2245d1ed6aa1SChristoph Hellwig 2246d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2247d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2248d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2249d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2250d1ed6aa1SChristoph Hellwig 2251d1ed6aa1SChristoph Hellwig sent--; 22525271edd4SChristoph Hellwig if (nr_queues) 2253db3cbfffSKeith Busch goto retry; 2254db3cbfffSKeith Busch } 22555271edd4SChristoph Hellwig return true; 2256db3cbfffSKeith Busch } 2257db3cbfffSKeith Busch 225857dacad5SJay Sternberg /* 22592b1b7e78SJianchao Wang * return error value only when tagset allocation failed 226057dacad5SJay Sternberg */ 226157dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 226257dacad5SJay Sternberg { 22632b1b7e78SJianchao Wang int ret; 22642b1b7e78SJianchao Wang 22655bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2266c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 226757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2268ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2269ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2270ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 227157dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 227257dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 227357dacad5SJay Sternberg dev->tagset.queue_depth = 227457dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2275d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 227657dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 227757dacad5SJay Sternberg dev->tagset.driver_data = dev; 227857dacad5SJay Sternberg 22792b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22802b1b7e78SJianchao Wang if (ret) { 22812b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22822b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22832b1b7e78SJianchao Wang return ret; 22842b1b7e78SJianchao Wang } 22855bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2286949928c1SKeith Busch } else { 2287949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2288949928c1SKeith Busch 2289949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2290949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 229157dacad5SJay Sternberg } 2292949928c1SKeith Busch 2293e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 229457dacad5SJay Sternberg return 0; 229557dacad5SJay Sternberg } 229657dacad5SJay Sternberg 2297b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 229857dacad5SJay Sternberg { 2299b00a726aSKeith Busch int result = -ENOMEM; 230057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 230157dacad5SJay Sternberg 230257dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 230357dacad5SJay Sternberg return result; 230457dacad5SJay Sternberg 230557dacad5SJay Sternberg pci_set_master(pdev); 230657dacad5SJay Sternberg 230757dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 230857dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 230957dacad5SJay Sternberg goto disable; 231057dacad5SJay Sternberg 23117a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 231257dacad5SJay Sternberg result = -ENODEV; 2313b00a726aSKeith Busch goto disable; 231457dacad5SJay Sternberg } 231557dacad5SJay Sternberg 231657dacad5SJay Sternberg /* 2317a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2318a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2319a5229050SKeith Busch * adjust this later. 232057dacad5SJay Sternberg */ 2321dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2322dca51e78SChristoph Hellwig if (result < 0) 2323dca51e78SChristoph Hellwig return result; 232457dacad5SJay Sternberg 232520d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23267a67cbeaSChristoph Hellwig 232720d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2328b27c1e68Sweiping zhang io_queue_depth); 232920d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23307a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23311f390c1fSStephan Günther 23321f390c1fSStephan Günther /* 23331f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23341f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23351f390c1fSStephan Günther */ 23361f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23371f390c1fSStephan Günther dev->q_depth = 2; 23389bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23399bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23401f390c1fSStephan Günther dev->q_depth); 2341d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2342d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 234320d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2344d554b5e1SMartin K. Petersen dev->q_depth = 64; 2345d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2346d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23471f390c1fSStephan Günther } 23481f390c1fSStephan Günther 2349f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2350202021c1SStephen Bates 2351a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2352a0a3408eSKeith Busch pci_save_state(pdev); 235357dacad5SJay Sternberg return 0; 235457dacad5SJay Sternberg 235557dacad5SJay Sternberg disable: 235657dacad5SJay Sternberg pci_disable_device(pdev); 235757dacad5SJay Sternberg return result; 235857dacad5SJay Sternberg } 235957dacad5SJay Sternberg 236057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 236157dacad5SJay Sternberg { 2362b00a726aSKeith Busch if (dev->bar) 2363b00a726aSKeith Busch iounmap(dev->bar); 2364a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2365b00a726aSKeith Busch } 2366b00a726aSKeith Busch 2367b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2368b00a726aSKeith Busch { 236957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 237057dacad5SJay Sternberg 2371dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 237257dacad5SJay Sternberg 2373a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2374a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 237557dacad5SJay Sternberg pci_disable_device(pdev); 237657dacad5SJay Sternberg } 2377a0a3408eSKeith Busch } 237857dacad5SJay Sternberg 2379a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 238057dacad5SJay Sternberg { 2381e43269e6SKeith Busch bool dead = true, freeze = false; 2382302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 238357dacad5SJay Sternberg 238477bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2385302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2386302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2387302ad8ccSKeith Busch 2388ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2389e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2390e43269e6SKeith Busch freeze = true; 2391302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2392e43269e6SKeith Busch } 2393302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2394302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 239557dacad5SJay Sternberg } 2396c21377f8SGabriel Krisman Bertazi 2397302ad8ccSKeith Busch /* 2398302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2399302ad8ccSKeith Busch * doing a safe shutdown. 2400302ad8ccSKeith Busch */ 2401e43269e6SKeith Busch if (!dead && shutdown && freeze) 2402302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 240387ad72a5SChristoph Hellwig 24049a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24059a915a5bSJianchao Wang 240664ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24078fae268bSKeith Busch nvme_disable_io_queues(dev); 2408a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 240957dacad5SJay Sternberg } 24108fae268bSKeith Busch nvme_suspend_io_queues(dev); 24118fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2412b00a726aSKeith Busch nvme_pci_disable(dev); 241357dacad5SJay Sternberg 2414e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2415e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2416302ad8ccSKeith Busch 2417302ad8ccSKeith Busch /* 2418302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2419302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2420302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2421302ad8ccSKeith Busch */ 2422c8e9e9b7SKeith Busch if (shutdown) { 2423302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2424c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2425c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2426c8e9e9b7SKeith Busch } 242777bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 242857dacad5SJay Sternberg } 242957dacad5SJay Sternberg 243057dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 243157dacad5SJay Sternberg { 243257dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 243357dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 243457dacad5SJay Sternberg if (!dev->prp_page_pool) 243557dacad5SJay Sternberg return -ENOMEM; 243657dacad5SJay Sternberg 243757dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 243857dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 243957dacad5SJay Sternberg 256, 256, 0); 244057dacad5SJay Sternberg if (!dev->prp_small_pool) { 244157dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 244257dacad5SJay Sternberg return -ENOMEM; 244357dacad5SJay Sternberg } 244457dacad5SJay Sternberg return 0; 244557dacad5SJay Sternberg } 244657dacad5SJay Sternberg 244757dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 244857dacad5SJay Sternberg { 244957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 245057dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 245157dacad5SJay Sternberg } 245257dacad5SJay Sternberg 24531673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 245457dacad5SJay Sternberg { 24551673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 245657dacad5SJay Sternberg 2457f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 245857dacad5SJay Sternberg put_device(dev->dev); 245957dacad5SJay Sternberg if (dev->tagset.tags) 246057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24611c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24621c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 246357dacad5SJay Sternberg kfree(dev->queues); 2464e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2465943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 246657dacad5SJay Sternberg kfree(dev); 246757dacad5SJay Sternberg } 246857dacad5SJay Sternberg 2469f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2470f58944e2SKeith Busch { 2471237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2472f58944e2SKeith Busch 2473d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 247469d9a99cSKeith Busch nvme_dev_disable(dev, false); 24759f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 247603e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2477f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2478f58944e2SKeith Busch } 2479f58944e2SKeith Busch 2480fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 248157dacad5SJay Sternberg { 2482d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2483d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2484a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2485f58944e2SKeith Busch int result = -ENODEV; 24862b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 248757dacad5SJay Sternberg 248882b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2489fd634f41SChristoph Hellwig goto out; 2490fd634f41SChristoph Hellwig 2491fd634f41SChristoph Hellwig /* 2492fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2493fd634f41SChristoph Hellwig * moving on. 2494fd634f41SChristoph Hellwig */ 2495b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2496a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2497d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2498fd634f41SChristoph Hellwig 24995c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2500b00a726aSKeith Busch result = nvme_pci_enable(dev); 250157dacad5SJay Sternberg if (result) 25024726bcf3SKeith Busch goto out_unlock; 250357dacad5SJay Sternberg 250401ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 250557dacad5SJay Sternberg if (result) 25064726bcf3SKeith Busch goto out_unlock; 250757dacad5SJay Sternberg 250857dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 250957dacad5SJay Sternberg if (result) 25104726bcf3SKeith Busch goto out_unlock; 251157dacad5SJay Sternberg 2512943e942eSJens Axboe /* 2513943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2514943e942eSJens Axboe * over a single page. 2515943e942eSJens Axboe */ 2516943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2517943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2518a48bc520SChristoph Hellwig 2519a48bc520SChristoph Hellwig /* 2520a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2521a48bc520SChristoph Hellwig */ 2522a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2523a48bc520SChristoph Hellwig 25245c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25255c959d73SKeith Busch 25265c959d73SKeith Busch /* 25275c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25285c959d73SKeith Busch * initializing procedure here. 25295c959d73SKeith Busch */ 25305c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25315c959d73SKeith Busch dev_warn(dev->ctrl.device, 25325c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 25335c959d73SKeith Busch goto out; 25345c959d73SKeith Busch } 2535943e942eSJens Axboe 2536ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2537ce4541f4SChristoph Hellwig if (result) 2538f58944e2SKeith Busch goto out; 2539ce4541f4SChristoph Hellwig 2540e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2541e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25424f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25434f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2544e286bcfcSScott Bauer else if (was_suspend) 25454f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2546e286bcfcSScott Bauer } else { 2547e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2548e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2549e286bcfcSScott Bauer } 2550a98e58e5SScott Bauer 2551f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2552f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2553f9f38e33SHelen Koike if (result) 2554f9f38e33SHelen Koike dev_warn(dev->dev, 2555f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2556f9f38e33SHelen Koike } 2557f9f38e33SHelen Koike 25589620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25599620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25609620cfbaSChristoph Hellwig if (result < 0) 25619620cfbaSChristoph Hellwig goto out; 25629620cfbaSChristoph Hellwig } 256387ad72a5SChristoph Hellwig 256457dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 256557dacad5SJay Sternberg if (result) 2566f58944e2SKeith Busch goto out; 256757dacad5SJay Sternberg 256821f033f7SKeith Busch /* 256957dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 257057dacad5SJay Sternberg * any working I/O queue. 257157dacad5SJay Sternberg */ 257257dacad5SJay Sternberg if (dev->online_queues < 2) { 25731b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25743b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25755bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25762b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 257757dacad5SJay Sternberg } else { 257825646264SKeith Busch nvme_start_queues(&dev->ctrl); 2579302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25802b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25812b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25822b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2583302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 258457dacad5SJay Sternberg } 258557dacad5SJay Sternberg 25862b1b7e78SJianchao Wang /* 25872b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25882b1b7e78SJianchao Wang * recovery. 25892b1b7e78SJianchao Wang */ 25902b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 25912b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25922b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2593bb8d261eSChristoph Hellwig goto out; 2594bb8d261eSChristoph Hellwig } 259592911a55SChristoph Hellwig 2596d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 259757dacad5SJay Sternberg return; 259857dacad5SJay Sternberg 25994726bcf3SKeith Busch out_unlock: 26004726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 260157dacad5SJay Sternberg out: 2602f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 260357dacad5SJay Sternberg } 260457dacad5SJay Sternberg 26055c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 260657dacad5SJay Sternberg { 26075c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 260857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 260957dacad5SJay Sternberg 261057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2611921920abSKeith Busch device_release_driver(&pdev->dev); 26121673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 261357dacad5SJay Sternberg } 261457dacad5SJay Sternberg 26151c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 261657dacad5SJay Sternberg { 26171c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26181c63dc66SChristoph Hellwig return 0; 261957dacad5SJay Sternberg } 26201c63dc66SChristoph Hellwig 26215fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26225fd4ce1bSChristoph Hellwig { 26235fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26245fd4ce1bSChristoph Hellwig return 0; 26255fd4ce1bSChristoph Hellwig } 26265fd4ce1bSChristoph Hellwig 26277fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26287fd8930fSChristoph Hellwig { 26297fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26307fd8930fSChristoph Hellwig return 0; 26317fd8930fSChristoph Hellwig } 26327fd8930fSChristoph Hellwig 263397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 263497c12223SKeith Busch { 263597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 263697c12223SKeith Busch 263797c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 263897c12223SKeith Busch } 263997c12223SKeith Busch 26401c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26411a353d85SMing Lin .name = "pcie", 2642e439bb12SSagi Grimberg .module = THIS_MODULE, 2643e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2644e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26451c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26465fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26477fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26481673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2649f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 265097c12223SKeith Busch .get_address = nvme_pci_get_address, 26511c63dc66SChristoph Hellwig }; 265257dacad5SJay Sternberg 2653b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2654b00a726aSKeith Busch { 2655b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2656b00a726aSKeith Busch 2657a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2658b00a726aSKeith Busch return -ENODEV; 2659b00a726aSKeith Busch 266097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2661b00a726aSKeith Busch goto release; 2662b00a726aSKeith Busch 2663b00a726aSKeith Busch return 0; 2664b00a726aSKeith Busch release: 2665a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2666b00a726aSKeith Busch return -ENODEV; 2667b00a726aSKeith Busch } 2668b00a726aSKeith Busch 26698427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2670ff5350a8SAndy Lutomirski { 2671ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2672ff5350a8SAndy Lutomirski /* 2673ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2674ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2675ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2676ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2677ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2678ff5350a8SAndy Lutomirski * laptops. 2679ff5350a8SAndy Lutomirski */ 2680ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2681ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2682ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2683ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26848427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26858427bbc2SKai-Heng Feng /* 26868427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2687467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2688467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2689467c77d4SJarosław Janik * ASUS PRIME Z370-A 26908427bbc2SKai-Heng Feng */ 26918427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2692467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2693467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 26948427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2695ff5350a8SAndy Lutomirski } 2696ff5350a8SAndy Lutomirski 2697ff5350a8SAndy Lutomirski return 0; 2698ff5350a8SAndy Lutomirski } 2699ff5350a8SAndy Lutomirski 270018119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 270118119775SKeith Busch { 270218119775SKeith Busch struct nvme_dev *dev = data; 270380f513b5SKeith Busch 270418119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 270518119775SKeith Busch flush_work(&dev->ctrl.scan_work); 270680f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 270718119775SKeith Busch } 270818119775SKeith Busch 270957dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 271057dacad5SJay Sternberg { 271157dacad5SJay Sternberg int node, result = -ENOMEM; 271257dacad5SJay Sternberg struct nvme_dev *dev; 2713ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2714943e942eSJens Axboe size_t alloc_size; 271557dacad5SJay Sternberg 271657dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 271757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27182fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 271957dacad5SJay Sternberg 272057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 272157dacad5SJay Sternberg if (!dev) 272257dacad5SJay Sternberg return -ENOMEM; 2723147b27e4SSagi Grimberg 27243b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27253b6592f7SJens Axboe GFP_KERNEL, node); 272657dacad5SJay Sternberg if (!dev->queues) 272757dacad5SJay Sternberg goto free; 272857dacad5SJay Sternberg 272957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 273057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 273157dacad5SJay Sternberg 2732b00a726aSKeith Busch result = nvme_dev_map(dev); 2733b00a726aSKeith Busch if (result) 2734b00c9b7aSChristophe JAILLET goto put_pci; 2735b00a726aSKeith Busch 2736d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27375c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 273877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2739f3ca80fcSChristoph Hellwig 2740f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2741f3ca80fcSChristoph Hellwig if (result) 2742b00c9b7aSChristophe JAILLET goto unmap; 2743f3ca80fcSChristoph Hellwig 27448427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2745ff5350a8SAndy Lutomirski 2746943e942eSJens Axboe /* 2747943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2748943e942eSJens Axboe * command we support. 2749943e942eSJens Axboe */ 2750943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2751943e942eSJens Axboe NVME_MAX_SEGS, true); 2752943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2753943e942eSJens Axboe 2754943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2755943e942eSJens Axboe mempool_kfree, 2756943e942eSJens Axboe (void *) alloc_size, 2757943e942eSJens Axboe GFP_KERNEL, node); 2758943e942eSJens Axboe if (!dev->iod_mempool) { 2759943e942eSJens Axboe result = -ENOMEM; 2760943e942eSJens Axboe goto release_pools; 2761943e942eSJens Axboe } 2762943e942eSJens Axboe 2763b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2764b6e44b4cSKeith Busch quirks); 2765b6e44b4cSKeith Busch if (result) 2766b6e44b4cSKeith Busch goto release_mempool; 2767b6e44b4cSKeith Busch 27681b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27691b3c47c1SSagi Grimberg 277080f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 277118119775SKeith Busch async_schedule(nvme_async_probe, dev); 27724caff8fcSSagi Grimberg 277357dacad5SJay Sternberg return 0; 277457dacad5SJay Sternberg 2775b6e44b4cSKeith Busch release_mempool: 2776b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 277757dacad5SJay Sternberg release_pools: 277857dacad5SJay Sternberg nvme_release_prp_pools(dev); 2779b00c9b7aSChristophe JAILLET unmap: 2780b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 278157dacad5SJay Sternberg put_pci: 278257dacad5SJay Sternberg put_device(dev->dev); 278357dacad5SJay Sternberg free: 278457dacad5SJay Sternberg kfree(dev->queues); 278557dacad5SJay Sternberg kfree(dev); 278657dacad5SJay Sternberg return result; 278757dacad5SJay Sternberg } 278857dacad5SJay Sternberg 2789775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 279057dacad5SJay Sternberg { 279157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2792a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2793775755edSChristoph Hellwig } 279457dacad5SJay Sternberg 2795775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2796775755edSChristoph Hellwig { 2797f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 279879c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 279957dacad5SJay Sternberg } 280057dacad5SJay Sternberg 280157dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 280257dacad5SJay Sternberg { 280357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2804a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 280557dacad5SJay Sternberg } 280657dacad5SJay Sternberg 2807f58944e2SKeith Busch /* 2808f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2809f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2810f58944e2SKeith Busch * order to proceed. 2811f58944e2SKeith Busch */ 281257dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 281357dacad5SJay Sternberg { 281457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 281557dacad5SJay Sternberg 2816bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 281757dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28180ff9d4e1SKeith Busch 28196db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28200ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28211d39e692SKeith Busch nvme_dev_disable(dev, true); 2822cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28236db28edaSKeith Busch } 28240ff9d4e1SKeith Busch 2825d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2826d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2827d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2828a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28299fe5c59fSKeith Busch nvme_release_cmb(dev); 283087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 283157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 283257dacad5SJay Sternberg nvme_free_queues(dev, 0); 2833d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 283457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2835b00a726aSKeith Busch nvme_dev_unmap(dev); 28361673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 283757dacad5SJay Sternberg } 283857dacad5SJay Sternberg 283957dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2840d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2841d916b1beSKeith Busch { 2842d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2843d916b1beSKeith Busch } 2844d916b1beSKeith Busch 2845d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2846d916b1beSKeith Busch { 2847d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2848d916b1beSKeith Busch } 2849d916b1beSKeith Busch 2850d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2851d916b1beSKeith Busch { 2852d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2853d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2854d916b1beSKeith Busch 2855d916b1beSKeith Busch if (pm_resume_via_firmware() || !ctrl->npss || 2856d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2857d916b1beSKeith Busch nvme_reset_ctrl(ctrl); 2858d916b1beSKeith Busch return 0; 2859d916b1beSKeith Busch } 2860d916b1beSKeith Busch 286157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 286257dacad5SJay Sternberg { 286357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 286457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2865d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2866d916b1beSKeith Busch int ret = -EBUSY; 2867d916b1beSKeith Busch 2868d916b1beSKeith Busch /* 2869d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 2870d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 2871d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 2872d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 2873d916b1beSKeith Busch * device does not support any non-default power states, shut down the 2874d916b1beSKeith Busch * device fully. 2875d916b1beSKeith Busch */ 2876d916b1beSKeith Busch if (pm_suspend_via_firmware() || !ctrl->npss) { 2877d916b1beSKeith Busch nvme_dev_disable(ndev, true); 2878d916b1beSKeith Busch return 0; 2879d916b1beSKeith Busch } 2880d916b1beSKeith Busch 2881d916b1beSKeith Busch nvme_start_freeze(ctrl); 2882d916b1beSKeith Busch nvme_wait_freeze(ctrl); 2883d916b1beSKeith Busch nvme_sync_queues(ctrl); 2884d916b1beSKeith Busch 2885d916b1beSKeith Busch if (ctrl->state != NVME_CTRL_LIVE && 2886d916b1beSKeith Busch ctrl->state != NVME_CTRL_ADMIN_ONLY) 2887d916b1beSKeith Busch goto unfreeze; 2888d916b1beSKeith Busch 2889d916b1beSKeith Busch ndev->last_ps = 0; 2890d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2891d916b1beSKeith Busch if (ret < 0) 2892d916b1beSKeith Busch goto unfreeze; 2893d916b1beSKeith Busch 2894d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 2895d916b1beSKeith Busch if (ret < 0) 2896d916b1beSKeith Busch goto unfreeze; 2897d916b1beSKeith Busch 2898d916b1beSKeith Busch if (ret) { 2899d916b1beSKeith Busch /* 2900d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 2901d916b1beSKeith Busch * correct value will be resdicovered then. 2902d916b1beSKeith Busch */ 2903d916b1beSKeith Busch nvme_dev_disable(ndev, true); 2904d916b1beSKeith Busch ctrl->npss = 0; 2905d916b1beSKeith Busch ret = 0; 2906d916b1beSKeith Busch goto unfreeze; 2907d916b1beSKeith Busch } 2908d916b1beSKeith Busch /* 2909d916b1beSKeith Busch * A saved state prevents pci pm from generically controlling the 2910d916b1beSKeith Busch * device's power. If we're using protocol specific settings, we don't 2911d916b1beSKeith Busch * want pci interfering. 2912d916b1beSKeith Busch */ 2913d916b1beSKeith Busch pci_save_state(pdev); 2914d916b1beSKeith Busch unfreeze: 2915d916b1beSKeith Busch nvme_unfreeze(ctrl); 2916d916b1beSKeith Busch return ret; 2917d916b1beSKeith Busch } 2918d916b1beSKeith Busch 2919d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 2920d916b1beSKeith Busch { 2921d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 292257dacad5SJay Sternberg 2923a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 292457dacad5SJay Sternberg return 0; 292557dacad5SJay Sternberg } 292657dacad5SJay Sternberg 2927d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 292857dacad5SJay Sternberg { 292957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 293057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 293157dacad5SJay Sternberg 2932d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 293357dacad5SJay Sternberg return 0; 293457dacad5SJay Sternberg } 293557dacad5SJay Sternberg 2936d916b1beSKeith Busch const struct dev_pm_ops nvme_dev_pm_ops = { 2937d916b1beSKeith Busch .suspend = nvme_suspend, 2938d916b1beSKeith Busch .resume = nvme_resume, 2939d916b1beSKeith Busch .freeze = nvme_simple_suspend, 2940d916b1beSKeith Busch .thaw = nvme_simple_resume, 2941d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 2942d916b1beSKeith Busch .restore = nvme_simple_resume, 2943d916b1beSKeith Busch }; 2944d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 294557dacad5SJay Sternberg 2946a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2947a0a3408eSKeith Busch pci_channel_state_t state) 2948a0a3408eSKeith Busch { 2949a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2950a0a3408eSKeith Busch 2951a0a3408eSKeith Busch /* 2952a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2953a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2954a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2955a0a3408eSKeith Busch */ 2956a0a3408eSKeith Busch switch (state) { 2957a0a3408eSKeith Busch case pci_channel_io_normal: 2958a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2959a0a3408eSKeith Busch case pci_channel_io_frozen: 2960d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2961d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2962a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2963a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2964a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2965d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2966d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2967a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2968a0a3408eSKeith Busch } 2969a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2970a0a3408eSKeith Busch } 2971a0a3408eSKeith Busch 2972a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2973a0a3408eSKeith Busch { 2974a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2975a0a3408eSKeith Busch 29761b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2977a0a3408eSKeith Busch pci_restore_state(pdev); 2978d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2979a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2980a0a3408eSKeith Busch } 2981a0a3408eSKeith Busch 2982a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2983a0a3408eSKeith Busch { 298472cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 298572cd4cc2SKeith Busch 298672cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2987a0a3408eSKeith Busch } 2988a0a3408eSKeith Busch 298957dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 299057dacad5SJay Sternberg .error_detected = nvme_error_detected, 299157dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 299257dacad5SJay Sternberg .resume = nvme_error_resume, 2993775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2994775755edSChristoph Hellwig .reset_done = nvme_reset_done, 299557dacad5SJay Sternberg }; 299657dacad5SJay Sternberg 299757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2998106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 299908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3000e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 300199466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 300299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3003e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 300499466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 300599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3006e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3007f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 3008f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3009f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 301050af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 30119abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 30129abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 30136299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 30146299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3015540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 30167b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 30177b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 30180302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 30190302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 302054adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 302154adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 30228c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 30238c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3024015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3025015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3026d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3027d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3028d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3029d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3030608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3031608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3032608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3033608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3034ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3035ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 303657dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3037c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3038124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 303957dacad5SJay Sternberg { 0, } 304057dacad5SJay Sternberg }; 304157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 304257dacad5SJay Sternberg 304357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 304457dacad5SJay Sternberg .name = "nvme", 304557dacad5SJay Sternberg .id_table = nvme_id_table, 304657dacad5SJay Sternberg .probe = nvme_probe, 304757dacad5SJay Sternberg .remove = nvme_remove, 304857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3049d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 305057dacad5SJay Sternberg .driver = { 305157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 305257dacad5SJay Sternberg }, 3053d916b1beSKeith Busch #endif 305474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 305557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 305657dacad5SJay Sternberg }; 305757dacad5SJay Sternberg 305857dacad5SJay Sternberg static int __init nvme_init(void) 305957dacad5SJay Sternberg { 306081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 306181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 306281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3063612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 30649a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 306557dacad5SJay Sternberg } 306657dacad5SJay Sternberg 306757dacad5SJay Sternberg static void __exit nvme_exit(void) 306857dacad5SJay Sternberg { 306957dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 307003e0f3a6SMing Lei flush_workqueue(nvme_wq); 307157dacad5SJay Sternberg } 307257dacad5SJay Sternberg 307357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 307457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 307557dacad5SJay Sternberg MODULE_VERSION("1.0"); 307657dacad5SJay Sternberg module_init(nvme_init); 307757dacad5SJay Sternberg module_exit(nvme_exit); 3078