15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 1857dacad5SJay Sternberg #include <linux/mm.h> 1957dacad5SJay Sternberg #include <linux/module.h> 2077bf25eaSKeith Busch #include <linux/mutex.h> 21d0877473SKeith Busch #include <linux/once.h> 2257dacad5SJay Sternberg #include <linux/pci.h> 23d916b1beSKeith Busch #include <linux/suspend.h> 2457dacad5SJay Sternberg #include <linux/t10-pi.h> 2557dacad5SJay Sternberg #include <linux/types.h> 269cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2720d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 28a98e58e5SScott Bauer #include <linux/sed-opal.h> 290f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3057dacad5SJay Sternberg 31604c01d5Syupeng #include "trace.h" 3257dacad5SJay Sternberg #include "nvme.h" 3357dacad5SJay Sternberg 34c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 358a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3657dacad5SJay Sternberg 37a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 38adf68f21SChristoph Hellwig 39943e942eSJens Axboe /* 40943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 41943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 42943e942eSJens Axboe */ 43943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 44943e942eSJens Axboe #define NVME_MAX_SEGS 127 45943e942eSJens Axboe 4657dacad5SJay Sternberg static int use_threaded_interrupts; 4757dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4857dacad5SJay Sternberg 4957dacad5SJay Sternberg static bool use_cmb_sqes = true; 5069f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5157dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5257dacad5SJay Sternberg 5387ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5487ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5587ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5687ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5757dacad5SJay Sternberg 58a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 59a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 60a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 61a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 62a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 63a7a7cbe3SChaitanya Kulkarni 6427453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6527453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 66b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 67b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 68b27c1e68Sweiping zhang .set = io_queue_depth_set, 6961f3b896SChaitanya Kulkarni .get = param_get_uint, 70b27c1e68Sweiping zhang }; 71b27c1e68Sweiping zhang 7261f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 73b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7427453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 75b27c1e68Sweiping zhang 769c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 779c9e76d5SWeiping Zhang { 789c9e76d5SWeiping Zhang unsigned int n; 799c9e76d5SWeiping Zhang int ret; 809c9e76d5SWeiping Zhang 819c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 829c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 839c9e76d5SWeiping Zhang return -EINVAL; 849c9e76d5SWeiping Zhang return param_set_uint(val, kp); 859c9e76d5SWeiping Zhang } 869c9e76d5SWeiping Zhang 879c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 889c9e76d5SWeiping Zhang .set = io_queue_count_set, 899c9e76d5SWeiping Zhang .get = param_get_uint, 909c9e76d5SWeiping Zhang }; 919c9e76d5SWeiping Zhang 923f68baf7SKeith Busch static unsigned int write_queues; 939c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 943b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 953b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 963b6592f7SJens Axboe "will share a queue set."); 973b6592f7SJens Axboe 983f68baf7SKeith Busch static unsigned int poll_queues; 999c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1004b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1014b04cc6aSJens Axboe 102df4f9bc4SDavid E. Box static bool noacpi; 103df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 104df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 105df4f9bc4SDavid E. Box 1061c63dc66SChristoph Hellwig struct nvme_dev; 1071c63dc66SChristoph Hellwig struct nvme_queue; 10857dacad5SJay Sternberg 109a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1108fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11157dacad5SJay Sternberg 11257dacad5SJay Sternberg /* 1131c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1141c63dc66SChristoph Hellwig */ 1151c63dc66SChristoph Hellwig struct nvme_dev { 116147b27e4SSagi Grimberg struct nvme_queue *queues; 1171c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1191c63dc66SChristoph Hellwig u32 __iomem *dbs; 1201c63dc66SChristoph Hellwig struct device *dev; 1211c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1231c63dc66SChristoph Hellwig unsigned online_queues; 1241c63dc66SChristoph Hellwig unsigned max_qid; 125e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12622b55601SKeith Busch unsigned int num_vecs; 1277442ddceSJohn Garry u32 q_depth; 128c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1291c63dc66SChristoph Hellwig u32 db_stride; 1301c63dc66SChristoph Hellwig void __iomem *bar; 13197f6ef64SXu Yu unsigned long bar_mapped_size; 1325c8809e6SChristoph Hellwig struct work_struct remove_work; 13377bf25eaSKeith Busch struct mutex shutdown_lock; 1341c63dc66SChristoph Hellwig bool subsystem; 1351c63dc66SChristoph Hellwig u64 cmb_size; 1360f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1371c63dc66SChristoph Hellwig u32 cmbsz; 138202021c1SStephen Bates u32 cmbloc; 1391c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 140d916b1beSKeith Busch u32 last_ps; 141a5df5e79SKeith Busch bool hmb; 14287ad72a5SChristoph Hellwig 143943e942eSJens Axboe mempool_t *iod_mempool; 144943e942eSJens Axboe 14587ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 146f9f38e33SHelen Koike u32 *dbbuf_dbs; 147f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 148f9f38e33SHelen Koike u32 *dbbuf_eis; 149f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15087ad72a5SChristoph Hellwig 15187ad72a5SChristoph Hellwig /* host memory buffer support: */ 15287ad72a5SChristoph Hellwig u64 host_mem_size; 15387ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1544033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15687ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1572a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1582a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 1600521905eSKeith Busch 1610521905eSKeith Busch bool attrs_added; 16257dacad5SJay Sternberg }; 16357dacad5SJay Sternberg 164b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 165b27c1e68Sweiping zhang { 16627453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16727453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 168b27c1e68Sweiping zhang } 169b27c1e68Sweiping zhang 170f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171f9f38e33SHelen Koike { 172f9f38e33SHelen Koike return qid * 2 * stride; 173f9f38e33SHelen Koike } 174f9f38e33SHelen Koike 175f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176f9f38e33SHelen Koike { 177f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 178f9f38e33SHelen Koike } 179f9f38e33SHelen Koike 1801c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1811c63dc66SChristoph Hellwig { 1821c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1831c63dc66SChristoph Hellwig } 1841c63dc66SChristoph Hellwig 18557dacad5SJay Sternberg /* 18657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18757dacad5SJay Sternberg * commands and one for I/O commands). 18857dacad5SJay Sternberg */ 18957dacad5SJay Sternberg struct nvme_queue { 19057dacad5SJay Sternberg struct nvme_dev *dev; 1911ab0cd69SJens Axboe spinlock_t sq_lock; 192c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1933a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1943a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19574943d45SKeith Busch struct nvme_completion *cqes; 19657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19857dacad5SJay Sternberg u32 __iomem *q_db; 1997442ddceSJohn Garry u32 q_depth; 2007c349ddeSKeith Busch u16 cq_vector; 20157dacad5SJay Sternberg u16 sq_tail; 20238210800SKeith Busch u16 last_sq_tail; 20357dacad5SJay Sternberg u16 cq_head; 20457dacad5SJay Sternberg u16 qid; 20557dacad5SJay Sternberg u8 cq_phase; 206c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2074e224106SChristoph Hellwig unsigned long flags; 2084e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20963223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 210d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2117c349ddeSKeith Busch #define NVMEQ_POLLED 3 212f9f38e33SHelen Koike u32 *dbbuf_sq_db; 213f9f38e33SHelen Koike u32 *dbbuf_cq_db; 214f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 215f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 216d1ed6aa1SChristoph Hellwig struct completion delete_done; 21757dacad5SJay Sternberg }; 21857dacad5SJay Sternberg 21957dacad5SJay Sternberg /* 2209b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2219b048119SChristoph Hellwig * 2229b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2239b048119SChristoph Hellwig * to the actual struct scatterlist. 22471bd150cSChristoph Hellwig */ 22571bd150cSChristoph Hellwig struct nvme_iod { 226d49187e9SChristoph Hellwig struct nvme_request req; 227af7fae85SKeith Busch struct nvme_command cmd; 228f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 229a7a7cbe3SChaitanya Kulkarni bool use_sgl; 230f4800d6dSChristoph Hellwig int aborted; 23171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23371bd150cSChristoph Hellwig dma_addr_t first_dma; 234dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 235783b94bdSChristoph Hellwig dma_addr_t meta_dma; 236f4800d6dSChristoph Hellwig struct scatterlist *sg; 23757dacad5SJay Sternberg }; 23857dacad5SJay Sternberg 2392a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2403b6592f7SJens Axboe { 2412a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 242f9f38e33SHelen Koike } 243f9f38e33SHelen Koike 244f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 245f9f38e33SHelen Koike { 2462a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 247f9f38e33SHelen Koike 24858847f12SKeith Busch if (dev->dbbuf_dbs) { 24958847f12SKeith Busch /* 25058847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25158847f12SKeith Busch * values from the previous instantiation. 25258847f12SKeith Busch */ 25358847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25458847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 255f9f38e33SHelen Koike return 0; 25658847f12SKeith Busch } 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 260f9f38e33SHelen Koike GFP_KERNEL); 261f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 262f9f38e33SHelen Koike return -ENOMEM; 263f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 265f9f38e33SHelen Koike GFP_KERNEL); 266f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 267f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 268f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 269f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 270f9f38e33SHelen Koike return -ENOMEM; 271f9f38e33SHelen Koike } 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike return 0; 274f9f38e33SHelen Koike } 275f9f38e33SHelen Koike 276f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 277f9f38e33SHelen Koike { 2782a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 279f9f38e33SHelen Koike 280f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 281f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 282f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 283f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike if (dev->dbbuf_eis) { 286f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 287f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 288f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 289f9f38e33SHelen Koike } 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 293f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 294f9f38e33SHelen Koike { 295f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 296f9f38e33SHelen Koike return; 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 299f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 300f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 301f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike } 303f9f38e33SHelen Koike 3040f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3050f0d2c87SMinwoo Im { 3060f0d2c87SMinwoo Im if (!nvmeq->qid) 3070f0d2c87SMinwoo Im return; 3080f0d2c87SMinwoo Im 3090f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3100f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3110f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3120f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3130f0d2c87SMinwoo Im } 3140f0d2c87SMinwoo Im 315f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 316f9f38e33SHelen Koike { 317f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3180f0d2c87SMinwoo Im unsigned int i; 319f9f38e33SHelen Koike 320f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 321f9f38e33SHelen Koike return; 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 324f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 325f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 326f9f38e33SHelen Koike 327f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3289bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 329f9f38e33SHelen Koike /* Free memory and continue on */ 330f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3310f0d2c87SMinwoo Im 3320f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3330f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 334f9f38e33SHelen Koike } 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 338f9f38e33SHelen Koike { 339f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 343f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 344f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 345f9f38e33SHelen Koike { 346f9f38e33SHelen Koike if (dbbuf_db) { 347f9f38e33SHelen Koike u16 old_value; 348f9f38e33SHelen Koike 349f9f38e33SHelen Koike /* 350f9f38e33SHelen Koike * Ensure that the queue is written before updating 351f9f38e33SHelen Koike * the doorbell in memory 352f9f38e33SHelen Koike */ 353f9f38e33SHelen Koike wmb(); 354f9f38e33SHelen Koike 355f9f38e33SHelen Koike old_value = *dbbuf_db; 356f9f38e33SHelen Koike *dbbuf_db = value; 357f9f38e33SHelen Koike 358f1ed3df2SMichal Wnukowski /* 359f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 360f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 361f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 362f1ed3df2SMichal Wnukowski * the doorbell. 363f1ed3df2SMichal Wnukowski */ 364f1ed3df2SMichal Wnukowski mb(); 365f1ed3df2SMichal Wnukowski 366f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 367f9f38e33SHelen Koike return false; 368f9f38e33SHelen Koike } 369f9f38e33SHelen Koike 370f9f38e33SHelen Koike return true; 37157dacad5SJay Sternberg } 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg /* 37457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37657dacad5SJay Sternberg * the I/O. 37757dacad5SJay Sternberg */ 378b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37957dacad5SJay Sternberg { 380b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3816c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38257dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38357dacad5SJay Sternberg } 38457dacad5SJay Sternberg 385a7a7cbe3SChaitanya Kulkarni /* 386a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 387a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 388a7a7cbe3SChaitanya Kulkarni */ 389b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 390f4800d6dSChristoph Hellwig { 391b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 392b13c6393SChaitanya Kulkarni PAGE_SIZE); 393f4800d6dSChristoph Hellwig } 394f4800d6dSChristoph Hellwig 395b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 39657dacad5SJay Sternberg { 397b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 398a7a7cbe3SChaitanya Kulkarni 399b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 400b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 401a7a7cbe3SChaitanya Kulkarni } 402a7a7cbe3SChaitanya Kulkarni 40357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40457dacad5SJay Sternberg unsigned int hctx_idx) 40557dacad5SJay Sternberg { 40657dacad5SJay Sternberg struct nvme_dev *dev = data; 407147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40857dacad5SJay Sternberg 40957dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 41057dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41157dacad5SJay Sternberg 41257dacad5SJay Sternberg hctx->driver_data = nvmeq; 41357dacad5SJay Sternberg return 0; 41457dacad5SJay Sternberg } 41557dacad5SJay Sternberg 41657dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41757dacad5SJay Sternberg unsigned int hctx_idx) 41857dacad5SJay Sternberg { 41957dacad5SJay Sternberg struct nvme_dev *dev = data; 420147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 42157dacad5SJay Sternberg 42257dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 42357dacad5SJay Sternberg hctx->driver_data = nvmeq; 42457dacad5SJay Sternberg return 0; 42557dacad5SJay Sternberg } 42657dacad5SJay Sternberg 427d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 428d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42957dacad5SJay Sternberg { 430d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 431f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4320350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 433147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg BUG_ON(!nvmeq); 436f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 43759e29ce6SSagi Grimberg 43859e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 439f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 44057dacad5SJay Sternberg return 0; 44157dacad5SJay Sternberg } 44257dacad5SJay Sternberg 4433b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4443b6592f7SJens Axboe { 4453b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4463b6592f7SJens Axboe if (dev->num_vecs > 1) 4473b6592f7SJens Axboe return 1; 4483b6592f7SJens Axboe 4493b6592f7SJens Axboe return 0; 4503b6592f7SJens Axboe } 4513b6592f7SJens Axboe 452dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 453dca51e78SChristoph Hellwig { 454dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4553b6592f7SJens Axboe int i, qoff, offset; 456dca51e78SChristoph Hellwig 4573b6592f7SJens Axboe offset = queue_irq_offset(dev); 4583b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4593b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4603b6592f7SJens Axboe 4613b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4623b6592f7SJens Axboe if (!map->nr_queues) { 463e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4647e849dd9SChristoph Hellwig continue; 4653b6592f7SJens Axboe } 4663b6592f7SJens Axboe 4674b04cc6aSJens Axboe /* 4684b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4694b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4704b04cc6aSJens Axboe */ 4713b6592f7SJens Axboe map->queue_offset = qoff; 472cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4733b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4744b04cc6aSJens Axboe else 4754b04cc6aSJens Axboe blk_mq_map_queues(map); 4763b6592f7SJens Axboe qoff += map->nr_queues; 4773b6592f7SJens Axboe offset += map->nr_queues; 4783b6592f7SJens Axboe } 4793b6592f7SJens Axboe 4803b6592f7SJens Axboe return 0; 481dca51e78SChristoph Hellwig } 482dca51e78SChristoph Hellwig 48338210800SKeith Busch /* 48438210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 48538210800SKeith Busch */ 48638210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 48704f3eafdSJens Axboe { 48838210800SKeith Busch if (!write_sq) { 48938210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 49038210800SKeith Busch 49138210800SKeith Busch if (next_tail == nvmeq->q_depth) 49238210800SKeith Busch next_tail = 0; 49338210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 49438210800SKeith Busch return; 49538210800SKeith Busch } 49638210800SKeith Busch 49704f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 49804f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49904f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 50038210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 50104f3eafdSJens Axboe } 50204f3eafdSJens Axboe 5033233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 5043233b94cSJens Axboe struct nvme_command *cmd) 50557dacad5SJay Sternberg { 506c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 5073233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 50890ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50990ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 51004f3eafdSJens Axboe } 51104f3eafdSJens Axboe 51204f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51304f3eafdSJens Axboe { 51404f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51504f3eafdSJens Axboe 51604f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51738210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51838210800SKeith Busch nvme_write_sq_db(nvmeq, true); 51990ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52057dacad5SJay Sternberg } 52157dacad5SJay Sternberg 522a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52357dacad5SJay Sternberg { 524f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 525a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg 528955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 529955b1b5aSMinwoo Im { 530955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53120469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 532955b1b5aSMinwoo Im unsigned int avg_seg_size; 533955b1b5aSMinwoo Im 53420469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 535955b1b5aSMinwoo Im 536253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 537955b1b5aSMinwoo Im return false; 538955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 539955b1b5aSMinwoo Im return false; 540955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 541955b1b5aSMinwoo Im return false; 542955b1b5aSMinwoo Im return true; 543955b1b5aSMinwoo Im } 544955b1b5aSMinwoo Im 5459275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54657dacad5SJay Sternberg { 5476c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5489275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5499275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 55057dacad5SJay Sternberg int i; 55157dacad5SJay Sternberg 5529275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5539275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5549275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5559275c206SChristoph Hellwig 5569275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5579275c206SChristoph Hellwig dma_addr = next_dma_addr; 558dff824b2SChristoph Hellwig } 5599275c206SChristoph Hellwig } 5609275c206SChristoph Hellwig 5619275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5629275c206SChristoph Hellwig { 5639275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5649275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5659275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5669275c206SChristoph Hellwig int i; 5679275c206SChristoph Hellwig 5689275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5699275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5709275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5719275c206SChristoph Hellwig 5729275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5739275c206SChristoph Hellwig dma_addr = next_dma_addr; 5749275c206SChristoph Hellwig } 5759275c206SChristoph Hellwig } 5769275c206SChristoph Hellwig 5779275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5789275c206SChristoph Hellwig { 5799275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 580dff824b2SChristoph Hellwig 5817f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5827f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5837f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5847f73eac3SLogan Gunthorpe else 585dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5869275c206SChristoph Hellwig } 5877fe07d14SChristoph Hellwig 5889275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5899275c206SChristoph Hellwig { 5909275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5917fe07d14SChristoph Hellwig 5929275c206SChristoph Hellwig if (iod->dma_len) { 5939275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5949275c206SChristoph Hellwig rq_dma_dir(req)); 5959275c206SChristoph Hellwig return; 5969275c206SChristoph Hellwig } 5979275c206SChristoph Hellwig 5989275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 5999275c206SChristoph Hellwig 6009275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 60157dacad5SJay Sternberg if (iod->npages == 0) 602a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6039275c206SChristoph Hellwig iod->first_dma); 6049275c206SChristoph Hellwig else if (iod->use_sgl) 6059275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6069275c206SChristoph Hellwig else 6079275c206SChristoph Hellwig nvme_free_prps(dev, req); 608943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 60957dacad5SJay Sternberg } 61057dacad5SJay Sternberg 611d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 612d0877473SKeith Busch { 613d0877473SKeith Busch int i; 614d0877473SKeith Busch struct scatterlist *sg; 615d0877473SKeith Busch 616d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 617d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 618d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 619d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 620d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 621d0877473SKeith Busch sg_dma_len(sg)); 622d0877473SKeith Busch } 623d0877473SKeith Busch } 624d0877473SKeith Busch 625a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 626a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62757dacad5SJay Sternberg { 628f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 62957dacad5SJay Sternberg struct dma_pool *pool; 630b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63157dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63257dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63357dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6346c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63557dacad5SJay Sternberg __le64 *prp_list; 636a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63757dacad5SJay Sternberg dma_addr_t prp_dma; 63857dacad5SJay Sternberg int nprps, i; 63957dacad5SJay Sternberg 6406c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6415228b328SJan H. Schönherr if (length <= 0) { 6425228b328SJan H. Schönherr iod->first_dma = 0; 643a7a7cbe3SChaitanya Kulkarni goto done; 6445228b328SJan H. Schönherr } 64557dacad5SJay Sternberg 6466c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 64757dacad5SJay Sternberg if (dma_len) { 6486c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 64957dacad5SJay Sternberg } else { 65057dacad5SJay Sternberg sg = sg_next(sg); 65157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65357dacad5SJay Sternberg } 65457dacad5SJay Sternberg 6556c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65657dacad5SJay Sternberg iod->first_dma = dma_addr; 657a7a7cbe3SChaitanya Kulkarni goto done; 65857dacad5SJay Sternberg } 65957dacad5SJay Sternberg 6606c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 66157dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66257dacad5SJay Sternberg pool = dev->prp_small_pool; 66357dacad5SJay Sternberg iod->npages = 0; 66457dacad5SJay Sternberg } else { 66557dacad5SJay Sternberg pool = dev->prp_page_pool; 66657dacad5SJay Sternberg iod->npages = 1; 66757dacad5SJay Sternberg } 66857dacad5SJay Sternberg 66969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67057dacad5SJay Sternberg if (!prp_list) { 67157dacad5SJay Sternberg iod->first_dma = dma_addr; 67257dacad5SJay Sternberg iod->npages = -1; 67386eea289SKeith Busch return BLK_STS_RESOURCE; 67457dacad5SJay Sternberg } 67557dacad5SJay Sternberg list[0] = prp_list; 67657dacad5SJay Sternberg iod->first_dma = prp_dma; 67757dacad5SJay Sternberg i = 0; 67857dacad5SJay Sternberg for (;;) { 6796c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 68057dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68257dacad5SJay Sternberg if (!prp_list) 683fa073216SChristoph Hellwig goto free_prps; 68457dacad5SJay Sternberg list[iod->npages++] = prp_list; 68557dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68657dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68757dacad5SJay Sternberg i = 1; 68857dacad5SJay Sternberg } 68957dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6906c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6916c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6926c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69357dacad5SJay Sternberg if (length <= 0) 69457dacad5SJay Sternberg break; 69557dacad5SJay Sternberg if (dma_len > 0) 69657dacad5SJay Sternberg continue; 69786eea289SKeith Busch if (unlikely(dma_len < 0)) 69886eea289SKeith Busch goto bad_sgl; 69957dacad5SJay Sternberg sg = sg_next(sg); 70057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70257dacad5SJay Sternberg } 703a7a7cbe3SChaitanya Kulkarni done: 704a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 705a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70686eea289SKeith Busch return BLK_STS_OK; 707fa073216SChristoph Hellwig free_prps: 708fa073216SChristoph Hellwig nvme_free_prps(dev, req); 709fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 71086eea289SKeith Busch bad_sgl: 711d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 712d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 713d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71486eea289SKeith Busch return BLK_STS_IOERR; 71557dacad5SJay Sternberg } 71657dacad5SJay Sternberg 717a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 718a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 719a7a7cbe3SChaitanya Kulkarni { 720a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 721a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 722a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 723a7a7cbe3SChaitanya Kulkarni } 724a7a7cbe3SChaitanya Kulkarni 725a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 726a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 727a7a7cbe3SChaitanya Kulkarni { 728a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 729a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 730a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 731a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 732a7a7cbe3SChaitanya Kulkarni } else { 733a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 734a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 735a7a7cbe3SChaitanya Kulkarni } 736a7a7cbe3SChaitanya Kulkarni } 737a7a7cbe3SChaitanya Kulkarni 738a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 739b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 740a7a7cbe3SChaitanya Kulkarni { 741a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 742a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 743a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 744a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 745a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 746b0f2853bSChristoph Hellwig int i = 0; 747a7a7cbe3SChaitanya Kulkarni 748a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 749a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 750a7a7cbe3SChaitanya Kulkarni 751b0f2853bSChristoph Hellwig if (entries == 1) { 752a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 753a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 754a7a7cbe3SChaitanya Kulkarni } 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 757a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 758a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 759a7a7cbe3SChaitanya Kulkarni } else { 760a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 761a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 762a7a7cbe3SChaitanya Kulkarni } 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 765a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 766a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 767a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 768a7a7cbe3SChaitanya Kulkarni } 769a7a7cbe3SChaitanya Kulkarni 770a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 771a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 774a7a7cbe3SChaitanya Kulkarni 775a7a7cbe3SChaitanya Kulkarni do { 776a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 777a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 778a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 779a7a7cbe3SChaitanya Kulkarni 780a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 781a7a7cbe3SChaitanya Kulkarni if (!sg_list) 782fa073216SChristoph Hellwig goto free_sgls; 783a7a7cbe3SChaitanya Kulkarni 784a7a7cbe3SChaitanya Kulkarni i = 0; 785a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 786a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 787a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 788a7a7cbe3SChaitanya Kulkarni } 789a7a7cbe3SChaitanya Kulkarni 790a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 791a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 792b0f2853bSChristoph Hellwig } while (--entries > 0); 793a7a7cbe3SChaitanya Kulkarni 794a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 795fa073216SChristoph Hellwig free_sgls: 796fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 797fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 798a7a7cbe3SChaitanya Kulkarni } 799a7a7cbe3SChaitanya Kulkarni 800dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 801dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 802dff824b2SChristoph Hellwig struct bio_vec *bv) 803dff824b2SChristoph Hellwig { 804dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8056c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8066c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 807dff824b2SChristoph Hellwig 808dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 809dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 810dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 811dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 812dff824b2SChristoph Hellwig 813dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 814dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 815dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 816359c1f88SBaolin Wang return BLK_STS_OK; 817dff824b2SChristoph Hellwig } 818dff824b2SChristoph Hellwig 81929791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82029791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82129791057SChristoph Hellwig struct bio_vec *bv) 82229791057SChristoph Hellwig { 82329791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82429791057SChristoph Hellwig 82529791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82629791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 82729791057SChristoph Hellwig return BLK_STS_RESOURCE; 82829791057SChristoph Hellwig iod->dma_len = bv->bv_len; 82929791057SChristoph Hellwig 830049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 83129791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83229791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83329791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 834359c1f88SBaolin Wang return BLK_STS_OK; 83529791057SChristoph Hellwig } 83629791057SChristoph Hellwig 837fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 838b131c61dSChristoph Hellwig struct nvme_command *cmnd) 83957dacad5SJay Sternberg { 840f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84170479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 842b0f2853bSChristoph Hellwig int nr_mapped; 84357dacad5SJay Sternberg 844dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 845dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 846dff824b2SChristoph Hellwig 847dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8486c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 849dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 850dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85129791057SChristoph Hellwig 852e51183beSNiklas Cassel if (iod->nvmeq->qid && sgl_threshold && 853253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 85429791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85529791057SChristoph Hellwig &cmnd->rw, &bv); 856dff824b2SChristoph Hellwig } 857dff824b2SChristoph Hellwig } 858dff824b2SChristoph Hellwig 859dff824b2SChristoph Hellwig iod->dma_len = 0; 8609b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8619b048119SChristoph Hellwig if (!iod->sg) 8629b048119SChristoph Hellwig return BLK_STS_RESOURCE; 863f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86470479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 865ba1ca37eSChristoph Hellwig if (!iod->nents) 866fa073216SChristoph Hellwig goto out_free_sg; 867ba1ca37eSChristoph Hellwig 868e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8692b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8702b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 871e0596ab2SLogan Gunthorpe else 872e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87370479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 874b0f2853bSChristoph Hellwig if (!nr_mapped) 875fa073216SChristoph Hellwig goto out_free_sg; 876ba1ca37eSChristoph Hellwig 87770479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 878955b1b5aSMinwoo Im if (iod->use_sgl) 879b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 880a7a7cbe3SChaitanya Kulkarni else 881a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8824aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 883fa073216SChristoph Hellwig goto out_unmap_sg; 884fa073216SChristoph Hellwig return BLK_STS_OK; 885fa073216SChristoph Hellwig 886fa073216SChristoph Hellwig out_unmap_sg: 887fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 888fa073216SChristoph Hellwig out_free_sg: 889fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 890ba1ca37eSChristoph Hellwig return ret; 89157dacad5SJay Sternberg } 89257dacad5SJay Sternberg 8934aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8944aedb705SChristoph Hellwig struct nvme_command *cmnd) 8954aedb705SChristoph Hellwig { 8964aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8974aedb705SChristoph Hellwig 8984aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8994aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9004aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9014aedb705SChristoph Hellwig return BLK_STS_IOERR; 9024aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 903359c1f88SBaolin Wang return BLK_STS_OK; 9044aedb705SChristoph Hellwig } 9054aedb705SChristoph Hellwig 90662451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 90762451a2bSJens Axboe { 90862451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 90962451a2bSJens Axboe blk_status_t ret; 91062451a2bSJens Axboe 91162451a2bSJens Axboe iod->aborted = 0; 91262451a2bSJens Axboe iod->npages = -1; 91362451a2bSJens Axboe iod->nents = 0; 91462451a2bSJens Axboe 91562451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 91662451a2bSJens Axboe if (ret) 91762451a2bSJens Axboe return ret; 91862451a2bSJens Axboe 91962451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 92062451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 92162451a2bSJens Axboe if (ret) 92262451a2bSJens Axboe goto out_free_cmd; 92362451a2bSJens Axboe } 92462451a2bSJens Axboe 92562451a2bSJens Axboe if (blk_integrity_rq(req)) { 92662451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 92762451a2bSJens Axboe if (ret) 92862451a2bSJens Axboe goto out_unmap_data; 92962451a2bSJens Axboe } 93062451a2bSJens Axboe 93162451a2bSJens Axboe blk_mq_start_request(req); 93262451a2bSJens Axboe return BLK_STS_OK; 93362451a2bSJens Axboe out_unmap_data: 93462451a2bSJens Axboe nvme_unmap_data(dev, req); 93562451a2bSJens Axboe out_free_cmd: 93662451a2bSJens Axboe nvme_cleanup_cmd(req); 93762451a2bSJens Axboe return ret; 93862451a2bSJens Axboe } 93962451a2bSJens Axboe 94057dacad5SJay Sternberg /* 94157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 94257dacad5SJay Sternberg */ 943fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 94457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 94557dacad5SJay Sternberg { 94657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 94757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 94857dacad5SJay Sternberg struct request *req = bd->rq; 9499b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 950ebe6d874SChristoph Hellwig blk_status_t ret; 95157dacad5SJay Sternberg 952d1f06f4aSJens Axboe /* 953d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 954d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 955d1f06f4aSJens Axboe */ 9564e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 957d1f06f4aSJens Axboe return BLK_STS_IOERR; 958d1f06f4aSJens Axboe 95962451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 960d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 961d4060d2bSTao Chiu 96262451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 96362451a2bSJens Axboe if (unlikely(ret)) 964f4800d6dSChristoph Hellwig return ret; 9653233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9663233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9673233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9683233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 969fc17b653SChristoph Hellwig return BLK_STS_OK; 97057dacad5SJay Sternberg } 97157dacad5SJay Sternberg 972*d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 973*d62cbcf6SJens Axboe { 974*d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 975*d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 976*d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 977*d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 978*d62cbcf6SJens Axboe 979*d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 980*d62cbcf6SJens Axboe } 981*d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 982*d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 983*d62cbcf6SJens Axboe } 984*d62cbcf6SJens Axboe 985*d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 986*d62cbcf6SJens Axboe { 987*d62cbcf6SJens Axboe /* 988*d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 989*d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 990*d62cbcf6SJens Axboe */ 991*d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 992*d62cbcf6SJens Axboe return false; 993*d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 994*d62cbcf6SJens Axboe return false; 995*d62cbcf6SJens Axboe 996*d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 997*d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 998*d62cbcf6SJens Axboe } 999*d62cbcf6SJens Axboe 1000*d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 1001*d62cbcf6SJens Axboe { 1002*d62cbcf6SJens Axboe struct request *req = rq_list_peek(rqlist), *prev = NULL; 1003*d62cbcf6SJens Axboe struct request *requeue_list = NULL; 1004*d62cbcf6SJens Axboe 1005*d62cbcf6SJens Axboe do { 1006*d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1007*d62cbcf6SJens Axboe 1008*d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 1009*d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 1010*d62cbcf6SJens Axboe if (prev) 1011*d62cbcf6SJens Axboe prev->rq_next = req->rq_next; 1012*d62cbcf6SJens Axboe rq_list_add(&requeue_list, req); 1013*d62cbcf6SJens Axboe } else { 1014*d62cbcf6SJens Axboe prev = req; 1015*d62cbcf6SJens Axboe } 1016*d62cbcf6SJens Axboe 1017*d62cbcf6SJens Axboe req = rq_list_next(req); 1018*d62cbcf6SJens Axboe if (!req || (prev && req->mq_hctx != prev->mq_hctx)) { 1019*d62cbcf6SJens Axboe /* detach rest of list, and submit */ 1020*d62cbcf6SJens Axboe if (prev) 1021*d62cbcf6SJens Axboe prev->rq_next = NULL; 1022*d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 1023*d62cbcf6SJens Axboe *rqlist = req; 1024*d62cbcf6SJens Axboe } 1025*d62cbcf6SJens Axboe } while (req); 1026*d62cbcf6SJens Axboe 1027*d62cbcf6SJens Axboe *rqlist = requeue_list; 1028*d62cbcf6SJens Axboe } 1029*d62cbcf6SJens Axboe 1030c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1031eee417b0SChristoph Hellwig { 1032f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 10334aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 1034eee417b0SChristoph Hellwig 10354aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 10364aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10374aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1038b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10394aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1040c234a653SJens Axboe } 1041c234a653SJens Axboe 1042c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1043c234a653SJens Axboe { 1044c234a653SJens Axboe nvme_pci_unmap_rq(req); 104577f02a7aSChristoph Hellwig nvme_complete_rq(req); 104657dacad5SJay Sternberg } 104757dacad5SJay Sternberg 1048c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1049c234a653SJens Axboe { 1050c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1051c234a653SJens Axboe } 1052c234a653SJens Axboe 1053d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1054750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1055d783e0bdSMarta Rybczynska { 105674943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 105774943d45SKeith Busch 105874943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1059d783e0bdSMarta Rybczynska } 1060d783e0bdSMarta Rybczynska 1061eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 106257dacad5SJay Sternberg { 1063eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 106457dacad5SJay Sternberg 1065eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1066eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1067eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1068eb281c82SSagi Grimberg } 1069adf68f21SChristoph Hellwig 1070cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1071cfa27356SChristoph Hellwig { 1072cfa27356SChristoph Hellwig if (!nvmeq->qid) 1073cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1074cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1075cfa27356SChristoph Hellwig } 1076cfa27356SChristoph Hellwig 1077c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1078c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 107957dacad5SJay Sternberg { 108074943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 108162df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 108257dacad5SJay Sternberg struct request *req; 1083adf68f21SChristoph Hellwig 1084adf68f21SChristoph Hellwig /* 1085adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1086adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1087adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1088adf68f21SChristoph Hellwig * for them but rather special case them here. 1089adf68f21SChristoph Hellwig */ 109062df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10917bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 109283a12fb7SSagi Grimberg cqe->status, &cqe->result); 1093a0fa9647SJens Axboe return; 109457dacad5SJay Sternberg } 109557dacad5SJay Sternberg 1096e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 109750b7c243SXianting Tian if (unlikely(!req)) { 109850b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 109950b7c243SXianting Tian "invalid id %d completed on queue %d\n", 110062df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 110150b7c243SXianting Tian return; 110250b7c243SXianting Tian } 110350b7c243SXianting Tian 1104604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1105c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1106c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1107c234a653SJens Axboe nvme_pci_complete_batch)) 1108ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 110983a12fb7SSagi Grimberg } 111057dacad5SJay Sternberg 11115cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 11125cb525c8SJens Axboe { 1113a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1114a8de6639SAlexey Dobriyan 1115a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1116920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1117e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1118a8de6639SAlexey Dobriyan } else { 1119a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1120920d13a8SSagi Grimberg } 1121a0fa9647SJens Axboe } 1122a0fa9647SJens Axboe 1123c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1124c234a653SJens Axboe struct io_comp_batch *iob) 1125a0fa9647SJens Axboe { 11261052b8acSJens Axboe int found = 0; 112783a12fb7SSagi Grimberg 11281052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11291052b8acSJens Axboe found++; 1130b69e2ef2SKeith Busch /* 1131b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1132b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1133b69e2ef2SKeith Busch */ 1134b69e2ef2SKeith Busch dma_rmb(); 1135c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11365cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 113757dacad5SJay Sternberg } 113857dacad5SJay Sternberg 1139324b494cSKeith Busch if (found) 1140eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11415cb525c8SJens Axboe return found; 114257dacad5SJay Sternberg } 114357dacad5SJay Sternberg 114457dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 114557dacad5SJay Sternberg { 114657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11474f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11485cb525c8SJens Axboe 11494f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11504f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11514f502245SJens Axboe nvme_pci_complete_batch(&iob); 115205fae499SChaitanya Kulkarni return IRQ_HANDLED; 11534f502245SJens Axboe } 115405fae499SChaitanya Kulkarni return IRQ_NONE; 115557dacad5SJay Sternberg } 115657dacad5SJay Sternberg 115757dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 115857dacad5SJay Sternberg { 115957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11604e523547SBaolin Wang 1161750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 116257dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1163d783e0bdSMarta Rybczynska return IRQ_NONE; 116457dacad5SJay Sternberg } 116557dacad5SJay Sternberg 11660b2a8a9fSChristoph Hellwig /* 1167fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11680b2a8a9fSChristoph Hellwig * Can be called from any context. 11690b2a8a9fSChristoph Hellwig */ 1170fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1171a0fa9647SJens Axboe { 11723a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1173a0fa9647SJens Axboe 1174fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1175fa059b85SKeith Busch 11763a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1177c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11783a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 117991a509f8SChristoph Hellwig } 1180442e19b7SSagi Grimberg 11815a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11827776db1cSKeith Busch { 11837776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1184dabcefabSJens Axboe bool found; 1185dabcefabSJens Axboe 1186dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1187dabcefabSJens Axboe return 0; 1188dabcefabSJens Axboe 11893a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1190c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11913a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1192dabcefabSJens Axboe 1193dabcefabSJens Axboe return found; 1194dabcefabSJens Axboe } 1195dabcefabSJens Axboe 1196ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 119757dacad5SJay Sternberg { 1198f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1199147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1200f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 120157dacad5SJay Sternberg 120257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1203ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 12043233b94cSJens Axboe 12053233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 12063233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 12073233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 12083233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 120957dacad5SJay Sternberg } 121057dacad5SJay Sternberg 121157dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 121257dacad5SJay Sternberg { 1213f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 121457dacad5SJay Sternberg 121557dacad5SJay Sternberg c.delete_queue.opcode = opcode; 121657dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 121757dacad5SJay Sternberg 12181c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 121957dacad5SJay Sternberg } 122057dacad5SJay Sternberg 122157dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1222a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 122357dacad5SJay Sternberg { 1224f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12254b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12264b04cc6aSJens Axboe 12277c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12284b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 122957dacad5SJay Sternberg 123057dacad5SJay Sternberg /* 123116772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 123257dacad5SJay Sternberg * is attached to the request. 123357dacad5SJay Sternberg */ 123457dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 123557dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 123657dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 123757dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 123857dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1239a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 124057dacad5SJay Sternberg 12411c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 124257dacad5SJay Sternberg } 124357dacad5SJay Sternberg 124457dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 124557dacad5SJay Sternberg struct nvme_queue *nvmeq) 124657dacad5SJay Sternberg { 12479abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1248f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 124981c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 125057dacad5SJay Sternberg 125157dacad5SJay Sternberg /* 12529abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12539abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12549abd68efSJens Axboe * URGENT. 12559abd68efSJens Axboe */ 12569abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12579abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12589abd68efSJens Axboe 12599abd68efSJens Axboe /* 126016772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 126157dacad5SJay Sternberg * is attached to the request. 126257dacad5SJay Sternberg */ 126357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 126457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 126557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 126657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 126757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 126857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 126957dacad5SJay Sternberg 12701c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 127157dacad5SJay Sternberg } 127257dacad5SJay Sternberg 127357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 127457dacad5SJay Sternberg { 127557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 127657dacad5SJay Sternberg } 127757dacad5SJay Sternberg 127857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 127957dacad5SJay Sternberg { 128057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 128157dacad5SJay Sternberg } 128257dacad5SJay Sternberg 12832a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 128457dacad5SJay Sternberg { 1285f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1286f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 128757dacad5SJay Sternberg 128827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 128927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1290e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1291e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 129257dacad5SJay Sternberg } 129357dacad5SJay Sternberg 1294b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1295b2a0eb1aSKeith Busch { 1296b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1297b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1298b2a0eb1aSKeith Busch */ 1299b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1300b2a0eb1aSKeith Busch 1301ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1302ad70062cSJianchao Wang switch (dev->ctrl.state) { 1303ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1304ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1305b2a0eb1aSKeith Busch return false; 1306ad70062cSJianchao Wang default: 1307ad70062cSJianchao Wang break; 1308ad70062cSJianchao Wang } 1309b2a0eb1aSKeith Busch 1310b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1311b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1312b2a0eb1aSKeith Busch */ 1313b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1314b2a0eb1aSKeith Busch return false; 1315b2a0eb1aSKeith Busch 1316b2a0eb1aSKeith Busch return true; 1317b2a0eb1aSKeith Busch } 1318b2a0eb1aSKeith Busch 1319b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1320b2a0eb1aSKeith Busch { 1321b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1322b2a0eb1aSKeith Busch u16 pci_status; 1323b2a0eb1aSKeith Busch int result; 1324b2a0eb1aSKeith Busch 1325b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1326b2a0eb1aSKeith Busch &pci_status); 1327b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1328b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1329b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1330b2a0eb1aSKeith Busch csts, pci_status); 1331b2a0eb1aSKeith Busch else 1332b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1333b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1334b2a0eb1aSKeith Busch csts, result); 1335b2a0eb1aSKeith Busch } 1336b2a0eb1aSKeith Busch 133731c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 133857dacad5SJay Sternberg { 1339f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1340f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 134157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 134257dacad5SJay Sternberg struct request *abort_req; 1343f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1344b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1345b2a0eb1aSKeith Busch 1346651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1347651438bbSWen Xiong * the recovery mechanism will surely fail. 1348651438bbSWen Xiong */ 1349651438bbSWen Xiong mb(); 1350651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1351651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1352651438bbSWen Xiong 1353b2a0eb1aSKeith Busch /* 1354b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1355b2a0eb1aSKeith Busch */ 1356b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1357b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1358b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1359d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1360db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1361b2a0eb1aSKeith Busch } 136257dacad5SJay Sternberg 136331c7c7d2SChristoph Hellwig /* 13647776db1cSKeith Busch * Did we miss an interrupt? 13657776db1cSKeith Busch */ 1366fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13675a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1368fa059b85SKeith Busch else 1369bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1370fa059b85SKeith Busch 1371bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13727776db1cSKeith Busch dev_warn(dev->ctrl.device, 13737776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13747776db1cSKeith Busch req->tag, nvmeq->qid); 1375db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13767776db1cSKeith Busch } 13777776db1cSKeith Busch 13787776db1cSKeith Busch /* 1379fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1380fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1381fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1382db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1383fd634f41SChristoph Hellwig */ 13844244140dSKeith Busch switch (dev->ctrl.state) { 13854244140dSKeith Busch case NVME_CTRL_CONNECTING: 13862036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1387df561f66SGustavo A. R. Silva fallthrough; 13882036f726SKeith Busch case NVME_CTRL_DELETING: 1389b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1390fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1391fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 139227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13937ad92f65STong Zhang nvme_dev_disable(dev, true); 1394db8c48e4SChristoph Hellwig return BLK_EH_DONE; 139539a9dd81SKeith Busch case NVME_CTRL_RESETTING: 139639a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13974244140dSKeith Busch default: 13984244140dSKeith Busch break; 1399fd634f41SChristoph Hellwig } 1400fd634f41SChristoph Hellwig 1401fd634f41SChristoph Hellwig /* 1402e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1403e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1404e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 140531c7c7d2SChristoph Hellwig */ 1406f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 14071b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 140857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 140957dacad5SJay Sternberg req->tag, nvmeq->qid); 14107ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1411a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1412d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1413e1569a16SKeith Busch 1414db8c48e4SChristoph Hellwig return BLK_EH_DONE; 141557dacad5SJay Sternberg } 141657dacad5SJay Sternberg 1417e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1418e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1419e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1420e7a2a87dSChristoph Hellwig } 14217bf7d778SKeith Busch iod->aborted = 1; 142257dacad5SJay Sternberg 142357dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 142485f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 142557dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 142657dacad5SJay Sternberg 14271b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 14281b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 142957dacad5SJay Sternberg req->tag, nvmeq->qid); 1430e7a2a87dSChristoph Hellwig 1431e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 143239dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14336bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14346bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 143531c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 143657dacad5SJay Sternberg } 143757dacad5SJay Sternberg 1438e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1439b84ba30bSChristoph Hellwig blk_execute_rq_nowait(abort_req, false, abort_endio); 144057dacad5SJay Sternberg 144157dacad5SJay Sternberg /* 144257dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 144357dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 144457dacad5SJay Sternberg * as the device then is in a faulty state. 144557dacad5SJay Sternberg */ 144657dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 144757dacad5SJay Sternberg } 144857dacad5SJay Sternberg 144957dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 145057dacad5SJay Sternberg { 14518a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 145257dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 145363223078SChristoph Hellwig if (!nvmeq->sq_cmds) 145463223078SChristoph Hellwig return; 14550f238ff5SLogan Gunthorpe 145663223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 145788a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14588a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 145963223078SChristoph Hellwig } else { 14608a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 146163223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14620f238ff5SLogan Gunthorpe } 146357dacad5SJay Sternberg } 146457dacad5SJay Sternberg 146557dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 146657dacad5SJay Sternberg { 146757dacad5SJay Sternberg int i; 146857dacad5SJay Sternberg 1469d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1470d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1471147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 147257dacad5SJay Sternberg } 147357dacad5SJay Sternberg } 147457dacad5SJay Sternberg 147557dacad5SJay Sternberg /** 147657dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 147740581d1aSBart Van Assche * @nvmeq: queue to suspend 147857dacad5SJay Sternberg */ 147957dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 148057dacad5SJay Sternberg { 14814e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 148257dacad5SJay Sternberg return 1; 148357dacad5SJay Sternberg 14844e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1485d1f06f4aSJens Axboe mb(); 148657dacad5SJay Sternberg 14874e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14881c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14896ca1d902SMing Lei nvme_stop_admin_queue(&nvmeq->dev->ctrl); 14907c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14914e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 149257dacad5SJay Sternberg return 0; 149357dacad5SJay Sternberg } 149457dacad5SJay Sternberg 14958fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14968fae268bSKeith Busch { 14978fae268bSKeith Busch int i; 14988fae268bSKeith Busch 14998fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 15008fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 15018fae268bSKeith Busch } 15028fae268bSKeith Busch 1503a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 150457dacad5SJay Sternberg { 1505147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 150657dacad5SJay Sternberg 1507a5cdb68cSKeith Busch if (shutdown) 1508a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1509a5cdb68cSKeith Busch else 1510b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 151157dacad5SJay Sternberg 1512bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 151357dacad5SJay Sternberg } 151457dacad5SJay Sternberg 1515fa46c6fbSKeith Busch /* 1516fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15179210c075SDongli Zhang * that can check this device's completion queues have synced, except 15189210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15199210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1520fa46c6fbSKeith Busch */ 1521fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1522fa46c6fbSKeith Busch { 1523fa46c6fbSKeith Busch int i; 1524fa46c6fbSKeith Busch 15259210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15269210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1527c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15289210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15299210c075SDongli Zhang } 1530fa46c6fbSKeith Busch } 1531fa46c6fbSKeith Busch 153257dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 153357dacad5SJay Sternberg int entry_size) 153457dacad5SJay Sternberg { 153557dacad5SJay Sternberg int q_depth = dev->q_depth; 15365fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15376c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 153857dacad5SJay Sternberg 153957dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 154057dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15414e523547SBaolin Wang 15426c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 154357dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 154457dacad5SJay Sternberg 154557dacad5SJay Sternberg /* 154657dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 154757dacad5SJay Sternberg * would be better to map queues in system memory with the 154857dacad5SJay Sternberg * original depth 154957dacad5SJay Sternberg */ 155057dacad5SJay Sternberg if (q_depth < 64) 155157dacad5SJay Sternberg return -ENOMEM; 155257dacad5SJay Sternberg } 155357dacad5SJay Sternberg 155457dacad5SJay Sternberg return q_depth; 155557dacad5SJay Sternberg } 155657dacad5SJay Sternberg 155757dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15588a1d09a6SBenjamin Herrenschmidt int qid) 155957dacad5SJay Sternberg { 15600f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1561815c6704SKeith Busch 15620f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15638a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1564bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15650f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15660f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 156763223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 156863223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 156963223078SChristoph Hellwig return 0; 157063223078SChristoph Hellwig } 1571bfac8e9fSAlan Mikhak 15728a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1573bfac8e9fSAlan Mikhak } 15740f238ff5SLogan Gunthorpe } 15750f238ff5SLogan Gunthorpe 15768a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 157757dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 157857dacad5SJay Sternberg if (!nvmeq->sq_cmds) 157957dacad5SJay Sternberg return -ENOMEM; 158057dacad5SJay Sternberg return 0; 158157dacad5SJay Sternberg } 158257dacad5SJay Sternberg 1583a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 158457dacad5SJay Sternberg { 1585147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 158657dacad5SJay Sternberg 158762314e40SKeith Busch if (dev->ctrl.queue_count > qid) 158862314e40SKeith Busch return 0; 158957dacad5SJay Sternberg 1590c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15918a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15928a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 159357dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 159457dacad5SJay Sternberg if (!nvmeq->cqes) 159557dacad5SJay Sternberg goto free_nvmeq; 159657dacad5SJay Sternberg 15978a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 159857dacad5SJay Sternberg goto free_cqdma; 159957dacad5SJay Sternberg 160057dacad5SJay Sternberg nvmeq->dev = dev; 16011ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 16023a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 160357dacad5SJay Sternberg nvmeq->cq_head = 0; 160457dacad5SJay Sternberg nvmeq->cq_phase = 1; 160557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 160657dacad5SJay Sternberg nvmeq->qid = qid; 1607d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 160857dacad5SJay Sternberg 1609147b27e4SSagi Grimberg return 0; 161057dacad5SJay Sternberg 161157dacad5SJay Sternberg free_cqdma: 16128a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 161357dacad5SJay Sternberg nvmeq->cq_dma_addr); 161457dacad5SJay Sternberg free_nvmeq: 1615147b27e4SSagi Grimberg return -ENOMEM; 161657dacad5SJay Sternberg } 161757dacad5SJay Sternberg 1618dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 161957dacad5SJay Sternberg { 16200ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16210ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16220ff199cbSChristoph Hellwig 16230ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16240ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16250ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16260ff199cbSChristoph Hellwig } else { 16270ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16280ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16290ff199cbSChristoph Hellwig } 163057dacad5SJay Sternberg } 163157dacad5SJay Sternberg 163257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 163357dacad5SJay Sternberg { 163457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 163557dacad5SJay Sternberg 163657dacad5SJay Sternberg nvmeq->sq_tail = 0; 163738210800SKeith Busch nvmeq->last_sq_tail = 0; 163857dacad5SJay Sternberg nvmeq->cq_head = 0; 163957dacad5SJay Sternberg nvmeq->cq_phase = 1; 164057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16418a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1642f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 164357dacad5SJay Sternberg dev->online_queues++; 16443a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 164557dacad5SJay Sternberg } 164657dacad5SJay Sternberg 1647e4b9852aSCasey Chen /* 1648e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1649e4b9852aSCasey Chen */ 1650e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1651e4b9852aSCasey Chen { 1652e4b9852aSCasey Chen /* 1653e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1654e4b9852aSCasey Chen */ 1655e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1656e4b9852aSCasey Chen return -ENODEV; 1657e4b9852aSCasey Chen 1658e4b9852aSCasey Chen /* 1659e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1660e4b9852aSCasey Chen */ 1661e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1662e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1663e4b9852aSCasey Chen return -ENODEV; 1664e4b9852aSCasey Chen } 1665e4b9852aSCasey Chen 1666e4b9852aSCasey Chen return 0; 1667e4b9852aSCasey Chen } 1668e4b9852aSCasey Chen 16694b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 167057dacad5SJay Sternberg { 167157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 167257dacad5SJay Sternberg int result; 16737c349ddeSKeith Busch u16 vector = 0; 167457dacad5SJay Sternberg 1675d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1676d1ed6aa1SChristoph Hellwig 167722b55601SKeith Busch /* 167822b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 167922b55601SKeith Busch * has only one vector available. 168022b55601SKeith Busch */ 16814b04cc6aSJens Axboe if (!polled) 1682a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16834b04cc6aSJens Axboe else 16847c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16854b04cc6aSJens Axboe 1686a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1687ded45505SKeith Busch if (result) 1688ded45505SKeith Busch return result; 168957dacad5SJay Sternberg 169057dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 169157dacad5SJay Sternberg if (result < 0) 1692ded45505SKeith Busch return result; 1693c80b36cdSEdmund Nadolski if (result) 169457dacad5SJay Sternberg goto release_cq; 169557dacad5SJay Sternberg 1696a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16974b04cc6aSJens Axboe 1698e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1699e4b9852aSCasey Chen if (result) 1700e4b9852aSCasey Chen return result; 1701e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 17027c349ddeSKeith Busch if (!polled) { 1703dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 170457dacad5SJay Sternberg if (result < 0) 170557dacad5SJay Sternberg goto release_sq; 17064b04cc6aSJens Axboe } 170757dacad5SJay Sternberg 17084e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1709e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171057dacad5SJay Sternberg return result; 171157dacad5SJay Sternberg 171257dacad5SJay Sternberg release_sq: 1713f25a2dfcSJianchao Wang dev->online_queues--; 1714e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171557dacad5SJay Sternberg adapter_delete_sq(dev, qid); 171657dacad5SJay Sternberg release_cq: 171757dacad5SJay Sternberg adapter_delete_cq(dev, qid); 171857dacad5SJay Sternberg return result; 171957dacad5SJay Sternberg } 172057dacad5SJay Sternberg 1721f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 172257dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 172377f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 172457dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 17250350815aSChristoph Hellwig .init_request = nvme_init_request, 172657dacad5SJay Sternberg .timeout = nvme_timeout, 172757dacad5SJay Sternberg }; 172857dacad5SJay Sternberg 1729f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1730376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1731*d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1732376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1733376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1734376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1735376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1736376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1737376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1738c6d962aeSChristoph Hellwig .poll = nvme_poll, 1739dabcefabSJens Axboe }; 1740dabcefabSJens Axboe 174157dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 174257dacad5SJay Sternberg { 17431c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 174469d9a99cSKeith Busch /* 174569d9a99cSKeith Busch * If the controller was reset during removal, it's possible 174669d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 174769d9a99cSKeith Busch * queue to flush these to completion. 174869d9a99cSKeith Busch */ 17496ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 17501c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 175157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 175257dacad5SJay Sternberg } 175357dacad5SJay Sternberg } 175457dacad5SJay Sternberg 175557dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 175657dacad5SJay Sternberg { 17571c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 175857dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 175957dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1760e3e9d50cSKeith Busch 176138dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1762dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1763d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1764d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1765d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 176657dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 176757dacad5SJay Sternberg 176857dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 176957dacad5SJay Sternberg return -ENOMEM; 177034b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 177157dacad5SJay Sternberg 17721c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 17731c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 177457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 177557dacad5SJay Sternberg return -ENOMEM; 177657dacad5SJay Sternberg } 17771c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 177857dacad5SJay Sternberg nvme_dev_remove_admin(dev); 17791c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 178057dacad5SJay Sternberg return -ENODEV; 178157dacad5SJay Sternberg } 178257dacad5SJay Sternberg } else 17836ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 178457dacad5SJay Sternberg 178557dacad5SJay Sternberg return 0; 178657dacad5SJay Sternberg } 178757dacad5SJay Sternberg 178897f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 178997f6ef64SXu Yu { 179097f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 179197f6ef64SXu Yu } 179297f6ef64SXu Yu 179397f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 179497f6ef64SXu Yu { 179597f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 179697f6ef64SXu Yu 179797f6ef64SXu Yu if (size <= dev->bar_mapped_size) 179897f6ef64SXu Yu return 0; 179997f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 180097f6ef64SXu Yu return -ENOMEM; 180197f6ef64SXu Yu if (dev->bar) 180297f6ef64SXu Yu iounmap(dev->bar); 180397f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 180497f6ef64SXu Yu if (!dev->bar) { 180597f6ef64SXu Yu dev->bar_mapped_size = 0; 180697f6ef64SXu Yu return -ENOMEM; 180797f6ef64SXu Yu } 180897f6ef64SXu Yu dev->bar_mapped_size = size; 180997f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 181097f6ef64SXu Yu 181197f6ef64SXu Yu return 0; 181297f6ef64SXu Yu } 181397f6ef64SXu Yu 181401ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 181557dacad5SJay Sternberg { 181657dacad5SJay Sternberg int result; 181757dacad5SJay Sternberg u32 aqa; 181857dacad5SJay Sternberg struct nvme_queue *nvmeq; 181957dacad5SJay Sternberg 182097f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 182197f6ef64SXu Yu if (result < 0) 182297f6ef64SXu Yu return result; 182397f6ef64SXu Yu 18248ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 182520d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 182657dacad5SJay Sternberg 18277a67cbeaSChristoph Hellwig if (dev->subsystem && 18287a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18297a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 183057dacad5SJay Sternberg 1831b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 183257dacad5SJay Sternberg if (result < 0) 183357dacad5SJay Sternberg return result; 183457dacad5SJay Sternberg 1835a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1836147b27e4SSagi Grimberg if (result) 1837147b27e4SSagi Grimberg return result; 183857dacad5SJay Sternberg 1839635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1840635333e4SMax Gurtovoy 1841147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 184257dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 184357dacad5SJay Sternberg aqa |= aqa << 16; 184457dacad5SJay Sternberg 18457a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18467a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18477a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 184857dacad5SJay Sternberg 1849c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 185057dacad5SJay Sternberg if (result) 1851d4875622SKeith Busch return result; 185257dacad5SJay Sternberg 185357dacad5SJay Sternberg nvmeq->cq_vector = 0; 1854161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1855dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 185657dacad5SJay Sternberg if (result) { 18577c349ddeSKeith Busch dev->online_queues--; 1858d4875622SKeith Busch return result; 185957dacad5SJay Sternberg } 186057dacad5SJay Sternberg 18614e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 186257dacad5SJay Sternberg return result; 186357dacad5SJay Sternberg } 186457dacad5SJay Sternberg 1865749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 186657dacad5SJay Sternberg { 18674b04cc6aSJens Axboe unsigned i, max, rw_queues; 1868749941f2SChristoph Hellwig int ret = 0; 186957dacad5SJay Sternberg 1870d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1871a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1872749941f2SChristoph Hellwig ret = -ENOMEM; 187357dacad5SJay Sternberg break; 1874749941f2SChristoph Hellwig } 1875749941f2SChristoph Hellwig } 187657dacad5SJay Sternberg 1877d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1878e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1879e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1880e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18814b04cc6aSJens Axboe } else { 18824b04cc6aSJens Axboe rw_queues = max; 18834b04cc6aSJens Axboe } 18844b04cc6aSJens Axboe 1885949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18864b04cc6aSJens Axboe bool polled = i > rw_queues; 18874b04cc6aSJens Axboe 18884b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1889d4875622SKeith Busch if (ret) 189057dacad5SJay Sternberg break; 189157dacad5SJay Sternberg } 189257dacad5SJay Sternberg 1893749941f2SChristoph Hellwig /* 1894749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18958adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18968adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1897749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1898749941f2SChristoph Hellwig */ 1899749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 190057dacad5SJay Sternberg } 190157dacad5SJay Sternberg 190288de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 190357dacad5SJay Sternberg { 190488de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 190588de4598SChristoph Hellwig 190688de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 190788de4598SChristoph Hellwig } 190888de4598SChristoph Hellwig 190988de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 191088de4598SChristoph Hellwig { 191188de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 191288de4598SChristoph Hellwig } 191388de4598SChristoph Hellwig 1914f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 191557dacad5SJay Sternberg { 191688de4598SChristoph Hellwig u64 size, offset; 191757dacad5SJay Sternberg resource_size_t bar_size; 191857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19198969f1f8SChristoph Hellwig int bar; 192057dacad5SJay Sternberg 19219fe5c59fSKeith Busch if (dev->cmb_size) 19229fe5c59fSKeith Busch return; 19239fe5c59fSKeith Busch 192420d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 192520d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 192620d3bb92SKlaus Jensen 19277a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1928f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1929f65efd6dSChristoph Hellwig return; 1930202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 193157dacad5SJay Sternberg 193288de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 193388de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19348969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19358969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 193657dacad5SJay Sternberg 193757dacad5SJay Sternberg if (offset > bar_size) 1938f65efd6dSChristoph Hellwig return; 193957dacad5SJay Sternberg 194057dacad5SJay Sternberg /* 194120d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 194220d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 194320d3bb92SKlaus Jensen */ 194420d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 194520d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 194620d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 194720d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 194820d3bb92SKlaus Jensen } 194920d3bb92SKlaus Jensen 195020d3bb92SKlaus Jensen /* 195157dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 195257dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 195357dacad5SJay Sternberg * the reported size of the BAR 195457dacad5SJay Sternberg */ 195557dacad5SJay Sternberg if (size > bar_size - offset) 195657dacad5SJay Sternberg size = bar_size - offset; 195757dacad5SJay Sternberg 19580f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19590f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19600f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1961f65efd6dSChristoph Hellwig return; 19620f238ff5SLogan Gunthorpe } 19630f238ff5SLogan Gunthorpe 196457dacad5SJay Sternberg dev->cmb_size = size; 19650f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19660f238ff5SLogan Gunthorpe 19670f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19680f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19690f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 197057dacad5SJay Sternberg } 197157dacad5SJay Sternberg 197287ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 197357dacad5SJay Sternberg { 19746c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19754033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1976f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 197787ad72a5SChristoph Hellwig int ret; 197887ad72a5SChristoph Hellwig 197987ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 198087ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 198187ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19826c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 198387ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 198487ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 198587ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 198887ad72a5SChristoph Hellwig if (ret) { 198987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199087ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 199187ad72a5SChristoph Hellwig ret, bits); 1992a5df5e79SKeith Busch } else 1993a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1994a5df5e79SKeith Busch 199587ad72a5SChristoph Hellwig return ret; 199687ad72a5SChristoph Hellwig } 199787ad72a5SChristoph Hellwig 199887ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 199987ad72a5SChristoph Hellwig { 200087ad72a5SChristoph Hellwig int i; 200187ad72a5SChristoph Hellwig 200287ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 200387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 20046c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 200587ad72a5SChristoph Hellwig 2006cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 2007cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 2008cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 200987ad72a5SChristoph Hellwig } 201087ad72a5SChristoph Hellwig 201187ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 201287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 20134033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20144033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20154033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 201687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20177e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 201887ad72a5SChristoph Hellwig } 201987ad72a5SChristoph Hellwig 202092dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 202192dc6895SChristoph Hellwig u32 chunk_size) 202287ad72a5SChristoph Hellwig { 202387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 202492dc6895SChristoph Hellwig u32 max_entries, len; 20254033f35dSChristoph Hellwig dma_addr_t descs_dma; 20262ee0e4edSDan Carpenter int i = 0; 202787ad72a5SChristoph Hellwig void **bufs; 20286fbcde66SMinwoo Im u64 size, tmp; 202987ad72a5SChristoph Hellwig 203087ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 203187ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 203287ad72a5SChristoph Hellwig max_entries = tmp; 2033044a9df1SChristoph Hellwig 2034044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2035044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2036044a9df1SChristoph Hellwig 2037750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20384033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 203987ad72a5SChristoph Hellwig if (!descs) 204087ad72a5SChristoph Hellwig goto out; 204187ad72a5SChristoph Hellwig 204287ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 204387ad72a5SChristoph Hellwig if (!bufs) 204487ad72a5SChristoph Hellwig goto out_free_descs; 204587ad72a5SChristoph Hellwig 2046244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 204787ad72a5SChristoph Hellwig dma_addr_t dma_addr; 204887ad72a5SChristoph Hellwig 204950cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 205087ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 205187ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 205287ad72a5SChristoph Hellwig if (!bufs[i]) 205387ad72a5SChristoph Hellwig break; 205487ad72a5SChristoph Hellwig 205587ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20566c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 205787ad72a5SChristoph Hellwig i++; 205887ad72a5SChristoph Hellwig } 205987ad72a5SChristoph Hellwig 206092dc6895SChristoph Hellwig if (!size) 206187ad72a5SChristoph Hellwig goto out_free_bufs; 206287ad72a5SChristoph Hellwig 206387ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 206487ad72a5SChristoph Hellwig dev->host_mem_size = size; 206587ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20664033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 206787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 206887ad72a5SChristoph Hellwig return 0; 206987ad72a5SChristoph Hellwig 207087ad72a5SChristoph Hellwig out_free_bufs: 207187ad72a5SChristoph Hellwig while (--i >= 0) { 20726c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 207387ad72a5SChristoph Hellwig 2074cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2075cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2076cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 207787ad72a5SChristoph Hellwig } 207887ad72a5SChristoph Hellwig 207987ad72a5SChristoph Hellwig kfree(bufs); 208087ad72a5SChristoph Hellwig out_free_descs: 20814033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20824033f35dSChristoph Hellwig descs_dma); 208387ad72a5SChristoph Hellwig out: 208487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 208587ad72a5SChristoph Hellwig return -ENOMEM; 208687ad72a5SChristoph Hellwig } 208787ad72a5SChristoph Hellwig 208892dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 208992dc6895SChristoph Hellwig { 20909dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20919dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20929dc54a0dSChaitanya Kulkarni u64 chunk_size; 209392dc6895SChristoph Hellwig 209492dc6895SChristoph Hellwig /* start big and work our way down */ 20959dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 209692dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 209792dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 209892dc6895SChristoph Hellwig return 0; 209992dc6895SChristoph Hellwig nvme_free_host_mem(dev); 210092dc6895SChristoph Hellwig } 210192dc6895SChristoph Hellwig } 210292dc6895SChristoph Hellwig 210392dc6895SChristoph Hellwig return -ENOMEM; 210492dc6895SChristoph Hellwig } 210592dc6895SChristoph Hellwig 21069620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 210787ad72a5SChristoph Hellwig { 210887ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 210987ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 211087ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 211187ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 21126fbcde66SMinwoo Im int ret; 211387ad72a5SChristoph Hellwig 211487ad72a5SChristoph Hellwig preferred = min(preferred, max); 211587ad72a5SChristoph Hellwig if (min > max) { 211687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 211787ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 211887ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 211987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21209620cfbaSChristoph Hellwig return 0; 212187ad72a5SChristoph Hellwig } 212287ad72a5SChristoph Hellwig 212387ad72a5SChristoph Hellwig /* 212487ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 212587ad72a5SChristoph Hellwig */ 212687ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 212787ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 212887ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 212987ad72a5SChristoph Hellwig else 213087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 213187ad72a5SChristoph Hellwig } 213287ad72a5SChristoph Hellwig 213387ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 213492dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 213592dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 213692dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21379620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 213887ad72a5SChristoph Hellwig } 213987ad72a5SChristoph Hellwig 214092dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 214192dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 214292dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 214392dc6895SChristoph Hellwig } 214492dc6895SChristoph Hellwig 21459620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21469620cfbaSChristoph Hellwig if (ret) 214787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21489620cfbaSChristoph Hellwig return ret; 214957dacad5SJay Sternberg } 215057dacad5SJay Sternberg 21510521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21520521905eSKeith Busch char *buf) 21530521905eSKeith Busch { 21540521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21550521905eSKeith Busch 21560521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21570521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21580521905eSKeith Busch } 21590521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21600521905eSKeith Busch 21611751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21621751e97aSKeith Busch char *buf) 21631751e97aSKeith Busch { 21641751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21651751e97aSKeith Busch 21661751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21671751e97aSKeith Busch } 21681751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21691751e97aSKeith Busch 21701751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21711751e97aSKeith Busch char *buf) 21721751e97aSKeith Busch { 21731751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21741751e97aSKeith Busch 21751751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21761751e97aSKeith Busch } 21771751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21781751e97aSKeith Busch 2179a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2180a5df5e79SKeith Busch char *buf) 2181a5df5e79SKeith Busch { 2182a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2183a5df5e79SKeith Busch 2184a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2185a5df5e79SKeith Busch } 2186a5df5e79SKeith Busch 2187a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2188a5df5e79SKeith Busch const char *buf, size_t count) 2189a5df5e79SKeith Busch { 2190a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2191a5df5e79SKeith Busch bool new; 2192a5df5e79SKeith Busch int ret; 2193a5df5e79SKeith Busch 2194a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2195a5df5e79SKeith Busch return -EINVAL; 2196a5df5e79SKeith Busch 2197a5df5e79SKeith Busch if (new == ndev->hmb) 2198a5df5e79SKeith Busch return count; 2199a5df5e79SKeith Busch 2200a5df5e79SKeith Busch if (new) { 2201a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2202a5df5e79SKeith Busch } else { 2203a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2204a5df5e79SKeith Busch if (!ret) 2205a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2206a5df5e79SKeith Busch } 2207a5df5e79SKeith Busch 2208a5df5e79SKeith Busch if (ret < 0) 2209a5df5e79SKeith Busch return ret; 2210a5df5e79SKeith Busch 2211a5df5e79SKeith Busch return count; 2212a5df5e79SKeith Busch } 2213a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2214a5df5e79SKeith Busch 22150521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22160521905eSKeith Busch struct attribute *a, int n) 22170521905eSKeith Busch { 22180521905eSKeith Busch struct nvme_ctrl *ctrl = 22190521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22200521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22210521905eSKeith Busch 22221751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22231751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22241751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22251751e97aSKeith Busch if (!dev->cmbsz) 22260521905eSKeith Busch return 0; 22271751e97aSKeith Busch } 2228a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2229a5df5e79SKeith Busch return 0; 2230a5df5e79SKeith Busch 22310521905eSKeith Busch return a->mode; 22320521905eSKeith Busch } 22330521905eSKeith Busch 22340521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22350521905eSKeith Busch &dev_attr_cmb.attr, 22361751e97aSKeith Busch &dev_attr_cmbloc.attr, 22371751e97aSKeith Busch &dev_attr_cmbsz.attr, 2238a5df5e79SKeith Busch &dev_attr_hmb.attr, 22390521905eSKeith Busch NULL, 22400521905eSKeith Busch }; 22410521905eSKeith Busch 22420521905eSKeith Busch static const struct attribute_group nvme_pci_attr_group = { 22430521905eSKeith Busch .attrs = nvme_pci_attrs, 22440521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22450521905eSKeith Busch }; 22460521905eSKeith Busch 2247612b7286SMing Lei /* 2248612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2249612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2250612b7286SMing Lei */ 2251612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22523b6592f7SJens Axboe { 2253612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22542a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2255c45b1fa2SMing Lei 22563b6592f7SJens Axboe /* 2257ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2258612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2259612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2260612b7286SMing Lei * 2261612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2262612b7286SMing Lei * write and read queues. 2263612b7286SMing Lei * 2264612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2265612b7286SMing Lei * queue. 22663b6592f7SJens Axboe */ 2267612b7286SMing Lei if (!nrirqs) { 2268612b7286SMing Lei nrirqs = 1; 2269612b7286SMing Lei nr_read_queues = 0; 22702a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2271612b7286SMing Lei nr_read_queues = 0; 22722a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2273612b7286SMing Lei nr_read_queues = 1; 22743b6592f7SJens Axboe } else { 22752a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22763b6592f7SJens Axboe } 2277612b7286SMing Lei 2278612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2279612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2280612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2281612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2282612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22833b6592f7SJens Axboe } 22843b6592f7SJens Axboe 22856451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22863b6592f7SJens Axboe { 22873b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22883b6592f7SJens Axboe struct irq_affinity affd = { 22893b6592f7SJens Axboe .pre_vectors = 1, 2290612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2291612b7286SMing Lei .priv = dev, 22923b6592f7SJens Axboe }; 229321cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22946451fe73SJens Axboe 22956451fe73SJens Axboe /* 229621cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 229721cc2f3fSJeffle Xu * left over for non-polled I/O. 22986451fe73SJens Axboe */ 229921cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 230021cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 23013b6592f7SJens Axboe 230221cc2f3fSJeffle Xu /* 230321cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 230421cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 230521cc2f3fSJeffle Xu */ 2306612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2307612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23083b6592f7SJens Axboe 230966341331SBenjamin Herrenschmidt /* 231021cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 231121cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 231221cc2f3fSJeffle Xu * vector. 231366341331SBenjamin Herrenschmidt */ 231466341331SBenjamin Herrenschmidt irq_queues = 1; 231521cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 231621cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2317612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23183b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23193b6592f7SJens Axboe } 23203b6592f7SJens Axboe 23218fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23228fae268bSKeith Busch { 23238fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23248fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23258fae268bSKeith Busch } 23268fae268bSKeith Busch 23272a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23282a5bcfddSWeiping Zhang { 2329e3aef095SNiklas Schnelle /* 2330e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2331e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2332e3aef095SNiklas Schnelle */ 2333e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2334e3aef095SNiklas Schnelle return 1; 23352a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23362a5bcfddSWeiping Zhang } 23372a5bcfddSWeiping Zhang 233857dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 233957dacad5SJay Sternberg { 2340147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 234157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23422a5bcfddSWeiping Zhang unsigned int nr_io_queues; 234397f6ef64SXu Yu unsigned long size; 23442a5bcfddSWeiping Zhang int result; 234557dacad5SJay Sternberg 23462a5bcfddSWeiping Zhang /* 23472a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23482a5bcfddSWeiping Zhang * stable values to work with. 23492a5bcfddSWeiping Zhang */ 23502a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23512a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2352d38e9f04SBenjamin Herrenschmidt 2353ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23549a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23559a0be7abSChristoph Hellwig if (result < 0) 235657dacad5SJay Sternberg return result; 23579a0be7abSChristoph Hellwig 2358f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2359a5229050SKeith Busch return 0; 236057dacad5SJay Sternberg 2361e4b9852aSCasey Chen /* 2362e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2363e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2364e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2365e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2366e4b9852aSCasey Chen * nvme_dev_disable() path. 2367e4b9852aSCasey Chen */ 2368e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2369e4b9852aSCasey Chen if (result) 2370e4b9852aSCasey Chen return result; 2371e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2372e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23734e224106SChristoph Hellwig 23740f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 237557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 237657dacad5SJay Sternberg sizeof(struct nvme_command)); 237757dacad5SJay Sternberg if (result > 0) 237857dacad5SJay Sternberg dev->q_depth = result; 237957dacad5SJay Sternberg else 23800f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 238157dacad5SJay Sternberg } 238257dacad5SJay Sternberg 238357dacad5SJay Sternberg do { 238497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 238597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 238697f6ef64SXu Yu if (!result) 238757dacad5SJay Sternberg break; 2388e4b9852aSCasey Chen if (!--nr_io_queues) { 2389e4b9852aSCasey Chen result = -ENOMEM; 2390e4b9852aSCasey Chen goto out_unlock; 2391e4b9852aSCasey Chen } 239257dacad5SJay Sternberg } while (1); 239357dacad5SJay Sternberg adminq->q_db = dev->dbs; 239457dacad5SJay Sternberg 23958fae268bSKeith Busch retry: 239657dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2397e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23980ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 239957dacad5SJay Sternberg 240057dacad5SJay Sternberg /* 240157dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 240257dacad5SJay Sternberg * setting up the full range we need. 240357dacad5SJay Sternberg */ 2404dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 24053b6592f7SJens Axboe 24063b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2407e4b9852aSCasey Chen if (result <= 0) { 2408e4b9852aSCasey Chen result = -EIO; 2409e4b9852aSCasey Chen goto out_unlock; 2410e4b9852aSCasey Chen } 24113b6592f7SJens Axboe 241222b55601SKeith Busch dev->num_vecs = result; 24134b04cc6aSJens Axboe result = max(result - 1, 1); 2414e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 241557dacad5SJay Sternberg 241657dacad5SJay Sternberg /* 241757dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 241857dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 241957dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 242057dacad5SJay Sternberg * number of interrupts. 242157dacad5SJay Sternberg */ 2422dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24237c349ddeSKeith Busch if (result) 2424e4b9852aSCasey Chen goto out_unlock; 24254e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2426e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24278fae268bSKeith Busch 24288fae268bSKeith Busch result = nvme_create_io_queues(dev); 24298fae268bSKeith Busch if (result || dev->online_queues < 2) 24308fae268bSKeith Busch return result; 24318fae268bSKeith Busch 24328fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24338fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24348fae268bSKeith Busch nvme_disable_io_queues(dev); 2435e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2436e4b9852aSCasey Chen if (result) 2437e4b9852aSCasey Chen return result; 24388fae268bSKeith Busch nvme_suspend_io_queues(dev); 24398fae268bSKeith Busch goto retry; 24408fae268bSKeith Busch } 24418fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24428fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24438fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24448fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24458fae268bSKeith Busch return 0; 2446e4b9852aSCasey Chen out_unlock: 2447e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2448e4b9852aSCasey Chen return result; 244957dacad5SJay Sternberg } 245057dacad5SJay Sternberg 24512a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2452db3cbfffSKeith Busch { 2453db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2454db3cbfffSKeith Busch 2455db3cbfffSKeith Busch blk_mq_free_request(req); 2456d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2457db3cbfffSKeith Busch } 2458db3cbfffSKeith Busch 24592a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2460db3cbfffSKeith Busch { 2461db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2462db3cbfffSKeith Busch 2463d1ed6aa1SChristoph Hellwig if (error) 2464d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2465db3cbfffSKeith Busch 2466db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2467db3cbfffSKeith Busch } 2468db3cbfffSKeith Busch 2469db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2470db3cbfffSKeith Busch { 2471db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2472db3cbfffSKeith Busch struct request *req; 2473f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2474db3cbfffSKeith Busch 2475db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2476db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2477db3cbfffSKeith Busch 247839dfe844SChaitanya Kulkarni req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2479db3cbfffSKeith Busch if (IS_ERR(req)) 2480db3cbfffSKeith Busch return PTR_ERR(req); 2481db3cbfffSKeith Busch 2482db3cbfffSKeith Busch req->end_io_data = nvmeq; 2483db3cbfffSKeith Busch 2484d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2485b84ba30bSChristoph Hellwig blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ? 2486db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2487db3cbfffSKeith Busch return 0; 2488db3cbfffSKeith Busch } 2489db3cbfffSKeith Busch 24908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2491db3cbfffSKeith Busch { 24925271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2493db3cbfffSKeith Busch unsigned long timeout; 2494db3cbfffSKeith Busch 2495db3cbfffSKeith Busch retry: 2496dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24975271edd4SChristoph Hellwig while (nr_queues > 0) { 24985271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2499db3cbfffSKeith Busch break; 25005271edd4SChristoph Hellwig nr_queues--; 25015271edd4SChristoph Hellwig sent++; 25025271edd4SChristoph Hellwig } 2503d1ed6aa1SChristoph Hellwig while (sent) { 2504d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2505d1ed6aa1SChristoph Hellwig 2506d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25075271edd4SChristoph Hellwig timeout); 2508db3cbfffSKeith Busch if (timeout == 0) 25095271edd4SChristoph Hellwig return false; 2510d1ed6aa1SChristoph Hellwig 2511d1ed6aa1SChristoph Hellwig sent--; 25125271edd4SChristoph Hellwig if (nr_queues) 2513db3cbfffSKeith Busch goto retry; 2514db3cbfffSKeith Busch } 25155271edd4SChristoph Hellwig return true; 2516db3cbfffSKeith Busch } 2517db3cbfffSKeith Busch 25185d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 251957dacad5SJay Sternberg { 25202b1b7e78SJianchao Wang int ret; 25212b1b7e78SJianchao Wang 25225bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2523c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 252457dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 25258fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2526ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2527ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 252857dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2529d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 253061f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 253161f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2532d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 253357dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 253457dacad5SJay Sternberg dev->tagset.driver_data = dev; 253557dacad5SJay Sternberg 2536d38e9f04SBenjamin Herrenschmidt /* 2537d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2538d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2539d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2540d38e9f04SBenjamin Herrenschmidt */ 2541d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2542d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2543d38e9f04SBenjamin Herrenschmidt 25442b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 25452b1b7e78SJianchao Wang if (ret) { 25462b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25472b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25485d02a5c1SKeith Busch return; 25492b1b7e78SJianchao Wang } 25505bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2551949928c1SKeith Busch } else { 2552949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2553949928c1SKeith Busch 2554949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2555949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 255657dacad5SJay Sternberg } 2557949928c1SKeith Busch 2558e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 255957dacad5SJay Sternberg } 256057dacad5SJay Sternberg 2561b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 256257dacad5SJay Sternberg { 2563b00a726aSKeith Busch int result = -ENOMEM; 256457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25654bdf2603SFilippo Sironi int dma_address_bits = 64; 256657dacad5SJay Sternberg 256757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 256857dacad5SJay Sternberg return result; 256957dacad5SJay Sternberg 257057dacad5SJay Sternberg pci_set_master(pdev); 257157dacad5SJay Sternberg 25724bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25734bdf2603SFilippo Sironi dma_address_bits = 48; 25744bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 257557dacad5SJay Sternberg goto disable; 257657dacad5SJay Sternberg 25777a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 257857dacad5SJay Sternberg result = -ENODEV; 2579b00a726aSKeith Busch goto disable; 258057dacad5SJay Sternberg } 258157dacad5SJay Sternberg 258257dacad5SJay Sternberg /* 2583a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2584a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2585a5229050SKeith Busch * adjust this later. 258657dacad5SJay Sternberg */ 2587dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2588dca51e78SChristoph Hellwig if (result < 0) 2589dca51e78SChristoph Hellwig return result; 259057dacad5SJay Sternberg 259120d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25927a67cbeaSChristoph Hellwig 25937442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2594b27c1e68Sweiping zhang io_queue_depth); 2595aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 259620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 25977a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 25981f390c1fSStephan Günther 25991f390c1fSStephan Günther /* 260066341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260166341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 260266341331SBenjamin Herrenschmidt * so we don't bother updating it here. 260366341331SBenjamin Herrenschmidt */ 260466341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 260566341331SBenjamin Herrenschmidt dev->io_sqes = 7; 260666341331SBenjamin Herrenschmidt else 2607c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26081f390c1fSStephan Günther 26091f390c1fSStephan Günther /* 26101f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26111f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26121f390c1fSStephan Günther */ 26131f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26141f390c1fSStephan Günther dev->q_depth = 2; 26159bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26169bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26171f390c1fSStephan Günther dev->q_depth); 2618d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2619d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2621d554b5e1SMartin K. Petersen dev->q_depth = 64; 2622d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2623d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26241f390c1fSStephan Günther } 26251f390c1fSStephan Günther 2626d38e9f04SBenjamin Herrenschmidt /* 2627d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2628d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2629d38e9f04SBenjamin Herrenschmidt */ 2630d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2631d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2632d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2633d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2634d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2635d38e9f04SBenjamin Herrenschmidt } 2636d38e9f04SBenjamin Herrenschmidt 2637d38e9f04SBenjamin Herrenschmidt 2638f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2639202021c1SStephen Bates 2640a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2641a0a3408eSKeith Busch pci_save_state(pdev); 264257dacad5SJay Sternberg return 0; 264357dacad5SJay Sternberg 264457dacad5SJay Sternberg disable: 264557dacad5SJay Sternberg pci_disable_device(pdev); 264657dacad5SJay Sternberg return result; 264757dacad5SJay Sternberg } 264857dacad5SJay Sternberg 264957dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265057dacad5SJay Sternberg { 2651b00a726aSKeith Busch if (dev->bar) 2652b00a726aSKeith Busch iounmap(dev->bar); 2653a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2654b00a726aSKeith Busch } 2655b00a726aSKeith Busch 2656b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2657b00a726aSKeith Busch { 265857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 265957dacad5SJay Sternberg 2660dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 266157dacad5SJay Sternberg 2662a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2663a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 266457dacad5SJay Sternberg pci_disable_device(pdev); 266557dacad5SJay Sternberg } 2666a0a3408eSKeith Busch } 266757dacad5SJay Sternberg 2668a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 266957dacad5SJay Sternberg { 2670e43269e6SKeith Busch bool dead = true, freeze = false; 2671302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 267257dacad5SJay Sternberg 267377bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2674302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2675302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2676302ad8ccSKeith Busch 2677ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2678e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2679e43269e6SKeith Busch freeze = true; 2680302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2681e43269e6SKeith Busch } 2682302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2683302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 268457dacad5SJay Sternberg } 2685c21377f8SGabriel Krisman Bertazi 2686302ad8ccSKeith Busch /* 2687302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2688302ad8ccSKeith Busch * doing a safe shutdown. 2689302ad8ccSKeith Busch */ 2690e43269e6SKeith Busch if (!dead && shutdown && freeze) 2691302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 269287ad72a5SChristoph Hellwig 26939a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 26949a915a5bSJianchao Wang 269564ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 26968fae268bSKeith Busch nvme_disable_io_queues(dev); 2697a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 269857dacad5SJay Sternberg } 26998fae268bSKeith Busch nvme_suspend_io_queues(dev); 27008fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2701b00a726aSKeith Busch nvme_pci_disable(dev); 2702fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 270357dacad5SJay Sternberg 2704e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2705e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2706622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2707622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2708302ad8ccSKeith Busch 2709302ad8ccSKeith Busch /* 2710302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2711302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2712302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2713302ad8ccSKeith Busch */ 2714c8e9e9b7SKeith Busch if (shutdown) { 2715302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2716c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27176ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 2718c8e9e9b7SKeith Busch } 271977bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 272057dacad5SJay Sternberg } 272157dacad5SJay Sternberg 2722c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2723c1ac9a4bSKeith Busch { 2724c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2725c1ac9a4bSKeith Busch return -EBUSY; 2726c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2727c1ac9a4bSKeith Busch return 0; 2728c1ac9a4bSKeith Busch } 2729c1ac9a4bSKeith Busch 273057dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 273157dacad5SJay Sternberg { 273257dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2733c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2734c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 273557dacad5SJay Sternberg if (!dev->prp_page_pool) 273657dacad5SJay Sternberg return -ENOMEM; 273757dacad5SJay Sternberg 273857dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 273957dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 274057dacad5SJay Sternberg 256, 256, 0); 274157dacad5SJay Sternberg if (!dev->prp_small_pool) { 274257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 274357dacad5SJay Sternberg return -ENOMEM; 274457dacad5SJay Sternberg } 274557dacad5SJay Sternberg return 0; 274657dacad5SJay Sternberg } 274757dacad5SJay Sternberg 274857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 274957dacad5SJay Sternberg { 275057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275157dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 275257dacad5SJay Sternberg } 275357dacad5SJay Sternberg 2754770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2755770597ecSKeith Busch { 2756770597ecSKeith Busch if (dev->tagset.tags) 2757770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2758770597ecSKeith Busch dev->ctrl.tagset = NULL; 2759770597ecSKeith Busch } 2760770597ecSKeith Busch 27611673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 276257dacad5SJay Sternberg { 27631673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 276457dacad5SJay Sternberg 2765f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2766770597ecSKeith Busch nvme_free_tagset(dev); 27671c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 27681c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2769e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2770943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2771253fd4acSIsrael Rukshin put_device(dev->dev); 2772253fd4acSIsrael Rukshin kfree(dev->queues); 277357dacad5SJay Sternberg kfree(dev); 277457dacad5SJay Sternberg } 277557dacad5SJay Sternberg 27767c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2777f58944e2SKeith Busch { 2778c1ac9a4bSKeith Busch /* 2779c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2780c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2781c1ac9a4bSKeith Busch */ 2782c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2783d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 278469d9a99cSKeith Busch nvme_dev_disable(dev, false); 27859f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 278603e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2787f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2788f58944e2SKeith Busch } 2789f58944e2SKeith Busch 2790fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 279157dacad5SJay Sternberg { 2792d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2793d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2794a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2795e71afda4SChaitanya Kulkarni int result; 279657dacad5SJay Sternberg 27977764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 27987764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 27997764656bSZhihao Cheng dev->ctrl.state); 2800e71afda4SChaitanya Kulkarni result = -ENODEV; 2801fd634f41SChristoph Hellwig goto out; 2802e71afda4SChaitanya Kulkarni } 2803fd634f41SChristoph Hellwig 2804fd634f41SChristoph Hellwig /* 2805fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2806fd634f41SChristoph Hellwig * moving on. 2807fd634f41SChristoph Hellwig */ 2808b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2809a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2810d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2811fd634f41SChristoph Hellwig 28125c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2813b00a726aSKeith Busch result = nvme_pci_enable(dev); 281457dacad5SJay Sternberg if (result) 28154726bcf3SKeith Busch goto out_unlock; 281657dacad5SJay Sternberg 281701ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 281857dacad5SJay Sternberg if (result) 28194726bcf3SKeith Busch goto out_unlock; 282057dacad5SJay Sternberg 282157dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 282257dacad5SJay Sternberg if (result) 28234726bcf3SKeith Busch goto out_unlock; 282457dacad5SJay Sternberg 2825943e942eSJens Axboe /* 2826943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2827943e942eSJens Axboe * over a single page. 2828943e942eSJens Axboe */ 28297637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 28307637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2831943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2832a48bc520SChristoph Hellwig 2833a48bc520SChristoph Hellwig /* 2834a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2835a48bc520SChristoph Hellwig */ 2836a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 28373d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2838a48bc520SChristoph Hellwig 28395c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28405c959d73SKeith Busch 28415c959d73SKeith Busch /* 28425c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28435c959d73SKeith Busch * initializing procedure here. 28445c959d73SKeith Busch */ 28455c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28465c959d73SKeith Busch dev_warn(dev->ctrl.device, 28475c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2848cee6c269SMinwoo Im result = -EBUSY; 28495c959d73SKeith Busch goto out; 28505c959d73SKeith Busch } 2851943e942eSJens Axboe 285295093350SMax Gurtovoy /* 285395093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 285495093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 285595093350SMax Gurtovoy */ 285695093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 285795093350SMax Gurtovoy 2858f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2859ce4541f4SChristoph Hellwig if (result) 2860f58944e2SKeith Busch goto out; 2861ce4541f4SChristoph Hellwig 2862e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2863e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 28644f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 28654f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2866e286bcfcSScott Bauer else if (was_suspend) 28674f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2868e286bcfcSScott Bauer } else { 2869e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2870e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2871e286bcfcSScott Bauer } 2872a98e58e5SScott Bauer 2873f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2874f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2875f9f38e33SHelen Koike if (result) 2876f9f38e33SHelen Koike dev_warn(dev->dev, 2877f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2878f9f38e33SHelen Koike } 2879f9f38e33SHelen Koike 28809620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 28819620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28829620cfbaSChristoph Hellwig if (result < 0) 28839620cfbaSChristoph Hellwig goto out; 28849620cfbaSChristoph Hellwig } 288587ad72a5SChristoph Hellwig 288657dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 288757dacad5SJay Sternberg if (result) 2888f58944e2SKeith Busch goto out; 288957dacad5SJay Sternberg 289021f033f7SKeith Busch /* 289157dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 289257dacad5SJay Sternberg * any working I/O queue. 289357dacad5SJay Sternberg */ 289457dacad5SJay Sternberg if (dev->online_queues < 2) { 28951b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 28963b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 28975bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2898770597ecSKeith Busch nvme_free_tagset(dev); 289957dacad5SJay Sternberg } else { 290025646264SKeith Busch nvme_start_queues(&dev->ctrl); 2901302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 29025d02a5c1SKeith Busch nvme_dev_add(dev); 2903302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 290457dacad5SJay Sternberg } 290557dacad5SJay Sternberg 29062b1b7e78SJianchao Wang /* 29072b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 29082b1b7e78SJianchao Wang * recovery. 29092b1b7e78SJianchao Wang */ 29105d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 29112b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 29125d02a5c1SKeith Busch "failed to mark controller live state\n"); 2913e71afda4SChaitanya Kulkarni result = -ENODEV; 2914bb8d261eSChristoph Hellwig goto out; 2915bb8d261eSChristoph Hellwig } 291692911a55SChristoph Hellwig 29170521905eSKeith Busch if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 29180521905eSKeith Busch &nvme_pci_attr_group)) 29190521905eSKeith Busch dev->attrs_added = true; 29200521905eSKeith Busch 2921d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 292257dacad5SJay Sternberg return; 292357dacad5SJay Sternberg 29244726bcf3SKeith Busch out_unlock: 29254726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 292657dacad5SJay Sternberg out: 29277c1ce408SChaitanya Kulkarni if (result) 29287c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 29297c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 29307c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 293157dacad5SJay Sternberg } 293257dacad5SJay Sternberg 29335c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 293457dacad5SJay Sternberg { 29355c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 293657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 293757dacad5SJay Sternberg 293857dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2939921920abSKeith Busch device_release_driver(&pdev->dev); 29401673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 294157dacad5SJay Sternberg } 294257dacad5SJay Sternberg 29431c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 294457dacad5SJay Sternberg { 29451c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29461c63dc66SChristoph Hellwig return 0; 294757dacad5SJay Sternberg } 29481c63dc66SChristoph Hellwig 29495fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29505fd4ce1bSChristoph Hellwig { 29515fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29525fd4ce1bSChristoph Hellwig return 0; 29535fd4ce1bSChristoph Hellwig } 29545fd4ce1bSChristoph Hellwig 29557fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29567fd8930fSChristoph Hellwig { 29573a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29587fd8930fSChristoph Hellwig return 0; 29597fd8930fSChristoph Hellwig } 29607fd8930fSChristoph Hellwig 296197c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 296297c12223SKeith Busch { 296397c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 296497c12223SKeith Busch 29652db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 296697c12223SKeith Busch } 296797c12223SKeith Busch 29681c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29691a353d85SMing Lin .name = "pcie", 2970e439bb12SSagi Grimberg .module = THIS_MODULE, 2971e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2972e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 29731c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29745fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29757fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29761673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2977f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 297897c12223SKeith Busch .get_address = nvme_pci_get_address, 29791c63dc66SChristoph Hellwig }; 298057dacad5SJay Sternberg 2981b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2982b00a726aSKeith Busch { 2983b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2984b00a726aSKeith Busch 2985a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2986b00a726aSKeith Busch return -ENODEV; 2987b00a726aSKeith Busch 298897f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2989b00a726aSKeith Busch goto release; 2990b00a726aSKeith Busch 2991b00a726aSKeith Busch return 0; 2992b00a726aSKeith Busch release: 2993a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2994b00a726aSKeith Busch return -ENODEV; 2995b00a726aSKeith Busch } 2996b00a726aSKeith Busch 29978427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2998ff5350a8SAndy Lutomirski { 2999ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3000ff5350a8SAndy Lutomirski /* 3001ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 3002ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 3003ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3004ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3005ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 3006ff5350a8SAndy Lutomirski * laptops. 3007ff5350a8SAndy Lutomirski */ 3008ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3009ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3010ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3011ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 30128427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 30138427bbc2SKai-Heng Feng /* 30148427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 3015467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3016467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 3017467c77d4SJarosław Janik * ASUS PRIME Z370-A 30188427bbc2SKai-Heng Feng */ 30198427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3020467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3021467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30228427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30231fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30241fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30251fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30261fae37acSShyjumon N /* 30271fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30281fae37acSShyjumon N * lowest idle power with quick resume latency on 30291fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30301fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30311fae37acSShyjumon N */ 30321fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30331fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30341fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3035ff5350a8SAndy Lutomirski } 3036ff5350a8SAndy Lutomirski 3037ff5350a8SAndy Lutomirski return 0; 3038ff5350a8SAndy Lutomirski } 3039ff5350a8SAndy Lutomirski 304018119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 304118119775SKeith Busch { 304218119775SKeith Busch struct nvme_dev *dev = data; 304380f513b5SKeith Busch 3044bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 304518119775SKeith Busch flush_work(&dev->ctrl.scan_work); 304680f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 304718119775SKeith Busch } 304818119775SKeith Busch 304957dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 305057dacad5SJay Sternberg { 305157dacad5SJay Sternberg int node, result = -ENOMEM; 305257dacad5SJay Sternberg struct nvme_dev *dev; 3053ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 3054943e942eSJens Axboe size_t alloc_size; 305557dacad5SJay Sternberg 305657dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 305757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30582fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 305957dacad5SJay Sternberg 306057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 306157dacad5SJay Sternberg if (!dev) 306257dacad5SJay Sternberg return -ENOMEM; 3063147b27e4SSagi Grimberg 30642a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30652a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 30662a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 30672a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30682a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 306957dacad5SJay Sternberg if (!dev->queues) 307057dacad5SJay Sternberg goto free; 307157dacad5SJay Sternberg 307257dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 307357dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 307457dacad5SJay Sternberg 3075b00a726aSKeith Busch result = nvme_dev_map(dev); 3076b00a726aSKeith Busch if (result) 3077b00c9b7aSChristophe JAILLET goto put_pci; 3078b00a726aSKeith Busch 3079d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30805c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 308177bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 3082f3ca80fcSChristoph Hellwig 3083f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 3084f3ca80fcSChristoph Hellwig if (result) 3085b00c9b7aSChristophe JAILLET goto unmap; 3086f3ca80fcSChristoph Hellwig 30878427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 3088ff5350a8SAndy Lutomirski 30892744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3090df4f9bc4SDavid E. Box /* 3091df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3092df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3093df4f9bc4SDavid E. Box */ 3094df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3095df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3096df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3097df4f9bc4SDavid E. Box } 3098df4f9bc4SDavid E. Box 3099943e942eSJens Axboe /* 3100943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 3101943e942eSJens Axboe * command we support. 3102943e942eSJens Axboe */ 3103b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 3104943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3105943e942eSJens Axboe 3106943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3107943e942eSJens Axboe mempool_kfree, 3108943e942eSJens Axboe (void *) alloc_size, 3109943e942eSJens Axboe GFP_KERNEL, node); 3110943e942eSJens Axboe if (!dev->iod_mempool) { 3111943e942eSJens Axboe result = -ENOMEM; 3112943e942eSJens Axboe goto release_pools; 3113943e942eSJens Axboe } 3114943e942eSJens Axboe 3115b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3116b6e44b4cSKeith Busch quirks); 3117b6e44b4cSKeith Busch if (result) 3118b6e44b4cSKeith Busch goto release_mempool; 3119b6e44b4cSKeith Busch 31201b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 31211b3c47c1SSagi Grimberg 3122bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 312318119775SKeith Busch async_schedule(nvme_async_probe, dev); 31244caff8fcSSagi Grimberg 312557dacad5SJay Sternberg return 0; 312657dacad5SJay Sternberg 3127b6e44b4cSKeith Busch release_mempool: 3128b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 312957dacad5SJay Sternberg release_pools: 313057dacad5SJay Sternberg nvme_release_prp_pools(dev); 3131b00c9b7aSChristophe JAILLET unmap: 3132b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 313357dacad5SJay Sternberg put_pci: 313457dacad5SJay Sternberg put_device(dev->dev); 313557dacad5SJay Sternberg free: 313657dacad5SJay Sternberg kfree(dev->queues); 313757dacad5SJay Sternberg kfree(dev); 313857dacad5SJay Sternberg return result; 313957dacad5SJay Sternberg } 314057dacad5SJay Sternberg 3141775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 314257dacad5SJay Sternberg { 314357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3144c1ac9a4bSKeith Busch 3145c1ac9a4bSKeith Busch /* 3146c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3147c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3148c1ac9a4bSKeith Busch * with ->remove(). 3149c1ac9a4bSKeith Busch */ 3150c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3151c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3152775755edSChristoph Hellwig } 315357dacad5SJay Sternberg 3154775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3155775755edSChristoph Hellwig { 3156f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3157c1ac9a4bSKeith Busch 3158c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3159c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 316057dacad5SJay Sternberg } 316157dacad5SJay Sternberg 316257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 316357dacad5SJay Sternberg { 316457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 31654e523547SBaolin Wang 3166c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 316757dacad5SJay Sternberg } 316857dacad5SJay Sternberg 31690521905eSKeith Busch static void nvme_remove_attrs(struct nvme_dev *dev) 31700521905eSKeith Busch { 31710521905eSKeith Busch if (dev->attrs_added) 31720521905eSKeith Busch sysfs_remove_group(&dev->ctrl.device->kobj, 31730521905eSKeith Busch &nvme_pci_attr_group); 31740521905eSKeith Busch } 31750521905eSKeith Busch 3176f58944e2SKeith Busch /* 3177f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3178f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3179f58944e2SKeith Busch * order to proceed. 3180f58944e2SKeith Busch */ 318157dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 318257dacad5SJay Sternberg { 318357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 318457dacad5SJay Sternberg 3185bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 318657dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 31870ff9d4e1SKeith Busch 31886db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 31890ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 31901d39e692SKeith Busch nvme_dev_disable(dev, true); 31916db28edaSKeith Busch } 31920ff9d4e1SKeith Busch 3193d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3194d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3195d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3196a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 31970521905eSKeith Busch nvme_remove_attrs(dev); 319887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 319957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 320057dacad5SJay Sternberg nvme_free_queues(dev, 0); 320157dacad5SJay Sternberg nvme_release_prp_pools(dev); 3202b00a726aSKeith Busch nvme_dev_unmap(dev); 3203726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 320457dacad5SJay Sternberg } 320557dacad5SJay Sternberg 320657dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3207d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3208d916b1beSKeith Busch { 3209d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3210d916b1beSKeith Busch } 3211d916b1beSKeith Busch 3212d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3213d916b1beSKeith Busch { 3214d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3215d916b1beSKeith Busch } 3216d916b1beSKeith Busch 3217d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3218d916b1beSKeith Busch { 3219d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3220d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3221d916b1beSKeith Busch 32224eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3223d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3224e5ad96f3SKeith Busch goto reset; 3225e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3226e5ad96f3SKeith Busch goto reset; 3227e5ad96f3SKeith Busch 3228d916b1beSKeith Busch return 0; 3229e5ad96f3SKeith Busch reset: 3230e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3231d916b1beSKeith Busch } 3232d916b1beSKeith Busch 323357dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 323457dacad5SJay Sternberg { 323557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 323657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3237d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3238d916b1beSKeith Busch int ret = -EBUSY; 3239d916b1beSKeith Busch 32404eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32414eaefe8cSRafael J. Wysocki 3242d916b1beSKeith Busch /* 3243d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3244d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3245d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3246d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3247d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3248d916b1beSKeith Busch * device fully. 32494eaefe8cSRafael J. Wysocki * 32504eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32514eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32524eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32534eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3254d916b1beSKeith Busch */ 32554eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3256cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3257c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3258c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3259d916b1beSKeith Busch 3260d916b1beSKeith Busch nvme_start_freeze(ctrl); 3261d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3262d916b1beSKeith Busch nvme_sync_queues(ctrl); 3263d916b1beSKeith Busch 32645d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3265d916b1beSKeith Busch goto unfreeze; 3266d916b1beSKeith Busch 3267e5ad96f3SKeith Busch /* 3268e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3269e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3270e5ad96f3SKeith Busch * non-operational power state. 3271e5ad96f3SKeith Busch */ 3272e5ad96f3SKeith Busch if (ndev->hmb) { 3273e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3274e5ad96f3SKeith Busch if (ret < 0) 3275e5ad96f3SKeith Busch goto unfreeze; 3276e5ad96f3SKeith Busch } 3277e5ad96f3SKeith Busch 3278d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3279d916b1beSKeith Busch if (ret < 0) 3280d916b1beSKeith Busch goto unfreeze; 3281d916b1beSKeith Busch 32827cbb5c6fSMario Limonciello /* 32837cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 32847cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 32857cbb5c6fSMario Limonciello * want pci interfering. 32867cbb5c6fSMario Limonciello */ 32877cbb5c6fSMario Limonciello pci_save_state(pdev); 32887cbb5c6fSMario Limonciello 3289d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3290d916b1beSKeith Busch if (ret < 0) 3291d916b1beSKeith Busch goto unfreeze; 3292d916b1beSKeith Busch 3293d916b1beSKeith Busch if (ret) { 32947cbb5c6fSMario Limonciello /* discard the saved state */ 32957cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 32967cbb5c6fSMario Limonciello 3297d916b1beSKeith Busch /* 3298d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 329905d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3300d916b1beSKeith Busch */ 3301c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3302d916b1beSKeith Busch ctrl->npss = 0; 3303d916b1beSKeith Busch } 3304d916b1beSKeith Busch unfreeze: 3305d916b1beSKeith Busch nvme_unfreeze(ctrl); 3306d916b1beSKeith Busch return ret; 3307d916b1beSKeith Busch } 3308d916b1beSKeith Busch 3309d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3310d916b1beSKeith Busch { 3311d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33124e523547SBaolin Wang 3313c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 331457dacad5SJay Sternberg } 331557dacad5SJay Sternberg 3316d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 331757dacad5SJay Sternberg { 331857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 331957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 332057dacad5SJay Sternberg 3321c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 332257dacad5SJay Sternberg } 332357dacad5SJay Sternberg 332421774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3325d916b1beSKeith Busch .suspend = nvme_suspend, 3326d916b1beSKeith Busch .resume = nvme_resume, 3327d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3328d916b1beSKeith Busch .thaw = nvme_simple_resume, 3329d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3330d916b1beSKeith Busch .restore = nvme_simple_resume, 3331d916b1beSKeith Busch }; 3332d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 333357dacad5SJay Sternberg 3334a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3335a0a3408eSKeith Busch pci_channel_state_t state) 3336a0a3408eSKeith Busch { 3337a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3338a0a3408eSKeith Busch 3339a0a3408eSKeith Busch /* 3340a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3341a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3342a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3343a0a3408eSKeith Busch */ 3344a0a3408eSKeith Busch switch (state) { 3345a0a3408eSKeith Busch case pci_channel_io_normal: 3346a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3347a0a3408eSKeith Busch case pci_channel_io_frozen: 3348d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3349d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3350a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3351a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3352a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3353d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3354d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3355a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3356a0a3408eSKeith Busch } 3357a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3358a0a3408eSKeith Busch } 3359a0a3408eSKeith Busch 3360a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3361a0a3408eSKeith Busch { 3362a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3363a0a3408eSKeith Busch 33641b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3365a0a3408eSKeith Busch pci_restore_state(pdev); 3366d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3367a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3368a0a3408eSKeith Busch } 3369a0a3408eSKeith Busch 3370a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3371a0a3408eSKeith Busch { 337272cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 337372cd4cc2SKeith Busch 337472cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3375a0a3408eSKeith Busch } 3376a0a3408eSKeith Busch 337757dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 337857dacad5SJay Sternberg .error_detected = nvme_error_detected, 337957dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 338057dacad5SJay Sternberg .resume = nvme_error_resume, 3381775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3382775755edSChristoph Hellwig .reset_done = nvme_reset_done, 338357dacad5SJay Sternberg }; 338457dacad5SJay Sternberg 338557dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3386972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 338708095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3388e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3389972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 339099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3391e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3392972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 339399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3394e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3395972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3396f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3397f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 339850af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 33999abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34006c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3401ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3402ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34036299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34046299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3405540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34067b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 34077b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34085bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 34095bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 34100302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34115e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34125e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 341354adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 341454adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34158c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34168c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3417015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3418015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3419d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3420d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3421d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34227ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3423abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34247ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3425c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3426c9e95c39SClaus Stovgaard .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34276e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34286e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34296e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 343008b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 343108b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3432f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3433f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3434f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34355611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34365611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 343702ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 343802ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 343989919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 344089919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3441dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3442dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3443538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3444538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 34454bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 34464bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34474bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 34484bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34494bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 34504bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34514bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 34524bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34534bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 34544bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34554bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 34564bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 345798f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 345898f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3459124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 346066341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 346166341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3462d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3463a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3464a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 34650b85f59dSAndy Shevchenko 34660b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 346757dacad5SJay Sternberg { 0, } 346857dacad5SJay Sternberg }; 346957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 347057dacad5SJay Sternberg 347157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 347257dacad5SJay Sternberg .name = "nvme", 347357dacad5SJay Sternberg .id_table = nvme_id_table, 347457dacad5SJay Sternberg .probe = nvme_probe, 347557dacad5SJay Sternberg .remove = nvme_remove, 347657dacad5SJay Sternberg .shutdown = nvme_shutdown, 3477d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 347857dacad5SJay Sternberg .driver = { 347957dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 348057dacad5SJay Sternberg }, 3481d916b1beSKeith Busch #endif 348274d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 348357dacad5SJay Sternberg .err_handler = &nvme_err_handler, 348457dacad5SJay Sternberg }; 348557dacad5SJay Sternberg 348657dacad5SJay Sternberg static int __init nvme_init(void) 348757dacad5SJay Sternberg { 348881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 348981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 349081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3491612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 349217c33167SKeith Busch 34939a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 349457dacad5SJay Sternberg } 349557dacad5SJay Sternberg 349657dacad5SJay Sternberg static void __exit nvme_exit(void) 349757dacad5SJay Sternberg { 349857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 349903e0f3a6SMing Lei flush_workqueue(nvme_wq); 350057dacad5SJay Sternberg } 350157dacad5SJay Sternberg 350257dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 350357dacad5SJay Sternberg MODULE_LICENSE("GPL"); 350457dacad5SJay Sternberg MODULE_VERSION("1.0"); 350557dacad5SJay Sternberg module_init(nvme_init); 350657dacad5SJay Sternberg module_exit(nvme_exit); 3507