15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 21d916b1beSKeith Busch #include <linux/suspend.h> 2257dacad5SJay Sternberg #include <linux/t10-pi.h> 2357dacad5SJay Sternberg #include <linux/types.h> 249cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 25a98e58e5SScott Bauer #include <linux/sed-opal.h> 260f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2757dacad5SJay Sternberg 28604c01d5Syupeng #include "trace.h" 2957dacad5SJay Sternberg #include "nvme.h" 3057dacad5SJay Sternberg 3157dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3257dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3357dacad5SJay Sternberg 34a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35adf68f21SChristoph Hellwig 36943e942eSJens Axboe /* 37943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 38943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 39943e942eSJens Axboe */ 40943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 41943e942eSJens Axboe #define NVME_MAX_SEGS 127 42943e942eSJens Axboe 4357dacad5SJay Sternberg static int use_threaded_interrupts; 4457dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4557dacad5SJay Sternberg 4657dacad5SJay Sternberg static bool use_cmb_sqes = true; 4769f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4857dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4957dacad5SJay Sternberg 5087ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5187ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5287ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5387ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5457dacad5SJay Sternberg 55a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 56a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 57a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 58a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 59a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 60a7a7cbe3SChaitanya Kulkarni 61b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 63b27c1e68Sweiping zhang .set = io_queue_depth_set, 64b27c1e68Sweiping zhang .get = param_get_int, 65b27c1e68Sweiping zhang }; 66b27c1e68Sweiping zhang 67b27c1e68Sweiping zhang static int io_queue_depth = 1024; 68b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70b27c1e68Sweiping zhang 713b6592f7SJens Axboe static int write_queues; 72483178f3SMinwoo Im module_param(write_queues, int, 0644); 733b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 743b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 753b6592f7SJens Axboe "will share a queue set."); 763b6592f7SJens Axboe 77a232ea0eSMinwoo Im static int poll_queues; 78483178f3SMinwoo Im module_param(poll_queues, int, 0644); 794b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 804b04cc6aSJens Axboe 811c63dc66SChristoph Hellwig struct nvme_dev; 821c63dc66SChristoph Hellwig struct nvme_queue; 8357dacad5SJay Sternberg 84a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 858fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 8657dacad5SJay Sternberg 8757dacad5SJay Sternberg /* 881c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 891c63dc66SChristoph Hellwig */ 901c63dc66SChristoph Hellwig struct nvme_dev { 91147b27e4SSagi Grimberg struct nvme_queue *queues; 921c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 931c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 941c63dc66SChristoph Hellwig u32 __iomem *dbs; 951c63dc66SChristoph Hellwig struct device *dev; 961c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 971c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 981c63dc66SChristoph Hellwig unsigned online_queues; 991c63dc66SChristoph Hellwig unsigned max_qid; 100e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10122b55601SKeith Busch unsigned int num_vecs; 1021c63dc66SChristoph Hellwig int q_depth; 1031c63dc66SChristoph Hellwig u32 db_stride; 1041c63dc66SChristoph Hellwig void __iomem *bar; 10597f6ef64SXu Yu unsigned long bar_mapped_size; 1065c8809e6SChristoph Hellwig struct work_struct remove_work; 10777bf25eaSKeith Busch struct mutex shutdown_lock; 1081c63dc66SChristoph Hellwig bool subsystem; 1091c63dc66SChristoph Hellwig u64 cmb_size; 1100f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1111c63dc66SChristoph Hellwig u32 cmbsz; 112202021c1SStephen Bates u32 cmbloc; 1131c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 114d916b1beSKeith Busch u32 last_ps; 11587ad72a5SChristoph Hellwig 116943e942eSJens Axboe mempool_t *iod_mempool; 117943e942eSJens Axboe 11887ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 119f9f38e33SHelen Koike u32 *dbbuf_dbs; 120f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 121f9f38e33SHelen Koike u32 *dbbuf_eis; 122f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12387ad72a5SChristoph Hellwig 12487ad72a5SChristoph Hellwig /* host memory buffer support: */ 12587ad72a5SChristoph Hellwig u64 host_mem_size; 12687ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1274033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 12987ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13057dacad5SJay Sternberg }; 13157dacad5SJay Sternberg 132b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 133b27c1e68Sweiping zhang { 134b27c1e68Sweiping zhang int n = 0, ret; 135b27c1e68Sweiping zhang 136b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 137b27c1e68Sweiping zhang if (ret != 0 || n < 2) 138b27c1e68Sweiping zhang return -EINVAL; 139b27c1e68Sweiping zhang 140b27c1e68Sweiping zhang return param_set_int(val, kp); 141b27c1e68Sweiping zhang } 142b27c1e68Sweiping zhang 143f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 144f9f38e33SHelen Koike { 145f9f38e33SHelen Koike return qid * 2 * stride; 146f9f38e33SHelen Koike } 147f9f38e33SHelen Koike 148f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 149f9f38e33SHelen Koike { 150f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 151f9f38e33SHelen Koike } 152f9f38e33SHelen Koike 1531c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1541c63dc66SChristoph Hellwig { 1551c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1561c63dc66SChristoph Hellwig } 1571c63dc66SChristoph Hellwig 15857dacad5SJay Sternberg /* 15957dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 16057dacad5SJay Sternberg * commands and one for I/O commands). 16157dacad5SJay Sternberg */ 16257dacad5SJay Sternberg struct nvme_queue { 16357dacad5SJay Sternberg struct nvme_dev *dev; 1641ab0cd69SJens Axboe spinlock_t sq_lock; 16557dacad5SJay Sternberg struct nvme_command *sq_cmds; 1663a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1673a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 16857dacad5SJay Sternberg volatile struct nvme_completion *cqes; 16957dacad5SJay Sternberg struct blk_mq_tags **tags; 17057dacad5SJay Sternberg dma_addr_t sq_dma_addr; 17157dacad5SJay Sternberg dma_addr_t cq_dma_addr; 17257dacad5SJay Sternberg u32 __iomem *q_db; 17357dacad5SJay Sternberg u16 q_depth; 1747c349ddeSKeith Busch u16 cq_vector; 17557dacad5SJay Sternberg u16 sq_tail; 17604f3eafdSJens Axboe u16 last_sq_tail; 17757dacad5SJay Sternberg u16 cq_head; 17868fa9dbeSJens Axboe u16 last_cq_head; 17957dacad5SJay Sternberg u16 qid; 18057dacad5SJay Sternberg u8 cq_phase; 1814e224106SChristoph Hellwig unsigned long flags; 1824e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 18363223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 184d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 1857c349ddeSKeith Busch #define NVMEQ_POLLED 3 186f9f38e33SHelen Koike u32 *dbbuf_sq_db; 187f9f38e33SHelen Koike u32 *dbbuf_cq_db; 188f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 189f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 190d1ed6aa1SChristoph Hellwig struct completion delete_done; 19157dacad5SJay Sternberg }; 19257dacad5SJay Sternberg 19357dacad5SJay Sternberg /* 1949b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 1959b048119SChristoph Hellwig * 1969b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 1979b048119SChristoph Hellwig * to the actual struct scatterlist. 19871bd150cSChristoph Hellwig */ 19971bd150cSChristoph Hellwig struct nvme_iod { 200d49187e9SChristoph Hellwig struct nvme_request req; 201f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 202a7a7cbe3SChaitanya Kulkarni bool use_sgl; 203f4800d6dSChristoph Hellwig int aborted; 20471bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 20571bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 20671bd150cSChristoph Hellwig dma_addr_t first_dma; 207dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 208783b94bdSChristoph Hellwig dma_addr_t meta_dma; 209f4800d6dSChristoph Hellwig struct scatterlist *sg; 21057dacad5SJay Sternberg }; 21157dacad5SJay Sternberg 2123b6592f7SJens Axboe static unsigned int max_io_queues(void) 2133b6592f7SJens Axboe { 2144b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2153b6592f7SJens Axboe } 2163b6592f7SJens Axboe 2173b6592f7SJens Axboe static unsigned int max_queue_count(void) 2183b6592f7SJens Axboe { 2193b6592f7SJens Axboe /* IO queues + admin queue */ 2203b6592f7SJens Axboe return 1 + max_io_queues(); 2213b6592f7SJens Axboe } 2223b6592f7SJens Axboe 223f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 224f9f38e33SHelen Koike { 2253b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 226f9f38e33SHelen Koike } 227f9f38e33SHelen Koike 228f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 229f9f38e33SHelen Koike { 230f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 231f9f38e33SHelen Koike 232f9f38e33SHelen Koike if (dev->dbbuf_dbs) 233f9f38e33SHelen Koike return 0; 234f9f38e33SHelen Koike 235f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 236f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 237f9f38e33SHelen Koike GFP_KERNEL); 238f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 239f9f38e33SHelen Koike return -ENOMEM; 240f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 241f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 242f9f38e33SHelen Koike GFP_KERNEL); 243f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 244f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 245f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 246f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 247f9f38e33SHelen Koike return -ENOMEM; 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike 250f9f38e33SHelen Koike return 0; 251f9f38e33SHelen Koike } 252f9f38e33SHelen Koike 253f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 254f9f38e33SHelen Koike { 255f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 256f9f38e33SHelen Koike 257f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 258f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 260f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 261f9f38e33SHelen Koike } 262f9f38e33SHelen Koike if (dev->dbbuf_eis) { 263f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 265f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike } 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 270f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 273f9f38e33SHelen Koike return; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 276f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 277f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 278f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 279f9f38e33SHelen Koike } 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 282f9f38e33SHelen Koike { 283f9f38e33SHelen Koike struct nvme_command c; 284f9f38e33SHelen Koike 285f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 286f9f38e33SHelen Koike return; 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 289f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 290f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 291f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2949bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 295f9f38e33SHelen Koike /* Free memory and continue on */ 296f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 297f9f38e33SHelen Koike } 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike 300f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 301f9f38e33SHelen Koike { 302f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike 305f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 306f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 307f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike if (dbbuf_db) { 310f9f38e33SHelen Koike u16 old_value; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike /* 313f9f38e33SHelen Koike * Ensure that the queue is written before updating 314f9f38e33SHelen Koike * the doorbell in memory 315f9f38e33SHelen Koike */ 316f9f38e33SHelen Koike wmb(); 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike old_value = *dbbuf_db; 319f9f38e33SHelen Koike *dbbuf_db = value; 320f9f38e33SHelen Koike 321f1ed3df2SMichal Wnukowski /* 322f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 323f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 324f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 325f1ed3df2SMichal Wnukowski * the doorbell. 326f1ed3df2SMichal Wnukowski */ 327f1ed3df2SMichal Wnukowski mb(); 328f1ed3df2SMichal Wnukowski 329f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 330f9f38e33SHelen Koike return false; 331f9f38e33SHelen Koike } 332f9f38e33SHelen Koike 333f9f38e33SHelen Koike return true; 33457dacad5SJay Sternberg } 33557dacad5SJay Sternberg 33657dacad5SJay Sternberg /* 33757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 33857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 33957dacad5SJay Sternberg * the I/O. 34057dacad5SJay Sternberg */ 34157dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 34257dacad5SJay Sternberg { 3435fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3445fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 34657dacad5SJay Sternberg } 34757dacad5SJay Sternberg 348a7a7cbe3SChaitanya Kulkarni /* 349a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 350a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 351a7a7cbe3SChaitanya Kulkarni */ 352a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 353f4800d6dSChristoph Hellwig { 354a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 355f4800d6dSChristoph Hellwig } 356f4800d6dSChristoph Hellwig 357a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 358a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 35957dacad5SJay Sternberg { 360a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 361a7a7cbe3SChaitanya Kulkarni 362a7a7cbe3SChaitanya Kulkarni if (use_sgl) 363a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 364a7a7cbe3SChaitanya Kulkarni else 365a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 366a7a7cbe3SChaitanya Kulkarni 367a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 368a7a7cbe3SChaitanya Kulkarni } 369a7a7cbe3SChaitanya Kulkarni 37057dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37157dacad5SJay Sternberg unsigned int hctx_idx) 37257dacad5SJay Sternberg { 37357dacad5SJay Sternberg struct nvme_dev *dev = data; 374147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37757dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37857dacad5SJay Sternberg WARN_ON(nvmeq->tags); 37957dacad5SJay Sternberg 38057dacad5SJay Sternberg hctx->driver_data = nvmeq; 38157dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 38257dacad5SJay Sternberg return 0; 38357dacad5SJay Sternberg } 38457dacad5SJay Sternberg 38557dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38657dacad5SJay Sternberg { 38757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg nvmeq->tags = NULL; 39057dacad5SJay Sternberg } 39157dacad5SJay Sternberg 39257dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39357dacad5SJay Sternberg unsigned int hctx_idx) 39457dacad5SJay Sternberg { 39557dacad5SJay Sternberg struct nvme_dev *dev = data; 396147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39757dacad5SJay Sternberg 39857dacad5SJay Sternberg if (!nvmeq->tags) 39957dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 40057dacad5SJay Sternberg 40157dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 40257dacad5SJay Sternberg hctx->driver_data = nvmeq; 40357dacad5SJay Sternberg return 0; 40457dacad5SJay Sternberg } 40557dacad5SJay Sternberg 406d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 407d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40857dacad5SJay Sternberg { 409d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 410f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4110350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 412147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg BUG_ON(!nvmeq); 415f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41659e29ce6SSagi Grimberg 41759e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 41857dacad5SJay Sternberg return 0; 41957dacad5SJay Sternberg } 42057dacad5SJay Sternberg 4213b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4223b6592f7SJens Axboe { 4233b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4243b6592f7SJens Axboe if (dev->num_vecs > 1) 4253b6592f7SJens Axboe return 1; 4263b6592f7SJens Axboe 4273b6592f7SJens Axboe return 0; 4283b6592f7SJens Axboe } 4293b6592f7SJens Axboe 430dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 431dca51e78SChristoph Hellwig { 432dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4333b6592f7SJens Axboe int i, qoff, offset; 434dca51e78SChristoph Hellwig 4353b6592f7SJens Axboe offset = queue_irq_offset(dev); 4363b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4373b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4383b6592f7SJens Axboe 4393b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4403b6592f7SJens Axboe if (!map->nr_queues) { 441e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4427e849dd9SChristoph Hellwig continue; 4433b6592f7SJens Axboe } 4443b6592f7SJens Axboe 4454b04cc6aSJens Axboe /* 4464b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4474b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4484b04cc6aSJens Axboe */ 4493b6592f7SJens Axboe map->queue_offset = qoff; 450cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4513b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4524b04cc6aSJens Axboe else 4534b04cc6aSJens Axboe blk_mq_map_queues(map); 4543b6592f7SJens Axboe qoff += map->nr_queues; 4553b6592f7SJens Axboe offset += map->nr_queues; 4563b6592f7SJens Axboe } 4573b6592f7SJens Axboe 4583b6592f7SJens Axboe return 0; 459dca51e78SChristoph Hellwig } 460dca51e78SChristoph Hellwig 46104f3eafdSJens Axboe /* 46204f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 46304f3eafdSJens Axboe */ 46404f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 46504f3eafdSJens Axboe { 46604f3eafdSJens Axboe if (!write_sq) { 46704f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 46804f3eafdSJens Axboe 46904f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 47004f3eafdSJens Axboe next_tail = 0; 47104f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 47204f3eafdSJens Axboe return; 47304f3eafdSJens Axboe } 47404f3eafdSJens Axboe 47504f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 47604f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 47704f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 47804f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 47904f3eafdSJens Axboe } 48004f3eafdSJens Axboe 48157dacad5SJay Sternberg /** 48290ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 48357dacad5SJay Sternberg * @nvmeq: The queue to use 48457dacad5SJay Sternberg * @cmd: The command to send 48504f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 48657dacad5SJay Sternberg */ 48704f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 48804f3eafdSJens Axboe bool write_sq) 48957dacad5SJay Sternberg { 49090ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 49190ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 49290ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49390ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49404f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 49504f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 49604f3eafdSJens Axboe } 49704f3eafdSJens Axboe 49804f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 49904f3eafdSJens Axboe { 50004f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50104f3eafdSJens Axboe 50204f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50304f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50404f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 50590ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50657dacad5SJay Sternberg } 50757dacad5SJay Sternberg 508a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 50957dacad5SJay Sternberg { 510f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 511a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 51257dacad5SJay Sternberg } 51357dacad5SJay Sternberg 514955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 515955b1b5aSMinwoo Im { 516955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 51720469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 518955b1b5aSMinwoo Im unsigned int avg_seg_size; 519955b1b5aSMinwoo Im 52020469a37SKeith Busch if (nseg == 0) 52120469a37SKeith Busch return false; 52220469a37SKeith Busch 52320469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 524955b1b5aSMinwoo Im 525955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 526955b1b5aSMinwoo Im return false; 527955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 528955b1b5aSMinwoo Im return false; 529955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 530955b1b5aSMinwoo Im return false; 531955b1b5aSMinwoo Im return true; 532955b1b5aSMinwoo Im } 533955b1b5aSMinwoo Im 5347fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 53557dacad5SJay Sternberg { 536f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5377fe07d14SChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 5387fe07d14SChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 539a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 540a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 54157dacad5SJay Sternberg int i; 54257dacad5SJay Sternberg 543dff824b2SChristoph Hellwig if (iod->dma_len) { 544dff824b2SChristoph Hellwig dma_unmap_page(dev->dev, dma_addr, iod->dma_len, dma_dir); 545dff824b2SChristoph Hellwig return; 546dff824b2SChristoph Hellwig } 547dff824b2SChristoph Hellwig 548dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 549dff824b2SChristoph Hellwig 5507fe07d14SChristoph Hellwig /* P2PDMA requests do not need to be unmapped */ 5517fe07d14SChristoph Hellwig if (!is_pci_p2pdma_page(sg_page(iod->sg))) 552dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5537fe07d14SChristoph Hellwig 5547fe07d14SChristoph Hellwig 55557dacad5SJay Sternberg if (iod->npages == 0) 556a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 557a7a7cbe3SChaitanya Kulkarni dma_addr); 558a7a7cbe3SChaitanya Kulkarni 55957dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 560a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 561a7a7cbe3SChaitanya Kulkarni 562a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 563a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 564a7a7cbe3SChaitanya Kulkarni 565a7a7cbe3SChaitanya Kulkarni next_dma_addr = 566a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 567a7a7cbe3SChaitanya Kulkarni } else { 568a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 569a7a7cbe3SChaitanya Kulkarni 570a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 571a7a7cbe3SChaitanya Kulkarni } 572a7a7cbe3SChaitanya Kulkarni 573a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 574a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 57557dacad5SJay Sternberg } 57657dacad5SJay Sternberg 577943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 57857dacad5SJay Sternberg } 57957dacad5SJay Sternberg 580d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 581d0877473SKeith Busch { 582d0877473SKeith Busch int i; 583d0877473SKeith Busch struct scatterlist *sg; 584d0877473SKeith Busch 585d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 586d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 587d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 588d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 589d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 590d0877473SKeith Busch sg_dma_len(sg)); 591d0877473SKeith Busch } 592d0877473SKeith Busch } 593d0877473SKeith Busch 594a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 595a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 59657dacad5SJay Sternberg { 597f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 59857dacad5SJay Sternberg struct dma_pool *pool; 599b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 60057dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 60157dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 60257dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6035fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 60457dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 60557dacad5SJay Sternberg __le64 *prp_list; 606a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 60757dacad5SJay Sternberg dma_addr_t prp_dma; 60857dacad5SJay Sternberg int nprps, i; 60957dacad5SJay Sternberg 61057dacad5SJay Sternberg length -= (page_size - offset); 6115228b328SJan H. Schönherr if (length <= 0) { 6125228b328SJan H. Schönherr iod->first_dma = 0; 613a7a7cbe3SChaitanya Kulkarni goto done; 6145228b328SJan H. Schönherr } 61557dacad5SJay Sternberg 61657dacad5SJay Sternberg dma_len -= (page_size - offset); 61757dacad5SJay Sternberg if (dma_len) { 61857dacad5SJay Sternberg dma_addr += (page_size - offset); 61957dacad5SJay Sternberg } else { 62057dacad5SJay Sternberg sg = sg_next(sg); 62157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 62257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62357dacad5SJay Sternberg } 62457dacad5SJay Sternberg 62557dacad5SJay Sternberg if (length <= page_size) { 62657dacad5SJay Sternberg iod->first_dma = dma_addr; 627a7a7cbe3SChaitanya Kulkarni goto done; 62857dacad5SJay Sternberg } 62957dacad5SJay Sternberg 63057dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 63157dacad5SJay Sternberg if (nprps <= (256 / 8)) { 63257dacad5SJay Sternberg pool = dev->prp_small_pool; 63357dacad5SJay Sternberg iod->npages = 0; 63457dacad5SJay Sternberg } else { 63557dacad5SJay Sternberg pool = dev->prp_page_pool; 63657dacad5SJay Sternberg iod->npages = 1; 63757dacad5SJay Sternberg } 63857dacad5SJay Sternberg 63969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64057dacad5SJay Sternberg if (!prp_list) { 64157dacad5SJay Sternberg iod->first_dma = dma_addr; 64257dacad5SJay Sternberg iod->npages = -1; 64386eea289SKeith Busch return BLK_STS_RESOURCE; 64457dacad5SJay Sternberg } 64557dacad5SJay Sternberg list[0] = prp_list; 64657dacad5SJay Sternberg iod->first_dma = prp_dma; 64757dacad5SJay Sternberg i = 0; 64857dacad5SJay Sternberg for (;;) { 64957dacad5SJay Sternberg if (i == page_size >> 3) { 65057dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65257dacad5SJay Sternberg if (!prp_list) 65386eea289SKeith Busch return BLK_STS_RESOURCE; 65457dacad5SJay Sternberg list[iod->npages++] = prp_list; 65557dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 65657dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 65757dacad5SJay Sternberg i = 1; 65857dacad5SJay Sternberg } 65957dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 66057dacad5SJay Sternberg dma_len -= page_size; 66157dacad5SJay Sternberg dma_addr += page_size; 66257dacad5SJay Sternberg length -= page_size; 66357dacad5SJay Sternberg if (length <= 0) 66457dacad5SJay Sternberg break; 66557dacad5SJay Sternberg if (dma_len > 0) 66657dacad5SJay Sternberg continue; 66786eea289SKeith Busch if (unlikely(dma_len < 0)) 66886eea289SKeith Busch goto bad_sgl; 66957dacad5SJay Sternberg sg = sg_next(sg); 67057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 67257dacad5SJay Sternberg } 67357dacad5SJay Sternberg 674a7a7cbe3SChaitanya Kulkarni done: 675a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 676a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 677a7a7cbe3SChaitanya Kulkarni 67886eea289SKeith Busch return BLK_STS_OK; 67986eea289SKeith Busch 68086eea289SKeith Busch bad_sgl: 681d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 682d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 683d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 68486eea289SKeith Busch return BLK_STS_IOERR; 68557dacad5SJay Sternberg } 68657dacad5SJay Sternberg 687a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 688a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 689a7a7cbe3SChaitanya Kulkarni { 690a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 691a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 692a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 693a7a7cbe3SChaitanya Kulkarni } 694a7a7cbe3SChaitanya Kulkarni 695a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 696a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 697a7a7cbe3SChaitanya Kulkarni { 698a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 699a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 700a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 701a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 702a7a7cbe3SChaitanya Kulkarni } else { 703a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 704a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 705a7a7cbe3SChaitanya Kulkarni } 706a7a7cbe3SChaitanya Kulkarni } 707a7a7cbe3SChaitanya Kulkarni 708a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 709b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 710a7a7cbe3SChaitanya Kulkarni { 711a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 712a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 713a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 714a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 715a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 716b0f2853bSChristoph Hellwig int i = 0; 717a7a7cbe3SChaitanya Kulkarni 718a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 719a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 720a7a7cbe3SChaitanya Kulkarni 721b0f2853bSChristoph Hellwig if (entries == 1) { 722a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 723a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 724a7a7cbe3SChaitanya Kulkarni } 725a7a7cbe3SChaitanya Kulkarni 726a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 727a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 728a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 729a7a7cbe3SChaitanya Kulkarni } else { 730a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 731a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 732a7a7cbe3SChaitanya Kulkarni } 733a7a7cbe3SChaitanya Kulkarni 734a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 735a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 736a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 737a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 738a7a7cbe3SChaitanya Kulkarni } 739a7a7cbe3SChaitanya Kulkarni 740a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 741a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 742a7a7cbe3SChaitanya Kulkarni 743a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni do { 746a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 747a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 748a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 749a7a7cbe3SChaitanya Kulkarni 750a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 751a7a7cbe3SChaitanya Kulkarni if (!sg_list) 752a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni i = 0; 755a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 756a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 757a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 758a7a7cbe3SChaitanya Kulkarni } 759a7a7cbe3SChaitanya Kulkarni 760a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 761a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 762b0f2853bSChristoph Hellwig } while (--entries > 0); 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 765a7a7cbe3SChaitanya Kulkarni } 766a7a7cbe3SChaitanya Kulkarni 767dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 768dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 769dff824b2SChristoph Hellwig struct bio_vec *bv) 770dff824b2SChristoph Hellwig { 771dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 772dff824b2SChristoph Hellwig unsigned int first_prp_len = dev->ctrl.page_size - bv->bv_offset; 773dff824b2SChristoph Hellwig 774dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 775dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 776dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 777dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 778dff824b2SChristoph Hellwig 779dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 780dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 781dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 782dff824b2SChristoph Hellwig return 0; 783dff824b2SChristoph Hellwig } 784dff824b2SChristoph Hellwig 78529791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 78629791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 78729791057SChristoph Hellwig struct bio_vec *bv) 78829791057SChristoph Hellwig { 78929791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 79029791057SChristoph Hellwig 79129791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 79229791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 79329791057SChristoph Hellwig return BLK_STS_RESOURCE; 79429791057SChristoph Hellwig iod->dma_len = bv->bv_len; 79529791057SChristoph Hellwig 796049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 79729791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 79829791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 79929791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 80029791057SChristoph Hellwig return 0; 80129791057SChristoph Hellwig } 80229791057SChristoph Hellwig 803fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 804b131c61dSChristoph Hellwig struct nvme_command *cmnd) 80557dacad5SJay Sternberg { 806f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80770479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 808b0f2853bSChristoph Hellwig int nr_mapped; 80957dacad5SJay Sternberg 810dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 811dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 812dff824b2SChristoph Hellwig 813dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 814dff824b2SChristoph Hellwig if (bv.bv_offset + bv.bv_len <= dev->ctrl.page_size * 2) 815dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 816dff824b2SChristoph Hellwig &cmnd->rw, &bv); 81729791057SChristoph Hellwig 81829791057SChristoph Hellwig if (iod->nvmeq->qid && 81929791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 82029791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 82129791057SChristoph Hellwig &cmnd->rw, &bv); 822dff824b2SChristoph Hellwig } 823dff824b2SChristoph Hellwig } 824dff824b2SChristoph Hellwig 825dff824b2SChristoph Hellwig iod->dma_len = 0; 8269b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8279b048119SChristoph Hellwig if (!iod->sg) 8289b048119SChristoph Hellwig return BLK_STS_RESOURCE; 829f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 83070479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 831ba1ca37eSChristoph Hellwig if (!iod->nents) 832ba1ca37eSChristoph Hellwig goto out; 833ba1ca37eSChristoph Hellwig 834e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 835e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 83670479b71SChristoph Hellwig rq_dma_dir(req)); 837e0596ab2SLogan Gunthorpe else 838e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 83970479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 840b0f2853bSChristoph Hellwig if (!nr_mapped) 841ba1ca37eSChristoph Hellwig goto out; 842ba1ca37eSChristoph Hellwig 84370479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 844955b1b5aSMinwoo Im if (iod->use_sgl) 845b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 846a7a7cbe3SChaitanya Kulkarni else 847a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 848ba1ca37eSChristoph Hellwig out: 8494aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8507fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 851ba1ca37eSChristoph Hellwig return ret; 85257dacad5SJay Sternberg } 85357dacad5SJay Sternberg 8544aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8554aedb705SChristoph Hellwig struct nvme_command *cmnd) 8564aedb705SChristoph Hellwig { 8574aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8584aedb705SChristoph Hellwig 8594aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8604aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8614aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8624aedb705SChristoph Hellwig return BLK_STS_IOERR; 8634aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 8644aedb705SChristoph Hellwig return 0; 8654aedb705SChristoph Hellwig } 8664aedb705SChristoph Hellwig 86757dacad5SJay Sternberg /* 86857dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86957dacad5SJay Sternberg */ 870fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 87157dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 87257dacad5SJay Sternberg { 87357dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 87457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87657dacad5SJay Sternberg struct request *req = bd->rq; 8779b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 878ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 879ebe6d874SChristoph Hellwig blk_status_t ret; 88057dacad5SJay Sternberg 8819b048119SChristoph Hellwig iod->aborted = 0; 8829b048119SChristoph Hellwig iod->npages = -1; 8839b048119SChristoph Hellwig iod->nents = 0; 8849b048119SChristoph Hellwig 885d1f06f4aSJens Axboe /* 886d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 887d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 888d1f06f4aSJens Axboe */ 8894e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 890d1f06f4aSJens Axboe return BLK_STS_IOERR; 891d1f06f4aSJens Axboe 892f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 893fc17b653SChristoph Hellwig if (ret) 894f4800d6dSChristoph Hellwig return ret; 89557dacad5SJay Sternberg 896fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 897b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 898fc17b653SChristoph Hellwig if (ret) 8999b048119SChristoph Hellwig goto out_free_cmd; 900fc17b653SChristoph Hellwig } 901ba1ca37eSChristoph Hellwig 9024aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 9034aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 9044aedb705SChristoph Hellwig if (ret) 9054aedb705SChristoph Hellwig goto out_unmap_data; 9064aedb705SChristoph Hellwig } 9074aedb705SChristoph Hellwig 908aae239e1SChristoph Hellwig blk_mq_start_request(req); 90904f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 910fc17b653SChristoph Hellwig return BLK_STS_OK; 9114aedb705SChristoph Hellwig out_unmap_data: 9124aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 913f9d03f96SChristoph Hellwig out_free_cmd: 914f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 915ba1ca37eSChristoph Hellwig return ret; 91657dacad5SJay Sternberg } 91757dacad5SJay Sternberg 91877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 919eee417b0SChristoph Hellwig { 920f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9214aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 922eee417b0SChristoph Hellwig 923915f04c9SChristoph Hellwig nvme_cleanup_cmd(req); 9244aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9254aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9264aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 927b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9284aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 92977f02a7aSChristoph Hellwig nvme_complete_rq(req); 93057dacad5SJay Sternberg } 93157dacad5SJay Sternberg 932d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 933750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 934d783e0bdSMarta Rybczynska { 935750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 936750dde44SChristoph Hellwig nvmeq->cq_phase; 937d783e0bdSMarta Rybczynska } 938d783e0bdSMarta Rybczynska 939eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 94057dacad5SJay Sternberg { 941eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 94257dacad5SJay Sternberg 943eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 944eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 945eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 946eb281c82SSagi Grimberg } 947adf68f21SChristoph Hellwig 9485cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 94957dacad5SJay Sternberg { 9505cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 95157dacad5SJay Sternberg struct request *req; 952adf68f21SChristoph Hellwig 95383a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9541b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 955aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 95683a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 95783a12fb7SSagi Grimberg return; 958aae239e1SChristoph Hellwig } 959aae239e1SChristoph Hellwig 960adf68f21SChristoph Hellwig /* 961adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 962adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 963adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 964adf68f21SChristoph Hellwig * for them but rather special case them here. 965adf68f21SChristoph Hellwig */ 966adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 96738dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9687bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 96983a12fb7SSagi Grimberg cqe->status, &cqe->result); 970a0fa9647SJens Axboe return; 97157dacad5SJay Sternberg } 97257dacad5SJay Sternberg 97383a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 974604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 97583a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 97683a12fb7SSagi Grimberg } 97757dacad5SJay Sternberg 9785cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 97983a12fb7SSagi Grimberg { 9805cb525c8SJens Axboe while (start != end) { 9815cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9825cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9835cb525c8SJens Axboe start = 0; 9845cb525c8SJens Axboe } 9855cb525c8SJens Axboe } 98683a12fb7SSagi Grimberg 9875cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9885cb525c8SJens Axboe { 989dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 990920d13a8SSagi Grimberg nvmeq->cq_head = 0; 991920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 992dcca1662SHongbo Yao } else { 993dcca1662SHongbo Yao nvmeq->cq_head++; 994920d13a8SSagi Grimberg } 995a0fa9647SJens Axboe } 996a0fa9647SJens Axboe 9971052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9981052b8acSJens Axboe u16 *end, unsigned int tag) 999a0fa9647SJens Axboe { 10001052b8acSJens Axboe int found = 0; 100183a12fb7SSagi Grimberg 10025cb525c8SJens Axboe *start = nvmeq->cq_head; 10031052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10041052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10051052b8acSJens Axboe found++; 10065cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 100757dacad5SJay Sternberg } 10085cb525c8SJens Axboe *end = nvmeq->cq_head; 100957dacad5SJay Sternberg 10105cb525c8SJens Axboe if (*start != *end) 1011eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10125cb525c8SJens Axboe return found; 101357dacad5SJay Sternberg } 101457dacad5SJay Sternberg 101557dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 101657dacad5SJay Sternberg { 101757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 101868fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10195cb525c8SJens Axboe u16 start, end; 10205cb525c8SJens Axboe 10213a7afd8eSChristoph Hellwig /* 10223a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10233a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10243a7afd8eSChristoph Hellwig */ 10253a7afd8eSChristoph Hellwig rmb(); 102668fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 102768fa9dbeSJens Axboe ret = IRQ_HANDLED; 10285cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 102968fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10303a7afd8eSChristoph Hellwig wmb(); 10315cb525c8SJens Axboe 103268fa9dbeSJens Axboe if (start != end) { 10335cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10345cb525c8SJens Axboe return IRQ_HANDLED; 103557dacad5SJay Sternberg } 103657dacad5SJay Sternberg 103768fa9dbeSJens Axboe return ret; 103857dacad5SJay Sternberg } 103957dacad5SJay Sternberg 104057dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 104157dacad5SJay Sternberg { 104257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1043750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 104457dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1045d783e0bdSMarta Rybczynska return IRQ_NONE; 104657dacad5SJay Sternberg } 104757dacad5SJay Sternberg 10480b2a8a9fSChristoph Hellwig /* 10490b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10500b2a8a9fSChristoph Hellwig * Can be called from any context. 10510b2a8a9fSChristoph Hellwig */ 10520b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1053a0fa9647SJens Axboe { 10543a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10555cb525c8SJens Axboe u16 start, end; 10561052b8acSJens Axboe int found; 1057a0fa9647SJens Axboe 10583a7afd8eSChristoph Hellwig /* 10593a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10603a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10613a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10623a7afd8eSChristoph Hellwig */ 10637c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10643a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 106591a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 106691a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 106791a509f8SChristoph Hellwig } else { 10683a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10695cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10703a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 107191a509f8SChristoph Hellwig } 1072442e19b7SSagi Grimberg 10735cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1074442e19b7SSagi Grimberg return found; 1075a0fa9647SJens Axboe } 1076a0fa9647SJens Axboe 10779743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10787776db1cSKeith Busch { 10797776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1080dabcefabSJens Axboe u16 start, end; 1081dabcefabSJens Axboe bool found; 1082dabcefabSJens Axboe 1083dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1084dabcefabSJens Axboe return 0; 1085dabcefabSJens Axboe 10863a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 10879743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 10883a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1089dabcefabSJens Axboe 1090dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1091dabcefabSJens Axboe return found; 1092dabcefabSJens Axboe } 1093dabcefabSJens Axboe 1094ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 109557dacad5SJay Sternberg { 1096f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1097147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 109857dacad5SJay Sternberg struct nvme_command c; 109957dacad5SJay Sternberg 110057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110157dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1102ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 110304f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 110457dacad5SJay Sternberg } 110557dacad5SJay Sternberg 110657dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 110757dacad5SJay Sternberg { 110857dacad5SJay Sternberg struct nvme_command c; 110957dacad5SJay Sternberg 111057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111157dacad5SJay Sternberg c.delete_queue.opcode = opcode; 111257dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 111357dacad5SJay Sternberg 11141c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 111557dacad5SJay Sternberg } 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1118a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 111957dacad5SJay Sternberg { 112057dacad5SJay Sternberg struct nvme_command c; 11214b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11224b04cc6aSJens Axboe 11237c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11244b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 112557dacad5SJay Sternberg 112657dacad5SJay Sternberg /* 112716772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 112857dacad5SJay Sternberg * is attached to the request. 112957dacad5SJay Sternberg */ 113057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113157dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 113257dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 113357dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 113457dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 113557dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1136a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 113757dacad5SJay Sternberg 11381c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 113957dacad5SJay Sternberg } 114057dacad5SJay Sternberg 114157dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 114257dacad5SJay Sternberg struct nvme_queue *nvmeq) 114357dacad5SJay Sternberg { 11449abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 114557dacad5SJay Sternberg struct nvme_command c; 114681c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 114757dacad5SJay Sternberg 114857dacad5SJay Sternberg /* 11499abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11509abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11519abd68efSJens Axboe * URGENT. 11529abd68efSJens Axboe */ 11539abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11549abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11559abd68efSJens Axboe 11569abd68efSJens Axboe /* 115716772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 115857dacad5SJay Sternberg * is attached to the request. 115957dacad5SJay Sternberg */ 116057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 116157dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 116257dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 116357dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 116457dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 116557dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 116657dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 116757dacad5SJay Sternberg 11681c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116957dacad5SJay Sternberg } 117057dacad5SJay Sternberg 117157dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 117257dacad5SJay Sternberg { 117357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 117457dacad5SJay Sternberg } 117557dacad5SJay Sternberg 117657dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 117757dacad5SJay Sternberg { 117857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 117957dacad5SJay Sternberg } 118057dacad5SJay Sternberg 11812a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 118257dacad5SJay Sternberg { 1183f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1184f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 118557dacad5SJay Sternberg 118627fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 118727fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1188e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1189e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 119057dacad5SJay Sternberg } 119157dacad5SJay Sternberg 1192b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1193b2a0eb1aSKeith Busch { 1194b2a0eb1aSKeith Busch 1195b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1196b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1197b2a0eb1aSKeith Busch */ 1198b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1199b2a0eb1aSKeith Busch 1200ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1201ad70062cSJianchao Wang switch (dev->ctrl.state) { 1202ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1203ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1204b2a0eb1aSKeith Busch return false; 1205ad70062cSJianchao Wang default: 1206ad70062cSJianchao Wang break; 1207ad70062cSJianchao Wang } 1208b2a0eb1aSKeith Busch 1209b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1210b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1211b2a0eb1aSKeith Busch */ 1212b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1213b2a0eb1aSKeith Busch return false; 1214b2a0eb1aSKeith Busch 1215b2a0eb1aSKeith Busch return true; 1216b2a0eb1aSKeith Busch } 1217b2a0eb1aSKeith Busch 1218b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1219b2a0eb1aSKeith Busch { 1220b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1221b2a0eb1aSKeith Busch u16 pci_status; 1222b2a0eb1aSKeith Busch int result; 1223b2a0eb1aSKeith Busch 1224b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1225b2a0eb1aSKeith Busch &pci_status); 1226b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1227b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1228b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1229b2a0eb1aSKeith Busch csts, pci_status); 1230b2a0eb1aSKeith Busch else 1231b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1232b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1233b2a0eb1aSKeith Busch csts, result); 1234b2a0eb1aSKeith Busch } 1235b2a0eb1aSKeith Busch 123631c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 123757dacad5SJay Sternberg { 1238f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1239f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 124057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 124157dacad5SJay Sternberg struct request *abort_req; 124257dacad5SJay Sternberg struct nvme_command cmd; 1243b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1244b2a0eb1aSKeith Busch 1245651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1246651438bbSWen Xiong * the recovery mechanism will surely fail. 1247651438bbSWen Xiong */ 1248651438bbSWen Xiong mb(); 1249651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1250651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1251651438bbSWen Xiong 1252b2a0eb1aSKeith Busch /* 1253b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1254b2a0eb1aSKeith Busch */ 1255b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1256b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1257b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1258d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1259db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1260b2a0eb1aSKeith Busch } 126157dacad5SJay Sternberg 126231c7c7d2SChristoph Hellwig /* 12637776db1cSKeith Busch * Did we miss an interrupt? 12647776db1cSKeith Busch */ 12650b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12667776db1cSKeith Busch dev_warn(dev->ctrl.device, 12677776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12687776db1cSKeith Busch req->tag, nvmeq->qid); 1269db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12707776db1cSKeith Busch } 12717776db1cSKeith Busch 12727776db1cSKeith Busch /* 1273fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1274fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1275fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1276db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1277fd634f41SChristoph Hellwig */ 12784244140dSKeith Busch switch (dev->ctrl.state) { 12794244140dSKeith Busch case NVME_CTRL_CONNECTING: 12802036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 12812036f726SKeith Busch /* fall through */ 12822036f726SKeith Busch case NVME_CTRL_DELETING: 1283b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1284fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1285fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 12862036f726SKeith Busch nvme_dev_disable(dev, true); 128727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1288db8c48e4SChristoph Hellwig return BLK_EH_DONE; 128939a9dd81SKeith Busch case NVME_CTRL_RESETTING: 129039a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12914244140dSKeith Busch default: 12924244140dSKeith Busch break; 1293fd634f41SChristoph Hellwig } 1294fd634f41SChristoph Hellwig 1295fd634f41SChristoph Hellwig /* 1296e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1297e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1298e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 129931c7c7d2SChristoph Hellwig */ 1300f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13011b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 130257dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 130357dacad5SJay Sternberg req->tag, nvmeq->qid); 1304a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1305d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1306e1569a16SKeith Busch 130727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1308db8c48e4SChristoph Hellwig return BLK_EH_DONE; 130957dacad5SJay Sternberg } 131057dacad5SJay Sternberg 1311e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1312e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1313e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1314e7a2a87dSChristoph Hellwig } 13157bf7d778SKeith Busch iod->aborted = 1; 131657dacad5SJay Sternberg 131757dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 131857dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 131957dacad5SJay Sternberg cmd.abort.cid = req->tag; 132057dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 132157dacad5SJay Sternberg 13221b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13231b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 132457dacad5SJay Sternberg req->tag, nvmeq->qid); 1325e7a2a87dSChristoph Hellwig 1326e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1327eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13286bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13296bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 133031c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 133157dacad5SJay Sternberg } 133257dacad5SJay Sternberg 1333e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1334e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1335e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 133657dacad5SJay Sternberg 133757dacad5SJay Sternberg /* 133857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 133957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 134057dacad5SJay Sternberg * as the device then is in a faulty state. 134157dacad5SJay Sternberg */ 134257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 134357dacad5SJay Sternberg } 134457dacad5SJay Sternberg 134557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 134657dacad5SJay Sternberg { 134788a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 134857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 134963223078SChristoph Hellwig if (!nvmeq->sq_cmds) 135063223078SChristoph Hellwig return; 13510f238ff5SLogan Gunthorpe 135263223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 135388a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 135463223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 135563223078SChristoph Hellwig } else { 135688a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 135763223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13580f238ff5SLogan Gunthorpe } 135957dacad5SJay Sternberg } 136057dacad5SJay Sternberg 136157dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 136257dacad5SJay Sternberg { 136357dacad5SJay Sternberg int i; 136457dacad5SJay Sternberg 1365d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1366d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1367147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 136857dacad5SJay Sternberg } 136957dacad5SJay Sternberg } 137057dacad5SJay Sternberg 137157dacad5SJay Sternberg /** 137257dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 137340581d1aSBart Van Assche * @nvmeq: queue to suspend 137457dacad5SJay Sternberg */ 137557dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 137657dacad5SJay Sternberg { 13774e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 137857dacad5SJay Sternberg return 1; 137957dacad5SJay Sternberg 13804e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1381d1f06f4aSJens Axboe mb(); 138257dacad5SJay Sternberg 13834e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13841c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1385c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13867c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13874e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 138857dacad5SJay Sternberg return 0; 138957dacad5SJay Sternberg } 139057dacad5SJay Sternberg 13918fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13928fae268bSKeith Busch { 13938fae268bSKeith Busch int i; 13948fae268bSKeith Busch 13958fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13968fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13978fae268bSKeith Busch } 13988fae268bSKeith Busch 1399a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 140057dacad5SJay Sternberg { 1401147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 140257dacad5SJay Sternberg 1403a5cdb68cSKeith Busch if (shutdown) 1404a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1405a5cdb68cSKeith Busch else 140620d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 140757dacad5SJay Sternberg 14080b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 140957dacad5SJay Sternberg } 141057dacad5SJay Sternberg 141157dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 141257dacad5SJay Sternberg int entry_size) 141357dacad5SJay Sternberg { 141457dacad5SJay Sternberg int q_depth = dev->q_depth; 14155fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14165fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 141757dacad5SJay Sternberg 141857dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 141957dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14205fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 142157dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 142257dacad5SJay Sternberg 142357dacad5SJay Sternberg /* 142457dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 142557dacad5SJay Sternberg * would be better to map queues in system memory with the 142657dacad5SJay Sternberg * original depth 142757dacad5SJay Sternberg */ 142857dacad5SJay Sternberg if (q_depth < 64) 142957dacad5SJay Sternberg return -ENOMEM; 143057dacad5SJay Sternberg } 143157dacad5SJay Sternberg 143257dacad5SJay Sternberg return q_depth; 143357dacad5SJay Sternberg } 143457dacad5SJay Sternberg 143557dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 143657dacad5SJay Sternberg int qid, int depth) 143757dacad5SJay Sternberg { 14380f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1439815c6704SKeith Busch 14400f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14410f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14420f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14430f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 144463223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 144563223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 144663223078SChristoph Hellwig return 0; 144763223078SChristoph Hellwig } 14480f238ff5SLogan Gunthorpe } 14490f238ff5SLogan Gunthorpe 145057dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 145157dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 145257dacad5SJay Sternberg if (!nvmeq->sq_cmds) 145357dacad5SJay Sternberg return -ENOMEM; 145457dacad5SJay Sternberg return 0; 145557dacad5SJay Sternberg } 145657dacad5SJay Sternberg 1457a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 145857dacad5SJay Sternberg { 1459147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 146057dacad5SJay Sternberg 146162314e40SKeith Busch if (dev->ctrl.queue_count > qid) 146262314e40SKeith Busch return 0; 146357dacad5SJay Sternberg 1464750afb08SLuis Chamberlain nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 146557dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 146657dacad5SJay Sternberg if (!nvmeq->cqes) 146757dacad5SJay Sternberg goto free_nvmeq; 146857dacad5SJay Sternberg 146957dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 147057dacad5SJay Sternberg goto free_cqdma; 147157dacad5SJay Sternberg 147257dacad5SJay Sternberg nvmeq->dev = dev; 14731ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14743a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 147557dacad5SJay Sternberg nvmeq->cq_head = 0; 147657dacad5SJay Sternberg nvmeq->cq_phase = 1; 147757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 147857dacad5SJay Sternberg nvmeq->q_depth = depth; 147957dacad5SJay Sternberg nvmeq->qid = qid; 1480d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 148157dacad5SJay Sternberg 1482147b27e4SSagi Grimberg return 0; 148357dacad5SJay Sternberg 148457dacad5SJay Sternberg free_cqdma: 148557dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 148657dacad5SJay Sternberg nvmeq->cq_dma_addr); 148757dacad5SJay Sternberg free_nvmeq: 1488147b27e4SSagi Grimberg return -ENOMEM; 148957dacad5SJay Sternberg } 149057dacad5SJay Sternberg 1491dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 149257dacad5SJay Sternberg { 14930ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14940ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14950ff199cbSChristoph Hellwig 14960ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14970ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14980ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14990ff199cbSChristoph Hellwig } else { 15000ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15010ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15020ff199cbSChristoph Hellwig } 150357dacad5SJay Sternberg } 150457dacad5SJay Sternberg 150557dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 150657dacad5SJay Sternberg { 150757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 150857dacad5SJay Sternberg 150957dacad5SJay Sternberg nvmeq->sq_tail = 0; 151004f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 151157dacad5SJay Sternberg nvmeq->cq_head = 0; 151257dacad5SJay Sternberg nvmeq->cq_phase = 1; 151357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 151457dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1515f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 151657dacad5SJay Sternberg dev->online_queues++; 15173a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 151857dacad5SJay Sternberg } 151957dacad5SJay Sternberg 15204b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 152157dacad5SJay Sternberg { 152257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152357dacad5SJay Sternberg int result; 15247c349ddeSKeith Busch u16 vector = 0; 152557dacad5SJay Sternberg 1526d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1527d1ed6aa1SChristoph Hellwig 152822b55601SKeith Busch /* 152922b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 153022b55601SKeith Busch * has only one vector available. 153122b55601SKeith Busch */ 15324b04cc6aSJens Axboe if (!polled) 1533a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15344b04cc6aSJens Axboe else 15357c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15364b04cc6aSJens Axboe 1537a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1538ded45505SKeith Busch if (result) 1539ded45505SKeith Busch return result; 154057dacad5SJay Sternberg 154157dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 154257dacad5SJay Sternberg if (result < 0) 1543ded45505SKeith Busch return result; 1544ded45505SKeith Busch else if (result) 154557dacad5SJay Sternberg goto release_cq; 154657dacad5SJay Sternberg 1547a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1548161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15494b04cc6aSJens Axboe 15507c349ddeSKeith Busch if (!polled) { 15517c349ddeSKeith Busch nvmeq->cq_vector = vector; 1552dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 155357dacad5SJay Sternberg if (result < 0) 155457dacad5SJay Sternberg goto release_sq; 15554b04cc6aSJens Axboe } 155657dacad5SJay Sternberg 15574e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 155857dacad5SJay Sternberg return result; 155957dacad5SJay Sternberg 156057dacad5SJay Sternberg release_sq: 1561f25a2dfcSJianchao Wang dev->online_queues--; 156257dacad5SJay Sternberg adapter_delete_sq(dev, qid); 156357dacad5SJay Sternberg release_cq: 156457dacad5SJay Sternberg adapter_delete_cq(dev, qid); 156557dacad5SJay Sternberg return result; 156657dacad5SJay Sternberg } 156757dacad5SJay Sternberg 1568f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 156957dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 157077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 157157dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 157257dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15730350815aSChristoph Hellwig .init_request = nvme_init_request, 157457dacad5SJay Sternberg .timeout = nvme_timeout, 157557dacad5SJay Sternberg }; 157657dacad5SJay Sternberg 1577f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1578376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1579376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1580376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1581376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1582376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1583376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1584376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1585c6d962aeSChristoph Hellwig .poll = nvme_poll, 1586dabcefabSJens Axboe }; 1587dabcefabSJens Axboe 158857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 158957dacad5SJay Sternberg { 15901c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 159169d9a99cSKeith Busch /* 159269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 159369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 159469d9a99cSKeith Busch * queue to flush these to completion. 159569d9a99cSKeith Busch */ 1596c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15971c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 159857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 159957dacad5SJay Sternberg } 160057dacad5SJay Sternberg } 160157dacad5SJay Sternberg 160257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 160357dacad5SJay Sternberg { 16041c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 160557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 160657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1607e3e9d50cSKeith Busch 160838dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 160957dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 161057dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1611d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1612d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 161357dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 161457dacad5SJay Sternberg 161557dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 161657dacad5SJay Sternberg return -ENOMEM; 161734b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 161857dacad5SJay Sternberg 16191c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16201c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 162157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 162257dacad5SJay Sternberg return -ENOMEM; 162357dacad5SJay Sternberg } 16241c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 162557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16261c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 162757dacad5SJay Sternberg return -ENODEV; 162857dacad5SJay Sternberg } 162957dacad5SJay Sternberg } else 1630c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 163157dacad5SJay Sternberg 163257dacad5SJay Sternberg return 0; 163357dacad5SJay Sternberg } 163457dacad5SJay Sternberg 163597f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 163697f6ef64SXu Yu { 163797f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 163897f6ef64SXu Yu } 163997f6ef64SXu Yu 164097f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 164197f6ef64SXu Yu { 164297f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 164397f6ef64SXu Yu 164497f6ef64SXu Yu if (size <= dev->bar_mapped_size) 164597f6ef64SXu Yu return 0; 164697f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 164797f6ef64SXu Yu return -ENOMEM; 164897f6ef64SXu Yu if (dev->bar) 164997f6ef64SXu Yu iounmap(dev->bar); 165097f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 165197f6ef64SXu Yu if (!dev->bar) { 165297f6ef64SXu Yu dev->bar_mapped_size = 0; 165397f6ef64SXu Yu return -ENOMEM; 165497f6ef64SXu Yu } 165597f6ef64SXu Yu dev->bar_mapped_size = size; 165697f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 165797f6ef64SXu Yu 165897f6ef64SXu Yu return 0; 165997f6ef64SXu Yu } 166097f6ef64SXu Yu 166101ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 166257dacad5SJay Sternberg { 166357dacad5SJay Sternberg int result; 166457dacad5SJay Sternberg u32 aqa; 166557dacad5SJay Sternberg struct nvme_queue *nvmeq; 166657dacad5SJay Sternberg 166797f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 166897f6ef64SXu Yu if (result < 0) 166997f6ef64SXu Yu return result; 167097f6ef64SXu Yu 16718ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 167220d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 167357dacad5SJay Sternberg 16747a67cbeaSChristoph Hellwig if (dev->subsystem && 16757a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16767a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 167757dacad5SJay Sternberg 167820d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 167957dacad5SJay Sternberg if (result < 0) 168057dacad5SJay Sternberg return result; 168157dacad5SJay Sternberg 1682a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1683147b27e4SSagi Grimberg if (result) 1684147b27e4SSagi Grimberg return result; 168557dacad5SJay Sternberg 1686147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 168757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 168857dacad5SJay Sternberg aqa |= aqa << 16; 168957dacad5SJay Sternberg 16907a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16917a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16927a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 169357dacad5SJay Sternberg 169420d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 169557dacad5SJay Sternberg if (result) 1696d4875622SKeith Busch return result; 169757dacad5SJay Sternberg 169857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1699161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1700dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 170157dacad5SJay Sternberg if (result) { 17027c349ddeSKeith Busch dev->online_queues--; 1703d4875622SKeith Busch return result; 170457dacad5SJay Sternberg } 170557dacad5SJay Sternberg 17064e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 170757dacad5SJay Sternberg return result; 170857dacad5SJay Sternberg } 170957dacad5SJay Sternberg 1710749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 171157dacad5SJay Sternberg { 17124b04cc6aSJens Axboe unsigned i, max, rw_queues; 1713749941f2SChristoph Hellwig int ret = 0; 171457dacad5SJay Sternberg 1715d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1716a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1717749941f2SChristoph Hellwig ret = -ENOMEM; 171857dacad5SJay Sternberg break; 1719749941f2SChristoph Hellwig } 1720749941f2SChristoph Hellwig } 172157dacad5SJay Sternberg 1722d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1723e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1724e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1725e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17264b04cc6aSJens Axboe } else { 17274b04cc6aSJens Axboe rw_queues = max; 17284b04cc6aSJens Axboe } 17294b04cc6aSJens Axboe 1730949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17314b04cc6aSJens Axboe bool polled = i > rw_queues; 17324b04cc6aSJens Axboe 17334b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1734d4875622SKeith Busch if (ret) 173557dacad5SJay Sternberg break; 173657dacad5SJay Sternberg } 173757dacad5SJay Sternberg 1738749941f2SChristoph Hellwig /* 1739749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17408adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17418adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1742749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1743749941f2SChristoph Hellwig */ 1744749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 174557dacad5SJay Sternberg } 174657dacad5SJay Sternberg 1747202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1748202021c1SStephen Bates struct device_attribute *attr, 1749202021c1SStephen Bates char *buf) 1750202021c1SStephen Bates { 1751202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1752202021c1SStephen Bates 1753c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1754202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1755202021c1SStephen Bates } 1756202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1757202021c1SStephen Bates 175888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 175957dacad5SJay Sternberg { 176088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 176188de4598SChristoph Hellwig 176288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 176388de4598SChristoph Hellwig } 176488de4598SChristoph Hellwig 176588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 176688de4598SChristoph Hellwig { 176788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 176888de4598SChristoph Hellwig } 176988de4598SChristoph Hellwig 1770f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 177157dacad5SJay Sternberg { 177288de4598SChristoph Hellwig u64 size, offset; 177357dacad5SJay Sternberg resource_size_t bar_size; 177457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17758969f1f8SChristoph Hellwig int bar; 177657dacad5SJay Sternberg 17779fe5c59fSKeith Busch if (dev->cmb_size) 17789fe5c59fSKeith Busch return; 17799fe5c59fSKeith Busch 17807a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1781f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1782f65efd6dSChristoph Hellwig return; 1783202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 178457dacad5SJay Sternberg 178588de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 178688de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17878969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17888969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 178957dacad5SJay Sternberg 179057dacad5SJay Sternberg if (offset > bar_size) 1791f65efd6dSChristoph Hellwig return; 179257dacad5SJay Sternberg 179357dacad5SJay Sternberg /* 179457dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 179557dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 179657dacad5SJay Sternberg * the reported size of the BAR 179757dacad5SJay Sternberg */ 179857dacad5SJay Sternberg if (size > bar_size - offset) 179957dacad5SJay Sternberg size = bar_size - offset; 180057dacad5SJay Sternberg 18010f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18020f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18030f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1804f65efd6dSChristoph Hellwig return; 18050f238ff5SLogan Gunthorpe } 18060f238ff5SLogan Gunthorpe 180757dacad5SJay Sternberg dev->cmb_size = size; 18080f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18090f238ff5SLogan Gunthorpe 18100f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18110f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18120f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1813f65efd6dSChristoph Hellwig 1814f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1815f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1816f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1817f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 181857dacad5SJay Sternberg } 181957dacad5SJay Sternberg 182057dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 182157dacad5SJay Sternberg { 18220f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1823f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1824f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18250f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1826f63572dfSJon Derrick } 182757dacad5SJay Sternberg } 182857dacad5SJay Sternberg 182987ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 183057dacad5SJay Sternberg { 18314033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 183287ad72a5SChristoph Hellwig struct nvme_command c; 183387ad72a5SChristoph Hellwig int ret; 183487ad72a5SChristoph Hellwig 183587ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 183687ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 183787ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 183887ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 183987ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 184087ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 184187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 184287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 184387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 184487ad72a5SChristoph Hellwig 184587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 184687ad72a5SChristoph Hellwig if (ret) { 184787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 184887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 184987ad72a5SChristoph Hellwig ret, bits); 185087ad72a5SChristoph Hellwig } 185187ad72a5SChristoph Hellwig return ret; 185287ad72a5SChristoph Hellwig } 185387ad72a5SChristoph Hellwig 185487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 185587ad72a5SChristoph Hellwig { 185687ad72a5SChristoph Hellwig int i; 185787ad72a5SChristoph Hellwig 185887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 185987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 186087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 186187ad72a5SChristoph Hellwig 1862cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1863cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1864cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 186587ad72a5SChristoph Hellwig } 186687ad72a5SChristoph Hellwig 186787ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 186887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18694033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18704033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18714033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 187287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18737e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 187487ad72a5SChristoph Hellwig } 187587ad72a5SChristoph Hellwig 187692dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 187792dc6895SChristoph Hellwig u32 chunk_size) 187887ad72a5SChristoph Hellwig { 187987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 188092dc6895SChristoph Hellwig u32 max_entries, len; 18814033f35dSChristoph Hellwig dma_addr_t descs_dma; 18822ee0e4edSDan Carpenter int i = 0; 188387ad72a5SChristoph Hellwig void **bufs; 18846fbcde66SMinwoo Im u64 size, tmp; 188587ad72a5SChristoph Hellwig 188687ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 188787ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 188887ad72a5SChristoph Hellwig max_entries = tmp; 1889044a9df1SChristoph Hellwig 1890044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1891044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1892044a9df1SChristoph Hellwig 1893750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 18944033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 189587ad72a5SChristoph Hellwig if (!descs) 189687ad72a5SChristoph Hellwig goto out; 189787ad72a5SChristoph Hellwig 189887ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 189987ad72a5SChristoph Hellwig if (!bufs) 190087ad72a5SChristoph Hellwig goto out_free_descs; 190187ad72a5SChristoph Hellwig 1902244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 190387ad72a5SChristoph Hellwig dma_addr_t dma_addr; 190487ad72a5SChristoph Hellwig 190550cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 190687ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 190787ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 190887ad72a5SChristoph Hellwig if (!bufs[i]) 190987ad72a5SChristoph Hellwig break; 191087ad72a5SChristoph Hellwig 191187ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 191287ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 191387ad72a5SChristoph Hellwig i++; 191487ad72a5SChristoph Hellwig } 191587ad72a5SChristoph Hellwig 191692dc6895SChristoph Hellwig if (!size) 191787ad72a5SChristoph Hellwig goto out_free_bufs; 191887ad72a5SChristoph Hellwig 191987ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 192087ad72a5SChristoph Hellwig dev->host_mem_size = size; 192187ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19224033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 192387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 192487ad72a5SChristoph Hellwig return 0; 192587ad72a5SChristoph Hellwig 192687ad72a5SChristoph Hellwig out_free_bufs: 192787ad72a5SChristoph Hellwig while (--i >= 0) { 192887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 192987ad72a5SChristoph Hellwig 1930cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1931cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1932cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 193387ad72a5SChristoph Hellwig } 193487ad72a5SChristoph Hellwig 193587ad72a5SChristoph Hellwig kfree(bufs); 193687ad72a5SChristoph Hellwig out_free_descs: 19374033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19384033f35dSChristoph Hellwig descs_dma); 193987ad72a5SChristoph Hellwig out: 194087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 194187ad72a5SChristoph Hellwig return -ENOMEM; 194287ad72a5SChristoph Hellwig } 194387ad72a5SChristoph Hellwig 194492dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 194592dc6895SChristoph Hellwig { 194692dc6895SChristoph Hellwig u32 chunk_size; 194792dc6895SChristoph Hellwig 194892dc6895SChristoph Hellwig /* start big and work our way down */ 194930f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1950044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 195192dc6895SChristoph Hellwig chunk_size /= 2) { 195292dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 195392dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 195492dc6895SChristoph Hellwig return 0; 195592dc6895SChristoph Hellwig nvme_free_host_mem(dev); 195692dc6895SChristoph Hellwig } 195792dc6895SChristoph Hellwig } 195892dc6895SChristoph Hellwig 195992dc6895SChristoph Hellwig return -ENOMEM; 196092dc6895SChristoph Hellwig } 196192dc6895SChristoph Hellwig 19629620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 196387ad72a5SChristoph Hellwig { 196487ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 196587ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 196687ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 196787ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19686fbcde66SMinwoo Im int ret; 196987ad72a5SChristoph Hellwig 197087ad72a5SChristoph Hellwig preferred = min(preferred, max); 197187ad72a5SChristoph Hellwig if (min > max) { 197287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 197387ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 197487ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 197587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19769620cfbaSChristoph Hellwig return 0; 197787ad72a5SChristoph Hellwig } 197887ad72a5SChristoph Hellwig 197987ad72a5SChristoph Hellwig /* 198087ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 198187ad72a5SChristoph Hellwig */ 198287ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 198387ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 198487ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 198587ad72a5SChristoph Hellwig else 198687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 198787ad72a5SChristoph Hellwig } 198887ad72a5SChristoph Hellwig 198987ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 199092dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 199192dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 199292dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19939620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199692dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 199792dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 199892dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 199992dc6895SChristoph Hellwig } 200092dc6895SChristoph Hellwig 20019620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20029620cfbaSChristoph Hellwig if (ret) 200387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20049620cfbaSChristoph Hellwig return ret; 200557dacad5SJay Sternberg } 200657dacad5SJay Sternberg 2007612b7286SMing Lei /* 2008612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2009612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2010612b7286SMing Lei */ 2011612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20123b6592f7SJens Axboe { 2013612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2014612b7286SMing Lei unsigned int nr_read_queues; 2015c45b1fa2SMing Lei 20163b6592f7SJens Axboe /* 2017612b7286SMing Lei * If there is no interupt available for queues, ensure that 2018612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2019612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2020612b7286SMing Lei * 2021612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2022612b7286SMing Lei * write and read queues. 2023612b7286SMing Lei * 2024612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2025612b7286SMing Lei * queue. 20263b6592f7SJens Axboe */ 2027612b7286SMing Lei if (!nrirqs) { 2028612b7286SMing Lei nrirqs = 1; 2029612b7286SMing Lei nr_read_queues = 0; 2030612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2031612b7286SMing Lei nr_read_queues = 0; 2032612b7286SMing Lei } else if (write_queues >= nrirqs) { 2033612b7286SMing Lei nr_read_queues = 1; 20343b6592f7SJens Axboe } else { 2035612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20363b6592f7SJens Axboe } 2037612b7286SMing Lei 2038612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2039612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2040612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2041612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2042612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20433b6592f7SJens Axboe } 20443b6592f7SJens Axboe 20456451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20463b6592f7SJens Axboe { 20473b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20483b6592f7SJens Axboe struct irq_affinity affd = { 20493b6592f7SJens Axboe .pre_vectors = 1, 2050612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2051612b7286SMing Lei .priv = dev, 20523b6592f7SJens Axboe }; 20536451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 2054dad77d63SMinwoo Im unsigned int nr_cpus = num_possible_cpus(); 20556451fe73SJens Axboe 20566451fe73SJens Axboe /* 20576451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20586451fe73SJens Axboe * queue left over for non-polled IO. 20596451fe73SJens Axboe */ 20606451fe73SJens Axboe this_p_queues = poll_queues; 20616451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20626451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20636451fe73SJens Axboe irq_queues = 1; 20646451fe73SJens Axboe } else { 2065dad77d63SMinwoo Im if (nr_cpus < nr_io_queues - this_p_queues) 2066dad77d63SMinwoo Im irq_queues = nr_cpus + 1; 2067dad77d63SMinwoo Im else 2068c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20696451fe73SJens Axboe } 20706451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20713b6592f7SJens Axboe 2072612b7286SMing Lei /* Initialize for the single interrupt case */ 2073612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2074612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20753b6592f7SJens Axboe 2076612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20773b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20783b6592f7SJens Axboe } 20793b6592f7SJens Axboe 20808fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20818fae268bSKeith Busch { 20828fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20838fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20848fae268bSKeith Busch } 20858fae268bSKeith Busch 208657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 208757dacad5SJay Sternberg { 2088147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 208957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 209097f6ef64SXu Yu int result, nr_io_queues; 209197f6ef64SXu Yu unsigned long size; 209257dacad5SJay Sternberg 20933b6592f7SJens Axboe nr_io_queues = max_io_queues(); 20949a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 20959a0be7abSChristoph Hellwig if (result < 0) 209657dacad5SJay Sternberg return result; 20979a0be7abSChristoph Hellwig 2098f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2099a5229050SKeith Busch return 0; 210057dacad5SJay Sternberg 21014e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21024e224106SChristoph Hellwig 21030f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 210457dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 210557dacad5SJay Sternberg sizeof(struct nvme_command)); 210657dacad5SJay Sternberg if (result > 0) 210757dacad5SJay Sternberg dev->q_depth = result; 210857dacad5SJay Sternberg else 21090f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 211057dacad5SJay Sternberg } 211157dacad5SJay Sternberg 211257dacad5SJay Sternberg do { 211397f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 211497f6ef64SXu Yu result = nvme_remap_bar(dev, size); 211597f6ef64SXu Yu if (!result) 211657dacad5SJay Sternberg break; 211757dacad5SJay Sternberg if (!--nr_io_queues) 211857dacad5SJay Sternberg return -ENOMEM; 211957dacad5SJay Sternberg } while (1); 212057dacad5SJay Sternberg adminq->q_db = dev->dbs; 212157dacad5SJay Sternberg 21228fae268bSKeith Busch retry: 212357dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21240ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 212557dacad5SJay Sternberg 212657dacad5SJay Sternberg /* 212757dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 212857dacad5SJay Sternberg * setting up the full range we need. 212957dacad5SJay Sternberg */ 2130dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21313b6592f7SJens Axboe 21323b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 213322b55601SKeith Busch if (result <= 0) 2134dca51e78SChristoph Hellwig return -EIO; 21353b6592f7SJens Axboe 213622b55601SKeith Busch dev->num_vecs = result; 21374b04cc6aSJens Axboe result = max(result - 1, 1); 2138e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 213957dacad5SJay Sternberg 214057dacad5SJay Sternberg /* 214157dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 214257dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 214357dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 214457dacad5SJay Sternberg * number of interrupts. 214557dacad5SJay Sternberg */ 2146dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21477c349ddeSKeith Busch if (result) 2148d4875622SKeith Busch return result; 21494e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21508fae268bSKeith Busch 21518fae268bSKeith Busch result = nvme_create_io_queues(dev); 21528fae268bSKeith Busch if (result || dev->online_queues < 2) 21538fae268bSKeith Busch return result; 21548fae268bSKeith Busch 21558fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21568fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21578fae268bSKeith Busch nvme_disable_io_queues(dev); 21588fae268bSKeith Busch nvme_suspend_io_queues(dev); 21598fae268bSKeith Busch goto retry; 21608fae268bSKeith Busch } 21618fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21628fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21638fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21648fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21658fae268bSKeith Busch return 0; 216657dacad5SJay Sternberg } 216757dacad5SJay Sternberg 21682a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2169db3cbfffSKeith Busch { 2170db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2171db3cbfffSKeith Busch 2172db3cbfffSKeith Busch blk_mq_free_request(req); 2173d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2174db3cbfffSKeith Busch } 2175db3cbfffSKeith Busch 21762a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2177db3cbfffSKeith Busch { 2178db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2179db3cbfffSKeith Busch 2180d1ed6aa1SChristoph Hellwig if (error) 2181d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2182db3cbfffSKeith Busch 2183db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2184db3cbfffSKeith Busch } 2185db3cbfffSKeith Busch 2186db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2187db3cbfffSKeith Busch { 2188db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2189db3cbfffSKeith Busch struct request *req; 2190db3cbfffSKeith Busch struct nvme_command cmd; 2191db3cbfffSKeith Busch 2192db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2193db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2194db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2195db3cbfffSKeith Busch 2196eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2197db3cbfffSKeith Busch if (IS_ERR(req)) 2198db3cbfffSKeith Busch return PTR_ERR(req); 2199db3cbfffSKeith Busch 2200db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2201db3cbfffSKeith Busch req->end_io_data = nvmeq; 2202db3cbfffSKeith Busch 2203d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2204db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2205db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2206db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2207db3cbfffSKeith Busch return 0; 2208db3cbfffSKeith Busch } 2209db3cbfffSKeith Busch 22108fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2211db3cbfffSKeith Busch { 22125271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2213db3cbfffSKeith Busch unsigned long timeout; 2214db3cbfffSKeith Busch 2215db3cbfffSKeith Busch retry: 2216db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22175271edd4SChristoph Hellwig while (nr_queues > 0) { 22185271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2219db3cbfffSKeith Busch break; 22205271edd4SChristoph Hellwig nr_queues--; 22215271edd4SChristoph Hellwig sent++; 22225271edd4SChristoph Hellwig } 2223d1ed6aa1SChristoph Hellwig while (sent) { 2224d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2225d1ed6aa1SChristoph Hellwig 2226d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22275271edd4SChristoph Hellwig timeout); 2228db3cbfffSKeith Busch if (timeout == 0) 22295271edd4SChristoph Hellwig return false; 2230d1ed6aa1SChristoph Hellwig 2231d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2232d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2233d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2234d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2235d1ed6aa1SChristoph Hellwig 2236d1ed6aa1SChristoph Hellwig sent--; 22375271edd4SChristoph Hellwig if (nr_queues) 2238db3cbfffSKeith Busch goto retry; 2239db3cbfffSKeith Busch } 22405271edd4SChristoph Hellwig return true; 2241db3cbfffSKeith Busch } 2242db3cbfffSKeith Busch 224357dacad5SJay Sternberg /* 22442b1b7e78SJianchao Wang * return error value only when tagset allocation failed 224557dacad5SJay Sternberg */ 224657dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 224757dacad5SJay Sternberg { 22482b1b7e78SJianchao Wang int ret; 22492b1b7e78SJianchao Wang 22505bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2251c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 225257dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2253ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2254ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2255ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 225657dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 225757dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 225857dacad5SJay Sternberg dev->tagset.queue_depth = 225957dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2260d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 226157dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 226257dacad5SJay Sternberg dev->tagset.driver_data = dev; 226357dacad5SJay Sternberg 22642b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22652b1b7e78SJianchao Wang if (ret) { 22662b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22672b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22682b1b7e78SJianchao Wang return ret; 22692b1b7e78SJianchao Wang } 22705bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2271949928c1SKeith Busch } else { 2272949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2273949928c1SKeith Busch 2274949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2275949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 227657dacad5SJay Sternberg } 2277949928c1SKeith Busch 2278e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 227957dacad5SJay Sternberg return 0; 228057dacad5SJay Sternberg } 228157dacad5SJay Sternberg 2282b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 228357dacad5SJay Sternberg { 2284b00a726aSKeith Busch int result = -ENOMEM; 228557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 228657dacad5SJay Sternberg 228757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 228857dacad5SJay Sternberg return result; 228957dacad5SJay Sternberg 229057dacad5SJay Sternberg pci_set_master(pdev); 229157dacad5SJay Sternberg 229257dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 229357dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 229457dacad5SJay Sternberg goto disable; 229557dacad5SJay Sternberg 22967a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 229757dacad5SJay Sternberg result = -ENODEV; 2298b00a726aSKeith Busch goto disable; 229957dacad5SJay Sternberg } 230057dacad5SJay Sternberg 230157dacad5SJay Sternberg /* 2302a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2303a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2304a5229050SKeith Busch * adjust this later. 230557dacad5SJay Sternberg */ 2306dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2307dca51e78SChristoph Hellwig if (result < 0) 2308dca51e78SChristoph Hellwig return result; 230957dacad5SJay Sternberg 231020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23117a67cbeaSChristoph Hellwig 231220d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2313b27c1e68Sweiping zhang io_queue_depth); 231420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23157a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23161f390c1fSStephan Günther 23171f390c1fSStephan Günther /* 23181f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23191f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23201f390c1fSStephan Günther */ 23211f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23221f390c1fSStephan Günther dev->q_depth = 2; 23239bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23249bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23251f390c1fSStephan Günther dev->q_depth); 2326d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2327d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 232820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2329d554b5e1SMartin K. Petersen dev->q_depth = 64; 2330d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2331d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23321f390c1fSStephan Günther } 23331f390c1fSStephan Günther 2334f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2335202021c1SStephen Bates 2336a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2337a0a3408eSKeith Busch pci_save_state(pdev); 233857dacad5SJay Sternberg return 0; 233957dacad5SJay Sternberg 234057dacad5SJay Sternberg disable: 234157dacad5SJay Sternberg pci_disable_device(pdev); 234257dacad5SJay Sternberg return result; 234357dacad5SJay Sternberg } 234457dacad5SJay Sternberg 234557dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 234657dacad5SJay Sternberg { 2347b00a726aSKeith Busch if (dev->bar) 2348b00a726aSKeith Busch iounmap(dev->bar); 2349a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2350b00a726aSKeith Busch } 2351b00a726aSKeith Busch 2352b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2353b00a726aSKeith Busch { 235457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 235557dacad5SJay Sternberg 2356dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 235757dacad5SJay Sternberg 2358a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2359a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 236057dacad5SJay Sternberg pci_disable_device(pdev); 236157dacad5SJay Sternberg } 2362a0a3408eSKeith Busch } 236357dacad5SJay Sternberg 2364a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 236557dacad5SJay Sternberg { 2366e43269e6SKeith Busch bool dead = true, freeze = false; 2367302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 236857dacad5SJay Sternberg 236977bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2370302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2371302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2372302ad8ccSKeith Busch 2373ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2374e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2375e43269e6SKeith Busch freeze = true; 2376302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2377e43269e6SKeith Busch } 2378302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2379302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 238057dacad5SJay Sternberg } 2381c21377f8SGabriel Krisman Bertazi 2382302ad8ccSKeith Busch /* 2383302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2384302ad8ccSKeith Busch * doing a safe shutdown. 2385302ad8ccSKeith Busch */ 2386e43269e6SKeith Busch if (!dead && shutdown && freeze) 2387302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 238887ad72a5SChristoph Hellwig 23899a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 23909a915a5bSJianchao Wang 239164ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 23928fae268bSKeith Busch nvme_disable_io_queues(dev); 2393a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 239457dacad5SJay Sternberg } 23958fae268bSKeith Busch nvme_suspend_io_queues(dev); 23968fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2397b00a726aSKeith Busch nvme_pci_disable(dev); 239857dacad5SJay Sternberg 2399e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2400e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2401302ad8ccSKeith Busch 2402302ad8ccSKeith Busch /* 2403302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2404302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2405302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2406302ad8ccSKeith Busch */ 2407c8e9e9b7SKeith Busch if (shutdown) { 2408302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2409c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2410c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2411c8e9e9b7SKeith Busch } 241277bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 241357dacad5SJay Sternberg } 241457dacad5SJay Sternberg 241557dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 241657dacad5SJay Sternberg { 241757dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 241857dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 241957dacad5SJay Sternberg if (!dev->prp_page_pool) 242057dacad5SJay Sternberg return -ENOMEM; 242157dacad5SJay Sternberg 242257dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 242357dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 242457dacad5SJay Sternberg 256, 256, 0); 242557dacad5SJay Sternberg if (!dev->prp_small_pool) { 242657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 242757dacad5SJay Sternberg return -ENOMEM; 242857dacad5SJay Sternberg } 242957dacad5SJay Sternberg return 0; 243057dacad5SJay Sternberg } 243157dacad5SJay Sternberg 243257dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 243357dacad5SJay Sternberg { 243457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 243557dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 243657dacad5SJay Sternberg } 243757dacad5SJay Sternberg 24381673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 243957dacad5SJay Sternberg { 24401673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 244157dacad5SJay Sternberg 2442f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 244357dacad5SJay Sternberg put_device(dev->dev); 244457dacad5SJay Sternberg if (dev->tagset.tags) 244557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24461c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24471c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 244857dacad5SJay Sternberg kfree(dev->queues); 2449e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2450943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 245157dacad5SJay Sternberg kfree(dev); 245257dacad5SJay Sternberg } 245357dacad5SJay Sternberg 2454f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2455f58944e2SKeith Busch { 2456237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2457f58944e2SKeith Busch 2458d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 245969d9a99cSKeith Busch nvme_dev_disable(dev, false); 24609f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 246103e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2462f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2463f58944e2SKeith Busch } 2464f58944e2SKeith Busch 2465fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 246657dacad5SJay Sternberg { 2467d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2468d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2469a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2470e71afda4SChaitanya Kulkarni int result; 24712b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 247257dacad5SJay Sternberg 2473e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2474e71afda4SChaitanya Kulkarni result = -ENODEV; 2475fd634f41SChristoph Hellwig goto out; 2476e71afda4SChaitanya Kulkarni } 2477fd634f41SChristoph Hellwig 2478fd634f41SChristoph Hellwig /* 2479fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2480fd634f41SChristoph Hellwig * moving on. 2481fd634f41SChristoph Hellwig */ 2482b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2483a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2484d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2485fd634f41SChristoph Hellwig 24865c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2487b00a726aSKeith Busch result = nvme_pci_enable(dev); 248857dacad5SJay Sternberg if (result) 24894726bcf3SKeith Busch goto out_unlock; 249057dacad5SJay Sternberg 249101ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 249257dacad5SJay Sternberg if (result) 24934726bcf3SKeith Busch goto out_unlock; 249457dacad5SJay Sternberg 249557dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 249657dacad5SJay Sternberg if (result) 24974726bcf3SKeith Busch goto out_unlock; 249857dacad5SJay Sternberg 2499943e942eSJens Axboe /* 2500943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2501943e942eSJens Axboe * over a single page. 2502943e942eSJens Axboe */ 2503943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2504943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2505a48bc520SChristoph Hellwig 2506a48bc520SChristoph Hellwig /* 2507a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2508a48bc520SChristoph Hellwig */ 2509a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2510a48bc520SChristoph Hellwig 25115c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25125c959d73SKeith Busch 25135c959d73SKeith Busch /* 25145c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25155c959d73SKeith Busch * initializing procedure here. 25165c959d73SKeith Busch */ 25175c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25185c959d73SKeith Busch dev_warn(dev->ctrl.device, 25195c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2520*cee6c269SMinwoo Im result = -EBUSY; 25215c959d73SKeith Busch goto out; 25225c959d73SKeith Busch } 2523943e942eSJens Axboe 2524ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2525ce4541f4SChristoph Hellwig if (result) 2526f58944e2SKeith Busch goto out; 2527ce4541f4SChristoph Hellwig 2528e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2529e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25304f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25314f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2532e286bcfcSScott Bauer else if (was_suspend) 25334f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2534e286bcfcSScott Bauer } else { 2535e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2536e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2537e286bcfcSScott Bauer } 2538a98e58e5SScott Bauer 2539f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2540f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2541f9f38e33SHelen Koike if (result) 2542f9f38e33SHelen Koike dev_warn(dev->dev, 2543f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2544f9f38e33SHelen Koike } 2545f9f38e33SHelen Koike 25469620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25479620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25489620cfbaSChristoph Hellwig if (result < 0) 25499620cfbaSChristoph Hellwig goto out; 25509620cfbaSChristoph Hellwig } 255187ad72a5SChristoph Hellwig 255257dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 255357dacad5SJay Sternberg if (result) 2554f58944e2SKeith Busch goto out; 255557dacad5SJay Sternberg 255621f033f7SKeith Busch /* 255757dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 255857dacad5SJay Sternberg * any working I/O queue. 255957dacad5SJay Sternberg */ 256057dacad5SJay Sternberg if (dev->online_queues < 2) { 25611b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25623b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25635bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25642b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 256557dacad5SJay Sternberg } else { 256625646264SKeith Busch nvme_start_queues(&dev->ctrl); 2567302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25682b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25692b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25702b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2571302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 257257dacad5SJay Sternberg } 257357dacad5SJay Sternberg 25742b1b7e78SJianchao Wang /* 25752b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25762b1b7e78SJianchao Wang * recovery. 25772b1b7e78SJianchao Wang */ 25782b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 25792b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25802b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2581e71afda4SChaitanya Kulkarni result = -ENODEV; 2582bb8d261eSChristoph Hellwig goto out; 2583bb8d261eSChristoph Hellwig } 258492911a55SChristoph Hellwig 2585d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 258657dacad5SJay Sternberg return; 258757dacad5SJay Sternberg 25884726bcf3SKeith Busch out_unlock: 25894726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 259057dacad5SJay Sternberg out: 2591f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 259257dacad5SJay Sternberg } 259357dacad5SJay Sternberg 25945c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 259557dacad5SJay Sternberg { 25965c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 259757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 259857dacad5SJay Sternberg 259957dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2600921920abSKeith Busch device_release_driver(&pdev->dev); 26011673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 260257dacad5SJay Sternberg } 260357dacad5SJay Sternberg 26041c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 260557dacad5SJay Sternberg { 26061c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26071c63dc66SChristoph Hellwig return 0; 260857dacad5SJay Sternberg } 26091c63dc66SChristoph Hellwig 26105fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26115fd4ce1bSChristoph Hellwig { 26125fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26135fd4ce1bSChristoph Hellwig return 0; 26145fd4ce1bSChristoph Hellwig } 26155fd4ce1bSChristoph Hellwig 26167fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26177fd8930fSChristoph Hellwig { 26187fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26197fd8930fSChristoph Hellwig return 0; 26207fd8930fSChristoph Hellwig } 26217fd8930fSChristoph Hellwig 262297c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 262397c12223SKeith Busch { 262497c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 262597c12223SKeith Busch 262697c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 262797c12223SKeith Busch } 262897c12223SKeith Busch 26291c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26301a353d85SMing Lin .name = "pcie", 2631e439bb12SSagi Grimberg .module = THIS_MODULE, 2632e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2633e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26341c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26355fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26367fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26371673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2638f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 263997c12223SKeith Busch .get_address = nvme_pci_get_address, 26401c63dc66SChristoph Hellwig }; 264157dacad5SJay Sternberg 2642b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2643b00a726aSKeith Busch { 2644b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2645b00a726aSKeith Busch 2646a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2647b00a726aSKeith Busch return -ENODEV; 2648b00a726aSKeith Busch 264997f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2650b00a726aSKeith Busch goto release; 2651b00a726aSKeith Busch 2652b00a726aSKeith Busch return 0; 2653b00a726aSKeith Busch release: 2654a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2655b00a726aSKeith Busch return -ENODEV; 2656b00a726aSKeith Busch } 2657b00a726aSKeith Busch 26588427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2659ff5350a8SAndy Lutomirski { 2660ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2661ff5350a8SAndy Lutomirski /* 2662ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2663ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2664ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2665ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2666ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2667ff5350a8SAndy Lutomirski * laptops. 2668ff5350a8SAndy Lutomirski */ 2669ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2670ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2671ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2672ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26738427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26748427bbc2SKai-Heng Feng /* 26758427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2676467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2677467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2678467c77d4SJarosław Janik * ASUS PRIME Z370-A 26798427bbc2SKai-Heng Feng */ 26808427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2681467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2682467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 26838427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2684ff5350a8SAndy Lutomirski } 2685ff5350a8SAndy Lutomirski 2686ff5350a8SAndy Lutomirski return 0; 2687ff5350a8SAndy Lutomirski } 2688ff5350a8SAndy Lutomirski 268918119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 269018119775SKeith Busch { 269118119775SKeith Busch struct nvme_dev *dev = data; 269280f513b5SKeith Busch 269318119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 269418119775SKeith Busch flush_work(&dev->ctrl.scan_work); 269580f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 269618119775SKeith Busch } 269718119775SKeith Busch 269857dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 269957dacad5SJay Sternberg { 270057dacad5SJay Sternberg int node, result = -ENOMEM; 270157dacad5SJay Sternberg struct nvme_dev *dev; 2702ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2703943e942eSJens Axboe size_t alloc_size; 270457dacad5SJay Sternberg 270557dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 270657dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27072fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 270857dacad5SJay Sternberg 270957dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 271057dacad5SJay Sternberg if (!dev) 271157dacad5SJay Sternberg return -ENOMEM; 2712147b27e4SSagi Grimberg 27133b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27143b6592f7SJens Axboe GFP_KERNEL, node); 271557dacad5SJay Sternberg if (!dev->queues) 271657dacad5SJay Sternberg goto free; 271757dacad5SJay Sternberg 271857dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 271957dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 272057dacad5SJay Sternberg 2721b00a726aSKeith Busch result = nvme_dev_map(dev); 2722b00a726aSKeith Busch if (result) 2723b00c9b7aSChristophe JAILLET goto put_pci; 2724b00a726aSKeith Busch 2725d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27265c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 272777bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2728f3ca80fcSChristoph Hellwig 2729f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2730f3ca80fcSChristoph Hellwig if (result) 2731b00c9b7aSChristophe JAILLET goto unmap; 2732f3ca80fcSChristoph Hellwig 27338427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2734ff5350a8SAndy Lutomirski 2735943e942eSJens Axboe /* 2736943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2737943e942eSJens Axboe * command we support. 2738943e942eSJens Axboe */ 2739943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2740943e942eSJens Axboe NVME_MAX_SEGS, true); 2741943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2742943e942eSJens Axboe 2743943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2744943e942eSJens Axboe mempool_kfree, 2745943e942eSJens Axboe (void *) alloc_size, 2746943e942eSJens Axboe GFP_KERNEL, node); 2747943e942eSJens Axboe if (!dev->iod_mempool) { 2748943e942eSJens Axboe result = -ENOMEM; 2749943e942eSJens Axboe goto release_pools; 2750943e942eSJens Axboe } 2751943e942eSJens Axboe 2752b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2753b6e44b4cSKeith Busch quirks); 2754b6e44b4cSKeith Busch if (result) 2755b6e44b4cSKeith Busch goto release_mempool; 2756b6e44b4cSKeith Busch 27571b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27581b3c47c1SSagi Grimberg 275980f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 276018119775SKeith Busch async_schedule(nvme_async_probe, dev); 27614caff8fcSSagi Grimberg 276257dacad5SJay Sternberg return 0; 276357dacad5SJay Sternberg 2764b6e44b4cSKeith Busch release_mempool: 2765b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 276657dacad5SJay Sternberg release_pools: 276757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2768b00c9b7aSChristophe JAILLET unmap: 2769b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 277057dacad5SJay Sternberg put_pci: 277157dacad5SJay Sternberg put_device(dev->dev); 277257dacad5SJay Sternberg free: 277357dacad5SJay Sternberg kfree(dev->queues); 277457dacad5SJay Sternberg kfree(dev); 277557dacad5SJay Sternberg return result; 277657dacad5SJay Sternberg } 277757dacad5SJay Sternberg 2778775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 277957dacad5SJay Sternberg { 278057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2781a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2782775755edSChristoph Hellwig } 278357dacad5SJay Sternberg 2784775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2785775755edSChristoph Hellwig { 2786f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 278779c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 278857dacad5SJay Sternberg } 278957dacad5SJay Sternberg 279057dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 279157dacad5SJay Sternberg { 279257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2793a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 279457dacad5SJay Sternberg } 279557dacad5SJay Sternberg 2796f58944e2SKeith Busch /* 2797f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2798f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2799f58944e2SKeith Busch * order to proceed. 2800f58944e2SKeith Busch */ 280157dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 280257dacad5SJay Sternberg { 280357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 280457dacad5SJay Sternberg 2805bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 280657dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28070ff9d4e1SKeith Busch 28086db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28090ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28101d39e692SKeith Busch nvme_dev_disable(dev, true); 2811cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28126db28edaSKeith Busch } 28130ff9d4e1SKeith Busch 2814d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2815d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2816d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2817a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28189fe5c59fSKeith Busch nvme_release_cmb(dev); 281987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 282057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 282157dacad5SJay Sternberg nvme_free_queues(dev, 0); 2822d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 282357dacad5SJay Sternberg nvme_release_prp_pools(dev); 2824b00a726aSKeith Busch nvme_dev_unmap(dev); 28251673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 282657dacad5SJay Sternberg } 282757dacad5SJay Sternberg 282857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2829d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2830d916b1beSKeith Busch { 2831d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2832d916b1beSKeith Busch } 2833d916b1beSKeith Busch 2834d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2835d916b1beSKeith Busch { 2836d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2837d916b1beSKeith Busch } 2838d916b1beSKeith Busch 2839d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2840d916b1beSKeith Busch { 2841d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2842d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2843d916b1beSKeith Busch 2844d916b1beSKeith Busch if (pm_resume_via_firmware() || !ctrl->npss || 2845d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2846d916b1beSKeith Busch nvme_reset_ctrl(ctrl); 2847d916b1beSKeith Busch return 0; 2848d916b1beSKeith Busch } 2849d916b1beSKeith Busch 285057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 285157dacad5SJay Sternberg { 285257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 285357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2854d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2855d916b1beSKeith Busch int ret = -EBUSY; 2856d916b1beSKeith Busch 2857d916b1beSKeith Busch /* 2858d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 2859d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 2860d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 2861d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 2862d916b1beSKeith Busch * device does not support any non-default power states, shut down the 2863d916b1beSKeith Busch * device fully. 2864d916b1beSKeith Busch */ 2865d916b1beSKeith Busch if (pm_suspend_via_firmware() || !ctrl->npss) { 2866d916b1beSKeith Busch nvme_dev_disable(ndev, true); 2867d916b1beSKeith Busch return 0; 2868d916b1beSKeith Busch } 2869d916b1beSKeith Busch 2870d916b1beSKeith Busch nvme_start_freeze(ctrl); 2871d916b1beSKeith Busch nvme_wait_freeze(ctrl); 2872d916b1beSKeith Busch nvme_sync_queues(ctrl); 2873d916b1beSKeith Busch 2874d916b1beSKeith Busch if (ctrl->state != NVME_CTRL_LIVE && 2875d916b1beSKeith Busch ctrl->state != NVME_CTRL_ADMIN_ONLY) 2876d916b1beSKeith Busch goto unfreeze; 2877d916b1beSKeith Busch 2878d916b1beSKeith Busch ndev->last_ps = 0; 2879d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2880d916b1beSKeith Busch if (ret < 0) 2881d916b1beSKeith Busch goto unfreeze; 2882d916b1beSKeith Busch 2883d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 2884d916b1beSKeith Busch if (ret < 0) 2885d916b1beSKeith Busch goto unfreeze; 2886d916b1beSKeith Busch 2887d916b1beSKeith Busch if (ret) { 2888d916b1beSKeith Busch /* 2889d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 2890d916b1beSKeith Busch * correct value will be resdicovered then. 2891d916b1beSKeith Busch */ 2892d916b1beSKeith Busch nvme_dev_disable(ndev, true); 2893d916b1beSKeith Busch ctrl->npss = 0; 2894d916b1beSKeith Busch ret = 0; 2895d916b1beSKeith Busch goto unfreeze; 2896d916b1beSKeith Busch } 2897d916b1beSKeith Busch /* 2898d916b1beSKeith Busch * A saved state prevents pci pm from generically controlling the 2899d916b1beSKeith Busch * device's power. If we're using protocol specific settings, we don't 2900d916b1beSKeith Busch * want pci interfering. 2901d916b1beSKeith Busch */ 2902d916b1beSKeith Busch pci_save_state(pdev); 2903d916b1beSKeith Busch unfreeze: 2904d916b1beSKeith Busch nvme_unfreeze(ctrl); 2905d916b1beSKeith Busch return ret; 2906d916b1beSKeith Busch } 2907d916b1beSKeith Busch 2908d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 2909d916b1beSKeith Busch { 2910d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 291157dacad5SJay Sternberg 2912a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 291357dacad5SJay Sternberg return 0; 291457dacad5SJay Sternberg } 291557dacad5SJay Sternberg 2916d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 291757dacad5SJay Sternberg { 291857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 291957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 292057dacad5SJay Sternberg 2921d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 292257dacad5SJay Sternberg return 0; 292357dacad5SJay Sternberg } 292457dacad5SJay Sternberg 2925d916b1beSKeith Busch const struct dev_pm_ops nvme_dev_pm_ops = { 2926d916b1beSKeith Busch .suspend = nvme_suspend, 2927d916b1beSKeith Busch .resume = nvme_resume, 2928d916b1beSKeith Busch .freeze = nvme_simple_suspend, 2929d916b1beSKeith Busch .thaw = nvme_simple_resume, 2930d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 2931d916b1beSKeith Busch .restore = nvme_simple_resume, 2932d916b1beSKeith Busch }; 2933d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 293457dacad5SJay Sternberg 2935a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2936a0a3408eSKeith Busch pci_channel_state_t state) 2937a0a3408eSKeith Busch { 2938a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2939a0a3408eSKeith Busch 2940a0a3408eSKeith Busch /* 2941a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2942a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2943a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2944a0a3408eSKeith Busch */ 2945a0a3408eSKeith Busch switch (state) { 2946a0a3408eSKeith Busch case pci_channel_io_normal: 2947a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2948a0a3408eSKeith Busch case pci_channel_io_frozen: 2949d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2950d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2951a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2952a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2953a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2954d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2955d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2956a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2957a0a3408eSKeith Busch } 2958a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2959a0a3408eSKeith Busch } 2960a0a3408eSKeith Busch 2961a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2962a0a3408eSKeith Busch { 2963a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2964a0a3408eSKeith Busch 29651b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2966a0a3408eSKeith Busch pci_restore_state(pdev); 2967d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2968a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2969a0a3408eSKeith Busch } 2970a0a3408eSKeith Busch 2971a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2972a0a3408eSKeith Busch { 297372cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 297472cd4cc2SKeith Busch 297572cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2976a0a3408eSKeith Busch } 2977a0a3408eSKeith Busch 297857dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 297957dacad5SJay Sternberg .error_detected = nvme_error_detected, 298057dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 298157dacad5SJay Sternberg .resume = nvme_error_resume, 2982775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2983775755edSChristoph Hellwig .reset_done = nvme_reset_done, 298457dacad5SJay Sternberg }; 298557dacad5SJay Sternberg 298657dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2987106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 298808095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2989e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 299099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 299199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2992e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 299399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 299499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2995e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2996f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2997f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2998f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 299950af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 30009abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 30019abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 30026299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 30036299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3004540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 30057b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 30067b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 30070302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 30080302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 300954adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 301054adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 30118c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 30128c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3013015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3014015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3015d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3016d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3017d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3018d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3019608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3020608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3021608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3022608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3023ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3024ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 302557dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3026c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3027124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 302857dacad5SJay Sternberg { 0, } 302957dacad5SJay Sternberg }; 303057dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 303157dacad5SJay Sternberg 303257dacad5SJay Sternberg static struct pci_driver nvme_driver = { 303357dacad5SJay Sternberg .name = "nvme", 303457dacad5SJay Sternberg .id_table = nvme_id_table, 303557dacad5SJay Sternberg .probe = nvme_probe, 303657dacad5SJay Sternberg .remove = nvme_remove, 303757dacad5SJay Sternberg .shutdown = nvme_shutdown, 3038d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 303957dacad5SJay Sternberg .driver = { 304057dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 304157dacad5SJay Sternberg }, 3042d916b1beSKeith Busch #endif 304374d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 304457dacad5SJay Sternberg .err_handler = &nvme_err_handler, 304557dacad5SJay Sternberg }; 304657dacad5SJay Sternberg 304757dacad5SJay Sternberg static int __init nvme_init(void) 304857dacad5SJay Sternberg { 304981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 305081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 305181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3052612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 30539a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 305457dacad5SJay Sternberg } 305557dacad5SJay Sternberg 305657dacad5SJay Sternberg static void __exit nvme_exit(void) 305757dacad5SJay Sternberg { 305857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 305903e0f3a6SMing Lei flush_workqueue(nvme_wq); 306057dacad5SJay Sternberg } 306157dacad5SJay Sternberg 306257dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 306357dacad5SJay Sternberg MODULE_LICENSE("GPL"); 306457dacad5SJay Sternberg MODULE_VERSION("1.0"); 306557dacad5SJay Sternberg module_init(nvme_init); 306657dacad5SJay Sternberg module_exit(nvme_exit); 3067