157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #include "nvme.h" 3657dacad5SJay Sternberg 3757dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3857dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3957dacad5SJay Sternberg 40a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 41adf68f21SChristoph Hellwig 42943e942eSJens Axboe /* 43943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 44943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 45943e942eSJens Axboe */ 46943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 47943e942eSJens Axboe #define NVME_MAX_SEGS 127 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 5057dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 70b27c1e68Sweiping zhang .get = param_get_int, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 73b27c1e68Sweiping zhang static int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 76b27c1e68Sweiping zhang 773b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 783b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 793b6592f7SJens Axboe .set = queue_count_set, 803b6592f7SJens Axboe .get = param_get_int, 813b6592f7SJens Axboe }; 823b6592f7SJens Axboe 833b6592f7SJens Axboe static int write_queues; 843b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 853b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 863b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 873b6592f7SJens Axboe "will share a queue set."); 883b6592f7SJens Axboe 89a4668d9bSJens Axboe static int poll_queues = 0; 904b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 914b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 924b04cc6aSJens Axboe 931c63dc66SChristoph Hellwig struct nvme_dev; 941c63dc66SChristoph Hellwig struct nvme_queue; 9557dacad5SJay Sternberg 96a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 9757dacad5SJay Sternberg 9857dacad5SJay Sternberg /* 991c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1001c63dc66SChristoph Hellwig */ 1011c63dc66SChristoph Hellwig struct nvme_dev { 102147b27e4SSagi Grimberg struct nvme_queue *queues; 1031c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1041c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1051c63dc66SChristoph Hellwig u32 __iomem *dbs; 1061c63dc66SChristoph Hellwig struct device *dev; 1071c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1081c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1091c63dc66SChristoph Hellwig unsigned online_queues; 1101c63dc66SChristoph Hellwig unsigned max_qid; 111e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 11222b55601SKeith Busch unsigned int num_vecs; 1131c63dc66SChristoph Hellwig int q_depth; 1141c63dc66SChristoph Hellwig u32 db_stride; 1151c63dc66SChristoph Hellwig void __iomem *bar; 11697f6ef64SXu Yu unsigned long bar_mapped_size; 1175c8809e6SChristoph Hellwig struct work_struct remove_work; 11877bf25eaSKeith Busch struct mutex shutdown_lock; 1191c63dc66SChristoph Hellwig bool subsystem; 1201c63dc66SChristoph Hellwig u64 cmb_size; 1210f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1221c63dc66SChristoph Hellwig u32 cmbsz; 123202021c1SStephen Bates u32 cmbloc; 1241c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 125db3cbfffSKeith Busch struct completion ioq_wait; 12687ad72a5SChristoph Hellwig 127943e942eSJens Axboe mempool_t *iod_mempool; 128943e942eSJens Axboe 12987ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 130f9f38e33SHelen Koike u32 *dbbuf_dbs; 131f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 132f9f38e33SHelen Koike u32 *dbbuf_eis; 133f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 13487ad72a5SChristoph Hellwig 13587ad72a5SChristoph Hellwig /* host memory buffer support: */ 13687ad72a5SChristoph Hellwig u64 host_mem_size; 13787ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1384033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 14087ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 14157dacad5SJay Sternberg }; 14257dacad5SJay Sternberg 143b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 144b27c1e68Sweiping zhang { 145b27c1e68Sweiping zhang int n = 0, ret; 146b27c1e68Sweiping zhang 147b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 148b27c1e68Sweiping zhang if (ret != 0 || n < 2) 149b27c1e68Sweiping zhang return -EINVAL; 150b27c1e68Sweiping zhang 151b27c1e68Sweiping zhang return param_set_int(val, kp); 152b27c1e68Sweiping zhang } 153b27c1e68Sweiping zhang 1543b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1553b6592f7SJens Axboe { 1563b6592f7SJens Axboe int n = 0, ret; 1573b6592f7SJens Axboe 1583b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 1593b6592f7SJens Axboe if (n > num_possible_cpus()) 1603b6592f7SJens Axboe n = num_possible_cpus(); 1613b6592f7SJens Axboe 1623b6592f7SJens Axboe return param_set_int(val, kp); 1633b6592f7SJens Axboe } 1643b6592f7SJens Axboe 165f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 166f9f38e33SHelen Koike { 167f9f38e33SHelen Koike return qid * 2 * stride; 168f9f38e33SHelen Koike } 169f9f38e33SHelen Koike 170f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 171f9f38e33SHelen Koike { 172f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 173f9f38e33SHelen Koike } 174f9f38e33SHelen Koike 1751c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1761c63dc66SChristoph Hellwig { 1771c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1781c63dc66SChristoph Hellwig } 1791c63dc66SChristoph Hellwig 18057dacad5SJay Sternberg /* 18157dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18257dacad5SJay Sternberg * commands and one for I/O commands). 18357dacad5SJay Sternberg */ 18457dacad5SJay Sternberg struct nvme_queue { 18557dacad5SJay Sternberg struct device *q_dmadev; 18657dacad5SJay Sternberg struct nvme_dev *dev; 1871ab0cd69SJens Axboe spinlock_t sq_lock; 18857dacad5SJay Sternberg struct nvme_command *sq_cmds; 1891ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 19057dacad5SJay Sternberg volatile struct nvme_completion *cqes; 19157dacad5SJay Sternberg struct blk_mq_tags **tags; 19257dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19357dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19457dacad5SJay Sternberg u32 __iomem *q_db; 19557dacad5SJay Sternberg u16 q_depth; 19657dacad5SJay Sternberg s16 cq_vector; 19757dacad5SJay Sternberg u16 sq_tail; 19804f3eafdSJens Axboe u16 last_sq_tail; 19957dacad5SJay Sternberg u16 cq_head; 20068fa9dbeSJens Axboe u16 last_cq_head; 20157dacad5SJay Sternberg u16 qid; 20257dacad5SJay Sternberg u8 cq_phase; 2034e224106SChristoph Hellwig unsigned long flags; 2044e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20563223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 206f9f38e33SHelen Koike u32 *dbbuf_sq_db; 207f9f38e33SHelen Koike u32 *dbbuf_cq_db; 208f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 209f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 21057dacad5SJay Sternberg }; 21157dacad5SJay Sternberg 21257dacad5SJay Sternberg /* 21371bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 21471bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 215f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 21671bd150cSChristoph Hellwig * allocated to store the PRP list. 21771bd150cSChristoph Hellwig */ 21871bd150cSChristoph Hellwig struct nvme_iod { 219d49187e9SChristoph Hellwig struct nvme_request req; 220f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 221a7a7cbe3SChaitanya Kulkarni bool use_sgl; 222f4800d6dSChristoph Hellwig int aborted; 22371bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22471bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22571bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 22671bd150cSChristoph Hellwig dma_addr_t first_dma; 227bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 228f4800d6dSChristoph Hellwig struct scatterlist *sg; 229f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 23057dacad5SJay Sternberg }; 23157dacad5SJay Sternberg 23257dacad5SJay Sternberg /* 23357dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23457dacad5SJay Sternberg */ 23557dacad5SJay Sternberg static inline void _nvme_check_size(void) 23657dacad5SJay Sternberg { 23757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 23857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 24257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2450add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2460add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 24857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 249f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 250f9f38e33SHelen Koike } 251f9f38e33SHelen Koike 2523b6592f7SJens Axboe static unsigned int max_io_queues(void) 2533b6592f7SJens Axboe { 2544b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2553b6592f7SJens Axboe } 2563b6592f7SJens Axboe 2573b6592f7SJens Axboe static unsigned int max_queue_count(void) 2583b6592f7SJens Axboe { 2593b6592f7SJens Axboe /* IO queues + admin queue */ 2603b6592f7SJens Axboe return 1 + max_io_queues(); 2613b6592f7SJens Axboe } 2623b6592f7SJens Axboe 263f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 264f9f38e33SHelen Koike { 2653b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike if (dev->dbbuf_dbs) 273f9f38e33SHelen Koike return 0; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 276f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 277f9f38e33SHelen Koike GFP_KERNEL); 278f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 279f9f38e33SHelen Koike return -ENOMEM; 280f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 281f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 282f9f38e33SHelen Koike GFP_KERNEL); 283f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 284f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 285f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 286f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 287f9f38e33SHelen Koike return -ENOMEM; 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike return 0; 291f9f38e33SHelen Koike } 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 294f9f38e33SHelen Koike { 295f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 296f9f38e33SHelen Koike 297f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 298f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 299f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 300f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 301f9f38e33SHelen Koike } 302f9f38e33SHelen Koike if (dev->dbbuf_eis) { 303f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 304f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 305f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 306f9f38e33SHelen Koike } 307f9f38e33SHelen Koike } 308f9f38e33SHelen Koike 309f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 310f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 311f9f38e33SHelen Koike { 312f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 313f9f38e33SHelen Koike return; 314f9f38e33SHelen Koike 315f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 316f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 317f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 318f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 319f9f38e33SHelen Koike } 320f9f38e33SHelen Koike 321f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 322f9f38e33SHelen Koike { 323f9f38e33SHelen Koike struct nvme_command c; 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 326f9f38e33SHelen Koike return; 327f9f38e33SHelen Koike 328f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 329f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 330f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 331f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 332f9f38e33SHelen Koike 333f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3349bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 335f9f38e33SHelen Koike /* Free memory and continue on */ 336f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 337f9f38e33SHelen Koike } 338f9f38e33SHelen Koike } 339f9f38e33SHelen Koike 340f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 341f9f38e33SHelen Koike { 342f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 343f9f38e33SHelen Koike } 344f9f38e33SHelen Koike 345f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 346f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 347f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 348f9f38e33SHelen Koike { 349f9f38e33SHelen Koike if (dbbuf_db) { 350f9f38e33SHelen Koike u16 old_value; 351f9f38e33SHelen Koike 352f9f38e33SHelen Koike /* 353f9f38e33SHelen Koike * Ensure that the queue is written before updating 354f9f38e33SHelen Koike * the doorbell in memory 355f9f38e33SHelen Koike */ 356f9f38e33SHelen Koike wmb(); 357f9f38e33SHelen Koike 358f9f38e33SHelen Koike old_value = *dbbuf_db; 359f9f38e33SHelen Koike *dbbuf_db = value; 360f9f38e33SHelen Koike 361f1ed3df2SMichal Wnukowski /* 362f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 363f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 364f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 365f1ed3df2SMichal Wnukowski * the doorbell. 366f1ed3df2SMichal Wnukowski */ 367f1ed3df2SMichal Wnukowski mb(); 368f1ed3df2SMichal Wnukowski 369f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 370f9f38e33SHelen Koike return false; 371f9f38e33SHelen Koike } 372f9f38e33SHelen Koike 373f9f38e33SHelen Koike return true; 37457dacad5SJay Sternberg } 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg /* 37757dacad5SJay Sternberg * Max size of iod being embedded in the request payload 37857dacad5SJay Sternberg */ 37957dacad5SJay Sternberg #define NVME_INT_PAGES 2 3805fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 38157dacad5SJay Sternberg 38257dacad5SJay Sternberg /* 38357dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38457dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38557dacad5SJay Sternberg * the I/O. 38657dacad5SJay Sternberg */ 38757dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 38857dacad5SJay Sternberg { 3895fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3905fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 39157dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 39257dacad5SJay Sternberg } 39357dacad5SJay Sternberg 394a7a7cbe3SChaitanya Kulkarni /* 395a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 396a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 397a7a7cbe3SChaitanya Kulkarni */ 398a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 399f4800d6dSChristoph Hellwig { 400a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 401f4800d6dSChristoph Hellwig } 402f4800d6dSChristoph Hellwig 403a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 404a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 40557dacad5SJay Sternberg { 406a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 407a7a7cbe3SChaitanya Kulkarni 408a7a7cbe3SChaitanya Kulkarni if (use_sgl) 409a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 410a7a7cbe3SChaitanya Kulkarni else 411a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 412a7a7cbe3SChaitanya Kulkarni 413a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 414a7a7cbe3SChaitanya Kulkarni } 415a7a7cbe3SChaitanya Kulkarni 416a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 417a7a7cbe3SChaitanya Kulkarni { 418a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 419a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 420a7a7cbe3SChaitanya Kulkarni use_sgl); 421a7a7cbe3SChaitanya Kulkarni 422a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42357dacad5SJay Sternberg } 42457dacad5SJay Sternberg 42557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 42657dacad5SJay Sternberg unsigned int hctx_idx) 42757dacad5SJay Sternberg { 42857dacad5SJay Sternberg struct nvme_dev *dev = data; 429147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 43057dacad5SJay Sternberg 43157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 43257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43357dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg hctx->driver_data = nvmeq; 43657dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 43757dacad5SJay Sternberg return 0; 43857dacad5SJay Sternberg } 43957dacad5SJay Sternberg 44057dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 44157dacad5SJay Sternberg { 44257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44357dacad5SJay Sternberg 44457dacad5SJay Sternberg nvmeq->tags = NULL; 44557dacad5SJay Sternberg } 44657dacad5SJay Sternberg 44757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 44857dacad5SJay Sternberg unsigned int hctx_idx) 44957dacad5SJay Sternberg { 45057dacad5SJay Sternberg struct nvme_dev *dev = data; 451147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 45257dacad5SJay Sternberg 45357dacad5SJay Sternberg if (!nvmeq->tags) 45457dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 45557dacad5SJay Sternberg 45657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 45757dacad5SJay Sternberg hctx->driver_data = nvmeq; 45857dacad5SJay Sternberg return 0; 45957dacad5SJay Sternberg } 46057dacad5SJay Sternberg 461d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 462d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46357dacad5SJay Sternberg { 464d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 465f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4660350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 467147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 46857dacad5SJay Sternberg 46957dacad5SJay Sternberg BUG_ON(!nvmeq); 470f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 47159e29ce6SSagi Grimberg 47259e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47357dacad5SJay Sternberg return 0; 47457dacad5SJay Sternberg } 47557dacad5SJay Sternberg 4763b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4773b6592f7SJens Axboe { 4783b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4793b6592f7SJens Axboe if (dev->num_vecs > 1) 4803b6592f7SJens Axboe return 1; 4813b6592f7SJens Axboe 4823b6592f7SJens Axboe return 0; 4833b6592f7SJens Axboe } 4843b6592f7SJens Axboe 485dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 486dca51e78SChristoph Hellwig { 487dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4883b6592f7SJens Axboe int i, qoff, offset; 489dca51e78SChristoph Hellwig 4903b6592f7SJens Axboe offset = queue_irq_offset(dev); 4913b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4923b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4933b6592f7SJens Axboe 4943b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4953b6592f7SJens Axboe if (!map->nr_queues) { 496e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4973b6592f7SJens Axboe 4983b6592f7SJens Axboe /* shared set, resuse read set parameters */ 499e20ba6e1SChristoph Hellwig map->nr_queues = dev->io_queues[HCTX_TYPE_DEFAULT]; 5003b6592f7SJens Axboe qoff = 0; 5013b6592f7SJens Axboe offset = queue_irq_offset(dev); 5023b6592f7SJens Axboe } 5033b6592f7SJens Axboe 5044b04cc6aSJens Axboe /* 5054b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 5064b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5074b04cc6aSJens Axboe */ 5083b6592f7SJens Axboe map->queue_offset = qoff; 509e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 5103b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5114b04cc6aSJens Axboe else 5124b04cc6aSJens Axboe blk_mq_map_queues(map); 5133b6592f7SJens Axboe qoff += map->nr_queues; 5143b6592f7SJens Axboe offset += map->nr_queues; 5153b6592f7SJens Axboe } 5163b6592f7SJens Axboe 5173b6592f7SJens Axboe return 0; 518dca51e78SChristoph Hellwig } 519dca51e78SChristoph Hellwig 52004f3eafdSJens Axboe /* 52104f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 52204f3eafdSJens Axboe */ 52304f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 52404f3eafdSJens Axboe { 52504f3eafdSJens Axboe if (!write_sq) { 52604f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 52704f3eafdSJens Axboe 52804f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 52904f3eafdSJens Axboe next_tail = 0; 53004f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 53104f3eafdSJens Axboe return; 53204f3eafdSJens Axboe } 53304f3eafdSJens Axboe 53404f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 53504f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 53604f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 53704f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 53804f3eafdSJens Axboe } 53904f3eafdSJens Axboe 54057dacad5SJay Sternberg /** 54190ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 54257dacad5SJay Sternberg * @nvmeq: The queue to use 54357dacad5SJay Sternberg * @cmd: The command to send 54404f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 54557dacad5SJay Sternberg */ 54604f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 54704f3eafdSJens Axboe bool write_sq) 54857dacad5SJay Sternberg { 54990ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 55090ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 55190ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 55290ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 55304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 55404f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 55504f3eafdSJens Axboe } 55604f3eafdSJens Axboe 55704f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 55804f3eafdSJens Axboe { 55904f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 56004f3eafdSJens Axboe 56104f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 56204f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 56304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 56490ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 56557dacad5SJay Sternberg } 56657dacad5SJay Sternberg 567a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 56857dacad5SJay Sternberg { 569f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 570a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 57157dacad5SJay Sternberg } 57257dacad5SJay Sternberg 573955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 574955b1b5aSMinwoo Im { 575955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 57620469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 577955b1b5aSMinwoo Im unsigned int avg_seg_size; 578955b1b5aSMinwoo Im 57920469a37SKeith Busch if (nseg == 0) 58020469a37SKeith Busch return false; 58120469a37SKeith Busch 58220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 583955b1b5aSMinwoo Im 584955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 585955b1b5aSMinwoo Im return false; 586955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 587955b1b5aSMinwoo Im return false; 588955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 589955b1b5aSMinwoo Im return false; 590955b1b5aSMinwoo Im return true; 591955b1b5aSMinwoo Im } 592955b1b5aSMinwoo Im 593fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 59457dacad5SJay Sternberg { 595f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 596f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 597b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 598f4800d6dSChristoph Hellwig 599955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 600955b1b5aSMinwoo Im 601f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 602943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 603f4800d6dSChristoph Hellwig if (!iod->sg) 604fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 605f4800d6dSChristoph Hellwig } else { 606f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 60757dacad5SJay Sternberg } 60857dacad5SJay Sternberg 609f4800d6dSChristoph Hellwig iod->aborted = 0; 61057dacad5SJay Sternberg iod->npages = -1; 61157dacad5SJay Sternberg iod->nents = 0; 612f4800d6dSChristoph Hellwig iod->length = size; 613f80ec966SKeith Busch 614fc17b653SChristoph Hellwig return BLK_STS_OK; 61557dacad5SJay Sternberg } 61657dacad5SJay Sternberg 617f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 61857dacad5SJay Sternberg { 619f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 620a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 621a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 622a7a7cbe3SChaitanya Kulkarni 62357dacad5SJay Sternberg int i; 62457dacad5SJay Sternberg 62557dacad5SJay Sternberg if (iod->npages == 0) 626a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 627a7a7cbe3SChaitanya Kulkarni dma_addr); 628a7a7cbe3SChaitanya Kulkarni 62957dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 630a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 631a7a7cbe3SChaitanya Kulkarni 632a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 633a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 634a7a7cbe3SChaitanya Kulkarni 635a7a7cbe3SChaitanya Kulkarni next_dma_addr = 636a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 637a7a7cbe3SChaitanya Kulkarni } else { 638a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 639a7a7cbe3SChaitanya Kulkarni 640a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 641a7a7cbe3SChaitanya Kulkarni } 642a7a7cbe3SChaitanya Kulkarni 643a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 644a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 64557dacad5SJay Sternberg } 64657dacad5SJay Sternberg 647f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 648943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 64957dacad5SJay Sternberg } 65057dacad5SJay Sternberg 651d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 652d0877473SKeith Busch { 653d0877473SKeith Busch int i; 654d0877473SKeith Busch struct scatterlist *sg; 655d0877473SKeith Busch 656d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 657d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 658d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 659d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 660d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 661d0877473SKeith Busch sg_dma_len(sg)); 662d0877473SKeith Busch } 663d0877473SKeith Busch } 664d0877473SKeith Busch 665a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 666a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 66757dacad5SJay Sternberg { 668f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 66957dacad5SJay Sternberg struct dma_pool *pool; 670b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 67157dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 67257dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 67357dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6745fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 67557dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 67657dacad5SJay Sternberg __le64 *prp_list; 677a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 67857dacad5SJay Sternberg dma_addr_t prp_dma; 67957dacad5SJay Sternberg int nprps, i; 68057dacad5SJay Sternberg 68157dacad5SJay Sternberg length -= (page_size - offset); 6825228b328SJan H. Schönherr if (length <= 0) { 6835228b328SJan H. Schönherr iod->first_dma = 0; 684a7a7cbe3SChaitanya Kulkarni goto done; 6855228b328SJan H. Schönherr } 68657dacad5SJay Sternberg 68757dacad5SJay Sternberg dma_len -= (page_size - offset); 68857dacad5SJay Sternberg if (dma_len) { 68957dacad5SJay Sternberg dma_addr += (page_size - offset); 69057dacad5SJay Sternberg } else { 69157dacad5SJay Sternberg sg = sg_next(sg); 69257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69457dacad5SJay Sternberg } 69557dacad5SJay Sternberg 69657dacad5SJay Sternberg if (length <= page_size) { 69757dacad5SJay Sternberg iod->first_dma = dma_addr; 698a7a7cbe3SChaitanya Kulkarni goto done; 69957dacad5SJay Sternberg } 70057dacad5SJay Sternberg 70157dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 70257dacad5SJay Sternberg if (nprps <= (256 / 8)) { 70357dacad5SJay Sternberg pool = dev->prp_small_pool; 70457dacad5SJay Sternberg iod->npages = 0; 70557dacad5SJay Sternberg } else { 70657dacad5SJay Sternberg pool = dev->prp_page_pool; 70757dacad5SJay Sternberg iod->npages = 1; 70857dacad5SJay Sternberg } 70957dacad5SJay Sternberg 71069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 71157dacad5SJay Sternberg if (!prp_list) { 71257dacad5SJay Sternberg iod->first_dma = dma_addr; 71357dacad5SJay Sternberg iod->npages = -1; 71486eea289SKeith Busch return BLK_STS_RESOURCE; 71557dacad5SJay Sternberg } 71657dacad5SJay Sternberg list[0] = prp_list; 71757dacad5SJay Sternberg iod->first_dma = prp_dma; 71857dacad5SJay Sternberg i = 0; 71957dacad5SJay Sternberg for (;;) { 72057dacad5SJay Sternberg if (i == page_size >> 3) { 72157dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 72269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 72357dacad5SJay Sternberg if (!prp_list) 72486eea289SKeith Busch return BLK_STS_RESOURCE; 72557dacad5SJay Sternberg list[iod->npages++] = prp_list; 72657dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 72757dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 72857dacad5SJay Sternberg i = 1; 72957dacad5SJay Sternberg } 73057dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 73157dacad5SJay Sternberg dma_len -= page_size; 73257dacad5SJay Sternberg dma_addr += page_size; 73357dacad5SJay Sternberg length -= page_size; 73457dacad5SJay Sternberg if (length <= 0) 73557dacad5SJay Sternberg break; 73657dacad5SJay Sternberg if (dma_len > 0) 73757dacad5SJay Sternberg continue; 73886eea289SKeith Busch if (unlikely(dma_len < 0)) 73986eea289SKeith Busch goto bad_sgl; 74057dacad5SJay Sternberg sg = sg_next(sg); 74157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 74257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 74357dacad5SJay Sternberg } 74457dacad5SJay Sternberg 745a7a7cbe3SChaitanya Kulkarni done: 746a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 747a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 748a7a7cbe3SChaitanya Kulkarni 74986eea289SKeith Busch return BLK_STS_OK; 75086eea289SKeith Busch 75186eea289SKeith Busch bad_sgl: 752d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 753d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 754d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 75586eea289SKeith Busch return BLK_STS_IOERR; 75657dacad5SJay Sternberg } 75757dacad5SJay Sternberg 758a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 759a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 760a7a7cbe3SChaitanya Kulkarni { 761a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 762a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 763a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 764a7a7cbe3SChaitanya Kulkarni } 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 767a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 768a7a7cbe3SChaitanya Kulkarni { 769a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 770a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 771a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 772a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 773a7a7cbe3SChaitanya Kulkarni } else { 774a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 775a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 776a7a7cbe3SChaitanya Kulkarni } 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 780b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 781a7a7cbe3SChaitanya Kulkarni { 782a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 783a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 784a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 785a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 786a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 787b0f2853bSChristoph Hellwig int i = 0; 788a7a7cbe3SChaitanya Kulkarni 789a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 790a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 791a7a7cbe3SChaitanya Kulkarni 792b0f2853bSChristoph Hellwig if (entries == 1) { 793a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 794a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 795a7a7cbe3SChaitanya Kulkarni } 796a7a7cbe3SChaitanya Kulkarni 797a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 798a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 799a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 800a7a7cbe3SChaitanya Kulkarni } else { 801a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 802a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 803a7a7cbe3SChaitanya Kulkarni } 804a7a7cbe3SChaitanya Kulkarni 805a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 806a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 807a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 808a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 809a7a7cbe3SChaitanya Kulkarni } 810a7a7cbe3SChaitanya Kulkarni 811a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 812a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 813a7a7cbe3SChaitanya Kulkarni 814a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 815a7a7cbe3SChaitanya Kulkarni 816a7a7cbe3SChaitanya Kulkarni do { 817a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 818a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 819a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 820a7a7cbe3SChaitanya Kulkarni 821a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 822a7a7cbe3SChaitanya Kulkarni if (!sg_list) 823a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 824a7a7cbe3SChaitanya Kulkarni 825a7a7cbe3SChaitanya Kulkarni i = 0; 826a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 827a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 828a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 829a7a7cbe3SChaitanya Kulkarni } 830a7a7cbe3SChaitanya Kulkarni 831a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 832a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 833b0f2853bSChristoph Hellwig } while (--entries > 0); 834a7a7cbe3SChaitanya Kulkarni 835a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 836a7a7cbe3SChaitanya Kulkarni } 837a7a7cbe3SChaitanya Kulkarni 838fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 839b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84057dacad5SJay Sternberg { 841f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 842ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 843ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 844ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 845fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 846b0f2853bSChristoph Hellwig int nr_mapped; 84757dacad5SJay Sternberg 848f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 849ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 850ba1ca37eSChristoph Hellwig if (!iod->nents) 851ba1ca37eSChristoph Hellwig goto out; 852ba1ca37eSChristoph Hellwig 853fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 854e0596ab2SLogan Gunthorpe 855e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 856e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 857e0596ab2SLogan Gunthorpe dma_dir); 858e0596ab2SLogan Gunthorpe else 859e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 860e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 861b0f2853bSChristoph Hellwig if (!nr_mapped) 862ba1ca37eSChristoph Hellwig goto out; 863ba1ca37eSChristoph Hellwig 864955b1b5aSMinwoo Im if (iod->use_sgl) 865b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 866a7a7cbe3SChaitanya Kulkarni else 867a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 868a7a7cbe3SChaitanya Kulkarni 86986eea289SKeith Busch if (ret != BLK_STS_OK) 870ba1ca37eSChristoph Hellwig goto out_unmap; 871ba1ca37eSChristoph Hellwig 872fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 873ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 874ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 875ba1ca37eSChristoph Hellwig goto out_unmap; 876ba1ca37eSChristoph Hellwig 877bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 878bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 879ba1ca37eSChristoph Hellwig goto out_unmap; 880ba1ca37eSChristoph Hellwig 881bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 882ba1ca37eSChristoph Hellwig goto out_unmap; 8833045c0d0SChaitanya Kulkarni 8843045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 88557dacad5SJay Sternberg } 88657dacad5SJay Sternberg 887fc17b653SChristoph Hellwig return BLK_STS_OK; 888ba1ca37eSChristoph Hellwig 889ba1ca37eSChristoph Hellwig out_unmap: 890ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 891ba1ca37eSChristoph Hellwig out: 892ba1ca37eSChristoph Hellwig return ret; 89357dacad5SJay Sternberg } 89457dacad5SJay Sternberg 895f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 896d4f6c3abSChristoph Hellwig { 897f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 898d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 899d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 900d4f6c3abSChristoph Hellwig 901d4f6c3abSChristoph Hellwig if (iod->nents) { 902e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 903e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 904d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 905e0596ab2SLogan Gunthorpe 906f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 907bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 908d4f6c3abSChristoph Hellwig } 909d4f6c3abSChristoph Hellwig 910f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 911f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 91257dacad5SJay Sternberg } 91357dacad5SJay Sternberg 91457dacad5SJay Sternberg /* 91557dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91657dacad5SJay Sternberg */ 917fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91857dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91957dacad5SJay Sternberg { 92057dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 92157dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92357dacad5SJay Sternberg struct request *req = bd->rq; 924ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 925ebe6d874SChristoph Hellwig blk_status_t ret; 92657dacad5SJay Sternberg 927d1f06f4aSJens Axboe /* 928d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 929d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 930d1f06f4aSJens Axboe */ 9314e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 932d1f06f4aSJens Axboe return BLK_STS_IOERR; 933d1f06f4aSJens Axboe 934f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 935fc17b653SChristoph Hellwig if (ret) 936f4800d6dSChristoph Hellwig return ret; 93757dacad5SJay Sternberg 938b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 939fc17b653SChristoph Hellwig if (ret) 940f9d03f96SChristoph Hellwig goto out_free_cmd; 94157dacad5SJay Sternberg 942fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 943b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 944fc17b653SChristoph Hellwig if (ret) 945f9d03f96SChristoph Hellwig goto out_cleanup_iod; 946fc17b653SChristoph Hellwig } 947ba1ca37eSChristoph Hellwig 948aae239e1SChristoph Hellwig blk_mq_start_request(req); 94904f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 950fc17b653SChristoph Hellwig return BLK_STS_OK; 951f9d03f96SChristoph Hellwig out_cleanup_iod: 952f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 953f9d03f96SChristoph Hellwig out_free_cmd: 954f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 955ba1ca37eSChristoph Hellwig return ret; 95657dacad5SJay Sternberg } 95757dacad5SJay Sternberg 95877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 959eee417b0SChristoph Hellwig { 960f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 961eee417b0SChristoph Hellwig 96277f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 96377f02a7aSChristoph Hellwig nvme_complete_rq(req); 96457dacad5SJay Sternberg } 96557dacad5SJay Sternberg 966d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 967750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 968d783e0bdSMarta Rybczynska { 969750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 970750dde44SChristoph Hellwig nvmeq->cq_phase; 971d783e0bdSMarta Rybczynska } 972d783e0bdSMarta Rybczynska 973eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 97457dacad5SJay Sternberg { 975eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 97657dacad5SJay Sternberg 977eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 978eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 979eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 980eb281c82SSagi Grimberg } 981adf68f21SChristoph Hellwig 9825cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 98357dacad5SJay Sternberg { 9845cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 98557dacad5SJay Sternberg struct request *req; 986adf68f21SChristoph Hellwig 98783a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9881b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 989aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 99083a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 99183a12fb7SSagi Grimberg return; 992aae239e1SChristoph Hellwig } 993aae239e1SChristoph Hellwig 994adf68f21SChristoph Hellwig /* 995adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 996adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 997adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 998adf68f21SChristoph Hellwig * for them but rather special case them here. 999adf68f21SChristoph Hellwig */ 1000adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 100138dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 10027bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 100383a12fb7SSagi Grimberg cqe->status, &cqe->result); 1004a0fa9647SJens Axboe return; 100557dacad5SJay Sternberg } 100657dacad5SJay Sternberg 100783a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 100883a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 100983a12fb7SSagi Grimberg } 101057dacad5SJay Sternberg 10115cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 101283a12fb7SSagi Grimberg { 10135cb525c8SJens Axboe while (start != end) { 10145cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10155cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10165cb525c8SJens Axboe start = 0; 10175cb525c8SJens Axboe } 10185cb525c8SJens Axboe } 101983a12fb7SSagi Grimberg 10205cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10215cb525c8SJens Axboe { 1022920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 1023920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1024920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1025920d13a8SSagi Grimberg } 1026a0fa9647SJens Axboe } 1027a0fa9647SJens Axboe 10281052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10291052b8acSJens Axboe u16 *end, unsigned int tag) 1030a0fa9647SJens Axboe { 10311052b8acSJens Axboe int found = 0; 103283a12fb7SSagi Grimberg 10335cb525c8SJens Axboe *start = nvmeq->cq_head; 10341052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10351052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10361052b8acSJens Axboe found++; 10375cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 103857dacad5SJay Sternberg } 10395cb525c8SJens Axboe *end = nvmeq->cq_head; 104057dacad5SJay Sternberg 10415cb525c8SJens Axboe if (*start != *end) 1042eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10435cb525c8SJens Axboe return found; 104457dacad5SJay Sternberg } 104557dacad5SJay Sternberg 104657dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 104757dacad5SJay Sternberg { 104857dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 104968fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10505cb525c8SJens Axboe u16 start, end; 10515cb525c8SJens Axboe 10521ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 105368fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 105468fa9dbeSJens Axboe ret = IRQ_HANDLED; 10555cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 105668fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10571ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 10585cb525c8SJens Axboe 105968fa9dbeSJens Axboe if (start != end) { 10605cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10615cb525c8SJens Axboe return IRQ_HANDLED; 106257dacad5SJay Sternberg } 106357dacad5SJay Sternberg 106468fa9dbeSJens Axboe return ret; 106557dacad5SJay Sternberg } 106657dacad5SJay Sternberg 106757dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 106857dacad5SJay Sternberg { 106957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1070750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107157dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1072d783e0bdSMarta Rybczynska return IRQ_NONE; 107357dacad5SJay Sternberg } 107457dacad5SJay Sternberg 10757776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1076a0fa9647SJens Axboe { 10775cb525c8SJens Axboe u16 start, end; 10781052b8acSJens Axboe int found; 1079a0fa9647SJens Axboe 1080750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 1081442e19b7SSagi Grimberg return 0; 1082442e19b7SSagi Grimberg 10831ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 10845cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10851ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 1086442e19b7SSagi Grimberg 10875cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1088442e19b7SSagi Grimberg return found; 1089a0fa9647SJens Axboe } 1090a0fa9647SJens Axboe 10919743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10927776db1cSKeith Busch { 10937776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1094dabcefabSJens Axboe u16 start, end; 1095dabcefabSJens Axboe bool found; 1096dabcefabSJens Axboe 1097dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1098dabcefabSJens Axboe return 0; 1099dabcefabSJens Axboe 1100dabcefabSJens Axboe spin_lock(&nvmeq->cq_lock); 11019743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 1102dabcefabSJens Axboe spin_unlock(&nvmeq->cq_lock); 1103dabcefabSJens Axboe 1104dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1105dabcefabSJens Axboe return found; 1106dabcefabSJens Axboe } 1107dabcefabSJens Axboe 1108ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 110957dacad5SJay Sternberg { 1110f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1111147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 111257dacad5SJay Sternberg struct nvme_command c; 111357dacad5SJay Sternberg 111457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1116ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 111704f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 111857dacad5SJay Sternberg } 111957dacad5SJay Sternberg 112057dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 112157dacad5SJay Sternberg { 112257dacad5SJay Sternberg struct nvme_command c; 112357dacad5SJay Sternberg 112457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112557dacad5SJay Sternberg c.delete_queue.opcode = opcode; 112657dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 112757dacad5SJay Sternberg 11281c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112957dacad5SJay Sternberg } 113057dacad5SJay Sternberg 113157dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1132a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 113357dacad5SJay Sternberg { 113457dacad5SJay Sternberg struct nvme_command c; 11354b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11364b04cc6aSJens Axboe 11374b04cc6aSJens Axboe if (vector != -1) 11384b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg /* 114116772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 114257dacad5SJay Sternberg * is attached to the request. 114357dacad5SJay Sternberg */ 114457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 114557dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 114657dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 114757dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 114857dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 114957dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 11504b04cc6aSJens Axboe if (vector != -1) 1151a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 11524b04cc6aSJens Axboe else 11534b04cc6aSJens Axboe c.create_cq.irq_vector = 0; 115457dacad5SJay Sternberg 11551c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115657dacad5SJay Sternberg } 115757dacad5SJay Sternberg 115857dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 115957dacad5SJay Sternberg struct nvme_queue *nvmeq) 116057dacad5SJay Sternberg { 11619abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 116257dacad5SJay Sternberg struct nvme_command c; 116381c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 116457dacad5SJay Sternberg 116557dacad5SJay Sternberg /* 11669abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11679abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11689abd68efSJens Axboe * URGENT. 11699abd68efSJens Axboe */ 11709abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11719abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11729abd68efSJens Axboe 11739abd68efSJens Axboe /* 117416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117557dacad5SJay Sternberg * is attached to the request. 117657dacad5SJay Sternberg */ 117757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 117857dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 117957dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 118057dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 118157dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 118257dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 118357dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 118457dacad5SJay Sternberg 11851c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 118657dacad5SJay Sternberg } 118757dacad5SJay Sternberg 118857dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 118957dacad5SJay Sternberg { 119057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 119157dacad5SJay Sternberg } 119257dacad5SJay Sternberg 119357dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 119457dacad5SJay Sternberg { 119557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 119657dacad5SJay Sternberg } 119757dacad5SJay Sternberg 11982a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 119957dacad5SJay Sternberg { 1200f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1201f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 120257dacad5SJay Sternberg 120327fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 120427fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1205e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1206e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 120757dacad5SJay Sternberg } 120857dacad5SJay Sternberg 1209b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1210b2a0eb1aSKeith Busch { 1211b2a0eb1aSKeith Busch 1212b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1213b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1214b2a0eb1aSKeith Busch */ 1215b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1216b2a0eb1aSKeith Busch 1217ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1218ad70062cSJianchao Wang switch (dev->ctrl.state) { 1219ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1220ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1221b2a0eb1aSKeith Busch return false; 1222ad70062cSJianchao Wang default: 1223ad70062cSJianchao Wang break; 1224ad70062cSJianchao Wang } 1225b2a0eb1aSKeith Busch 1226b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1227b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1228b2a0eb1aSKeith Busch */ 1229b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1230b2a0eb1aSKeith Busch return false; 1231b2a0eb1aSKeith Busch 1232b2a0eb1aSKeith Busch return true; 1233b2a0eb1aSKeith Busch } 1234b2a0eb1aSKeith Busch 1235b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1236b2a0eb1aSKeith Busch { 1237b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1238b2a0eb1aSKeith Busch u16 pci_status; 1239b2a0eb1aSKeith Busch int result; 1240b2a0eb1aSKeith Busch 1241b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1242b2a0eb1aSKeith Busch &pci_status); 1243b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1244b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1245b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1246b2a0eb1aSKeith Busch csts, pci_status); 1247b2a0eb1aSKeith Busch else 1248b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1249b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1250b2a0eb1aSKeith Busch csts, result); 1251b2a0eb1aSKeith Busch } 1252b2a0eb1aSKeith Busch 125331c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 125457dacad5SJay Sternberg { 1255f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1256f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 125757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 125857dacad5SJay Sternberg struct request *abort_req; 125957dacad5SJay Sternberg struct nvme_command cmd; 1260b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1261b2a0eb1aSKeith Busch 1262651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1263651438bbSWen Xiong * the recovery mechanism will surely fail. 1264651438bbSWen Xiong */ 1265651438bbSWen Xiong mb(); 1266651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1267651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1268651438bbSWen Xiong 1269b2a0eb1aSKeith Busch /* 1270b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1271b2a0eb1aSKeith Busch */ 1272b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1273b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1274b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1275d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1276db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1277b2a0eb1aSKeith Busch } 127857dacad5SJay Sternberg 127931c7c7d2SChristoph Hellwig /* 12807776db1cSKeith Busch * Did we miss an interrupt? 12817776db1cSKeith Busch */ 12827776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12837776db1cSKeith Busch dev_warn(dev->ctrl.device, 12847776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12857776db1cSKeith Busch req->tag, nvmeq->qid); 1286db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12877776db1cSKeith Busch } 12887776db1cSKeith Busch 12897776db1cSKeith Busch /* 1290fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1291fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1292fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1293db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1294fd634f41SChristoph Hellwig */ 12954244140dSKeith Busch switch (dev->ctrl.state) { 12964244140dSKeith Busch case NVME_CTRL_CONNECTING: 12974244140dSKeith Busch case NVME_CTRL_RESETTING: 1298b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1299fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1300fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1301a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 130227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1303db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13044244140dSKeith Busch default: 13054244140dSKeith Busch break; 1306fd634f41SChristoph Hellwig } 1307fd634f41SChristoph Hellwig 1308fd634f41SChristoph Hellwig /* 1309e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1310e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1311e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 131231c7c7d2SChristoph Hellwig */ 1313f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13141b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 131557dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 131657dacad5SJay Sternberg req->tag, nvmeq->qid); 1317a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1318d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1319e1569a16SKeith Busch 132027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1321db8c48e4SChristoph Hellwig return BLK_EH_DONE; 132257dacad5SJay Sternberg } 132357dacad5SJay Sternberg 1324e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1325e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1326e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1327e7a2a87dSChristoph Hellwig } 13287bf7d778SKeith Busch iod->aborted = 1; 132957dacad5SJay Sternberg 133057dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 133157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 133257dacad5SJay Sternberg cmd.abort.cid = req->tag; 133357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 133457dacad5SJay Sternberg 13351b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13361b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 133757dacad5SJay Sternberg req->tag, nvmeq->qid); 1338e7a2a87dSChristoph Hellwig 1339e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1340eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13416bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13426bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 134331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 134457dacad5SJay Sternberg } 134557dacad5SJay Sternberg 1346e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1347e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1348e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 134957dacad5SJay Sternberg 135057dacad5SJay Sternberg /* 135157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 135257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 135357dacad5SJay Sternberg * as the device then is in a faulty state. 135457dacad5SJay Sternberg */ 135557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 135657dacad5SJay Sternberg } 135757dacad5SJay Sternberg 135857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 135957dacad5SJay Sternberg { 136057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 136157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 136263223078SChristoph Hellwig if (!nvmeq->sq_cmds) 136363223078SChristoph Hellwig return; 13640f238ff5SLogan Gunthorpe 136563223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 13660f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 136763223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 136863223078SChristoph Hellwig } else { 136963223078SChristoph Hellwig dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 137063223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13710f238ff5SLogan Gunthorpe } 137257dacad5SJay Sternberg } 137357dacad5SJay Sternberg 137457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 137557dacad5SJay Sternberg { 137657dacad5SJay Sternberg int i; 137757dacad5SJay Sternberg 1378d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1379d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1380147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 138157dacad5SJay Sternberg } 138257dacad5SJay Sternberg } 138357dacad5SJay Sternberg 138457dacad5SJay Sternberg /** 138557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 138640581d1aSBart Van Assche * @nvmeq: queue to suspend 138757dacad5SJay Sternberg */ 138857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 138957dacad5SJay Sternberg { 13904e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 139157dacad5SJay Sternberg return 1; 139257dacad5SJay Sternberg 13934e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1394d1f06f4aSJens Axboe mb(); 139557dacad5SJay Sternberg 13964e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13971c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1398c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13994e224106SChristoph Hellwig if (nvmeq->cq_vector == -1) 14004e224106SChristoph Hellwig return 0; 14014e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 14024e224106SChristoph Hellwig nvmeq->cq_vector = -1; 140357dacad5SJay Sternberg return 0; 140457dacad5SJay Sternberg } 140557dacad5SJay Sternberg 1406a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 140757dacad5SJay Sternberg { 1408147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 14095cb525c8SJens Axboe u16 start, end; 141057dacad5SJay Sternberg 1411a5cdb68cSKeith Busch if (shutdown) 1412a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1413a5cdb68cSKeith Busch else 141420d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 141557dacad5SJay Sternberg 14161ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 14175cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 14181ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 14195cb525c8SJens Axboe 14205cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 142157dacad5SJay Sternberg } 142257dacad5SJay Sternberg 142357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 142457dacad5SJay Sternberg int entry_size) 142557dacad5SJay Sternberg { 142657dacad5SJay Sternberg int q_depth = dev->q_depth; 14275fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14285fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 142957dacad5SJay Sternberg 143057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 143157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14325fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 143357dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 143457dacad5SJay Sternberg 143557dacad5SJay Sternberg /* 143657dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 143757dacad5SJay Sternberg * would be better to map queues in system memory with the 143857dacad5SJay Sternberg * original depth 143957dacad5SJay Sternberg */ 144057dacad5SJay Sternberg if (q_depth < 64) 144157dacad5SJay Sternberg return -ENOMEM; 144257dacad5SJay Sternberg } 144357dacad5SJay Sternberg 144457dacad5SJay Sternberg return q_depth; 144557dacad5SJay Sternberg } 144657dacad5SJay Sternberg 144757dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 144857dacad5SJay Sternberg int qid, int depth) 144957dacad5SJay Sternberg { 14500f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1451815c6704SKeith Busch 14520f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14530f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14540f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14550f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 145663223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 145763223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 145863223078SChristoph Hellwig return 0; 145963223078SChristoph Hellwig } 14600f238ff5SLogan Gunthorpe } 14610f238ff5SLogan Gunthorpe 146257dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 146357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 146457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 146557dacad5SJay Sternberg return -ENOMEM; 146657dacad5SJay Sternberg return 0; 146757dacad5SJay Sternberg } 146857dacad5SJay Sternberg 1469a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 147057dacad5SJay Sternberg { 1471147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 147257dacad5SJay Sternberg 147362314e40SKeith Busch if (dev->ctrl.queue_count > qid) 147462314e40SKeith Busch return 0; 147557dacad5SJay Sternberg 147657dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 147757dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 147857dacad5SJay Sternberg if (!nvmeq->cqes) 147957dacad5SJay Sternberg goto free_nvmeq; 148057dacad5SJay Sternberg 148157dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 148257dacad5SJay Sternberg goto free_cqdma; 148357dacad5SJay Sternberg 148457dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 148557dacad5SJay Sternberg nvmeq->dev = dev; 14861ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14871ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 148857dacad5SJay Sternberg nvmeq->cq_head = 0; 148957dacad5SJay Sternberg nvmeq->cq_phase = 1; 149057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 149157dacad5SJay Sternberg nvmeq->q_depth = depth; 149257dacad5SJay Sternberg nvmeq->qid = qid; 149357dacad5SJay Sternberg nvmeq->cq_vector = -1; 1494d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 149557dacad5SJay Sternberg 1496147b27e4SSagi Grimberg return 0; 149757dacad5SJay Sternberg 149857dacad5SJay Sternberg free_cqdma: 149957dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 150057dacad5SJay Sternberg nvmeq->cq_dma_addr); 150157dacad5SJay Sternberg free_nvmeq: 1502147b27e4SSagi Grimberg return -ENOMEM; 150357dacad5SJay Sternberg } 150457dacad5SJay Sternberg 1505dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 150657dacad5SJay Sternberg { 15070ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15080ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15090ff199cbSChristoph Hellwig 15100ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15110ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15120ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15130ff199cbSChristoph Hellwig } else { 15140ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15150ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15160ff199cbSChristoph Hellwig } 151757dacad5SJay Sternberg } 151857dacad5SJay Sternberg 151957dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 152057dacad5SJay Sternberg { 152157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 152257dacad5SJay Sternberg 15231ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 152457dacad5SJay Sternberg nvmeq->sq_tail = 0; 152504f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 152657dacad5SJay Sternberg nvmeq->cq_head = 0; 152757dacad5SJay Sternberg nvmeq->cq_phase = 1; 152857dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 152957dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1530f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 153157dacad5SJay Sternberg dev->online_queues++; 15321ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 153357dacad5SJay Sternberg } 153457dacad5SJay Sternberg 15354b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 153657dacad5SJay Sternberg { 153757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153857dacad5SJay Sternberg int result; 1539a8e3e0bbSJianchao Wang s16 vector; 154057dacad5SJay Sternberg 154122b55601SKeith Busch /* 154222b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 154322b55601SKeith Busch * has only one vector available. 154422b55601SKeith Busch */ 15454b04cc6aSJens Axboe if (!polled) 1546a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15474b04cc6aSJens Axboe else 15484b04cc6aSJens Axboe vector = -1; 15494b04cc6aSJens Axboe 1550a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1551ded45505SKeith Busch if (result) 1552ded45505SKeith Busch return result; 155357dacad5SJay Sternberg 155457dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 155557dacad5SJay Sternberg if (result < 0) 1556ded45505SKeith Busch return result; 1557ded45505SKeith Busch else if (result) 155857dacad5SJay Sternberg goto release_cq; 155957dacad5SJay Sternberg 1560a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1561161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15624b04cc6aSJens Axboe 15634b04cc6aSJens Axboe if (vector != -1) { 1564dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 156557dacad5SJay Sternberg if (result < 0) 156657dacad5SJay Sternberg goto release_sq; 15674b04cc6aSJens Axboe } 156857dacad5SJay Sternberg 15694e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 157057dacad5SJay Sternberg return result; 157157dacad5SJay Sternberg 157257dacad5SJay Sternberg release_sq: 1573a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1574f25a2dfcSJianchao Wang dev->online_queues--; 157557dacad5SJay Sternberg adapter_delete_sq(dev, qid); 157657dacad5SJay Sternberg release_cq: 157757dacad5SJay Sternberg adapter_delete_cq(dev, qid); 157857dacad5SJay Sternberg return result; 157957dacad5SJay Sternberg } 158057dacad5SJay Sternberg 1581f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 158257dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158377f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 158457dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 158557dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15860350815aSChristoph Hellwig .init_request = nvme_init_request, 158757dacad5SJay Sternberg .timeout = nvme_timeout, 158857dacad5SJay Sternberg }; 158957dacad5SJay Sternberg 1590dabcefabSJens Axboe #define NVME_SHARED_MQ_OPS \ 1591dabcefabSJens Axboe .queue_rq = nvme_queue_rq, \ 159204f3eafdSJens Axboe .commit_rqs = nvme_commit_rqs, \ 1593dabcefabSJens Axboe .complete = nvme_pci_complete_rq, \ 1594dabcefabSJens Axboe .init_hctx = nvme_init_hctx, \ 1595dabcefabSJens Axboe .init_request = nvme_init_request, \ 1596dabcefabSJens Axboe .map_queues = nvme_pci_map_queues, \ 1597dabcefabSJens Axboe .timeout = nvme_timeout \ 1598dabcefabSJens Axboe 1599f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1600dabcefabSJens Axboe NVME_SHARED_MQ_OPS, 160157dacad5SJay Sternberg }; 160257dacad5SJay Sternberg 1603c6d962aeSChristoph Hellwig static const struct blk_mq_ops nvme_mq_poll_ops = { 1604dabcefabSJens Axboe NVME_SHARED_MQ_OPS, 1605c6d962aeSChristoph Hellwig .poll = nvme_poll, 1606dabcefabSJens Axboe }; 1607dabcefabSJens Axboe 160857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 160957dacad5SJay Sternberg { 16101c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 161169d9a99cSKeith Busch /* 161269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 161369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 161469d9a99cSKeith Busch * queue to flush these to completion. 161569d9a99cSKeith Busch */ 1616c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16171c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 161857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 161957dacad5SJay Sternberg } 162057dacad5SJay Sternberg } 162157dacad5SJay Sternberg 162257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 162357dacad5SJay Sternberg { 16241c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 162557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 162657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1627e3e9d50cSKeith Busch 162838dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 162957dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 163057dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1631a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1632d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 163357dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 163457dacad5SJay Sternberg 163557dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 163657dacad5SJay Sternberg return -ENOMEM; 163734b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 163857dacad5SJay Sternberg 16391c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16401c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 164157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 164257dacad5SJay Sternberg return -ENOMEM; 164357dacad5SJay Sternberg } 16441c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 164557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16461c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 164757dacad5SJay Sternberg return -ENODEV; 164857dacad5SJay Sternberg } 164957dacad5SJay Sternberg } else 1650c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 165157dacad5SJay Sternberg 165257dacad5SJay Sternberg return 0; 165357dacad5SJay Sternberg } 165457dacad5SJay Sternberg 165597f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 165697f6ef64SXu Yu { 165797f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 165897f6ef64SXu Yu } 165997f6ef64SXu Yu 166097f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 166197f6ef64SXu Yu { 166297f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 166397f6ef64SXu Yu 166497f6ef64SXu Yu if (size <= dev->bar_mapped_size) 166597f6ef64SXu Yu return 0; 166697f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 166797f6ef64SXu Yu return -ENOMEM; 166897f6ef64SXu Yu if (dev->bar) 166997f6ef64SXu Yu iounmap(dev->bar); 167097f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 167197f6ef64SXu Yu if (!dev->bar) { 167297f6ef64SXu Yu dev->bar_mapped_size = 0; 167397f6ef64SXu Yu return -ENOMEM; 167497f6ef64SXu Yu } 167597f6ef64SXu Yu dev->bar_mapped_size = size; 167697f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 167797f6ef64SXu Yu 167897f6ef64SXu Yu return 0; 167997f6ef64SXu Yu } 168097f6ef64SXu Yu 168101ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 168257dacad5SJay Sternberg { 168357dacad5SJay Sternberg int result; 168457dacad5SJay Sternberg u32 aqa; 168557dacad5SJay Sternberg struct nvme_queue *nvmeq; 168657dacad5SJay Sternberg 168797f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 168897f6ef64SXu Yu if (result < 0) 168997f6ef64SXu Yu return result; 169097f6ef64SXu Yu 16918ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 169220d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 169357dacad5SJay Sternberg 16947a67cbeaSChristoph Hellwig if (dev->subsystem && 16957a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16967a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 169757dacad5SJay Sternberg 169820d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 169957dacad5SJay Sternberg if (result < 0) 170057dacad5SJay Sternberg return result; 170157dacad5SJay Sternberg 1702a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1703147b27e4SSagi Grimberg if (result) 1704147b27e4SSagi Grimberg return result; 170557dacad5SJay Sternberg 1706147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 170757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 170857dacad5SJay Sternberg aqa |= aqa << 16; 170957dacad5SJay Sternberg 17107a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17117a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17127a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 171357dacad5SJay Sternberg 171420d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 171557dacad5SJay Sternberg if (result) 1716d4875622SKeith Busch return result; 171757dacad5SJay Sternberg 171857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1719161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1720dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 172157dacad5SJay Sternberg if (result) { 172257dacad5SJay Sternberg nvmeq->cq_vector = -1; 1723d4875622SKeith Busch return result; 172457dacad5SJay Sternberg } 172557dacad5SJay Sternberg 17264e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 172757dacad5SJay Sternberg return result; 172857dacad5SJay Sternberg } 172957dacad5SJay Sternberg 1730749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 173157dacad5SJay Sternberg { 17324b04cc6aSJens Axboe unsigned i, max, rw_queues; 1733749941f2SChristoph Hellwig int ret = 0; 173457dacad5SJay Sternberg 1735d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1736a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1737749941f2SChristoph Hellwig ret = -ENOMEM; 173857dacad5SJay Sternberg break; 1739749941f2SChristoph Hellwig } 1740749941f2SChristoph Hellwig } 174157dacad5SJay Sternberg 1742d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1743e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1744e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1745e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17464b04cc6aSJens Axboe } else { 17474b04cc6aSJens Axboe rw_queues = max; 17484b04cc6aSJens Axboe } 17494b04cc6aSJens Axboe 1750949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17514b04cc6aSJens Axboe bool polled = i > rw_queues; 17524b04cc6aSJens Axboe 17534b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1754d4875622SKeith Busch if (ret) 175557dacad5SJay Sternberg break; 175657dacad5SJay Sternberg } 175757dacad5SJay Sternberg 1758749941f2SChristoph Hellwig /* 1759749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17608adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17618adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1762749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1763749941f2SChristoph Hellwig */ 1764749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 176557dacad5SJay Sternberg } 176657dacad5SJay Sternberg 1767202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1768202021c1SStephen Bates struct device_attribute *attr, 1769202021c1SStephen Bates char *buf) 1770202021c1SStephen Bates { 1771202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1772202021c1SStephen Bates 1773c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1774202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1775202021c1SStephen Bates } 1776202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1777202021c1SStephen Bates 177888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 177957dacad5SJay Sternberg { 178088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 178188de4598SChristoph Hellwig 178288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 178388de4598SChristoph Hellwig } 178488de4598SChristoph Hellwig 178588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 178688de4598SChristoph Hellwig { 178788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 178888de4598SChristoph Hellwig } 178988de4598SChristoph Hellwig 1790f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 179157dacad5SJay Sternberg { 179288de4598SChristoph Hellwig u64 size, offset; 179357dacad5SJay Sternberg resource_size_t bar_size; 179457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17958969f1f8SChristoph Hellwig int bar; 179657dacad5SJay Sternberg 17979fe5c59fSKeith Busch if (dev->cmb_size) 17989fe5c59fSKeith Busch return; 17999fe5c59fSKeith Busch 18007a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1801f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1802f65efd6dSChristoph Hellwig return; 1803202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 180457dacad5SJay Sternberg 180588de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 180688de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18078969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18088969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 180957dacad5SJay Sternberg 181057dacad5SJay Sternberg if (offset > bar_size) 1811f65efd6dSChristoph Hellwig return; 181257dacad5SJay Sternberg 181357dacad5SJay Sternberg /* 181457dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 181557dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 181657dacad5SJay Sternberg * the reported size of the BAR 181757dacad5SJay Sternberg */ 181857dacad5SJay Sternberg if (size > bar_size - offset) 181957dacad5SJay Sternberg size = bar_size - offset; 182057dacad5SJay Sternberg 18210f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18220f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18230f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1824f65efd6dSChristoph Hellwig return; 18250f238ff5SLogan Gunthorpe } 18260f238ff5SLogan Gunthorpe 182757dacad5SJay Sternberg dev->cmb_size = size; 18280f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18290f238ff5SLogan Gunthorpe 18300f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18310f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18320f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1833f65efd6dSChristoph Hellwig 1834f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1835f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1836f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1837f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 183857dacad5SJay Sternberg } 183957dacad5SJay Sternberg 184057dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 184157dacad5SJay Sternberg { 18420f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1843f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1844f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18450f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1846f63572dfSJon Derrick } 184757dacad5SJay Sternberg } 184857dacad5SJay Sternberg 184987ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 185057dacad5SJay Sternberg { 18514033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 185287ad72a5SChristoph Hellwig struct nvme_command c; 185387ad72a5SChristoph Hellwig int ret; 185487ad72a5SChristoph Hellwig 185587ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 185687ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 185787ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 185887ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 185987ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 186087ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 186187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 186287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 186387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 186487ad72a5SChristoph Hellwig 186587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 186687ad72a5SChristoph Hellwig if (ret) { 186787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 186887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 186987ad72a5SChristoph Hellwig ret, bits); 187087ad72a5SChristoph Hellwig } 187187ad72a5SChristoph Hellwig return ret; 187287ad72a5SChristoph Hellwig } 187387ad72a5SChristoph Hellwig 187487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 187587ad72a5SChristoph Hellwig { 187687ad72a5SChristoph Hellwig int i; 187787ad72a5SChristoph Hellwig 187887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 187987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 188087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 188187ad72a5SChristoph Hellwig 188287ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 188387ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 188487ad72a5SChristoph Hellwig } 188587ad72a5SChristoph Hellwig 188687ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 188787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18884033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18894033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18904033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 189187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18927e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 189387ad72a5SChristoph Hellwig } 189487ad72a5SChristoph Hellwig 189592dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 189692dc6895SChristoph Hellwig u32 chunk_size) 189787ad72a5SChristoph Hellwig { 189887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 189992dc6895SChristoph Hellwig u32 max_entries, len; 19004033f35dSChristoph Hellwig dma_addr_t descs_dma; 19012ee0e4edSDan Carpenter int i = 0; 190287ad72a5SChristoph Hellwig void **bufs; 19036fbcde66SMinwoo Im u64 size, tmp; 190487ad72a5SChristoph Hellwig 190587ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 190687ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 190787ad72a5SChristoph Hellwig max_entries = tmp; 1908044a9df1SChristoph Hellwig 1909044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1910044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1911044a9df1SChristoph Hellwig 19124033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 19134033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 191487ad72a5SChristoph Hellwig if (!descs) 191587ad72a5SChristoph Hellwig goto out; 191687ad72a5SChristoph Hellwig 191787ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 191887ad72a5SChristoph Hellwig if (!bufs) 191987ad72a5SChristoph Hellwig goto out_free_descs; 192087ad72a5SChristoph Hellwig 1921244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 192287ad72a5SChristoph Hellwig dma_addr_t dma_addr; 192387ad72a5SChristoph Hellwig 192450cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 192587ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 192687ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192787ad72a5SChristoph Hellwig if (!bufs[i]) 192887ad72a5SChristoph Hellwig break; 192987ad72a5SChristoph Hellwig 193087ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 193187ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 193287ad72a5SChristoph Hellwig i++; 193387ad72a5SChristoph Hellwig } 193487ad72a5SChristoph Hellwig 193592dc6895SChristoph Hellwig if (!size) 193687ad72a5SChristoph Hellwig goto out_free_bufs; 193787ad72a5SChristoph Hellwig 193887ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 193987ad72a5SChristoph Hellwig dev->host_mem_size = size; 194087ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19414033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 194287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 194387ad72a5SChristoph Hellwig return 0; 194487ad72a5SChristoph Hellwig 194587ad72a5SChristoph Hellwig out_free_bufs: 194687ad72a5SChristoph Hellwig while (--i >= 0) { 194787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 194887ad72a5SChristoph Hellwig 194987ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 195087ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 195187ad72a5SChristoph Hellwig } 195287ad72a5SChristoph Hellwig 195387ad72a5SChristoph Hellwig kfree(bufs); 195487ad72a5SChristoph Hellwig out_free_descs: 19554033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19564033f35dSChristoph Hellwig descs_dma); 195787ad72a5SChristoph Hellwig out: 195887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 195987ad72a5SChristoph Hellwig return -ENOMEM; 196087ad72a5SChristoph Hellwig } 196187ad72a5SChristoph Hellwig 196292dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 196392dc6895SChristoph Hellwig { 196492dc6895SChristoph Hellwig u32 chunk_size; 196592dc6895SChristoph Hellwig 196692dc6895SChristoph Hellwig /* start big and work our way down */ 196730f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1968044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 196992dc6895SChristoph Hellwig chunk_size /= 2) { 197092dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197192dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 197292dc6895SChristoph Hellwig return 0; 197392dc6895SChristoph Hellwig nvme_free_host_mem(dev); 197492dc6895SChristoph Hellwig } 197592dc6895SChristoph Hellwig } 197692dc6895SChristoph Hellwig 197792dc6895SChristoph Hellwig return -ENOMEM; 197892dc6895SChristoph Hellwig } 197992dc6895SChristoph Hellwig 19809620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198187ad72a5SChristoph Hellwig { 198287ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 198387ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 198487ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 198587ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19866fbcde66SMinwoo Im int ret; 198787ad72a5SChristoph Hellwig 198887ad72a5SChristoph Hellwig preferred = min(preferred, max); 198987ad72a5SChristoph Hellwig if (min > max) { 199087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 199287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 199387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19949620cfbaSChristoph Hellwig return 0; 199587ad72a5SChristoph Hellwig } 199687ad72a5SChristoph Hellwig 199787ad72a5SChristoph Hellwig /* 199887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 199987ad72a5SChristoph Hellwig */ 200087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 200287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 200387ad72a5SChristoph Hellwig else 200487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 200587ad72a5SChristoph Hellwig } 200687ad72a5SChristoph Hellwig 200787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 200892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 200992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 201092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20119620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 201287ad72a5SChristoph Hellwig } 201387ad72a5SChristoph Hellwig 201492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 201592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 201692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 201792dc6895SChristoph Hellwig } 201892dc6895SChristoph Hellwig 20199620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20209620cfbaSChristoph Hellwig if (ret) 202187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20229620cfbaSChristoph Hellwig return ret; 202357dacad5SJay Sternberg } 202457dacad5SJay Sternberg 20253b6592f7SJens Axboe static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int nr_io_queues) 20263b6592f7SJens Axboe { 20273b6592f7SJens Axboe unsigned int this_w_queues = write_queues; 20284b04cc6aSJens Axboe unsigned int this_p_queues = poll_queues; 20293b6592f7SJens Axboe 20303b6592f7SJens Axboe /* 20313b6592f7SJens Axboe * Setup read/write queue split 20323b6592f7SJens Axboe */ 20333b6592f7SJens Axboe if (nr_io_queues == 1) { 2034e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2035e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 2036e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL] = 0; 20373b6592f7SJens Axboe return; 20383b6592f7SJens Axboe } 20393b6592f7SJens Axboe 20403b6592f7SJens Axboe /* 20414b04cc6aSJens Axboe * Configure number of poll queues, if set 20424b04cc6aSJens Axboe */ 20434b04cc6aSJens Axboe if (this_p_queues) { 20444b04cc6aSJens Axboe /* 20454b04cc6aSJens Axboe * We need at least one queue left. With just one queue, we'll 20464b04cc6aSJens Axboe * have a single shared read/write set. 20474b04cc6aSJens Axboe */ 20484b04cc6aSJens Axboe if (this_p_queues >= nr_io_queues) { 20494b04cc6aSJens Axboe this_w_queues = 0; 20504b04cc6aSJens Axboe this_p_queues = nr_io_queues - 1; 20514b04cc6aSJens Axboe } 20524b04cc6aSJens Axboe 2053e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20544b04cc6aSJens Axboe nr_io_queues -= this_p_queues; 20554b04cc6aSJens Axboe } else 2056e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL] = 0; 20574b04cc6aSJens Axboe 20584b04cc6aSJens Axboe /* 20593b6592f7SJens Axboe * If 'write_queues' is set, ensure it leaves room for at least 20603b6592f7SJens Axboe * one read queue 20613b6592f7SJens Axboe */ 20623b6592f7SJens Axboe if (this_w_queues >= nr_io_queues) 20633b6592f7SJens Axboe this_w_queues = nr_io_queues - 1; 20643b6592f7SJens Axboe 20653b6592f7SJens Axboe /* 20663b6592f7SJens Axboe * If 'write_queues' is set to zero, reads and writes will share 20673b6592f7SJens Axboe * a queue set. 20683b6592f7SJens Axboe */ 20693b6592f7SJens Axboe if (!this_w_queues) { 2070e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = nr_io_queues; 2071e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 20723b6592f7SJens Axboe } else { 2073e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues; 2074e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = nr_io_queues - this_w_queues; 20753b6592f7SJens Axboe } 20763b6592f7SJens Axboe } 20773b6592f7SJens Axboe 20783b6592f7SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, int nr_io_queues) 20793b6592f7SJens Axboe { 20803b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20813b6592f7SJens Axboe int irq_sets[2]; 20823b6592f7SJens Axboe struct irq_affinity affd = { 20833b6592f7SJens Axboe .pre_vectors = 1, 20843b6592f7SJens Axboe .nr_sets = ARRAY_SIZE(irq_sets), 20853b6592f7SJens Axboe .sets = irq_sets, 20863b6592f7SJens Axboe }; 208730e06628SJens Axboe int result = 0; 20883b6592f7SJens Axboe 20893b6592f7SJens Axboe /* 20903b6592f7SJens Axboe * For irq sets, we have to ask for minvec == maxvec. This passes 20913b6592f7SJens Axboe * any reduction back to us, so we can adjust our queue counts and 20923b6592f7SJens Axboe * IRQ vector needs. 20933b6592f7SJens Axboe */ 20943b6592f7SJens Axboe do { 20953b6592f7SJens Axboe nvme_calc_io_queues(dev, nr_io_queues); 2096e20ba6e1SChristoph Hellwig irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT]; 2097e20ba6e1SChristoph Hellwig irq_sets[1] = dev->io_queues[HCTX_TYPE_READ]; 20983b6592f7SJens Axboe if (!irq_sets[1]) 20993b6592f7SJens Axboe affd.nr_sets = 1; 21003b6592f7SJens Axboe 21013b6592f7SJens Axboe /* 2102db29eb05SJens Axboe * If we got a failure and we're down to asking for just 2103db29eb05SJens Axboe * 1 + 1 queues, just ask for a single vector. We'll share 2104db29eb05SJens Axboe * that between the single IO queue and the admin queue. 21053b6592f7SJens Axboe */ 2106db29eb05SJens Axboe if (!(result < 0 && nr_io_queues == 1)) 21073b6592f7SJens Axboe nr_io_queues = irq_sets[0] + irq_sets[1] + 1; 21083b6592f7SJens Axboe 21093b6592f7SJens Axboe result = pci_alloc_irq_vectors_affinity(pdev, nr_io_queues, 21103b6592f7SJens Axboe nr_io_queues, 21113b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21123b6592f7SJens Axboe 21133b6592f7SJens Axboe /* 2114db29eb05SJens Axboe * Need to reduce our vec counts. If we get ENOSPC, the 2115db29eb05SJens Axboe * platform should support mulitple vecs, we just need 2116db29eb05SJens Axboe * to decrease our ask. If we get EINVAL, the platform 2117db29eb05SJens Axboe * likely does not. Back down to ask for just one vector. 21183b6592f7SJens Axboe */ 21193b6592f7SJens Axboe if (result == -ENOSPC) { 21203b6592f7SJens Axboe nr_io_queues--; 21213b6592f7SJens Axboe if (!nr_io_queues) 21223b6592f7SJens Axboe return result; 21233b6592f7SJens Axboe continue; 2124db29eb05SJens Axboe } else if (result == -EINVAL) { 2125db29eb05SJens Axboe nr_io_queues = 1; 2126db29eb05SJens Axboe continue; 21273b6592f7SJens Axboe } else if (result <= 0) 21283b6592f7SJens Axboe return -EIO; 21293b6592f7SJens Axboe break; 21303b6592f7SJens Axboe } while (1); 21313b6592f7SJens Axboe 21323b6592f7SJens Axboe return result; 21333b6592f7SJens Axboe } 21343b6592f7SJens Axboe 213557dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 213657dacad5SJay Sternberg { 2137147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 213857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 213997f6ef64SXu Yu int result, nr_io_queues; 214097f6ef64SXu Yu unsigned long size; 214157dacad5SJay Sternberg 21423b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21439a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21449a0be7abSChristoph Hellwig if (result < 0) 214557dacad5SJay Sternberg return result; 21469a0be7abSChristoph Hellwig 2147f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2148a5229050SKeith Busch return 0; 214957dacad5SJay Sternberg 21504e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21514e224106SChristoph Hellwig 21520f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 215357dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 215457dacad5SJay Sternberg sizeof(struct nvme_command)); 215557dacad5SJay Sternberg if (result > 0) 215657dacad5SJay Sternberg dev->q_depth = result; 215757dacad5SJay Sternberg else 21580f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 215957dacad5SJay Sternberg } 216057dacad5SJay Sternberg 216157dacad5SJay Sternberg do { 216297f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 216397f6ef64SXu Yu result = nvme_remap_bar(dev, size); 216497f6ef64SXu Yu if (!result) 216557dacad5SJay Sternberg break; 216657dacad5SJay Sternberg if (!--nr_io_queues) 216757dacad5SJay Sternberg return -ENOMEM; 216857dacad5SJay Sternberg } while (1); 216957dacad5SJay Sternberg adminq->q_db = dev->dbs; 217057dacad5SJay Sternberg 217157dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21720ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 217357dacad5SJay Sternberg 217457dacad5SJay Sternberg /* 217557dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 217657dacad5SJay Sternberg * setting up the full range we need. 217757dacad5SJay Sternberg */ 2178dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21793b6592f7SJens Axboe 21803b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 218122b55601SKeith Busch if (result <= 0) 2182dca51e78SChristoph Hellwig return -EIO; 21833b6592f7SJens Axboe 218422b55601SKeith Busch dev->num_vecs = result; 21854b04cc6aSJens Axboe result = max(result - 1, 1); 2186e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 218757dacad5SJay Sternberg 2188e20ba6e1SChristoph Hellwig dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2189e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT], 2190e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ], 2191e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL]); 21923b6592f7SJens Axboe 219357dacad5SJay Sternberg /* 219457dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 219557dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 219657dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 219757dacad5SJay Sternberg * number of interrupts. 219857dacad5SJay Sternberg */ 219957dacad5SJay Sternberg 2200dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 220157dacad5SJay Sternberg if (result) { 220257dacad5SJay Sternberg adminq->cq_vector = -1; 2203d4875622SKeith Busch return result; 220457dacad5SJay Sternberg } 22054e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2206749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 220757dacad5SJay Sternberg } 220857dacad5SJay Sternberg 22092a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2210db3cbfffSKeith Busch { 2211db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2212db3cbfffSKeith Busch 2213db3cbfffSKeith Busch blk_mq_free_request(req); 2214db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 2215db3cbfffSKeith Busch } 2216db3cbfffSKeith Busch 22172a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2218db3cbfffSKeith Busch { 2219db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 22205cb525c8SJens Axboe u16 start, end; 2221db3cbfffSKeith Busch 2222db3cbfffSKeith Busch if (!error) { 2223db3cbfffSKeith Busch unsigned long flags; 2224db3cbfffSKeith Busch 22250bc88192SKeith Busch spin_lock_irqsave(&nvmeq->cq_lock, flags); 22265cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 22271ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 22285cb525c8SJens Axboe 22295cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 2230db3cbfffSKeith Busch } 2231db3cbfffSKeith Busch 2232db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2233db3cbfffSKeith Busch } 2234db3cbfffSKeith Busch 2235db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2236db3cbfffSKeith Busch { 2237db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2238db3cbfffSKeith Busch struct request *req; 2239db3cbfffSKeith Busch struct nvme_command cmd; 2240db3cbfffSKeith Busch 2241db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2242db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2243db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2244db3cbfffSKeith Busch 2245eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2246db3cbfffSKeith Busch if (IS_ERR(req)) 2247db3cbfffSKeith Busch return PTR_ERR(req); 2248db3cbfffSKeith Busch 2249db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2250db3cbfffSKeith Busch req->end_io_data = nvmeq; 2251db3cbfffSKeith Busch 2252db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2253db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2254db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2255db3cbfffSKeith Busch return 0; 2256db3cbfffSKeith Busch } 2257db3cbfffSKeith Busch 2258ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2259db3cbfffSKeith Busch { 2260ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2261db3cbfffSKeith Busch unsigned long timeout; 2262db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2263db3cbfffSKeith Busch 2264db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2265014a0d60SKeith Busch int sent = 0, i = queues; 2266db3cbfffSKeith Busch 2267db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2268db3cbfffSKeith Busch retry: 2269db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2270c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2271147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2272db3cbfffSKeith Busch break; 2273c21377f8SGabriel Krisman Bertazi 2274db3cbfffSKeith Busch while (sent--) { 2275db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2276db3cbfffSKeith Busch if (timeout == 0) 2277db3cbfffSKeith Busch return; 2278db3cbfffSKeith Busch if (i) 2279db3cbfffSKeith Busch goto retry; 2280db3cbfffSKeith Busch } 2281db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2282db3cbfffSKeith Busch } 2283db3cbfffSKeith Busch } 2284db3cbfffSKeith Busch 228557dacad5SJay Sternberg /* 22862b1b7e78SJianchao Wang * return error value only when tagset allocation failed 228757dacad5SJay Sternberg */ 228857dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 228957dacad5SJay Sternberg { 22902b1b7e78SJianchao Wang int ret; 22912b1b7e78SJianchao Wang 22925bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2293c6d962aeSChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2294c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_poll_ops; 2295dabcefabSJens Axboe else 2296c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 2297dabcefabSJens Axboe 229857dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2299e20ba6e1SChristoph Hellwig dev->tagset.nr_maps = HCTX_MAX_TYPES; 230057dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 230157dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 230257dacad5SJay Sternberg dev->tagset.queue_depth = 230357dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2304a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2305a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2306a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2307a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2308a7a7cbe3SChaitanya Kulkarni } 230957dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 231057dacad5SJay Sternberg dev->tagset.driver_data = dev; 231157dacad5SJay Sternberg 23122b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23132b1b7e78SJianchao Wang if (ret) { 23142b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23152b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23162b1b7e78SJianchao Wang return ret; 23172b1b7e78SJianchao Wang } 23185bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2319f9f38e33SHelen Koike 2320f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2321949928c1SKeith Busch } else { 2322949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2323949928c1SKeith Busch 2324949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2325949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 232657dacad5SJay Sternberg } 2327949928c1SKeith Busch 232857dacad5SJay Sternberg return 0; 232957dacad5SJay Sternberg } 233057dacad5SJay Sternberg 2331b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 233257dacad5SJay Sternberg { 2333b00a726aSKeith Busch int result = -ENOMEM; 233457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 233557dacad5SJay Sternberg 233657dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 233757dacad5SJay Sternberg return result; 233857dacad5SJay Sternberg 233957dacad5SJay Sternberg pci_set_master(pdev); 234057dacad5SJay Sternberg 234157dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 234257dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 234357dacad5SJay Sternberg goto disable; 234457dacad5SJay Sternberg 23457a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 234657dacad5SJay Sternberg result = -ENODEV; 2347b00a726aSKeith Busch goto disable; 234857dacad5SJay Sternberg } 234957dacad5SJay Sternberg 235057dacad5SJay Sternberg /* 2351a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2352a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2353a5229050SKeith Busch * adjust this later. 235457dacad5SJay Sternberg */ 2355dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2356dca51e78SChristoph Hellwig if (result < 0) 2357dca51e78SChristoph Hellwig return result; 235857dacad5SJay Sternberg 235920d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23607a67cbeaSChristoph Hellwig 236120d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2362b27c1e68Sweiping zhang io_queue_depth); 236320d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23647a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23651f390c1fSStephan Günther 23661f390c1fSStephan Günther /* 23671f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23681f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23691f390c1fSStephan Günther */ 23701f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23711f390c1fSStephan Günther dev->q_depth = 2; 23729bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23739bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23741f390c1fSStephan Günther dev->q_depth); 2375d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2376d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 237720d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2378d554b5e1SMartin K. Petersen dev->q_depth = 64; 2379d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2380d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23811f390c1fSStephan Günther } 23821f390c1fSStephan Günther 2383f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2384202021c1SStephen Bates 2385a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2386a0a3408eSKeith Busch pci_save_state(pdev); 238757dacad5SJay Sternberg return 0; 238857dacad5SJay Sternberg 238957dacad5SJay Sternberg disable: 239057dacad5SJay Sternberg pci_disable_device(pdev); 239157dacad5SJay Sternberg return result; 239257dacad5SJay Sternberg } 239357dacad5SJay Sternberg 239457dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 239557dacad5SJay Sternberg { 2396b00a726aSKeith Busch if (dev->bar) 2397b00a726aSKeith Busch iounmap(dev->bar); 2398a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2399b00a726aSKeith Busch } 2400b00a726aSKeith Busch 2401b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2402b00a726aSKeith Busch { 240357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 240457dacad5SJay Sternberg 2405dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 240657dacad5SJay Sternberg 2407a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2408a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 240957dacad5SJay Sternberg pci_disable_device(pdev); 241057dacad5SJay Sternberg } 2411a0a3408eSKeith Busch } 241257dacad5SJay Sternberg 2413a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 241457dacad5SJay Sternberg { 2415ee9aebb2SKeith Busch int i; 2416302ad8ccSKeith Busch bool dead = true; 2417302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 241857dacad5SJay Sternberg 241977bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2420302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2421302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2422302ad8ccSKeith Busch 2423ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2424ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2425302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2426302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2427302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 242857dacad5SJay Sternberg } 2429c21377f8SGabriel Krisman Bertazi 2430302ad8ccSKeith Busch /* 2431302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2432302ad8ccSKeith Busch * doing a safe shutdown. 2433302ad8ccSKeith Busch */ 243487ad72a5SChristoph Hellwig if (!dead) { 243587ad72a5SChristoph Hellwig if (shutdown) 2436302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24379a915a5bSJianchao Wang } 243887ad72a5SChristoph Hellwig 24399a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24409a915a5bSJianchao Wang 244164ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 2442ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2443a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 244457dacad5SJay Sternberg } 2445ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2446ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2447ee9aebb2SKeith Busch 2448b00a726aSKeith Busch nvme_pci_disable(dev); 244957dacad5SJay Sternberg 2450e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2451e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2452302ad8ccSKeith Busch 2453302ad8ccSKeith Busch /* 2454302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2455302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2456302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2457302ad8ccSKeith Busch */ 2458302ad8ccSKeith Busch if (shutdown) 2459302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 246077bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 246157dacad5SJay Sternberg } 246257dacad5SJay Sternberg 246357dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 246457dacad5SJay Sternberg { 246557dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 246657dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 246757dacad5SJay Sternberg if (!dev->prp_page_pool) 246857dacad5SJay Sternberg return -ENOMEM; 246957dacad5SJay Sternberg 247057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 247157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 247257dacad5SJay Sternberg 256, 256, 0); 247357dacad5SJay Sternberg if (!dev->prp_small_pool) { 247457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 247557dacad5SJay Sternberg return -ENOMEM; 247657dacad5SJay Sternberg } 247757dacad5SJay Sternberg return 0; 247857dacad5SJay Sternberg } 247957dacad5SJay Sternberg 248057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 248157dacad5SJay Sternberg { 248257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 248357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 248457dacad5SJay Sternberg } 248557dacad5SJay Sternberg 24861673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 248757dacad5SJay Sternberg { 24881673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 248957dacad5SJay Sternberg 2490f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 249157dacad5SJay Sternberg put_device(dev->dev); 249257dacad5SJay Sternberg if (dev->tagset.tags) 249357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24941c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24951c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 249657dacad5SJay Sternberg kfree(dev->queues); 2497e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2498943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 249957dacad5SJay Sternberg kfree(dev); 250057dacad5SJay Sternberg } 250157dacad5SJay Sternberg 2502f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2503f58944e2SKeith Busch { 2504237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2505f58944e2SKeith Busch 2506d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 250769d9a99cSKeith Busch nvme_dev_disable(dev, false); 25089f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 250903e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2510f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2511f58944e2SKeith Busch } 2512f58944e2SKeith Busch 2513fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 251457dacad5SJay Sternberg { 2515d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2516d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2517a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2518f58944e2SKeith Busch int result = -ENODEV; 25192b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 252057dacad5SJay Sternberg 252182b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2522fd634f41SChristoph Hellwig goto out; 2523fd634f41SChristoph Hellwig 2524fd634f41SChristoph Hellwig /* 2525fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2526fd634f41SChristoph Hellwig * moving on. 2527fd634f41SChristoph Hellwig */ 2528b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2529a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2530fd634f41SChristoph Hellwig 2531ad70062cSJianchao Wang /* 2532ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2533ad70062cSJianchao Wang * initializing procedure here. 2534ad70062cSJianchao Wang */ 2535ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2536ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2537ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2538ad70062cSJianchao Wang goto out; 2539ad70062cSJianchao Wang } 2540ad70062cSJianchao Wang 2541b00a726aSKeith Busch result = nvme_pci_enable(dev); 254257dacad5SJay Sternberg if (result) 254357dacad5SJay Sternberg goto out; 254457dacad5SJay Sternberg 254501ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 254657dacad5SJay Sternberg if (result) 2547f58944e2SKeith Busch goto out; 254857dacad5SJay Sternberg 254957dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 255057dacad5SJay Sternberg if (result) 2551f58944e2SKeith Busch goto out; 255257dacad5SJay Sternberg 2553943e942eSJens Axboe /* 2554943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2555943e942eSJens Axboe * over a single page. 2556943e942eSJens Axboe */ 2557943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2558943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2559943e942eSJens Axboe 2560ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2561ce4541f4SChristoph Hellwig if (result) 2562f58944e2SKeith Busch goto out; 2563ce4541f4SChristoph Hellwig 2564e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2565e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25664f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25674f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2568e286bcfcSScott Bauer else if (was_suspend) 25694f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2570e286bcfcSScott Bauer } else { 2571e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2572e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2573e286bcfcSScott Bauer } 2574a98e58e5SScott Bauer 2575f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2576f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2577f9f38e33SHelen Koike if (result) 2578f9f38e33SHelen Koike dev_warn(dev->dev, 2579f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2580f9f38e33SHelen Koike } 2581f9f38e33SHelen Koike 25829620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25839620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25849620cfbaSChristoph Hellwig if (result < 0) 25859620cfbaSChristoph Hellwig goto out; 25869620cfbaSChristoph Hellwig } 258787ad72a5SChristoph Hellwig 258857dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 258957dacad5SJay Sternberg if (result) 2590f58944e2SKeith Busch goto out; 259157dacad5SJay Sternberg 259221f033f7SKeith Busch /* 259357dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 259457dacad5SJay Sternberg * any working I/O queue. 259557dacad5SJay Sternberg */ 259657dacad5SJay Sternberg if (dev->online_queues < 2) { 25971b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25983b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25995bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 26002b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 260157dacad5SJay Sternberg } else { 260225646264SKeith Busch nvme_start_queues(&dev->ctrl); 2603302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26042b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 26052b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 26062b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2607302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 260857dacad5SJay Sternberg } 260957dacad5SJay Sternberg 26102b1b7e78SJianchao Wang /* 26112b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26122b1b7e78SJianchao Wang * recovery. 26132b1b7e78SJianchao Wang */ 26142b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 26152b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26162b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2617bb8d261eSChristoph Hellwig goto out; 2618bb8d261eSChristoph Hellwig } 261992911a55SChristoph Hellwig 2620d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 262157dacad5SJay Sternberg return; 262257dacad5SJay Sternberg 262357dacad5SJay Sternberg out: 2624f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 262557dacad5SJay Sternberg } 262657dacad5SJay Sternberg 26275c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 262857dacad5SJay Sternberg { 26295c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 263057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 263157dacad5SJay Sternberg 263257dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2633921920abSKeith Busch device_release_driver(&pdev->dev); 26341673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 263557dacad5SJay Sternberg } 263657dacad5SJay Sternberg 26371c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 263857dacad5SJay Sternberg { 26391c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26401c63dc66SChristoph Hellwig return 0; 264157dacad5SJay Sternberg } 26421c63dc66SChristoph Hellwig 26435fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26445fd4ce1bSChristoph Hellwig { 26455fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26465fd4ce1bSChristoph Hellwig return 0; 26475fd4ce1bSChristoph Hellwig } 26485fd4ce1bSChristoph Hellwig 26497fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26507fd8930fSChristoph Hellwig { 26517fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26527fd8930fSChristoph Hellwig return 0; 26537fd8930fSChristoph Hellwig } 26547fd8930fSChristoph Hellwig 265597c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 265697c12223SKeith Busch { 265797c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 265897c12223SKeith Busch 265997c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 266097c12223SKeith Busch } 266197c12223SKeith Busch 26621c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26631a353d85SMing Lin .name = "pcie", 2664e439bb12SSagi Grimberg .module = THIS_MODULE, 2665e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2666e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26671c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26685fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26697fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26701673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2671f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 267297c12223SKeith Busch .get_address = nvme_pci_get_address, 26731c63dc66SChristoph Hellwig }; 267457dacad5SJay Sternberg 2675b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2676b00a726aSKeith Busch { 2677b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2678b00a726aSKeith Busch 2679a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2680b00a726aSKeith Busch return -ENODEV; 2681b00a726aSKeith Busch 268297f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2683b00a726aSKeith Busch goto release; 2684b00a726aSKeith Busch 2685b00a726aSKeith Busch return 0; 2686b00a726aSKeith Busch release: 2687a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2688b00a726aSKeith Busch return -ENODEV; 2689b00a726aSKeith Busch } 2690b00a726aSKeith Busch 26918427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2692ff5350a8SAndy Lutomirski { 2693ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2694ff5350a8SAndy Lutomirski /* 2695ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2696ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2697ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2698ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2699ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2700ff5350a8SAndy Lutomirski * laptops. 2701ff5350a8SAndy Lutomirski */ 2702ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2703ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2704ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2705ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27068427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27078427bbc2SKai-Heng Feng /* 27088427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2709467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2710467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2711467c77d4SJarosław Janik * ASUS PRIME Z370-A 27128427bbc2SKai-Heng Feng */ 27138427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2714467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2715467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27168427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2717ff5350a8SAndy Lutomirski } 2718ff5350a8SAndy Lutomirski 2719ff5350a8SAndy Lutomirski return 0; 2720ff5350a8SAndy Lutomirski } 2721ff5350a8SAndy Lutomirski 272218119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 272318119775SKeith Busch { 272418119775SKeith Busch struct nvme_dev *dev = data; 272580f513b5SKeith Busch 272618119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 272718119775SKeith Busch flush_work(&dev->ctrl.scan_work); 272880f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 272918119775SKeith Busch } 273018119775SKeith Busch 273157dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 273257dacad5SJay Sternberg { 273357dacad5SJay Sternberg int node, result = -ENOMEM; 273457dacad5SJay Sternberg struct nvme_dev *dev; 2735ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2736943e942eSJens Axboe size_t alloc_size; 273757dacad5SJay Sternberg 273857dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 273957dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27402fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 274157dacad5SJay Sternberg 274257dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 274357dacad5SJay Sternberg if (!dev) 274457dacad5SJay Sternberg return -ENOMEM; 2745147b27e4SSagi Grimberg 27463b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27473b6592f7SJens Axboe GFP_KERNEL, node); 274857dacad5SJay Sternberg if (!dev->queues) 274957dacad5SJay Sternberg goto free; 275057dacad5SJay Sternberg 275157dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 275257dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 275357dacad5SJay Sternberg 2754b00a726aSKeith Busch result = nvme_dev_map(dev); 2755b00a726aSKeith Busch if (result) 2756b00c9b7aSChristophe JAILLET goto put_pci; 2757b00a726aSKeith Busch 2758d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27595c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 276077bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2761db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2762f3ca80fcSChristoph Hellwig 2763f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2764f3ca80fcSChristoph Hellwig if (result) 2765b00c9b7aSChristophe JAILLET goto unmap; 2766f3ca80fcSChristoph Hellwig 27678427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2768ff5350a8SAndy Lutomirski 2769943e942eSJens Axboe /* 2770943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2771943e942eSJens Axboe * command we support. 2772943e942eSJens Axboe */ 2773943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2774943e942eSJens Axboe NVME_MAX_SEGS, true); 2775943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2776943e942eSJens Axboe 2777943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2778943e942eSJens Axboe mempool_kfree, 2779943e942eSJens Axboe (void *) alloc_size, 2780943e942eSJens Axboe GFP_KERNEL, node); 2781943e942eSJens Axboe if (!dev->iod_mempool) { 2782943e942eSJens Axboe result = -ENOMEM; 2783943e942eSJens Axboe goto release_pools; 2784943e942eSJens Axboe } 2785943e942eSJens Axboe 2786b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2787b6e44b4cSKeith Busch quirks); 2788b6e44b4cSKeith Busch if (result) 2789b6e44b4cSKeith Busch goto release_mempool; 2790b6e44b4cSKeith Busch 27911b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27921b3c47c1SSagi Grimberg 279380f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 279418119775SKeith Busch async_schedule(nvme_async_probe, dev); 27954caff8fcSSagi Grimberg 279657dacad5SJay Sternberg return 0; 279757dacad5SJay Sternberg 2798b6e44b4cSKeith Busch release_mempool: 2799b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 280057dacad5SJay Sternberg release_pools: 280157dacad5SJay Sternberg nvme_release_prp_pools(dev); 2802b00c9b7aSChristophe JAILLET unmap: 2803b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 280457dacad5SJay Sternberg put_pci: 280557dacad5SJay Sternberg put_device(dev->dev); 280657dacad5SJay Sternberg free: 280757dacad5SJay Sternberg kfree(dev->queues); 280857dacad5SJay Sternberg kfree(dev); 280957dacad5SJay Sternberg return result; 281057dacad5SJay Sternberg } 281157dacad5SJay Sternberg 2812775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 281357dacad5SJay Sternberg { 281457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2815a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2816775755edSChristoph Hellwig } 281757dacad5SJay Sternberg 2818775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2819775755edSChristoph Hellwig { 2820f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 282179c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 282257dacad5SJay Sternberg } 282357dacad5SJay Sternberg 282457dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 282557dacad5SJay Sternberg { 282657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2827a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 282857dacad5SJay Sternberg } 282957dacad5SJay Sternberg 2830f58944e2SKeith Busch /* 2831f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2832f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2833f58944e2SKeith Busch * order to proceed. 2834f58944e2SKeith Busch */ 283557dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 283657dacad5SJay Sternberg { 283757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 283857dacad5SJay Sternberg 2839bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 284057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28410ff9d4e1SKeith Busch 28426db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28430ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28441d39e692SKeith Busch nvme_dev_disable(dev, true); 2845cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28466db28edaSKeith Busch } 28470ff9d4e1SKeith Busch 2848d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2849d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2850d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2851a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28529fe5c59fSKeith Busch nvme_release_cmb(dev); 285387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 285457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 285557dacad5SJay Sternberg nvme_free_queues(dev, 0); 2856d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 285757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2858b00a726aSKeith Busch nvme_dev_unmap(dev); 28591673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 286057dacad5SJay Sternberg } 286157dacad5SJay Sternberg 286257dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 286357dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 286457dacad5SJay Sternberg { 286557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 286657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 286757dacad5SJay Sternberg 2868a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 286957dacad5SJay Sternberg return 0; 287057dacad5SJay Sternberg } 287157dacad5SJay Sternberg 287257dacad5SJay Sternberg static int nvme_resume(struct device *dev) 287357dacad5SJay Sternberg { 287457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 287557dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 287657dacad5SJay Sternberg 2877d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 287857dacad5SJay Sternberg return 0; 287957dacad5SJay Sternberg } 288057dacad5SJay Sternberg #endif 288157dacad5SJay Sternberg 288257dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 288357dacad5SJay Sternberg 2884a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2885a0a3408eSKeith Busch pci_channel_state_t state) 2886a0a3408eSKeith Busch { 2887a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2888a0a3408eSKeith Busch 2889a0a3408eSKeith Busch /* 2890a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2891a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2892a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2893a0a3408eSKeith Busch */ 2894a0a3408eSKeith Busch switch (state) { 2895a0a3408eSKeith Busch case pci_channel_io_normal: 2896a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2897a0a3408eSKeith Busch case pci_channel_io_frozen: 2898d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2899d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2900a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2901a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2902a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2903d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2904d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2905a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2906a0a3408eSKeith Busch } 2907a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2908a0a3408eSKeith Busch } 2909a0a3408eSKeith Busch 2910a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2911a0a3408eSKeith Busch { 2912a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2913a0a3408eSKeith Busch 29141b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2915a0a3408eSKeith Busch pci_restore_state(pdev); 2916d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2917a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2918a0a3408eSKeith Busch } 2919a0a3408eSKeith Busch 2920a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2921a0a3408eSKeith Busch { 292272cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 292372cd4cc2SKeith Busch 292472cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2925a0a3408eSKeith Busch } 2926a0a3408eSKeith Busch 292757dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 292857dacad5SJay Sternberg .error_detected = nvme_error_detected, 292957dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 293057dacad5SJay Sternberg .resume = nvme_error_resume, 2931775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2932775755edSChristoph Hellwig .reset_done = nvme_reset_done, 293357dacad5SJay Sternberg }; 293457dacad5SJay Sternberg 293557dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2936106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 293708095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2938e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 293999466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 294099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2941e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 294299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 294399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2944e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2945f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2946f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2947f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 294850af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29499abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29509abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2951540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2952540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 29530302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29540302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 295554adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 295654adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29578c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29588c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2959015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2960015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2961d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2962d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2963d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2964d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2965608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2966608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2967608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2968608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2969ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2970ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 297157dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2972c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2973124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 297457dacad5SJay Sternberg { 0, } 297557dacad5SJay Sternberg }; 297657dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 297757dacad5SJay Sternberg 297857dacad5SJay Sternberg static struct pci_driver nvme_driver = { 297957dacad5SJay Sternberg .name = "nvme", 298057dacad5SJay Sternberg .id_table = nvme_id_table, 298157dacad5SJay Sternberg .probe = nvme_probe, 298257dacad5SJay Sternberg .remove = nvme_remove, 298357dacad5SJay Sternberg .shutdown = nvme_shutdown, 298457dacad5SJay Sternberg .driver = { 298557dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 298657dacad5SJay Sternberg }, 298774d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 298857dacad5SJay Sternberg .err_handler = &nvme_err_handler, 298957dacad5SJay Sternberg }; 299057dacad5SJay Sternberg 299157dacad5SJay Sternberg static int __init nvme_init(void) 299257dacad5SJay Sternberg { 29939a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 299457dacad5SJay Sternberg } 299557dacad5SJay Sternberg 299657dacad5SJay Sternberg static void __exit nvme_exit(void) 299757dacad5SJay Sternberg { 299857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 299903e0f3a6SMing Lei flush_workqueue(nvme_wq); 300057dacad5SJay Sternberg _nvme_check_size(); 300157dacad5SJay Sternberg } 300257dacad5SJay Sternberg 300357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 300457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 300557dacad5SJay Sternberg MODULE_VERSION("1.0"); 300657dacad5SJay Sternberg module_init(nvme_init); 300757dacad5SJay Sternberg module_exit(nvme_exit); 3008