157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 35604c01d5Syupeng #include "trace.h" 3657dacad5SJay Sternberg #include "nvme.h" 3757dacad5SJay Sternberg 3857dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3957dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 4057dacad5SJay Sternberg 41a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 42adf68f21SChristoph Hellwig 43943e942eSJens Axboe /* 44943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 45943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 46943e942eSJens Axboe */ 47943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 48943e942eSJens Axboe #define NVME_MAX_SEGS 127 49943e942eSJens Axboe 5057dacad5SJay Sternberg static int use_threaded_interrupts; 5157dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5257dacad5SJay Sternberg 5357dacad5SJay Sternberg static bool use_cmb_sqes = true; 5469f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5557dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5657dacad5SJay Sternberg 5787ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5887ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5987ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 6087ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6157dacad5SJay Sternberg 62a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 63a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 64a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 65a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 66a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 67a7a7cbe3SChaitanya Kulkarni 68b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 70b27c1e68Sweiping zhang .set = io_queue_depth_set, 71b27c1e68Sweiping zhang .get = param_get_int, 72b27c1e68Sweiping zhang }; 73b27c1e68Sweiping zhang 74b27c1e68Sweiping zhang static int io_queue_depth = 1024; 75b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 76b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 77b27c1e68Sweiping zhang 783b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 793b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 803b6592f7SJens Axboe .set = queue_count_set, 813b6592f7SJens Axboe .get = param_get_int, 823b6592f7SJens Axboe }; 833b6592f7SJens Axboe 843b6592f7SJens Axboe static int write_queues; 853b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 863b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 873b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 883b6592f7SJens Axboe "will share a queue set."); 893b6592f7SJens Axboe 90a4668d9bSJens Axboe static int poll_queues = 0; 914b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 924b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 934b04cc6aSJens Axboe 941c63dc66SChristoph Hellwig struct nvme_dev; 951c63dc66SChristoph Hellwig struct nvme_queue; 9657dacad5SJay Sternberg 97a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 988fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 9957dacad5SJay Sternberg 10057dacad5SJay Sternberg /* 1011c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1021c63dc66SChristoph Hellwig */ 1031c63dc66SChristoph Hellwig struct nvme_dev { 104147b27e4SSagi Grimberg struct nvme_queue *queues; 1051c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1061c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1071c63dc66SChristoph Hellwig u32 __iomem *dbs; 1081c63dc66SChristoph Hellwig struct device *dev; 1091c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1101c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1111c63dc66SChristoph Hellwig unsigned online_queues; 1121c63dc66SChristoph Hellwig unsigned max_qid; 113e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 11422b55601SKeith Busch unsigned int num_vecs; 1151c63dc66SChristoph Hellwig int q_depth; 1161c63dc66SChristoph Hellwig u32 db_stride; 1171c63dc66SChristoph Hellwig void __iomem *bar; 11897f6ef64SXu Yu unsigned long bar_mapped_size; 1195c8809e6SChristoph Hellwig struct work_struct remove_work; 12077bf25eaSKeith Busch struct mutex shutdown_lock; 1211c63dc66SChristoph Hellwig bool subsystem; 1221c63dc66SChristoph Hellwig u64 cmb_size; 1230f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1241c63dc66SChristoph Hellwig u32 cmbsz; 125202021c1SStephen Bates u32 cmbloc; 1261c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 12787ad72a5SChristoph Hellwig 128943e942eSJens Axboe mempool_t *iod_mempool; 129943e942eSJens Axboe 13087ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 131f9f38e33SHelen Koike u32 *dbbuf_dbs; 132f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 133f9f38e33SHelen Koike u32 *dbbuf_eis; 134f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 13587ad72a5SChristoph Hellwig 13687ad72a5SChristoph Hellwig /* host memory buffer support: */ 13787ad72a5SChristoph Hellwig u64 host_mem_size; 13887ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1394033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 14087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 14187ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 14257dacad5SJay Sternberg }; 14357dacad5SJay Sternberg 144b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 145b27c1e68Sweiping zhang { 146b27c1e68Sweiping zhang int n = 0, ret; 147b27c1e68Sweiping zhang 148b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 149b27c1e68Sweiping zhang if (ret != 0 || n < 2) 150b27c1e68Sweiping zhang return -EINVAL; 151b27c1e68Sweiping zhang 152b27c1e68Sweiping zhang return param_set_int(val, kp); 153b27c1e68Sweiping zhang } 154b27c1e68Sweiping zhang 1553b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1563b6592f7SJens Axboe { 1573b6592f7SJens Axboe int n = 0, ret; 1583b6592f7SJens Axboe 1593b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 1603b6592f7SJens Axboe if (n > num_possible_cpus()) 1613b6592f7SJens Axboe n = num_possible_cpus(); 1623b6592f7SJens Axboe 1633b6592f7SJens Axboe return param_set_int(val, kp); 1643b6592f7SJens Axboe } 1653b6592f7SJens Axboe 166f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 167f9f38e33SHelen Koike { 168f9f38e33SHelen Koike return qid * 2 * stride; 169f9f38e33SHelen Koike } 170f9f38e33SHelen Koike 171f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 172f9f38e33SHelen Koike { 173f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 174f9f38e33SHelen Koike } 175f9f38e33SHelen Koike 1761c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1771c63dc66SChristoph Hellwig { 1781c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1791c63dc66SChristoph Hellwig } 1801c63dc66SChristoph Hellwig 18157dacad5SJay Sternberg /* 18257dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18357dacad5SJay Sternberg * commands and one for I/O commands). 18457dacad5SJay Sternberg */ 18557dacad5SJay Sternberg struct nvme_queue { 18657dacad5SJay Sternberg struct device *q_dmadev; 18757dacad5SJay Sternberg struct nvme_dev *dev; 1881ab0cd69SJens Axboe spinlock_t sq_lock; 18957dacad5SJay Sternberg struct nvme_command *sq_cmds; 1903a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1913a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19257dacad5SJay Sternberg volatile struct nvme_completion *cqes; 19357dacad5SJay Sternberg struct blk_mq_tags **tags; 19457dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19557dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19657dacad5SJay Sternberg u32 __iomem *q_db; 19757dacad5SJay Sternberg u16 q_depth; 19857dacad5SJay Sternberg s16 cq_vector; 19957dacad5SJay Sternberg u16 sq_tail; 20004f3eafdSJens Axboe u16 last_sq_tail; 20157dacad5SJay Sternberg u16 cq_head; 20268fa9dbeSJens Axboe u16 last_cq_head; 20357dacad5SJay Sternberg u16 qid; 20457dacad5SJay Sternberg u8 cq_phase; 2054e224106SChristoph Hellwig unsigned long flags; 2064e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20763223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 208d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 209f9f38e33SHelen Koike u32 *dbbuf_sq_db; 210f9f38e33SHelen Koike u32 *dbbuf_cq_db; 211f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 212f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 213d1ed6aa1SChristoph Hellwig struct completion delete_done; 21457dacad5SJay Sternberg }; 21557dacad5SJay Sternberg 21657dacad5SJay Sternberg /* 21771bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 21871bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 219f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 22071bd150cSChristoph Hellwig * allocated to store the PRP list. 22171bd150cSChristoph Hellwig */ 22271bd150cSChristoph Hellwig struct nvme_iod { 223d49187e9SChristoph Hellwig struct nvme_request req; 224f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 225a7a7cbe3SChaitanya Kulkarni bool use_sgl; 226f4800d6dSChristoph Hellwig int aborted; 22771bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22871bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22971bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 23071bd150cSChristoph Hellwig dma_addr_t first_dma; 231bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 232f4800d6dSChristoph Hellwig struct scatterlist *sg; 233f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 23457dacad5SJay Sternberg }; 23557dacad5SJay Sternberg 23657dacad5SJay Sternberg /* 23757dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23857dacad5SJay Sternberg */ 23957dacad5SJay Sternberg static inline void _nvme_check_size(void) 24057dacad5SJay Sternberg { 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 24257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 24357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 24657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2490add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2500add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 25157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 25257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 253f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 254f9f38e33SHelen Koike } 255f9f38e33SHelen Koike 2563b6592f7SJens Axboe static unsigned int max_io_queues(void) 2573b6592f7SJens Axboe { 2584b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2593b6592f7SJens Axboe } 2603b6592f7SJens Axboe 2613b6592f7SJens Axboe static unsigned int max_queue_count(void) 2623b6592f7SJens Axboe { 2633b6592f7SJens Axboe /* IO queues + admin queue */ 2643b6592f7SJens Axboe return 1 + max_io_queues(); 2653b6592f7SJens Axboe } 2663b6592f7SJens Axboe 267f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 268f9f38e33SHelen Koike { 2693b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 270f9f38e33SHelen Koike } 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 273f9f38e33SHelen Koike { 274f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 275f9f38e33SHelen Koike 276f9f38e33SHelen Koike if (dev->dbbuf_dbs) 277f9f38e33SHelen Koike return 0; 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 280f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 281f9f38e33SHelen Koike GFP_KERNEL); 282f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 283f9f38e33SHelen Koike return -ENOMEM; 284f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 285f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 286f9f38e33SHelen Koike GFP_KERNEL); 287f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 288f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 289f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 290f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 291f9f38e33SHelen Koike return -ENOMEM; 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike return 0; 295f9f38e33SHelen Koike } 296f9f38e33SHelen Koike 297f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 298f9f38e33SHelen Koike { 299f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 302f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 303f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 304f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 305f9f38e33SHelen Koike } 306f9f38e33SHelen Koike if (dev->dbbuf_eis) { 307f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 308f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 309f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 310f9f38e33SHelen Koike } 311f9f38e33SHelen Koike } 312f9f38e33SHelen Koike 313f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 314f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 315f9f38e33SHelen Koike { 316f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 317f9f38e33SHelen Koike return; 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 320f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 321f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 322f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 323f9f38e33SHelen Koike } 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 326f9f38e33SHelen Koike { 327f9f38e33SHelen Koike struct nvme_command c; 328f9f38e33SHelen Koike 329f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 330f9f38e33SHelen Koike return; 331f9f38e33SHelen Koike 332f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 333f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 334f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 335f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3389bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 339f9f38e33SHelen Koike /* Free memory and continue on */ 340f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 341f9f38e33SHelen Koike } 342f9f38e33SHelen Koike } 343f9f38e33SHelen Koike 344f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 345f9f38e33SHelen Koike { 346f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 347f9f38e33SHelen Koike } 348f9f38e33SHelen Koike 349f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 350f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 351f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 352f9f38e33SHelen Koike { 353f9f38e33SHelen Koike if (dbbuf_db) { 354f9f38e33SHelen Koike u16 old_value; 355f9f38e33SHelen Koike 356f9f38e33SHelen Koike /* 357f9f38e33SHelen Koike * Ensure that the queue is written before updating 358f9f38e33SHelen Koike * the doorbell in memory 359f9f38e33SHelen Koike */ 360f9f38e33SHelen Koike wmb(); 361f9f38e33SHelen Koike 362f9f38e33SHelen Koike old_value = *dbbuf_db; 363f9f38e33SHelen Koike *dbbuf_db = value; 364f9f38e33SHelen Koike 365f1ed3df2SMichal Wnukowski /* 366f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 367f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 368f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 369f1ed3df2SMichal Wnukowski * the doorbell. 370f1ed3df2SMichal Wnukowski */ 371f1ed3df2SMichal Wnukowski mb(); 372f1ed3df2SMichal Wnukowski 373f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 374f9f38e33SHelen Koike return false; 375f9f38e33SHelen Koike } 376f9f38e33SHelen Koike 377f9f38e33SHelen Koike return true; 37857dacad5SJay Sternberg } 37957dacad5SJay Sternberg 38057dacad5SJay Sternberg /* 38157dacad5SJay Sternberg * Max size of iod being embedded in the request payload 38257dacad5SJay Sternberg */ 38357dacad5SJay Sternberg #define NVME_INT_PAGES 2 3845fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 38557dacad5SJay Sternberg 38657dacad5SJay Sternberg /* 38757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38957dacad5SJay Sternberg * the I/O. 39057dacad5SJay Sternberg */ 39157dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 39257dacad5SJay Sternberg { 3935fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3945fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 39557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 39657dacad5SJay Sternberg } 39757dacad5SJay Sternberg 398a7a7cbe3SChaitanya Kulkarni /* 399a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 400a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 401a7a7cbe3SChaitanya Kulkarni */ 402a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 403f4800d6dSChristoph Hellwig { 404a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 405f4800d6dSChristoph Hellwig } 406f4800d6dSChristoph Hellwig 407a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 408a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 40957dacad5SJay Sternberg { 410a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 411a7a7cbe3SChaitanya Kulkarni 412a7a7cbe3SChaitanya Kulkarni if (use_sgl) 413a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 414a7a7cbe3SChaitanya Kulkarni else 415a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 416a7a7cbe3SChaitanya Kulkarni 417a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 418a7a7cbe3SChaitanya Kulkarni } 419a7a7cbe3SChaitanya Kulkarni 420a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 421a7a7cbe3SChaitanya Kulkarni { 422a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 423a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 424a7a7cbe3SChaitanya Kulkarni use_sgl); 425a7a7cbe3SChaitanya Kulkarni 426a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42757dacad5SJay Sternberg } 42857dacad5SJay Sternberg 42957dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 43057dacad5SJay Sternberg unsigned int hctx_idx) 43157dacad5SJay Sternberg { 43257dacad5SJay Sternberg struct nvme_dev *dev = data; 433147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 43657dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43757dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43857dacad5SJay Sternberg 43957dacad5SJay Sternberg hctx->driver_data = nvmeq; 44057dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 44157dacad5SJay Sternberg return 0; 44257dacad5SJay Sternberg } 44357dacad5SJay Sternberg 44457dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 44557dacad5SJay Sternberg { 44657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44757dacad5SJay Sternberg 44857dacad5SJay Sternberg nvmeq->tags = NULL; 44957dacad5SJay Sternberg } 45057dacad5SJay Sternberg 45157dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 45257dacad5SJay Sternberg unsigned int hctx_idx) 45357dacad5SJay Sternberg { 45457dacad5SJay Sternberg struct nvme_dev *dev = data; 455147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 45657dacad5SJay Sternberg 45757dacad5SJay Sternberg if (!nvmeq->tags) 45857dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 45957dacad5SJay Sternberg 46057dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 46157dacad5SJay Sternberg hctx->driver_data = nvmeq; 46257dacad5SJay Sternberg return 0; 46357dacad5SJay Sternberg } 46457dacad5SJay Sternberg 465d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 466d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46757dacad5SJay Sternberg { 468d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 469f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4700350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 471147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 47257dacad5SJay Sternberg 47357dacad5SJay Sternberg BUG_ON(!nvmeq); 474f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 47559e29ce6SSagi Grimberg 47659e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47757dacad5SJay Sternberg return 0; 47857dacad5SJay Sternberg } 47957dacad5SJay Sternberg 4803b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4813b6592f7SJens Axboe { 4823b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4833b6592f7SJens Axboe if (dev->num_vecs > 1) 4843b6592f7SJens Axboe return 1; 4853b6592f7SJens Axboe 4863b6592f7SJens Axboe return 0; 4873b6592f7SJens Axboe } 4883b6592f7SJens Axboe 489dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 490dca51e78SChristoph Hellwig { 491dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4923b6592f7SJens Axboe int i, qoff, offset; 493dca51e78SChristoph Hellwig 4943b6592f7SJens Axboe offset = queue_irq_offset(dev); 4953b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4963b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4973b6592f7SJens Axboe 4983b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4993b6592f7SJens Axboe if (!map->nr_queues) { 500e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 5017e849dd9SChristoph Hellwig continue; 5023b6592f7SJens Axboe } 5033b6592f7SJens Axboe 5044b04cc6aSJens Axboe /* 5054b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 5064b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5074b04cc6aSJens Axboe */ 5083b6592f7SJens Axboe map->queue_offset = qoff; 509e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 5103b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5114b04cc6aSJens Axboe else 5124b04cc6aSJens Axboe blk_mq_map_queues(map); 5133b6592f7SJens Axboe qoff += map->nr_queues; 5143b6592f7SJens Axboe offset += map->nr_queues; 5153b6592f7SJens Axboe } 5163b6592f7SJens Axboe 5173b6592f7SJens Axboe return 0; 518dca51e78SChristoph Hellwig } 519dca51e78SChristoph Hellwig 52004f3eafdSJens Axboe /* 52104f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 52204f3eafdSJens Axboe */ 52304f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 52404f3eafdSJens Axboe { 52504f3eafdSJens Axboe if (!write_sq) { 52604f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 52704f3eafdSJens Axboe 52804f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 52904f3eafdSJens Axboe next_tail = 0; 53004f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 53104f3eafdSJens Axboe return; 53204f3eafdSJens Axboe } 53304f3eafdSJens Axboe 53404f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 53504f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 53604f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 53704f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 53804f3eafdSJens Axboe } 53904f3eafdSJens Axboe 54057dacad5SJay Sternberg /** 54190ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 54257dacad5SJay Sternberg * @nvmeq: The queue to use 54357dacad5SJay Sternberg * @cmd: The command to send 54404f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 54557dacad5SJay Sternberg */ 54604f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 54704f3eafdSJens Axboe bool write_sq) 54857dacad5SJay Sternberg { 54990ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 55090ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 55190ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 55290ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 55304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 55404f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 55504f3eafdSJens Axboe } 55604f3eafdSJens Axboe 55704f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 55804f3eafdSJens Axboe { 55904f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 56004f3eafdSJens Axboe 56104f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 56204f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 56304f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 56490ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 56557dacad5SJay Sternberg } 56657dacad5SJay Sternberg 567a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 56857dacad5SJay Sternberg { 569f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 570a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 57157dacad5SJay Sternberg } 57257dacad5SJay Sternberg 573955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 574955b1b5aSMinwoo Im { 575955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 57620469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 577955b1b5aSMinwoo Im unsigned int avg_seg_size; 578955b1b5aSMinwoo Im 57920469a37SKeith Busch if (nseg == 0) 58020469a37SKeith Busch return false; 58120469a37SKeith Busch 58220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 583955b1b5aSMinwoo Im 584955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 585955b1b5aSMinwoo Im return false; 586955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 587955b1b5aSMinwoo Im return false; 588955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 589955b1b5aSMinwoo Im return false; 590955b1b5aSMinwoo Im return true; 591955b1b5aSMinwoo Im } 592955b1b5aSMinwoo Im 593fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 59457dacad5SJay Sternberg { 595f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 596f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 597b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 598f4800d6dSChristoph Hellwig 599955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 600955b1b5aSMinwoo Im 601f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 602943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 603f4800d6dSChristoph Hellwig if (!iod->sg) 604fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 605f4800d6dSChristoph Hellwig } else { 606f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 60757dacad5SJay Sternberg } 60857dacad5SJay Sternberg 609f4800d6dSChristoph Hellwig iod->aborted = 0; 61057dacad5SJay Sternberg iod->npages = -1; 61157dacad5SJay Sternberg iod->nents = 0; 612f4800d6dSChristoph Hellwig iod->length = size; 613f80ec966SKeith Busch 614fc17b653SChristoph Hellwig return BLK_STS_OK; 61557dacad5SJay Sternberg } 61657dacad5SJay Sternberg 617f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 61857dacad5SJay Sternberg { 619f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 620a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 621a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 622a7a7cbe3SChaitanya Kulkarni 62357dacad5SJay Sternberg int i; 62457dacad5SJay Sternberg 62557dacad5SJay Sternberg if (iod->npages == 0) 626a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 627a7a7cbe3SChaitanya Kulkarni dma_addr); 628a7a7cbe3SChaitanya Kulkarni 62957dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 630a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 631a7a7cbe3SChaitanya Kulkarni 632a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 633a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 634a7a7cbe3SChaitanya Kulkarni 635a7a7cbe3SChaitanya Kulkarni next_dma_addr = 636a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 637a7a7cbe3SChaitanya Kulkarni } else { 638a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 639a7a7cbe3SChaitanya Kulkarni 640a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 641a7a7cbe3SChaitanya Kulkarni } 642a7a7cbe3SChaitanya Kulkarni 643a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 644a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 64557dacad5SJay Sternberg } 64657dacad5SJay Sternberg 647f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 648943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 64957dacad5SJay Sternberg } 65057dacad5SJay Sternberg 651d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 652d0877473SKeith Busch { 653d0877473SKeith Busch int i; 654d0877473SKeith Busch struct scatterlist *sg; 655d0877473SKeith Busch 656d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 657d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 658d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 659d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 660d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 661d0877473SKeith Busch sg_dma_len(sg)); 662d0877473SKeith Busch } 663d0877473SKeith Busch } 664d0877473SKeith Busch 665a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 666a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 66757dacad5SJay Sternberg { 668f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 66957dacad5SJay Sternberg struct dma_pool *pool; 670b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 67157dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 67257dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 67357dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6745fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 67557dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 67657dacad5SJay Sternberg __le64 *prp_list; 677a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 67857dacad5SJay Sternberg dma_addr_t prp_dma; 67957dacad5SJay Sternberg int nprps, i; 68057dacad5SJay Sternberg 68157dacad5SJay Sternberg length -= (page_size - offset); 6825228b328SJan H. Schönherr if (length <= 0) { 6835228b328SJan H. Schönherr iod->first_dma = 0; 684a7a7cbe3SChaitanya Kulkarni goto done; 6855228b328SJan H. Schönherr } 68657dacad5SJay Sternberg 68757dacad5SJay Sternberg dma_len -= (page_size - offset); 68857dacad5SJay Sternberg if (dma_len) { 68957dacad5SJay Sternberg dma_addr += (page_size - offset); 69057dacad5SJay Sternberg } else { 69157dacad5SJay Sternberg sg = sg_next(sg); 69257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69457dacad5SJay Sternberg } 69557dacad5SJay Sternberg 69657dacad5SJay Sternberg if (length <= page_size) { 69757dacad5SJay Sternberg iod->first_dma = dma_addr; 698a7a7cbe3SChaitanya Kulkarni goto done; 69957dacad5SJay Sternberg } 70057dacad5SJay Sternberg 70157dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 70257dacad5SJay Sternberg if (nprps <= (256 / 8)) { 70357dacad5SJay Sternberg pool = dev->prp_small_pool; 70457dacad5SJay Sternberg iod->npages = 0; 70557dacad5SJay Sternberg } else { 70657dacad5SJay Sternberg pool = dev->prp_page_pool; 70757dacad5SJay Sternberg iod->npages = 1; 70857dacad5SJay Sternberg } 70957dacad5SJay Sternberg 71069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 71157dacad5SJay Sternberg if (!prp_list) { 71257dacad5SJay Sternberg iod->first_dma = dma_addr; 71357dacad5SJay Sternberg iod->npages = -1; 71486eea289SKeith Busch return BLK_STS_RESOURCE; 71557dacad5SJay Sternberg } 71657dacad5SJay Sternberg list[0] = prp_list; 71757dacad5SJay Sternberg iod->first_dma = prp_dma; 71857dacad5SJay Sternberg i = 0; 71957dacad5SJay Sternberg for (;;) { 72057dacad5SJay Sternberg if (i == page_size >> 3) { 72157dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 72269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 72357dacad5SJay Sternberg if (!prp_list) 72486eea289SKeith Busch return BLK_STS_RESOURCE; 72557dacad5SJay Sternberg list[iod->npages++] = prp_list; 72657dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 72757dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 72857dacad5SJay Sternberg i = 1; 72957dacad5SJay Sternberg } 73057dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 73157dacad5SJay Sternberg dma_len -= page_size; 73257dacad5SJay Sternberg dma_addr += page_size; 73357dacad5SJay Sternberg length -= page_size; 73457dacad5SJay Sternberg if (length <= 0) 73557dacad5SJay Sternberg break; 73657dacad5SJay Sternberg if (dma_len > 0) 73757dacad5SJay Sternberg continue; 73886eea289SKeith Busch if (unlikely(dma_len < 0)) 73986eea289SKeith Busch goto bad_sgl; 74057dacad5SJay Sternberg sg = sg_next(sg); 74157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 74257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 74357dacad5SJay Sternberg } 74457dacad5SJay Sternberg 745a7a7cbe3SChaitanya Kulkarni done: 746a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 747a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 748a7a7cbe3SChaitanya Kulkarni 74986eea289SKeith Busch return BLK_STS_OK; 75086eea289SKeith Busch 75186eea289SKeith Busch bad_sgl: 752d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 753d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 754d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 75586eea289SKeith Busch return BLK_STS_IOERR; 75657dacad5SJay Sternberg } 75757dacad5SJay Sternberg 758a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 759a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 760a7a7cbe3SChaitanya Kulkarni { 761a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 762a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 763a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 764a7a7cbe3SChaitanya Kulkarni } 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 767a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 768a7a7cbe3SChaitanya Kulkarni { 769a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 770a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 771a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 772a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 773a7a7cbe3SChaitanya Kulkarni } else { 774a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 775a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 776a7a7cbe3SChaitanya Kulkarni } 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 780b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 781a7a7cbe3SChaitanya Kulkarni { 782a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 783a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 784a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 785a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 786a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 787b0f2853bSChristoph Hellwig int i = 0; 788a7a7cbe3SChaitanya Kulkarni 789a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 790a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 791a7a7cbe3SChaitanya Kulkarni 792b0f2853bSChristoph Hellwig if (entries == 1) { 793a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 794a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 795a7a7cbe3SChaitanya Kulkarni } 796a7a7cbe3SChaitanya Kulkarni 797a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 798a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 799a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 800a7a7cbe3SChaitanya Kulkarni } else { 801a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 802a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 803a7a7cbe3SChaitanya Kulkarni } 804a7a7cbe3SChaitanya Kulkarni 805a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 806a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 807a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 808a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 809a7a7cbe3SChaitanya Kulkarni } 810a7a7cbe3SChaitanya Kulkarni 811a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 812a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 813a7a7cbe3SChaitanya Kulkarni 814a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 815a7a7cbe3SChaitanya Kulkarni 816a7a7cbe3SChaitanya Kulkarni do { 817a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 818a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 819a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 820a7a7cbe3SChaitanya Kulkarni 821a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 822a7a7cbe3SChaitanya Kulkarni if (!sg_list) 823a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 824a7a7cbe3SChaitanya Kulkarni 825a7a7cbe3SChaitanya Kulkarni i = 0; 826a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 827a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 828a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 829a7a7cbe3SChaitanya Kulkarni } 830a7a7cbe3SChaitanya Kulkarni 831a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 832a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 833b0f2853bSChristoph Hellwig } while (--entries > 0); 834a7a7cbe3SChaitanya Kulkarni 835a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 836a7a7cbe3SChaitanya Kulkarni } 837a7a7cbe3SChaitanya Kulkarni 838fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 839b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84057dacad5SJay Sternberg { 841f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 842ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 843ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 844ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 845fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 846b0f2853bSChristoph Hellwig int nr_mapped; 84757dacad5SJay Sternberg 848f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 849ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 850ba1ca37eSChristoph Hellwig if (!iod->nents) 851ba1ca37eSChristoph Hellwig goto out; 852ba1ca37eSChristoph Hellwig 853fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 854e0596ab2SLogan Gunthorpe 855e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 856e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 857e0596ab2SLogan Gunthorpe dma_dir); 858e0596ab2SLogan Gunthorpe else 859e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 860e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 861b0f2853bSChristoph Hellwig if (!nr_mapped) 862ba1ca37eSChristoph Hellwig goto out; 863ba1ca37eSChristoph Hellwig 864955b1b5aSMinwoo Im if (iod->use_sgl) 865b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 866a7a7cbe3SChaitanya Kulkarni else 867a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 868a7a7cbe3SChaitanya Kulkarni 86986eea289SKeith Busch if (ret != BLK_STS_OK) 870ba1ca37eSChristoph Hellwig goto out_unmap; 871ba1ca37eSChristoph Hellwig 872fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 873ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 874ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 875ba1ca37eSChristoph Hellwig goto out_unmap; 876ba1ca37eSChristoph Hellwig 877bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 878bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 879ba1ca37eSChristoph Hellwig goto out_unmap; 880ba1ca37eSChristoph Hellwig 881bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 882ba1ca37eSChristoph Hellwig goto out_unmap; 8833045c0d0SChaitanya Kulkarni 8843045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 88557dacad5SJay Sternberg } 88657dacad5SJay Sternberg 887fc17b653SChristoph Hellwig return BLK_STS_OK; 888ba1ca37eSChristoph Hellwig 889ba1ca37eSChristoph Hellwig out_unmap: 890ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 891ba1ca37eSChristoph Hellwig out: 892ba1ca37eSChristoph Hellwig return ret; 89357dacad5SJay Sternberg } 89457dacad5SJay Sternberg 895f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 896d4f6c3abSChristoph Hellwig { 897f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 898d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 899d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 900d4f6c3abSChristoph Hellwig 901d4f6c3abSChristoph Hellwig if (iod->nents) { 902e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 903e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 904d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 905e0596ab2SLogan Gunthorpe 906f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 907bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 908d4f6c3abSChristoph Hellwig } 909d4f6c3abSChristoph Hellwig 910f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 911f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 91257dacad5SJay Sternberg } 91357dacad5SJay Sternberg 91457dacad5SJay Sternberg /* 91557dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91657dacad5SJay Sternberg */ 917fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91857dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91957dacad5SJay Sternberg { 92057dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 92157dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92357dacad5SJay Sternberg struct request *req = bd->rq; 924ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 925ebe6d874SChristoph Hellwig blk_status_t ret; 92657dacad5SJay Sternberg 927d1f06f4aSJens Axboe /* 928d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 929d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 930d1f06f4aSJens Axboe */ 9314e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 932d1f06f4aSJens Axboe return BLK_STS_IOERR; 933d1f06f4aSJens Axboe 934f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 935fc17b653SChristoph Hellwig if (ret) 936f4800d6dSChristoph Hellwig return ret; 93757dacad5SJay Sternberg 938b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 939fc17b653SChristoph Hellwig if (ret) 940f9d03f96SChristoph Hellwig goto out_free_cmd; 94157dacad5SJay Sternberg 942fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 943b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 944fc17b653SChristoph Hellwig if (ret) 945f9d03f96SChristoph Hellwig goto out_cleanup_iod; 946fc17b653SChristoph Hellwig } 947ba1ca37eSChristoph Hellwig 948aae239e1SChristoph Hellwig blk_mq_start_request(req); 94904f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 950fc17b653SChristoph Hellwig return BLK_STS_OK; 951f9d03f96SChristoph Hellwig out_cleanup_iod: 952f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 953f9d03f96SChristoph Hellwig out_free_cmd: 954f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 955ba1ca37eSChristoph Hellwig return ret; 95657dacad5SJay Sternberg } 95757dacad5SJay Sternberg 95877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 959eee417b0SChristoph Hellwig { 960f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 961eee417b0SChristoph Hellwig 96277f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 96377f02a7aSChristoph Hellwig nvme_complete_rq(req); 96457dacad5SJay Sternberg } 96557dacad5SJay Sternberg 966d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 967750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 968d783e0bdSMarta Rybczynska { 969750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 970750dde44SChristoph Hellwig nvmeq->cq_phase; 971d783e0bdSMarta Rybczynska } 972d783e0bdSMarta Rybczynska 973eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 97457dacad5SJay Sternberg { 975eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 97657dacad5SJay Sternberg 977eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 978eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 979eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 980eb281c82SSagi Grimberg } 981adf68f21SChristoph Hellwig 9825cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 98357dacad5SJay Sternberg { 9845cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 98557dacad5SJay Sternberg struct request *req; 986adf68f21SChristoph Hellwig 98783a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9881b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 989aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 99083a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 99183a12fb7SSagi Grimberg return; 992aae239e1SChristoph Hellwig } 993aae239e1SChristoph Hellwig 994adf68f21SChristoph Hellwig /* 995adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 996adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 997adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 998adf68f21SChristoph Hellwig * for them but rather special case them here. 999adf68f21SChristoph Hellwig */ 1000adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 100138dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 10027bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 100383a12fb7SSagi Grimberg cqe->status, &cqe->result); 1004a0fa9647SJens Axboe return; 100557dacad5SJay Sternberg } 100657dacad5SJay Sternberg 100783a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 1008604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 100983a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 101083a12fb7SSagi Grimberg } 101157dacad5SJay Sternberg 10125cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 101383a12fb7SSagi Grimberg { 10145cb525c8SJens Axboe while (start != end) { 10155cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10165cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10175cb525c8SJens Axboe start = 0; 10185cb525c8SJens Axboe } 10195cb525c8SJens Axboe } 102083a12fb7SSagi Grimberg 10215cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10225cb525c8SJens Axboe { 1023dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1024920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1025920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1026dcca1662SHongbo Yao } else { 1027dcca1662SHongbo Yao nvmeq->cq_head++; 1028920d13a8SSagi Grimberg } 1029a0fa9647SJens Axboe } 1030a0fa9647SJens Axboe 10311052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10321052b8acSJens Axboe u16 *end, unsigned int tag) 1033a0fa9647SJens Axboe { 10341052b8acSJens Axboe int found = 0; 103583a12fb7SSagi Grimberg 10365cb525c8SJens Axboe *start = nvmeq->cq_head; 10371052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10381052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10391052b8acSJens Axboe found++; 10405cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 104157dacad5SJay Sternberg } 10425cb525c8SJens Axboe *end = nvmeq->cq_head; 104357dacad5SJay Sternberg 10445cb525c8SJens Axboe if (*start != *end) 1045eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10465cb525c8SJens Axboe return found; 104757dacad5SJay Sternberg } 104857dacad5SJay Sternberg 104957dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 105057dacad5SJay Sternberg { 105157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 105268fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10535cb525c8SJens Axboe u16 start, end; 10545cb525c8SJens Axboe 10553a7afd8eSChristoph Hellwig /* 10563a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10573a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10583a7afd8eSChristoph Hellwig */ 10593a7afd8eSChristoph Hellwig rmb(); 106068fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 106168fa9dbeSJens Axboe ret = IRQ_HANDLED; 10625cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 106368fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10643a7afd8eSChristoph Hellwig wmb(); 10655cb525c8SJens Axboe 106668fa9dbeSJens Axboe if (start != end) { 10675cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10685cb525c8SJens Axboe return IRQ_HANDLED; 106957dacad5SJay Sternberg } 107057dacad5SJay Sternberg 107168fa9dbeSJens Axboe return ret; 107257dacad5SJay Sternberg } 107357dacad5SJay Sternberg 107457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 107557dacad5SJay Sternberg { 107657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1077750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107857dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1079d783e0bdSMarta Rybczynska return IRQ_NONE; 108057dacad5SJay Sternberg } 108157dacad5SJay Sternberg 10820b2a8a9fSChristoph Hellwig /* 10830b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10840b2a8a9fSChristoph Hellwig * Can be called from any context. 10850b2a8a9fSChristoph Hellwig */ 10860b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1087a0fa9647SJens Axboe { 10883a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10895cb525c8SJens Axboe u16 start, end; 10901052b8acSJens Axboe int found; 1091a0fa9647SJens Axboe 10923a7afd8eSChristoph Hellwig /* 10933a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10943a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10953a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10963a7afd8eSChristoph Hellwig */ 109791a509f8SChristoph Hellwig if (nvmeq->cq_vector == -1) { 10983a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 109991a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 110091a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 110191a509f8SChristoph Hellwig } else { 11023a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 11035cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 11043a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 110591a509f8SChristoph Hellwig } 1106442e19b7SSagi Grimberg 11075cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1108442e19b7SSagi Grimberg return found; 1109a0fa9647SJens Axboe } 1110a0fa9647SJens Axboe 11119743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 11127776db1cSKeith Busch { 11137776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1114dabcefabSJens Axboe u16 start, end; 1115dabcefabSJens Axboe bool found; 1116dabcefabSJens Axboe 1117dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1118dabcefabSJens Axboe return 0; 1119dabcefabSJens Axboe 11203a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11219743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11223a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1123dabcefabSJens Axboe 1124dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1125dabcefabSJens Axboe return found; 1126dabcefabSJens Axboe } 1127dabcefabSJens Axboe 1128ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 112957dacad5SJay Sternberg { 1130f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1131147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 113257dacad5SJay Sternberg struct nvme_command c; 113357dacad5SJay Sternberg 113457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1136ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 113704f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 113857dacad5SJay Sternberg } 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 114157dacad5SJay Sternberg { 114257dacad5SJay Sternberg struct nvme_command c; 114357dacad5SJay Sternberg 114457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 114557dacad5SJay Sternberg c.delete_queue.opcode = opcode; 114657dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 114757dacad5SJay Sternberg 11481c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 114957dacad5SJay Sternberg } 115057dacad5SJay Sternberg 115157dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1152a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 115357dacad5SJay Sternberg { 115457dacad5SJay Sternberg struct nvme_command c; 11554b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11564b04cc6aSJens Axboe 11574b04cc6aSJens Axboe if (vector != -1) 11584b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 115957dacad5SJay Sternberg 116057dacad5SJay Sternberg /* 116116772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 116257dacad5SJay Sternberg * is attached to the request. 116357dacad5SJay Sternberg */ 116457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 116557dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 116657dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 116757dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 116857dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 116957dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 11704b04cc6aSJens Axboe if (vector != -1) 1171a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 11724b04cc6aSJens Axboe else 11734b04cc6aSJens Axboe c.create_cq.irq_vector = 0; 117457dacad5SJay Sternberg 11751c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117657dacad5SJay Sternberg } 117757dacad5SJay Sternberg 117857dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 117957dacad5SJay Sternberg struct nvme_queue *nvmeq) 118057dacad5SJay Sternberg { 11819abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 118257dacad5SJay Sternberg struct nvme_command c; 118381c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 118457dacad5SJay Sternberg 118557dacad5SJay Sternberg /* 11869abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11879abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11889abd68efSJens Axboe * URGENT. 11899abd68efSJens Axboe */ 11909abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11919abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11929abd68efSJens Axboe 11939abd68efSJens Axboe /* 119416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 119557dacad5SJay Sternberg * is attached to the request. 119657dacad5SJay Sternberg */ 119757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 119857dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 119957dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 120057dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 120157dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 120257dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 120357dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 120457dacad5SJay Sternberg 12051c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120657dacad5SJay Sternberg } 120757dacad5SJay Sternberg 120857dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 120957dacad5SJay Sternberg { 121057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 121457dacad5SJay Sternberg { 121557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 121657dacad5SJay Sternberg } 121757dacad5SJay Sternberg 12182a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 121957dacad5SJay Sternberg { 1220f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1221f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 122257dacad5SJay Sternberg 122327fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 122427fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1225e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1226e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 122757dacad5SJay Sternberg } 122857dacad5SJay Sternberg 1229b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1230b2a0eb1aSKeith Busch { 1231b2a0eb1aSKeith Busch 1232b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1233b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1234b2a0eb1aSKeith Busch */ 1235b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1236b2a0eb1aSKeith Busch 1237ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1238ad70062cSJianchao Wang switch (dev->ctrl.state) { 1239ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1240ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1241b2a0eb1aSKeith Busch return false; 1242ad70062cSJianchao Wang default: 1243ad70062cSJianchao Wang break; 1244ad70062cSJianchao Wang } 1245b2a0eb1aSKeith Busch 1246b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1247b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1248b2a0eb1aSKeith Busch */ 1249b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1250b2a0eb1aSKeith Busch return false; 1251b2a0eb1aSKeith Busch 1252b2a0eb1aSKeith Busch return true; 1253b2a0eb1aSKeith Busch } 1254b2a0eb1aSKeith Busch 1255b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1256b2a0eb1aSKeith Busch { 1257b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1258b2a0eb1aSKeith Busch u16 pci_status; 1259b2a0eb1aSKeith Busch int result; 1260b2a0eb1aSKeith Busch 1261b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1262b2a0eb1aSKeith Busch &pci_status); 1263b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1264b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1265b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1266b2a0eb1aSKeith Busch csts, pci_status); 1267b2a0eb1aSKeith Busch else 1268b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1269b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1270b2a0eb1aSKeith Busch csts, result); 1271b2a0eb1aSKeith Busch } 1272b2a0eb1aSKeith Busch 127331c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 127457dacad5SJay Sternberg { 1275f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1276f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 127757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 127857dacad5SJay Sternberg struct request *abort_req; 127957dacad5SJay Sternberg struct nvme_command cmd; 1280b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1281b2a0eb1aSKeith Busch 1282651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1283651438bbSWen Xiong * the recovery mechanism will surely fail. 1284651438bbSWen Xiong */ 1285651438bbSWen Xiong mb(); 1286651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1287651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1288651438bbSWen Xiong 1289b2a0eb1aSKeith Busch /* 1290b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1291b2a0eb1aSKeith Busch */ 1292b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1293b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1294b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1295d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1296db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1297b2a0eb1aSKeith Busch } 129857dacad5SJay Sternberg 129931c7c7d2SChristoph Hellwig /* 13007776db1cSKeith Busch * Did we miss an interrupt? 13017776db1cSKeith Busch */ 13020b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 13037776db1cSKeith Busch dev_warn(dev->ctrl.device, 13047776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13057776db1cSKeith Busch req->tag, nvmeq->qid); 1306db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13077776db1cSKeith Busch } 13087776db1cSKeith Busch 13097776db1cSKeith Busch /* 1310fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1311fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1312fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1313db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1314fd634f41SChristoph Hellwig */ 13154244140dSKeith Busch switch (dev->ctrl.state) { 13164244140dSKeith Busch case NVME_CTRL_CONNECTING: 13174244140dSKeith Busch case NVME_CTRL_RESETTING: 1318b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1319fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1320fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1321a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 132227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1323db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13244244140dSKeith Busch default: 13254244140dSKeith Busch break; 1326fd634f41SChristoph Hellwig } 1327fd634f41SChristoph Hellwig 1328fd634f41SChristoph Hellwig /* 1329e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1330e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1331e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 133231c7c7d2SChristoph Hellwig */ 1333f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13341b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 133557dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 133657dacad5SJay Sternberg req->tag, nvmeq->qid); 1337a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1338d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1339e1569a16SKeith Busch 134027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1341db8c48e4SChristoph Hellwig return BLK_EH_DONE; 134257dacad5SJay Sternberg } 134357dacad5SJay Sternberg 1344e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1345e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1346e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1347e7a2a87dSChristoph Hellwig } 13487bf7d778SKeith Busch iod->aborted = 1; 134957dacad5SJay Sternberg 135057dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 135157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 135257dacad5SJay Sternberg cmd.abort.cid = req->tag; 135357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 135457dacad5SJay Sternberg 13551b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13561b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 135757dacad5SJay Sternberg req->tag, nvmeq->qid); 1358e7a2a87dSChristoph Hellwig 1359e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1360eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13616bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13626bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 136331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 136457dacad5SJay Sternberg } 136557dacad5SJay Sternberg 1366e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1367e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1368e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 136957dacad5SJay Sternberg 137057dacad5SJay Sternberg /* 137157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 137257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 137357dacad5SJay Sternberg * as the device then is in a faulty state. 137457dacad5SJay Sternberg */ 137557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 137657dacad5SJay Sternberg } 137757dacad5SJay Sternberg 137857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 137957dacad5SJay Sternberg { 138057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 138157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 138263223078SChristoph Hellwig if (!nvmeq->sq_cmds) 138363223078SChristoph Hellwig return; 13840f238ff5SLogan Gunthorpe 138563223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 13860f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 138763223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 138863223078SChristoph Hellwig } else { 138963223078SChristoph Hellwig dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 139063223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13910f238ff5SLogan Gunthorpe } 139257dacad5SJay Sternberg } 139357dacad5SJay Sternberg 139457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 139557dacad5SJay Sternberg { 139657dacad5SJay Sternberg int i; 139757dacad5SJay Sternberg 1398d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1399d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1400147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 140157dacad5SJay Sternberg } 140257dacad5SJay Sternberg } 140357dacad5SJay Sternberg 140457dacad5SJay Sternberg /** 140557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 140640581d1aSBart Van Assche * @nvmeq: queue to suspend 140757dacad5SJay Sternberg */ 140857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 140957dacad5SJay Sternberg { 14104e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 141157dacad5SJay Sternberg return 1; 141257dacad5SJay Sternberg 14134e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1414d1f06f4aSJens Axboe mb(); 141557dacad5SJay Sternberg 14164e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14171c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1418c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14194e224106SChristoph Hellwig if (nvmeq->cq_vector == -1) 14204e224106SChristoph Hellwig return 0; 14214e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 14224e224106SChristoph Hellwig nvmeq->cq_vector = -1; 142357dacad5SJay Sternberg return 0; 142457dacad5SJay Sternberg } 142557dacad5SJay Sternberg 14268fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14278fae268bSKeith Busch { 14288fae268bSKeith Busch int i; 14298fae268bSKeith Busch 14308fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14318fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14328fae268bSKeith Busch } 14338fae268bSKeith Busch 1434a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 143557dacad5SJay Sternberg { 1436147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 143757dacad5SJay Sternberg 1438a5cdb68cSKeith Busch if (shutdown) 1439a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1440a5cdb68cSKeith Busch else 144120d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 144257dacad5SJay Sternberg 14430b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 144457dacad5SJay Sternberg } 144557dacad5SJay Sternberg 144657dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 144757dacad5SJay Sternberg int entry_size) 144857dacad5SJay Sternberg { 144957dacad5SJay Sternberg int q_depth = dev->q_depth; 14505fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14515fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 145257dacad5SJay Sternberg 145357dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 145457dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14555fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 145657dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 145757dacad5SJay Sternberg 145857dacad5SJay Sternberg /* 145957dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 146057dacad5SJay Sternberg * would be better to map queues in system memory with the 146157dacad5SJay Sternberg * original depth 146257dacad5SJay Sternberg */ 146357dacad5SJay Sternberg if (q_depth < 64) 146457dacad5SJay Sternberg return -ENOMEM; 146557dacad5SJay Sternberg } 146657dacad5SJay Sternberg 146757dacad5SJay Sternberg return q_depth; 146857dacad5SJay Sternberg } 146957dacad5SJay Sternberg 147057dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 147157dacad5SJay Sternberg int qid, int depth) 147257dacad5SJay Sternberg { 14730f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1474815c6704SKeith Busch 14750f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14760f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14770f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14780f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 147963223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 148063223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 148163223078SChristoph Hellwig return 0; 148263223078SChristoph Hellwig } 14830f238ff5SLogan Gunthorpe } 14840f238ff5SLogan Gunthorpe 148557dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 148657dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 148757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 148857dacad5SJay Sternberg return -ENOMEM; 148957dacad5SJay Sternberg return 0; 149057dacad5SJay Sternberg } 149157dacad5SJay Sternberg 1492a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 149357dacad5SJay Sternberg { 1494147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 149557dacad5SJay Sternberg 149662314e40SKeith Busch if (dev->ctrl.queue_count > qid) 149762314e40SKeith Busch return 0; 149857dacad5SJay Sternberg 149957dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 150057dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 150157dacad5SJay Sternberg if (!nvmeq->cqes) 150257dacad5SJay Sternberg goto free_nvmeq; 150357dacad5SJay Sternberg 150457dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 150557dacad5SJay Sternberg goto free_cqdma; 150657dacad5SJay Sternberg 150757dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 150857dacad5SJay Sternberg nvmeq->dev = dev; 15091ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15103a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 151157dacad5SJay Sternberg nvmeq->cq_head = 0; 151257dacad5SJay Sternberg nvmeq->cq_phase = 1; 151357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 151457dacad5SJay Sternberg nvmeq->q_depth = depth; 151557dacad5SJay Sternberg nvmeq->qid = qid; 151657dacad5SJay Sternberg nvmeq->cq_vector = -1; 1517d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 151857dacad5SJay Sternberg 1519147b27e4SSagi Grimberg return 0; 152057dacad5SJay Sternberg 152157dacad5SJay Sternberg free_cqdma: 152257dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 152357dacad5SJay Sternberg nvmeq->cq_dma_addr); 152457dacad5SJay Sternberg free_nvmeq: 1525147b27e4SSagi Grimberg return -ENOMEM; 152657dacad5SJay Sternberg } 152757dacad5SJay Sternberg 1528dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 152957dacad5SJay Sternberg { 15300ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15310ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15320ff199cbSChristoph Hellwig 15330ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15340ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15350ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15360ff199cbSChristoph Hellwig } else { 15370ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15380ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15390ff199cbSChristoph Hellwig } 154057dacad5SJay Sternberg } 154157dacad5SJay Sternberg 154257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 154357dacad5SJay Sternberg { 154457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154557dacad5SJay Sternberg 154657dacad5SJay Sternberg nvmeq->sq_tail = 0; 154704f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 154857dacad5SJay Sternberg nvmeq->cq_head = 0; 154957dacad5SJay Sternberg nvmeq->cq_phase = 1; 155057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 155157dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1552f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 155357dacad5SJay Sternberg dev->online_queues++; 15543a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 155557dacad5SJay Sternberg } 155657dacad5SJay Sternberg 15574b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 155857dacad5SJay Sternberg { 155957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 156057dacad5SJay Sternberg int result; 1561a8e3e0bbSJianchao Wang s16 vector; 156257dacad5SJay Sternberg 1563d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1564d1ed6aa1SChristoph Hellwig 156522b55601SKeith Busch /* 156622b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 156722b55601SKeith Busch * has only one vector available. 156822b55601SKeith Busch */ 15694b04cc6aSJens Axboe if (!polled) 1570a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15714b04cc6aSJens Axboe else 15724b04cc6aSJens Axboe vector = -1; 15734b04cc6aSJens Axboe 1574a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1575ded45505SKeith Busch if (result) 1576ded45505SKeith Busch return result; 157757dacad5SJay Sternberg 157857dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 157957dacad5SJay Sternberg if (result < 0) 1580ded45505SKeith Busch return result; 1581ded45505SKeith Busch else if (result) 158257dacad5SJay Sternberg goto release_cq; 158357dacad5SJay Sternberg 1584a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1585161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15864b04cc6aSJens Axboe 15874b04cc6aSJens Axboe if (vector != -1) { 1588dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 158957dacad5SJay Sternberg if (result < 0) 159057dacad5SJay Sternberg goto release_sq; 15914b04cc6aSJens Axboe } 159257dacad5SJay Sternberg 15934e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 159457dacad5SJay Sternberg return result; 159557dacad5SJay Sternberg 159657dacad5SJay Sternberg release_sq: 1597a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1598f25a2dfcSJianchao Wang dev->online_queues--; 159957dacad5SJay Sternberg adapter_delete_sq(dev, qid); 160057dacad5SJay Sternberg release_cq: 160157dacad5SJay Sternberg adapter_delete_cq(dev, qid); 160257dacad5SJay Sternberg return result; 160357dacad5SJay Sternberg } 160457dacad5SJay Sternberg 1605f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 160657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 160777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 160857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 160957dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 16100350815aSChristoph Hellwig .init_request = nvme_init_request, 161157dacad5SJay Sternberg .timeout = nvme_timeout, 161257dacad5SJay Sternberg }; 161357dacad5SJay Sternberg 1614f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1615376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1616376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1617376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1618376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1619376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1620376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1621376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1622c6d962aeSChristoph Hellwig .poll = nvme_poll, 1623dabcefabSJens Axboe }; 1624dabcefabSJens Axboe 162557dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 162657dacad5SJay Sternberg { 16271c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 162869d9a99cSKeith Busch /* 162969d9a99cSKeith Busch * If the controller was reset during removal, it's possible 163069d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 163169d9a99cSKeith Busch * queue to flush these to completion. 163269d9a99cSKeith Busch */ 1633c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16341c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 163557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163657dacad5SJay Sternberg } 163757dacad5SJay Sternberg } 163857dacad5SJay Sternberg 163957dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 164057dacad5SJay Sternberg { 16411c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 164257dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 164357dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1644e3e9d50cSKeith Busch 164538dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 164657dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 164757dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1648a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1649d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 165057dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 165157dacad5SJay Sternberg 165257dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 165357dacad5SJay Sternberg return -ENOMEM; 165434b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 165557dacad5SJay Sternberg 16561c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16571c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 165857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 165957dacad5SJay Sternberg return -ENOMEM; 166057dacad5SJay Sternberg } 16611c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 166257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16631c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 166457dacad5SJay Sternberg return -ENODEV; 166557dacad5SJay Sternberg } 166657dacad5SJay Sternberg } else 1667c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 166857dacad5SJay Sternberg 166957dacad5SJay Sternberg return 0; 167057dacad5SJay Sternberg } 167157dacad5SJay Sternberg 167297f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 167397f6ef64SXu Yu { 167497f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 167597f6ef64SXu Yu } 167697f6ef64SXu Yu 167797f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 167897f6ef64SXu Yu { 167997f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 168097f6ef64SXu Yu 168197f6ef64SXu Yu if (size <= dev->bar_mapped_size) 168297f6ef64SXu Yu return 0; 168397f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 168497f6ef64SXu Yu return -ENOMEM; 168597f6ef64SXu Yu if (dev->bar) 168697f6ef64SXu Yu iounmap(dev->bar); 168797f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 168897f6ef64SXu Yu if (!dev->bar) { 168997f6ef64SXu Yu dev->bar_mapped_size = 0; 169097f6ef64SXu Yu return -ENOMEM; 169197f6ef64SXu Yu } 169297f6ef64SXu Yu dev->bar_mapped_size = size; 169397f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 169497f6ef64SXu Yu 169597f6ef64SXu Yu return 0; 169697f6ef64SXu Yu } 169797f6ef64SXu Yu 169801ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 169957dacad5SJay Sternberg { 170057dacad5SJay Sternberg int result; 170157dacad5SJay Sternberg u32 aqa; 170257dacad5SJay Sternberg struct nvme_queue *nvmeq; 170357dacad5SJay Sternberg 170497f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 170597f6ef64SXu Yu if (result < 0) 170697f6ef64SXu Yu return result; 170797f6ef64SXu Yu 17088ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 170920d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 171057dacad5SJay Sternberg 17117a67cbeaSChristoph Hellwig if (dev->subsystem && 17127a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17137a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 171457dacad5SJay Sternberg 171520d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 171657dacad5SJay Sternberg if (result < 0) 171757dacad5SJay Sternberg return result; 171857dacad5SJay Sternberg 1719a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1720147b27e4SSagi Grimberg if (result) 1721147b27e4SSagi Grimberg return result; 172257dacad5SJay Sternberg 1723147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 172457dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 172557dacad5SJay Sternberg aqa |= aqa << 16; 172657dacad5SJay Sternberg 17277a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17287a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17297a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 173057dacad5SJay Sternberg 173120d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 173257dacad5SJay Sternberg if (result) 1733d4875622SKeith Busch return result; 173457dacad5SJay Sternberg 173557dacad5SJay Sternberg nvmeq->cq_vector = 0; 1736161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1737dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 173857dacad5SJay Sternberg if (result) { 173957dacad5SJay Sternberg nvmeq->cq_vector = -1; 1740d4875622SKeith Busch return result; 174157dacad5SJay Sternberg } 174257dacad5SJay Sternberg 17434e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 174457dacad5SJay Sternberg return result; 174557dacad5SJay Sternberg } 174657dacad5SJay Sternberg 1747749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 174857dacad5SJay Sternberg { 17494b04cc6aSJens Axboe unsigned i, max, rw_queues; 1750749941f2SChristoph Hellwig int ret = 0; 175157dacad5SJay Sternberg 1752d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1753a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1754749941f2SChristoph Hellwig ret = -ENOMEM; 175557dacad5SJay Sternberg break; 1756749941f2SChristoph Hellwig } 1757749941f2SChristoph Hellwig } 175857dacad5SJay Sternberg 1759d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1760e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1761e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1762e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17634b04cc6aSJens Axboe } else { 17644b04cc6aSJens Axboe rw_queues = max; 17654b04cc6aSJens Axboe } 17664b04cc6aSJens Axboe 1767949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17684b04cc6aSJens Axboe bool polled = i > rw_queues; 17694b04cc6aSJens Axboe 17704b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1771d4875622SKeith Busch if (ret) 177257dacad5SJay Sternberg break; 177357dacad5SJay Sternberg } 177457dacad5SJay Sternberg 1775749941f2SChristoph Hellwig /* 1776749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17778adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17788adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1779749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1780749941f2SChristoph Hellwig */ 1781749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 178257dacad5SJay Sternberg } 178357dacad5SJay Sternberg 1784202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1785202021c1SStephen Bates struct device_attribute *attr, 1786202021c1SStephen Bates char *buf) 1787202021c1SStephen Bates { 1788202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1789202021c1SStephen Bates 1790c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1791202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1792202021c1SStephen Bates } 1793202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1794202021c1SStephen Bates 179588de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 179657dacad5SJay Sternberg { 179788de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 179888de4598SChristoph Hellwig 179988de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 180088de4598SChristoph Hellwig } 180188de4598SChristoph Hellwig 180288de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 180388de4598SChristoph Hellwig { 180488de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 180588de4598SChristoph Hellwig } 180688de4598SChristoph Hellwig 1807f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 180857dacad5SJay Sternberg { 180988de4598SChristoph Hellwig u64 size, offset; 181057dacad5SJay Sternberg resource_size_t bar_size; 181157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18128969f1f8SChristoph Hellwig int bar; 181357dacad5SJay Sternberg 18149fe5c59fSKeith Busch if (dev->cmb_size) 18159fe5c59fSKeith Busch return; 18169fe5c59fSKeith Busch 18177a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1818f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1819f65efd6dSChristoph Hellwig return; 1820202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 182157dacad5SJay Sternberg 182288de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 182388de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18248969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18258969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 182657dacad5SJay Sternberg 182757dacad5SJay Sternberg if (offset > bar_size) 1828f65efd6dSChristoph Hellwig return; 182957dacad5SJay Sternberg 183057dacad5SJay Sternberg /* 183157dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 183257dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 183357dacad5SJay Sternberg * the reported size of the BAR 183457dacad5SJay Sternberg */ 183557dacad5SJay Sternberg if (size > bar_size - offset) 183657dacad5SJay Sternberg size = bar_size - offset; 183757dacad5SJay Sternberg 18380f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18390f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18400f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1841f65efd6dSChristoph Hellwig return; 18420f238ff5SLogan Gunthorpe } 18430f238ff5SLogan Gunthorpe 184457dacad5SJay Sternberg dev->cmb_size = size; 18450f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18460f238ff5SLogan Gunthorpe 18470f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18480f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18490f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1850f65efd6dSChristoph Hellwig 1851f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1852f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1853f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1854f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 185557dacad5SJay Sternberg } 185657dacad5SJay Sternberg 185757dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 185857dacad5SJay Sternberg { 18590f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1860f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1861f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18620f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1863f63572dfSJon Derrick } 186457dacad5SJay Sternberg } 186557dacad5SJay Sternberg 186687ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 186757dacad5SJay Sternberg { 18684033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 186987ad72a5SChristoph Hellwig struct nvme_command c; 187087ad72a5SChristoph Hellwig int ret; 187187ad72a5SChristoph Hellwig 187287ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 187387ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 187487ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 187587ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 187687ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 187787ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 187887ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 187987ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 188087ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 188187ad72a5SChristoph Hellwig 188287ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 188387ad72a5SChristoph Hellwig if (ret) { 188487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 188587ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 188687ad72a5SChristoph Hellwig ret, bits); 188787ad72a5SChristoph Hellwig } 188887ad72a5SChristoph Hellwig return ret; 188987ad72a5SChristoph Hellwig } 189087ad72a5SChristoph Hellwig 189187ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 189287ad72a5SChristoph Hellwig { 189387ad72a5SChristoph Hellwig int i; 189487ad72a5SChristoph Hellwig 189587ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 189687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 189787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 189887ad72a5SChristoph Hellwig 1899cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1900cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1901cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 190287ad72a5SChristoph Hellwig } 190387ad72a5SChristoph Hellwig 190487ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 190587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19064033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19074033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19084033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 190987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19107e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 191187ad72a5SChristoph Hellwig } 191287ad72a5SChristoph Hellwig 191392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 191492dc6895SChristoph Hellwig u32 chunk_size) 191587ad72a5SChristoph Hellwig { 191687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 191792dc6895SChristoph Hellwig u32 max_entries, len; 19184033f35dSChristoph Hellwig dma_addr_t descs_dma; 19192ee0e4edSDan Carpenter int i = 0; 192087ad72a5SChristoph Hellwig void **bufs; 19216fbcde66SMinwoo Im u64 size, tmp; 192287ad72a5SChristoph Hellwig 192387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 192487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 192587ad72a5SChristoph Hellwig max_entries = tmp; 1926044a9df1SChristoph Hellwig 1927044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1928044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1929044a9df1SChristoph Hellwig 19304033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 19314033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 193287ad72a5SChristoph Hellwig if (!descs) 193387ad72a5SChristoph Hellwig goto out; 193487ad72a5SChristoph Hellwig 193587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 193687ad72a5SChristoph Hellwig if (!bufs) 193787ad72a5SChristoph Hellwig goto out_free_descs; 193887ad72a5SChristoph Hellwig 1939244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 194087ad72a5SChristoph Hellwig dma_addr_t dma_addr; 194187ad72a5SChristoph Hellwig 194250cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 194387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 194487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 194587ad72a5SChristoph Hellwig if (!bufs[i]) 194687ad72a5SChristoph Hellwig break; 194787ad72a5SChristoph Hellwig 194887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 194987ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 195087ad72a5SChristoph Hellwig i++; 195187ad72a5SChristoph Hellwig } 195287ad72a5SChristoph Hellwig 195392dc6895SChristoph Hellwig if (!size) 195487ad72a5SChristoph Hellwig goto out_free_bufs; 195587ad72a5SChristoph Hellwig 195687ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 195787ad72a5SChristoph Hellwig dev->host_mem_size = size; 195887ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19594033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 196087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 196187ad72a5SChristoph Hellwig return 0; 196287ad72a5SChristoph Hellwig 196387ad72a5SChristoph Hellwig out_free_bufs: 196487ad72a5SChristoph Hellwig while (--i >= 0) { 196587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 196687ad72a5SChristoph Hellwig 1967cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1968cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1969cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 197087ad72a5SChristoph Hellwig } 197187ad72a5SChristoph Hellwig 197287ad72a5SChristoph Hellwig kfree(bufs); 197387ad72a5SChristoph Hellwig out_free_descs: 19744033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19754033f35dSChristoph Hellwig descs_dma); 197687ad72a5SChristoph Hellwig out: 197787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 197887ad72a5SChristoph Hellwig return -ENOMEM; 197987ad72a5SChristoph Hellwig } 198087ad72a5SChristoph Hellwig 198192dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 198292dc6895SChristoph Hellwig { 198392dc6895SChristoph Hellwig u32 chunk_size; 198492dc6895SChristoph Hellwig 198592dc6895SChristoph Hellwig /* start big and work our way down */ 198630f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1987044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 198892dc6895SChristoph Hellwig chunk_size /= 2) { 198992dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 199092dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 199192dc6895SChristoph Hellwig return 0; 199292dc6895SChristoph Hellwig nvme_free_host_mem(dev); 199392dc6895SChristoph Hellwig } 199492dc6895SChristoph Hellwig } 199592dc6895SChristoph Hellwig 199692dc6895SChristoph Hellwig return -ENOMEM; 199792dc6895SChristoph Hellwig } 199892dc6895SChristoph Hellwig 19999620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 200087ad72a5SChristoph Hellwig { 200187ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 200287ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 200387ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 200487ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20056fbcde66SMinwoo Im int ret; 200687ad72a5SChristoph Hellwig 200787ad72a5SChristoph Hellwig preferred = min(preferred, max); 200887ad72a5SChristoph Hellwig if (min > max) { 200987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 201087ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 201187ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 201287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20139620cfbaSChristoph Hellwig return 0; 201487ad72a5SChristoph Hellwig } 201587ad72a5SChristoph Hellwig 201687ad72a5SChristoph Hellwig /* 201787ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 201887ad72a5SChristoph Hellwig */ 201987ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 202087ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 202187ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 202287ad72a5SChristoph Hellwig else 202387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 202487ad72a5SChristoph Hellwig } 202587ad72a5SChristoph Hellwig 202687ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 202792dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 202892dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 202992dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20309620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 203187ad72a5SChristoph Hellwig } 203287ad72a5SChristoph Hellwig 203392dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 203492dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 203592dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 203692dc6895SChristoph Hellwig } 203792dc6895SChristoph Hellwig 20389620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20399620cfbaSChristoph Hellwig if (ret) 204087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20419620cfbaSChristoph Hellwig return ret; 204257dacad5SJay Sternberg } 204357dacad5SJay Sternberg 2044c45b1fa2SMing Lei /* irq_queues covers admin queue */ 20456451fe73SJens Axboe static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues) 20463b6592f7SJens Axboe { 20473b6592f7SJens Axboe unsigned int this_w_queues = write_queues; 20483b6592f7SJens Axboe 2049c45b1fa2SMing Lei WARN_ON(!irq_queues); 2050c45b1fa2SMing Lei 20513b6592f7SJens Axboe /* 2052c45b1fa2SMing Lei * Setup read/write queue split, assign admin queue one independent 2053c45b1fa2SMing Lei * irq vector if irq_queues is > 1. 20543b6592f7SJens Axboe */ 2055c45b1fa2SMing Lei if (irq_queues <= 2) { 2056e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2057e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 20583b6592f7SJens Axboe return; 20593b6592f7SJens Axboe } 20603b6592f7SJens Axboe 20613b6592f7SJens Axboe /* 20623b6592f7SJens Axboe * If 'write_queues' is set, ensure it leaves room for at least 2063c45b1fa2SMing Lei * one read queue and one admin queue 20643b6592f7SJens Axboe */ 20656451fe73SJens Axboe if (this_w_queues >= irq_queues) 2066c45b1fa2SMing Lei this_w_queues = irq_queues - 2; 20673b6592f7SJens Axboe 20683b6592f7SJens Axboe /* 20693b6592f7SJens Axboe * If 'write_queues' is set to zero, reads and writes will share 20703b6592f7SJens Axboe * a queue set. 20713b6592f7SJens Axboe */ 20723b6592f7SJens Axboe if (!this_w_queues) { 2073c45b1fa2SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues - 1; 2074e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 20753b6592f7SJens Axboe } else { 2076e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues; 2077c45b1fa2SMing Lei dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues - 1; 20783b6592f7SJens Axboe } 20793b6592f7SJens Axboe } 20803b6592f7SJens Axboe 20816451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20823b6592f7SJens Axboe { 20833b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20843b6592f7SJens Axboe int irq_sets[2]; 20853b6592f7SJens Axboe struct irq_affinity affd = { 20863b6592f7SJens Axboe .pre_vectors = 1, 20873b6592f7SJens Axboe .nr_sets = ARRAY_SIZE(irq_sets), 20883b6592f7SJens Axboe .sets = irq_sets, 20893b6592f7SJens Axboe }; 209030e06628SJens Axboe int result = 0; 20916451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20926451fe73SJens Axboe 20936451fe73SJens Axboe /* 20946451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20956451fe73SJens Axboe * queue left over for non-polled IO. 20966451fe73SJens Axboe */ 20976451fe73SJens Axboe this_p_queues = poll_queues; 20986451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20996451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 21006451fe73SJens Axboe irq_queues = 1; 21016451fe73SJens Axboe } else { 2102c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 21036451fe73SJens Axboe } 21046451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 21053b6592f7SJens Axboe 21063b6592f7SJens Axboe /* 21073b6592f7SJens Axboe * For irq sets, we have to ask for minvec == maxvec. This passes 21083b6592f7SJens Axboe * any reduction back to us, so we can adjust our queue counts and 21093b6592f7SJens Axboe * IRQ vector needs. 21103b6592f7SJens Axboe */ 21113b6592f7SJens Axboe do { 21126451fe73SJens Axboe nvme_calc_io_queues(dev, irq_queues); 2113e20ba6e1SChristoph Hellwig irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT]; 2114e20ba6e1SChristoph Hellwig irq_sets[1] = dev->io_queues[HCTX_TYPE_READ]; 21153b6592f7SJens Axboe if (!irq_sets[1]) 21163b6592f7SJens Axboe affd.nr_sets = 1; 21173b6592f7SJens Axboe 21183b6592f7SJens Axboe /* 2119db29eb05SJens Axboe * If we got a failure and we're down to asking for just 2120db29eb05SJens Axboe * 1 + 1 queues, just ask for a single vector. We'll share 2121db29eb05SJens Axboe * that between the single IO queue and the admin queue. 2122c45b1fa2SMing Lei * Otherwise, we assign one independent vector to admin queue. 21233b6592f7SJens Axboe */ 2124c45b1fa2SMing Lei if (irq_queues > 1) 21256451fe73SJens Axboe irq_queues = irq_sets[0] + irq_sets[1] + 1; 21263b6592f7SJens Axboe 21276451fe73SJens Axboe result = pci_alloc_irq_vectors_affinity(pdev, irq_queues, 21286451fe73SJens Axboe irq_queues, 21293b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21303b6592f7SJens Axboe 21313b6592f7SJens Axboe /* 2132db29eb05SJens Axboe * Need to reduce our vec counts. If we get ENOSPC, the 2133db29eb05SJens Axboe * platform should support mulitple vecs, we just need 2134db29eb05SJens Axboe * to decrease our ask. If we get EINVAL, the platform 2135db29eb05SJens Axboe * likely does not. Back down to ask for just one vector. 21363b6592f7SJens Axboe */ 21373b6592f7SJens Axboe if (result == -ENOSPC) { 21386451fe73SJens Axboe irq_queues--; 21396451fe73SJens Axboe if (!irq_queues) 21403b6592f7SJens Axboe return result; 21413b6592f7SJens Axboe continue; 2142db29eb05SJens Axboe } else if (result == -EINVAL) { 21436451fe73SJens Axboe irq_queues = 1; 2144db29eb05SJens Axboe continue; 21453b6592f7SJens Axboe } else if (result <= 0) 21463b6592f7SJens Axboe return -EIO; 21473b6592f7SJens Axboe break; 21483b6592f7SJens Axboe } while (1); 21493b6592f7SJens Axboe 21503b6592f7SJens Axboe return result; 21513b6592f7SJens Axboe } 21523b6592f7SJens Axboe 21538fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 21548fae268bSKeith Busch { 21558fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 21568fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 21578fae268bSKeith Busch } 21588fae268bSKeith Busch 215957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 216057dacad5SJay Sternberg { 2161147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 216257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 216397f6ef64SXu Yu int result, nr_io_queues; 216497f6ef64SXu Yu unsigned long size; 216557dacad5SJay Sternberg 21663b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21679a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21689a0be7abSChristoph Hellwig if (result < 0) 216957dacad5SJay Sternberg return result; 21709a0be7abSChristoph Hellwig 2171f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2172a5229050SKeith Busch return 0; 217357dacad5SJay Sternberg 21744e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21754e224106SChristoph Hellwig 21760f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 217757dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 217857dacad5SJay Sternberg sizeof(struct nvme_command)); 217957dacad5SJay Sternberg if (result > 0) 218057dacad5SJay Sternberg dev->q_depth = result; 218157dacad5SJay Sternberg else 21820f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 218357dacad5SJay Sternberg } 218457dacad5SJay Sternberg 218557dacad5SJay Sternberg do { 218697f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 218797f6ef64SXu Yu result = nvme_remap_bar(dev, size); 218897f6ef64SXu Yu if (!result) 218957dacad5SJay Sternberg break; 219057dacad5SJay Sternberg if (!--nr_io_queues) 219157dacad5SJay Sternberg return -ENOMEM; 219257dacad5SJay Sternberg } while (1); 219357dacad5SJay Sternberg adminq->q_db = dev->dbs; 219457dacad5SJay Sternberg 21958fae268bSKeith Busch retry: 219657dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21970ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 219857dacad5SJay Sternberg 219957dacad5SJay Sternberg /* 220057dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 220157dacad5SJay Sternberg * setting up the full range we need. 220257dacad5SJay Sternberg */ 2203dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 22043b6592f7SJens Axboe 22053b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 220622b55601SKeith Busch if (result <= 0) 2207dca51e78SChristoph Hellwig return -EIO; 22083b6592f7SJens Axboe 220922b55601SKeith Busch dev->num_vecs = result; 22104b04cc6aSJens Axboe result = max(result - 1, 1); 2211e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 221257dacad5SJay Sternberg 221357dacad5SJay Sternberg /* 221457dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 221557dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 221657dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 221757dacad5SJay Sternberg * number of interrupts. 221857dacad5SJay Sternberg */ 2219dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 222057dacad5SJay Sternberg if (result) { 222157dacad5SJay Sternberg adminq->cq_vector = -1; 2222d4875622SKeith Busch return result; 222357dacad5SJay Sternberg } 22244e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 22258fae268bSKeith Busch 22268fae268bSKeith Busch result = nvme_create_io_queues(dev); 22278fae268bSKeith Busch if (result || dev->online_queues < 2) 22288fae268bSKeith Busch return result; 22298fae268bSKeith Busch 22308fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 22318fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 22328fae268bSKeith Busch nvme_disable_io_queues(dev); 22338fae268bSKeith Busch nvme_suspend_io_queues(dev); 22348fae268bSKeith Busch goto retry; 22358fae268bSKeith Busch } 22368fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 22378fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 22388fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 22398fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 22408fae268bSKeith Busch return 0; 224157dacad5SJay Sternberg } 224257dacad5SJay Sternberg 22432a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2244db3cbfffSKeith Busch { 2245db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2246db3cbfffSKeith Busch 2247db3cbfffSKeith Busch blk_mq_free_request(req); 2248d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2249db3cbfffSKeith Busch } 2250db3cbfffSKeith Busch 22512a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2252db3cbfffSKeith Busch { 2253db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2254db3cbfffSKeith Busch 2255d1ed6aa1SChristoph Hellwig if (error) 2256d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2257db3cbfffSKeith Busch 2258db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2259db3cbfffSKeith Busch } 2260db3cbfffSKeith Busch 2261db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2262db3cbfffSKeith Busch { 2263db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2264db3cbfffSKeith Busch struct request *req; 2265db3cbfffSKeith Busch struct nvme_command cmd; 2266db3cbfffSKeith Busch 2267db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2268db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2269db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2270db3cbfffSKeith Busch 2271eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2272db3cbfffSKeith Busch if (IS_ERR(req)) 2273db3cbfffSKeith Busch return PTR_ERR(req); 2274db3cbfffSKeith Busch 2275db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2276db3cbfffSKeith Busch req->end_io_data = nvmeq; 2277db3cbfffSKeith Busch 2278d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2279db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2280db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2281db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2282db3cbfffSKeith Busch return 0; 2283db3cbfffSKeith Busch } 2284db3cbfffSKeith Busch 22858fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2286db3cbfffSKeith Busch { 22875271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2288db3cbfffSKeith Busch unsigned long timeout; 2289db3cbfffSKeith Busch 2290db3cbfffSKeith Busch retry: 2291db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22925271edd4SChristoph Hellwig while (nr_queues > 0) { 22935271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2294db3cbfffSKeith Busch break; 22955271edd4SChristoph Hellwig nr_queues--; 22965271edd4SChristoph Hellwig sent++; 22975271edd4SChristoph Hellwig } 2298d1ed6aa1SChristoph Hellwig while (sent) { 2299d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2300d1ed6aa1SChristoph Hellwig 2301d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 23025271edd4SChristoph Hellwig timeout); 2303db3cbfffSKeith Busch if (timeout == 0) 23045271edd4SChristoph Hellwig return false; 2305d1ed6aa1SChristoph Hellwig 2306d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2307d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2308d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2309d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2310d1ed6aa1SChristoph Hellwig 2311d1ed6aa1SChristoph Hellwig sent--; 23125271edd4SChristoph Hellwig if (nr_queues) 2313db3cbfffSKeith Busch goto retry; 2314db3cbfffSKeith Busch } 23155271edd4SChristoph Hellwig return true; 2316db3cbfffSKeith Busch } 2317db3cbfffSKeith Busch 231857dacad5SJay Sternberg /* 23192b1b7e78SJianchao Wang * return error value only when tagset allocation failed 232057dacad5SJay Sternberg */ 232157dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 232257dacad5SJay Sternberg { 23232b1b7e78SJianchao Wang int ret; 23242b1b7e78SJianchao Wang 23255bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2326c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 232757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2328ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2329ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2330ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 233157dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 233257dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 233357dacad5SJay Sternberg dev->tagset.queue_depth = 233457dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2335a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2336a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2337a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2338a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2339a7a7cbe3SChaitanya Kulkarni } 234057dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 234157dacad5SJay Sternberg dev->tagset.driver_data = dev; 234257dacad5SJay Sternberg 23432b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23442b1b7e78SJianchao Wang if (ret) { 23452b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23462b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23472b1b7e78SJianchao Wang return ret; 23482b1b7e78SJianchao Wang } 23495bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2350f9f38e33SHelen Koike 2351f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2352949928c1SKeith Busch } else { 2353949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2354949928c1SKeith Busch 2355949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2356949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 235757dacad5SJay Sternberg } 2358949928c1SKeith Busch 235957dacad5SJay Sternberg return 0; 236057dacad5SJay Sternberg } 236157dacad5SJay Sternberg 2362b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 236357dacad5SJay Sternberg { 2364b00a726aSKeith Busch int result = -ENOMEM; 236557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 236657dacad5SJay Sternberg 236757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 236857dacad5SJay Sternberg return result; 236957dacad5SJay Sternberg 237057dacad5SJay Sternberg pci_set_master(pdev); 237157dacad5SJay Sternberg 237257dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 237357dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 237457dacad5SJay Sternberg goto disable; 237557dacad5SJay Sternberg 23767a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 237757dacad5SJay Sternberg result = -ENODEV; 2378b00a726aSKeith Busch goto disable; 237957dacad5SJay Sternberg } 238057dacad5SJay Sternberg 238157dacad5SJay Sternberg /* 2382a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2383a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2384a5229050SKeith Busch * adjust this later. 238557dacad5SJay Sternberg */ 2386dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2387dca51e78SChristoph Hellwig if (result < 0) 2388dca51e78SChristoph Hellwig return result; 238957dacad5SJay Sternberg 239020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23917a67cbeaSChristoph Hellwig 239220d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2393b27c1e68Sweiping zhang io_queue_depth); 239420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23957a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23961f390c1fSStephan Günther 23971f390c1fSStephan Günther /* 23981f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23991f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 24001f390c1fSStephan Günther */ 24011f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 24021f390c1fSStephan Günther dev->q_depth = 2; 24039bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 24049bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 24051f390c1fSStephan Günther dev->q_depth); 2406d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2407d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 240820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2409d554b5e1SMartin K. Petersen dev->q_depth = 64; 2410d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2411d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 24121f390c1fSStephan Günther } 24131f390c1fSStephan Günther 2414f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2415202021c1SStephen Bates 2416a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2417a0a3408eSKeith Busch pci_save_state(pdev); 241857dacad5SJay Sternberg return 0; 241957dacad5SJay Sternberg 242057dacad5SJay Sternberg disable: 242157dacad5SJay Sternberg pci_disable_device(pdev); 242257dacad5SJay Sternberg return result; 242357dacad5SJay Sternberg } 242457dacad5SJay Sternberg 242557dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 242657dacad5SJay Sternberg { 2427b00a726aSKeith Busch if (dev->bar) 2428b00a726aSKeith Busch iounmap(dev->bar); 2429a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2430b00a726aSKeith Busch } 2431b00a726aSKeith Busch 2432b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2433b00a726aSKeith Busch { 243457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 243557dacad5SJay Sternberg 2436dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 243757dacad5SJay Sternberg 2438a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2439a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 244057dacad5SJay Sternberg pci_disable_device(pdev); 244157dacad5SJay Sternberg } 2442a0a3408eSKeith Busch } 244357dacad5SJay Sternberg 2444a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 244557dacad5SJay Sternberg { 2446302ad8ccSKeith Busch bool dead = true; 2447302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 244857dacad5SJay Sternberg 244977bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2450302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2451302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2452302ad8ccSKeith Busch 2453ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2454ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2455302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2456302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2457302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 245857dacad5SJay Sternberg } 2459c21377f8SGabriel Krisman Bertazi 2460302ad8ccSKeith Busch /* 2461302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2462302ad8ccSKeith Busch * doing a safe shutdown. 2463302ad8ccSKeith Busch */ 246487ad72a5SChristoph Hellwig if (!dead) { 246587ad72a5SChristoph Hellwig if (shutdown) 2466302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24679a915a5bSJianchao Wang } 246887ad72a5SChristoph Hellwig 24699a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24709a915a5bSJianchao Wang 247164ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24728fae268bSKeith Busch nvme_disable_io_queues(dev); 2473a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 247457dacad5SJay Sternberg } 24758fae268bSKeith Busch nvme_suspend_io_queues(dev); 24768fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2477b00a726aSKeith Busch nvme_pci_disable(dev); 247857dacad5SJay Sternberg 2479e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2480e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2481302ad8ccSKeith Busch 2482302ad8ccSKeith Busch /* 2483302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2484302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2485302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2486302ad8ccSKeith Busch */ 2487302ad8ccSKeith Busch if (shutdown) 2488302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 248977bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 249057dacad5SJay Sternberg } 249157dacad5SJay Sternberg 249257dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 249357dacad5SJay Sternberg { 249457dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 249557dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 249657dacad5SJay Sternberg if (!dev->prp_page_pool) 249757dacad5SJay Sternberg return -ENOMEM; 249857dacad5SJay Sternberg 249957dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 250057dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 250157dacad5SJay Sternberg 256, 256, 0); 250257dacad5SJay Sternberg if (!dev->prp_small_pool) { 250357dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 250457dacad5SJay Sternberg return -ENOMEM; 250557dacad5SJay Sternberg } 250657dacad5SJay Sternberg return 0; 250757dacad5SJay Sternberg } 250857dacad5SJay Sternberg 250957dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 251057dacad5SJay Sternberg { 251157dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 251257dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 251357dacad5SJay Sternberg } 251457dacad5SJay Sternberg 25151673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 251657dacad5SJay Sternberg { 25171673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 251857dacad5SJay Sternberg 2519f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 252057dacad5SJay Sternberg put_device(dev->dev); 252157dacad5SJay Sternberg if (dev->tagset.tags) 252257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 25231c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 25241c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 252557dacad5SJay Sternberg kfree(dev->queues); 2526e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2527943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 252857dacad5SJay Sternberg kfree(dev); 252957dacad5SJay Sternberg } 253057dacad5SJay Sternberg 2531f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2532f58944e2SKeith Busch { 2533237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2534f58944e2SKeith Busch 2535d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 253669d9a99cSKeith Busch nvme_dev_disable(dev, false); 25379f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 253803e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2539f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2540f58944e2SKeith Busch } 2541f58944e2SKeith Busch 2542fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 254357dacad5SJay Sternberg { 2544d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2545d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2546a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2547f58944e2SKeith Busch int result = -ENODEV; 25482b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 254957dacad5SJay Sternberg 255082b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2551fd634f41SChristoph Hellwig goto out; 2552fd634f41SChristoph Hellwig 2553fd634f41SChristoph Hellwig /* 2554fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2555fd634f41SChristoph Hellwig * moving on. 2556fd634f41SChristoph Hellwig */ 2557b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2558a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2559fd634f41SChristoph Hellwig 2560ad70062cSJianchao Wang /* 2561ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2562ad70062cSJianchao Wang * initializing procedure here. 2563ad70062cSJianchao Wang */ 2564ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2565ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2566ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2567ad70062cSJianchao Wang goto out; 2568ad70062cSJianchao Wang } 2569ad70062cSJianchao Wang 2570b00a726aSKeith Busch result = nvme_pci_enable(dev); 257157dacad5SJay Sternberg if (result) 257257dacad5SJay Sternberg goto out; 257357dacad5SJay Sternberg 257401ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 257557dacad5SJay Sternberg if (result) 2576f58944e2SKeith Busch goto out; 257757dacad5SJay Sternberg 257857dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 257957dacad5SJay Sternberg if (result) 2580f58944e2SKeith Busch goto out; 258157dacad5SJay Sternberg 2582943e942eSJens Axboe /* 2583943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2584943e942eSJens Axboe * over a single page. 2585943e942eSJens Axboe */ 2586943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2587943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2588943e942eSJens Axboe 2589ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2590ce4541f4SChristoph Hellwig if (result) 2591f58944e2SKeith Busch goto out; 2592ce4541f4SChristoph Hellwig 2593e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2594e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25954f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25964f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2597e286bcfcSScott Bauer else if (was_suspend) 25984f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2599e286bcfcSScott Bauer } else { 2600e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2601e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2602e286bcfcSScott Bauer } 2603a98e58e5SScott Bauer 2604f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2605f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2606f9f38e33SHelen Koike if (result) 2607f9f38e33SHelen Koike dev_warn(dev->dev, 2608f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2609f9f38e33SHelen Koike } 2610f9f38e33SHelen Koike 26119620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 26129620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26139620cfbaSChristoph Hellwig if (result < 0) 26149620cfbaSChristoph Hellwig goto out; 26159620cfbaSChristoph Hellwig } 261687ad72a5SChristoph Hellwig 261757dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 261857dacad5SJay Sternberg if (result) 2619f58944e2SKeith Busch goto out; 262057dacad5SJay Sternberg 262121f033f7SKeith Busch /* 262257dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 262357dacad5SJay Sternberg * any working I/O queue. 262457dacad5SJay Sternberg */ 262557dacad5SJay Sternberg if (dev->online_queues < 2) { 26261b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26273b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26285bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 26292b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 263057dacad5SJay Sternberg } else { 263125646264SKeith Busch nvme_start_queues(&dev->ctrl); 2632302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26332b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 26342b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 26352b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2636302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 263757dacad5SJay Sternberg } 263857dacad5SJay Sternberg 26392b1b7e78SJianchao Wang /* 26402b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26412b1b7e78SJianchao Wang * recovery. 26422b1b7e78SJianchao Wang */ 26432b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 26442b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26452b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2646bb8d261eSChristoph Hellwig goto out; 2647bb8d261eSChristoph Hellwig } 264892911a55SChristoph Hellwig 2649d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 265057dacad5SJay Sternberg return; 265157dacad5SJay Sternberg 265257dacad5SJay Sternberg out: 2653f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 265457dacad5SJay Sternberg } 265557dacad5SJay Sternberg 26565c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 265757dacad5SJay Sternberg { 26585c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 265957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266057dacad5SJay Sternberg 266157dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2662921920abSKeith Busch device_release_driver(&pdev->dev); 26631673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 266457dacad5SJay Sternberg } 266557dacad5SJay Sternberg 26661c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 266757dacad5SJay Sternberg { 26681c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26691c63dc66SChristoph Hellwig return 0; 267057dacad5SJay Sternberg } 26711c63dc66SChristoph Hellwig 26725fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26735fd4ce1bSChristoph Hellwig { 26745fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26755fd4ce1bSChristoph Hellwig return 0; 26765fd4ce1bSChristoph Hellwig } 26775fd4ce1bSChristoph Hellwig 26787fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26797fd8930fSChristoph Hellwig { 26807fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26817fd8930fSChristoph Hellwig return 0; 26827fd8930fSChristoph Hellwig } 26837fd8930fSChristoph Hellwig 268497c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 268597c12223SKeith Busch { 268697c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 268797c12223SKeith Busch 268897c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 268997c12223SKeith Busch } 269097c12223SKeith Busch 26911c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26921a353d85SMing Lin .name = "pcie", 2693e439bb12SSagi Grimberg .module = THIS_MODULE, 2694e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2695e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26961c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26975fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26987fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26991673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2700f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 270197c12223SKeith Busch .get_address = nvme_pci_get_address, 27021c63dc66SChristoph Hellwig }; 270357dacad5SJay Sternberg 2704b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2705b00a726aSKeith Busch { 2706b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2707b00a726aSKeith Busch 2708a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2709b00a726aSKeith Busch return -ENODEV; 2710b00a726aSKeith Busch 271197f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2712b00a726aSKeith Busch goto release; 2713b00a726aSKeith Busch 2714b00a726aSKeith Busch return 0; 2715b00a726aSKeith Busch release: 2716a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2717b00a726aSKeith Busch return -ENODEV; 2718b00a726aSKeith Busch } 2719b00a726aSKeith Busch 27208427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2721ff5350a8SAndy Lutomirski { 2722ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2723ff5350a8SAndy Lutomirski /* 2724ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2725ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2726ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2727ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2728ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2729ff5350a8SAndy Lutomirski * laptops. 2730ff5350a8SAndy Lutomirski */ 2731ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2732ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2733ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2734ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27358427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27368427bbc2SKai-Heng Feng /* 27378427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2738467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2739467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2740467c77d4SJarosław Janik * ASUS PRIME Z370-A 27418427bbc2SKai-Heng Feng */ 27428427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2743467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2744467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27458427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2746ff5350a8SAndy Lutomirski } 2747ff5350a8SAndy Lutomirski 2748ff5350a8SAndy Lutomirski return 0; 2749ff5350a8SAndy Lutomirski } 2750ff5350a8SAndy Lutomirski 275118119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 275218119775SKeith Busch { 275318119775SKeith Busch struct nvme_dev *dev = data; 275480f513b5SKeith Busch 275518119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 275618119775SKeith Busch flush_work(&dev->ctrl.scan_work); 275780f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 275818119775SKeith Busch } 275918119775SKeith Busch 276057dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 276157dacad5SJay Sternberg { 276257dacad5SJay Sternberg int node, result = -ENOMEM; 276357dacad5SJay Sternberg struct nvme_dev *dev; 2764ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2765943e942eSJens Axboe size_t alloc_size; 276657dacad5SJay Sternberg 276757dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 276857dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27692fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 277057dacad5SJay Sternberg 277157dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 277257dacad5SJay Sternberg if (!dev) 277357dacad5SJay Sternberg return -ENOMEM; 2774147b27e4SSagi Grimberg 27753b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27763b6592f7SJens Axboe GFP_KERNEL, node); 277757dacad5SJay Sternberg if (!dev->queues) 277857dacad5SJay Sternberg goto free; 277957dacad5SJay Sternberg 278057dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 278157dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 278257dacad5SJay Sternberg 2783b00a726aSKeith Busch result = nvme_dev_map(dev); 2784b00a726aSKeith Busch if (result) 2785b00c9b7aSChristophe JAILLET goto put_pci; 2786b00a726aSKeith Busch 2787d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27885c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 278977bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2790f3ca80fcSChristoph Hellwig 2791f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2792f3ca80fcSChristoph Hellwig if (result) 2793b00c9b7aSChristophe JAILLET goto unmap; 2794f3ca80fcSChristoph Hellwig 27958427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2796ff5350a8SAndy Lutomirski 2797943e942eSJens Axboe /* 2798943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2799943e942eSJens Axboe * command we support. 2800943e942eSJens Axboe */ 2801943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2802943e942eSJens Axboe NVME_MAX_SEGS, true); 2803943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2804943e942eSJens Axboe 2805943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2806943e942eSJens Axboe mempool_kfree, 2807943e942eSJens Axboe (void *) alloc_size, 2808943e942eSJens Axboe GFP_KERNEL, node); 2809943e942eSJens Axboe if (!dev->iod_mempool) { 2810943e942eSJens Axboe result = -ENOMEM; 2811943e942eSJens Axboe goto release_pools; 2812943e942eSJens Axboe } 2813943e942eSJens Axboe 2814b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2815b6e44b4cSKeith Busch quirks); 2816b6e44b4cSKeith Busch if (result) 2817b6e44b4cSKeith Busch goto release_mempool; 2818b6e44b4cSKeith Busch 28191b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 28201b3c47c1SSagi Grimberg 282180f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 282218119775SKeith Busch async_schedule(nvme_async_probe, dev); 28234caff8fcSSagi Grimberg 282457dacad5SJay Sternberg return 0; 282557dacad5SJay Sternberg 2826b6e44b4cSKeith Busch release_mempool: 2827b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 282857dacad5SJay Sternberg release_pools: 282957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2830b00c9b7aSChristophe JAILLET unmap: 2831b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 283257dacad5SJay Sternberg put_pci: 283357dacad5SJay Sternberg put_device(dev->dev); 283457dacad5SJay Sternberg free: 283557dacad5SJay Sternberg kfree(dev->queues); 283657dacad5SJay Sternberg kfree(dev); 283757dacad5SJay Sternberg return result; 283857dacad5SJay Sternberg } 283957dacad5SJay Sternberg 2840775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 284157dacad5SJay Sternberg { 284257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2843a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2844775755edSChristoph Hellwig } 284557dacad5SJay Sternberg 2846775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2847775755edSChristoph Hellwig { 2848f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 284979c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 285057dacad5SJay Sternberg } 285157dacad5SJay Sternberg 285257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 285357dacad5SJay Sternberg { 285457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2855a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 285657dacad5SJay Sternberg } 285757dacad5SJay Sternberg 2858f58944e2SKeith Busch /* 2859f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2860f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2861f58944e2SKeith Busch * order to proceed. 2862f58944e2SKeith Busch */ 286357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 286457dacad5SJay Sternberg { 286557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 286657dacad5SJay Sternberg 2867bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 286857dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28690ff9d4e1SKeith Busch 28706db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28710ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28721d39e692SKeith Busch nvme_dev_disable(dev, true); 2873cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28746db28edaSKeith Busch } 28750ff9d4e1SKeith Busch 2876d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2877d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2878d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2879a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28809fe5c59fSKeith Busch nvme_release_cmb(dev); 288187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 288257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 288357dacad5SJay Sternberg nvme_free_queues(dev, 0); 2884d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 288557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2886b00a726aSKeith Busch nvme_dev_unmap(dev); 28871673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 288857dacad5SJay Sternberg } 288957dacad5SJay Sternberg 289057dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 289157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 289257dacad5SJay Sternberg { 289357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 289457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 289557dacad5SJay Sternberg 2896a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 289757dacad5SJay Sternberg return 0; 289857dacad5SJay Sternberg } 289957dacad5SJay Sternberg 290057dacad5SJay Sternberg static int nvme_resume(struct device *dev) 290157dacad5SJay Sternberg { 290257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 290357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 290457dacad5SJay Sternberg 2905d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 290657dacad5SJay Sternberg return 0; 290757dacad5SJay Sternberg } 290857dacad5SJay Sternberg #endif 290957dacad5SJay Sternberg 291057dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 291157dacad5SJay Sternberg 2912a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2913a0a3408eSKeith Busch pci_channel_state_t state) 2914a0a3408eSKeith Busch { 2915a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2916a0a3408eSKeith Busch 2917a0a3408eSKeith Busch /* 2918a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2919a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2920a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2921a0a3408eSKeith Busch */ 2922a0a3408eSKeith Busch switch (state) { 2923a0a3408eSKeith Busch case pci_channel_io_normal: 2924a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2925a0a3408eSKeith Busch case pci_channel_io_frozen: 2926d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2927d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2928a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2929a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2930a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2931d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2932d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2933a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2934a0a3408eSKeith Busch } 2935a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2936a0a3408eSKeith Busch } 2937a0a3408eSKeith Busch 2938a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2939a0a3408eSKeith Busch { 2940a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2941a0a3408eSKeith Busch 29421b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2943a0a3408eSKeith Busch pci_restore_state(pdev); 2944d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2945a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2946a0a3408eSKeith Busch } 2947a0a3408eSKeith Busch 2948a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2949a0a3408eSKeith Busch { 295072cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 295172cd4cc2SKeith Busch 295272cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2953a0a3408eSKeith Busch } 2954a0a3408eSKeith Busch 295557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 295657dacad5SJay Sternberg .error_detected = nvme_error_detected, 295757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 295857dacad5SJay Sternberg .resume = nvme_error_resume, 2959775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2960775755edSChristoph Hellwig .reset_done = nvme_reset_done, 296157dacad5SJay Sternberg }; 296257dacad5SJay Sternberg 296357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2964106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 296508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2966e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 296799466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 296899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2969e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 297099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 297199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2972e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2973f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2974f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2975f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 297650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29779abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29789abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 29796299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 29806299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2981540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2982540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 29830302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29840302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 298554adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 298654adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29878c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29888c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2989015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2990015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2991d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2992d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2993d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2994d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2995608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2996608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2997608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2998608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2999ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3000ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 300157dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 3002c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 3003124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 300457dacad5SJay Sternberg { 0, } 300557dacad5SJay Sternberg }; 300657dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 300757dacad5SJay Sternberg 300857dacad5SJay Sternberg static struct pci_driver nvme_driver = { 300957dacad5SJay Sternberg .name = "nvme", 301057dacad5SJay Sternberg .id_table = nvme_id_table, 301157dacad5SJay Sternberg .probe = nvme_probe, 301257dacad5SJay Sternberg .remove = nvme_remove, 301357dacad5SJay Sternberg .shutdown = nvme_shutdown, 301457dacad5SJay Sternberg .driver = { 301557dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 301657dacad5SJay Sternberg }, 301774d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 301857dacad5SJay Sternberg .err_handler = &nvme_err_handler, 301957dacad5SJay Sternberg }; 302057dacad5SJay Sternberg 302157dacad5SJay Sternberg static int __init nvme_init(void) 302257dacad5SJay Sternberg { 30239a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 302457dacad5SJay Sternberg } 302557dacad5SJay Sternberg 302657dacad5SJay Sternberg static void __exit nvme_exit(void) 302757dacad5SJay Sternberg { 302857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 302903e0f3a6SMing Lei flush_workqueue(nvme_wq); 303057dacad5SJay Sternberg _nvme_check_size(); 303157dacad5SJay Sternberg } 303257dacad5SJay Sternberg 303357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 303457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 303557dacad5SJay Sternberg MODULE_VERSION("1.0"); 303657dacad5SJay Sternberg module_init(nvme_init); 303757dacad5SJay Sternberg module_exit(nvme_exit); 3038