15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 13ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1457dacad5SJay Sternberg #include <linux/init.h> 1557dacad5SJay Sternberg #include <linux/interrupt.h> 1657dacad5SJay Sternberg #include <linux/io.h> 1799722c8aSChristophe JAILLET #include <linux/kstrtox.h> 18dc90f084SChristoph Hellwig #include <linux/memremap.h> 1957dacad5SJay Sternberg #include <linux/mm.h> 2057dacad5SJay Sternberg #include <linux/module.h> 2177bf25eaSKeith Busch #include <linux/mutex.h> 22d0877473SKeith Busch #include <linux/once.h> 2357dacad5SJay Sternberg #include <linux/pci.h> 24d916b1beSKeith Busch #include <linux/suspend.h> 2557dacad5SJay Sternberg #include <linux/t10-pi.h> 2657dacad5SJay Sternberg #include <linux/types.h> 279cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2820d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 29a98e58e5SScott Bauer #include <linux/sed-opal.h> 300f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3157dacad5SJay Sternberg 32604c01d5Syupeng #include "trace.h" 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 35c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 368a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 3884173423SKeith Busch #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 40943e942eSJens Axboe /* 41943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 42943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 43943e942eSJens Axboe */ 447846c1b5SKeith Busch #define NVME_MAX_KB_SZ 8192 457846c1b5SKeith Busch #define NVME_MAX_SEGS 128 467846c1b5SKeith Busch #define NVME_MAX_NR_ALLOCATIONS 5 47943e942eSJens Axboe 4857dacad5SJay Sternberg static int use_threaded_interrupts; 492e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 5057dacad5SJay Sternberg 5157dacad5SJay Sternberg static bool use_cmb_sqes = true; 5269f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5357dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5457dacad5SJay Sternberg 5587ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5687ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5787ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5887ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5957dacad5SJay Sternberg 60a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 61a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 62a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 63a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 64a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 65a7a7cbe3SChaitanya Kulkarni 6627453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6727453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 68b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 70b27c1e68Sweiping zhang .set = io_queue_depth_set, 7161f3b896SChaitanya Kulkarni .get = param_get_uint, 72b27c1e68Sweiping zhang }; 73b27c1e68Sweiping zhang 7461f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 75b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7627453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 77b27c1e68Sweiping zhang 789c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 799c9e76d5SWeiping Zhang { 809c9e76d5SWeiping Zhang unsigned int n; 819c9e76d5SWeiping Zhang int ret; 829c9e76d5SWeiping Zhang 839c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 849c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 859c9e76d5SWeiping Zhang return -EINVAL; 869c9e76d5SWeiping Zhang return param_set_uint(val, kp); 879c9e76d5SWeiping Zhang } 889c9e76d5SWeiping Zhang 899c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 909c9e76d5SWeiping Zhang .set = io_queue_count_set, 919c9e76d5SWeiping Zhang .get = param_get_uint, 929c9e76d5SWeiping Zhang }; 939c9e76d5SWeiping Zhang 943f68baf7SKeith Busch static unsigned int write_queues; 959c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 963b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 973b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 983b6592f7SJens Axboe "will share a queue set."); 993b6592f7SJens Axboe 1003f68baf7SKeith Busch static unsigned int poll_queues; 1019c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1024b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1034b04cc6aSJens Axboe 104df4f9bc4SDavid E. Box static bool noacpi; 105df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 106df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 107df4f9bc4SDavid E. Box 1081c63dc66SChristoph Hellwig struct nvme_dev; 1091c63dc66SChristoph Hellwig struct nvme_queue; 11057dacad5SJay Sternberg 111a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1127d879c90SChristoph Hellwig static void nvme_delete_io_queues(struct nvme_dev *dev); 113e917a849SKeith Busch static void nvme_update_attrs(struct nvme_dev *dev); 11457dacad5SJay Sternberg 11557dacad5SJay Sternberg /* 1161c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1171c63dc66SChristoph Hellwig */ 1181c63dc66SChristoph Hellwig struct nvme_dev { 119147b27e4SSagi Grimberg struct nvme_queue *queues; 1201c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1211c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1221c63dc66SChristoph Hellwig u32 __iomem *dbs; 1231c63dc66SChristoph Hellwig struct device *dev; 1241c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1251c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1261c63dc66SChristoph Hellwig unsigned online_queues; 1271c63dc66SChristoph Hellwig unsigned max_qid; 128e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12922b55601SKeith Busch unsigned int num_vecs; 1307442ddceSJohn Garry u32 q_depth; 131c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1321c63dc66SChristoph Hellwig u32 db_stride; 1331c63dc66SChristoph Hellwig void __iomem *bar; 13497f6ef64SXu Yu unsigned long bar_mapped_size; 13577bf25eaSKeith Busch struct mutex shutdown_lock; 1361c63dc66SChristoph Hellwig bool subsystem; 1371c63dc66SChristoph Hellwig u64 cmb_size; 1380f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1391c63dc66SChristoph Hellwig u32 cmbsz; 140202021c1SStephen Bates u32 cmbloc; 1411c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 142d916b1beSKeith Busch u32 last_ps; 143a5df5e79SKeith Busch bool hmb; 14487ad72a5SChristoph Hellwig 145943e942eSJens Axboe mempool_t *iod_mempool; 146943e942eSJens Axboe 14787ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 148b5f96cb7SKlaus Jensen __le32 *dbbuf_dbs; 149f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 150b5f96cb7SKlaus Jensen __le32 *dbbuf_eis; 151f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15287ad72a5SChristoph Hellwig 15387ad72a5SChristoph Hellwig /* host memory buffer support: */ 15487ad72a5SChristoph Hellwig u64 host_mem_size; 15587ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1564033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15887ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1592a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1612a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 16257dacad5SJay Sternberg }; 16357dacad5SJay Sternberg 164b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 165b27c1e68Sweiping zhang { 16627453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16727453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 168b27c1e68Sweiping zhang } 169b27c1e68Sweiping zhang 170f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171f9f38e33SHelen Koike { 172f9f38e33SHelen Koike return qid * 2 * stride; 173f9f38e33SHelen Koike } 174f9f38e33SHelen Koike 175f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176f9f38e33SHelen Koike { 177f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 178f9f38e33SHelen Koike } 179f9f38e33SHelen Koike 1801c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1811c63dc66SChristoph Hellwig { 1821c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1831c63dc66SChristoph Hellwig } 1841c63dc66SChristoph Hellwig 18557dacad5SJay Sternberg /* 18657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18757dacad5SJay Sternberg * commands and one for I/O commands). 18857dacad5SJay Sternberg */ 18957dacad5SJay Sternberg struct nvme_queue { 19057dacad5SJay Sternberg struct nvme_dev *dev; 1911ab0cd69SJens Axboe spinlock_t sq_lock; 192c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1933a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1943a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19574943d45SKeith Busch struct nvme_completion *cqes; 19657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19857dacad5SJay Sternberg u32 __iomem *q_db; 1997442ddceSJohn Garry u32 q_depth; 2007c349ddeSKeith Busch u16 cq_vector; 20157dacad5SJay Sternberg u16 sq_tail; 20238210800SKeith Busch u16 last_sq_tail; 20357dacad5SJay Sternberg u16 cq_head; 20457dacad5SJay Sternberg u16 qid; 20557dacad5SJay Sternberg u8 cq_phase; 206c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2074e224106SChristoph Hellwig unsigned long flags; 2084e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20963223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 210d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2117c349ddeSKeith Busch #define NVMEQ_POLLED 3 212b5f96cb7SKlaus Jensen __le32 *dbbuf_sq_db; 213b5f96cb7SKlaus Jensen __le32 *dbbuf_cq_db; 214b5f96cb7SKlaus Jensen __le32 *dbbuf_sq_ei; 215b5f96cb7SKlaus Jensen __le32 *dbbuf_cq_ei; 216d1ed6aa1SChristoph Hellwig struct completion delete_done; 21757dacad5SJay Sternberg }; 21857dacad5SJay Sternberg 2197846c1b5SKeith Busch union nvme_descriptor { 2207846c1b5SKeith Busch struct nvme_sgl_desc *sg_list; 2217846c1b5SKeith Busch __le64 *prp_list; 2227846c1b5SKeith Busch }; 2237846c1b5SKeith Busch 22457dacad5SJay Sternberg /* 2259b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2269b048119SChristoph Hellwig * 2279b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2289b048119SChristoph Hellwig * to the actual struct scatterlist. 22971bd150cSChristoph Hellwig */ 23071bd150cSChristoph Hellwig struct nvme_iod { 231d49187e9SChristoph Hellwig struct nvme_request req; 232af7fae85SKeith Busch struct nvme_command cmd; 23352da4f3fSKeith Busch bool aborted; 234c372cdd1SKeith Busch s8 nr_allocations; /* PRP list pool allocations. 0 means small 235c372cdd1SKeith Busch pool in use */ 236dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 237c4c22c52SKeith Busch dma_addr_t first_dma; 238783b94bdSChristoph Hellwig dma_addr_t meta_dma; 23991fb2b60SLogan Gunthorpe struct sg_table sgt; 2407846c1b5SKeith Busch union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS]; 24157dacad5SJay Sternberg }; 24257dacad5SJay Sternberg 2432a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2443b6592f7SJens Axboe { 2452a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 246f9f38e33SHelen Koike } 247f9f38e33SHelen Koike 24865a54646SChristoph Hellwig static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 249f9f38e33SHelen Koike { 2502a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 251f9f38e33SHelen Koike 25265a54646SChristoph Hellwig if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 25365a54646SChristoph Hellwig return; 25465a54646SChristoph Hellwig 25558847f12SKeith Busch if (dev->dbbuf_dbs) { 25658847f12SKeith Busch /* 25758847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25858847f12SKeith Busch * values from the previous instantiation. 25958847f12SKeith Busch */ 26058847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 26158847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 26265a54646SChristoph Hellwig return; 26358847f12SKeith Busch } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 266f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 267f9f38e33SHelen Koike GFP_KERNEL); 268f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 26965a54646SChristoph Hellwig goto fail; 270f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 271f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 272f9f38e33SHelen Koike GFP_KERNEL); 27365a54646SChristoph Hellwig if (!dev->dbbuf_eis) 27465a54646SChristoph Hellwig goto fail_free_dbbuf_dbs; 27565a54646SChristoph Hellwig return; 276f9f38e33SHelen Koike 27765a54646SChristoph Hellwig fail_free_dbbuf_dbs: 27865a54646SChristoph Hellwig dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 27965a54646SChristoph Hellwig dev->dbbuf_dbs_dma_addr); 28065a54646SChristoph Hellwig dev->dbbuf_dbs = NULL; 28165a54646SChristoph Hellwig fail: 28265a54646SChristoph Hellwig dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 283f9f38e33SHelen Koike } 284f9f38e33SHelen Koike 285f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 286f9f38e33SHelen Koike { 2872a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 288f9f38e33SHelen Koike 289f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 290f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 291f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 292f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike if (dev->dbbuf_eis) { 295f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 296f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 297f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike } 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 302f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 303f9f38e33SHelen Koike { 304f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 305f9f38e33SHelen Koike return; 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 308f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 309f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 310f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 311f9f38e33SHelen Koike } 312f9f38e33SHelen Koike 3130f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3140f0d2c87SMinwoo Im { 3150f0d2c87SMinwoo Im if (!nvmeq->qid) 3160f0d2c87SMinwoo Im return; 3170f0d2c87SMinwoo Im 3180f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3190f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3200f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3210f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3220f0d2c87SMinwoo Im } 3230f0d2c87SMinwoo Im 324f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 325f9f38e33SHelen Koike { 326f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3270f0d2c87SMinwoo Im unsigned int i; 328f9f38e33SHelen Koike 329f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 330f9f38e33SHelen Koike return; 331f9f38e33SHelen Koike 332f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 333f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 334f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 335f9f38e33SHelen Koike 336f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3379bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 338f9f38e33SHelen Koike /* Free memory and continue on */ 339f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3400f0d2c87SMinwoo Im 3410f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3420f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 343f9f38e33SHelen Koike } 344f9f38e33SHelen Koike } 345f9f38e33SHelen Koike 346f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 347f9f38e33SHelen Koike { 348f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 349f9f38e33SHelen Koike } 350f9f38e33SHelen Koike 351f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 352b5f96cb7SKlaus Jensen static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db, 353b5f96cb7SKlaus Jensen volatile __le32 *dbbuf_ei) 354f9f38e33SHelen Koike { 355f9f38e33SHelen Koike if (dbbuf_db) { 356b5f96cb7SKlaus Jensen u16 old_value, event_idx; 357f9f38e33SHelen Koike 358f9f38e33SHelen Koike /* 359f9f38e33SHelen Koike * Ensure that the queue is written before updating 360f9f38e33SHelen Koike * the doorbell in memory 361f9f38e33SHelen Koike */ 362f9f38e33SHelen Koike wmb(); 363f9f38e33SHelen Koike 364b5f96cb7SKlaus Jensen old_value = le32_to_cpu(*dbbuf_db); 365b5f96cb7SKlaus Jensen *dbbuf_db = cpu_to_le32(value); 366f9f38e33SHelen Koike 367f1ed3df2SMichal Wnukowski /* 368f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 369f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 370f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 371f1ed3df2SMichal Wnukowski * the doorbell. 372f1ed3df2SMichal Wnukowski */ 373f1ed3df2SMichal Wnukowski mb(); 374f1ed3df2SMichal Wnukowski 375b5f96cb7SKlaus Jensen event_idx = le32_to_cpu(*dbbuf_ei); 376b5f96cb7SKlaus Jensen if (!nvme_dbbuf_need_event(event_idx, value, old_value)) 377f9f38e33SHelen Koike return false; 378f9f38e33SHelen Koike } 379f9f38e33SHelen Koike 380f9f38e33SHelen Koike return true; 38157dacad5SJay Sternberg } 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg /* 38457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38657dacad5SJay Sternberg * the I/O. 38757dacad5SJay Sternberg */ 388b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 38957dacad5SJay Sternberg { 390c89a529eSKeith Busch unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; 391c89a529eSKeith Busch unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); 39284173423SKeith Busch return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); 39357dacad5SJay Sternberg } 39457dacad5SJay Sternberg 39557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39657dacad5SJay Sternberg unsigned int hctx_idx) 39757dacad5SJay Sternberg { 3980da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(data); 399147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40057dacad5SJay Sternberg 40157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40357dacad5SJay Sternberg 40457dacad5SJay Sternberg hctx->driver_data = nvmeq; 40557dacad5SJay Sternberg return 0; 40657dacad5SJay Sternberg } 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40957dacad5SJay Sternberg unsigned int hctx_idx) 41057dacad5SJay Sternberg { 4110da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(data); 412147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41557dacad5SJay Sternberg hctx->driver_data = nvmeq; 41657dacad5SJay Sternberg return 0; 41757dacad5SJay Sternberg } 41857dacad5SJay Sternberg 419e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 420e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 421e559398fSChristoph Hellwig unsigned int numa_node) 42257dacad5SJay Sternberg { 423f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 42459e29ce6SSagi Grimberg 4254a4d9bc0SIrvin Cote nvme_req(req)->ctrl = set->driver_data; 426f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 42757dacad5SJay Sternberg return 0; 42857dacad5SJay Sternberg } 42957dacad5SJay Sternberg 4303b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4313b6592f7SJens Axboe { 4323b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4333b6592f7SJens Axboe if (dev->num_vecs > 1) 4343b6592f7SJens Axboe return 1; 4353b6592f7SJens Axboe 4363b6592f7SJens Axboe return 0; 4373b6592f7SJens Axboe } 4383b6592f7SJens Axboe 439a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 440dca51e78SChristoph Hellwig { 4410da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(set->driver_data); 4423b6592f7SJens Axboe int i, qoff, offset; 443dca51e78SChristoph Hellwig 4443b6592f7SJens Axboe offset = queue_irq_offset(dev); 4453b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4463b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4473b6592f7SJens Axboe 4483b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4493b6592f7SJens Axboe if (!map->nr_queues) { 450e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4517e849dd9SChristoph Hellwig continue; 4523b6592f7SJens Axboe } 4533b6592f7SJens Axboe 4544b04cc6aSJens Axboe /* 4554b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4564b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4574b04cc6aSJens Axboe */ 4583b6592f7SJens Axboe map->queue_offset = qoff; 459cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4603b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4614b04cc6aSJens Axboe else 4624b04cc6aSJens Axboe blk_mq_map_queues(map); 4633b6592f7SJens Axboe qoff += map->nr_queues; 4643b6592f7SJens Axboe offset += map->nr_queues; 4653b6592f7SJens Axboe } 466dca51e78SChristoph Hellwig } 467dca51e78SChristoph Hellwig 46838210800SKeith Busch /* 46938210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47038210800SKeith Busch */ 47138210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47204f3eafdSJens Axboe { 47338210800SKeith Busch if (!write_sq) { 47438210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47538210800SKeith Busch 47638210800SKeith Busch if (next_tail == nvmeq->q_depth) 47738210800SKeith Busch next_tail = 0; 47838210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 47938210800SKeith Busch return; 48038210800SKeith Busch } 48138210800SKeith Busch 48204f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48304f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48404f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48538210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 48604f3eafdSJens Axboe } 48704f3eafdSJens Axboe 4883233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4893233b94cSJens Axboe struct nvme_command *cmd) 49057dacad5SJay Sternberg { 491c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 4923233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 49390ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49490ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49504f3eafdSJens Axboe } 49604f3eafdSJens Axboe 49704f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 49804f3eafdSJens Axboe { 49904f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50004f3eafdSJens Axboe 50104f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50238210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50338210800SKeith Busch nvme_write_sq_db(nvmeq, true); 50490ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50557dacad5SJay Sternberg } 50657dacad5SJay Sternberg 507ae582935SKeith Busch static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req, 508ae582935SKeith Busch int nseg) 509955b1b5aSMinwoo Im { 510a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 511955b1b5aSMinwoo Im unsigned int avg_seg_size; 512955b1b5aSMinwoo Im 51320469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 514955b1b5aSMinwoo Im 515253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 516955b1b5aSMinwoo Im return false; 517a53232cbSKeith Busch if (!nvmeq->qid) 518955b1b5aSMinwoo Im return false; 519955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 520955b1b5aSMinwoo Im return false; 521955b1b5aSMinwoo Im return true; 522955b1b5aSMinwoo Im } 523955b1b5aSMinwoo Im 5249275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 52557dacad5SJay Sternberg { 5266c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5279275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5289275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 52957dacad5SJay Sternberg int i; 53057dacad5SJay Sternberg 531c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5327846c1b5SKeith Busch __le64 *prp_list = iod->list[i].prp_list; 5339275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5349275c206SChristoph Hellwig 5359275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5369275c206SChristoph Hellwig dma_addr = next_dma_addr; 537dff824b2SChristoph Hellwig } 5389275c206SChristoph Hellwig } 5399275c206SChristoph Hellwig 5409275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5419275c206SChristoph Hellwig { 5429275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5437fe07d14SChristoph Hellwig 5449275c206SChristoph Hellwig if (iod->dma_len) { 5459275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5469275c206SChristoph Hellwig rq_dma_dir(req)); 5479275c206SChristoph Hellwig return; 5489275c206SChristoph Hellwig } 5499275c206SChristoph Hellwig 55091fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5519275c206SChristoph Hellwig 55291fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 55391fb2b60SLogan Gunthorpe 554c372cdd1SKeith Busch if (iod->nr_allocations == 0) 5557846c1b5SKeith Busch dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, 5569275c206SChristoph Hellwig iod->first_dma); 5578f0edf45SKeith Busch else if (iod->nr_allocations == 1) 5587846c1b5SKeith Busch dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, 55901df742dSKeith Busch iod->first_dma); 5609275c206SChristoph Hellwig else 5619275c206SChristoph Hellwig nvme_free_prps(dev, req); 56291fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 56357dacad5SJay Sternberg } 56457dacad5SJay Sternberg 565d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 566d0877473SKeith Busch { 567d0877473SKeith Busch int i; 568d0877473SKeith Busch struct scatterlist *sg; 569d0877473SKeith Busch 570d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 571d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 572d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 573d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 574d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 575d0877473SKeith Busch sg_dma_len(sg)); 576d0877473SKeith Busch } 577d0877473SKeith Busch } 578d0877473SKeith Busch 579a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 580a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 58157dacad5SJay Sternberg { 582f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 58357dacad5SJay Sternberg struct dma_pool *pool; 584b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 58591fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 58657dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 58757dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5886c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 58957dacad5SJay Sternberg __le64 *prp_list; 59057dacad5SJay Sternberg dma_addr_t prp_dma; 59157dacad5SJay Sternberg int nprps, i; 59257dacad5SJay Sternberg 5936c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 5945228b328SJan H. Schönherr if (length <= 0) { 5955228b328SJan H. Schönherr iod->first_dma = 0; 596a7a7cbe3SChaitanya Kulkarni goto done; 5975228b328SJan H. Schönherr } 59857dacad5SJay Sternberg 5996c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 60057dacad5SJay Sternberg if (dma_len) { 6016c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 60257dacad5SJay Sternberg } else { 60357dacad5SJay Sternberg sg = sg_next(sg); 60457dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 60557dacad5SJay Sternberg dma_len = sg_dma_len(sg); 60657dacad5SJay Sternberg } 60757dacad5SJay Sternberg 6086c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 60957dacad5SJay Sternberg iod->first_dma = dma_addr; 610a7a7cbe3SChaitanya Kulkarni goto done; 61157dacad5SJay Sternberg } 61257dacad5SJay Sternberg 6136c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 61457dacad5SJay Sternberg if (nprps <= (256 / 8)) { 61557dacad5SJay Sternberg pool = dev->prp_small_pool; 616c372cdd1SKeith Busch iod->nr_allocations = 0; 61757dacad5SJay Sternberg } else { 61857dacad5SJay Sternberg pool = dev->prp_page_pool; 619c372cdd1SKeith Busch iod->nr_allocations = 1; 62057dacad5SJay Sternberg } 62157dacad5SJay Sternberg 62269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 62357dacad5SJay Sternberg if (!prp_list) { 624c372cdd1SKeith Busch iod->nr_allocations = -1; 62586eea289SKeith Busch return BLK_STS_RESOURCE; 62657dacad5SJay Sternberg } 6277846c1b5SKeith Busch iod->list[0].prp_list = prp_list; 62857dacad5SJay Sternberg iod->first_dma = prp_dma; 62957dacad5SJay Sternberg i = 0; 63057dacad5SJay Sternberg for (;;) { 6316c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 63257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 63369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 63457dacad5SJay Sternberg if (!prp_list) 635fa073216SChristoph Hellwig goto free_prps; 6367846c1b5SKeith Busch iod->list[iod->nr_allocations++].prp_list = prp_list; 63757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 63857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 63957dacad5SJay Sternberg i = 1; 64057dacad5SJay Sternberg } 64157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6426c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6436c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6446c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 64557dacad5SJay Sternberg if (length <= 0) 64657dacad5SJay Sternberg break; 64757dacad5SJay Sternberg if (dma_len > 0) 64857dacad5SJay Sternberg continue; 64986eea289SKeith Busch if (unlikely(dma_len < 0)) 65086eea289SKeith Busch goto bad_sgl; 65157dacad5SJay Sternberg sg = sg_next(sg); 65257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65457dacad5SJay Sternberg } 655a7a7cbe3SChaitanya Kulkarni done: 65691fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 657a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 65886eea289SKeith Busch return BLK_STS_OK; 659fa073216SChristoph Hellwig free_prps: 660fa073216SChristoph Hellwig nvme_free_prps(dev, req); 661fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 66286eea289SKeith Busch bad_sgl: 66391fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 664d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 66591fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 66686eea289SKeith Busch return BLK_STS_IOERR; 66757dacad5SJay Sternberg } 66857dacad5SJay Sternberg 669a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 670a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 671a7a7cbe3SChaitanya Kulkarni { 672a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 673a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 674a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 675a7a7cbe3SChaitanya Kulkarni } 676a7a7cbe3SChaitanya Kulkarni 677a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 678a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 679a7a7cbe3SChaitanya Kulkarni { 680a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 681a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 682a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 683a7a7cbe3SChaitanya Kulkarni } 684a7a7cbe3SChaitanya Kulkarni 685a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 68691fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 687a7a7cbe3SChaitanya Kulkarni { 688a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 689a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 690a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 69191fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 69291fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 693a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 694b0f2853bSChristoph Hellwig int i = 0; 695a7a7cbe3SChaitanya Kulkarni 696a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 697a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 698a7a7cbe3SChaitanya Kulkarni 699b0f2853bSChristoph Hellwig if (entries == 1) { 700a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 701a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 702a7a7cbe3SChaitanya Kulkarni } 703a7a7cbe3SChaitanya Kulkarni 704a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 705a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 706c372cdd1SKeith Busch iod->nr_allocations = 0; 707a7a7cbe3SChaitanya Kulkarni } else { 708a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 709c372cdd1SKeith Busch iod->nr_allocations = 1; 710a7a7cbe3SChaitanya Kulkarni } 711a7a7cbe3SChaitanya Kulkarni 712a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 713a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 714c372cdd1SKeith Busch iod->nr_allocations = -1; 715a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 716a7a7cbe3SChaitanya Kulkarni } 717a7a7cbe3SChaitanya Kulkarni 7187846c1b5SKeith Busch iod->list[0].sg_list = sg_list; 719a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 720a7a7cbe3SChaitanya Kulkarni 721a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 722a7a7cbe3SChaitanya Kulkarni do { 723a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 724a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 725b0f2853bSChristoph Hellwig } while (--entries > 0); 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 728a7a7cbe3SChaitanya Kulkarni } 729a7a7cbe3SChaitanya Kulkarni 730dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 731dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 732dff824b2SChristoph Hellwig struct bio_vec *bv) 733dff824b2SChristoph Hellwig { 734dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7356c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7366c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 737dff824b2SChristoph Hellwig 738dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 739dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 740dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 741dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 742dff824b2SChristoph Hellwig 743dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 744dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 745dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 746a56ea614SLei Rao else 747a56ea614SLei Rao cmnd->dptr.prp2 = 0; 748359c1f88SBaolin Wang return BLK_STS_OK; 749dff824b2SChristoph Hellwig } 750dff824b2SChristoph Hellwig 75129791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 75229791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 75329791057SChristoph Hellwig struct bio_vec *bv) 75429791057SChristoph Hellwig { 75529791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 75629791057SChristoph Hellwig 75729791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 75829791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 75929791057SChristoph Hellwig return BLK_STS_RESOURCE; 76029791057SChristoph Hellwig iod->dma_len = bv->bv_len; 76129791057SChristoph Hellwig 762049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 76329791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 76429791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 76529791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 766359c1f88SBaolin Wang return BLK_STS_OK; 76729791057SChristoph Hellwig } 76829791057SChristoph Hellwig 769fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 770b131c61dSChristoph Hellwig struct nvme_command *cmnd) 77157dacad5SJay Sternberg { 772f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 77370479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 77491fb2b60SLogan Gunthorpe int rc; 77557dacad5SJay Sternberg 776dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 777a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 778dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 779dff824b2SChristoph Hellwig 780dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 7816c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 782dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 783dff824b2SChristoph Hellwig &cmnd->rw, &bv); 78429791057SChristoph Hellwig 785a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 786253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 78729791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 78829791057SChristoph Hellwig &cmnd->rw, &bv); 789dff824b2SChristoph Hellwig } 790dff824b2SChristoph Hellwig } 791dff824b2SChristoph Hellwig 792dff824b2SChristoph Hellwig iod->dma_len = 0; 79391fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 79491fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 7959b048119SChristoph Hellwig return BLK_STS_RESOURCE; 79691fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 79791fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 79891fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 799fa073216SChristoph Hellwig goto out_free_sg; 800ba1ca37eSChristoph Hellwig 80191fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 80291fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 80391fb2b60SLogan Gunthorpe if (rc) { 80491fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 80591fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 806fa073216SChristoph Hellwig goto out_free_sg; 80791fb2b60SLogan Gunthorpe } 808ba1ca37eSChristoph Hellwig 809b6c0c237SKeith Busch if (nvme_pci_use_sgls(dev, req, iod->sgt.nents)) 81091fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 811a7a7cbe3SChaitanya Kulkarni else 812a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8134aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 814fa073216SChristoph Hellwig goto out_unmap_sg; 815fa073216SChristoph Hellwig return BLK_STS_OK; 816fa073216SChristoph Hellwig 817fa073216SChristoph Hellwig out_unmap_sg: 81891fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 819fa073216SChristoph Hellwig out_free_sg: 82091fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 821ba1ca37eSChristoph Hellwig return ret; 82257dacad5SJay Sternberg } 82357dacad5SJay Sternberg 8244aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8254aedb705SChristoph Hellwig struct nvme_command *cmnd) 8264aedb705SChristoph Hellwig { 8274aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8284aedb705SChristoph Hellwig 8294aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8304aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8314aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8324aedb705SChristoph Hellwig return BLK_STS_IOERR; 8334aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 834359c1f88SBaolin Wang return BLK_STS_OK; 8354aedb705SChristoph Hellwig } 8364aedb705SChristoph Hellwig 83762451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 83862451a2bSJens Axboe { 83962451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84062451a2bSJens Axboe blk_status_t ret; 84162451a2bSJens Axboe 84252da4f3fSKeith Busch iod->aborted = false; 843c372cdd1SKeith Busch iod->nr_allocations = -1; 84491fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 84562451a2bSJens Axboe 84662451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 84762451a2bSJens Axboe if (ret) 84862451a2bSJens Axboe return ret; 84962451a2bSJens Axboe 85062451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 85162451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 85262451a2bSJens Axboe if (ret) 85362451a2bSJens Axboe goto out_free_cmd; 85462451a2bSJens Axboe } 85562451a2bSJens Axboe 85662451a2bSJens Axboe if (blk_integrity_rq(req)) { 85762451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 85862451a2bSJens Axboe if (ret) 85962451a2bSJens Axboe goto out_unmap_data; 86062451a2bSJens Axboe } 86162451a2bSJens Axboe 8626887fc64SSagi Grimberg nvme_start_request(req); 86362451a2bSJens Axboe return BLK_STS_OK; 86462451a2bSJens Axboe out_unmap_data: 86562451a2bSJens Axboe nvme_unmap_data(dev, req); 86662451a2bSJens Axboe out_free_cmd: 86762451a2bSJens Axboe nvme_cleanup_cmd(req); 86862451a2bSJens Axboe return ret; 86962451a2bSJens Axboe } 87062451a2bSJens Axboe 87157dacad5SJay Sternberg /* 87257dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 87357dacad5SJay Sternberg */ 874fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 87557dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 87657dacad5SJay Sternberg { 87757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87957dacad5SJay Sternberg struct request *req = bd->rq; 8809b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 881ebe6d874SChristoph Hellwig blk_status_t ret; 88257dacad5SJay Sternberg 883d1f06f4aSJens Axboe /* 884d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 885d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 886d1f06f4aSJens Axboe */ 8874e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 888d1f06f4aSJens Axboe return BLK_STS_IOERR; 889d1f06f4aSJens Axboe 89062451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 891d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 892d4060d2bSTao Chiu 89362451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 89462451a2bSJens Axboe if (unlikely(ret)) 895f4800d6dSChristoph Hellwig return ret; 8963233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 8973233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 8983233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 8993233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 900fc17b653SChristoph Hellwig return BLK_STS_OK; 90157dacad5SJay Sternberg } 90257dacad5SJay Sternberg 903d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 904d62cbcf6SJens Axboe { 905d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 906d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 907d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 908d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 909d62cbcf6SJens Axboe 910d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 911d62cbcf6SJens Axboe } 912d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 913d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 914d62cbcf6SJens Axboe } 915d62cbcf6SJens Axboe 916d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 917d62cbcf6SJens Axboe { 918d62cbcf6SJens Axboe /* 919d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 920d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 921d62cbcf6SJens Axboe */ 922d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 923d62cbcf6SJens Axboe return false; 924d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 925d62cbcf6SJens Axboe return false; 926d62cbcf6SJens Axboe 927d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 928d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 929d62cbcf6SJens Axboe } 930d62cbcf6SJens Axboe 931d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 932d62cbcf6SJens Axboe { 9336bfec799SKeith Busch struct request *req, *next, *prev = NULL; 934d62cbcf6SJens Axboe struct request *requeue_list = NULL; 935d62cbcf6SJens Axboe 9366bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 937d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 938d62cbcf6SJens Axboe 939d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 940d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9416bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9426bfec799SKeith Busch 9436bfec799SKeith Busch req = prev; 9446bfec799SKeith Busch if (!req) 9456bfec799SKeith Busch continue; 946d62cbcf6SJens Axboe } 947d62cbcf6SJens Axboe 9486bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 949d62cbcf6SJens Axboe /* detach rest of list, and submit */ 9506bfec799SKeith Busch req->rq_next = NULL; 951d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 9526bfec799SKeith Busch *rqlist = next; 9536bfec799SKeith Busch prev = NULL; 9546bfec799SKeith Busch } else 9556bfec799SKeith Busch prev = req; 956d62cbcf6SJens Axboe } 957d62cbcf6SJens Axboe 958d62cbcf6SJens Axboe *rqlist = requeue_list; 959d62cbcf6SJens Axboe } 960d62cbcf6SJens Axboe 961c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 962eee417b0SChristoph Hellwig { 963a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 964a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 965eee417b0SChristoph Hellwig 966a53232cbSKeith Busch if (blk_integrity_rq(req)) { 967a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 968a53232cbSKeith Busch 9694aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 970*b8f6446bSMing Lei rq_integrity_vec(req)->bv_len, rq_dma_dir(req)); 971a53232cbSKeith Busch } 972a53232cbSKeith Busch 973b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9744aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 975c234a653SJens Axboe } 976c234a653SJens Axboe 977c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 978c234a653SJens Axboe { 979c234a653SJens Axboe nvme_pci_unmap_rq(req); 98077f02a7aSChristoph Hellwig nvme_complete_rq(req); 98157dacad5SJay Sternberg } 98257dacad5SJay Sternberg 983c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 984c234a653SJens Axboe { 985c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 986c234a653SJens Axboe } 987c234a653SJens Axboe 988d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 989750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 990d783e0bdSMarta Rybczynska { 99174943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 99274943d45SKeith Busch 99374943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 994d783e0bdSMarta Rybczynska } 995d783e0bdSMarta Rybczynska 996eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 99757dacad5SJay Sternberg { 998eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 99957dacad5SJay Sternberg 1000eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1001eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1002eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1003eb281c82SSagi Grimberg } 1004adf68f21SChristoph Hellwig 1005cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1006cfa27356SChristoph Hellwig { 1007cfa27356SChristoph Hellwig if (!nvmeq->qid) 1008cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1009cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1010cfa27356SChristoph Hellwig } 1011cfa27356SChristoph Hellwig 1012c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1013c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 101457dacad5SJay Sternberg { 101574943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 101662df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 101757dacad5SJay Sternberg struct request *req; 1018adf68f21SChristoph Hellwig 1019adf68f21SChristoph Hellwig /* 1020adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1021adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1022adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1023adf68f21SChristoph Hellwig * for them but rather special case them here. 1024adf68f21SChristoph Hellwig */ 102562df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10267bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 102783a12fb7SSagi Grimberg cqe->status, &cqe->result); 1028a0fa9647SJens Axboe return; 102957dacad5SJay Sternberg } 103057dacad5SJay Sternberg 1031e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 103250b7c243SXianting Tian if (unlikely(!req)) { 103350b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 103450b7c243SXianting Tian "invalid id %d completed on queue %d\n", 103562df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 103650b7c243SXianting Tian return; 103750b7c243SXianting Tian } 103850b7c243SXianting Tian 1039604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1040c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1041c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1042c234a653SJens Axboe nvme_pci_complete_batch)) 1043ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 104483a12fb7SSagi Grimberg } 104557dacad5SJay Sternberg 10465cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10475cb525c8SJens Axboe { 1048a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1049a8de6639SAlexey Dobriyan 1050a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1051920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1052e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1053a8de6639SAlexey Dobriyan } else { 1054a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1055920d13a8SSagi Grimberg } 1056a0fa9647SJens Axboe } 1057a0fa9647SJens Axboe 1058c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1059c234a653SJens Axboe struct io_comp_batch *iob) 1060a0fa9647SJens Axboe { 10611052b8acSJens Axboe int found = 0; 106283a12fb7SSagi Grimberg 10631052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10641052b8acSJens Axboe found++; 1065b69e2ef2SKeith Busch /* 1066b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1067b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1068b69e2ef2SKeith Busch */ 1069b69e2ef2SKeith Busch dma_rmb(); 1070c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 10715cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 107257dacad5SJay Sternberg } 107357dacad5SJay Sternberg 1074324b494cSKeith Busch if (found) 1075eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10765cb525c8SJens Axboe return found; 107757dacad5SJay Sternberg } 107857dacad5SJay Sternberg 107957dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 108057dacad5SJay Sternberg { 108157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10824f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 10835cb525c8SJens Axboe 10844f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 10854f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 10864f502245SJens Axboe nvme_pci_complete_batch(&iob); 108705fae499SChaitanya Kulkarni return IRQ_HANDLED; 10884f502245SJens Axboe } 108905fae499SChaitanya Kulkarni return IRQ_NONE; 109057dacad5SJay Sternberg } 109157dacad5SJay Sternberg 109257dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 109357dacad5SJay Sternberg { 109457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10954e523547SBaolin Wang 1096750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 109757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1098d783e0bdSMarta Rybczynska return IRQ_NONE; 109957dacad5SJay Sternberg } 110057dacad5SJay Sternberg 11010b2a8a9fSChristoph Hellwig /* 1102fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11030b2a8a9fSChristoph Hellwig * Can be called from any context. 11040b2a8a9fSChristoph Hellwig */ 1105fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1106a0fa9647SJens Axboe { 11073a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1108a0fa9647SJens Axboe 1109fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1110fa059b85SKeith Busch 11113a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1112c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11133a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 111491a509f8SChristoph Hellwig } 1115442e19b7SSagi Grimberg 11165a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11177776db1cSKeith Busch { 11187776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1119dabcefabSJens Axboe bool found; 1120dabcefabSJens Axboe 1121dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1122dabcefabSJens Axboe return 0; 1123dabcefabSJens Axboe 11243a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1125c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11263a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1127dabcefabSJens Axboe 1128dabcefabSJens Axboe return found; 1129dabcefabSJens Axboe } 1130dabcefabSJens Axboe 1131ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 113257dacad5SJay Sternberg { 1133f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1134147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1135f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 113657dacad5SJay Sternberg 113757dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1138ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11393233b94cSJens Axboe 11403233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11413233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11423233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11433233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 114457dacad5SJay Sternberg } 114557dacad5SJay Sternberg 114657dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 114757dacad5SJay Sternberg { 1148f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 114957dacad5SJay Sternberg 115057dacad5SJay Sternberg c.delete_queue.opcode = opcode; 115157dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 115257dacad5SJay Sternberg 11531c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115457dacad5SJay Sternberg } 115557dacad5SJay Sternberg 115657dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1157a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 115857dacad5SJay Sternberg { 1159f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 11604b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11614b04cc6aSJens Axboe 11627c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11634b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 116457dacad5SJay Sternberg 116557dacad5SJay Sternberg /* 116616772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 116757dacad5SJay Sternberg * is attached to the request. 116857dacad5SJay Sternberg */ 116957dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 117057dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 117157dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 117257dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117357dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1174a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 117557dacad5SJay Sternberg 11761c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117757dacad5SJay Sternberg } 117857dacad5SJay Sternberg 117957dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 118057dacad5SJay Sternberg struct nvme_queue *nvmeq) 118157dacad5SJay Sternberg { 11829abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1183f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118481c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 118557dacad5SJay Sternberg 118657dacad5SJay Sternberg /* 11879abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11889abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11899abd68efSJens Axboe * URGENT. 11909abd68efSJens Axboe */ 11919abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11929abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11939abd68efSJens Axboe 11949abd68efSJens Axboe /* 119516772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 119657dacad5SJay Sternberg * is attached to the request. 119757dacad5SJay Sternberg */ 119857dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 119957dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 120057dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 120157dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 120257dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 120357dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 120457dacad5SJay Sternberg 12051c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120657dacad5SJay Sternberg } 120757dacad5SJay Sternberg 120857dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 120957dacad5SJay Sternberg { 121057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 121457dacad5SJay Sternberg { 121557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 121657dacad5SJay Sternberg } 121757dacad5SJay Sternberg 1218de671d61SJens Axboe static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 121957dacad5SJay Sternberg { 1220a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 122157dacad5SJay Sternberg 122227fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 122327fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1224e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1225e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 1226de671d61SJens Axboe return RQ_END_IO_NONE; 122757dacad5SJay Sternberg } 122857dacad5SJay Sternberg 1229b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1230b2a0eb1aSKeith Busch { 1231b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1232b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1233b2a0eb1aSKeith Busch */ 1234b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1235b2a0eb1aSKeith Busch 1236ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1237ad70062cSJianchao Wang switch (dev->ctrl.state) { 1238ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1239ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1240b2a0eb1aSKeith Busch return false; 1241ad70062cSJianchao Wang default: 1242ad70062cSJianchao Wang break; 1243ad70062cSJianchao Wang } 1244b2a0eb1aSKeith Busch 1245b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1246b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1247b2a0eb1aSKeith Busch */ 1248b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1249b2a0eb1aSKeith Busch return false; 1250b2a0eb1aSKeith Busch 1251b2a0eb1aSKeith Busch return true; 1252b2a0eb1aSKeith Busch } 1253b2a0eb1aSKeith Busch 1254b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1255b2a0eb1aSKeith Busch { 1256b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1257b2a0eb1aSKeith Busch u16 pci_status; 1258b2a0eb1aSKeith Busch int result; 1259b2a0eb1aSKeith Busch 1260b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1261b2a0eb1aSKeith Busch &pci_status); 1262b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1263b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1264b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1265b2a0eb1aSKeith Busch csts, pci_status); 1266b2a0eb1aSKeith Busch else 1267b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1268b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1269b2a0eb1aSKeith Busch csts, result); 12704641a8e6SKeith Busch 12714641a8e6SKeith Busch if (csts != ~0) 12724641a8e6SKeith Busch return; 12734641a8e6SKeith Busch 12744641a8e6SKeith Busch dev_warn(dev->ctrl.device, 12754641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 12764641a8e6SKeith Busch dev_warn(dev->ctrl.device, 12774641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1278b2a0eb1aSKeith Busch } 1279b2a0eb1aSKeith Busch 12809bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 128157dacad5SJay Sternberg { 1282f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1283a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 128457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 128557dacad5SJay Sternberg struct request *abort_req; 1286f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1287b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1288b2a0eb1aSKeith Busch 1289651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1290651438bbSWen Xiong * the recovery mechanism will surely fail. 1291651438bbSWen Xiong */ 1292651438bbSWen Xiong mb(); 1293651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1294651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1295651438bbSWen Xiong 1296b2a0eb1aSKeith Busch /* 1297b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1298b2a0eb1aSKeith Busch */ 1299b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1300b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 130171a5bb15SKeith Busch goto disable; 1302b2a0eb1aSKeith Busch } 130357dacad5SJay Sternberg 130431c7c7d2SChristoph Hellwig /* 13057776db1cSKeith Busch * Did we miss an interrupt? 13067776db1cSKeith Busch */ 1307fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13085a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1309fa059b85SKeith Busch else 1310bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1311fa059b85SKeith Busch 13121c584208SKeith Busch if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { 13137776db1cSKeith Busch dev_warn(dev->ctrl.device, 13147776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13157776db1cSKeith Busch req->tag, nvmeq->qid); 1316db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13177776db1cSKeith Busch } 13187776db1cSKeith Busch 13197776db1cSKeith Busch /* 1320fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1321fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1322fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1323db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1324fd634f41SChristoph Hellwig */ 13254244140dSKeith Busch switch (dev->ctrl.state) { 13264244140dSKeith Busch case NVME_CTRL_CONNECTING: 13272036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1328df561f66SGustavo A. R. Silva fallthrough; 13292036f726SKeith Busch case NVME_CTRL_DELETING: 1330b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1331fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1332fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 133327fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13347ad92f65STong Zhang nvme_dev_disable(dev, true); 1335db8c48e4SChristoph Hellwig return BLK_EH_DONE; 133639a9dd81SKeith Busch case NVME_CTRL_RESETTING: 133739a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13384244140dSKeith Busch default: 13394244140dSKeith Busch break; 1340fd634f41SChristoph Hellwig } 1341fd634f41SChristoph Hellwig 1342fd634f41SChristoph Hellwig /* 1343e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1344e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1345e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 134631c7c7d2SChristoph Hellwig */ 1347f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13481b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 134957dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 135057dacad5SJay Sternberg req->tag, nvmeq->qid); 13517ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 135271a5bb15SKeith Busch goto disable; 135357dacad5SJay Sternberg } 135457dacad5SJay Sternberg 1355e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1356e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1357e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1358e7a2a87dSChristoph Hellwig } 135952da4f3fSKeith Busch iod->aborted = true; 136057dacad5SJay Sternberg 136157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 136285f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 136357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 136457dacad5SJay Sternberg 13651b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 136686141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 136786141440SChristoph Hellwig req->tag, 136886141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 136986141440SChristoph Hellwig nvmeq->qid); 1370e7a2a87dSChristoph Hellwig 1371e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 137239dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13736bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13746bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 137531c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 137657dacad5SJay Sternberg } 1377e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 137857dacad5SJay Sternberg 1379e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1380e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1381e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 138257dacad5SJay Sternberg 138357dacad5SJay Sternberg /* 138457dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 138557dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 138657dacad5SJay Sternberg * as the device then is in a faulty state. 138757dacad5SJay Sternberg */ 138857dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 138971a5bb15SKeith Busch 139071a5bb15SKeith Busch disable: 139171a5bb15SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) 139271a5bb15SKeith Busch return BLK_EH_DONE; 139371a5bb15SKeith Busch 139471a5bb15SKeith Busch nvme_dev_disable(dev, false); 139571a5bb15SKeith Busch if (nvme_try_sched_reset(&dev->ctrl)) 139671a5bb15SKeith Busch nvme_unquiesce_io_queues(&dev->ctrl); 139771a5bb15SKeith Busch return BLK_EH_DONE; 139857dacad5SJay Sternberg } 139957dacad5SJay Sternberg 140057dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 140157dacad5SJay Sternberg { 14028a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 140357dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 140463223078SChristoph Hellwig if (!nvmeq->sq_cmds) 140563223078SChristoph Hellwig return; 14060f238ff5SLogan Gunthorpe 140763223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 140888a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14098a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 141063223078SChristoph Hellwig } else { 14118a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 141263223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14130f238ff5SLogan Gunthorpe } 141457dacad5SJay Sternberg } 141557dacad5SJay Sternberg 141657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 141757dacad5SJay Sternberg { 141857dacad5SJay Sternberg int i; 141957dacad5SJay Sternberg 1420d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1421d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1422147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 142357dacad5SJay Sternberg } 142457dacad5SJay Sternberg } 142557dacad5SJay Sternberg 142610981f23SChristoph Hellwig static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid) 142757dacad5SJay Sternberg { 142810981f23SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[qid]; 142910981f23SChristoph Hellwig 14304e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 143110981f23SChristoph Hellwig return; 143257dacad5SJay Sternberg 14334e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1434d1f06f4aSJens Axboe mb(); 143557dacad5SJay Sternberg 14364e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14371c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14389f27bd70SChristoph Hellwig nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 14397c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 144010981f23SChristoph Hellwig pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); 144157dacad5SJay Sternberg } 144257dacad5SJay Sternberg 14438fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14448fae268bSKeith Busch { 14458fae268bSKeith Busch int i; 14468fae268bSKeith Busch 14478fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 144810981f23SChristoph Hellwig nvme_suspend_queue(dev, i); 144957dacad5SJay Sternberg } 145057dacad5SJay Sternberg 1451fa46c6fbSKeith Busch /* 1452fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14539210c075SDongli Zhang * that can check this device's completion queues have synced, except 14549210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14559210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1456fa46c6fbSKeith Busch */ 1457fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1458fa46c6fbSKeith Busch { 1459fa46c6fbSKeith Busch int i; 1460fa46c6fbSKeith Busch 14619210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14629210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1463c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 14649210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14659210c075SDongli Zhang } 1466fa46c6fbSKeith Busch } 1467fa46c6fbSKeith Busch 146857dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 146957dacad5SJay Sternberg int entry_size) 147057dacad5SJay Sternberg { 147157dacad5SJay Sternberg int q_depth = dev->q_depth; 14725fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14736c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 147457dacad5SJay Sternberg 147557dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 147657dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14774e523547SBaolin Wang 14786c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 147957dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 148057dacad5SJay Sternberg 148157dacad5SJay Sternberg /* 148257dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 148357dacad5SJay Sternberg * would be better to map queues in system memory with the 148457dacad5SJay Sternberg * original depth 148557dacad5SJay Sternberg */ 148657dacad5SJay Sternberg if (q_depth < 64) 148757dacad5SJay Sternberg return -ENOMEM; 148857dacad5SJay Sternberg } 148957dacad5SJay Sternberg 149057dacad5SJay Sternberg return q_depth; 149157dacad5SJay Sternberg } 149257dacad5SJay Sternberg 149357dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14948a1d09a6SBenjamin Herrenschmidt int qid) 149557dacad5SJay Sternberg { 14960f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1497815c6704SKeith Busch 14980f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14998a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1500bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15010f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15020f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 150363223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 150463223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 150563223078SChristoph Hellwig return 0; 150663223078SChristoph Hellwig } 1507bfac8e9fSAlan Mikhak 15088a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1509bfac8e9fSAlan Mikhak } 15100f238ff5SLogan Gunthorpe } 15110f238ff5SLogan Gunthorpe 15128a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 151357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 151457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 151557dacad5SJay Sternberg return -ENOMEM; 151657dacad5SJay Sternberg return 0; 151757dacad5SJay Sternberg } 151857dacad5SJay Sternberg 1519a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 152057dacad5SJay Sternberg { 1521147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 152257dacad5SJay Sternberg 152362314e40SKeith Busch if (dev->ctrl.queue_count > qid) 152462314e40SKeith Busch return 0; 152557dacad5SJay Sternberg 1526c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15278a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15288a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 152957dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 153057dacad5SJay Sternberg if (!nvmeq->cqes) 153157dacad5SJay Sternberg goto free_nvmeq; 153257dacad5SJay Sternberg 15338a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 153457dacad5SJay Sternberg goto free_cqdma; 153557dacad5SJay Sternberg 153657dacad5SJay Sternberg nvmeq->dev = dev; 15371ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15383a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 153957dacad5SJay Sternberg nvmeq->cq_head = 0; 154057dacad5SJay Sternberg nvmeq->cq_phase = 1; 154157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 154257dacad5SJay Sternberg nvmeq->qid = qid; 1543d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 154457dacad5SJay Sternberg 1545147b27e4SSagi Grimberg return 0; 154657dacad5SJay Sternberg 154757dacad5SJay Sternberg free_cqdma: 15488a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 154957dacad5SJay Sternberg nvmeq->cq_dma_addr); 155057dacad5SJay Sternberg free_nvmeq: 1551147b27e4SSagi Grimberg return -ENOMEM; 155257dacad5SJay Sternberg } 155357dacad5SJay Sternberg 1554dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 155557dacad5SJay Sternberg { 15560ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15570ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15580ff199cbSChristoph Hellwig 15590ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15600ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15610ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15620ff199cbSChristoph Hellwig } else { 15630ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15640ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15650ff199cbSChristoph Hellwig } 156657dacad5SJay Sternberg } 156757dacad5SJay Sternberg 156857dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 156957dacad5SJay Sternberg { 157057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 157157dacad5SJay Sternberg 157257dacad5SJay Sternberg nvmeq->sq_tail = 0; 157338210800SKeith Busch nvmeq->last_sq_tail = 0; 157457dacad5SJay Sternberg nvmeq->cq_head = 0; 157557dacad5SJay Sternberg nvmeq->cq_phase = 1; 157657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15778a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1578f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 157957dacad5SJay Sternberg dev->online_queues++; 15803a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 158157dacad5SJay Sternberg } 158257dacad5SJay Sternberg 1583e4b9852aSCasey Chen /* 1584e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1585e4b9852aSCasey Chen */ 1586e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1587e4b9852aSCasey Chen { 1588e4b9852aSCasey Chen /* 1589e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1590e4b9852aSCasey Chen */ 1591e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1592e4b9852aSCasey Chen return -ENODEV; 1593e4b9852aSCasey Chen 1594e4b9852aSCasey Chen /* 1595e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1596e4b9852aSCasey Chen */ 1597e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1598e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1599e4b9852aSCasey Chen return -ENODEV; 1600e4b9852aSCasey Chen } 1601e4b9852aSCasey Chen 1602e4b9852aSCasey Chen return 0; 1603e4b9852aSCasey Chen } 1604e4b9852aSCasey Chen 16054b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 160657dacad5SJay Sternberg { 160757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 160857dacad5SJay Sternberg int result; 16097c349ddeSKeith Busch u16 vector = 0; 161057dacad5SJay Sternberg 1611d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1612d1ed6aa1SChristoph Hellwig 161322b55601SKeith Busch /* 161422b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 161522b55601SKeith Busch * has only one vector available. 161622b55601SKeith Busch */ 16174b04cc6aSJens Axboe if (!polled) 1618a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16194b04cc6aSJens Axboe else 16207c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16214b04cc6aSJens Axboe 1622a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1623ded45505SKeith Busch if (result) 1624ded45505SKeith Busch return result; 162557dacad5SJay Sternberg 162657dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 162757dacad5SJay Sternberg if (result < 0) 1628ded45505SKeith Busch return result; 1629c80b36cdSEdmund Nadolski if (result) 163057dacad5SJay Sternberg goto release_cq; 163157dacad5SJay Sternberg 1632a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16334b04cc6aSJens Axboe 1634e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1635e4b9852aSCasey Chen if (result) 1636e4b9852aSCasey Chen return result; 1637e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16387c349ddeSKeith Busch if (!polled) { 1639dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 164057dacad5SJay Sternberg if (result < 0) 164157dacad5SJay Sternberg goto release_sq; 16424b04cc6aSJens Axboe } 164357dacad5SJay Sternberg 16444e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1645e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 164657dacad5SJay Sternberg return result; 164757dacad5SJay Sternberg 164857dacad5SJay Sternberg release_sq: 1649f25a2dfcSJianchao Wang dev->online_queues--; 1650e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 165157dacad5SJay Sternberg adapter_delete_sq(dev, qid); 165257dacad5SJay Sternberg release_cq: 165357dacad5SJay Sternberg adapter_delete_cq(dev, qid); 165457dacad5SJay Sternberg return result; 165557dacad5SJay Sternberg } 165657dacad5SJay Sternberg 1657f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 165857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 165977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 166057dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1661e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 166257dacad5SJay Sternberg .timeout = nvme_timeout, 166357dacad5SJay Sternberg }; 166457dacad5SJay Sternberg 1665f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1666376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1667d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1668376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1669376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1670376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1671e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1672376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1673376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1674c6d962aeSChristoph Hellwig .poll = nvme_poll, 1675dabcefabSJens Axboe }; 1676dabcefabSJens Axboe 167757dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 167857dacad5SJay Sternberg { 16791c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 168069d9a99cSKeith Busch /* 168169d9a99cSKeith Busch * If the controller was reset during removal, it's possible 168269d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 168369d9a99cSKeith Busch * queue to flush these to completion. 168469d9a99cSKeith Busch */ 16859f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 16860da7feaaSChristoph Hellwig nvme_remove_admin_tag_set(&dev->ctrl); 168757dacad5SJay Sternberg } 168857dacad5SJay Sternberg } 168957dacad5SJay Sternberg 169097f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 169197f6ef64SXu Yu { 169297f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 169397f6ef64SXu Yu } 169497f6ef64SXu Yu 169597f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 169697f6ef64SXu Yu { 169797f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 169897f6ef64SXu Yu 169997f6ef64SXu Yu if (size <= dev->bar_mapped_size) 170097f6ef64SXu Yu return 0; 170197f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 170297f6ef64SXu Yu return -ENOMEM; 170397f6ef64SXu Yu if (dev->bar) 170497f6ef64SXu Yu iounmap(dev->bar); 170597f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 170697f6ef64SXu Yu if (!dev->bar) { 170797f6ef64SXu Yu dev->bar_mapped_size = 0; 170897f6ef64SXu Yu return -ENOMEM; 170997f6ef64SXu Yu } 171097f6ef64SXu Yu dev->bar_mapped_size = size; 171197f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 171297f6ef64SXu Yu 171397f6ef64SXu Yu return 0; 171497f6ef64SXu Yu } 171597f6ef64SXu Yu 171601ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 171757dacad5SJay Sternberg { 171857dacad5SJay Sternberg int result; 171957dacad5SJay Sternberg u32 aqa; 172057dacad5SJay Sternberg struct nvme_queue *nvmeq; 172157dacad5SJay Sternberg 172297f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 172397f6ef64SXu Yu if (result < 0) 172497f6ef64SXu Yu return result; 172597f6ef64SXu Yu 17268ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 172720d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 172857dacad5SJay Sternberg 17297a67cbeaSChristoph Hellwig if (dev->subsystem && 17307a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17317a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 173257dacad5SJay Sternberg 1733285b6e9bSChristoph Hellwig /* 1734285b6e9bSChristoph Hellwig * If the device has been passed off to us in an enabled state, just 1735285b6e9bSChristoph Hellwig * clear the enabled bit. The spec says we should set the 'shutdown 1736285b6e9bSChristoph Hellwig * notification bits', but doing so may cause the device to complete 1737285b6e9bSChristoph Hellwig * commands to the admin queue ... and we don't know what memory that 1738285b6e9bSChristoph Hellwig * might be pointing at! 1739285b6e9bSChristoph Hellwig */ 1740285b6e9bSChristoph Hellwig result = nvme_disable_ctrl(&dev->ctrl, false); 174157dacad5SJay Sternberg if (result < 0) 174257dacad5SJay Sternberg return result; 174357dacad5SJay Sternberg 1744a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1745147b27e4SSagi Grimberg if (result) 1746147b27e4SSagi Grimberg return result; 174757dacad5SJay Sternberg 1748635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1749635333e4SMax Gurtovoy 1750147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 175157dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 175257dacad5SJay Sternberg aqa |= aqa << 16; 175357dacad5SJay Sternberg 17547a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17557a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17567a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 175757dacad5SJay Sternberg 1758c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 175957dacad5SJay Sternberg if (result) 1760d4875622SKeith Busch return result; 176157dacad5SJay Sternberg 176257dacad5SJay Sternberg nvmeq->cq_vector = 0; 1763161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1764dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 176557dacad5SJay Sternberg if (result) { 17667c349ddeSKeith Busch dev->online_queues--; 1767d4875622SKeith Busch return result; 176857dacad5SJay Sternberg } 176957dacad5SJay Sternberg 17704e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 177157dacad5SJay Sternberg return result; 177257dacad5SJay Sternberg } 177357dacad5SJay Sternberg 1774749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 177557dacad5SJay Sternberg { 17764b04cc6aSJens Axboe unsigned i, max, rw_queues; 1777749941f2SChristoph Hellwig int ret = 0; 177857dacad5SJay Sternberg 1779d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1780a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1781749941f2SChristoph Hellwig ret = -ENOMEM; 178257dacad5SJay Sternberg break; 1783749941f2SChristoph Hellwig } 1784749941f2SChristoph Hellwig } 178557dacad5SJay Sternberg 1786d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1787e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1788e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1789e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17904b04cc6aSJens Axboe } else { 17914b04cc6aSJens Axboe rw_queues = max; 17924b04cc6aSJens Axboe } 17934b04cc6aSJens Axboe 1794949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17954b04cc6aSJens Axboe bool polled = i > rw_queues; 17964b04cc6aSJens Axboe 17974b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1798d4875622SKeith Busch if (ret) 179957dacad5SJay Sternberg break; 180057dacad5SJay Sternberg } 180157dacad5SJay Sternberg 1802749941f2SChristoph Hellwig /* 1803749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18048adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18058adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1806749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1807749941f2SChristoph Hellwig */ 1808749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 180957dacad5SJay Sternberg } 181057dacad5SJay Sternberg 181188de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 181257dacad5SJay Sternberg { 181388de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 181488de4598SChristoph Hellwig 181588de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 181688de4598SChristoph Hellwig } 181788de4598SChristoph Hellwig 181888de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 181988de4598SChristoph Hellwig { 182088de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 182188de4598SChristoph Hellwig } 182288de4598SChristoph Hellwig 1823f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 182457dacad5SJay Sternberg { 182588de4598SChristoph Hellwig u64 size, offset; 182657dacad5SJay Sternberg resource_size_t bar_size; 182757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18288969f1f8SChristoph Hellwig int bar; 182957dacad5SJay Sternberg 18309fe5c59fSKeith Busch if (dev->cmb_size) 18319fe5c59fSKeith Busch return; 18329fe5c59fSKeith Busch 183320d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 183420d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 183520d3bb92SKlaus Jensen 18367a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1837f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1838f65efd6dSChristoph Hellwig return; 1839202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 184057dacad5SJay Sternberg 184188de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 184288de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18438969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18448969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 184557dacad5SJay Sternberg 184657dacad5SJay Sternberg if (offset > bar_size) 1847f65efd6dSChristoph Hellwig return; 184857dacad5SJay Sternberg 184957dacad5SJay Sternberg /* 185020d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 185120d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 185220d3bb92SKlaus Jensen */ 185320d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 185420d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 185520d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 185620d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 185720d3bb92SKlaus Jensen } 185820d3bb92SKlaus Jensen 185920d3bb92SKlaus Jensen /* 186057dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 186157dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 186257dacad5SJay Sternberg * the reported size of the BAR 186357dacad5SJay Sternberg */ 186457dacad5SJay Sternberg if (size > bar_size - offset) 186557dacad5SJay Sternberg size = bar_size - offset; 186657dacad5SJay Sternberg 18670f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18680f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18690f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1870f65efd6dSChristoph Hellwig return; 18710f238ff5SLogan Gunthorpe } 18720f238ff5SLogan Gunthorpe 187357dacad5SJay Sternberg dev->cmb_size = size; 18740f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18750f238ff5SLogan Gunthorpe 18760f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18770f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18780f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1879e917a849SKeith Busch 1880e917a849SKeith Busch nvme_update_attrs(dev); 188157dacad5SJay Sternberg } 188257dacad5SJay Sternberg 188387ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 188457dacad5SJay Sternberg { 18856c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18864033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1887f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 188887ad72a5SChristoph Hellwig int ret; 188987ad72a5SChristoph Hellwig 189087ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 189187ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 189287ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 18936c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 189487ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 189587ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 189687ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 189787ad72a5SChristoph Hellwig 189887ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 189987ad72a5SChristoph Hellwig if (ret) { 190087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 190187ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 190287ad72a5SChristoph Hellwig ret, bits); 1903a5df5e79SKeith Busch } else 1904a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1905a5df5e79SKeith Busch 190687ad72a5SChristoph Hellwig return ret; 190787ad72a5SChristoph Hellwig } 190887ad72a5SChristoph Hellwig 190987ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 191087ad72a5SChristoph Hellwig { 191187ad72a5SChristoph Hellwig int i; 191287ad72a5SChristoph Hellwig 191387ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 191487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19156c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 191687ad72a5SChristoph Hellwig 1917cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1918cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1919cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 192087ad72a5SChristoph Hellwig } 192187ad72a5SChristoph Hellwig 192287ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 192387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19244033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19254033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19264033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 192787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19287e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 192987ad72a5SChristoph Hellwig } 193087ad72a5SChristoph Hellwig 193192dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 193292dc6895SChristoph Hellwig u32 chunk_size) 193387ad72a5SChristoph Hellwig { 193487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 193592dc6895SChristoph Hellwig u32 max_entries, len; 19364033f35dSChristoph Hellwig dma_addr_t descs_dma; 19372ee0e4edSDan Carpenter int i = 0; 193887ad72a5SChristoph Hellwig void **bufs; 19396fbcde66SMinwoo Im u64 size, tmp; 194087ad72a5SChristoph Hellwig 194187ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 194287ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 194387ad72a5SChristoph Hellwig max_entries = tmp; 1944044a9df1SChristoph Hellwig 1945044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1946044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1947044a9df1SChristoph Hellwig 1948750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19494033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 195087ad72a5SChristoph Hellwig if (!descs) 195187ad72a5SChristoph Hellwig goto out; 195287ad72a5SChristoph Hellwig 195387ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 195487ad72a5SChristoph Hellwig if (!bufs) 195587ad72a5SChristoph Hellwig goto out_free_descs; 195687ad72a5SChristoph Hellwig 1957244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 195887ad72a5SChristoph Hellwig dma_addr_t dma_addr; 195987ad72a5SChristoph Hellwig 196050cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 196187ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 196287ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 196387ad72a5SChristoph Hellwig if (!bufs[i]) 196487ad72a5SChristoph Hellwig break; 196587ad72a5SChristoph Hellwig 196687ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19676c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 196887ad72a5SChristoph Hellwig i++; 196987ad72a5SChristoph Hellwig } 197087ad72a5SChristoph Hellwig 197192dc6895SChristoph Hellwig if (!size) 197287ad72a5SChristoph Hellwig goto out_free_bufs; 197387ad72a5SChristoph Hellwig 197487ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 197587ad72a5SChristoph Hellwig dev->host_mem_size = size; 197687ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19774033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 197887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 197987ad72a5SChristoph Hellwig return 0; 198087ad72a5SChristoph Hellwig 198187ad72a5SChristoph Hellwig out_free_bufs: 198287ad72a5SChristoph Hellwig while (--i >= 0) { 19836c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 198487ad72a5SChristoph Hellwig 1985cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1986cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1987cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 198887ad72a5SChristoph Hellwig } 198987ad72a5SChristoph Hellwig 199087ad72a5SChristoph Hellwig kfree(bufs); 199187ad72a5SChristoph Hellwig out_free_descs: 19924033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19934033f35dSChristoph Hellwig descs_dma); 199487ad72a5SChristoph Hellwig out: 199587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 199687ad72a5SChristoph Hellwig return -ENOMEM; 199787ad72a5SChristoph Hellwig } 199887ad72a5SChristoph Hellwig 199992dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 200092dc6895SChristoph Hellwig { 20019dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20029dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20039dc54a0dSChaitanya Kulkarni u64 chunk_size; 200492dc6895SChristoph Hellwig 200592dc6895SChristoph Hellwig /* start big and work our way down */ 20069dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 200792dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 200892dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 200992dc6895SChristoph Hellwig return 0; 201092dc6895SChristoph Hellwig nvme_free_host_mem(dev); 201192dc6895SChristoph Hellwig } 201292dc6895SChristoph Hellwig } 201392dc6895SChristoph Hellwig 201492dc6895SChristoph Hellwig return -ENOMEM; 201592dc6895SChristoph Hellwig } 201692dc6895SChristoph Hellwig 20179620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 201887ad72a5SChristoph Hellwig { 201987ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 202087ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 202187ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 202287ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20236fbcde66SMinwoo Im int ret; 202487ad72a5SChristoph Hellwig 2025acb71e53SChristoph Hellwig if (!dev->ctrl.hmpre) 2026acb71e53SChristoph Hellwig return 0; 2027acb71e53SChristoph Hellwig 202887ad72a5SChristoph Hellwig preferred = min(preferred, max); 202987ad72a5SChristoph Hellwig if (min > max) { 203087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 203187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 203287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 203387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20349620cfbaSChristoph Hellwig return 0; 203587ad72a5SChristoph Hellwig } 203687ad72a5SChristoph Hellwig 203787ad72a5SChristoph Hellwig /* 203887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 203987ad72a5SChristoph Hellwig */ 204087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 204187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 204287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 204387ad72a5SChristoph Hellwig else 204487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 204587ad72a5SChristoph Hellwig } 204687ad72a5SChristoph Hellwig 204787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 204892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 204992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 205092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20519620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 205287ad72a5SChristoph Hellwig } 205387ad72a5SChristoph Hellwig 205492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 205592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 205692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 205792dc6895SChristoph Hellwig } 205892dc6895SChristoph Hellwig 20599620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20609620cfbaSChristoph Hellwig if (ret) 206187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20629620cfbaSChristoph Hellwig return ret; 206357dacad5SJay Sternberg } 206457dacad5SJay Sternberg 20650521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 20660521905eSKeith Busch char *buf) 20670521905eSKeith Busch { 20680521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20690521905eSKeith Busch 20700521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 20710521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 20720521905eSKeith Busch } 20730521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 20740521905eSKeith Busch 20751751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 20761751e97aSKeith Busch char *buf) 20771751e97aSKeith Busch { 20781751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20791751e97aSKeith Busch 20801751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 20811751e97aSKeith Busch } 20821751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 20831751e97aSKeith Busch 20841751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 20851751e97aSKeith Busch char *buf) 20861751e97aSKeith Busch { 20871751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20881751e97aSKeith Busch 20891751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 20901751e97aSKeith Busch } 20911751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 20921751e97aSKeith Busch 2093a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2094a5df5e79SKeith Busch char *buf) 2095a5df5e79SKeith Busch { 2096a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2097a5df5e79SKeith Busch 2098a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2099a5df5e79SKeith Busch } 2100a5df5e79SKeith Busch 2101a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2102a5df5e79SKeith Busch const char *buf, size_t count) 2103a5df5e79SKeith Busch { 2104a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2105a5df5e79SKeith Busch bool new; 2106a5df5e79SKeith Busch int ret; 2107a5df5e79SKeith Busch 210899722c8aSChristophe JAILLET if (kstrtobool(buf, &new) < 0) 2109a5df5e79SKeith Busch return -EINVAL; 2110a5df5e79SKeith Busch 2111a5df5e79SKeith Busch if (new == ndev->hmb) 2112a5df5e79SKeith Busch return count; 2113a5df5e79SKeith Busch 2114a5df5e79SKeith Busch if (new) { 2115a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2116a5df5e79SKeith Busch } else { 2117a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2118a5df5e79SKeith Busch if (!ret) 2119a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2120a5df5e79SKeith Busch } 2121a5df5e79SKeith Busch 2122a5df5e79SKeith Busch if (ret < 0) 2123a5df5e79SKeith Busch return ret; 2124a5df5e79SKeith Busch 2125a5df5e79SKeith Busch return count; 2126a5df5e79SKeith Busch } 2127a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2128a5df5e79SKeith Busch 21290521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 21300521905eSKeith Busch struct attribute *a, int n) 21310521905eSKeith Busch { 21320521905eSKeith Busch struct nvme_ctrl *ctrl = 21330521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 21340521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 21350521905eSKeith Busch 21361751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 21371751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 21381751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 21391751e97aSKeith Busch if (!dev->cmbsz) 21400521905eSKeith Busch return 0; 21411751e97aSKeith Busch } 2142a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2143a5df5e79SKeith Busch return 0; 2144a5df5e79SKeith Busch 21450521905eSKeith Busch return a->mode; 21460521905eSKeith Busch } 21470521905eSKeith Busch 21480521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 21490521905eSKeith Busch &dev_attr_cmb.attr, 21501751e97aSKeith Busch &dev_attr_cmbloc.attr, 21511751e97aSKeith Busch &dev_attr_cmbsz.attr, 2152a5df5e79SKeith Busch &dev_attr_hmb.attr, 21530521905eSKeith Busch NULL, 21540521905eSKeith Busch }; 21550521905eSKeith Busch 215686adbf0cSChristoph Hellwig static const struct attribute_group nvme_pci_dev_attrs_group = { 21570521905eSKeith Busch .attrs = nvme_pci_attrs, 21580521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 21590521905eSKeith Busch }; 21600521905eSKeith Busch 216186adbf0cSChristoph Hellwig static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 216286adbf0cSChristoph Hellwig &nvme_dev_attrs_group, 216386adbf0cSChristoph Hellwig &nvme_pci_dev_attrs_group, 216486adbf0cSChristoph Hellwig NULL, 216586adbf0cSChristoph Hellwig }; 216686adbf0cSChristoph Hellwig 2167e917a849SKeith Busch static void nvme_update_attrs(struct nvme_dev *dev) 2168e917a849SKeith Busch { 2169e917a849SKeith Busch sysfs_update_group(&dev->ctrl.device->kobj, &nvme_pci_dev_attrs_group); 2170e917a849SKeith Busch } 2171e917a849SKeith Busch 2172612b7286SMing Lei /* 2173612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2174612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2175612b7286SMing Lei */ 2176612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 21773b6592f7SJens Axboe { 2178612b7286SMing Lei struct nvme_dev *dev = affd->priv; 21792a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2180c45b1fa2SMing Lei 21813b6592f7SJens Axboe /* 2182ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2183612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2184612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2185612b7286SMing Lei * 2186612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2187612b7286SMing Lei * write and read queues. 2188612b7286SMing Lei * 2189612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2190612b7286SMing Lei * queue. 21913b6592f7SJens Axboe */ 2192612b7286SMing Lei if (!nrirqs) { 2193612b7286SMing Lei nrirqs = 1; 2194612b7286SMing Lei nr_read_queues = 0; 21952a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2196612b7286SMing Lei nr_read_queues = 0; 21972a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2198612b7286SMing Lei nr_read_queues = 1; 21993b6592f7SJens Axboe } else { 22002a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22013b6592f7SJens Axboe } 2202612b7286SMing Lei 2203612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2204612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2205612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2206612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2207612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22083b6592f7SJens Axboe } 22093b6592f7SJens Axboe 22106451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22113b6592f7SJens Axboe { 22123b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22133b6592f7SJens Axboe struct irq_affinity affd = { 22143b6592f7SJens Axboe .pre_vectors = 1, 2215612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2216612b7286SMing Lei .priv = dev, 22173b6592f7SJens Axboe }; 221821cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22196451fe73SJens Axboe 22206451fe73SJens Axboe /* 222121cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 222221cc2f3fSJeffle Xu * left over for non-polled I/O. 22236451fe73SJens Axboe */ 222421cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 222521cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22263b6592f7SJens Axboe 222721cc2f3fSJeffle Xu /* 222821cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 222921cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 223021cc2f3fSJeffle Xu */ 2231612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2232612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 22333b6592f7SJens Axboe 223466341331SBenjamin Herrenschmidt /* 223521cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 223621cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 223721cc2f3fSJeffle Xu * vector. 223866341331SBenjamin Herrenschmidt */ 223966341331SBenjamin Herrenschmidt irq_queues = 1; 224021cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 224121cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2242612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 22433b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 22443b6592f7SJens Axboe } 22453b6592f7SJens Axboe 22462a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 22472a5bcfddSWeiping Zhang { 2248e3aef095SNiklas Schnelle /* 2249e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2250e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2251e3aef095SNiklas Schnelle */ 2252e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2253e3aef095SNiklas Schnelle return 1; 22542a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 22552a5bcfddSWeiping Zhang } 22562a5bcfddSWeiping Zhang 225757dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 225857dacad5SJay Sternberg { 2259147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 226057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 22612a5bcfddSWeiping Zhang unsigned int nr_io_queues; 226297f6ef64SXu Yu unsigned long size; 22632a5bcfddSWeiping Zhang int result; 226457dacad5SJay Sternberg 22652a5bcfddSWeiping Zhang /* 22662a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 22672a5bcfddSWeiping Zhang * stable values to work with. 22682a5bcfddSWeiping Zhang */ 22692a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 22702a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2271d38e9f04SBenjamin Herrenschmidt 2272ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 22739a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 22749a0be7abSChristoph Hellwig if (result < 0) 227557dacad5SJay Sternberg return result; 22769a0be7abSChristoph Hellwig 2277f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2278a5229050SKeith Busch return 0; 227957dacad5SJay Sternberg 2280e4b9852aSCasey Chen /* 2281e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2282e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2283e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2284e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2285e4b9852aSCasey Chen * nvme_dev_disable() path. 2286e4b9852aSCasey Chen */ 2287e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2288e4b9852aSCasey Chen if (result) 2289e4b9852aSCasey Chen return result; 2290e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2291e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 22924e224106SChristoph Hellwig 22930f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 229457dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 229557dacad5SJay Sternberg sizeof(struct nvme_command)); 229688d356caSChristoph Hellwig if (result > 0) { 229757dacad5SJay Sternberg dev->q_depth = result; 229888d356caSChristoph Hellwig dev->ctrl.sqsize = result - 1; 229988d356caSChristoph Hellwig } else { 23000f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 230157dacad5SJay Sternberg } 230288d356caSChristoph Hellwig } 230357dacad5SJay Sternberg 230457dacad5SJay Sternberg do { 230597f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 230697f6ef64SXu Yu result = nvme_remap_bar(dev, size); 230797f6ef64SXu Yu if (!result) 230857dacad5SJay Sternberg break; 2309e4b9852aSCasey Chen if (!--nr_io_queues) { 2310e4b9852aSCasey Chen result = -ENOMEM; 2311e4b9852aSCasey Chen goto out_unlock; 2312e4b9852aSCasey Chen } 231357dacad5SJay Sternberg } while (1); 231457dacad5SJay Sternberg adminq->q_db = dev->dbs; 231557dacad5SJay Sternberg 23168fae268bSKeith Busch retry: 231757dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2318e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23190ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 232057dacad5SJay Sternberg 232157dacad5SJay Sternberg /* 232257dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 232357dacad5SJay Sternberg * setting up the full range we need. 232457dacad5SJay Sternberg */ 2325dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 23263b6592f7SJens Axboe 23273b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2328e4b9852aSCasey Chen if (result <= 0) { 2329e4b9852aSCasey Chen result = -EIO; 2330e4b9852aSCasey Chen goto out_unlock; 2331e4b9852aSCasey Chen } 23323b6592f7SJens Axboe 233322b55601SKeith Busch dev->num_vecs = result; 23344b04cc6aSJens Axboe result = max(result - 1, 1); 2335e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 233657dacad5SJay Sternberg 233757dacad5SJay Sternberg /* 233857dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 233957dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 234057dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 234157dacad5SJay Sternberg * number of interrupts. 234257dacad5SJay Sternberg */ 2343dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 23447c349ddeSKeith Busch if (result) 2345e4b9852aSCasey Chen goto out_unlock; 23464e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2347e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 23488fae268bSKeith Busch 23498fae268bSKeith Busch result = nvme_create_io_queues(dev); 23508fae268bSKeith Busch if (result || dev->online_queues < 2) 23518fae268bSKeith Busch return result; 23528fae268bSKeith Busch 23538fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 23548fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 23557d879c90SChristoph Hellwig nvme_delete_io_queues(dev); 2356e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2357e4b9852aSCasey Chen if (result) 2358e4b9852aSCasey Chen return result; 23598fae268bSKeith Busch nvme_suspend_io_queues(dev); 23608fae268bSKeith Busch goto retry; 23618fae268bSKeith Busch } 23628fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 23638fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 23648fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 23658fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 23668fae268bSKeith Busch return 0; 2367e4b9852aSCasey Chen out_unlock: 2368e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2369e4b9852aSCasey Chen return result; 237057dacad5SJay Sternberg } 237157dacad5SJay Sternberg 2372de671d61SJens Axboe static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2373de671d61SJens Axboe blk_status_t error) 2374db3cbfffSKeith Busch { 2375db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2376db3cbfffSKeith Busch 2377db3cbfffSKeith Busch blk_mq_free_request(req); 2378d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2379de671d61SJens Axboe return RQ_END_IO_NONE; 2380db3cbfffSKeith Busch } 2381db3cbfffSKeith Busch 2382de671d61SJens Axboe static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2383de671d61SJens Axboe blk_status_t error) 2384db3cbfffSKeith Busch { 2385db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2386db3cbfffSKeith Busch 2387d1ed6aa1SChristoph Hellwig if (error) 2388d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2389db3cbfffSKeith Busch 2390de671d61SJens Axboe return nvme_del_queue_end(req, error); 2391db3cbfffSKeith Busch } 2392db3cbfffSKeith Busch 2393db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2394db3cbfffSKeith Busch { 2395db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2396db3cbfffSKeith Busch struct request *req; 2397f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2398db3cbfffSKeith Busch 2399db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2400db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2401db3cbfffSKeith Busch 2402e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2403db3cbfffSKeith Busch if (IS_ERR(req)) 2404db3cbfffSKeith Busch return PTR_ERR(req); 2405e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2406db3cbfffSKeith Busch 2407e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2408e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2409e2e53086SChristoph Hellwig else 2410e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2411db3cbfffSKeith Busch req->end_io_data = nvmeq; 2412db3cbfffSKeith Busch 2413d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2414e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2415db3cbfffSKeith Busch return 0; 2416db3cbfffSKeith Busch } 2417db3cbfffSKeith Busch 24187d879c90SChristoph Hellwig static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode) 2419db3cbfffSKeith Busch { 24205271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2421db3cbfffSKeith Busch unsigned long timeout; 2422db3cbfffSKeith Busch 2423db3cbfffSKeith Busch retry: 2424dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24255271edd4SChristoph Hellwig while (nr_queues > 0) { 24265271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2427db3cbfffSKeith Busch break; 24285271edd4SChristoph Hellwig nr_queues--; 24295271edd4SChristoph Hellwig sent++; 24305271edd4SChristoph Hellwig } 2431d1ed6aa1SChristoph Hellwig while (sent) { 2432d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2433d1ed6aa1SChristoph Hellwig 2434d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 24355271edd4SChristoph Hellwig timeout); 2436db3cbfffSKeith Busch if (timeout == 0) 24375271edd4SChristoph Hellwig return false; 2438d1ed6aa1SChristoph Hellwig 2439d1ed6aa1SChristoph Hellwig sent--; 24405271edd4SChristoph Hellwig if (nr_queues) 2441db3cbfffSKeith Busch goto retry; 2442db3cbfffSKeith Busch } 24435271edd4SChristoph Hellwig return true; 2444db3cbfffSKeith Busch } 2445db3cbfffSKeith Busch 24467d879c90SChristoph Hellwig static void nvme_delete_io_queues(struct nvme_dev *dev) 244757dacad5SJay Sternberg { 24487d879c90SChristoph Hellwig if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq)) 24497d879c90SChristoph Hellwig __nvme_delete_io_queues(dev, nvme_admin_delete_cq); 24502b1b7e78SJianchao Wang } 24517d879c90SChristoph Hellwig 24520da7feaaSChristoph Hellwig static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev) 245357dacad5SJay Sternberg { 245457dacad5SJay Sternberg if (dev->io_queues[HCTX_TYPE_POLL]) 24550da7feaaSChristoph Hellwig return 3; 24560da7feaaSChristoph Hellwig if (dev->io_queues[HCTX_TYPE_READ]) 24570da7feaaSChristoph Hellwig return 2; 24580da7feaaSChristoph Hellwig return 1; 245957dacad5SJay Sternberg } 2460949928c1SKeith Busch 24612455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 24622455a4b7SChristoph Hellwig { 24632455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 24642455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 24652455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 246657dacad5SJay Sternberg } 246757dacad5SJay Sternberg 2468b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 246957dacad5SJay Sternberg { 2470b00a726aSKeith Busch int result = -ENOMEM; 247157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 247257dacad5SJay Sternberg 247357dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 247457dacad5SJay Sternberg return result; 247557dacad5SJay Sternberg 247657dacad5SJay Sternberg pci_set_master(pdev); 247757dacad5SJay Sternberg 24787a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 247957dacad5SJay Sternberg result = -ENODEV; 2480b00a726aSKeith Busch goto disable; 248157dacad5SJay Sternberg } 248257dacad5SJay Sternberg 248357dacad5SJay Sternberg /* 2484a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2485a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2486a5229050SKeith Busch * adjust this later. 248757dacad5SJay Sternberg */ 2488dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2489dca51e78SChristoph Hellwig if (result < 0) 249009113abfSTong Zhang goto disable; 249157dacad5SJay Sternberg 249220d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 24937a67cbeaSChristoph Hellwig 24947442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2495b27c1e68Sweiping zhang io_queue_depth); 249620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 24977a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 24981f390c1fSStephan Günther 24991f390c1fSStephan Günther /* 250066341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 250166341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 250266341331SBenjamin Herrenschmidt * so we don't bother updating it here. 250366341331SBenjamin Herrenschmidt */ 250466341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 250566341331SBenjamin Herrenschmidt dev->io_sqes = 7; 250666341331SBenjamin Herrenschmidt else 2507c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 25081f390c1fSStephan Günther 25091f390c1fSStephan Günther /* 25101f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 25111f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 25121f390c1fSStephan Günther */ 25131f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 25141f390c1fSStephan Günther dev->q_depth = 2; 25159bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 25169bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 25171f390c1fSStephan Günther dev->q_depth); 2518d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2519d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 252020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2521d554b5e1SMartin K. Petersen dev->q_depth = 64; 2522d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2523d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 25241f390c1fSStephan Günther } 25251f390c1fSStephan Günther 2526d38e9f04SBenjamin Herrenschmidt /* 2527d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2528d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2529d38e9f04SBenjamin Herrenschmidt */ 2530d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2531d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2532d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2533d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2534d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2535d38e9f04SBenjamin Herrenschmidt } 253688d356caSChristoph Hellwig dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2537d38e9f04SBenjamin Herrenschmidt 2538f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2539202021c1SStephen Bates 2540a0a3408eSKeith Busch pci_save_state(pdev); 2541a6ee7f19SChristoph Hellwig 254209113abfSTong Zhang result = nvme_pci_configure_admin_queue(dev); 254309113abfSTong Zhang if (result) 254409113abfSTong Zhang goto free_irq; 254509113abfSTong Zhang return result; 254657dacad5SJay Sternberg 254709113abfSTong Zhang free_irq: 254809113abfSTong Zhang pci_free_irq_vectors(pdev); 254957dacad5SJay Sternberg disable: 255057dacad5SJay Sternberg pci_disable_device(pdev); 255157dacad5SJay Sternberg return result; 255257dacad5SJay Sternberg } 255357dacad5SJay Sternberg 255457dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 255557dacad5SJay Sternberg { 2556b00a726aSKeith Busch if (dev->bar) 2557b00a726aSKeith Busch iounmap(dev->bar); 2558a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2559b00a726aSKeith Busch } 2560b00a726aSKeith Busch 256168e81ebaSChristoph Hellwig static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev) 2562b00a726aSKeith Busch { 256357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 2564081f5e75SKeith Busch u32 csts; 256557dacad5SJay Sternberg 256668e81ebaSChristoph Hellwig if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev)) 256768e81ebaSChristoph Hellwig return true; 256868e81ebaSChristoph Hellwig if (pdev->error_state != pci_channel_io_normal) 256968e81ebaSChristoph Hellwig return true; 257057dacad5SJay Sternberg 257168e81ebaSChristoph Hellwig csts = readl(dev->bar + NVME_REG_CSTS); 257268e81ebaSChristoph Hellwig return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY); 2573a0a3408eSKeith Busch } 257457dacad5SJay Sternberg 2575a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 257657dacad5SJay Sternberg { 2577302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 257868e81ebaSChristoph Hellwig bool dead; 257957dacad5SJay Sternberg 258077bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 258168e81ebaSChristoph Hellwig dead = nvme_pci_ctrl_is_dead(dev); 2582ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2583e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 258468e81ebaSChristoph Hellwig if (pci_is_enabled(pdev)) 2585302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2586302ad8ccSKeith Busch /* 258768e81ebaSChristoph Hellwig * Give the controller a chance to complete all entered requests 258868e81ebaSChristoph Hellwig * if doing a safe shutdown. 2589302ad8ccSKeith Busch */ 259068e81ebaSChristoph Hellwig if (!dead && shutdown) 2591302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 259268e81ebaSChristoph Hellwig } 259387ad72a5SChristoph Hellwig 25949f27bd70SChristoph Hellwig nvme_quiesce_io_queues(&dev->ctrl); 25959a915a5bSJianchao Wang 259664ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 25977d879c90SChristoph Hellwig nvme_delete_io_queues(dev); 259847d42d22SChristoph Hellwig nvme_disable_ctrl(&dev->ctrl, shutdown); 259947d42d22SChristoph Hellwig nvme_poll_irqdisable(&dev->queues[0]); 260057dacad5SJay Sternberg } 26018fae268bSKeith Busch nvme_suspend_io_queues(dev); 260210981f23SChristoph Hellwig nvme_suspend_queue(dev, 0); 2603c80767f7SChristoph Hellwig pci_free_irq_vectors(pdev); 26041ad11eafSBjorn Helgaas if (pci_is_enabled(pdev)) 2605c80767f7SChristoph Hellwig pci_disable_device(pdev); 2606fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 260757dacad5SJay Sternberg 26081fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 26091fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2610302ad8ccSKeith Busch 2611302ad8ccSKeith Busch /* 2612302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2613302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2614302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2615302ad8ccSKeith Busch */ 2616c8e9e9b7SKeith Busch if (shutdown) { 26179f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2618c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 26199f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 2620c8e9e9b7SKeith Busch } 262177bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 262257dacad5SJay Sternberg } 262357dacad5SJay Sternberg 2624c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2625c1ac9a4bSKeith Busch { 2626c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2627c1ac9a4bSKeith Busch return -EBUSY; 2628c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2629c1ac9a4bSKeith Busch return 0; 2630c1ac9a4bSKeith Busch } 2631c1ac9a4bSKeith Busch 263257dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 263357dacad5SJay Sternberg { 263457dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2635c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2636c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 263757dacad5SJay Sternberg if (!dev->prp_page_pool) 263857dacad5SJay Sternberg return -ENOMEM; 263957dacad5SJay Sternberg 264057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 264157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 264257dacad5SJay Sternberg 256, 256, 0); 264357dacad5SJay Sternberg if (!dev->prp_small_pool) { 264457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 264557dacad5SJay Sternberg return -ENOMEM; 264657dacad5SJay Sternberg } 264757dacad5SJay Sternberg return 0; 264857dacad5SJay Sternberg } 264957dacad5SJay Sternberg 265057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 265157dacad5SJay Sternberg { 265257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 265357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 265457dacad5SJay Sternberg } 265557dacad5SJay Sternberg 2656081a7d95SChristoph Hellwig static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2657081a7d95SChristoph Hellwig { 26587846c1b5SKeith Busch size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS; 2659081a7d95SChristoph Hellwig 2660081a7d95SChristoph Hellwig dev->iod_mempool = mempool_create_node(1, 2661081a7d95SChristoph Hellwig mempool_kmalloc, mempool_kfree, 2662081a7d95SChristoph Hellwig (void *)alloc_size, GFP_KERNEL, 2663081a7d95SChristoph Hellwig dev_to_node(dev->dev)); 2664081a7d95SChristoph Hellwig if (!dev->iod_mempool) 2665081a7d95SChristoph Hellwig return -ENOMEM; 2666081a7d95SChristoph Hellwig return 0; 2667081a7d95SChristoph Hellwig } 2668081a7d95SChristoph Hellwig 2669770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2670770597ecSKeith Busch { 2671770597ecSKeith Busch if (dev->tagset.tags) 26720da7feaaSChristoph Hellwig nvme_remove_io_tag_set(&dev->ctrl); 2673770597ecSKeith Busch dev->ctrl.tagset = NULL; 2674770597ecSKeith Busch } 2675770597ecSKeith Busch 26762e87570bSChristoph Hellwig /* pairs with nvme_pci_alloc_dev */ 26771673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 267857dacad5SJay Sternberg { 26791673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 268057dacad5SJay Sternberg 2681770597ecSKeith Busch nvme_free_tagset(dev); 2682253fd4acSIsrael Rukshin put_device(dev->dev); 2683253fd4acSIsrael Rukshin kfree(dev->queues); 268457dacad5SJay Sternberg kfree(dev); 268557dacad5SJay Sternberg } 268657dacad5SJay Sternberg 2687fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 268857dacad5SJay Sternberg { 2689d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2690d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2691a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2692e71afda4SChaitanya Kulkarni int result; 269357dacad5SJay Sternberg 26947764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 26957764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 26967764656bSZhihao Cheng dev->ctrl.state); 26974e69d4daSKeith Busch result = -ENODEV; 26984e69d4daSKeith Busch goto out; 2699e71afda4SChaitanya Kulkarni } 2700fd634f41SChristoph Hellwig 2701fd634f41SChristoph Hellwig /* 2702fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2703fd634f41SChristoph Hellwig * moving on. 2704fd634f41SChristoph Hellwig */ 2705b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2706a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2707d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2708fd634f41SChristoph Hellwig 27095c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2710b00a726aSKeith Busch result = nvme_pci_enable(dev); 271157dacad5SJay Sternberg if (result) 27124726bcf3SKeith Busch goto out_unlock; 27139f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 27145c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 27155c959d73SKeith Busch 27165c959d73SKeith Busch /* 27175c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 27185c959d73SKeith Busch * initializing procedure here. 27195c959d73SKeith Busch */ 27205c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 27215c959d73SKeith Busch dev_warn(dev->ctrl.device, 27225c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2723cee6c269SMinwoo Im result = -EBUSY; 27245c959d73SKeith Busch goto out; 27255c959d73SKeith Busch } 2726943e942eSJens Axboe 272794cc781fSChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2728ce4541f4SChristoph Hellwig if (result) 2729f58944e2SKeith Busch goto out; 2730ce4541f4SChristoph Hellwig 273165a54646SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 2732a98e58e5SScott Bauer 27339620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 27349620cfbaSChristoph Hellwig if (result < 0) 27359620cfbaSChristoph Hellwig goto out; 273687ad72a5SChristoph Hellwig 273757dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 273857dacad5SJay Sternberg if (result) 2739f58944e2SKeith Busch goto out; 274057dacad5SJay Sternberg 274121f033f7SKeith Busch /* 27420ffc7e98SChristoph Hellwig * Freeze and update the number of I/O queues as thos might have 2743eac3ef26SChristoph Hellwig * changed. If there are no I/O queues left after this reset, keep the 2744eac3ef26SChristoph Hellwig * controller around but remove all namespaces. 274557dacad5SJay Sternberg */ 27460ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 27479f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2748302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 27492455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 27502455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2751302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 27520ffc7e98SChristoph Hellwig } else { 27530ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues lost\n"); 2754cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 27559f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 27560ffc7e98SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 27570ffc7e98SChristoph Hellwig nvme_free_tagset(dev); 275857dacad5SJay Sternberg } 275957dacad5SJay Sternberg 27602b1b7e78SJianchao Wang /* 27612b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 27622b1b7e78SJianchao Wang * recovery. 27632b1b7e78SJianchao Wang */ 27645d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 27652b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 27665d02a5c1SKeith Busch "failed to mark controller live state\n"); 2767e71afda4SChaitanya Kulkarni result = -ENODEV; 2768bb8d261eSChristoph Hellwig goto out; 2769bb8d261eSChristoph Hellwig } 277092911a55SChristoph Hellwig 2771d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 277257dacad5SJay Sternberg return; 277357dacad5SJay Sternberg 27744726bcf3SKeith Busch out_unlock: 27754726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 277657dacad5SJay Sternberg out: 2777c7c16c5bSChristoph Hellwig /* 2778c7c16c5bSChristoph Hellwig * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2779c7c16c5bSChristoph Hellwig * may be holding this pci_dev's device lock. 2780c7c16c5bSChristoph Hellwig */ 2781c7c16c5bSChristoph Hellwig dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2782c7c16c5bSChristoph Hellwig result); 2783c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2784c7c16c5bSChristoph Hellwig nvme_dev_disable(dev, true); 2785a2b5d544SKeith Busch nvme_sync_queues(&dev->ctrl); 2786c7c16c5bSChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 27872ab4e5f4SKeith Busch nvme_unquiesce_io_queues(&dev->ctrl); 2788c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 278957dacad5SJay Sternberg } 279057dacad5SJay Sternberg 27911c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 279257dacad5SJay Sternberg { 27931c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 27941c63dc66SChristoph Hellwig return 0; 279557dacad5SJay Sternberg } 27961c63dc66SChristoph Hellwig 27975fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 27985fd4ce1bSChristoph Hellwig { 27995fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 28005fd4ce1bSChristoph Hellwig return 0; 28015fd4ce1bSChristoph Hellwig } 28025fd4ce1bSChristoph Hellwig 28037fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 28047fd8930fSChristoph Hellwig { 28053a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 28067fd8930fSChristoph Hellwig return 0; 28077fd8930fSChristoph Hellwig } 28087fd8930fSChristoph Hellwig 280997c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 281097c12223SKeith Busch { 281197c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 281297c12223SKeith Busch 28132db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 281497c12223SKeith Busch } 281597c12223SKeith Busch 28162f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 28172f0dad17SKeith Busch { 28182f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 28192f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 28202f0dad17SKeith Busch 28212f0dad17SKeith Busch dev_err(ctrl->device, 28222f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 28232f0dad17SKeith Busch pdev->vendor, pdev->device, 28242f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 28252f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 28262f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 28272f0dad17SKeith Busch subsys->firmware_rev); 28282f0dad17SKeith Busch } 28292f0dad17SKeith Busch 28302f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 28312f859441SLogan Gunthorpe { 28322f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 28332f859441SLogan Gunthorpe 28342f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 28352f859441SLogan Gunthorpe } 28362f859441SLogan Gunthorpe 28371c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 28381a353d85SMing Lin .name = "pcie", 2839e439bb12SSagi Grimberg .module = THIS_MODULE, 28402f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 284186adbf0cSChristoph Hellwig .dev_attr_groups = nvme_pci_dev_attr_groups, 28421c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 28435fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 28447fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 28451673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2846f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 284797c12223SKeith Busch .get_address = nvme_pci_get_address, 28482f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 28492f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 28501c63dc66SChristoph Hellwig }; 285157dacad5SJay Sternberg 2852b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2853b00a726aSKeith Busch { 2854b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2855b00a726aSKeith Busch 2856a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2857b00a726aSKeith Busch return -ENODEV; 2858b00a726aSKeith Busch 285997f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2860b00a726aSKeith Busch goto release; 2861b00a726aSKeith Busch 2862b00a726aSKeith Busch return 0; 2863b00a726aSKeith Busch release: 2864a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2865b00a726aSKeith Busch return -ENODEV; 2866b00a726aSKeith Busch } 2867b00a726aSKeith Busch 28688427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2869ff5350a8SAndy Lutomirski { 2870ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2871ff5350a8SAndy Lutomirski /* 2872ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2873ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2874ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2875ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2876ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2877ff5350a8SAndy Lutomirski * laptops. 2878ff5350a8SAndy Lutomirski */ 2879ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2880ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2881ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2882ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 28838427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 28848427bbc2SKai-Heng Feng /* 28858427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2886467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2887467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2888467c77d4SJarosław Janik * ASUS PRIME Z370-A 28898427bbc2SKai-Heng Feng */ 28908427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2891467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2892467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 28938427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 28941fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 28951fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 28961fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 28971fae37acSShyjumon N /* 28981fae37acSShyjumon N * Forcing to use host managed nvme power settings for 28991fae37acSShyjumon N * lowest idle power with quick resume latency on 29001fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 29011fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 29021fae37acSShyjumon N */ 29031fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 29041fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 29051fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2906ff5350a8SAndy Lutomirski } 2907ff5350a8SAndy Lutomirski 2908ff5350a8SAndy Lutomirski return 0; 2909ff5350a8SAndy Lutomirski } 2910ff5350a8SAndy Lutomirski 29112e87570bSChristoph Hellwig static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 29122e87570bSChristoph Hellwig const struct pci_device_id *id) 291318119775SKeith Busch { 2914ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 29152e87570bSChristoph Hellwig int node = dev_to_node(&pdev->dev); 29162e87570bSChristoph Hellwig struct nvme_dev *dev; 29172e87570bSChristoph Hellwig int ret = -ENOMEM; 291857dacad5SJay Sternberg 291957dacad5SJay Sternberg if (node == NUMA_NO_NODE) 29202fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 292157dacad5SJay Sternberg 292257dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 292357dacad5SJay Sternberg if (!dev) 2924dc785d69SIrvin Cote return ERR_PTR(-ENOMEM); 29252e87570bSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 29262e87570bSChristoph Hellwig mutex_init(&dev->shutdown_lock); 2927147b27e4SSagi Grimberg 29282a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 29292a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 29302a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 29312a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 29322a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 293357dacad5SJay Sternberg if (!dev->queues) 29342e87570bSChristoph Hellwig goto out_free_dev; 293557dacad5SJay Sternberg 293657dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 2937f3ca80fcSChristoph Hellwig 29388427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 29392744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2940df4f9bc4SDavid E. Box /* 2941df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 2942df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 2943df4f9bc4SDavid E. Box */ 2944df4f9bc4SDavid E. Box dev_info(&pdev->dev, 2945df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 2946df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2947df4f9bc4SDavid E. Box } 29482e87570bSChristoph Hellwig ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 29492e87570bSChristoph Hellwig quirks); 29502e87570bSChristoph Hellwig if (ret) 29512e87570bSChristoph Hellwig goto out_put_device; 29523f30a79cSChristoph Hellwig 2953924bd96eSChristoph Hellwig if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 2954924bd96eSChristoph Hellwig dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)); 2955924bd96eSChristoph Hellwig else 2956924bd96eSChristoph Hellwig dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 29573f30a79cSChristoph Hellwig dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 29583f30a79cSChristoph Hellwig dma_set_max_seg_size(&pdev->dev, 0xffffffff); 2959df4f9bc4SDavid E. Box 2960943e942eSJens Axboe /* 29613f30a79cSChristoph Hellwig * Limit the max command size to prevent iod->sg allocations going 29623f30a79cSChristoph Hellwig * over a single page. 2963943e942eSJens Axboe */ 29643f30a79cSChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 29653710e2b0SAdrian Huang NVME_MAX_KB_SZ << 1, dma_opt_mapping_size(&pdev->dev) >> 9); 29663f30a79cSChristoph Hellwig dev->ctrl.max_segments = NVME_MAX_SEGS; 2967943e942eSJens Axboe 29683f30a79cSChristoph Hellwig /* 29693f30a79cSChristoph Hellwig * There is no support for SGLs for metadata (yet), so we are limited to 29703f30a79cSChristoph Hellwig * a single integrity segment for the separate metadata pointer. 29713f30a79cSChristoph Hellwig */ 29723f30a79cSChristoph Hellwig dev->ctrl.max_integrity_segments = 1; 29732e87570bSChristoph Hellwig return dev; 29742e87570bSChristoph Hellwig 29752e87570bSChristoph Hellwig out_put_device: 29762e87570bSChristoph Hellwig put_device(dev->dev); 29772e87570bSChristoph Hellwig kfree(dev->queues); 29782e87570bSChristoph Hellwig out_free_dev: 29792e87570bSChristoph Hellwig kfree(dev); 29802e87570bSChristoph Hellwig return ERR_PTR(ret); 2981943e942eSJens Axboe } 2982943e942eSJens Axboe 29832e87570bSChristoph Hellwig static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 29842e87570bSChristoph Hellwig { 29852e87570bSChristoph Hellwig struct nvme_dev *dev; 29862e87570bSChristoph Hellwig int result = -ENOMEM; 29872e87570bSChristoph Hellwig 29882e87570bSChristoph Hellwig dev = nvme_pci_alloc_dev(pdev, id); 2989dc785d69SIrvin Cote if (IS_ERR(dev)) 2990dc785d69SIrvin Cote return PTR_ERR(dev); 29912e87570bSChristoph Hellwig 29922e87570bSChristoph Hellwig result = nvme_dev_map(dev); 2993b6e44b4cSKeith Busch if (result) 29942e87570bSChristoph Hellwig goto out_uninit_ctrl; 29952e87570bSChristoph Hellwig 29962e87570bSChristoph Hellwig result = nvme_setup_prp_pools(dev); 29972e87570bSChristoph Hellwig if (result) 29982e87570bSChristoph Hellwig goto out_dev_unmap; 299957dacad5SJay Sternberg 3000081a7d95SChristoph Hellwig result = nvme_pci_alloc_iod_mempool(dev); 3001081a7d95SChristoph Hellwig if (result) 30022e87570bSChristoph Hellwig goto out_release_prp_pools; 3003b6e44b4cSKeith Busch 300457dacad5SJay Sternberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 300557dacad5SJay Sternberg 3006eac3ef26SChristoph Hellwig result = nvme_pci_enable(dev); 3007eac3ef26SChristoph Hellwig if (result) 3008eac3ef26SChristoph Hellwig goto out_release_iod_mempool; 300957dacad5SJay Sternberg 30100da7feaaSChristoph Hellwig result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset, 30110da7feaaSChristoph Hellwig &nvme_mq_admin_ops, sizeof(struct nvme_iod)); 3012eac3ef26SChristoph Hellwig if (result) 3013eac3ef26SChristoph Hellwig goto out_disable; 3014eac3ef26SChristoph Hellwig 3015eac3ef26SChristoph Hellwig /* 3016eac3ef26SChristoph Hellwig * Mark the controller as connecting before sending admin commands to 3017eac3ef26SChristoph Hellwig * allow the timeout handler to do the right thing. 3018eac3ef26SChristoph Hellwig */ 3019eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3020eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3021eac3ef26SChristoph Hellwig "failed to mark controller CONNECTING\n"); 3022eac3ef26SChristoph Hellwig result = -EBUSY; 3023eac3ef26SChristoph Hellwig goto out_disable; 3024eac3ef26SChristoph Hellwig } 3025eac3ef26SChristoph Hellwig 3026eac3ef26SChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, false); 3027eac3ef26SChristoph Hellwig if (result) 3028eac3ef26SChristoph Hellwig goto out_disable; 3029eac3ef26SChristoph Hellwig 3030eac3ef26SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 3031eac3ef26SChristoph Hellwig 3032eac3ef26SChristoph Hellwig result = nvme_setup_host_mem(dev); 3033eac3ef26SChristoph Hellwig if (result < 0) 3034eac3ef26SChristoph Hellwig goto out_disable; 3035eac3ef26SChristoph Hellwig 3036eac3ef26SChristoph Hellwig result = nvme_setup_io_queues(dev); 3037eac3ef26SChristoph Hellwig if (result) 3038eac3ef26SChristoph Hellwig goto out_disable; 3039eac3ef26SChristoph Hellwig 3040eac3ef26SChristoph Hellwig if (dev->online_queues > 1) { 30410da7feaaSChristoph Hellwig nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, 30420da7feaaSChristoph Hellwig nvme_pci_nr_maps(dev), sizeof(struct nvme_iod)); 3043eac3ef26SChristoph Hellwig nvme_dbbuf_set(dev); 3044eac3ef26SChristoph Hellwig } 3045eac3ef26SChristoph Hellwig 30460da7feaaSChristoph Hellwig if (!dev->ctrl.tagset) 30470da7feaaSChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues not created\n"); 30480da7feaaSChristoph Hellwig 3049eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3050eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3051eac3ef26SChristoph Hellwig "failed to mark controller live state\n"); 3052eac3ef26SChristoph Hellwig result = -ENODEV; 3053eac3ef26SChristoph Hellwig goto out_disable; 3054eac3ef26SChristoph Hellwig } 3055eac3ef26SChristoph Hellwig 30562e87570bSChristoph Hellwig pci_set_drvdata(pdev, dev); 305757dacad5SJay Sternberg 3058eac3ef26SChristoph Hellwig nvme_start_ctrl(&dev->ctrl); 3059eac3ef26SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 30605a5754a4SKeith Busch flush_work(&dev->ctrl.scan_work); 306157dacad5SJay Sternberg return 0; 306257dacad5SJay Sternberg 3063eac3ef26SChristoph Hellwig out_disable: 3064eac3ef26SChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3065eac3ef26SChristoph Hellwig nvme_dev_disable(dev, true); 3066eac3ef26SChristoph Hellwig nvme_free_host_mem(dev); 3067eac3ef26SChristoph Hellwig nvme_dev_remove_admin(dev); 3068eac3ef26SChristoph Hellwig nvme_dbbuf_dma_free(dev); 3069eac3ef26SChristoph Hellwig nvme_free_queues(dev, 0); 3070eac3ef26SChristoph Hellwig out_release_iod_mempool: 3071b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 30722e87570bSChristoph Hellwig out_release_prp_pools: 307357dacad5SJay Sternberg nvme_release_prp_pools(dev); 30742e87570bSChristoph Hellwig out_dev_unmap: 307557dacad5SJay Sternberg nvme_dev_unmap(dev); 30762e87570bSChristoph Hellwig out_uninit_ctrl: 30772e87570bSChristoph Hellwig nvme_uninit_ctrl(&dev->ctrl); 3078a61d2655SIrvin Cote nvme_put_ctrl(&dev->ctrl); 307957dacad5SJay Sternberg return result; 308057dacad5SJay Sternberg } 308157dacad5SJay Sternberg 3082775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 308357dacad5SJay Sternberg { 308457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3085c1ac9a4bSKeith Busch 3086c1ac9a4bSKeith Busch /* 3087c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3088c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3089c1ac9a4bSKeith Busch * with ->remove(). 3090c1ac9a4bSKeith Busch */ 3091c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3092c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3093775755edSChristoph Hellwig } 309457dacad5SJay Sternberg 3095775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3096775755edSChristoph Hellwig { 3097f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3098c1ac9a4bSKeith Busch 3099c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3100c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 310157dacad5SJay Sternberg } 310257dacad5SJay Sternberg 310357dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 310457dacad5SJay Sternberg { 310557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 31064e523547SBaolin Wang 3107c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 310857dacad5SJay Sternberg } 310957dacad5SJay Sternberg 3110f58944e2SKeith Busch /* 3111f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3112f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3113f58944e2SKeith Busch * order to proceed. 3114f58944e2SKeith Busch */ 311557dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 311657dacad5SJay Sternberg { 311757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 311857dacad5SJay Sternberg 3119bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 312057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 31210ff9d4e1SKeith Busch 31226db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 31230ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 31241d39e692SKeith Busch nvme_dev_disable(dev, true); 31256db28edaSKeith Busch } 31260ff9d4e1SKeith Busch 3127d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3128d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3129d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3130a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 313187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 313257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 3133c11b7716SChristoph Hellwig nvme_dbbuf_dma_free(dev); 313457dacad5SJay Sternberg nvme_free_queues(dev, 0); 3135c11b7716SChristoph Hellwig mempool_destroy(dev->iod_mempool); 313657dacad5SJay Sternberg nvme_release_prp_pools(dev); 3137b00a726aSKeith Busch nvme_dev_unmap(dev); 3138726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 313957dacad5SJay Sternberg } 314057dacad5SJay Sternberg 314157dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3142d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3143d916b1beSKeith Busch { 3144d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3145d916b1beSKeith Busch } 3146d916b1beSKeith Busch 3147d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3148d916b1beSKeith Busch { 3149d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3150d916b1beSKeith Busch } 3151d916b1beSKeith Busch 3152d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3153d916b1beSKeith Busch { 3154d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3155d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3156d916b1beSKeith Busch 31574eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3158d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3159e5ad96f3SKeith Busch goto reset; 3160e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3161e5ad96f3SKeith Busch goto reset; 3162e5ad96f3SKeith Busch 3163d916b1beSKeith Busch return 0; 3164e5ad96f3SKeith Busch reset: 3165e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3166d916b1beSKeith Busch } 3167d916b1beSKeith Busch 316857dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 316957dacad5SJay Sternberg { 317057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 317157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3172d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3173d916b1beSKeith Busch int ret = -EBUSY; 3174d916b1beSKeith Busch 31754eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 31764eaefe8cSRafael J. Wysocki 3177d916b1beSKeith Busch /* 3178d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3179d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3180d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3181d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3182d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3183d916b1beSKeith Busch * device fully. 31844eaefe8cSRafael J. Wysocki * 31854eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 31864eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 31874eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 31884eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3189d916b1beSKeith Busch */ 31904eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3191cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3192c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3193c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3194d916b1beSKeith Busch 3195d916b1beSKeith Busch nvme_start_freeze(ctrl); 3196d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3197d916b1beSKeith Busch nvme_sync_queues(ctrl); 3198d916b1beSKeith Busch 31995d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3200d916b1beSKeith Busch goto unfreeze; 3201d916b1beSKeith Busch 3202e5ad96f3SKeith Busch /* 3203e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3204e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3205e5ad96f3SKeith Busch * non-operational power state. 3206e5ad96f3SKeith Busch */ 3207e5ad96f3SKeith Busch if (ndev->hmb) { 3208e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3209e5ad96f3SKeith Busch if (ret < 0) 3210e5ad96f3SKeith Busch goto unfreeze; 3211e5ad96f3SKeith Busch } 3212e5ad96f3SKeith Busch 3213d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3214d916b1beSKeith Busch if (ret < 0) 3215d916b1beSKeith Busch goto unfreeze; 3216d916b1beSKeith Busch 32177cbb5c6fSMario Limonciello /* 32187cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 32197cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 32207cbb5c6fSMario Limonciello * want pci interfering. 32217cbb5c6fSMario Limonciello */ 32227cbb5c6fSMario Limonciello pci_save_state(pdev); 32237cbb5c6fSMario Limonciello 3224d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3225d916b1beSKeith Busch if (ret < 0) 3226d916b1beSKeith Busch goto unfreeze; 3227d916b1beSKeith Busch 3228d916b1beSKeith Busch if (ret) { 32297cbb5c6fSMario Limonciello /* discard the saved state */ 32307cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 32317cbb5c6fSMario Limonciello 3232d916b1beSKeith Busch /* 3233d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 323405d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3235d916b1beSKeith Busch */ 3236c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3237d916b1beSKeith Busch ctrl->npss = 0; 3238d916b1beSKeith Busch } 3239d916b1beSKeith Busch unfreeze: 3240d916b1beSKeith Busch nvme_unfreeze(ctrl); 3241d916b1beSKeith Busch return ret; 3242d916b1beSKeith Busch } 3243d916b1beSKeith Busch 3244d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3245d916b1beSKeith Busch { 3246d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 32474e523547SBaolin Wang 3248c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 324957dacad5SJay Sternberg } 325057dacad5SJay Sternberg 3251d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 325257dacad5SJay Sternberg { 325357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 325457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 325557dacad5SJay Sternberg 3256c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 325757dacad5SJay Sternberg } 325857dacad5SJay Sternberg 325921774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3260d916b1beSKeith Busch .suspend = nvme_suspend, 3261d916b1beSKeith Busch .resume = nvme_resume, 3262d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3263d916b1beSKeith Busch .thaw = nvme_simple_resume, 3264d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3265d916b1beSKeith Busch .restore = nvme_simple_resume, 3266d916b1beSKeith Busch }; 3267d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 326857dacad5SJay Sternberg 3269a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3270a0a3408eSKeith Busch pci_channel_state_t state) 3271a0a3408eSKeith Busch { 3272a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3273a0a3408eSKeith Busch 3274a0a3408eSKeith Busch /* 3275a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3276a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3277a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3278a0a3408eSKeith Busch */ 3279a0a3408eSKeith Busch switch (state) { 3280a0a3408eSKeith Busch case pci_channel_io_normal: 3281a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3282a0a3408eSKeith Busch case pci_channel_io_frozen: 3283d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3284d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 328571a5bb15SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) { 328671a5bb15SKeith Busch nvme_dev_disable(dev, true); 328771a5bb15SKeith Busch return PCI_ERS_RESULT_DISCONNECT; 328871a5bb15SKeith Busch } 3289a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3290a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3291a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3292d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3293d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3294a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3295a0a3408eSKeith Busch } 3296a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3297a0a3408eSKeith Busch } 3298a0a3408eSKeith Busch 3299a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3300a0a3408eSKeith Busch { 3301a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3302a0a3408eSKeith Busch 33031b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3304a0a3408eSKeith Busch pci_restore_state(pdev); 330571a5bb15SKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 330671a5bb15SKeith Busch nvme_unquiesce_io_queues(&dev->ctrl); 3307a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3308a0a3408eSKeith Busch } 3309a0a3408eSKeith Busch 3310a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3311a0a3408eSKeith Busch { 331272cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 331372cd4cc2SKeith Busch 331472cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3315a0a3408eSKeith Busch } 3316a0a3408eSKeith Busch 331757dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 331857dacad5SJay Sternberg .error_detected = nvme_error_detected, 331957dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 332057dacad5SJay Sternberg .resume = nvme_error_resume, 3321775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3322775755edSChristoph Hellwig .reset_done = nvme_reset_done, 332357dacad5SJay Sternberg }; 332457dacad5SJay Sternberg 332557dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3326972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 332708095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3328e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3329972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 333099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3331e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3332972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 333399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 333425e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 333525e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3336972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3337f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3338f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 333950af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 33409abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 33416c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3342ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3343ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33446299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 33456299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3346540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 33477b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 334866dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 334966dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 335066dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 335166dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 33525bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3353c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3354c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 33550302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 33565e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 33575e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 335854adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 335954adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 33608c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 33618c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3362015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3363015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3364d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3365d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3366d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 33677ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3368abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 33697ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 33702cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 33712cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3372c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 337373029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 337473029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 3375d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3376d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3377d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3378d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33796e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 33806e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 33816e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3382e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3383e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 338408b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 33851629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 33861629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 33875f69f009SDaniel Wagner { PCI_DEVICE(0x10ec, 0x5763), /* ADATA SX6000PNP */ 33885f69f009SDaniel Wagner .driver_data = NVME_QUIRK_BOGUS_NID, }, 3389f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3390f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3391f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 339241f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 339341f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3394d5ceb4d1SBean Huo { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3395d5ceb4d1SBean Huo .driver_data = NVME_QUIRK_BOGUS_NID, }, 33965611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 33975611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3398c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3399c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 340002ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 340102ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 340289919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 340389919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 340443047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 340543047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 340643047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 340743047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3408e5bb0988SPankaj Raghav { PCI_DEVICE(0x144d, 0xa802), /* Samsung SM953 */ 3409e5bb0988SPankaj Raghav .driver_data = NVME_QUIRK_BOGUS_NID, }, 341043047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 341143047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 341243047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 341343047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3414dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3415dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3416538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3417538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3418bd375feeSHristo Venev { PCI_DEVICE(0x2646, 0x5013), /* Kingston KC3000, Kingston FURY Renegade */ 3419bd375feeSHristo Venev .driver_data = NVME_QUIRK_NO_SECONDARY_TEMP_THRESH, }, 3420ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3421ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3422ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3423ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3424ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3425ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3426ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3427ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3428ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3429ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34309630d806SElmer Miroslav Mosher Golovin { PCI_DEVICE(0x1f40, 0x1202), /* Netac Technologies Co. NV3000 NVMe SSD */ 34319630d806SElmer Miroslav Mosher Golovin .driver_data = NVME_QUIRK_BOGUS_NID, }, 34328d6e38f6STiago Dias Ferreira { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */ 34338d6e38f6STiago Dias Ferreira .driver_data = NVME_QUIRK_BOGUS_NID, }, 343470ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 343570ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3436a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3437a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3438a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3439a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3440a3a9d63dSTatsuki Sugiura { PCI_DEVICE(0x1e4B, 0x1602), /* MAXIO MAP1602 */ 3441a3a9d63dSTatsuki Sugiura .driver_data = NVME_QUIRK_BOGUS_NID, }, 34423765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 34433765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3444f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3445f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 3446d5d3c100SXi Ruoyao { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3447d5d3c100SXi Ruoyao .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 34486b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 34496b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3450d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3451d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 3452200dccd0SShyamin Ayesh { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3453200dccd0SShyamin Ayesh .driver_data = NVME_QUIRK_BOGUS_NID, }, 3454b65d44faSPhilipp Geulen { PCI_DEVICE(0x1d97, 0x1d97), /* Lexar NM620 */ 3455b65d44faSPhilipp Geulen .driver_data = NVME_QUIRK_BOGUS_NID, }, 345680b26240SAbhijit { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 34571231363aSJuraj Pecigos .driver_data = NVME_QUIRK_BOGUS_NID | 34581231363aSJuraj Pecigos NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 345974391b3eSDuy Truong { PCI_DEVICE(0x10ec, 0x5763), /* TEAMGROUP T-FORCE CARDEA ZERO Z330 SSD */ 346074391b3eSDuy Truong .driver_data = NVME_QUIRK_BOGUS_NID, }, 34611616d6c3SSagi Grimberg { PCI_DEVICE(0x1e4b, 0x1602), /* HS-SSD-FUTURE 2048G */ 34621616d6c3SSagi Grimberg .driver_data = NVME_QUIRK_BOGUS_NID, }, 346306497281SDaniel Smith { PCI_DEVICE(0x10ec, 0x5765), /* TEAMGROUP MP33 2TB SSD */ 346406497281SDaniel Smith .driver_data = NVME_QUIRK_BOGUS_NID, }, 34654bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 34664bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34674bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 34684bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34694bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 34704bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34714bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 34724bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34734bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 34744bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34754bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 34764bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 347798f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 347898f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3479124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 348066341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 348166341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3482d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3483a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3484453116a4SHector Martin NVME_QUIRK_SKIP_CID_GEN | 3485453116a4SHector Martin NVME_QUIRK_IDENTIFY_CNS }, 34860b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 348757dacad5SJay Sternberg { 0, } 348857dacad5SJay Sternberg }; 348957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 349057dacad5SJay Sternberg 349157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 349257dacad5SJay Sternberg .name = "nvme", 349357dacad5SJay Sternberg .id_table = nvme_id_table, 349457dacad5SJay Sternberg .probe = nvme_probe, 349557dacad5SJay Sternberg .remove = nvme_remove, 349657dacad5SJay Sternberg .shutdown = nvme_shutdown, 349757dacad5SJay Sternberg .driver = { 3498eac3ef26SChristoph Hellwig .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3499eac3ef26SChristoph Hellwig #ifdef CONFIG_PM_SLEEP 350057dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 3501d916b1beSKeith Busch #endif 3502eac3ef26SChristoph Hellwig }, 350374d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 350457dacad5SJay Sternberg .err_handler = &nvme_err_handler, 350557dacad5SJay Sternberg }; 350657dacad5SJay Sternberg 350757dacad5SJay Sternberg static int __init nvme_init(void) 350857dacad5SJay Sternberg { 350981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 351081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 351181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3512612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 351301df742dSKeith Busch BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE); 35147846c1b5SKeith Busch BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE); 35157846c1b5SKeith Busch BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS); 351617c33167SKeith Busch 35179a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 351857dacad5SJay Sternberg } 351957dacad5SJay Sternberg 352057dacad5SJay Sternberg static void __exit nvme_exit(void) 352157dacad5SJay Sternberg { 352257dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 352303e0f3a6SMing Lei flush_workqueue(nvme_wq); 352457dacad5SJay Sternberg } 352557dacad5SJay Sternberg 352657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 352757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 352857dacad5SJay Sternberg MODULE_VERSION("1.0"); 352957dacad5SJay Sternberg module_init(nvme_init); 353057dacad5SJay Sternberg module_exit(nvme_exit); 3531