15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 21d916b1beSKeith Busch #include <linux/suspend.h> 2257dacad5SJay Sternberg #include <linux/t10-pi.h> 2357dacad5SJay Sternberg #include <linux/types.h> 249cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 25a98e58e5SScott Bauer #include <linux/sed-opal.h> 260f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2757dacad5SJay Sternberg 28604c01d5Syupeng #include "trace.h" 2957dacad5SJay Sternberg #include "nvme.h" 3057dacad5SJay Sternberg 31c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 328a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3357dacad5SJay Sternberg 34a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 35adf68f21SChristoph Hellwig 36943e942eSJens Axboe /* 37943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 38943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 39943e942eSJens Axboe */ 40943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 41943e942eSJens Axboe #define NVME_MAX_SEGS 127 42943e942eSJens Axboe 4357dacad5SJay Sternberg static int use_threaded_interrupts; 4457dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4557dacad5SJay Sternberg 4657dacad5SJay Sternberg static bool use_cmb_sqes = true; 4769f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4857dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4957dacad5SJay Sternberg 5087ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5187ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5287ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5387ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5457dacad5SJay Sternberg 55a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 56a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 57a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 58a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 59a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 60a7a7cbe3SChaitanya Kulkarni 61b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 62b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 63b27c1e68Sweiping zhang .set = io_queue_depth_set, 6461f3b896SChaitanya Kulkarni .get = param_get_uint, 65b27c1e68Sweiping zhang }; 66b27c1e68Sweiping zhang 6761f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 68b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 69b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 70b27c1e68Sweiping zhang 719c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 729c9e76d5SWeiping Zhang { 739c9e76d5SWeiping Zhang unsigned int n; 749c9e76d5SWeiping Zhang int ret; 759c9e76d5SWeiping Zhang 769c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 779c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 789c9e76d5SWeiping Zhang return -EINVAL; 799c9e76d5SWeiping Zhang return param_set_uint(val, kp); 809c9e76d5SWeiping Zhang } 819c9e76d5SWeiping Zhang 829c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 839c9e76d5SWeiping Zhang .set = io_queue_count_set, 849c9e76d5SWeiping Zhang .get = param_get_uint, 859c9e76d5SWeiping Zhang }; 869c9e76d5SWeiping Zhang 873f68baf7SKeith Busch static unsigned int write_queues; 889c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 893b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 903b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 913b6592f7SJens Axboe "will share a queue set."); 923b6592f7SJens Axboe 933f68baf7SKeith Busch static unsigned int poll_queues; 949c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 954b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 964b04cc6aSJens Axboe 971c63dc66SChristoph Hellwig struct nvme_dev; 981c63dc66SChristoph Hellwig struct nvme_queue; 9957dacad5SJay Sternberg 100a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1018fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 10257dacad5SJay Sternberg 10357dacad5SJay Sternberg /* 1041c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1051c63dc66SChristoph Hellwig */ 1061c63dc66SChristoph Hellwig struct nvme_dev { 107147b27e4SSagi Grimberg struct nvme_queue *queues; 1081c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1091c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1101c63dc66SChristoph Hellwig u32 __iomem *dbs; 1111c63dc66SChristoph Hellwig struct device *dev; 1121c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1131c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1141c63dc66SChristoph Hellwig unsigned online_queues; 1151c63dc66SChristoph Hellwig unsigned max_qid; 116e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 11722b55601SKeith Busch unsigned int num_vecs; 11861f3b896SChaitanya Kulkarni u16 q_depth; 119c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1201c63dc66SChristoph Hellwig u32 db_stride; 1211c63dc66SChristoph Hellwig void __iomem *bar; 12297f6ef64SXu Yu unsigned long bar_mapped_size; 1235c8809e6SChristoph Hellwig struct work_struct remove_work; 12477bf25eaSKeith Busch struct mutex shutdown_lock; 1251c63dc66SChristoph Hellwig bool subsystem; 1261c63dc66SChristoph Hellwig u64 cmb_size; 1270f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1281c63dc66SChristoph Hellwig u32 cmbsz; 129202021c1SStephen Bates u32 cmbloc; 1301c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 131d916b1beSKeith Busch u32 last_ps; 13287ad72a5SChristoph Hellwig 133943e942eSJens Axboe mempool_t *iod_mempool; 134943e942eSJens Axboe 13587ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 136f9f38e33SHelen Koike u32 *dbbuf_dbs; 137f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 138f9f38e33SHelen Koike u32 *dbbuf_eis; 139f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14087ad72a5SChristoph Hellwig 14187ad72a5SChristoph Hellwig /* host memory buffer support: */ 14287ad72a5SChristoph Hellwig u64 host_mem_size; 14387ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1444033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 14587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 14687ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1472a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1482a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1492a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 15057dacad5SJay Sternberg }; 15157dacad5SJay Sternberg 152b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 153b27c1e68Sweiping zhang { 15461f3b896SChaitanya Kulkarni int ret; 15561f3b896SChaitanya Kulkarni u16 n; 156b27c1e68Sweiping zhang 15761f3b896SChaitanya Kulkarni ret = kstrtou16(val, 10, &n); 158b27c1e68Sweiping zhang if (ret != 0 || n < 2) 159b27c1e68Sweiping zhang return -EINVAL; 160b27c1e68Sweiping zhang 16161f3b896SChaitanya Kulkarni return param_set_ushort(val, kp); 162b27c1e68Sweiping zhang } 163b27c1e68Sweiping zhang 164f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 165f9f38e33SHelen Koike { 166f9f38e33SHelen Koike return qid * 2 * stride; 167f9f38e33SHelen Koike } 168f9f38e33SHelen Koike 169f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 1741c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1751c63dc66SChristoph Hellwig { 1761c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1771c63dc66SChristoph Hellwig } 1781c63dc66SChristoph Hellwig 17957dacad5SJay Sternberg /* 18057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18157dacad5SJay Sternberg * commands and one for I/O commands). 18257dacad5SJay Sternberg */ 18357dacad5SJay Sternberg struct nvme_queue { 18457dacad5SJay Sternberg struct nvme_dev *dev; 1851ab0cd69SJens Axboe spinlock_t sq_lock; 186c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1873a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1883a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 18974943d45SKeith Busch struct nvme_completion *cqes; 19057dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19157dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19257dacad5SJay Sternberg u32 __iomem *q_db; 19357dacad5SJay Sternberg u16 q_depth; 1947c349ddeSKeith Busch u16 cq_vector; 19557dacad5SJay Sternberg u16 sq_tail; 19657dacad5SJay Sternberg u16 cq_head; 19757dacad5SJay Sternberg u16 qid; 19857dacad5SJay Sternberg u8 cq_phase; 199c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2004e224106SChristoph Hellwig unsigned long flags; 2014e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20263223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 203d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2047c349ddeSKeith Busch #define NVMEQ_POLLED 3 205f9f38e33SHelen Koike u32 *dbbuf_sq_db; 206f9f38e33SHelen Koike u32 *dbbuf_cq_db; 207f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 208f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 209d1ed6aa1SChristoph Hellwig struct completion delete_done; 21057dacad5SJay Sternberg }; 21157dacad5SJay Sternberg 21257dacad5SJay Sternberg /* 2139b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2149b048119SChristoph Hellwig * 2159b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2169b048119SChristoph Hellwig * to the actual struct scatterlist. 21771bd150cSChristoph Hellwig */ 21871bd150cSChristoph Hellwig struct nvme_iod { 219d49187e9SChristoph Hellwig struct nvme_request req; 220f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 221a7a7cbe3SChaitanya Kulkarni bool use_sgl; 222f4800d6dSChristoph Hellwig int aborted; 22371bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22471bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22571bd150cSChristoph Hellwig dma_addr_t first_dma; 226dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 227783b94bdSChristoph Hellwig dma_addr_t meta_dma; 228f4800d6dSChristoph Hellwig struct scatterlist *sg; 22957dacad5SJay Sternberg }; 23057dacad5SJay Sternberg 2312a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2323b6592f7SJens Axboe { 2332a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 234f9f38e33SHelen Koike } 235f9f38e33SHelen Koike 236f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 237f9f38e33SHelen Koike { 2382a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 239f9f38e33SHelen Koike 240f9f38e33SHelen Koike if (dev->dbbuf_dbs) 241f9f38e33SHelen Koike return 0; 242f9f38e33SHelen Koike 243f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 244f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 245f9f38e33SHelen Koike GFP_KERNEL); 246f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 247f9f38e33SHelen Koike return -ENOMEM; 248f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 249f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 250f9f38e33SHelen Koike GFP_KERNEL); 251f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 252f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 253f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 254f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 255f9f38e33SHelen Koike return -ENOMEM; 256f9f38e33SHelen Koike } 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike return 0; 259f9f38e33SHelen Koike } 260f9f38e33SHelen Koike 261f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 262f9f38e33SHelen Koike { 2632a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 266f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 267f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 268f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 269f9f38e33SHelen Koike } 270f9f38e33SHelen Koike if (dev->dbbuf_eis) { 271f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 272f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 273f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 274f9f38e33SHelen Koike } 275f9f38e33SHelen Koike } 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 278f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 279f9f38e33SHelen Koike { 280f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 281f9f38e33SHelen Koike return; 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 284f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 285f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 286f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 287f9f38e33SHelen Koike } 288f9f38e33SHelen Koike 289f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 290f9f38e33SHelen Koike { 291f9f38e33SHelen Koike struct nvme_command c; 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 294f9f38e33SHelen Koike return; 295f9f38e33SHelen Koike 296f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 297f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 298f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 299f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3029bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 303f9f38e33SHelen Koike /* Free memory and continue on */ 304f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 305f9f38e33SHelen Koike } 306f9f38e33SHelen Koike } 307f9f38e33SHelen Koike 308f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 309f9f38e33SHelen Koike { 310f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 311f9f38e33SHelen Koike } 312f9f38e33SHelen Koike 313f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 314f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 315f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 316f9f38e33SHelen Koike { 317f9f38e33SHelen Koike if (dbbuf_db) { 318f9f38e33SHelen Koike u16 old_value; 319f9f38e33SHelen Koike 320f9f38e33SHelen Koike /* 321f9f38e33SHelen Koike * Ensure that the queue is written before updating 322f9f38e33SHelen Koike * the doorbell in memory 323f9f38e33SHelen Koike */ 324f9f38e33SHelen Koike wmb(); 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike old_value = *dbbuf_db; 327f9f38e33SHelen Koike *dbbuf_db = value; 328f9f38e33SHelen Koike 329f1ed3df2SMichal Wnukowski /* 330f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 331f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 332f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 333f1ed3df2SMichal Wnukowski * the doorbell. 334f1ed3df2SMichal Wnukowski */ 335f1ed3df2SMichal Wnukowski mb(); 336f1ed3df2SMichal Wnukowski 337f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 338f9f38e33SHelen Koike return false; 339f9f38e33SHelen Koike } 340f9f38e33SHelen Koike 341f9f38e33SHelen Koike return true; 34257dacad5SJay Sternberg } 34357dacad5SJay Sternberg 34457dacad5SJay Sternberg /* 34557dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 34657dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 34757dacad5SJay Sternberg * the I/O. 34857dacad5SJay Sternberg */ 349b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 35057dacad5SJay Sternberg { 351b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3526c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 35357dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 35457dacad5SJay Sternberg } 35557dacad5SJay Sternberg 356a7a7cbe3SChaitanya Kulkarni /* 357a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 358a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 359a7a7cbe3SChaitanya Kulkarni */ 360b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 361f4800d6dSChristoph Hellwig { 362b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 363b13c6393SChaitanya Kulkarni PAGE_SIZE); 364f4800d6dSChristoph Hellwig } 365f4800d6dSChristoph Hellwig 366b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 36757dacad5SJay Sternberg { 368b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 369a7a7cbe3SChaitanya Kulkarni 370b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 371b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 372a7a7cbe3SChaitanya Kulkarni } 373a7a7cbe3SChaitanya Kulkarni 37457dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37557dacad5SJay Sternberg unsigned int hctx_idx) 37657dacad5SJay Sternberg { 37757dacad5SJay Sternberg struct nvme_dev *dev = data; 378147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37957dacad5SJay Sternberg 38057dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 38157dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg hctx->driver_data = nvmeq; 38457dacad5SJay Sternberg return 0; 38557dacad5SJay Sternberg } 38657dacad5SJay Sternberg 38757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38857dacad5SJay Sternberg unsigned int hctx_idx) 38957dacad5SJay Sternberg { 39057dacad5SJay Sternberg struct nvme_dev *dev = data; 391147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39257dacad5SJay Sternberg 39357dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39457dacad5SJay Sternberg hctx->driver_data = nvmeq; 39557dacad5SJay Sternberg return 0; 39657dacad5SJay Sternberg } 39757dacad5SJay Sternberg 398d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 399d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40057dacad5SJay Sternberg { 401d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 402f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4030350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 404147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40557dacad5SJay Sternberg 40657dacad5SJay Sternberg BUG_ON(!nvmeq); 407f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 40859e29ce6SSagi Grimberg 40959e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 41057dacad5SJay Sternberg return 0; 41157dacad5SJay Sternberg } 41257dacad5SJay Sternberg 4133b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4143b6592f7SJens Axboe { 4153b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4163b6592f7SJens Axboe if (dev->num_vecs > 1) 4173b6592f7SJens Axboe return 1; 4183b6592f7SJens Axboe 4193b6592f7SJens Axboe return 0; 4203b6592f7SJens Axboe } 4213b6592f7SJens Axboe 422dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 423dca51e78SChristoph Hellwig { 424dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4253b6592f7SJens Axboe int i, qoff, offset; 426dca51e78SChristoph Hellwig 4273b6592f7SJens Axboe offset = queue_irq_offset(dev); 4283b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4293b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4303b6592f7SJens Axboe 4313b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4323b6592f7SJens Axboe if (!map->nr_queues) { 433e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4347e849dd9SChristoph Hellwig continue; 4353b6592f7SJens Axboe } 4363b6592f7SJens Axboe 4374b04cc6aSJens Axboe /* 4384b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4394b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4404b04cc6aSJens Axboe */ 4413b6592f7SJens Axboe map->queue_offset = qoff; 442cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4433b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4444b04cc6aSJens Axboe else 4454b04cc6aSJens Axboe blk_mq_map_queues(map); 4463b6592f7SJens Axboe qoff += map->nr_queues; 4473b6592f7SJens Axboe offset += map->nr_queues; 4483b6592f7SJens Axboe } 4493b6592f7SJens Axboe 4503b6592f7SJens Axboe return 0; 451dca51e78SChristoph Hellwig } 452dca51e78SChristoph Hellwig 45354b2fceeSKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq) 45404f3eafdSJens Axboe { 45504f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 45604f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 45704f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 45804f3eafdSJens Axboe } 45904f3eafdSJens Axboe 46057dacad5SJay Sternberg /** 46190ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 46257dacad5SJay Sternberg * @nvmeq: The queue to use 46357dacad5SJay Sternberg * @cmd: The command to send 46404f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 46557dacad5SJay Sternberg */ 46604f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 46704f3eafdSJens Axboe bool write_sq) 46857dacad5SJay Sternberg { 46990ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 470c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 471c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 47290ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 47390ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 47454b2fceeSKeith Busch if (write_sq) 47554b2fceeSKeith Busch nvme_write_sq_db(nvmeq); 47604f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 47704f3eafdSJens Axboe } 47804f3eafdSJens Axboe 47904f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 48004f3eafdSJens Axboe { 48104f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 48204f3eafdSJens Axboe 48304f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 48454b2fceeSKeith Busch nvme_write_sq_db(nvmeq); 48590ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 48657dacad5SJay Sternberg } 48757dacad5SJay Sternberg 488a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 48957dacad5SJay Sternberg { 490f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 491a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 49257dacad5SJay Sternberg } 49357dacad5SJay Sternberg 494955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 495955b1b5aSMinwoo Im { 496955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 49720469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 498955b1b5aSMinwoo Im unsigned int avg_seg_size; 499955b1b5aSMinwoo Im 50020469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 501955b1b5aSMinwoo Im 502955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 503955b1b5aSMinwoo Im return false; 504955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 505955b1b5aSMinwoo Im return false; 506955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 507955b1b5aSMinwoo Im return false; 508955b1b5aSMinwoo Im return true; 509955b1b5aSMinwoo Im } 510955b1b5aSMinwoo Im 5117fe07d14SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 51257dacad5SJay Sternberg { 513f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5146c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 515a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 51657dacad5SJay Sternberg int i; 51757dacad5SJay Sternberg 518dff824b2SChristoph Hellwig if (iod->dma_len) { 519f2fa006fSIsrael Rukshin dma_unmap_page(dev->dev, dma_addr, iod->dma_len, 520f2fa006fSIsrael Rukshin rq_dma_dir(req)); 521dff824b2SChristoph Hellwig return; 522dff824b2SChristoph Hellwig } 523dff824b2SChristoph Hellwig 524dff824b2SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 525dff824b2SChristoph Hellwig 5267f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5277f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5287f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5297f73eac3SLogan Gunthorpe else 530dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5317fe07d14SChristoph Hellwig 5327fe07d14SChristoph Hellwig 53357dacad5SJay Sternberg if (iod->npages == 0) 534a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 535a7a7cbe3SChaitanya Kulkarni dma_addr); 536a7a7cbe3SChaitanya Kulkarni 53757dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 538a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 539a7a7cbe3SChaitanya Kulkarni 540a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 541a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 542a7a7cbe3SChaitanya Kulkarni 543a7a7cbe3SChaitanya Kulkarni next_dma_addr = 544a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 545a7a7cbe3SChaitanya Kulkarni } else { 546a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 547a7a7cbe3SChaitanya Kulkarni 548a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 549a7a7cbe3SChaitanya Kulkarni } 550a7a7cbe3SChaitanya Kulkarni 551a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 552a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 55357dacad5SJay Sternberg } 55457dacad5SJay Sternberg 555943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 55657dacad5SJay Sternberg } 55757dacad5SJay Sternberg 558d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 559d0877473SKeith Busch { 560d0877473SKeith Busch int i; 561d0877473SKeith Busch struct scatterlist *sg; 562d0877473SKeith Busch 563d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 564d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 565d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 566d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 567d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 568d0877473SKeith Busch sg_dma_len(sg)); 569d0877473SKeith Busch } 570d0877473SKeith Busch } 571d0877473SKeith Busch 572a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 573a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 57457dacad5SJay Sternberg { 575f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 57657dacad5SJay Sternberg struct dma_pool *pool; 577b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 57857dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 57957dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 58057dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5816c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 58257dacad5SJay Sternberg __le64 *prp_list; 583a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 58457dacad5SJay Sternberg dma_addr_t prp_dma; 58557dacad5SJay Sternberg int nprps, i; 58657dacad5SJay Sternberg 5876c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 5885228b328SJan H. Schönherr if (length <= 0) { 5895228b328SJan H. Schönherr iod->first_dma = 0; 590a7a7cbe3SChaitanya Kulkarni goto done; 5915228b328SJan H. Schönherr } 59257dacad5SJay Sternberg 5936c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 59457dacad5SJay Sternberg if (dma_len) { 5956c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 59657dacad5SJay Sternberg } else { 59757dacad5SJay Sternberg sg = sg_next(sg); 59857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 59957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 60057dacad5SJay Sternberg } 60157dacad5SJay Sternberg 6026c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 60357dacad5SJay Sternberg iod->first_dma = dma_addr; 604a7a7cbe3SChaitanya Kulkarni goto done; 60557dacad5SJay Sternberg } 60657dacad5SJay Sternberg 6076c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 60857dacad5SJay Sternberg if (nprps <= (256 / 8)) { 60957dacad5SJay Sternberg pool = dev->prp_small_pool; 61057dacad5SJay Sternberg iod->npages = 0; 61157dacad5SJay Sternberg } else { 61257dacad5SJay Sternberg pool = dev->prp_page_pool; 61357dacad5SJay Sternberg iod->npages = 1; 61457dacad5SJay Sternberg } 61557dacad5SJay Sternberg 61669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 61757dacad5SJay Sternberg if (!prp_list) { 61857dacad5SJay Sternberg iod->first_dma = dma_addr; 61957dacad5SJay Sternberg iod->npages = -1; 62086eea289SKeith Busch return BLK_STS_RESOURCE; 62157dacad5SJay Sternberg } 62257dacad5SJay Sternberg list[0] = prp_list; 62357dacad5SJay Sternberg iod->first_dma = prp_dma; 62457dacad5SJay Sternberg i = 0; 62557dacad5SJay Sternberg for (;;) { 6266c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 62757dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 62869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 62957dacad5SJay Sternberg if (!prp_list) 63086eea289SKeith Busch return BLK_STS_RESOURCE; 63157dacad5SJay Sternberg list[iod->npages++] = prp_list; 63257dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 63357dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 63457dacad5SJay Sternberg i = 1; 63557dacad5SJay Sternberg } 63657dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6376c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6386c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6396c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 64057dacad5SJay Sternberg if (length <= 0) 64157dacad5SJay Sternberg break; 64257dacad5SJay Sternberg if (dma_len > 0) 64357dacad5SJay Sternberg continue; 64486eea289SKeith Busch if (unlikely(dma_len < 0)) 64586eea289SKeith Busch goto bad_sgl; 64657dacad5SJay Sternberg sg = sg_next(sg); 64757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 64957dacad5SJay Sternberg } 65057dacad5SJay Sternberg 651a7a7cbe3SChaitanya Kulkarni done: 652a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 653a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 654a7a7cbe3SChaitanya Kulkarni 65586eea289SKeith Busch return BLK_STS_OK; 65686eea289SKeith Busch 65786eea289SKeith Busch bad_sgl: 658d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 659d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 660d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 66186eea289SKeith Busch return BLK_STS_IOERR; 66257dacad5SJay Sternberg } 66357dacad5SJay Sternberg 664a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 665a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 666a7a7cbe3SChaitanya Kulkarni { 667a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 668a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 669a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 670a7a7cbe3SChaitanya Kulkarni } 671a7a7cbe3SChaitanya Kulkarni 672a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 673a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 674a7a7cbe3SChaitanya Kulkarni { 675a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 676a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 677a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 678a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 679a7a7cbe3SChaitanya Kulkarni } else { 680a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 681a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 682a7a7cbe3SChaitanya Kulkarni } 683a7a7cbe3SChaitanya Kulkarni } 684a7a7cbe3SChaitanya Kulkarni 685a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 686b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 687a7a7cbe3SChaitanya Kulkarni { 688a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 689a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 690a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 691a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 692a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 693b0f2853bSChristoph Hellwig int i = 0; 694a7a7cbe3SChaitanya Kulkarni 695a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 696a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 697a7a7cbe3SChaitanya Kulkarni 698b0f2853bSChristoph Hellwig if (entries == 1) { 699a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 700a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 701a7a7cbe3SChaitanya Kulkarni } 702a7a7cbe3SChaitanya Kulkarni 703a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 704a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 705a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 706a7a7cbe3SChaitanya Kulkarni } else { 707a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 708a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 709a7a7cbe3SChaitanya Kulkarni } 710a7a7cbe3SChaitanya Kulkarni 711a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 712a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 713a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 714a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 715a7a7cbe3SChaitanya Kulkarni } 716a7a7cbe3SChaitanya Kulkarni 717a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 718a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 719a7a7cbe3SChaitanya Kulkarni 720a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 721a7a7cbe3SChaitanya Kulkarni 722a7a7cbe3SChaitanya Kulkarni do { 723a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 724a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 725a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 728a7a7cbe3SChaitanya Kulkarni if (!sg_list) 729a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 730a7a7cbe3SChaitanya Kulkarni 731a7a7cbe3SChaitanya Kulkarni i = 0; 732a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 733a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 734a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 735a7a7cbe3SChaitanya Kulkarni } 736a7a7cbe3SChaitanya Kulkarni 737a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 738a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 739b0f2853bSChristoph Hellwig } while (--entries > 0); 740a7a7cbe3SChaitanya Kulkarni 741a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 742a7a7cbe3SChaitanya Kulkarni } 743a7a7cbe3SChaitanya Kulkarni 744dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 745dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 746dff824b2SChristoph Hellwig struct bio_vec *bv) 747dff824b2SChristoph Hellwig { 748dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7496c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7506c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 751dff824b2SChristoph Hellwig 752dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 753dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 754dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 755dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 756dff824b2SChristoph Hellwig 757dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 758dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 759dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 760359c1f88SBaolin Wang return BLK_STS_OK; 761dff824b2SChristoph Hellwig } 762dff824b2SChristoph Hellwig 76329791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 76429791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 76529791057SChristoph Hellwig struct bio_vec *bv) 76629791057SChristoph Hellwig { 76729791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 76829791057SChristoph Hellwig 76929791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 77029791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 77129791057SChristoph Hellwig return BLK_STS_RESOURCE; 77229791057SChristoph Hellwig iod->dma_len = bv->bv_len; 77329791057SChristoph Hellwig 774049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 77529791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 77629791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 77729791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 778359c1f88SBaolin Wang return BLK_STS_OK; 77929791057SChristoph Hellwig } 78029791057SChristoph Hellwig 781fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 782b131c61dSChristoph Hellwig struct nvme_command *cmnd) 78357dacad5SJay Sternberg { 784f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 78570479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 786b0f2853bSChristoph Hellwig int nr_mapped; 78757dacad5SJay Sternberg 788dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 789dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 790dff824b2SChristoph Hellwig 791dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 7926c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 793dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 794dff824b2SChristoph Hellwig &cmnd->rw, &bv); 79529791057SChristoph Hellwig 79629791057SChristoph Hellwig if (iod->nvmeq->qid && 79729791057SChristoph Hellwig dev->ctrl.sgls & ((1 << 0) | (1 << 1))) 79829791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 79929791057SChristoph Hellwig &cmnd->rw, &bv); 800dff824b2SChristoph Hellwig } 801dff824b2SChristoph Hellwig } 802dff824b2SChristoph Hellwig 803dff824b2SChristoph Hellwig iod->dma_len = 0; 8049b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8059b048119SChristoph Hellwig if (!iod->sg) 8069b048119SChristoph Hellwig return BLK_STS_RESOURCE; 807f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 80870479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 809ba1ca37eSChristoph Hellwig if (!iod->nents) 810ba1ca37eSChristoph Hellwig goto out; 811ba1ca37eSChristoph Hellwig 812e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8132b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8142b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 815e0596ab2SLogan Gunthorpe else 816e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 81770479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 818b0f2853bSChristoph Hellwig if (!nr_mapped) 819ba1ca37eSChristoph Hellwig goto out; 820ba1ca37eSChristoph Hellwig 82170479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 822955b1b5aSMinwoo Im if (iod->use_sgl) 823b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 824a7a7cbe3SChaitanya Kulkarni else 825a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 826ba1ca37eSChristoph Hellwig out: 8274aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 8287fe07d14SChristoph Hellwig nvme_unmap_data(dev, req); 829ba1ca37eSChristoph Hellwig return ret; 83057dacad5SJay Sternberg } 83157dacad5SJay Sternberg 8324aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8334aedb705SChristoph Hellwig struct nvme_command *cmnd) 8344aedb705SChristoph Hellwig { 8354aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8364aedb705SChristoph Hellwig 8374aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8384aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8394aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8404aedb705SChristoph Hellwig return BLK_STS_IOERR; 8414aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 842359c1f88SBaolin Wang return BLK_STS_OK; 8434aedb705SChristoph Hellwig } 8444aedb705SChristoph Hellwig 84557dacad5SJay Sternberg /* 84657dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 84757dacad5SJay Sternberg */ 848fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 84957dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 85057dacad5SJay Sternberg { 85157dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 85257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 85357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 85457dacad5SJay Sternberg struct request *req = bd->rq; 8559b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 856ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 857ebe6d874SChristoph Hellwig blk_status_t ret; 85857dacad5SJay Sternberg 8599b048119SChristoph Hellwig iod->aborted = 0; 8609b048119SChristoph Hellwig iod->npages = -1; 8619b048119SChristoph Hellwig iod->nents = 0; 8629b048119SChristoph Hellwig 863d1f06f4aSJens Axboe /* 864d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 865d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 866d1f06f4aSJens Axboe */ 8674e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 868d1f06f4aSJens Axboe return BLK_STS_IOERR; 869d1f06f4aSJens Axboe 870f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 871fc17b653SChristoph Hellwig if (ret) 872f4800d6dSChristoph Hellwig return ret; 87357dacad5SJay Sternberg 874fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 875b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 876fc17b653SChristoph Hellwig if (ret) 8779b048119SChristoph Hellwig goto out_free_cmd; 878fc17b653SChristoph Hellwig } 879ba1ca37eSChristoph Hellwig 8804aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 8814aedb705SChristoph Hellwig ret = nvme_map_metadata(dev, req, &cmnd); 8824aedb705SChristoph Hellwig if (ret) 8834aedb705SChristoph Hellwig goto out_unmap_data; 8844aedb705SChristoph Hellwig } 8854aedb705SChristoph Hellwig 886aae239e1SChristoph Hellwig blk_mq_start_request(req); 88704f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 888fc17b653SChristoph Hellwig return BLK_STS_OK; 8894aedb705SChristoph Hellwig out_unmap_data: 8904aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 891f9d03f96SChristoph Hellwig out_free_cmd: 892f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 893ba1ca37eSChristoph Hellwig return ret; 89457dacad5SJay Sternberg } 89557dacad5SJay Sternberg 89677f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 897eee417b0SChristoph Hellwig { 898f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8994aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 900eee417b0SChristoph Hellwig 9014aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9024aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9034aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 904b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9054aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 90677f02a7aSChristoph Hellwig nvme_complete_rq(req); 90757dacad5SJay Sternberg } 90857dacad5SJay Sternberg 909d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 910750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 911d783e0bdSMarta Rybczynska { 91274943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 91374943d45SKeith Busch 91474943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 915d783e0bdSMarta Rybczynska } 916d783e0bdSMarta Rybczynska 917eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 91857dacad5SJay Sternberg { 919eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92057dacad5SJay Sternberg 921eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 922eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 923eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 924eb281c82SSagi Grimberg } 925adf68f21SChristoph Hellwig 926cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 927cfa27356SChristoph Hellwig { 928cfa27356SChristoph Hellwig if (!nvmeq->qid) 929cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 930cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 931cfa27356SChristoph Hellwig } 932cfa27356SChristoph Hellwig 9335cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 93457dacad5SJay Sternberg { 93574943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 93657dacad5SJay Sternberg struct request *req; 937adf68f21SChristoph Hellwig 93883a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9391b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 940aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94183a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94283a12fb7SSagi Grimberg return; 943aae239e1SChristoph Hellwig } 944aae239e1SChristoph Hellwig 945adf68f21SChristoph Hellwig /* 946adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 947adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 948adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 949adf68f21SChristoph Hellwig * for them but rather special case them here. 950adf68f21SChristoph Hellwig */ 95158a8df67SIsrael Rukshin if (unlikely(nvme_is_aen_req(nvmeq->qid, cqe->command_id))) { 9527bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95383a12fb7SSagi Grimberg cqe->status, &cqe->result); 954a0fa9647SJens Axboe return; 95557dacad5SJay Sternberg } 95657dacad5SJay Sternberg 957cfa27356SChristoph Hellwig req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), cqe->command_id); 958604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 959ff029451SChristoph Hellwig if (!nvme_end_request(req, cqe->status, cqe->result)) 960ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 96183a12fb7SSagi Grimberg } 96257dacad5SJay Sternberg 9635cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9645cb525c8SJens Axboe { 965a8de6639SAlexey Dobriyan u16 tmp = nvmeq->cq_head + 1; 966a8de6639SAlexey Dobriyan 967a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 968920d13a8SSagi Grimberg nvmeq->cq_head = 0; 969e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 970a8de6639SAlexey Dobriyan } else { 971a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 972920d13a8SSagi Grimberg } 973a0fa9647SJens Axboe } 974a0fa9647SJens Axboe 975324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 976a0fa9647SJens Axboe { 9771052b8acSJens Axboe int found = 0; 97883a12fb7SSagi Grimberg 9791052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 9801052b8acSJens Axboe found++; 981b69e2ef2SKeith Busch /* 982b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 983b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 984b69e2ef2SKeith Busch */ 985b69e2ef2SKeith Busch dma_rmb(); 986324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 9875cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 98857dacad5SJay Sternberg } 98957dacad5SJay Sternberg 990324b494cSKeith Busch if (found) 991eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9925cb525c8SJens Axboe return found; 99357dacad5SJay Sternberg } 99457dacad5SJay Sternberg 99557dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 99657dacad5SJay Sternberg { 99757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 99868fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 9995cb525c8SJens Axboe 10003a7afd8eSChristoph Hellwig /* 10013a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10023a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10033a7afd8eSChristoph Hellwig */ 10043a7afd8eSChristoph Hellwig rmb(); 1005324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 1006324b494cSKeith Busch ret = IRQ_HANDLED; 10073a7afd8eSChristoph Hellwig wmb(); 10085cb525c8SJens Axboe 100968fa9dbeSJens Axboe return ret; 101057dacad5SJay Sternberg } 101157dacad5SJay Sternberg 101257dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 101357dacad5SJay Sternberg { 101457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10154e523547SBaolin Wang 1016750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 101757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1018d783e0bdSMarta Rybczynska return IRQ_NONE; 101957dacad5SJay Sternberg } 102057dacad5SJay Sternberg 10210b2a8a9fSChristoph Hellwig /* 1022fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10230b2a8a9fSChristoph Hellwig * Can be called from any context. 10240b2a8a9fSChristoph Hellwig */ 1025fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1026a0fa9647SJens Axboe { 10273a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1028a0fa9647SJens Axboe 1029fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1030fa059b85SKeith Busch 10313a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1032fa059b85SKeith Busch nvme_process_cq(nvmeq); 10333a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 103491a509f8SChristoph Hellwig } 1035442e19b7SSagi Grimberg 10369743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10377776db1cSKeith Busch { 10387776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1039dabcefabSJens Axboe bool found; 1040dabcefabSJens Axboe 1041dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1042dabcefabSJens Axboe return 0; 1043dabcefabSJens Axboe 10443a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1045324b494cSKeith Busch found = nvme_process_cq(nvmeq); 10463a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1047dabcefabSJens Axboe 1048dabcefabSJens Axboe return found; 1049dabcefabSJens Axboe } 1050dabcefabSJens Axboe 1051ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 105257dacad5SJay Sternberg { 1053f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1054147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 105557dacad5SJay Sternberg struct nvme_command c; 105657dacad5SJay Sternberg 105757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105857dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1059ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 106004f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 106157dacad5SJay Sternberg } 106257dacad5SJay Sternberg 106357dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106457dacad5SJay Sternberg { 106557dacad5SJay Sternberg struct nvme_command c; 106657dacad5SJay Sternberg 106757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106857dacad5SJay Sternberg c.delete_queue.opcode = opcode; 106957dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 107057dacad5SJay Sternberg 10711c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107257dacad5SJay Sternberg } 107357dacad5SJay Sternberg 107457dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1075a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 107657dacad5SJay Sternberg { 107757dacad5SJay Sternberg struct nvme_command c; 10784b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 10794b04cc6aSJens Axboe 10807c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 10814b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 108257dacad5SJay Sternberg 108357dacad5SJay Sternberg /* 108416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 108557dacad5SJay Sternberg * is attached to the request. 108657dacad5SJay Sternberg */ 108757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108857dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 108957dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 109057dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 109157dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 109257dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1093a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 109457dacad5SJay Sternberg 10951c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 109657dacad5SJay Sternberg } 109757dacad5SJay Sternberg 109857dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 109957dacad5SJay Sternberg struct nvme_queue *nvmeq) 110057dacad5SJay Sternberg { 11019abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 110257dacad5SJay Sternberg struct nvme_command c; 110381c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 110457dacad5SJay Sternberg 110557dacad5SJay Sternberg /* 11069abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11079abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11089abd68efSJens Axboe * URGENT. 11099abd68efSJens Axboe */ 11109abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11119abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11129abd68efSJens Axboe 11139abd68efSJens Axboe /* 111416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 111557dacad5SJay Sternberg * is attached to the request. 111657dacad5SJay Sternberg */ 111757dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111857dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 111957dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 112057dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 112157dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 112257dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 112357dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 112457dacad5SJay Sternberg 11251c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112657dacad5SJay Sternberg } 112757dacad5SJay Sternberg 112857dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 112957dacad5SJay Sternberg { 113057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 113157dacad5SJay Sternberg } 113257dacad5SJay Sternberg 113357dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 113457dacad5SJay Sternberg { 113557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 113657dacad5SJay Sternberg } 113757dacad5SJay Sternberg 11382a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 113957dacad5SJay Sternberg { 1140f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1141f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 114257dacad5SJay Sternberg 114327fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 114427fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1145e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1146e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 114757dacad5SJay Sternberg } 114857dacad5SJay Sternberg 1149b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1150b2a0eb1aSKeith Busch { 1151b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1152b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1153b2a0eb1aSKeith Busch */ 1154b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1155b2a0eb1aSKeith Busch 1156ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1157ad70062cSJianchao Wang switch (dev->ctrl.state) { 1158ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1159ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1160b2a0eb1aSKeith Busch return false; 1161ad70062cSJianchao Wang default: 1162ad70062cSJianchao Wang break; 1163ad70062cSJianchao Wang } 1164b2a0eb1aSKeith Busch 1165b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1166b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1167b2a0eb1aSKeith Busch */ 1168b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1169b2a0eb1aSKeith Busch return false; 1170b2a0eb1aSKeith Busch 1171b2a0eb1aSKeith Busch return true; 1172b2a0eb1aSKeith Busch } 1173b2a0eb1aSKeith Busch 1174b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1175b2a0eb1aSKeith Busch { 1176b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1177b2a0eb1aSKeith Busch u16 pci_status; 1178b2a0eb1aSKeith Busch int result; 1179b2a0eb1aSKeith Busch 1180b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1181b2a0eb1aSKeith Busch &pci_status); 1182b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1183b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1184b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1185b2a0eb1aSKeith Busch csts, pci_status); 1186b2a0eb1aSKeith Busch else 1187b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1188b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1189b2a0eb1aSKeith Busch csts, result); 1190b2a0eb1aSKeith Busch } 1191b2a0eb1aSKeith Busch 119231c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 119357dacad5SJay Sternberg { 1194f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1195f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 119757dacad5SJay Sternberg struct request *abort_req; 119857dacad5SJay Sternberg struct nvme_command cmd; 1199b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1200b2a0eb1aSKeith Busch 1201651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1202651438bbSWen Xiong * the recovery mechanism will surely fail. 1203651438bbSWen Xiong */ 1204651438bbSWen Xiong mb(); 1205651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1206651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1207651438bbSWen Xiong 1208b2a0eb1aSKeith Busch /* 1209b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1210b2a0eb1aSKeith Busch */ 1211b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1212b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1213b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1214d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1215db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1216b2a0eb1aSKeith Busch } 121757dacad5SJay Sternberg 121831c7c7d2SChristoph Hellwig /* 12197776db1cSKeith Busch * Did we miss an interrupt? 12207776db1cSKeith Busch */ 1221fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1222fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1223fa059b85SKeith Busch else 1224bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1225fa059b85SKeith Busch 1226bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12277776db1cSKeith Busch dev_warn(dev->ctrl.device, 12287776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12297776db1cSKeith Busch req->tag, nvmeq->qid); 1230db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12317776db1cSKeith Busch } 12327776db1cSKeith Busch 12337776db1cSKeith Busch /* 1234fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1235fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1236fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1237db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1238fd634f41SChristoph Hellwig */ 12394244140dSKeith Busch switch (dev->ctrl.state) { 12404244140dSKeith Busch case NVME_CTRL_CONNECTING: 12412036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 12422036f726SKeith Busch /* fall through */ 12432036f726SKeith Busch case NVME_CTRL_DELETING: 1244b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1245fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1246fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 12472036f726SKeith Busch nvme_dev_disable(dev, true); 124827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1249db8c48e4SChristoph Hellwig return BLK_EH_DONE; 125039a9dd81SKeith Busch case NVME_CTRL_RESETTING: 125139a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 12524244140dSKeith Busch default: 12534244140dSKeith Busch break; 1254fd634f41SChristoph Hellwig } 1255fd634f41SChristoph Hellwig 1256fd634f41SChristoph Hellwig /* 1257e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1258e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1259e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 126031c7c7d2SChristoph Hellwig */ 1261f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12621b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 126357dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 126457dacad5SJay Sternberg req->tag, nvmeq->qid); 1265a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1266d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1267e1569a16SKeith Busch 126827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1269db8c48e4SChristoph Hellwig return BLK_EH_DONE; 127057dacad5SJay Sternberg } 127157dacad5SJay Sternberg 1272e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1273e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1274e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1275e7a2a87dSChristoph Hellwig } 12767bf7d778SKeith Busch iod->aborted = 1; 127757dacad5SJay Sternberg 127857dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 127957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 128057dacad5SJay Sternberg cmd.abort.cid = req->tag; 128157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 128257dacad5SJay Sternberg 12831b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12841b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 128557dacad5SJay Sternberg req->tag, nvmeq->qid); 1286e7a2a87dSChristoph Hellwig 1287e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1288eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12896bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12906bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 129131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 129257dacad5SJay Sternberg } 129357dacad5SJay Sternberg 1294e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1295e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1296e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 129757dacad5SJay Sternberg 129857dacad5SJay Sternberg /* 129957dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 130057dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 130157dacad5SJay Sternberg * as the device then is in a faulty state. 130257dacad5SJay Sternberg */ 130357dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 130457dacad5SJay Sternberg } 130557dacad5SJay Sternberg 130657dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 130757dacad5SJay Sternberg { 13088a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 130957dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 131063223078SChristoph Hellwig if (!nvmeq->sq_cmds) 131163223078SChristoph Hellwig return; 13120f238ff5SLogan Gunthorpe 131363223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 131488a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13158a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 131663223078SChristoph Hellwig } else { 13178a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 131863223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13190f238ff5SLogan Gunthorpe } 132057dacad5SJay Sternberg } 132157dacad5SJay Sternberg 132257dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 132357dacad5SJay Sternberg { 132457dacad5SJay Sternberg int i; 132557dacad5SJay Sternberg 1326d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1327d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1328147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 132957dacad5SJay Sternberg } 133057dacad5SJay Sternberg } 133157dacad5SJay Sternberg 133257dacad5SJay Sternberg /** 133357dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 133440581d1aSBart Van Assche * @nvmeq: queue to suspend 133557dacad5SJay Sternberg */ 133657dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 133757dacad5SJay Sternberg { 13384e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 133957dacad5SJay Sternberg return 1; 134057dacad5SJay Sternberg 13414e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1342d1f06f4aSJens Axboe mb(); 134357dacad5SJay Sternberg 13444e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13451c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1346c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13477c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13484e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 134957dacad5SJay Sternberg return 0; 135057dacad5SJay Sternberg } 135157dacad5SJay Sternberg 13528fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 13538fae268bSKeith Busch { 13548fae268bSKeith Busch int i; 13558fae268bSKeith Busch 13568fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 13578fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 13588fae268bSKeith Busch } 13598fae268bSKeith Busch 1360a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 136157dacad5SJay Sternberg { 1362147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 136357dacad5SJay Sternberg 1364a5cdb68cSKeith Busch if (shutdown) 1365a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1366a5cdb68cSKeith Busch else 1367b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 136857dacad5SJay Sternberg 1369bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 137057dacad5SJay Sternberg } 137157dacad5SJay Sternberg 1372fa46c6fbSKeith Busch /* 1373fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 13749210c075SDongli Zhang * that can check this device's completion queues have synced, except 13759210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 13769210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1377fa46c6fbSKeith Busch */ 1378fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1379fa46c6fbSKeith Busch { 1380fa46c6fbSKeith Busch int i; 1381fa46c6fbSKeith Busch 13829210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 13839210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1384324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 13859210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 13869210c075SDongli Zhang } 1387fa46c6fbSKeith Busch } 1388fa46c6fbSKeith Busch 138957dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 139057dacad5SJay Sternberg int entry_size) 139157dacad5SJay Sternberg { 139257dacad5SJay Sternberg int q_depth = dev->q_depth; 13935fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13946c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 139557dacad5SJay Sternberg 139657dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 139757dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13984e523547SBaolin Wang 13996c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 140057dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 140157dacad5SJay Sternberg 140257dacad5SJay Sternberg /* 140357dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 140457dacad5SJay Sternberg * would be better to map queues in system memory with the 140557dacad5SJay Sternberg * original depth 140657dacad5SJay Sternberg */ 140757dacad5SJay Sternberg if (q_depth < 64) 140857dacad5SJay Sternberg return -ENOMEM; 140957dacad5SJay Sternberg } 141057dacad5SJay Sternberg 141157dacad5SJay Sternberg return q_depth; 141257dacad5SJay Sternberg } 141357dacad5SJay Sternberg 141457dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14158a1d09a6SBenjamin Herrenschmidt int qid) 141657dacad5SJay Sternberg { 14170f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1418815c6704SKeith Busch 14190f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14208a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1421bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14220f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14230f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 142463223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 142563223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 142663223078SChristoph Hellwig return 0; 142763223078SChristoph Hellwig } 1428bfac8e9fSAlan Mikhak 14298a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1430bfac8e9fSAlan Mikhak } 14310f238ff5SLogan Gunthorpe } 14320f238ff5SLogan Gunthorpe 14338a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 143457dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 143557dacad5SJay Sternberg if (!nvmeq->sq_cmds) 143657dacad5SJay Sternberg return -ENOMEM; 143757dacad5SJay Sternberg return 0; 143857dacad5SJay Sternberg } 143957dacad5SJay Sternberg 1440a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 144157dacad5SJay Sternberg { 1442147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 144357dacad5SJay Sternberg 144462314e40SKeith Busch if (dev->ctrl.queue_count > qid) 144562314e40SKeith Busch return 0; 144657dacad5SJay Sternberg 1447c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 14488a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 14498a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 145057dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 145157dacad5SJay Sternberg if (!nvmeq->cqes) 145257dacad5SJay Sternberg goto free_nvmeq; 145357dacad5SJay Sternberg 14548a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 145557dacad5SJay Sternberg goto free_cqdma; 145657dacad5SJay Sternberg 145757dacad5SJay Sternberg nvmeq->dev = dev; 14581ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14593a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 146057dacad5SJay Sternberg nvmeq->cq_head = 0; 146157dacad5SJay Sternberg nvmeq->cq_phase = 1; 146257dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 146357dacad5SJay Sternberg nvmeq->qid = qid; 1464d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 146557dacad5SJay Sternberg 1466147b27e4SSagi Grimberg return 0; 146757dacad5SJay Sternberg 146857dacad5SJay Sternberg free_cqdma: 14698a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 147057dacad5SJay Sternberg nvmeq->cq_dma_addr); 147157dacad5SJay Sternberg free_nvmeq: 1472147b27e4SSagi Grimberg return -ENOMEM; 147357dacad5SJay Sternberg } 147457dacad5SJay Sternberg 1475dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 147657dacad5SJay Sternberg { 14770ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14780ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14790ff199cbSChristoph Hellwig 14800ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14810ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14820ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14830ff199cbSChristoph Hellwig } else { 14840ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14850ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14860ff199cbSChristoph Hellwig } 148757dacad5SJay Sternberg } 148857dacad5SJay Sternberg 148957dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 149057dacad5SJay Sternberg { 149157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 149257dacad5SJay Sternberg 149357dacad5SJay Sternberg nvmeq->sq_tail = 0; 149457dacad5SJay Sternberg nvmeq->cq_head = 0; 149557dacad5SJay Sternberg nvmeq->cq_phase = 1; 149657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 14978a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1498f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 149957dacad5SJay Sternberg dev->online_queues++; 15003a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 150157dacad5SJay Sternberg } 150257dacad5SJay Sternberg 15034b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 150457dacad5SJay Sternberg { 150557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 150657dacad5SJay Sternberg int result; 15077c349ddeSKeith Busch u16 vector = 0; 150857dacad5SJay Sternberg 1509d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1510d1ed6aa1SChristoph Hellwig 151122b55601SKeith Busch /* 151222b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 151322b55601SKeith Busch * has only one vector available. 151422b55601SKeith Busch */ 15154b04cc6aSJens Axboe if (!polled) 1516a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15174b04cc6aSJens Axboe else 15187c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15194b04cc6aSJens Axboe 1520a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1521ded45505SKeith Busch if (result) 1522ded45505SKeith Busch return result; 152357dacad5SJay Sternberg 152457dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 152557dacad5SJay Sternberg if (result < 0) 1526ded45505SKeith Busch return result; 1527c80b36cdSEdmund Nadolski if (result) 152857dacad5SJay Sternberg goto release_cq; 152957dacad5SJay Sternberg 1530a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1531161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15324b04cc6aSJens Axboe 15337c349ddeSKeith Busch if (!polled) { 1534dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 153557dacad5SJay Sternberg if (result < 0) 153657dacad5SJay Sternberg goto release_sq; 15374b04cc6aSJens Axboe } 153857dacad5SJay Sternberg 15394e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 154057dacad5SJay Sternberg return result; 154157dacad5SJay Sternberg 154257dacad5SJay Sternberg release_sq: 1543f25a2dfcSJianchao Wang dev->online_queues--; 154457dacad5SJay Sternberg adapter_delete_sq(dev, qid); 154557dacad5SJay Sternberg release_cq: 154657dacad5SJay Sternberg adapter_delete_cq(dev, qid); 154757dacad5SJay Sternberg return result; 154857dacad5SJay Sternberg } 154957dacad5SJay Sternberg 1550f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 155157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 155277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 155357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 15540350815aSChristoph Hellwig .init_request = nvme_init_request, 155557dacad5SJay Sternberg .timeout = nvme_timeout, 155657dacad5SJay Sternberg }; 155757dacad5SJay Sternberg 1558f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1559376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1560376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1561376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1562376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1563376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1564376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1565376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1566c6d962aeSChristoph Hellwig .poll = nvme_poll, 1567dabcefabSJens Axboe }; 1568dabcefabSJens Axboe 156957dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 157057dacad5SJay Sternberg { 15711c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 157269d9a99cSKeith Busch /* 157369d9a99cSKeith Busch * If the controller was reset during removal, it's possible 157469d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 157569d9a99cSKeith Busch * queue to flush these to completion. 157669d9a99cSKeith Busch */ 1577c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15781c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 157957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 158057dacad5SJay Sternberg } 158157dacad5SJay Sternberg } 158257dacad5SJay Sternberg 158357dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 158457dacad5SJay Sternberg { 15851c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 158657dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 158757dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1588e3e9d50cSKeith Busch 158938dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 159057dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 1591d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1592d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1593d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 159457dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 159557dacad5SJay Sternberg 159657dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 159757dacad5SJay Sternberg return -ENOMEM; 159834b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 159957dacad5SJay Sternberg 16001c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16011c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 160257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 160357dacad5SJay Sternberg return -ENOMEM; 160457dacad5SJay Sternberg } 16051c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 160657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16071c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 160857dacad5SJay Sternberg return -ENODEV; 160957dacad5SJay Sternberg } 161057dacad5SJay Sternberg } else 1611c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 161257dacad5SJay Sternberg 161357dacad5SJay Sternberg return 0; 161457dacad5SJay Sternberg } 161557dacad5SJay Sternberg 161697f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 161797f6ef64SXu Yu { 161897f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 161997f6ef64SXu Yu } 162097f6ef64SXu Yu 162197f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 162297f6ef64SXu Yu { 162397f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 162497f6ef64SXu Yu 162597f6ef64SXu Yu if (size <= dev->bar_mapped_size) 162697f6ef64SXu Yu return 0; 162797f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 162897f6ef64SXu Yu return -ENOMEM; 162997f6ef64SXu Yu if (dev->bar) 163097f6ef64SXu Yu iounmap(dev->bar); 163197f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 163297f6ef64SXu Yu if (!dev->bar) { 163397f6ef64SXu Yu dev->bar_mapped_size = 0; 163497f6ef64SXu Yu return -ENOMEM; 163597f6ef64SXu Yu } 163697f6ef64SXu Yu dev->bar_mapped_size = size; 163797f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 163897f6ef64SXu Yu 163997f6ef64SXu Yu return 0; 164097f6ef64SXu Yu } 164197f6ef64SXu Yu 164201ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 164357dacad5SJay Sternberg { 164457dacad5SJay Sternberg int result; 164557dacad5SJay Sternberg u32 aqa; 164657dacad5SJay Sternberg struct nvme_queue *nvmeq; 164757dacad5SJay Sternberg 164897f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 164997f6ef64SXu Yu if (result < 0) 165097f6ef64SXu Yu return result; 165197f6ef64SXu Yu 16528ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 165320d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 165457dacad5SJay Sternberg 16557a67cbeaSChristoph Hellwig if (dev->subsystem && 16567a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16577a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 165857dacad5SJay Sternberg 1659b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 166057dacad5SJay Sternberg if (result < 0) 166157dacad5SJay Sternberg return result; 166257dacad5SJay Sternberg 1663a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1664147b27e4SSagi Grimberg if (result) 1665147b27e4SSagi Grimberg return result; 166657dacad5SJay Sternberg 1667635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1668635333e4SMax Gurtovoy 1669147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 167057dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 167157dacad5SJay Sternberg aqa |= aqa << 16; 167257dacad5SJay Sternberg 16737a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16747a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16757a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 167657dacad5SJay Sternberg 1677c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 167857dacad5SJay Sternberg if (result) 1679d4875622SKeith Busch return result; 168057dacad5SJay Sternberg 168157dacad5SJay Sternberg nvmeq->cq_vector = 0; 1682161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1683dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 168457dacad5SJay Sternberg if (result) { 16857c349ddeSKeith Busch dev->online_queues--; 1686d4875622SKeith Busch return result; 168757dacad5SJay Sternberg } 168857dacad5SJay Sternberg 16894e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 169057dacad5SJay Sternberg return result; 169157dacad5SJay Sternberg } 169257dacad5SJay Sternberg 1693749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 169457dacad5SJay Sternberg { 16954b04cc6aSJens Axboe unsigned i, max, rw_queues; 1696749941f2SChristoph Hellwig int ret = 0; 169757dacad5SJay Sternberg 1698d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1699a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1700749941f2SChristoph Hellwig ret = -ENOMEM; 170157dacad5SJay Sternberg break; 1702749941f2SChristoph Hellwig } 1703749941f2SChristoph Hellwig } 170457dacad5SJay Sternberg 1705d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1706e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1707e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1708e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17094b04cc6aSJens Axboe } else { 17104b04cc6aSJens Axboe rw_queues = max; 17114b04cc6aSJens Axboe } 17124b04cc6aSJens Axboe 1713949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17144b04cc6aSJens Axboe bool polled = i > rw_queues; 17154b04cc6aSJens Axboe 17164b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1717d4875622SKeith Busch if (ret) 171857dacad5SJay Sternberg break; 171957dacad5SJay Sternberg } 172057dacad5SJay Sternberg 1721749941f2SChristoph Hellwig /* 1722749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17238adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17248adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1725749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1726749941f2SChristoph Hellwig */ 1727749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 172857dacad5SJay Sternberg } 172957dacad5SJay Sternberg 1730202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1731202021c1SStephen Bates struct device_attribute *attr, 1732202021c1SStephen Bates char *buf) 1733202021c1SStephen Bates { 1734202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1735202021c1SStephen Bates 1736c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1737202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1738202021c1SStephen Bates } 1739202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1740202021c1SStephen Bates 174188de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 174257dacad5SJay Sternberg { 174388de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 174488de4598SChristoph Hellwig 174588de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 174688de4598SChristoph Hellwig } 174788de4598SChristoph Hellwig 174888de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 174988de4598SChristoph Hellwig { 175088de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 175188de4598SChristoph Hellwig } 175288de4598SChristoph Hellwig 1753f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 175457dacad5SJay Sternberg { 175588de4598SChristoph Hellwig u64 size, offset; 175657dacad5SJay Sternberg resource_size_t bar_size; 175757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17588969f1f8SChristoph Hellwig int bar; 175957dacad5SJay Sternberg 17609fe5c59fSKeith Busch if (dev->cmb_size) 17619fe5c59fSKeith Busch return; 17629fe5c59fSKeith Busch 17637a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1764f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1765f65efd6dSChristoph Hellwig return; 1766202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 176757dacad5SJay Sternberg 176888de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 176988de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17708969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17718969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 177257dacad5SJay Sternberg 177357dacad5SJay Sternberg if (offset > bar_size) 1774f65efd6dSChristoph Hellwig return; 177557dacad5SJay Sternberg 177657dacad5SJay Sternberg /* 177757dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 177857dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 177957dacad5SJay Sternberg * the reported size of the BAR 178057dacad5SJay Sternberg */ 178157dacad5SJay Sternberg if (size > bar_size - offset) 178257dacad5SJay Sternberg size = bar_size - offset; 178357dacad5SJay Sternberg 17840f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 17850f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 17860f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1787f65efd6dSChristoph Hellwig return; 17880f238ff5SLogan Gunthorpe } 17890f238ff5SLogan Gunthorpe 179057dacad5SJay Sternberg dev->cmb_size = size; 17910f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 17920f238ff5SLogan Gunthorpe 17930f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 17940f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 17950f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1796f65efd6dSChristoph Hellwig 1797f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1798f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1799f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1800f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 180157dacad5SJay Sternberg } 180257dacad5SJay Sternberg 180357dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 180457dacad5SJay Sternberg { 18050f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1806f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1807f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18080f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1809f63572dfSJon Derrick } 181057dacad5SJay Sternberg } 181157dacad5SJay Sternberg 181287ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 181357dacad5SJay Sternberg { 18146c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18154033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 181687ad72a5SChristoph Hellwig struct nvme_command c; 181787ad72a5SChristoph Hellwig int ret; 181887ad72a5SChristoph Hellwig 181987ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 182087ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 182187ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 182287ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 18236c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 182487ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 182587ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 182687ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 182787ad72a5SChristoph Hellwig 182887ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 182987ad72a5SChristoph Hellwig if (ret) { 183087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 183187ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 183287ad72a5SChristoph Hellwig ret, bits); 183387ad72a5SChristoph Hellwig } 183487ad72a5SChristoph Hellwig return ret; 183587ad72a5SChristoph Hellwig } 183687ad72a5SChristoph Hellwig 183787ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 183887ad72a5SChristoph Hellwig { 183987ad72a5SChristoph Hellwig int i; 184087ad72a5SChristoph Hellwig 184187ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 184287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 18436c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 184487ad72a5SChristoph Hellwig 1845cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1846cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1847cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 184887ad72a5SChristoph Hellwig } 184987ad72a5SChristoph Hellwig 185087ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 185187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18524033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18534033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18544033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 185587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18567e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 185787ad72a5SChristoph Hellwig } 185887ad72a5SChristoph Hellwig 185992dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 186092dc6895SChristoph Hellwig u32 chunk_size) 186187ad72a5SChristoph Hellwig { 186287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 186392dc6895SChristoph Hellwig u32 max_entries, len; 18644033f35dSChristoph Hellwig dma_addr_t descs_dma; 18652ee0e4edSDan Carpenter int i = 0; 186687ad72a5SChristoph Hellwig void **bufs; 18676fbcde66SMinwoo Im u64 size, tmp; 186887ad72a5SChristoph Hellwig 186987ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 187087ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 187187ad72a5SChristoph Hellwig max_entries = tmp; 1872044a9df1SChristoph Hellwig 1873044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1874044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1875044a9df1SChristoph Hellwig 1876750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 18774033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 187887ad72a5SChristoph Hellwig if (!descs) 187987ad72a5SChristoph Hellwig goto out; 188087ad72a5SChristoph Hellwig 188187ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 188287ad72a5SChristoph Hellwig if (!bufs) 188387ad72a5SChristoph Hellwig goto out_free_descs; 188487ad72a5SChristoph Hellwig 1885244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 188687ad72a5SChristoph Hellwig dma_addr_t dma_addr; 188787ad72a5SChristoph Hellwig 188850cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 188987ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 189087ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 189187ad72a5SChristoph Hellwig if (!bufs[i]) 189287ad72a5SChristoph Hellwig break; 189387ad72a5SChristoph Hellwig 189487ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 18956c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 189687ad72a5SChristoph Hellwig i++; 189787ad72a5SChristoph Hellwig } 189887ad72a5SChristoph Hellwig 189992dc6895SChristoph Hellwig if (!size) 190087ad72a5SChristoph Hellwig goto out_free_bufs; 190187ad72a5SChristoph Hellwig 190287ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 190387ad72a5SChristoph Hellwig dev->host_mem_size = size; 190487ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19054033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 190687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 190787ad72a5SChristoph Hellwig return 0; 190887ad72a5SChristoph Hellwig 190987ad72a5SChristoph Hellwig out_free_bufs: 191087ad72a5SChristoph Hellwig while (--i >= 0) { 19116c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 191287ad72a5SChristoph Hellwig 1913cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1914cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1915cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191687ad72a5SChristoph Hellwig } 191787ad72a5SChristoph Hellwig 191887ad72a5SChristoph Hellwig kfree(bufs); 191987ad72a5SChristoph Hellwig out_free_descs: 19204033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19214033f35dSChristoph Hellwig descs_dma); 192287ad72a5SChristoph Hellwig out: 192387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 192487ad72a5SChristoph Hellwig return -ENOMEM; 192587ad72a5SChristoph Hellwig } 192687ad72a5SChristoph Hellwig 192792dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 192892dc6895SChristoph Hellwig { 19299dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 19309dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 19319dc54a0dSChaitanya Kulkarni u64 chunk_size; 193292dc6895SChristoph Hellwig 193392dc6895SChristoph Hellwig /* start big and work our way down */ 19349dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 193592dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 193692dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 193792dc6895SChristoph Hellwig return 0; 193892dc6895SChristoph Hellwig nvme_free_host_mem(dev); 193992dc6895SChristoph Hellwig } 194092dc6895SChristoph Hellwig } 194192dc6895SChristoph Hellwig 194292dc6895SChristoph Hellwig return -ENOMEM; 194392dc6895SChristoph Hellwig } 194492dc6895SChristoph Hellwig 19459620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 194687ad72a5SChristoph Hellwig { 194787ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 194887ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 194987ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 195087ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19516fbcde66SMinwoo Im int ret; 195287ad72a5SChristoph Hellwig 195387ad72a5SChristoph Hellwig preferred = min(preferred, max); 195487ad72a5SChristoph Hellwig if (min > max) { 195587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 195687ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 195787ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 195887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19599620cfbaSChristoph Hellwig return 0; 196087ad72a5SChristoph Hellwig } 196187ad72a5SChristoph Hellwig 196287ad72a5SChristoph Hellwig /* 196387ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 196487ad72a5SChristoph Hellwig */ 196587ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 196687ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 196787ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 196887ad72a5SChristoph Hellwig else 196987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 197087ad72a5SChristoph Hellwig } 197187ad72a5SChristoph Hellwig 197287ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 197392dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 197492dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 197592dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19769620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 197787ad72a5SChristoph Hellwig } 197887ad72a5SChristoph Hellwig 197992dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 198092dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 198192dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 198292dc6895SChristoph Hellwig } 198392dc6895SChristoph Hellwig 19849620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19859620cfbaSChristoph Hellwig if (ret) 198687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19879620cfbaSChristoph Hellwig return ret; 198857dacad5SJay Sternberg } 198957dacad5SJay Sternberg 1990612b7286SMing Lei /* 1991612b7286SMing Lei * nirqs is the number of interrupts available for write and read 1992612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 1993612b7286SMing Lei */ 1994612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 19953b6592f7SJens Axboe { 1996612b7286SMing Lei struct nvme_dev *dev = affd->priv; 19972a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 1998c45b1fa2SMing Lei 19993b6592f7SJens Axboe /* 2000ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2001612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2002612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2003612b7286SMing Lei * 2004612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2005612b7286SMing Lei * write and read queues. 2006612b7286SMing Lei * 2007612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2008612b7286SMing Lei * queue. 20093b6592f7SJens Axboe */ 2010612b7286SMing Lei if (!nrirqs) { 2011612b7286SMing Lei nrirqs = 1; 2012612b7286SMing Lei nr_read_queues = 0; 20132a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2014612b7286SMing Lei nr_read_queues = 0; 20152a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2016612b7286SMing Lei nr_read_queues = 1; 20173b6592f7SJens Axboe } else { 20182a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 20193b6592f7SJens Axboe } 2020612b7286SMing Lei 2021612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2022612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2023612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2024612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2025612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20263b6592f7SJens Axboe } 20273b6592f7SJens Axboe 20286451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20293b6592f7SJens Axboe { 20303b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20313b6592f7SJens Axboe struct irq_affinity affd = { 20323b6592f7SJens Axboe .pre_vectors = 1, 2033612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2034612b7286SMing Lei .priv = dev, 20353b6592f7SJens Axboe }; 20366451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20376451fe73SJens Axboe 20386451fe73SJens Axboe /* 20396451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20406451fe73SJens Axboe * queue left over for non-polled IO. 20416451fe73SJens Axboe */ 20422a5bcfddSWeiping Zhang this_p_queues = dev->nr_poll_queues; 20436451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20446451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20456451fe73SJens Axboe irq_queues = 1; 20466451fe73SJens Axboe } else { 2047c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20486451fe73SJens Axboe } 20496451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20503b6592f7SJens Axboe 2051612b7286SMing Lei /* Initialize for the single interrupt case */ 2052612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2053612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20543b6592f7SJens Axboe 205566341331SBenjamin Herrenschmidt /* 205666341331SBenjamin Herrenschmidt * Some Apple controllers require all queues to use the 205766341331SBenjamin Herrenschmidt * first vector. 205866341331SBenjamin Herrenschmidt */ 205966341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR) 206066341331SBenjamin Herrenschmidt irq_queues = 1; 206166341331SBenjamin Herrenschmidt 2062612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20633b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20643b6592f7SJens Axboe } 20653b6592f7SJens Axboe 20668fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20678fae268bSKeith Busch { 20688fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20698fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20708fae268bSKeith Busch } 20718fae268bSKeith Busch 20722a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 20732a5bcfddSWeiping Zhang { 20742a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 20752a5bcfddSWeiping Zhang } 20762a5bcfddSWeiping Zhang 207757dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 207857dacad5SJay Sternberg { 2079147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 208057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 20812a5bcfddSWeiping Zhang unsigned int nr_io_queues; 208297f6ef64SXu Yu unsigned long size; 20832a5bcfddSWeiping Zhang int result; 208457dacad5SJay Sternberg 20852a5bcfddSWeiping Zhang /* 20862a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 20872a5bcfddSWeiping Zhang * stable values to work with. 20882a5bcfddSWeiping Zhang */ 20892a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 20902a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2091d38e9f04SBenjamin Herrenschmidt 2092d38e9f04SBenjamin Herrenschmidt /* 2093d38e9f04SBenjamin Herrenschmidt * If tags are shared with admin queue (Apple bug), then 2094d38e9f04SBenjamin Herrenschmidt * make sure we only use one IO queue. 2095d38e9f04SBenjamin Herrenschmidt */ 2096d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2097d38e9f04SBenjamin Herrenschmidt nr_io_queues = 1; 20982a5bcfddSWeiping Zhang else 20992a5bcfddSWeiping Zhang nr_io_queues = min(nvme_max_io_queues(dev), 21002a5bcfddSWeiping Zhang dev->nr_allocated_queues - 1); 2101d38e9f04SBenjamin Herrenschmidt 21029a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21039a0be7abSChristoph Hellwig if (result < 0) 210457dacad5SJay Sternberg return result; 21059a0be7abSChristoph Hellwig 2106f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2107a5229050SKeith Busch return 0; 210857dacad5SJay Sternberg 21094e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21104e224106SChristoph Hellwig 21110f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 211257dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 211357dacad5SJay Sternberg sizeof(struct nvme_command)); 211457dacad5SJay Sternberg if (result > 0) 211557dacad5SJay Sternberg dev->q_depth = result; 211657dacad5SJay Sternberg else 21170f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 211857dacad5SJay Sternberg } 211957dacad5SJay Sternberg 212057dacad5SJay Sternberg do { 212197f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 212297f6ef64SXu Yu result = nvme_remap_bar(dev, size); 212397f6ef64SXu Yu if (!result) 212457dacad5SJay Sternberg break; 212557dacad5SJay Sternberg if (!--nr_io_queues) 212657dacad5SJay Sternberg return -ENOMEM; 212757dacad5SJay Sternberg } while (1); 212857dacad5SJay Sternberg adminq->q_db = dev->dbs; 212957dacad5SJay Sternberg 21308fae268bSKeith Busch retry: 213157dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21320ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 213357dacad5SJay Sternberg 213457dacad5SJay Sternberg /* 213557dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 213657dacad5SJay Sternberg * setting up the full range we need. 213757dacad5SJay Sternberg */ 2138dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21393b6592f7SJens Axboe 21403b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 214122b55601SKeith Busch if (result <= 0) 2142dca51e78SChristoph Hellwig return -EIO; 21433b6592f7SJens Axboe 214422b55601SKeith Busch dev->num_vecs = result; 21454b04cc6aSJens Axboe result = max(result - 1, 1); 2146e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 214757dacad5SJay Sternberg 214857dacad5SJay Sternberg /* 214957dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 215057dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 215157dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 215257dacad5SJay Sternberg * number of interrupts. 215357dacad5SJay Sternberg */ 2154dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21557c349ddeSKeith Busch if (result) 2156d4875622SKeith Busch return result; 21574e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21588fae268bSKeith Busch 21598fae268bSKeith Busch result = nvme_create_io_queues(dev); 21608fae268bSKeith Busch if (result || dev->online_queues < 2) 21618fae268bSKeith Busch return result; 21628fae268bSKeith Busch 21638fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21648fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21658fae268bSKeith Busch nvme_disable_io_queues(dev); 21668fae268bSKeith Busch nvme_suspend_io_queues(dev); 21678fae268bSKeith Busch goto retry; 21688fae268bSKeith Busch } 21698fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21708fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21718fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21728fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21738fae268bSKeith Busch return 0; 217457dacad5SJay Sternberg } 217557dacad5SJay Sternberg 21762a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2177db3cbfffSKeith Busch { 2178db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2179db3cbfffSKeith Busch 2180db3cbfffSKeith Busch blk_mq_free_request(req); 2181d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2182db3cbfffSKeith Busch } 2183db3cbfffSKeith Busch 21842a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2185db3cbfffSKeith Busch { 2186db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2187db3cbfffSKeith Busch 2188d1ed6aa1SChristoph Hellwig if (error) 2189d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2190db3cbfffSKeith Busch 2191db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2192db3cbfffSKeith Busch } 2193db3cbfffSKeith Busch 2194db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2195db3cbfffSKeith Busch { 2196db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2197db3cbfffSKeith Busch struct request *req; 2198db3cbfffSKeith Busch struct nvme_command cmd; 2199db3cbfffSKeith Busch 2200db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2201db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2202db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2203db3cbfffSKeith Busch 2204eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2205db3cbfffSKeith Busch if (IS_ERR(req)) 2206db3cbfffSKeith Busch return PTR_ERR(req); 2207db3cbfffSKeith Busch 2208db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2209db3cbfffSKeith Busch req->end_io_data = nvmeq; 2210db3cbfffSKeith Busch 2211d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2212db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2213db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2214db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2215db3cbfffSKeith Busch return 0; 2216db3cbfffSKeith Busch } 2217db3cbfffSKeith Busch 22188fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2219db3cbfffSKeith Busch { 22205271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2221db3cbfffSKeith Busch unsigned long timeout; 2222db3cbfffSKeith Busch 2223db3cbfffSKeith Busch retry: 2224db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22255271edd4SChristoph Hellwig while (nr_queues > 0) { 22265271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2227db3cbfffSKeith Busch break; 22285271edd4SChristoph Hellwig nr_queues--; 22295271edd4SChristoph Hellwig sent++; 22305271edd4SChristoph Hellwig } 2231d1ed6aa1SChristoph Hellwig while (sent) { 2232d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2233d1ed6aa1SChristoph Hellwig 2234d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22355271edd4SChristoph Hellwig timeout); 2236db3cbfffSKeith Busch if (timeout == 0) 22375271edd4SChristoph Hellwig return false; 2238d1ed6aa1SChristoph Hellwig 2239d1ed6aa1SChristoph Hellwig sent--; 22405271edd4SChristoph Hellwig if (nr_queues) 2241db3cbfffSKeith Busch goto retry; 2242db3cbfffSKeith Busch } 22435271edd4SChristoph Hellwig return true; 2244db3cbfffSKeith Busch } 2245db3cbfffSKeith Busch 22465d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 224757dacad5SJay Sternberg { 22482b1b7e78SJianchao Wang int ret; 22492b1b7e78SJianchao Wang 22505bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2251c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 225257dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 22538fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2254ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2255ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 225657dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2257d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 225861f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 225961f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2260d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 226157dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 226257dacad5SJay Sternberg dev->tagset.driver_data = dev; 226357dacad5SJay Sternberg 2264d38e9f04SBenjamin Herrenschmidt /* 2265d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2266d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2267d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2268d38e9f04SBenjamin Herrenschmidt */ 2269d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2270d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2271d38e9f04SBenjamin Herrenschmidt 22722b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22732b1b7e78SJianchao Wang if (ret) { 22742b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22752b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22765d02a5c1SKeith Busch return; 22772b1b7e78SJianchao Wang } 22785bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2279949928c1SKeith Busch } else { 2280949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2281949928c1SKeith Busch 2282949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2283949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 228457dacad5SJay Sternberg } 2285949928c1SKeith Busch 2286e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 228757dacad5SJay Sternberg } 228857dacad5SJay Sternberg 2289b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 229057dacad5SJay Sternberg { 2291b00a726aSKeith Busch int result = -ENOMEM; 229257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 229357dacad5SJay Sternberg 229457dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 229557dacad5SJay Sternberg return result; 229657dacad5SJay Sternberg 229757dacad5SJay Sternberg pci_set_master(pdev); 229857dacad5SJay Sternberg 22994fe06923SChristoph Hellwig if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64))) 230057dacad5SJay Sternberg goto disable; 230157dacad5SJay Sternberg 23027a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 230357dacad5SJay Sternberg result = -ENODEV; 2304b00a726aSKeith Busch goto disable; 230557dacad5SJay Sternberg } 230657dacad5SJay Sternberg 230757dacad5SJay Sternberg /* 2308a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2309a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2310a5229050SKeith Busch * adjust this later. 231157dacad5SJay Sternberg */ 2312dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2313dca51e78SChristoph Hellwig if (result < 0) 2314dca51e78SChristoph Hellwig return result; 231557dacad5SJay Sternberg 231620d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23177a67cbeaSChristoph Hellwig 231861f3b896SChaitanya Kulkarni dev->q_depth = min_t(u16, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2319b27c1e68Sweiping zhang io_queue_depth); 2320aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 232120d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23227a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23231f390c1fSStephan Günther 23241f390c1fSStephan Günther /* 232566341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 232666341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 232766341331SBenjamin Herrenschmidt * so we don't bother updating it here. 232866341331SBenjamin Herrenschmidt */ 232966341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 233066341331SBenjamin Herrenschmidt dev->io_sqes = 7; 233166341331SBenjamin Herrenschmidt else 2332c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 23331f390c1fSStephan Günther 23341f390c1fSStephan Günther /* 23351f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23361f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23371f390c1fSStephan Günther */ 23381f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23391f390c1fSStephan Günther dev->q_depth = 2; 23409bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23419bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23421f390c1fSStephan Günther dev->q_depth); 2343d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2344d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 234520d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2346d554b5e1SMartin K. Petersen dev->q_depth = 64; 2347d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2348d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23491f390c1fSStephan Günther } 23501f390c1fSStephan Günther 2351d38e9f04SBenjamin Herrenschmidt /* 2352d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2353d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2354d38e9f04SBenjamin Herrenschmidt */ 2355d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2356d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2357d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2358d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2359d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2360d38e9f04SBenjamin Herrenschmidt } 2361d38e9f04SBenjamin Herrenschmidt 2362d38e9f04SBenjamin Herrenschmidt 2363f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2364202021c1SStephen Bates 2365a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2366a0a3408eSKeith Busch pci_save_state(pdev); 236757dacad5SJay Sternberg return 0; 236857dacad5SJay Sternberg 236957dacad5SJay Sternberg disable: 237057dacad5SJay Sternberg pci_disable_device(pdev); 237157dacad5SJay Sternberg return result; 237257dacad5SJay Sternberg } 237357dacad5SJay Sternberg 237457dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 237557dacad5SJay Sternberg { 2376b00a726aSKeith Busch if (dev->bar) 2377b00a726aSKeith Busch iounmap(dev->bar); 2378a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2379b00a726aSKeith Busch } 2380b00a726aSKeith Busch 2381b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2382b00a726aSKeith Busch { 238357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 238457dacad5SJay Sternberg 2385dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 238657dacad5SJay Sternberg 2387a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2388a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 238957dacad5SJay Sternberg pci_disable_device(pdev); 239057dacad5SJay Sternberg } 2391a0a3408eSKeith Busch } 239257dacad5SJay Sternberg 2393a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 239457dacad5SJay Sternberg { 2395e43269e6SKeith Busch bool dead = true, freeze = false; 2396302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 239757dacad5SJay Sternberg 239877bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2399302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2400302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2401302ad8ccSKeith Busch 2402ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2403e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2404e43269e6SKeith Busch freeze = true; 2405302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2406e43269e6SKeith Busch } 2407302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2408302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 240957dacad5SJay Sternberg } 2410c21377f8SGabriel Krisman Bertazi 2411302ad8ccSKeith Busch /* 2412302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2413302ad8ccSKeith Busch * doing a safe shutdown. 2414302ad8ccSKeith Busch */ 2415e43269e6SKeith Busch if (!dead && shutdown && freeze) 2416302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 241787ad72a5SChristoph Hellwig 24189a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24199a915a5bSJianchao Wang 242064ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24218fae268bSKeith Busch nvme_disable_io_queues(dev); 2422a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 242357dacad5SJay Sternberg } 24248fae268bSKeith Busch nvme_suspend_io_queues(dev); 24258fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2426b00a726aSKeith Busch nvme_pci_disable(dev); 2427fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 242857dacad5SJay Sternberg 2429e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2430e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2431622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2432622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2433302ad8ccSKeith Busch 2434302ad8ccSKeith Busch /* 2435302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2436302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2437302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2438302ad8ccSKeith Busch */ 2439c8e9e9b7SKeith Busch if (shutdown) { 2440302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2441c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2442c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2443c8e9e9b7SKeith Busch } 244477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 244557dacad5SJay Sternberg } 244657dacad5SJay Sternberg 2447c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2448c1ac9a4bSKeith Busch { 2449c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2450c1ac9a4bSKeith Busch return -EBUSY; 2451c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2452c1ac9a4bSKeith Busch return 0; 2453c1ac9a4bSKeith Busch } 2454c1ac9a4bSKeith Busch 245557dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 245657dacad5SJay Sternberg { 245757dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 245857dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 245957dacad5SJay Sternberg if (!dev->prp_page_pool) 246057dacad5SJay Sternberg return -ENOMEM; 246157dacad5SJay Sternberg 246257dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 246357dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 246457dacad5SJay Sternberg 256, 256, 0); 246557dacad5SJay Sternberg if (!dev->prp_small_pool) { 246657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 246757dacad5SJay Sternberg return -ENOMEM; 246857dacad5SJay Sternberg } 246957dacad5SJay Sternberg return 0; 247057dacad5SJay Sternberg } 247157dacad5SJay Sternberg 247257dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 247357dacad5SJay Sternberg { 247457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 247557dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 247657dacad5SJay Sternberg } 247757dacad5SJay Sternberg 2478770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2479770597ecSKeith Busch { 2480770597ecSKeith Busch if (dev->tagset.tags) 2481770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2482770597ecSKeith Busch dev->ctrl.tagset = NULL; 2483770597ecSKeith Busch } 2484770597ecSKeith Busch 24851673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 248657dacad5SJay Sternberg { 24871673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 248857dacad5SJay Sternberg 2489f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2490770597ecSKeith Busch nvme_free_tagset(dev); 24911c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24921c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2493e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2494943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2495253fd4acSIsrael Rukshin put_device(dev->dev); 2496253fd4acSIsrael Rukshin kfree(dev->queues); 249757dacad5SJay Sternberg kfree(dev); 249857dacad5SJay Sternberg } 249957dacad5SJay Sternberg 25007c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2501f58944e2SKeith Busch { 2502c1ac9a4bSKeith Busch /* 2503c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2504c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2505c1ac9a4bSKeith Busch */ 2506c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2507d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 250869d9a99cSKeith Busch nvme_dev_disable(dev, false); 25099f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 251003e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2511f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2512f58944e2SKeith Busch } 2513f58944e2SKeith Busch 2514fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 251557dacad5SJay Sternberg { 2516d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2517d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2518a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2519e71afda4SChaitanya Kulkarni int result; 252057dacad5SJay Sternberg 2521e71afda4SChaitanya Kulkarni if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) { 2522e71afda4SChaitanya Kulkarni result = -ENODEV; 2523fd634f41SChristoph Hellwig goto out; 2524e71afda4SChaitanya Kulkarni } 2525fd634f41SChristoph Hellwig 2526fd634f41SChristoph Hellwig /* 2527fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2528fd634f41SChristoph Hellwig * moving on. 2529fd634f41SChristoph Hellwig */ 2530b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2531a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2532d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2533fd634f41SChristoph Hellwig 25345c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2535b00a726aSKeith Busch result = nvme_pci_enable(dev); 253657dacad5SJay Sternberg if (result) 25374726bcf3SKeith Busch goto out_unlock; 253857dacad5SJay Sternberg 253901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 254057dacad5SJay Sternberg if (result) 25414726bcf3SKeith Busch goto out_unlock; 254257dacad5SJay Sternberg 254357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 254457dacad5SJay Sternberg if (result) 25454726bcf3SKeith Busch goto out_unlock; 254657dacad5SJay Sternberg 2547943e942eSJens Axboe /* 2548943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2549943e942eSJens Axboe * over a single page. 2550943e942eSJens Axboe */ 25517637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 25527637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2553943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2554a48bc520SChristoph Hellwig 2555a48bc520SChristoph Hellwig /* 2556a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2557a48bc520SChristoph Hellwig */ 2558a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 2559a48bc520SChristoph Hellwig 25605c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25615c959d73SKeith Busch 25625c959d73SKeith Busch /* 25635c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25645c959d73SKeith Busch * initializing procedure here. 25655c959d73SKeith Busch */ 25665c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25675c959d73SKeith Busch dev_warn(dev->ctrl.device, 25685c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2569cee6c269SMinwoo Im result = -EBUSY; 25705c959d73SKeith Busch goto out; 25715c959d73SKeith Busch } 2572943e942eSJens Axboe 257395093350SMax Gurtovoy /* 257495093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 257595093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 257695093350SMax Gurtovoy */ 257795093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 257895093350SMax Gurtovoy 2579ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2580ce4541f4SChristoph Hellwig if (result) 2581f58944e2SKeith Busch goto out; 2582ce4541f4SChristoph Hellwig 2583e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2584e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25854f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25864f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2587e286bcfcSScott Bauer else if (was_suspend) 25884f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2589e286bcfcSScott Bauer } else { 2590e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2591e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2592e286bcfcSScott Bauer } 2593a98e58e5SScott Bauer 2594f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2595f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2596f9f38e33SHelen Koike if (result) 2597f9f38e33SHelen Koike dev_warn(dev->dev, 2598f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2599f9f38e33SHelen Koike } 2600f9f38e33SHelen Koike 26019620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 26029620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 26039620cfbaSChristoph Hellwig if (result < 0) 26049620cfbaSChristoph Hellwig goto out; 26059620cfbaSChristoph Hellwig } 260687ad72a5SChristoph Hellwig 260757dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 260857dacad5SJay Sternberg if (result) 2609f58944e2SKeith Busch goto out; 261057dacad5SJay Sternberg 261121f033f7SKeith Busch /* 261257dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 261357dacad5SJay Sternberg * any working I/O queue. 261457dacad5SJay Sternberg */ 261557dacad5SJay Sternberg if (dev->online_queues < 2) { 26161b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 26173b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 26185bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2619770597ecSKeith Busch nvme_free_tagset(dev); 262057dacad5SJay Sternberg } else { 262125646264SKeith Busch nvme_start_queues(&dev->ctrl); 2622302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 26235d02a5c1SKeith Busch nvme_dev_add(dev); 2624302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 262557dacad5SJay Sternberg } 262657dacad5SJay Sternberg 26272b1b7e78SJianchao Wang /* 26282b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26292b1b7e78SJianchao Wang * recovery. 26302b1b7e78SJianchao Wang */ 26315d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 26322b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26335d02a5c1SKeith Busch "failed to mark controller live state\n"); 2634e71afda4SChaitanya Kulkarni result = -ENODEV; 2635bb8d261eSChristoph Hellwig goto out; 2636bb8d261eSChristoph Hellwig } 263792911a55SChristoph Hellwig 2638d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 263957dacad5SJay Sternberg return; 264057dacad5SJay Sternberg 26414726bcf3SKeith Busch out_unlock: 26424726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 264357dacad5SJay Sternberg out: 26447c1ce408SChaitanya Kulkarni if (result) 26457c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 26467c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 26477c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 264857dacad5SJay Sternberg } 264957dacad5SJay Sternberg 26505c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 265157dacad5SJay Sternberg { 26525c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 265357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 265457dacad5SJay Sternberg 265557dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2656921920abSKeith Busch device_release_driver(&pdev->dev); 26571673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 265857dacad5SJay Sternberg } 265957dacad5SJay Sternberg 26601c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 266157dacad5SJay Sternberg { 26621c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26631c63dc66SChristoph Hellwig return 0; 266457dacad5SJay Sternberg } 26651c63dc66SChristoph Hellwig 26665fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26675fd4ce1bSChristoph Hellwig { 26685fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26695fd4ce1bSChristoph Hellwig return 0; 26705fd4ce1bSChristoph Hellwig } 26715fd4ce1bSChristoph Hellwig 26727fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26737fd8930fSChristoph Hellwig { 26743a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 26757fd8930fSChristoph Hellwig return 0; 26767fd8930fSChristoph Hellwig } 26777fd8930fSChristoph Hellwig 267897c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 267997c12223SKeith Busch { 268097c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 268197c12223SKeith Busch 26822db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 268397c12223SKeith Busch } 268497c12223SKeith Busch 26851c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26861a353d85SMing Lin .name = "pcie", 2687e439bb12SSagi Grimberg .module = THIS_MODULE, 2688e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2689e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26901c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26915fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26927fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26931673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2694f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 269597c12223SKeith Busch .get_address = nvme_pci_get_address, 26961c63dc66SChristoph Hellwig }; 269757dacad5SJay Sternberg 2698b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2699b00a726aSKeith Busch { 2700b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2701b00a726aSKeith Busch 2702a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2703b00a726aSKeith Busch return -ENODEV; 2704b00a726aSKeith Busch 270597f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2706b00a726aSKeith Busch goto release; 2707b00a726aSKeith Busch 2708b00a726aSKeith Busch return 0; 2709b00a726aSKeith Busch release: 2710a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2711b00a726aSKeith Busch return -ENODEV; 2712b00a726aSKeith Busch } 2713b00a726aSKeith Busch 27148427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2715ff5350a8SAndy Lutomirski { 2716ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2717ff5350a8SAndy Lutomirski /* 2718ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2719ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2720ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2721ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2722ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2723ff5350a8SAndy Lutomirski * laptops. 2724ff5350a8SAndy Lutomirski */ 2725ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2726ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2727ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2728ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27298427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27308427bbc2SKai-Heng Feng /* 27318427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2732467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2733467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2734467c77d4SJarosław Janik * ASUS PRIME Z370-A 27358427bbc2SKai-Heng Feng */ 27368427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2737467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2738467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27398427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 27401fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 27411fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 27421fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 27431fae37acSShyjumon N /* 27441fae37acSShyjumon N * Forcing to use host managed nvme power settings for 27451fae37acSShyjumon N * lowest idle power with quick resume latency on 27461fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 27471fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 27481fae37acSShyjumon N */ 27491fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 27501fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 27511fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2752ff5350a8SAndy Lutomirski } 2753ff5350a8SAndy Lutomirski 2754ff5350a8SAndy Lutomirski return 0; 2755ff5350a8SAndy Lutomirski } 2756ff5350a8SAndy Lutomirski 275718119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 275818119775SKeith Busch { 275918119775SKeith Busch struct nvme_dev *dev = data; 276080f513b5SKeith Busch 2761bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 276218119775SKeith Busch flush_work(&dev->ctrl.scan_work); 276380f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 276418119775SKeith Busch } 276518119775SKeith Busch 276657dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 276757dacad5SJay Sternberg { 276857dacad5SJay Sternberg int node, result = -ENOMEM; 276957dacad5SJay Sternberg struct nvme_dev *dev; 2770ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2771943e942eSJens Axboe size_t alloc_size; 277257dacad5SJay Sternberg 277357dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 277457dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27752fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 277657dacad5SJay Sternberg 277757dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 277857dacad5SJay Sternberg if (!dev) 277957dacad5SJay Sternberg return -ENOMEM; 2780147b27e4SSagi Grimberg 27812a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 27822a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 27832a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 27842a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 27852a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 278657dacad5SJay Sternberg if (!dev->queues) 278757dacad5SJay Sternberg goto free; 278857dacad5SJay Sternberg 278957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 279057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 279157dacad5SJay Sternberg 2792b00a726aSKeith Busch result = nvme_dev_map(dev); 2793b00a726aSKeith Busch if (result) 2794b00c9b7aSChristophe JAILLET goto put_pci; 2795b00a726aSKeith Busch 2796d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27975c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 279877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2799f3ca80fcSChristoph Hellwig 2800f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2801f3ca80fcSChristoph Hellwig if (result) 2802b00c9b7aSChristophe JAILLET goto unmap; 2803f3ca80fcSChristoph Hellwig 28048427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2805ff5350a8SAndy Lutomirski 2806943e942eSJens Axboe /* 2807943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2808943e942eSJens Axboe * command we support. 2809943e942eSJens Axboe */ 2810b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 2811943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2812943e942eSJens Axboe 2813943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2814943e942eSJens Axboe mempool_kfree, 2815943e942eSJens Axboe (void *) alloc_size, 2816943e942eSJens Axboe GFP_KERNEL, node); 2817943e942eSJens Axboe if (!dev->iod_mempool) { 2818943e942eSJens Axboe result = -ENOMEM; 2819943e942eSJens Axboe goto release_pools; 2820943e942eSJens Axboe } 2821943e942eSJens Axboe 2822b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2823b6e44b4cSKeith Busch quirks); 2824b6e44b4cSKeith Busch if (result) 2825b6e44b4cSKeith Busch goto release_mempool; 2826b6e44b4cSKeith Busch 28271b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 28281b3c47c1SSagi Grimberg 2829bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 283018119775SKeith Busch async_schedule(nvme_async_probe, dev); 28314caff8fcSSagi Grimberg 283257dacad5SJay Sternberg return 0; 283357dacad5SJay Sternberg 2834b6e44b4cSKeith Busch release_mempool: 2835b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 283657dacad5SJay Sternberg release_pools: 283757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2838b00c9b7aSChristophe JAILLET unmap: 2839b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 284057dacad5SJay Sternberg put_pci: 284157dacad5SJay Sternberg put_device(dev->dev); 284257dacad5SJay Sternberg free: 284357dacad5SJay Sternberg kfree(dev->queues); 284457dacad5SJay Sternberg kfree(dev); 284557dacad5SJay Sternberg return result; 284657dacad5SJay Sternberg } 284757dacad5SJay Sternberg 2848775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 284957dacad5SJay Sternberg { 285057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2851c1ac9a4bSKeith Busch 2852c1ac9a4bSKeith Busch /* 2853c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 2854c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 2855c1ac9a4bSKeith Busch * with ->remove(). 2856c1ac9a4bSKeith Busch */ 2857c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 2858c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 2859775755edSChristoph Hellwig } 286057dacad5SJay Sternberg 2861775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2862775755edSChristoph Hellwig { 2863f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 2864c1ac9a4bSKeith Busch 2865c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 2866c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 286757dacad5SJay Sternberg } 286857dacad5SJay Sternberg 286957dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 287057dacad5SJay Sternberg { 287157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 28724e523547SBaolin Wang 2873c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 287457dacad5SJay Sternberg } 287557dacad5SJay Sternberg 2876f58944e2SKeith Busch /* 2877f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2878f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2879f58944e2SKeith Busch * order to proceed. 2880f58944e2SKeith Busch */ 288157dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 288257dacad5SJay Sternberg { 288357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 288457dacad5SJay Sternberg 2885bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 288657dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28870ff9d4e1SKeith Busch 28886db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28890ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28901d39e692SKeith Busch nvme_dev_disable(dev, true); 2891cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28926db28edaSKeith Busch } 28930ff9d4e1SKeith Busch 2894d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2895d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2896d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2897a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28989fe5c59fSKeith Busch nvme_release_cmb(dev); 289987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 290057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 290157dacad5SJay Sternberg nvme_free_queues(dev, 0); 290257dacad5SJay Sternberg nvme_release_prp_pools(dev); 2903b00a726aSKeith Busch nvme_dev_unmap(dev); 2904726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 290557dacad5SJay Sternberg } 290657dacad5SJay Sternberg 290757dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 2908d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 2909d916b1beSKeith Busch { 2910d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 2911d916b1beSKeith Busch } 2912d916b1beSKeith Busch 2913d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 2914d916b1beSKeith Busch { 2915d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 2916d916b1beSKeith Busch } 2917d916b1beSKeith Busch 2918d916b1beSKeith Busch static int nvme_resume(struct device *dev) 2919d916b1beSKeith Busch { 2920d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 2921d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2922d916b1beSKeith Busch 29234eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 2924d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 2925c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 2926d916b1beSKeith Busch return 0; 2927d916b1beSKeith Busch } 2928d916b1beSKeith Busch 292957dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 293057dacad5SJay Sternberg { 293157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 293257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 2933d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 2934d916b1beSKeith Busch int ret = -EBUSY; 2935d916b1beSKeith Busch 29364eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 29374eaefe8cSRafael J. Wysocki 2938d916b1beSKeith Busch /* 2939d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 2940d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 2941d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 2942d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 2943d916b1beSKeith Busch * device does not support any non-default power states, shut down the 2944d916b1beSKeith Busch * device fully. 29454eaefe8cSRafael J. Wysocki * 29464eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 29474eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 29484eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 29494eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 2950b97120b1SChristoph Hellwig * 2951b97120b1SChristoph Hellwig * If a host memory buffer is enabled, shut down the device as the NVMe 2952b97120b1SChristoph Hellwig * specification allows the device to access the host memory buffer in 2953b97120b1SChristoph Hellwig * host DRAM from all power states, but hosts will fail access to DRAM 2954b97120b1SChristoph Hellwig * during S3. 2955d916b1beSKeith Busch */ 29564eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 2957cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 2958b97120b1SChristoph Hellwig ndev->nr_host_mem_descs || 2959c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 2960c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 2961d916b1beSKeith Busch 2962d916b1beSKeith Busch nvme_start_freeze(ctrl); 2963d916b1beSKeith Busch nvme_wait_freeze(ctrl); 2964d916b1beSKeith Busch nvme_sync_queues(ctrl); 2965d916b1beSKeith Busch 29665d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 2967d916b1beSKeith Busch goto unfreeze; 2968d916b1beSKeith Busch 2969d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 2970d916b1beSKeith Busch if (ret < 0) 2971d916b1beSKeith Busch goto unfreeze; 2972d916b1beSKeith Busch 29737cbb5c6fSMario Limonciello /* 29747cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 29757cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 29767cbb5c6fSMario Limonciello * want pci interfering. 29777cbb5c6fSMario Limonciello */ 29787cbb5c6fSMario Limonciello pci_save_state(pdev); 29797cbb5c6fSMario Limonciello 2980d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 2981d916b1beSKeith Busch if (ret < 0) 2982d916b1beSKeith Busch goto unfreeze; 2983d916b1beSKeith Busch 2984d916b1beSKeith Busch if (ret) { 29857cbb5c6fSMario Limonciello /* discard the saved state */ 29867cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 29877cbb5c6fSMario Limonciello 2988d916b1beSKeith Busch /* 2989d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 299005d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 2991d916b1beSKeith Busch */ 2992c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 2993d916b1beSKeith Busch ctrl->npss = 0; 2994d916b1beSKeith Busch } 2995d916b1beSKeith Busch unfreeze: 2996d916b1beSKeith Busch nvme_unfreeze(ctrl); 2997d916b1beSKeith Busch return ret; 2998d916b1beSKeith Busch } 2999d916b1beSKeith Busch 3000d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3001d916b1beSKeith Busch { 3002d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 30034e523547SBaolin Wang 3004c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 300557dacad5SJay Sternberg } 300657dacad5SJay Sternberg 3007d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 300857dacad5SJay Sternberg { 300957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 301057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 301157dacad5SJay Sternberg 3012c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 301357dacad5SJay Sternberg } 301457dacad5SJay Sternberg 301521774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3016d916b1beSKeith Busch .suspend = nvme_suspend, 3017d916b1beSKeith Busch .resume = nvme_resume, 3018d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3019d916b1beSKeith Busch .thaw = nvme_simple_resume, 3020d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3021d916b1beSKeith Busch .restore = nvme_simple_resume, 3022d916b1beSKeith Busch }; 3023d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 302457dacad5SJay Sternberg 3025a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3026a0a3408eSKeith Busch pci_channel_state_t state) 3027a0a3408eSKeith Busch { 3028a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3029a0a3408eSKeith Busch 3030a0a3408eSKeith Busch /* 3031a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3032a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3033a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3034a0a3408eSKeith Busch */ 3035a0a3408eSKeith Busch switch (state) { 3036a0a3408eSKeith Busch case pci_channel_io_normal: 3037a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3038a0a3408eSKeith Busch case pci_channel_io_frozen: 3039d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3040d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3041a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3042a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3043a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3044d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3045d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3046a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3047a0a3408eSKeith Busch } 3048a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3049a0a3408eSKeith Busch } 3050a0a3408eSKeith Busch 3051a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3052a0a3408eSKeith Busch { 3053a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3054a0a3408eSKeith Busch 30551b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3056a0a3408eSKeith Busch pci_restore_state(pdev); 3057d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3058a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3059a0a3408eSKeith Busch } 3060a0a3408eSKeith Busch 3061a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3062a0a3408eSKeith Busch { 306372cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 306472cd4cc2SKeith Busch 306572cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3066a0a3408eSKeith Busch } 3067a0a3408eSKeith Busch 306857dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 306957dacad5SJay Sternberg .error_detected = nvme_error_detected, 307057dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 307157dacad5SJay Sternberg .resume = nvme_error_resume, 3072775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3073775755edSChristoph Hellwig .reset_done = nvme_reset_done, 307457dacad5SJay Sternberg }; 307557dacad5SJay Sternberg 307657dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3077972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 307808095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3079e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3080972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 308199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3082e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3083972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 308499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3085e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3086972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3087f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3088f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 308950af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 30909abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 30916c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 30926c6aa2f2SAkinobu Mita NVME_QUIRK_NO_TEMP_THRESH_CHANGE }, 30936299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 30946299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3095540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 30967b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 30977b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 30980302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 30990302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 310054adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 310154adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 31028c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 31038c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3104015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3105015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3106d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3107d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3108d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 3109d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3110608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 3111608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3112608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 3113608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 3114ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 3115ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 311608b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 311708b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3118f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3119f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3120f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 312157dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 312298f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 312398f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3124124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 312566341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 312666341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3127d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3128d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_SHARED_TAGS }, 312957dacad5SJay Sternberg { 0, } 313057dacad5SJay Sternberg }; 313157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 313257dacad5SJay Sternberg 313357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 313457dacad5SJay Sternberg .name = "nvme", 313557dacad5SJay Sternberg .id_table = nvme_id_table, 313657dacad5SJay Sternberg .probe = nvme_probe, 313757dacad5SJay Sternberg .remove = nvme_remove, 313857dacad5SJay Sternberg .shutdown = nvme_shutdown, 3139d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 314057dacad5SJay Sternberg .driver = { 314157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 314257dacad5SJay Sternberg }, 3143d916b1beSKeith Busch #endif 314474d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 314557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 314657dacad5SJay Sternberg }; 314757dacad5SJay Sternberg 314857dacad5SJay Sternberg static int __init nvme_init(void) 314957dacad5SJay Sternberg { 315081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 315181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 315281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3153612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 315417c33167SKeith Busch 31559a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 315657dacad5SJay Sternberg } 315757dacad5SJay Sternberg 315857dacad5SJay Sternberg static void __exit nvme_exit(void) 315957dacad5SJay Sternberg { 316057dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 316103e0f3a6SMing Lei flush_workqueue(nvme_wq); 316257dacad5SJay Sternberg } 316357dacad5SJay Sternberg 316457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 316557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 316657dacad5SJay Sternberg MODULE_VERSION("1.0"); 316757dacad5SJay Sternberg module_init(nvme_init); 316857dacad5SJay Sternberg module_exit(nvme_exit); 3169