157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 3357dacad5SJay Sternberg 3457dacad5SJay Sternberg #include "nvme.h" 3557dacad5SJay Sternberg 3657dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3757dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3857dacad5SJay Sternberg 39a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40adf68f21SChristoph Hellwig 4157dacad5SJay Sternberg static int use_threaded_interrupts; 4257dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4357dacad5SJay Sternberg 4457dacad5SJay Sternberg static bool use_cmb_sqes = true; 4557dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 4657dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4757dacad5SJay Sternberg 4887ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 4987ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5087ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5187ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5257dacad5SJay Sternberg 53a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 54a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 55a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 56a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 57a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 58a7a7cbe3SChaitanya Kulkarni 59b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 60b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 61b27c1e68Sweiping zhang .set = io_queue_depth_set, 62b27c1e68Sweiping zhang .get = param_get_int, 63b27c1e68Sweiping zhang }; 64b27c1e68Sweiping zhang 65b27c1e68Sweiping zhang static int io_queue_depth = 1024; 66b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 67b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 68b27c1e68Sweiping zhang 691c63dc66SChristoph Hellwig struct nvme_dev; 701c63dc66SChristoph Hellwig struct nvme_queue; 7157dacad5SJay Sternberg 72a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7357dacad5SJay Sternberg 7457dacad5SJay Sternberg /* 751c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 761c63dc66SChristoph Hellwig */ 771c63dc66SChristoph Hellwig struct nvme_dev { 78147b27e4SSagi Grimberg struct nvme_queue *queues; 791c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 811c63dc66SChristoph Hellwig u32 __iomem *dbs; 821c63dc66SChristoph Hellwig struct device *dev; 831c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 841c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 851c63dc66SChristoph Hellwig unsigned online_queues; 861c63dc66SChristoph Hellwig unsigned max_qid; 8722b55601SKeith Busch unsigned int num_vecs; 881c63dc66SChristoph Hellwig int q_depth; 891c63dc66SChristoph Hellwig u32 db_stride; 901c63dc66SChristoph Hellwig void __iomem *bar; 9197f6ef64SXu Yu unsigned long bar_mapped_size; 925c8809e6SChristoph Hellwig struct work_struct remove_work; 9377bf25eaSKeith Busch struct mutex shutdown_lock; 941c63dc66SChristoph Hellwig bool subsystem; 951c63dc66SChristoph Hellwig void __iomem *cmb; 968969f1f8SChristoph Hellwig pci_bus_addr_t cmb_bus_addr; 971c63dc66SChristoph Hellwig u64 cmb_size; 981c63dc66SChristoph Hellwig u32 cmbsz; 99202021c1SStephen Bates u32 cmbloc; 1001c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 101db3cbfffSKeith Busch struct completion ioq_wait; 10287ad72a5SChristoph Hellwig 10387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 104f9f38e33SHelen Koike u32 *dbbuf_dbs; 105f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 106f9f38e33SHelen Koike u32 *dbbuf_eis; 107f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10887ad72a5SChristoph Hellwig 10987ad72a5SChristoph Hellwig /* host memory buffer support: */ 11087ad72a5SChristoph Hellwig u64 host_mem_size; 11187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1124033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 11387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11487ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11557dacad5SJay Sternberg }; 11657dacad5SJay Sternberg 117b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 118b27c1e68Sweiping zhang { 119b27c1e68Sweiping zhang int n = 0, ret; 120b27c1e68Sweiping zhang 121b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 122b27c1e68Sweiping zhang if (ret != 0 || n < 2) 123b27c1e68Sweiping zhang return -EINVAL; 124b27c1e68Sweiping zhang 125b27c1e68Sweiping zhang return param_set_int(val, kp); 126b27c1e68Sweiping zhang } 127b27c1e68Sweiping zhang 128f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 129f9f38e33SHelen Koike { 130f9f38e33SHelen Koike return qid * 2 * stride; 131f9f38e33SHelen Koike } 132f9f38e33SHelen Koike 133f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 134f9f38e33SHelen Koike { 135f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 136f9f38e33SHelen Koike } 137f9f38e33SHelen Koike 1381c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1391c63dc66SChristoph Hellwig { 1401c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1411c63dc66SChristoph Hellwig } 1421c63dc66SChristoph Hellwig 14357dacad5SJay Sternberg /* 14457dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14557dacad5SJay Sternberg * commands and one for I/O commands). 14657dacad5SJay Sternberg */ 14757dacad5SJay Sternberg struct nvme_queue { 14857dacad5SJay Sternberg struct device *q_dmadev; 14957dacad5SJay Sternberg struct nvme_dev *dev; 1501ab0cd69SJens Axboe spinlock_t sq_lock; 15157dacad5SJay Sternberg struct nvme_command *sq_cmds; 15257dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 1531ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 15457dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15557dacad5SJay Sternberg struct blk_mq_tags **tags; 15657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15857dacad5SJay Sternberg u32 __iomem *q_db; 15957dacad5SJay Sternberg u16 q_depth; 16057dacad5SJay Sternberg s16 cq_vector; 16157dacad5SJay Sternberg u16 sq_tail; 16257dacad5SJay Sternberg u16 cq_head; 16368fa9dbeSJens Axboe u16 last_cq_head; 16457dacad5SJay Sternberg u16 qid; 16557dacad5SJay Sternberg u8 cq_phase; 166f9f38e33SHelen Koike u32 *dbbuf_sq_db; 167f9f38e33SHelen Koike u32 *dbbuf_cq_db; 168f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 169f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 17057dacad5SJay Sternberg }; 17157dacad5SJay Sternberg 17257dacad5SJay Sternberg /* 17371bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17471bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 175f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17671bd150cSChristoph Hellwig * allocated to store the PRP list. 17771bd150cSChristoph Hellwig */ 17871bd150cSChristoph Hellwig struct nvme_iod { 179d49187e9SChristoph Hellwig struct nvme_request req; 180f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 181a7a7cbe3SChaitanya Kulkarni bool use_sgl; 182f4800d6dSChristoph Hellwig int aborted; 18371bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18471bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18571bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18671bd150cSChristoph Hellwig dma_addr_t first_dma; 187bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 188f4800d6dSChristoph Hellwig struct scatterlist *sg; 189f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 19057dacad5SJay Sternberg }; 19157dacad5SJay Sternberg 19257dacad5SJay Sternberg /* 19357dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19457dacad5SJay Sternberg */ 19557dacad5SJay Sternberg static inline void _nvme_check_size(void) 19657dacad5SJay Sternberg { 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2050add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2060add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 209f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 210f9f38e33SHelen Koike } 211f9f38e33SHelen Koike 212f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 213f9f38e33SHelen Koike { 214f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 215f9f38e33SHelen Koike } 216f9f38e33SHelen Koike 217f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 218f9f38e33SHelen Koike { 219f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike if (dev->dbbuf_dbs) 222f9f38e33SHelen Koike return 0; 223f9f38e33SHelen Koike 224f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 225f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 226f9f38e33SHelen Koike GFP_KERNEL); 227f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 228f9f38e33SHelen Koike return -ENOMEM; 229f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 230f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 231f9f38e33SHelen Koike GFP_KERNEL); 232f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 233f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 234f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 235f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 236f9f38e33SHelen Koike return -ENOMEM; 237f9f38e33SHelen Koike } 238f9f38e33SHelen Koike 239f9f38e33SHelen Koike return 0; 240f9f38e33SHelen Koike } 241f9f38e33SHelen Koike 242f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 243f9f38e33SHelen Koike { 244f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 245f9f38e33SHelen Koike 246f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 247f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 248f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 249f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 250f9f38e33SHelen Koike } 251f9f38e33SHelen Koike if (dev->dbbuf_eis) { 252f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 253f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 254f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 255f9f38e33SHelen Koike } 256f9f38e33SHelen Koike } 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 259f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 260f9f38e33SHelen Koike { 261f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 262f9f38e33SHelen Koike return; 263f9f38e33SHelen Koike 264f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 266f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 267f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 268f9f38e33SHelen Koike } 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike struct nvme_command c; 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 275f9f38e33SHelen Koike return; 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 278f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 279f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 280f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 281f9f38e33SHelen Koike 282f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2839bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 284f9f38e33SHelen Koike /* Free memory and continue on */ 285f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike } 288f9f38e33SHelen Koike 289f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 290f9f38e33SHelen Koike { 291f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 295f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 296f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 297f9f38e33SHelen Koike { 298f9f38e33SHelen Koike if (dbbuf_db) { 299f9f38e33SHelen Koike u16 old_value; 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike /* 302f9f38e33SHelen Koike * Ensure that the queue is written before updating 303f9f38e33SHelen Koike * the doorbell in memory 304f9f38e33SHelen Koike */ 305f9f38e33SHelen Koike wmb(); 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike old_value = *dbbuf_db; 308f9f38e33SHelen Koike *dbbuf_db = value; 309f9f38e33SHelen Koike 310f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 311f9f38e33SHelen Koike return false; 312f9f38e33SHelen Koike } 313f9f38e33SHelen Koike 314f9f38e33SHelen Koike return true; 31557dacad5SJay Sternberg } 31657dacad5SJay Sternberg 31757dacad5SJay Sternberg /* 31857dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31957dacad5SJay Sternberg */ 32057dacad5SJay Sternberg #define NVME_INT_PAGES 2 3215fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 32257dacad5SJay Sternberg 32357dacad5SJay Sternberg /* 32457dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32557dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32657dacad5SJay Sternberg * the I/O. 32757dacad5SJay Sternberg */ 32857dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32957dacad5SJay Sternberg { 3305fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3315fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 33257dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33357dacad5SJay Sternberg } 33457dacad5SJay Sternberg 335a7a7cbe3SChaitanya Kulkarni /* 336a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 337a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 338a7a7cbe3SChaitanya Kulkarni */ 339a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 340f4800d6dSChristoph Hellwig { 341a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 342f4800d6dSChristoph Hellwig } 343f4800d6dSChristoph Hellwig 344a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 345a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 34657dacad5SJay Sternberg { 347a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 348a7a7cbe3SChaitanya Kulkarni 349a7a7cbe3SChaitanya Kulkarni if (use_sgl) 350a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 351a7a7cbe3SChaitanya Kulkarni else 352a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 353a7a7cbe3SChaitanya Kulkarni 354a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 355a7a7cbe3SChaitanya Kulkarni } 356a7a7cbe3SChaitanya Kulkarni 357a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 358a7a7cbe3SChaitanya Kulkarni { 359a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 360a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 361a7a7cbe3SChaitanya Kulkarni use_sgl); 362a7a7cbe3SChaitanya Kulkarni 363a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 36457dacad5SJay Sternberg } 36557dacad5SJay Sternberg 36657dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36757dacad5SJay Sternberg unsigned int hctx_idx) 36857dacad5SJay Sternberg { 36957dacad5SJay Sternberg struct nvme_dev *dev = data; 370147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37157dacad5SJay Sternberg 37257dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37357dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37457dacad5SJay Sternberg WARN_ON(nvmeq->tags); 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg hctx->driver_data = nvmeq; 37757dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 37857dacad5SJay Sternberg return 0; 37957dacad5SJay Sternberg } 38057dacad5SJay Sternberg 38157dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38257dacad5SJay Sternberg { 38357dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 38457dacad5SJay Sternberg 38557dacad5SJay Sternberg nvmeq->tags = NULL; 38657dacad5SJay Sternberg } 38757dacad5SJay Sternberg 38857dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38957dacad5SJay Sternberg unsigned int hctx_idx) 39057dacad5SJay Sternberg { 39157dacad5SJay Sternberg struct nvme_dev *dev = data; 392147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39357dacad5SJay Sternberg 39457dacad5SJay Sternberg if (!nvmeq->tags) 39557dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 39657dacad5SJay Sternberg 39757dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39857dacad5SJay Sternberg hctx->driver_data = nvmeq; 39957dacad5SJay Sternberg return 0; 40057dacad5SJay Sternberg } 40157dacad5SJay Sternberg 402d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 403d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40457dacad5SJay Sternberg { 405d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 406f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4070350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 408147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40957dacad5SJay Sternberg 41057dacad5SJay Sternberg BUG_ON(!nvmeq); 411f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41257dacad5SJay Sternberg return 0; 41357dacad5SJay Sternberg } 41457dacad5SJay Sternberg 415dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 416dca51e78SChristoph Hellwig { 417dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 418dca51e78SChristoph Hellwig 41922b55601SKeith Busch return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 42022b55601SKeith Busch dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 421dca51e78SChristoph Hellwig } 422dca51e78SChristoph Hellwig 42357dacad5SJay Sternberg /** 424adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 42557dacad5SJay Sternberg * @nvmeq: The queue to use 42657dacad5SJay Sternberg * @cmd: The command to send 42757dacad5SJay Sternberg * 42857dacad5SJay Sternberg * Safe to use from interrupt context 42957dacad5SJay Sternberg */ 43057dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 43157dacad5SJay Sternberg struct nvme_command *cmd) 43257dacad5SJay Sternberg { 43357dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 43457dacad5SJay Sternberg 43557dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 43657dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 43757dacad5SJay Sternberg else 43857dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 43957dacad5SJay Sternberg 44057dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 44157dacad5SJay Sternberg tail = 0; 442f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 443f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 44457dacad5SJay Sternberg writel(tail, nvmeq->q_db); 44557dacad5SJay Sternberg nvmeq->sq_tail = tail; 44657dacad5SJay Sternberg } 44757dacad5SJay Sternberg 448a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 44957dacad5SJay Sternberg { 450f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 451a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 45257dacad5SJay Sternberg } 45357dacad5SJay Sternberg 454955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 455955b1b5aSMinwoo Im { 456955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 45720469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 458955b1b5aSMinwoo Im unsigned int avg_seg_size; 459955b1b5aSMinwoo Im 46020469a37SKeith Busch if (nseg == 0) 46120469a37SKeith Busch return false; 46220469a37SKeith Busch 46320469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 464955b1b5aSMinwoo Im 465955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 466955b1b5aSMinwoo Im return false; 467955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 468955b1b5aSMinwoo Im return false; 469955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 470955b1b5aSMinwoo Im return false; 471955b1b5aSMinwoo Im return true; 472955b1b5aSMinwoo Im } 473955b1b5aSMinwoo Im 474fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 47557dacad5SJay Sternberg { 476f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 477f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 478b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 479f4800d6dSChristoph Hellwig 480955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 481955b1b5aSMinwoo Im 482f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 483a7a7cbe3SChaitanya Kulkarni size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, 484a7a7cbe3SChaitanya Kulkarni iod->use_sgl); 485a7a7cbe3SChaitanya Kulkarni 486a7a7cbe3SChaitanya Kulkarni iod->sg = kmalloc(alloc_size, GFP_ATOMIC); 487f4800d6dSChristoph Hellwig if (!iod->sg) 488fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 489f4800d6dSChristoph Hellwig } else { 490f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 49157dacad5SJay Sternberg } 49257dacad5SJay Sternberg 493f4800d6dSChristoph Hellwig iod->aborted = 0; 49457dacad5SJay Sternberg iod->npages = -1; 49557dacad5SJay Sternberg iod->nents = 0; 496f4800d6dSChristoph Hellwig iod->length = size; 497f80ec966SKeith Busch 498fc17b653SChristoph Hellwig return BLK_STS_OK; 49957dacad5SJay Sternberg } 50057dacad5SJay Sternberg 501f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 50257dacad5SJay Sternberg { 503f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 504a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 505a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 506a7a7cbe3SChaitanya Kulkarni 50757dacad5SJay Sternberg int i; 50857dacad5SJay Sternberg 50957dacad5SJay Sternberg if (iod->npages == 0) 510a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 511a7a7cbe3SChaitanya Kulkarni dma_addr); 512a7a7cbe3SChaitanya Kulkarni 51357dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 514a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 515a7a7cbe3SChaitanya Kulkarni 516a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 517a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 518a7a7cbe3SChaitanya Kulkarni 519a7a7cbe3SChaitanya Kulkarni next_dma_addr = 520a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 521a7a7cbe3SChaitanya Kulkarni } else { 522a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 523a7a7cbe3SChaitanya Kulkarni 524a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 525a7a7cbe3SChaitanya Kulkarni } 526a7a7cbe3SChaitanya Kulkarni 527a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 528a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 52957dacad5SJay Sternberg } 53057dacad5SJay Sternberg 531f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 532f4800d6dSChristoph Hellwig kfree(iod->sg); 53357dacad5SJay Sternberg } 53457dacad5SJay Sternberg 53557dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 53657dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53757dacad5SJay Sternberg { 53857dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 53957dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 54057dacad5SJay Sternberg } 54157dacad5SJay Sternberg 54257dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54357dacad5SJay Sternberg { 54457dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 54557dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 54657dacad5SJay Sternberg } 54757dacad5SJay Sternberg 54857dacad5SJay Sternberg /** 54957dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 55057dacad5SJay Sternberg * 55157dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 55257dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 55357dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 55457dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 55557dacad5SJay Sternberg * 55657dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 55757dacad5SJay Sternberg */ 55857dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 55957dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 56057dacad5SJay Sternberg { 56157dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 56257dacad5SJay Sternberg struct bio_integrity_payload *bip; 56357dacad5SJay Sternberg struct t10_pi_tuple *pi; 56457dacad5SJay Sternberg void *p, *pmap; 56557dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 56657dacad5SJay Sternberg 56757dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 56857dacad5SJay Sternberg return; 56957dacad5SJay Sternberg 57057dacad5SJay Sternberg bip = bio_integrity(req->bio); 57157dacad5SJay Sternberg if (!bip) 57257dacad5SJay Sternberg return; 57357dacad5SJay Sternberg 57457dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 57557dacad5SJay Sternberg 57657dacad5SJay Sternberg p = pmap; 57757dacad5SJay Sternberg virt = bip_get_seed(bip); 57857dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 57957dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 580ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 58157dacad5SJay Sternberg 58257dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 58357dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 58457dacad5SJay Sternberg dif_swap(phys, virt, pi); 58557dacad5SJay Sternberg p += ts; 58657dacad5SJay Sternberg } 58757dacad5SJay Sternberg kunmap_atomic(pmap); 58857dacad5SJay Sternberg } 58957dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 59057dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 59157dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 59257dacad5SJay Sternberg { 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 59557dacad5SJay Sternberg { 59657dacad5SJay Sternberg } 59757dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 59857dacad5SJay Sternberg { 59957dacad5SJay Sternberg } 60057dacad5SJay Sternberg #endif 60157dacad5SJay Sternberg 602d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 603d0877473SKeith Busch { 604d0877473SKeith Busch int i; 605d0877473SKeith Busch struct scatterlist *sg; 606d0877473SKeith Busch 607d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 608d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 609d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 610d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 611d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 612d0877473SKeith Busch sg_dma_len(sg)); 613d0877473SKeith Busch } 614d0877473SKeith Busch } 615d0877473SKeith Busch 616a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 617a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 61857dacad5SJay Sternberg { 619f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 62057dacad5SJay Sternberg struct dma_pool *pool; 621b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 62257dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 62357dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 62457dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6255fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 62657dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 62757dacad5SJay Sternberg __le64 *prp_list; 628a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 62957dacad5SJay Sternberg dma_addr_t prp_dma; 63057dacad5SJay Sternberg int nprps, i; 63157dacad5SJay Sternberg 63257dacad5SJay Sternberg length -= (page_size - offset); 6335228b328SJan H. Schönherr if (length <= 0) { 6345228b328SJan H. Schönherr iod->first_dma = 0; 635a7a7cbe3SChaitanya Kulkarni goto done; 6365228b328SJan H. Schönherr } 63757dacad5SJay Sternberg 63857dacad5SJay Sternberg dma_len -= (page_size - offset); 63957dacad5SJay Sternberg if (dma_len) { 64057dacad5SJay Sternberg dma_addr += (page_size - offset); 64157dacad5SJay Sternberg } else { 64257dacad5SJay Sternberg sg = sg_next(sg); 64357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 64557dacad5SJay Sternberg } 64657dacad5SJay Sternberg 64757dacad5SJay Sternberg if (length <= page_size) { 64857dacad5SJay Sternberg iod->first_dma = dma_addr; 649a7a7cbe3SChaitanya Kulkarni goto done; 65057dacad5SJay Sternberg } 65157dacad5SJay Sternberg 65257dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 65357dacad5SJay Sternberg if (nprps <= (256 / 8)) { 65457dacad5SJay Sternberg pool = dev->prp_small_pool; 65557dacad5SJay Sternberg iod->npages = 0; 65657dacad5SJay Sternberg } else { 65757dacad5SJay Sternberg pool = dev->prp_page_pool; 65857dacad5SJay Sternberg iod->npages = 1; 65957dacad5SJay Sternberg } 66057dacad5SJay Sternberg 66169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66257dacad5SJay Sternberg if (!prp_list) { 66357dacad5SJay Sternberg iod->first_dma = dma_addr; 66457dacad5SJay Sternberg iod->npages = -1; 66586eea289SKeith Busch return BLK_STS_RESOURCE; 66657dacad5SJay Sternberg } 66757dacad5SJay Sternberg list[0] = prp_list; 66857dacad5SJay Sternberg iod->first_dma = prp_dma; 66957dacad5SJay Sternberg i = 0; 67057dacad5SJay Sternberg for (;;) { 67157dacad5SJay Sternberg if (i == page_size >> 3) { 67257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67457dacad5SJay Sternberg if (!prp_list) 67586eea289SKeith Busch return BLK_STS_RESOURCE; 67657dacad5SJay Sternberg list[iod->npages++] = prp_list; 67757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 67857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 67957dacad5SJay Sternberg i = 1; 68057dacad5SJay Sternberg } 68157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 68257dacad5SJay Sternberg dma_len -= page_size; 68357dacad5SJay Sternberg dma_addr += page_size; 68457dacad5SJay Sternberg length -= page_size; 68557dacad5SJay Sternberg if (length <= 0) 68657dacad5SJay Sternberg break; 68757dacad5SJay Sternberg if (dma_len > 0) 68857dacad5SJay Sternberg continue; 68986eea289SKeith Busch if (unlikely(dma_len < 0)) 69086eea289SKeith Busch goto bad_sgl; 69157dacad5SJay Sternberg sg = sg_next(sg); 69257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69457dacad5SJay Sternberg } 69557dacad5SJay Sternberg 696a7a7cbe3SChaitanya Kulkarni done: 697a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 698a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 699a7a7cbe3SChaitanya Kulkarni 70086eea289SKeith Busch return BLK_STS_OK; 70186eea289SKeith Busch 70286eea289SKeith Busch bad_sgl: 703d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 704d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 705d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 70686eea289SKeith Busch return BLK_STS_IOERR; 70757dacad5SJay Sternberg } 70857dacad5SJay Sternberg 709a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 710a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 711a7a7cbe3SChaitanya Kulkarni { 712a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 713a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 714a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 715a7a7cbe3SChaitanya Kulkarni } 716a7a7cbe3SChaitanya Kulkarni 717a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 718a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 719a7a7cbe3SChaitanya Kulkarni { 720a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 721a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 722a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 723a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 724a7a7cbe3SChaitanya Kulkarni } else { 725a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 726a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 727a7a7cbe3SChaitanya Kulkarni } 728a7a7cbe3SChaitanya Kulkarni } 729a7a7cbe3SChaitanya Kulkarni 730a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 731b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 732a7a7cbe3SChaitanya Kulkarni { 733a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 734a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 735a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 736a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 737a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 738b0f2853bSChristoph Hellwig int i = 0; 739a7a7cbe3SChaitanya Kulkarni 740a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 741a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 742a7a7cbe3SChaitanya Kulkarni 743b0f2853bSChristoph Hellwig if (entries == 1) { 744a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 745a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 746a7a7cbe3SChaitanya Kulkarni } 747a7a7cbe3SChaitanya Kulkarni 748a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 749a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 750a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 751a7a7cbe3SChaitanya Kulkarni } else { 752a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 753a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 754a7a7cbe3SChaitanya Kulkarni } 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 757a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 758a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 759a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 760a7a7cbe3SChaitanya Kulkarni } 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 763a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 764a7a7cbe3SChaitanya Kulkarni 765a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 766a7a7cbe3SChaitanya Kulkarni 767a7a7cbe3SChaitanya Kulkarni do { 768a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 769a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 770a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 771a7a7cbe3SChaitanya Kulkarni 772a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 773a7a7cbe3SChaitanya Kulkarni if (!sg_list) 774a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 775a7a7cbe3SChaitanya Kulkarni 776a7a7cbe3SChaitanya Kulkarni i = 0; 777a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 778a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 779a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 780a7a7cbe3SChaitanya Kulkarni } 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 783a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 784b0f2853bSChristoph Hellwig } while (--entries > 0); 785a7a7cbe3SChaitanya Kulkarni 786a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 787a7a7cbe3SChaitanya Kulkarni } 788a7a7cbe3SChaitanya Kulkarni 789fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 790b131c61dSChristoph Hellwig struct nvme_command *cmnd) 79157dacad5SJay Sternberg { 792f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 793ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 794ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 795ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 796fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 797b0f2853bSChristoph Hellwig int nr_mapped; 79857dacad5SJay Sternberg 799f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 800ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 801ba1ca37eSChristoph Hellwig if (!iod->nents) 802ba1ca37eSChristoph Hellwig goto out; 803ba1ca37eSChristoph Hellwig 804fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 805b0f2853bSChristoph Hellwig nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 806b0f2853bSChristoph Hellwig DMA_ATTR_NO_WARN); 807b0f2853bSChristoph Hellwig if (!nr_mapped) 808ba1ca37eSChristoph Hellwig goto out; 809ba1ca37eSChristoph Hellwig 810955b1b5aSMinwoo Im if (iod->use_sgl) 811b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 812a7a7cbe3SChaitanya Kulkarni else 813a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 814a7a7cbe3SChaitanya Kulkarni 81586eea289SKeith Busch if (ret != BLK_STS_OK) 816ba1ca37eSChristoph Hellwig goto out_unmap; 817ba1ca37eSChristoph Hellwig 818fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 819ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 820ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 821ba1ca37eSChristoph Hellwig goto out_unmap; 822ba1ca37eSChristoph Hellwig 823bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 824bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 825ba1ca37eSChristoph Hellwig goto out_unmap; 826ba1ca37eSChristoph Hellwig 827b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 828ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 829ba1ca37eSChristoph Hellwig 830bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 831ba1ca37eSChristoph Hellwig goto out_unmap; 83257dacad5SJay Sternberg } 83357dacad5SJay Sternberg 834ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 835bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 836fc17b653SChristoph Hellwig return BLK_STS_OK; 837ba1ca37eSChristoph Hellwig 838ba1ca37eSChristoph Hellwig out_unmap: 839ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 840ba1ca37eSChristoph Hellwig out: 841ba1ca37eSChristoph Hellwig return ret; 84257dacad5SJay Sternberg } 84357dacad5SJay Sternberg 844f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 845d4f6c3abSChristoph Hellwig { 846f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 847d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 848d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 849d4f6c3abSChristoph Hellwig 850d4f6c3abSChristoph Hellwig if (iod->nents) { 851d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 852d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 853b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 854d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 855bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 856d4f6c3abSChristoph Hellwig } 857d4f6c3abSChristoph Hellwig } 858d4f6c3abSChristoph Hellwig 859f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 860f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 86157dacad5SJay Sternberg } 86257dacad5SJay Sternberg 86357dacad5SJay Sternberg /* 86457dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86557dacad5SJay Sternberg */ 866fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86757dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86857dacad5SJay Sternberg { 86957dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 87057dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87257dacad5SJay Sternberg struct request *req = bd->rq; 873ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 874ebe6d874SChristoph Hellwig blk_status_t ret; 87557dacad5SJay Sternberg 876d1f06f4aSJens Axboe /* 877d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 878d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 879d1f06f4aSJens Axboe */ 880d1f06f4aSJens Axboe if (unlikely(nvmeq->cq_vector < 0)) 881d1f06f4aSJens Axboe return BLK_STS_IOERR; 882d1f06f4aSJens Axboe 883f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 884fc17b653SChristoph Hellwig if (ret) 885f4800d6dSChristoph Hellwig return ret; 88657dacad5SJay Sternberg 887b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 888fc17b653SChristoph Hellwig if (ret) 889f9d03f96SChristoph Hellwig goto out_free_cmd; 89057dacad5SJay Sternberg 891fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 892b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 893fc17b653SChristoph Hellwig if (ret) 894f9d03f96SChristoph Hellwig goto out_cleanup_iod; 895fc17b653SChristoph Hellwig } 896ba1ca37eSChristoph Hellwig 897aae239e1SChristoph Hellwig blk_mq_start_request(req); 898ba1ca37eSChristoph Hellwig 8991eae349dSJens Axboe spin_lock(&nvmeq->sq_lock); 900ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 9011eae349dSJens Axboe spin_unlock(&nvmeq->sq_lock); 902fc17b653SChristoph Hellwig return BLK_STS_OK; 903f9d03f96SChristoph Hellwig out_cleanup_iod: 904f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 905f9d03f96SChristoph Hellwig out_free_cmd: 906f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 907ba1ca37eSChristoph Hellwig return ret; 90857dacad5SJay Sternberg } 90957dacad5SJay Sternberg 91077f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 911eee417b0SChristoph Hellwig { 912f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 913eee417b0SChristoph Hellwig 91477f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 91577f02a7aSChristoph Hellwig nvme_complete_rq(req); 91657dacad5SJay Sternberg } 91757dacad5SJay Sternberg 918d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 919750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 920d783e0bdSMarta Rybczynska { 921750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 922750dde44SChristoph Hellwig nvmeq->cq_phase; 923d783e0bdSMarta Rybczynska } 924d783e0bdSMarta Rybczynska 925eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92657dacad5SJay Sternberg { 927eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92857dacad5SJay Sternberg 929eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 930eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 931eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 932eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 933eb281c82SSagi Grimberg } 93457dacad5SJay Sternberg } 935adf68f21SChristoph Hellwig 9365cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 93757dacad5SJay Sternberg { 9385cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 93957dacad5SJay Sternberg struct request *req; 940adf68f21SChristoph Hellwig 94183a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9421b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 943aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94483a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94583a12fb7SSagi Grimberg return; 946aae239e1SChristoph Hellwig } 947aae239e1SChristoph Hellwig 948adf68f21SChristoph Hellwig /* 949adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 950adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 951adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 952adf68f21SChristoph Hellwig * for them but rather special case them here. 953adf68f21SChristoph Hellwig */ 954adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 95538dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9567bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95783a12fb7SSagi Grimberg cqe->status, &cqe->result); 958a0fa9647SJens Axboe return; 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 96183a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 96283a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 96383a12fb7SSagi Grimberg } 96457dacad5SJay Sternberg 9655cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 96683a12fb7SSagi Grimberg { 9675cb525c8SJens Axboe while (start != end) { 9685cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9695cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9705cb525c8SJens Axboe start = 0; 9715cb525c8SJens Axboe } 9725cb525c8SJens Axboe } 97383a12fb7SSagi Grimberg 9745cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9755cb525c8SJens Axboe { 976920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 977920d13a8SSagi Grimberg nvmeq->cq_head = 0; 978920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 979920d13a8SSagi Grimberg } 980a0fa9647SJens Axboe } 981a0fa9647SJens Axboe 9825cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9835cb525c8SJens Axboe u16 *end, int tag) 984a0fa9647SJens Axboe { 9855cb525c8SJens Axboe bool found = false; 98683a12fb7SSagi Grimberg 9875cb525c8SJens Axboe *start = nvmeq->cq_head; 9885cb525c8SJens Axboe while (!found && nvme_cqe_pending(nvmeq)) { 9895cb525c8SJens Axboe if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 9905cb525c8SJens Axboe found = true; 9915cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 99257dacad5SJay Sternberg } 9935cb525c8SJens Axboe *end = nvmeq->cq_head; 99457dacad5SJay Sternberg 9955cb525c8SJens Axboe if (*start != *end) 996eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9975cb525c8SJens Axboe return found; 99857dacad5SJay Sternberg } 99957dacad5SJay Sternberg 100057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 100157dacad5SJay Sternberg { 100257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 100368fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10045cb525c8SJens Axboe u16 start, end; 10055cb525c8SJens Axboe 10061ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 100768fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 100868fa9dbeSJens Axboe ret = IRQ_HANDLED; 10095cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 101068fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10111ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 10125cb525c8SJens Axboe 101368fa9dbeSJens Axboe if (start != end) { 10145cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10155cb525c8SJens Axboe return IRQ_HANDLED; 101657dacad5SJay Sternberg } 101757dacad5SJay Sternberg 101868fa9dbeSJens Axboe return ret; 101968fa9dbeSJens Axboe } 102068fa9dbeSJens Axboe 102157dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 102257dacad5SJay Sternberg { 102357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1024750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 102557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1026d783e0bdSMarta Rybczynska return IRQ_NONE; 102757dacad5SJay Sternberg } 102857dacad5SJay Sternberg 10297776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1030a0fa9647SJens Axboe { 10315cb525c8SJens Axboe u16 start, end; 10325cb525c8SJens Axboe bool found; 1033a0fa9647SJens Axboe 1034750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 1035442e19b7SSagi Grimberg return 0; 1036442e19b7SSagi Grimberg 10371ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 10385cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10391ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 1040442e19b7SSagi Grimberg 10415cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1042442e19b7SSagi Grimberg return found; 1043a0fa9647SJens Axboe } 1044a0fa9647SJens Axboe 10457776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10467776db1cSKeith Busch { 10477776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10487776db1cSKeith Busch 10497776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10507776db1cSKeith Busch } 10517776db1cSKeith Busch 1052ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 105357dacad5SJay Sternberg { 1054f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1055147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 105657dacad5SJay Sternberg struct nvme_command c; 105757dacad5SJay Sternberg 105857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105957dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1060ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 106157dacad5SJay Sternberg 10621eae349dSJens Axboe spin_lock(&nvmeq->sq_lock); 10639396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 10641eae349dSJens Axboe spin_unlock(&nvmeq->sq_lock); 106557dacad5SJay Sternberg } 106657dacad5SJay Sternberg 106757dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106857dacad5SJay Sternberg { 106957dacad5SJay Sternberg struct nvme_command c; 107057dacad5SJay Sternberg 107157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 107257dacad5SJay Sternberg c.delete_queue.opcode = opcode; 107357dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 107457dacad5SJay Sternberg 10751c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107657dacad5SJay Sternberg } 107757dacad5SJay Sternberg 107857dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1079a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 108057dacad5SJay Sternberg { 108157dacad5SJay Sternberg struct nvme_command c; 108257dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 108357dacad5SJay Sternberg 108457dacad5SJay Sternberg /* 108516772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 108657dacad5SJay Sternberg * is attached to the request. 108757dacad5SJay Sternberg */ 108857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108957dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 109057dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 109157dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 109257dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 109357dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1094a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 109557dacad5SJay Sternberg 10961c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 109757dacad5SJay Sternberg } 109857dacad5SJay Sternberg 109957dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 110057dacad5SJay Sternberg struct nvme_queue *nvmeq) 110157dacad5SJay Sternberg { 110257dacad5SJay Sternberg struct nvme_command c; 110381c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 110457dacad5SJay Sternberg 110557dacad5SJay Sternberg /* 110616772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 110757dacad5SJay Sternberg * is attached to the request. 110857dacad5SJay Sternberg */ 110957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111057dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 111157dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 111257dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 111357dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 111457dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 111557dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 111657dacad5SJay Sternberg 11171c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 111857dacad5SJay Sternberg } 111957dacad5SJay Sternberg 112057dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 112157dacad5SJay Sternberg { 112257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 112357dacad5SJay Sternberg } 112457dacad5SJay Sternberg 112557dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 112657dacad5SJay Sternberg { 112757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 112857dacad5SJay Sternberg } 112957dacad5SJay Sternberg 11302a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 113157dacad5SJay Sternberg { 1132f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1133f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 113457dacad5SJay Sternberg 113527fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 113627fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1137e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1138e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 113957dacad5SJay Sternberg } 114057dacad5SJay Sternberg 1141b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1142b2a0eb1aSKeith Busch { 1143b2a0eb1aSKeith Busch 1144b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1145b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1146b2a0eb1aSKeith Busch */ 1147b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1148b2a0eb1aSKeith Busch 1149ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1150ad70062cSJianchao Wang switch (dev->ctrl.state) { 1151ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1152ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1153b2a0eb1aSKeith Busch return false; 1154ad70062cSJianchao Wang default: 1155ad70062cSJianchao Wang break; 1156ad70062cSJianchao Wang } 1157b2a0eb1aSKeith Busch 1158b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1159b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1160b2a0eb1aSKeith Busch */ 1161b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1162b2a0eb1aSKeith Busch return false; 1163b2a0eb1aSKeith Busch 1164b2a0eb1aSKeith Busch return true; 1165b2a0eb1aSKeith Busch } 1166b2a0eb1aSKeith Busch 1167b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1168b2a0eb1aSKeith Busch { 1169b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1170b2a0eb1aSKeith Busch u16 pci_status; 1171b2a0eb1aSKeith Busch int result; 1172b2a0eb1aSKeith Busch 1173b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1174b2a0eb1aSKeith Busch &pci_status); 1175b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1176b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1177b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1178b2a0eb1aSKeith Busch csts, pci_status); 1179b2a0eb1aSKeith Busch else 1180b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1181b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1182b2a0eb1aSKeith Busch csts, result); 1183b2a0eb1aSKeith Busch } 1184b2a0eb1aSKeith Busch 118531c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 118657dacad5SJay Sternberg { 1187f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1188f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 118957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 119057dacad5SJay Sternberg struct request *abort_req; 119157dacad5SJay Sternberg struct nvme_command cmd; 1192b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1193b2a0eb1aSKeith Busch 1194651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1195651438bbSWen Xiong * the recovery mechanism will surely fail. 1196651438bbSWen Xiong */ 1197651438bbSWen Xiong mb(); 1198651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1199651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1200651438bbSWen Xiong 1201b2a0eb1aSKeith Busch /* 1202b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1203b2a0eb1aSKeith Busch */ 1204b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1205b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1206b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1207d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1208b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1209b2a0eb1aSKeith Busch } 121057dacad5SJay Sternberg 121131c7c7d2SChristoph Hellwig /* 12127776db1cSKeith Busch * Did we miss an interrupt? 12137776db1cSKeith Busch */ 12147776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12157776db1cSKeith Busch dev_warn(dev->ctrl.device, 12167776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12177776db1cSKeith Busch req->tag, nvmeq->qid); 12187776db1cSKeith Busch return BLK_EH_HANDLED; 12197776db1cSKeith Busch } 12207776db1cSKeith Busch 12217776db1cSKeith Busch /* 1222fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1223fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1224fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1225fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1226fd634f41SChristoph Hellwig */ 12274244140dSKeith Busch switch (dev->ctrl.state) { 12284244140dSKeith Busch case NVME_CTRL_CONNECTING: 12294244140dSKeith Busch case NVME_CTRL_RESETTING: 12301b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1231fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1232fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1233a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 123427fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1235fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 12364244140dSKeith Busch default: 12374244140dSKeith Busch break; 1238fd634f41SChristoph Hellwig } 1239fd634f41SChristoph Hellwig 1240fd634f41SChristoph Hellwig /* 1241e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1242e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1243e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 124431c7c7d2SChristoph Hellwig */ 1245f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12461b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 124757dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 124857dacad5SJay Sternberg req->tag, nvmeq->qid); 1249a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1250d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1251e1569a16SKeith Busch 1252e1569a16SKeith Busch /* 1253e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1254e1569a16SKeith Busch * forces all outstanding requests to complete. 1255e1569a16SKeith Busch */ 125627fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1257e1569a16SKeith Busch return BLK_EH_HANDLED; 125857dacad5SJay Sternberg } 125957dacad5SJay Sternberg 1260e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1261e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1262e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1263e7a2a87dSChristoph Hellwig } 12647bf7d778SKeith Busch iod->aborted = 1; 126557dacad5SJay Sternberg 126657dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 126757dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 126857dacad5SJay Sternberg cmd.abort.cid = req->tag; 126957dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 127057dacad5SJay Sternberg 12711b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12721b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 127357dacad5SJay Sternberg req->tag, nvmeq->qid); 1274e7a2a87dSChristoph Hellwig 1275e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1276eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12776bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12786bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 127931c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 128057dacad5SJay Sternberg } 128157dacad5SJay Sternberg 1282e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1283e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1284e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 128557dacad5SJay Sternberg 128657dacad5SJay Sternberg /* 128757dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 128857dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 128957dacad5SJay Sternberg * as the device then is in a faulty state. 129057dacad5SJay Sternberg */ 129157dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 129257dacad5SJay Sternberg } 129357dacad5SJay Sternberg 129457dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 129557dacad5SJay Sternberg { 129657dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 129757dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 129857dacad5SJay Sternberg if (nvmeq->sq_cmds) 129957dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 130057dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 130157dacad5SJay Sternberg } 130257dacad5SJay Sternberg 130357dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 130457dacad5SJay Sternberg { 130557dacad5SJay Sternberg int i; 130657dacad5SJay Sternberg 1307d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1308d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1309147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 131057dacad5SJay Sternberg } 131157dacad5SJay Sternberg } 131257dacad5SJay Sternberg 131357dacad5SJay Sternberg /** 131457dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 131557dacad5SJay Sternberg * @nvmeq - queue to suspend 131657dacad5SJay Sternberg */ 131757dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 131857dacad5SJay Sternberg { 131957dacad5SJay Sternberg int vector; 132057dacad5SJay Sternberg 13211ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 132257dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 13231ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 132457dacad5SJay Sternberg return 1; 132557dacad5SJay Sternberg } 13260ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 132757dacad5SJay Sternberg nvmeq->dev->online_queues--; 132857dacad5SJay Sternberg nvmeq->cq_vector = -1; 13291ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 133057dacad5SJay Sternberg 1331d1f06f4aSJens Axboe /* 1332d1f06f4aSJens Axboe * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1333d1f06f4aSJens Axboe * having to grab the lock. 1334d1f06f4aSJens Axboe */ 1335d1f06f4aSJens Axboe mb(); 1336d1f06f4aSJens Axboe 13371c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1338c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 133957dacad5SJay Sternberg 13400ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 134157dacad5SJay Sternberg 134257dacad5SJay Sternberg return 0; 134357dacad5SJay Sternberg } 134457dacad5SJay Sternberg 1345a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 134657dacad5SJay Sternberg { 1347147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 13485cb525c8SJens Axboe u16 start, end; 134957dacad5SJay Sternberg 1350a5cdb68cSKeith Busch if (shutdown) 1351a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1352a5cdb68cSKeith Busch else 135320d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 135457dacad5SJay Sternberg 13551ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 13565cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 13571ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 13585cb525c8SJens Axboe 13595cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 136057dacad5SJay Sternberg } 136157dacad5SJay Sternberg 136257dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 136357dacad5SJay Sternberg int entry_size) 136457dacad5SJay Sternberg { 136557dacad5SJay Sternberg int q_depth = dev->q_depth; 13665fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13675fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 136857dacad5SJay Sternberg 136957dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 137057dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13715fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 137257dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 137357dacad5SJay Sternberg 137457dacad5SJay Sternberg /* 137557dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 137657dacad5SJay Sternberg * would be better to map queues in system memory with the 137757dacad5SJay Sternberg * original depth 137857dacad5SJay Sternberg */ 137957dacad5SJay Sternberg if (q_depth < 64) 138057dacad5SJay Sternberg return -ENOMEM; 138157dacad5SJay Sternberg } 138257dacad5SJay Sternberg 138357dacad5SJay Sternberg return q_depth; 138457dacad5SJay Sternberg } 138557dacad5SJay Sternberg 138657dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 138757dacad5SJay Sternberg int qid, int depth) 138857dacad5SJay Sternberg { 1389815c6704SKeith Busch /* CMB SQEs will be mapped before creation */ 1390815c6704SKeith Busch if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1391815c6704SKeith Busch return 0; 1392815c6704SKeith Busch 139357dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 139457dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 139557dacad5SJay Sternberg if (!nvmeq->sq_cmds) 139657dacad5SJay Sternberg return -ENOMEM; 139757dacad5SJay Sternberg return 0; 139857dacad5SJay Sternberg } 139957dacad5SJay Sternberg 1400a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 140157dacad5SJay Sternberg { 1402147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 140357dacad5SJay Sternberg 140462314e40SKeith Busch if (dev->ctrl.queue_count > qid) 140562314e40SKeith Busch return 0; 140657dacad5SJay Sternberg 140757dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 140857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 140957dacad5SJay Sternberg if (!nvmeq->cqes) 141057dacad5SJay Sternberg goto free_nvmeq; 141157dacad5SJay Sternberg 141257dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 141357dacad5SJay Sternberg goto free_cqdma; 141457dacad5SJay Sternberg 141557dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 141657dacad5SJay Sternberg nvmeq->dev = dev; 14171ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14181ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 141957dacad5SJay Sternberg nvmeq->cq_head = 0; 142057dacad5SJay Sternberg nvmeq->cq_phase = 1; 142157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 142257dacad5SJay Sternberg nvmeq->q_depth = depth; 142357dacad5SJay Sternberg nvmeq->qid = qid; 142457dacad5SJay Sternberg nvmeq->cq_vector = -1; 1425d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 142657dacad5SJay Sternberg 1427147b27e4SSagi Grimberg return 0; 142857dacad5SJay Sternberg 142957dacad5SJay Sternberg free_cqdma: 143057dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 143157dacad5SJay Sternberg nvmeq->cq_dma_addr); 143257dacad5SJay Sternberg free_nvmeq: 1433147b27e4SSagi Grimberg return -ENOMEM; 143457dacad5SJay Sternberg } 143557dacad5SJay Sternberg 1436dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 143757dacad5SJay Sternberg { 14380ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14390ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14400ff199cbSChristoph Hellwig 14410ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14420ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14430ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14440ff199cbSChristoph Hellwig } else { 14450ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14460ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14470ff199cbSChristoph Hellwig } 144857dacad5SJay Sternberg } 144957dacad5SJay Sternberg 145057dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 145157dacad5SJay Sternberg { 145257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 145357dacad5SJay Sternberg 14541ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 145557dacad5SJay Sternberg nvmeq->sq_tail = 0; 145657dacad5SJay Sternberg nvmeq->cq_head = 0; 145757dacad5SJay Sternberg nvmeq->cq_phase = 1; 145857dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 145957dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1460f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 146157dacad5SJay Sternberg dev->online_queues++; 14621ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 146357dacad5SJay Sternberg } 146457dacad5SJay Sternberg 146557dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 146657dacad5SJay Sternberg { 146757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 146857dacad5SJay Sternberg int result; 1469a8e3e0bbSJianchao Wang s16 vector; 147057dacad5SJay Sternberg 1471815c6704SKeith Busch if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1472815c6704SKeith Busch unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1473815c6704SKeith Busch dev->ctrl.page_size); 1474815c6704SKeith Busch nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1475815c6704SKeith Busch nvmeq->sq_cmds_io = dev->cmb + offset; 1476815c6704SKeith Busch } 1477815c6704SKeith Busch 147822b55601SKeith Busch /* 147922b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 148022b55601SKeith Busch * has only one vector available. 148122b55601SKeith Busch */ 1482a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 1483a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 148457dacad5SJay Sternberg if (result < 0) 1485a8e3e0bbSJianchao Wang goto out; 148657dacad5SJay Sternberg 148757dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 148857dacad5SJay Sternberg if (result < 0) 148957dacad5SJay Sternberg goto release_cq; 149057dacad5SJay Sternberg 1491a8e3e0bbSJianchao Wang /* 1492a8e3e0bbSJianchao Wang * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1493a8e3e0bbSJianchao Wang * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1494a8e3e0bbSJianchao Wang * xxx' warning if the create CQ/SQ command times out. 1495a8e3e0bbSJianchao Wang */ 1496a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1497161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1498dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 149957dacad5SJay Sternberg if (result < 0) 150057dacad5SJay Sternberg goto release_sq; 150157dacad5SJay Sternberg 150257dacad5SJay Sternberg return result; 150357dacad5SJay Sternberg 150457dacad5SJay Sternberg release_sq: 1505a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1506f25a2dfcSJianchao Wang dev->online_queues--; 150757dacad5SJay Sternberg adapter_delete_sq(dev, qid); 150857dacad5SJay Sternberg release_cq: 150957dacad5SJay Sternberg adapter_delete_cq(dev, qid); 1510a8e3e0bbSJianchao Wang out: 151157dacad5SJay Sternberg return result; 151257dacad5SJay Sternberg } 151357dacad5SJay Sternberg 1514f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 151557dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 151677f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 151757dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 151857dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15190350815aSChristoph Hellwig .init_request = nvme_init_request, 152057dacad5SJay Sternberg .timeout = nvme_timeout, 152157dacad5SJay Sternberg }; 152257dacad5SJay Sternberg 1523f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 152457dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 152577f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 152657dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 152757dacad5SJay Sternberg .init_request = nvme_init_request, 1528dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 152957dacad5SJay Sternberg .timeout = nvme_timeout, 1530a0fa9647SJens Axboe .poll = nvme_poll, 153157dacad5SJay Sternberg }; 153257dacad5SJay Sternberg 153357dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 153457dacad5SJay Sternberg { 15351c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 153669d9a99cSKeith Busch /* 153769d9a99cSKeith Busch * If the controller was reset during removal, it's possible 153869d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 153969d9a99cSKeith Busch * queue to flush these to completion. 154069d9a99cSKeith Busch */ 1541c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15421c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 154357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 154457dacad5SJay Sternberg } 154557dacad5SJay Sternberg } 154657dacad5SJay Sternberg 154757dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 154857dacad5SJay Sternberg { 15491c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 155057dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 155157dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1552e3e9d50cSKeith Busch 155338dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 155457dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 155557dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1556a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1557d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 155857dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 155957dacad5SJay Sternberg 156057dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 156157dacad5SJay Sternberg return -ENOMEM; 156234b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 156357dacad5SJay Sternberg 15641c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15651c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 156657dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 156757dacad5SJay Sternberg return -ENOMEM; 156857dacad5SJay Sternberg } 15691c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 157057dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15711c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 157257dacad5SJay Sternberg return -ENODEV; 157357dacad5SJay Sternberg } 157457dacad5SJay Sternberg } else 1575c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 157657dacad5SJay Sternberg 157757dacad5SJay Sternberg return 0; 157857dacad5SJay Sternberg } 157957dacad5SJay Sternberg 158097f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 158197f6ef64SXu Yu { 158297f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 158397f6ef64SXu Yu } 158497f6ef64SXu Yu 158597f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 158697f6ef64SXu Yu { 158797f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 158897f6ef64SXu Yu 158997f6ef64SXu Yu if (size <= dev->bar_mapped_size) 159097f6ef64SXu Yu return 0; 159197f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 159297f6ef64SXu Yu return -ENOMEM; 159397f6ef64SXu Yu if (dev->bar) 159497f6ef64SXu Yu iounmap(dev->bar); 159597f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 159697f6ef64SXu Yu if (!dev->bar) { 159797f6ef64SXu Yu dev->bar_mapped_size = 0; 159897f6ef64SXu Yu return -ENOMEM; 159997f6ef64SXu Yu } 160097f6ef64SXu Yu dev->bar_mapped_size = size; 160197f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 160297f6ef64SXu Yu 160397f6ef64SXu Yu return 0; 160497f6ef64SXu Yu } 160597f6ef64SXu Yu 160601ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 160757dacad5SJay Sternberg { 160857dacad5SJay Sternberg int result; 160957dacad5SJay Sternberg u32 aqa; 161057dacad5SJay Sternberg struct nvme_queue *nvmeq; 161157dacad5SJay Sternberg 161297f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 161397f6ef64SXu Yu if (result < 0) 161497f6ef64SXu Yu return result; 161597f6ef64SXu Yu 16168ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 161720d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 161857dacad5SJay Sternberg 16197a67cbeaSChristoph Hellwig if (dev->subsystem && 16207a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16217a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 162257dacad5SJay Sternberg 162320d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 162457dacad5SJay Sternberg if (result < 0) 162557dacad5SJay Sternberg return result; 162657dacad5SJay Sternberg 1627a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1628147b27e4SSagi Grimberg if (result) 1629147b27e4SSagi Grimberg return result; 163057dacad5SJay Sternberg 1631147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 163257dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 163357dacad5SJay Sternberg aqa |= aqa << 16; 163457dacad5SJay Sternberg 16357a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16367a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16377a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 163857dacad5SJay Sternberg 163920d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 164057dacad5SJay Sternberg if (result) 1641d4875622SKeith Busch return result; 164257dacad5SJay Sternberg 164357dacad5SJay Sternberg nvmeq->cq_vector = 0; 1644161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1645dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 164657dacad5SJay Sternberg if (result) { 164757dacad5SJay Sternberg nvmeq->cq_vector = -1; 1648d4875622SKeith Busch return result; 164957dacad5SJay Sternberg } 165057dacad5SJay Sternberg 165157dacad5SJay Sternberg return result; 165257dacad5SJay Sternberg } 165357dacad5SJay Sternberg 1654749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 165557dacad5SJay Sternberg { 1656949928c1SKeith Busch unsigned i, max; 1657749941f2SChristoph Hellwig int ret = 0; 165857dacad5SJay Sternberg 1659d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1660a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1661749941f2SChristoph Hellwig ret = -ENOMEM; 166257dacad5SJay Sternberg break; 1663749941f2SChristoph Hellwig } 1664749941f2SChristoph Hellwig } 166557dacad5SJay Sternberg 1666d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1667949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1668147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1669d4875622SKeith Busch if (ret) 167057dacad5SJay Sternberg break; 167157dacad5SJay Sternberg } 167257dacad5SJay Sternberg 1673749941f2SChristoph Hellwig /* 1674749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16758adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16768adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1677749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1678749941f2SChristoph Hellwig */ 1679749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 168057dacad5SJay Sternberg } 168157dacad5SJay Sternberg 1682202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1683202021c1SStephen Bates struct device_attribute *attr, 1684202021c1SStephen Bates char *buf) 1685202021c1SStephen Bates { 1686202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1687202021c1SStephen Bates 1688c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1689202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1690202021c1SStephen Bates } 1691202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1692202021c1SStephen Bates 169388de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 169457dacad5SJay Sternberg { 169588de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 169688de4598SChristoph Hellwig 169788de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 169888de4598SChristoph Hellwig } 169988de4598SChristoph Hellwig 170088de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 170188de4598SChristoph Hellwig { 170288de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 170388de4598SChristoph Hellwig } 170488de4598SChristoph Hellwig 1705f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 170657dacad5SJay Sternberg { 170788de4598SChristoph Hellwig u64 size, offset; 170857dacad5SJay Sternberg resource_size_t bar_size; 170957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17108969f1f8SChristoph Hellwig int bar; 171157dacad5SJay Sternberg 17127a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1713f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1714f65efd6dSChristoph Hellwig return; 1715202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 171657dacad5SJay Sternberg 1717202021c1SStephen Bates if (!use_cmb_sqes) 1718f65efd6dSChristoph Hellwig return; 171957dacad5SJay Sternberg 172088de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 172188de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17228969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17238969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 172457dacad5SJay Sternberg 172557dacad5SJay Sternberg if (offset > bar_size) 1726f65efd6dSChristoph Hellwig return; 172757dacad5SJay Sternberg 172857dacad5SJay Sternberg /* 172957dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 173057dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 173157dacad5SJay Sternberg * the reported size of the BAR 173257dacad5SJay Sternberg */ 173357dacad5SJay Sternberg if (size > bar_size - offset) 173457dacad5SJay Sternberg size = bar_size - offset; 173557dacad5SJay Sternberg 1736f65efd6dSChristoph Hellwig dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1737f65efd6dSChristoph Hellwig if (!dev->cmb) 1738f65efd6dSChristoph Hellwig return; 17398969f1f8SChristoph Hellwig dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 174057dacad5SJay Sternberg dev->cmb_size = size; 1741f65efd6dSChristoph Hellwig 1742f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1743f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1744f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1745f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 174657dacad5SJay Sternberg } 174757dacad5SJay Sternberg 174857dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 174957dacad5SJay Sternberg { 175057dacad5SJay Sternberg if (dev->cmb) { 175157dacad5SJay Sternberg iounmap(dev->cmb); 175257dacad5SJay Sternberg dev->cmb = NULL; 1753f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1754f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1755f63572dfSJon Derrick dev->cmbsz = 0; 1756f63572dfSJon Derrick } 175757dacad5SJay Sternberg } 175857dacad5SJay Sternberg 175987ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 176057dacad5SJay Sternberg { 17614033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 176287ad72a5SChristoph Hellwig struct nvme_command c; 176387ad72a5SChristoph Hellwig int ret; 176487ad72a5SChristoph Hellwig 176587ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 176687ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 176787ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 176887ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 176987ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 177087ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 177187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 177287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 177387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 177487ad72a5SChristoph Hellwig 177587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 177687ad72a5SChristoph Hellwig if (ret) { 177787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 177887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 177987ad72a5SChristoph Hellwig ret, bits); 178087ad72a5SChristoph Hellwig } 178187ad72a5SChristoph Hellwig return ret; 178287ad72a5SChristoph Hellwig } 178387ad72a5SChristoph Hellwig 178487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 178587ad72a5SChristoph Hellwig { 178687ad72a5SChristoph Hellwig int i; 178787ad72a5SChristoph Hellwig 178887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 178987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 179087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 179187ad72a5SChristoph Hellwig 179287ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 179387ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 179487ad72a5SChristoph Hellwig } 179587ad72a5SChristoph Hellwig 179687ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 179787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17984033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17994033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18004033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 180187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18027e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 180387ad72a5SChristoph Hellwig } 180487ad72a5SChristoph Hellwig 180592dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 180692dc6895SChristoph Hellwig u32 chunk_size) 180787ad72a5SChristoph Hellwig { 180887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 180992dc6895SChristoph Hellwig u32 max_entries, len; 18104033f35dSChristoph Hellwig dma_addr_t descs_dma; 18112ee0e4edSDan Carpenter int i = 0; 181287ad72a5SChristoph Hellwig void **bufs; 18136fbcde66SMinwoo Im u64 size, tmp; 181487ad72a5SChristoph Hellwig 181587ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 181687ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 181787ad72a5SChristoph Hellwig max_entries = tmp; 1818044a9df1SChristoph Hellwig 1819044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1820044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1821044a9df1SChristoph Hellwig 18224033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 18234033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 182487ad72a5SChristoph Hellwig if (!descs) 182587ad72a5SChristoph Hellwig goto out; 182687ad72a5SChristoph Hellwig 182787ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 182887ad72a5SChristoph Hellwig if (!bufs) 182987ad72a5SChristoph Hellwig goto out_free_descs; 183087ad72a5SChristoph Hellwig 1831244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 183287ad72a5SChristoph Hellwig dma_addr_t dma_addr; 183387ad72a5SChristoph Hellwig 183450cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 183587ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 183687ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 183787ad72a5SChristoph Hellwig if (!bufs[i]) 183887ad72a5SChristoph Hellwig break; 183987ad72a5SChristoph Hellwig 184087ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 184187ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 184287ad72a5SChristoph Hellwig i++; 184387ad72a5SChristoph Hellwig } 184487ad72a5SChristoph Hellwig 184592dc6895SChristoph Hellwig if (!size) 184687ad72a5SChristoph Hellwig goto out_free_bufs; 184787ad72a5SChristoph Hellwig 184887ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 184987ad72a5SChristoph Hellwig dev->host_mem_size = size; 185087ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 18514033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 185287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 185387ad72a5SChristoph Hellwig return 0; 185487ad72a5SChristoph Hellwig 185587ad72a5SChristoph Hellwig out_free_bufs: 185687ad72a5SChristoph Hellwig while (--i >= 0) { 185787ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 185887ad72a5SChristoph Hellwig 185987ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 186087ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 186187ad72a5SChristoph Hellwig } 186287ad72a5SChristoph Hellwig 186387ad72a5SChristoph Hellwig kfree(bufs); 186487ad72a5SChristoph Hellwig out_free_descs: 18654033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18664033f35dSChristoph Hellwig descs_dma); 186787ad72a5SChristoph Hellwig out: 186887ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 186987ad72a5SChristoph Hellwig return -ENOMEM; 187087ad72a5SChristoph Hellwig } 187187ad72a5SChristoph Hellwig 187292dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 187392dc6895SChristoph Hellwig { 187492dc6895SChristoph Hellwig u32 chunk_size; 187592dc6895SChristoph Hellwig 187692dc6895SChristoph Hellwig /* start big and work our way down */ 187730f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1878044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 187992dc6895SChristoph Hellwig chunk_size /= 2) { 188092dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 188192dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 188292dc6895SChristoph Hellwig return 0; 188392dc6895SChristoph Hellwig nvme_free_host_mem(dev); 188492dc6895SChristoph Hellwig } 188592dc6895SChristoph Hellwig } 188692dc6895SChristoph Hellwig 188792dc6895SChristoph Hellwig return -ENOMEM; 188892dc6895SChristoph Hellwig } 188992dc6895SChristoph Hellwig 18909620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 189187ad72a5SChristoph Hellwig { 189287ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 189387ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 189487ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 189587ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18966fbcde66SMinwoo Im int ret; 189787ad72a5SChristoph Hellwig 189887ad72a5SChristoph Hellwig preferred = min(preferred, max); 189987ad72a5SChristoph Hellwig if (min > max) { 190087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 190187ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 190287ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 190387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19049620cfbaSChristoph Hellwig return 0; 190587ad72a5SChristoph Hellwig } 190687ad72a5SChristoph Hellwig 190787ad72a5SChristoph Hellwig /* 190887ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 190987ad72a5SChristoph Hellwig */ 191087ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 191187ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 191287ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 191387ad72a5SChristoph Hellwig else 191487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 191587ad72a5SChristoph Hellwig } 191687ad72a5SChristoph Hellwig 191787ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 191892dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 191992dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 192092dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19219620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 192287ad72a5SChristoph Hellwig } 192387ad72a5SChristoph Hellwig 192492dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 192592dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 192692dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 192792dc6895SChristoph Hellwig } 192892dc6895SChristoph Hellwig 19299620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19309620cfbaSChristoph Hellwig if (ret) 193187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19329620cfbaSChristoph Hellwig return ret; 193357dacad5SJay Sternberg } 193457dacad5SJay Sternberg 193557dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 193657dacad5SJay Sternberg { 1937147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 193857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 193997f6ef64SXu Yu int result, nr_io_queues; 194097f6ef64SXu Yu unsigned long size; 194157dacad5SJay Sternberg 194222b55601SKeith Busch struct irq_affinity affd = { 194322b55601SKeith Busch .pre_vectors = 1 194422b55601SKeith Busch }; 194522b55601SKeith Busch 194616ccfff2SMing Lei nr_io_queues = num_possible_cpus(); 19479a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 19489a0be7abSChristoph Hellwig if (result < 0) 194957dacad5SJay Sternberg return result; 19509a0be7abSChristoph Hellwig 1951f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1952a5229050SKeith Busch return 0; 195357dacad5SJay Sternberg 195488de4598SChristoph Hellwig if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 195557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 195657dacad5SJay Sternberg sizeof(struct nvme_command)); 195757dacad5SJay Sternberg if (result > 0) 195857dacad5SJay Sternberg dev->q_depth = result; 195957dacad5SJay Sternberg else 196057dacad5SJay Sternberg nvme_release_cmb(dev); 196157dacad5SJay Sternberg } 196257dacad5SJay Sternberg 196357dacad5SJay Sternberg do { 196497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 196597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 196697f6ef64SXu Yu if (!result) 196757dacad5SJay Sternberg break; 196857dacad5SJay Sternberg if (!--nr_io_queues) 196957dacad5SJay Sternberg return -ENOMEM; 197057dacad5SJay Sternberg } while (1); 197157dacad5SJay Sternberg adminq->q_db = dev->dbs; 197257dacad5SJay Sternberg 197357dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19740ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 197557dacad5SJay Sternberg 197657dacad5SJay Sternberg /* 197757dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 197857dacad5SJay Sternberg * setting up the full range we need. 197957dacad5SJay Sternberg */ 1980dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 198122b55601SKeith Busch result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 198222b55601SKeith Busch PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 198322b55601SKeith Busch if (result <= 0) 1984dca51e78SChristoph Hellwig return -EIO; 198522b55601SKeith Busch dev->num_vecs = result; 198622b55601SKeith Busch dev->max_qid = max(result - 1, 1); 198757dacad5SJay Sternberg 198857dacad5SJay Sternberg /* 198957dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 199057dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 199157dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 199257dacad5SJay Sternberg * number of interrupts. 199357dacad5SJay Sternberg */ 199457dacad5SJay Sternberg 1995dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 199657dacad5SJay Sternberg if (result) { 199757dacad5SJay Sternberg adminq->cq_vector = -1; 1998d4875622SKeith Busch return result; 199957dacad5SJay Sternberg } 2000749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 200157dacad5SJay Sternberg } 200257dacad5SJay Sternberg 20032a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2004db3cbfffSKeith Busch { 2005db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2006db3cbfffSKeith Busch 2007db3cbfffSKeith Busch blk_mq_free_request(req); 2008db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 2009db3cbfffSKeith Busch } 2010db3cbfffSKeith Busch 20112a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2012db3cbfffSKeith Busch { 2013db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 20145cb525c8SJens Axboe u16 start, end; 2015db3cbfffSKeith Busch 2016db3cbfffSKeith Busch if (!error) { 2017db3cbfffSKeith Busch unsigned long flags; 2018db3cbfffSKeith Busch 20192e39e0f6SMing Lin /* 20201ab0cd69SJens Axboe * We might be called with the AQ cq_lock held 20211ab0cd69SJens Axboe * and the I/O queue cq_lock should always 20222e39e0f6SMing Lin * nest inside the AQ one. 20232e39e0f6SMing Lin */ 20241ab0cd69SJens Axboe spin_lock_irqsave_nested(&nvmeq->cq_lock, flags, 20252e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 20265cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 20271ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 20285cb525c8SJens Axboe 20295cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 2030db3cbfffSKeith Busch } 2031db3cbfffSKeith Busch 2032db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2033db3cbfffSKeith Busch } 2034db3cbfffSKeith Busch 2035db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2036db3cbfffSKeith Busch { 2037db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2038db3cbfffSKeith Busch struct request *req; 2039db3cbfffSKeith Busch struct nvme_command cmd; 2040db3cbfffSKeith Busch 2041db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2042db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2043db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2044db3cbfffSKeith Busch 2045eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2046db3cbfffSKeith Busch if (IS_ERR(req)) 2047db3cbfffSKeith Busch return PTR_ERR(req); 2048db3cbfffSKeith Busch 2049db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2050db3cbfffSKeith Busch req->end_io_data = nvmeq; 2051db3cbfffSKeith Busch 2052db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2053db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2054db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2055db3cbfffSKeith Busch return 0; 2056db3cbfffSKeith Busch } 2057db3cbfffSKeith Busch 2058ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2059db3cbfffSKeith Busch { 2060ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2061db3cbfffSKeith Busch unsigned long timeout; 2062db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2063db3cbfffSKeith Busch 2064db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2065014a0d60SKeith Busch int sent = 0, i = queues; 2066db3cbfffSKeith Busch 2067db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2068db3cbfffSKeith Busch retry: 2069db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2070c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2071147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2072db3cbfffSKeith Busch break; 2073c21377f8SGabriel Krisman Bertazi 2074db3cbfffSKeith Busch while (sent--) { 2075db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2076db3cbfffSKeith Busch if (timeout == 0) 2077db3cbfffSKeith Busch return; 2078db3cbfffSKeith Busch if (i) 2079db3cbfffSKeith Busch goto retry; 2080db3cbfffSKeith Busch } 2081db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2082db3cbfffSKeith Busch } 2083db3cbfffSKeith Busch } 2084db3cbfffSKeith Busch 208557dacad5SJay Sternberg /* 20862b1b7e78SJianchao Wang * return error value only when tagset allocation failed 208757dacad5SJay Sternberg */ 208857dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 208957dacad5SJay Sternberg { 20902b1b7e78SJianchao Wang int ret; 20912b1b7e78SJianchao Wang 20925bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 209357dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 209457dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 209557dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 209657dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 209757dacad5SJay Sternberg dev->tagset.queue_depth = 209857dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2099a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2100a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2101a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2102a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2103a7a7cbe3SChaitanya Kulkarni } 210457dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 210557dacad5SJay Sternberg dev->tagset.driver_data = dev; 210657dacad5SJay Sternberg 21072b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 21082b1b7e78SJianchao Wang if (ret) { 21092b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 21102b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 21112b1b7e78SJianchao Wang return ret; 21122b1b7e78SJianchao Wang } 21135bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2114f9f38e33SHelen Koike 2115f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2116949928c1SKeith Busch } else { 2117949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2118949928c1SKeith Busch 2119949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2120949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 212157dacad5SJay Sternberg } 2122949928c1SKeith Busch 212357dacad5SJay Sternberg return 0; 212457dacad5SJay Sternberg } 212557dacad5SJay Sternberg 2126b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 212757dacad5SJay Sternberg { 2128b00a726aSKeith Busch int result = -ENOMEM; 212957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 213057dacad5SJay Sternberg 213157dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 213257dacad5SJay Sternberg return result; 213357dacad5SJay Sternberg 213457dacad5SJay Sternberg pci_set_master(pdev); 213557dacad5SJay Sternberg 213657dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 213757dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 213857dacad5SJay Sternberg goto disable; 213957dacad5SJay Sternberg 21407a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 214157dacad5SJay Sternberg result = -ENODEV; 2142b00a726aSKeith Busch goto disable; 214357dacad5SJay Sternberg } 214457dacad5SJay Sternberg 214557dacad5SJay Sternberg /* 2146a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2147a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2148a5229050SKeith Busch * adjust this later. 214957dacad5SJay Sternberg */ 2150dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2151dca51e78SChristoph Hellwig if (result < 0) 2152dca51e78SChristoph Hellwig return result; 215357dacad5SJay Sternberg 215420d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 21557a67cbeaSChristoph Hellwig 215620d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2157b27c1e68Sweiping zhang io_queue_depth); 215820d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21597a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21601f390c1fSStephan Günther 21611f390c1fSStephan Günther /* 21621f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21631f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21641f390c1fSStephan Günther */ 21651f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21661f390c1fSStephan Günther dev->q_depth = 2; 21679bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21689bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21691f390c1fSStephan Günther dev->q_depth); 2170d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2171d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 217220d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2173d554b5e1SMartin K. Petersen dev->q_depth = 64; 2174d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2175d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21761f390c1fSStephan Günther } 21771f390c1fSStephan Günther 2178f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2179202021c1SStephen Bates 2180a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2181a0a3408eSKeith Busch pci_save_state(pdev); 218257dacad5SJay Sternberg return 0; 218357dacad5SJay Sternberg 218457dacad5SJay Sternberg disable: 218557dacad5SJay Sternberg pci_disable_device(pdev); 218657dacad5SJay Sternberg return result; 218757dacad5SJay Sternberg } 218857dacad5SJay Sternberg 218957dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 219057dacad5SJay Sternberg { 2191b00a726aSKeith Busch if (dev->bar) 2192b00a726aSKeith Busch iounmap(dev->bar); 2193a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2194b00a726aSKeith Busch } 2195b00a726aSKeith Busch 2196b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2197b00a726aSKeith Busch { 219857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 219957dacad5SJay Sternberg 2200f63572dfSJon Derrick nvme_release_cmb(dev); 2201dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 220257dacad5SJay Sternberg 2203a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2204a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 220557dacad5SJay Sternberg pci_disable_device(pdev); 220657dacad5SJay Sternberg } 2207a0a3408eSKeith Busch } 220857dacad5SJay Sternberg 2209a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 221057dacad5SJay Sternberg { 2211ee9aebb2SKeith Busch int i; 2212302ad8ccSKeith Busch bool dead = true; 2213302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 221457dacad5SJay Sternberg 221577bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2216302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2217302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2218302ad8ccSKeith Busch 2219ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2220ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2221302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2222302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2223302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 222457dacad5SJay Sternberg } 2225c21377f8SGabriel Krisman Bertazi 2226302ad8ccSKeith Busch /* 2227302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2228302ad8ccSKeith Busch * doing a safe shutdown. 2229302ad8ccSKeith Busch */ 223087ad72a5SChristoph Hellwig if (!dead) { 223187ad72a5SChristoph Hellwig if (shutdown) 2232302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 22339a915a5bSJianchao Wang } 223487ad72a5SChristoph Hellwig 22359a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 22369a915a5bSJianchao Wang 223764ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 223887ad72a5SChristoph Hellwig /* 223987ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 224087ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 224187ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 224287ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 224387ad72a5SChristoph Hellwig */ 224487ad72a5SChristoph Hellwig if (dev->host_mem_descs) 224587ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 2246ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2247a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 224857dacad5SJay Sternberg } 2249ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2250ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2251ee9aebb2SKeith Busch 2252b00a726aSKeith Busch nvme_pci_disable(dev); 225357dacad5SJay Sternberg 2254e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2255e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2256302ad8ccSKeith Busch 2257302ad8ccSKeith Busch /* 2258302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2259302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2260302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2261302ad8ccSKeith Busch */ 2262302ad8ccSKeith Busch if (shutdown) 2263302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 226477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 226557dacad5SJay Sternberg } 226657dacad5SJay Sternberg 226757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 226857dacad5SJay Sternberg { 226957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 227057dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 227157dacad5SJay Sternberg if (!dev->prp_page_pool) 227257dacad5SJay Sternberg return -ENOMEM; 227357dacad5SJay Sternberg 227457dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 227557dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 227657dacad5SJay Sternberg 256, 256, 0); 227757dacad5SJay Sternberg if (!dev->prp_small_pool) { 227857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 227957dacad5SJay Sternberg return -ENOMEM; 228057dacad5SJay Sternberg } 228157dacad5SJay Sternberg return 0; 228257dacad5SJay Sternberg } 228357dacad5SJay Sternberg 228457dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 228557dacad5SJay Sternberg { 228657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 228757dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 228857dacad5SJay Sternberg } 228957dacad5SJay Sternberg 22901673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 229157dacad5SJay Sternberg { 22921673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 229357dacad5SJay Sternberg 2294f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 229557dacad5SJay Sternberg put_device(dev->dev); 229657dacad5SJay Sternberg if (dev->tagset.tags) 229757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22981c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22991c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 230057dacad5SJay Sternberg kfree(dev->queues); 2301e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 230257dacad5SJay Sternberg kfree(dev); 230357dacad5SJay Sternberg } 230457dacad5SJay Sternberg 2305f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2306f58944e2SKeith Busch { 2307237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2308f58944e2SKeith Busch 2309d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 231069d9a99cSKeith Busch nvme_dev_disable(dev, false); 231103e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2312f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2313f58944e2SKeith Busch } 2314f58944e2SKeith Busch 2315fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 231657dacad5SJay Sternberg { 2317d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2318d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2319a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2320f58944e2SKeith Busch int result = -ENODEV; 23212b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 232257dacad5SJay Sternberg 232382b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2324fd634f41SChristoph Hellwig goto out; 2325fd634f41SChristoph Hellwig 2326fd634f41SChristoph Hellwig /* 2327fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2328fd634f41SChristoph Hellwig * moving on. 2329fd634f41SChristoph Hellwig */ 2330b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2331a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2332fd634f41SChristoph Hellwig 2333ad70062cSJianchao Wang /* 2334ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2335ad70062cSJianchao Wang * initializing procedure here. 2336ad70062cSJianchao Wang */ 2337ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2338ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2339ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2340ad70062cSJianchao Wang goto out; 2341ad70062cSJianchao Wang } 2342ad70062cSJianchao Wang 2343b00a726aSKeith Busch result = nvme_pci_enable(dev); 234457dacad5SJay Sternberg if (result) 234557dacad5SJay Sternberg goto out; 234657dacad5SJay Sternberg 234701ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 234857dacad5SJay Sternberg if (result) 2349f58944e2SKeith Busch goto out; 235057dacad5SJay Sternberg 235157dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 235257dacad5SJay Sternberg if (result) 2353f58944e2SKeith Busch goto out; 235457dacad5SJay Sternberg 2355ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2356ce4541f4SChristoph Hellwig if (result) 2357f58944e2SKeith Busch goto out; 2358ce4541f4SChristoph Hellwig 2359e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2360e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23614f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23624f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2363e286bcfcSScott Bauer else if (was_suspend) 23644f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2365e286bcfcSScott Bauer } else { 2366e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2367e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2368e286bcfcSScott Bauer } 2369a98e58e5SScott Bauer 2370f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2371f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2372f9f38e33SHelen Koike if (result) 2373f9f38e33SHelen Koike dev_warn(dev->dev, 2374f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2375f9f38e33SHelen Koike } 2376f9f38e33SHelen Koike 23779620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23789620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23799620cfbaSChristoph Hellwig if (result < 0) 23809620cfbaSChristoph Hellwig goto out; 23819620cfbaSChristoph Hellwig } 238287ad72a5SChristoph Hellwig 238357dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 238457dacad5SJay Sternberg if (result) 2385f58944e2SKeith Busch goto out; 238657dacad5SJay Sternberg 238721f033f7SKeith Busch /* 238857dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 238957dacad5SJay Sternberg * any working I/O queue. 239057dacad5SJay Sternberg */ 239157dacad5SJay Sternberg if (dev->online_queues < 2) { 23921b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23933b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23945bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23952b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 239657dacad5SJay Sternberg } else { 239725646264SKeith Busch nvme_start_queues(&dev->ctrl); 2398302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23992b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 24002b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 24012b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2402302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 240357dacad5SJay Sternberg } 240457dacad5SJay Sternberg 24052b1b7e78SJianchao Wang /* 24062b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 24072b1b7e78SJianchao Wang * recovery. 24082b1b7e78SJianchao Wang */ 24092b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 24102b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 24112b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2412bb8d261eSChristoph Hellwig goto out; 2413bb8d261eSChristoph Hellwig } 241492911a55SChristoph Hellwig 2415d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 241657dacad5SJay Sternberg return; 241757dacad5SJay Sternberg 241857dacad5SJay Sternberg out: 2419f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 242057dacad5SJay Sternberg } 242157dacad5SJay Sternberg 24225c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 242357dacad5SJay Sternberg { 24245c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 242557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 242657dacad5SJay Sternberg 242769d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 242857dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2429921920abSKeith Busch device_release_driver(&pdev->dev); 24301673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 243157dacad5SJay Sternberg } 243257dacad5SJay Sternberg 24331c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 243457dacad5SJay Sternberg { 24351c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 24361c63dc66SChristoph Hellwig return 0; 243757dacad5SJay Sternberg } 24381c63dc66SChristoph Hellwig 24395fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 24405fd4ce1bSChristoph Hellwig { 24415fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 24425fd4ce1bSChristoph Hellwig return 0; 24435fd4ce1bSChristoph Hellwig } 24445fd4ce1bSChristoph Hellwig 24457fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 24467fd8930fSChristoph Hellwig { 24477fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24487fd8930fSChristoph Hellwig return 0; 24497fd8930fSChristoph Hellwig } 24507fd8930fSChristoph Hellwig 245197c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 245297c12223SKeith Busch { 245397c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 245497c12223SKeith Busch 245597c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 245697c12223SKeith Busch } 245797c12223SKeith Busch 24581c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24591a353d85SMing Lin .name = "pcie", 2460e439bb12SSagi Grimberg .module = THIS_MODULE, 2461c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24621c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24635fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24647fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24651673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2466f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 246797c12223SKeith Busch .get_address = nvme_pci_get_address, 24681c63dc66SChristoph Hellwig }; 246957dacad5SJay Sternberg 2470b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2471b00a726aSKeith Busch { 2472b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2473b00a726aSKeith Busch 2474a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2475b00a726aSKeith Busch return -ENODEV; 2476b00a726aSKeith Busch 247797f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2478b00a726aSKeith Busch goto release; 2479b00a726aSKeith Busch 2480b00a726aSKeith Busch return 0; 2481b00a726aSKeith Busch release: 2482a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2483b00a726aSKeith Busch return -ENODEV; 2484b00a726aSKeith Busch } 2485b00a726aSKeith Busch 24868427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2487ff5350a8SAndy Lutomirski { 2488ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2489ff5350a8SAndy Lutomirski /* 2490ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2491ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2492ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2493ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2494ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2495ff5350a8SAndy Lutomirski * laptops. 2496ff5350a8SAndy Lutomirski */ 2497ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2498ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2499ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2500ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 25018427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 25028427bbc2SKai-Heng Feng /* 25038427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2504467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2505467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2506467c77d4SJarosław Janik * ASUS PRIME Z370-A 25078427bbc2SKai-Heng Feng */ 25088427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2509467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2510467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 25118427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2512ff5350a8SAndy Lutomirski } 2513ff5350a8SAndy Lutomirski 2514ff5350a8SAndy Lutomirski return 0; 2515ff5350a8SAndy Lutomirski } 2516ff5350a8SAndy Lutomirski 251718119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 251818119775SKeith Busch { 251918119775SKeith Busch struct nvme_dev *dev = data; 252080f513b5SKeith Busch 252118119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 252218119775SKeith Busch flush_work(&dev->ctrl.scan_work); 252380f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 252418119775SKeith Busch } 252518119775SKeith Busch 252657dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 252757dacad5SJay Sternberg { 252857dacad5SJay Sternberg int node, result = -ENOMEM; 252957dacad5SJay Sternberg struct nvme_dev *dev; 2530ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 253157dacad5SJay Sternberg 253257dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 253357dacad5SJay Sternberg if (node == NUMA_NO_NODE) 25342fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 253557dacad5SJay Sternberg 253657dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 253757dacad5SJay Sternberg if (!dev) 253857dacad5SJay Sternberg return -ENOMEM; 2539147b27e4SSagi Grimberg 2540147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2541147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 254257dacad5SJay Sternberg if (!dev->queues) 254357dacad5SJay Sternberg goto free; 254457dacad5SJay Sternberg 254557dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 254657dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 254757dacad5SJay Sternberg 2548b00a726aSKeith Busch result = nvme_dev_map(dev); 2549b00a726aSKeith Busch if (result) 2550b00c9b7aSChristophe JAILLET goto put_pci; 2551b00a726aSKeith Busch 2552d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 25535c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 255477bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2555db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2556f3ca80fcSChristoph Hellwig 2557f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2558f3ca80fcSChristoph Hellwig if (result) 2559b00c9b7aSChristophe JAILLET goto unmap; 2560f3ca80fcSChristoph Hellwig 25618427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2562ff5350a8SAndy Lutomirski 2563f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2564ff5350a8SAndy Lutomirski quirks); 2565f3ca80fcSChristoph Hellwig if (result) 2566f3ca80fcSChristoph Hellwig goto release_pools; 2567f3ca80fcSChristoph Hellwig 25681b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25691b3c47c1SSagi Grimberg 257080f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 257118119775SKeith Busch async_schedule(nvme_async_probe, dev); 25724caff8fcSSagi Grimberg 257357dacad5SJay Sternberg return 0; 257457dacad5SJay Sternberg 257557dacad5SJay Sternberg release_pools: 257657dacad5SJay Sternberg nvme_release_prp_pools(dev); 2577b00c9b7aSChristophe JAILLET unmap: 2578b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 257957dacad5SJay Sternberg put_pci: 258057dacad5SJay Sternberg put_device(dev->dev); 258157dacad5SJay Sternberg free: 258257dacad5SJay Sternberg kfree(dev->queues); 258357dacad5SJay Sternberg kfree(dev); 258457dacad5SJay Sternberg return result; 258557dacad5SJay Sternberg } 258657dacad5SJay Sternberg 2587775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 258857dacad5SJay Sternberg { 258957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2590a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2591775755edSChristoph Hellwig } 259257dacad5SJay Sternberg 2593775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2594775755edSChristoph Hellwig { 2595f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 259679c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 259757dacad5SJay Sternberg } 259857dacad5SJay Sternberg 259957dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 260057dacad5SJay Sternberg { 260157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2602a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 260357dacad5SJay Sternberg } 260457dacad5SJay Sternberg 2605f58944e2SKeith Busch /* 2606f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2607f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2608f58944e2SKeith Busch * order to proceed. 2609f58944e2SKeith Busch */ 261057dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 261157dacad5SJay Sternberg { 261257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 261357dacad5SJay Sternberg 2614bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2615bb8d261eSChristoph Hellwig 2616d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 261757dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 26180ff9d4e1SKeith Busch 26196db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 26200ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 26216db28edaSKeith Busch nvme_dev_disable(dev, false); 26226db28edaSKeith Busch } 26230ff9d4e1SKeith Busch 2624d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2625d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2626d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2627a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 262887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 262957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 263057dacad5SJay Sternberg nvme_free_queues(dev, 0); 2631d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 263257dacad5SJay Sternberg nvme_release_prp_pools(dev); 2633b00a726aSKeith Busch nvme_dev_unmap(dev); 26341673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 263557dacad5SJay Sternberg } 263657dacad5SJay Sternberg 263713880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 263813880f5bSKeith Busch { 263913880f5bSKeith Busch int ret = 0; 264013880f5bSKeith Busch 264113880f5bSKeith Busch if (numvfs == 0) { 264213880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 264313880f5bSKeith Busch dev_warn(&pdev->dev, 264413880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 264513880f5bSKeith Busch return -EPERM; 264613880f5bSKeith Busch } 264713880f5bSKeith Busch pci_disable_sriov(pdev); 264813880f5bSKeith Busch return 0; 264913880f5bSKeith Busch } 265013880f5bSKeith Busch 265113880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 265213880f5bSKeith Busch return ret ? ret : numvfs; 265313880f5bSKeith Busch } 265413880f5bSKeith Busch 265557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 265657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 265757dacad5SJay Sternberg { 265857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 265957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 266057dacad5SJay Sternberg 2661a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 266257dacad5SJay Sternberg return 0; 266357dacad5SJay Sternberg } 266457dacad5SJay Sternberg 266557dacad5SJay Sternberg static int nvme_resume(struct device *dev) 266657dacad5SJay Sternberg { 266757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 266857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 266957dacad5SJay Sternberg 2670d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 267157dacad5SJay Sternberg return 0; 267257dacad5SJay Sternberg } 267357dacad5SJay Sternberg #endif 267457dacad5SJay Sternberg 267557dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 267657dacad5SJay Sternberg 2677a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2678a0a3408eSKeith Busch pci_channel_state_t state) 2679a0a3408eSKeith Busch { 2680a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2681a0a3408eSKeith Busch 2682a0a3408eSKeith Busch /* 2683a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2684a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2685a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2686a0a3408eSKeith Busch */ 2687a0a3408eSKeith Busch switch (state) { 2688a0a3408eSKeith Busch case pci_channel_io_normal: 2689a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2690a0a3408eSKeith Busch case pci_channel_io_frozen: 2691d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2692d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2693a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2694a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2695a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2696d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2697d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2698a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2699a0a3408eSKeith Busch } 2700a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2701a0a3408eSKeith Busch } 2702a0a3408eSKeith Busch 2703a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2704a0a3408eSKeith Busch { 2705a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2706a0a3408eSKeith Busch 27071b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2708a0a3408eSKeith Busch pci_restore_state(pdev); 2709cc1d5e74SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 2710cc1d5e74SKeith Busch 2711cc1d5e74SKeith Busch switch (dev->ctrl.state) { 2712cc1d5e74SKeith Busch case NVME_CTRL_LIVE: 2713cc1d5e74SKeith Busch case NVME_CTRL_ADMIN_ONLY: 2714a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2715cc1d5e74SKeith Busch default: 2716cc1d5e74SKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2717cc1d5e74SKeith Busch } 2718a0a3408eSKeith Busch } 2719a0a3408eSKeith Busch 2720a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2721a0a3408eSKeith Busch { 2722a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2723a0a3408eSKeith Busch } 2724a0a3408eSKeith Busch 272557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 272657dacad5SJay Sternberg .error_detected = nvme_error_detected, 272757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 272857dacad5SJay Sternberg .resume = nvme_error_resume, 2729775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2730775755edSChristoph Hellwig .reset_done = nvme_reset_done, 273157dacad5SJay Sternberg }; 273257dacad5SJay Sternberg 273357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2734106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 273508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2736e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 273799466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 273899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2739e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 274099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 274199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2742e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2743f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2744f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2745f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 274650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 274750af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2748540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2749540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 27500302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 27510302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 275254adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 275354adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 27548c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 27558c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2756015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2757015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2758d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2759d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2760d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2761d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2762608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2763608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2764608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2765608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2766ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2767ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 276857dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2769c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2770124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 277157dacad5SJay Sternberg { 0, } 277257dacad5SJay Sternberg }; 277357dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 277457dacad5SJay Sternberg 277557dacad5SJay Sternberg static struct pci_driver nvme_driver = { 277657dacad5SJay Sternberg .name = "nvme", 277757dacad5SJay Sternberg .id_table = nvme_id_table, 277857dacad5SJay Sternberg .probe = nvme_probe, 277957dacad5SJay Sternberg .remove = nvme_remove, 278057dacad5SJay Sternberg .shutdown = nvme_shutdown, 278157dacad5SJay Sternberg .driver = { 278257dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 278357dacad5SJay Sternberg }, 278413880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 278557dacad5SJay Sternberg .err_handler = &nvme_err_handler, 278657dacad5SJay Sternberg }; 278757dacad5SJay Sternberg 278857dacad5SJay Sternberg static int __init nvme_init(void) 278957dacad5SJay Sternberg { 27909a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 279157dacad5SJay Sternberg } 279257dacad5SJay Sternberg 279357dacad5SJay Sternberg static void __exit nvme_exit(void) 279457dacad5SJay Sternberg { 279557dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 279603e0f3a6SMing Lei flush_workqueue(nvme_wq); 279757dacad5SJay Sternberg _nvme_check_size(); 279857dacad5SJay Sternberg } 279957dacad5SJay Sternberg 280057dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 280157dacad5SJay Sternberg MODULE_LICENSE("GPL"); 280257dacad5SJay Sternberg MODULE_VERSION("1.0"); 280357dacad5SJay Sternberg module_init(nvme_init); 280457dacad5SJay Sternberg module_exit(nvme_exit); 2805