15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 18dc90f084SChristoph Hellwig #include <linux/memremap.h> 1957dacad5SJay Sternberg #include <linux/mm.h> 2057dacad5SJay Sternberg #include <linux/module.h> 2177bf25eaSKeith Busch #include <linux/mutex.h> 22d0877473SKeith Busch #include <linux/once.h> 2357dacad5SJay Sternberg #include <linux/pci.h> 24d916b1beSKeith Busch #include <linux/suspend.h> 2557dacad5SJay Sternberg #include <linux/t10-pi.h> 2657dacad5SJay Sternberg #include <linux/types.h> 279cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2820d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 29a98e58e5SScott Bauer #include <linux/sed-opal.h> 300f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3157dacad5SJay Sternberg 32604c01d5Syupeng #include "trace.h" 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 35c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 368a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 40943e942eSJens Axboe /* 41943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 42943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 43943e942eSJens Axboe */ 44943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 45943e942eSJens Axboe #define NVME_MAX_SEGS 127 46943e942eSJens Axboe 4757dacad5SJay Sternberg static int use_threaded_interrupts; 482e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5169f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 60a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 61a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 62a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 63a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 64a7a7cbe3SChaitanya Kulkarni 6527453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6627453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 7061f3b896SChaitanya Kulkarni .get = param_get_uint, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 7361f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7527453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76b27c1e68Sweiping zhang 779c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 789c9e76d5SWeiping Zhang { 799c9e76d5SWeiping Zhang unsigned int n; 809c9e76d5SWeiping Zhang int ret; 819c9e76d5SWeiping Zhang 829c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 839c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 849c9e76d5SWeiping Zhang return -EINVAL; 859c9e76d5SWeiping Zhang return param_set_uint(val, kp); 869c9e76d5SWeiping Zhang } 879c9e76d5SWeiping Zhang 889c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 899c9e76d5SWeiping Zhang .set = io_queue_count_set, 909c9e76d5SWeiping Zhang .get = param_get_uint, 919c9e76d5SWeiping Zhang }; 929c9e76d5SWeiping Zhang 933f68baf7SKeith Busch static unsigned int write_queues; 949c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 953b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 963b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 973b6592f7SJens Axboe "will share a queue set."); 983b6592f7SJens Axboe 993f68baf7SKeith Busch static unsigned int poll_queues; 1009c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1014b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1024b04cc6aSJens Axboe 103df4f9bc4SDavid E. Box static bool noacpi; 104df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 105df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106df4f9bc4SDavid E. Box 1071c63dc66SChristoph Hellwig struct nvme_dev; 1081c63dc66SChristoph Hellwig struct nvme_queue; 10957dacad5SJay Sternberg 110a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1118fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11257dacad5SJay Sternberg 11357dacad5SJay Sternberg /* 1141c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1151c63dc66SChristoph Hellwig */ 1161c63dc66SChristoph Hellwig struct nvme_dev { 117147b27e4SSagi Grimberg struct nvme_queue *queues; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1201c63dc66SChristoph Hellwig u32 __iomem *dbs; 1211c63dc66SChristoph Hellwig struct device *dev; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1241c63dc66SChristoph Hellwig unsigned online_queues; 1251c63dc66SChristoph Hellwig unsigned max_qid; 126e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12722b55601SKeith Busch unsigned int num_vecs; 1287442ddceSJohn Garry u32 q_depth; 129c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1301c63dc66SChristoph Hellwig u32 db_stride; 1311c63dc66SChristoph Hellwig void __iomem *bar; 13297f6ef64SXu Yu unsigned long bar_mapped_size; 1335c8809e6SChristoph Hellwig struct work_struct remove_work; 13477bf25eaSKeith Busch struct mutex shutdown_lock; 1351c63dc66SChristoph Hellwig bool subsystem; 1361c63dc66SChristoph Hellwig u64 cmb_size; 1370f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1381c63dc66SChristoph Hellwig u32 cmbsz; 139202021c1SStephen Bates u32 cmbloc; 1401c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 141d916b1beSKeith Busch u32 last_ps; 142a5df5e79SKeith Busch bool hmb; 14387ad72a5SChristoph Hellwig 144943e942eSJens Axboe mempool_t *iod_mempool; 145943e942eSJens Axboe 14687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 147f9f38e33SHelen Koike u32 *dbbuf_dbs; 148f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 149f9f38e33SHelen Koike u32 *dbbuf_eis; 150f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15187ad72a5SChristoph Hellwig 15287ad72a5SChristoph Hellwig /* host memory buffer support: */ 15387ad72a5SChristoph Hellwig u64 host_mem_size; 15487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1554033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1582a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 16157dacad5SJay Sternberg }; 16257dacad5SJay Sternberg 163b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 164b27c1e68Sweiping zhang { 16527453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16627453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 167b27c1e68Sweiping zhang } 168b27c1e68Sweiping zhang 169f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return qid * 2 * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 174f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175f9f38e33SHelen Koike { 176f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 177f9f38e33SHelen Koike } 178f9f38e33SHelen Koike 1791c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1801c63dc66SChristoph Hellwig { 1811c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1821c63dc66SChristoph Hellwig } 1831c63dc66SChristoph Hellwig 18457dacad5SJay Sternberg /* 18557dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18657dacad5SJay Sternberg * commands and one for I/O commands). 18757dacad5SJay Sternberg */ 18857dacad5SJay Sternberg struct nvme_queue { 18957dacad5SJay Sternberg struct nvme_dev *dev; 1901ab0cd69SJens Axboe spinlock_t sq_lock; 191c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1923a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1933a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19474943d45SKeith Busch struct nvme_completion *cqes; 19557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19757dacad5SJay Sternberg u32 __iomem *q_db; 1987442ddceSJohn Garry u32 q_depth; 1997c349ddeSKeith Busch u16 cq_vector; 20057dacad5SJay Sternberg u16 sq_tail; 20138210800SKeith Busch u16 last_sq_tail; 20257dacad5SJay Sternberg u16 cq_head; 20357dacad5SJay Sternberg u16 qid; 20457dacad5SJay Sternberg u8 cq_phase; 205c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2064e224106SChristoph Hellwig unsigned long flags; 2074e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20863223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 209d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2107c349ddeSKeith Busch #define NVMEQ_POLLED 3 211f9f38e33SHelen Koike u32 *dbbuf_sq_db; 212f9f38e33SHelen Koike u32 *dbbuf_cq_db; 213f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 214f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 215d1ed6aa1SChristoph Hellwig struct completion delete_done; 21657dacad5SJay Sternberg }; 21757dacad5SJay Sternberg 21857dacad5SJay Sternberg /* 2199b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2209b048119SChristoph Hellwig * 2219b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2229b048119SChristoph Hellwig * to the actual struct scatterlist. 22371bd150cSChristoph Hellwig */ 22471bd150cSChristoph Hellwig struct nvme_iod { 225d49187e9SChristoph Hellwig struct nvme_request req; 226af7fae85SKeith Busch struct nvme_command cmd; 227a7a7cbe3SChaitanya Kulkarni bool use_sgl; 22852da4f3fSKeith Busch bool aborted; 229c372cdd1SKeith Busch s8 nr_allocations; /* PRP list pool allocations. 0 means small 230c372cdd1SKeith Busch pool in use */ 231dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 232c4c22c52SKeith Busch dma_addr_t first_dma; 233783b94bdSChristoph Hellwig dma_addr_t meta_dma; 23491fb2b60SLogan Gunthorpe struct sg_table sgt; 23557dacad5SJay Sternberg }; 23657dacad5SJay Sternberg 2372a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2383b6592f7SJens Axboe { 2392a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 240f9f38e33SHelen Koike } 241f9f38e33SHelen Koike 242f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 243f9f38e33SHelen Koike { 2442a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 245f9f38e33SHelen Koike 24658847f12SKeith Busch if (dev->dbbuf_dbs) { 24758847f12SKeith Busch /* 24858847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 24958847f12SKeith Busch * values from the previous instantiation. 25058847f12SKeith Busch */ 25158847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25258847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 253f9f38e33SHelen Koike return 0; 25458847f12SKeith Busch } 255f9f38e33SHelen Koike 256f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 257f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 258f9f38e33SHelen Koike GFP_KERNEL); 259f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 260f9f38e33SHelen Koike return -ENOMEM; 261f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 262f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 263f9f38e33SHelen Koike GFP_KERNEL); 264f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 265f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 266f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 267f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 268f9f38e33SHelen Koike return -ENOMEM; 269f9f38e33SHelen Koike } 270f9f38e33SHelen Koike 271f9f38e33SHelen Koike return 0; 272f9f38e33SHelen Koike } 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 275f9f38e33SHelen Koike { 2762a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 277f9f38e33SHelen Koike 278f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 279f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 280f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 281f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 282f9f38e33SHelen Koike } 283f9f38e33SHelen Koike if (dev->dbbuf_eis) { 284f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 285f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 286f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 287f9f38e33SHelen Koike } 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 291f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 292f9f38e33SHelen Koike { 293f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 294f9f38e33SHelen Koike return; 295f9f38e33SHelen Koike 296f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 297f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 298f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 299f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 300f9f38e33SHelen Koike } 301f9f38e33SHelen Koike 3020f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3030f0d2c87SMinwoo Im { 3040f0d2c87SMinwoo Im if (!nvmeq->qid) 3050f0d2c87SMinwoo Im return; 3060f0d2c87SMinwoo Im 3070f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3080f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3090f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3100f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3110f0d2c87SMinwoo Im } 3120f0d2c87SMinwoo Im 313f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 314f9f38e33SHelen Koike { 315f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3160f0d2c87SMinwoo Im unsigned int i; 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 319f9f38e33SHelen Koike return; 320f9f38e33SHelen Koike 321f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 322f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 323f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3269bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 327f9f38e33SHelen Koike /* Free memory and continue on */ 328f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3290f0d2c87SMinwoo Im 3300f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3310f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 332f9f38e33SHelen Koike } 333f9f38e33SHelen Koike } 334f9f38e33SHelen Koike 335f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 336f9f38e33SHelen Koike { 337f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 338f9f38e33SHelen Koike } 339f9f38e33SHelen Koike 340f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 341f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 342f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 343f9f38e33SHelen Koike { 344f9f38e33SHelen Koike if (dbbuf_db) { 345f9f38e33SHelen Koike u16 old_value; 346f9f38e33SHelen Koike 347f9f38e33SHelen Koike /* 348f9f38e33SHelen Koike * Ensure that the queue is written before updating 349f9f38e33SHelen Koike * the doorbell in memory 350f9f38e33SHelen Koike */ 351f9f38e33SHelen Koike wmb(); 352f9f38e33SHelen Koike 353f9f38e33SHelen Koike old_value = *dbbuf_db; 354f9f38e33SHelen Koike *dbbuf_db = value; 355f9f38e33SHelen Koike 356f1ed3df2SMichal Wnukowski /* 357f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 358f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 359f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 360f1ed3df2SMichal Wnukowski * the doorbell. 361f1ed3df2SMichal Wnukowski */ 362f1ed3df2SMichal Wnukowski mb(); 363f1ed3df2SMichal Wnukowski 364f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 365f9f38e33SHelen Koike return false; 366f9f38e33SHelen Koike } 367f9f38e33SHelen Koike 368f9f38e33SHelen Koike return true; 36957dacad5SJay Sternberg } 37057dacad5SJay Sternberg 37157dacad5SJay Sternberg /* 37257dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37357dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37457dacad5SJay Sternberg * the I/O. 37557dacad5SJay Sternberg */ 376b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37757dacad5SJay Sternberg { 378b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3796c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38057dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38157dacad5SJay Sternberg } 38257dacad5SJay Sternberg 383a7a7cbe3SChaitanya Kulkarni /* 384a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 385a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 386a7a7cbe3SChaitanya Kulkarni */ 387b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 388f4800d6dSChristoph Hellwig { 389b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 390b13c6393SChaitanya Kulkarni PAGE_SIZE); 391f4800d6dSChristoph Hellwig } 392f4800d6dSChristoph Hellwig 39357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39457dacad5SJay Sternberg unsigned int hctx_idx) 39557dacad5SJay Sternberg { 39657dacad5SJay Sternberg struct nvme_dev *dev = data; 397147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 39857dacad5SJay Sternberg 39957dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40057dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg hctx->driver_data = nvmeq; 40357dacad5SJay Sternberg return 0; 40457dacad5SJay Sternberg } 40557dacad5SJay Sternberg 40657dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40757dacad5SJay Sternberg unsigned int hctx_idx) 40857dacad5SJay Sternberg { 40957dacad5SJay Sternberg struct nvme_dev *dev = data; 410147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41157dacad5SJay Sternberg 41257dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41357dacad5SJay Sternberg hctx->driver_data = nvmeq; 41457dacad5SJay Sternberg return 0; 41557dacad5SJay Sternberg } 41657dacad5SJay Sternberg 417e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 418e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 419e559398fSChristoph Hellwig unsigned int numa_node) 42057dacad5SJay Sternberg { 421d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 422f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 42359e29ce6SSagi Grimberg 42459e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 425f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 42657dacad5SJay Sternberg return 0; 42757dacad5SJay Sternberg } 42857dacad5SJay Sternberg 4293b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4303b6592f7SJens Axboe { 4313b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4323b6592f7SJens Axboe if (dev->num_vecs > 1) 4333b6592f7SJens Axboe return 1; 4343b6592f7SJens Axboe 4353b6592f7SJens Axboe return 0; 4363b6592f7SJens Axboe } 4373b6592f7SJens Axboe 438a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 439dca51e78SChristoph Hellwig { 440dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4413b6592f7SJens Axboe int i, qoff, offset; 442dca51e78SChristoph Hellwig 4433b6592f7SJens Axboe offset = queue_irq_offset(dev); 4443b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4453b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4463b6592f7SJens Axboe 4473b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4483b6592f7SJens Axboe if (!map->nr_queues) { 449e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4507e849dd9SChristoph Hellwig continue; 4513b6592f7SJens Axboe } 4523b6592f7SJens Axboe 4534b04cc6aSJens Axboe /* 4544b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4554b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4564b04cc6aSJens Axboe */ 4573b6592f7SJens Axboe map->queue_offset = qoff; 458cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4593b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4604b04cc6aSJens Axboe else 4614b04cc6aSJens Axboe blk_mq_map_queues(map); 4623b6592f7SJens Axboe qoff += map->nr_queues; 4633b6592f7SJens Axboe offset += map->nr_queues; 4643b6592f7SJens Axboe } 465dca51e78SChristoph Hellwig } 466dca51e78SChristoph Hellwig 46738210800SKeith Busch /* 46838210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 46938210800SKeith Busch */ 47038210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47104f3eafdSJens Axboe { 47238210800SKeith Busch if (!write_sq) { 47338210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47438210800SKeith Busch 47538210800SKeith Busch if (next_tail == nvmeq->q_depth) 47638210800SKeith Busch next_tail = 0; 47738210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 47838210800SKeith Busch return; 47938210800SKeith Busch } 48038210800SKeith Busch 48104f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48204f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48304f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48438210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 48504f3eafdSJens Axboe } 48604f3eafdSJens Axboe 4873233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4883233b94cSJens Axboe struct nvme_command *cmd) 48957dacad5SJay Sternberg { 490c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 4913233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 49290ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49390ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49404f3eafdSJens Axboe } 49504f3eafdSJens Axboe 49604f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 49704f3eafdSJens Axboe { 49804f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 49904f3eafdSJens Axboe 50004f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50138210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50238210800SKeith Busch nvme_write_sq_db(nvmeq, true); 50390ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50457dacad5SJay Sternberg } 50557dacad5SJay Sternberg 506a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 50757dacad5SJay Sternberg { 508f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 50991fb2b60SLogan Gunthorpe return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 51057dacad5SJay Sternberg } 51157dacad5SJay Sternberg 512955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 513955b1b5aSMinwoo Im { 514a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 51520469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 516955b1b5aSMinwoo Im unsigned int avg_seg_size; 517955b1b5aSMinwoo Im 51820469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 519955b1b5aSMinwoo Im 520253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 521955b1b5aSMinwoo Im return false; 522a53232cbSKeith Busch if (!nvmeq->qid) 523955b1b5aSMinwoo Im return false; 524955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 525955b1b5aSMinwoo Im return false; 526955b1b5aSMinwoo Im return true; 527955b1b5aSMinwoo Im } 528955b1b5aSMinwoo Im 5299275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 53057dacad5SJay Sternberg { 5316c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5329275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5339275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 53457dacad5SJay Sternberg int i; 53557dacad5SJay Sternberg 536c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5379275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5389275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5399275c206SChristoph Hellwig 5409275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5419275c206SChristoph Hellwig dma_addr = next_dma_addr; 542dff824b2SChristoph Hellwig } 5439275c206SChristoph Hellwig } 5449275c206SChristoph Hellwig 5459275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5469275c206SChristoph Hellwig { 5479275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5489275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5499275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5509275c206SChristoph Hellwig int i; 5519275c206SChristoph Hellwig 552c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5539275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5549275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5559275c206SChristoph Hellwig 5569275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5579275c206SChristoph Hellwig dma_addr = next_dma_addr; 5589275c206SChristoph Hellwig } 5599275c206SChristoph Hellwig } 5609275c206SChristoph Hellwig 5619275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5629275c206SChristoph Hellwig { 5639275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5647fe07d14SChristoph Hellwig 5659275c206SChristoph Hellwig if (iod->dma_len) { 5669275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5679275c206SChristoph Hellwig rq_dma_dir(req)); 5689275c206SChristoph Hellwig return; 5699275c206SChristoph Hellwig } 5709275c206SChristoph Hellwig 57191fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5729275c206SChristoph Hellwig 57391fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 57491fb2b60SLogan Gunthorpe 575c372cdd1SKeith Busch if (iod->nr_allocations == 0) 576a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 5779275c206SChristoph Hellwig iod->first_dma); 5789275c206SChristoph Hellwig else if (iod->use_sgl) 5799275c206SChristoph Hellwig nvme_free_sgls(dev, req); 5809275c206SChristoph Hellwig else 5819275c206SChristoph Hellwig nvme_free_prps(dev, req); 58291fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 58357dacad5SJay Sternberg } 58457dacad5SJay Sternberg 585d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 586d0877473SKeith Busch { 587d0877473SKeith Busch int i; 588d0877473SKeith Busch struct scatterlist *sg; 589d0877473SKeith Busch 590d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 591d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 592d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 593d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 594d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 595d0877473SKeith Busch sg_dma_len(sg)); 596d0877473SKeith Busch } 597d0877473SKeith Busch } 598d0877473SKeith Busch 599a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 600a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 60157dacad5SJay Sternberg { 602f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 60357dacad5SJay Sternberg struct dma_pool *pool; 604b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 60591fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 60657dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 60757dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6086c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 60957dacad5SJay Sternberg __le64 *prp_list; 610a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 61157dacad5SJay Sternberg dma_addr_t prp_dma; 61257dacad5SJay Sternberg int nprps, i; 61357dacad5SJay Sternberg 6146c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6155228b328SJan H. Schönherr if (length <= 0) { 6165228b328SJan H. Schönherr iod->first_dma = 0; 617a7a7cbe3SChaitanya Kulkarni goto done; 6185228b328SJan H. Schönherr } 61957dacad5SJay Sternberg 6206c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 62157dacad5SJay Sternberg if (dma_len) { 6226c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 62357dacad5SJay Sternberg } else { 62457dacad5SJay Sternberg sg = sg_next(sg); 62557dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 62657dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62757dacad5SJay Sternberg } 62857dacad5SJay Sternberg 6296c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 63057dacad5SJay Sternberg iod->first_dma = dma_addr; 631a7a7cbe3SChaitanya Kulkarni goto done; 63257dacad5SJay Sternberg } 63357dacad5SJay Sternberg 6346c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 63557dacad5SJay Sternberg if (nprps <= (256 / 8)) { 63657dacad5SJay Sternberg pool = dev->prp_small_pool; 637c372cdd1SKeith Busch iod->nr_allocations = 0; 63857dacad5SJay Sternberg } else { 63957dacad5SJay Sternberg pool = dev->prp_page_pool; 640c372cdd1SKeith Busch iod->nr_allocations = 1; 64157dacad5SJay Sternberg } 64257dacad5SJay Sternberg 64369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64457dacad5SJay Sternberg if (!prp_list) { 645c372cdd1SKeith Busch iod->nr_allocations = -1; 64686eea289SKeith Busch return BLK_STS_RESOURCE; 64757dacad5SJay Sternberg } 64857dacad5SJay Sternberg list[0] = prp_list; 64957dacad5SJay Sternberg iod->first_dma = prp_dma; 65057dacad5SJay Sternberg i = 0; 65157dacad5SJay Sternberg for (;;) { 6526c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 65357dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65557dacad5SJay Sternberg if (!prp_list) 656fa073216SChristoph Hellwig goto free_prps; 657c372cdd1SKeith Busch list[iod->nr_allocations++] = prp_list; 65857dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 65957dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 66057dacad5SJay Sternberg i = 1; 66157dacad5SJay Sternberg } 66257dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6636c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6646c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6656c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 66657dacad5SJay Sternberg if (length <= 0) 66757dacad5SJay Sternberg break; 66857dacad5SJay Sternberg if (dma_len > 0) 66957dacad5SJay Sternberg continue; 67086eea289SKeith Busch if (unlikely(dma_len < 0)) 67186eea289SKeith Busch goto bad_sgl; 67257dacad5SJay Sternberg sg = sg_next(sg); 67357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 67557dacad5SJay Sternberg } 676a7a7cbe3SChaitanya Kulkarni done: 67791fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 678a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 67986eea289SKeith Busch return BLK_STS_OK; 680fa073216SChristoph Hellwig free_prps: 681fa073216SChristoph Hellwig nvme_free_prps(dev, req); 682fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 68386eea289SKeith Busch bad_sgl: 68491fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 685d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 68691fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 68786eea289SKeith Busch return BLK_STS_IOERR; 68857dacad5SJay Sternberg } 68957dacad5SJay Sternberg 690a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 691a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 692a7a7cbe3SChaitanya Kulkarni { 693a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 694a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 695a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 696a7a7cbe3SChaitanya Kulkarni } 697a7a7cbe3SChaitanya Kulkarni 698a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 699a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 700a7a7cbe3SChaitanya Kulkarni { 701a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 702a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 703a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 704a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 705a7a7cbe3SChaitanya Kulkarni } else { 706a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 707a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 708a7a7cbe3SChaitanya Kulkarni } 709a7a7cbe3SChaitanya Kulkarni } 710a7a7cbe3SChaitanya Kulkarni 711a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 71291fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 713a7a7cbe3SChaitanya Kulkarni { 714a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 715a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 716a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 71791fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 71891fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 719a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 720b0f2853bSChristoph Hellwig int i = 0; 721a7a7cbe3SChaitanya Kulkarni 722a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 723a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 724a7a7cbe3SChaitanya Kulkarni 725b0f2853bSChristoph Hellwig if (entries == 1) { 726a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 727a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 728a7a7cbe3SChaitanya Kulkarni } 729a7a7cbe3SChaitanya Kulkarni 730a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 731a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 732c372cdd1SKeith Busch iod->nr_allocations = 0; 733a7a7cbe3SChaitanya Kulkarni } else { 734a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 735c372cdd1SKeith Busch iod->nr_allocations = 1; 736a7a7cbe3SChaitanya Kulkarni } 737a7a7cbe3SChaitanya Kulkarni 738a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 739a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 740c372cdd1SKeith Busch iod->nr_allocations = -1; 741a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 742a7a7cbe3SChaitanya Kulkarni } 743a7a7cbe3SChaitanya Kulkarni 744a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 745a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 746a7a7cbe3SChaitanya Kulkarni 747a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 748a7a7cbe3SChaitanya Kulkarni 749a7a7cbe3SChaitanya Kulkarni do { 750a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 751a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 752a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 755a7a7cbe3SChaitanya Kulkarni if (!sg_list) 756fa073216SChristoph Hellwig goto free_sgls; 757a7a7cbe3SChaitanya Kulkarni 758a7a7cbe3SChaitanya Kulkarni i = 0; 759c372cdd1SKeith Busch nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; 760a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 761a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 762a7a7cbe3SChaitanya Kulkarni } 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 765a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 766b0f2853bSChristoph Hellwig } while (--entries > 0); 767a7a7cbe3SChaitanya Kulkarni 768a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 769fa073216SChristoph Hellwig free_sgls: 770fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 771fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 772a7a7cbe3SChaitanya Kulkarni } 773a7a7cbe3SChaitanya Kulkarni 774dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 775dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 776dff824b2SChristoph Hellwig struct bio_vec *bv) 777dff824b2SChristoph Hellwig { 778dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7796c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7806c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 781dff824b2SChristoph Hellwig 782dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 783dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 784dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 785dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 786dff824b2SChristoph Hellwig 787dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 788dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 789dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 790359c1f88SBaolin Wang return BLK_STS_OK; 791dff824b2SChristoph Hellwig } 792dff824b2SChristoph Hellwig 79329791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 79429791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 79529791057SChristoph Hellwig struct bio_vec *bv) 79629791057SChristoph Hellwig { 79729791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 79829791057SChristoph Hellwig 79929791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 80029791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 80129791057SChristoph Hellwig return BLK_STS_RESOURCE; 80229791057SChristoph Hellwig iod->dma_len = bv->bv_len; 80329791057SChristoph Hellwig 804049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 80529791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 80629791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 80729791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 808359c1f88SBaolin Wang return BLK_STS_OK; 80929791057SChristoph Hellwig } 81029791057SChristoph Hellwig 811fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 812b131c61dSChristoph Hellwig struct nvme_command *cmnd) 81357dacad5SJay Sternberg { 814f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 81570479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 81691fb2b60SLogan Gunthorpe int rc; 81757dacad5SJay Sternberg 818dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 819a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 820dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 821dff824b2SChristoph Hellwig 822dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8236c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 824dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 825dff824b2SChristoph Hellwig &cmnd->rw, &bv); 82629791057SChristoph Hellwig 827a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 828253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 82929791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 83029791057SChristoph Hellwig &cmnd->rw, &bv); 831dff824b2SChristoph Hellwig } 832dff824b2SChristoph Hellwig } 833dff824b2SChristoph Hellwig 834dff824b2SChristoph Hellwig iod->dma_len = 0; 83591fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 83691fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 8379b048119SChristoph Hellwig return BLK_STS_RESOURCE; 83891fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 83991fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 84091fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 841fa073216SChristoph Hellwig goto out_free_sg; 842ba1ca37eSChristoph Hellwig 84391fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 84491fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 84591fb2b60SLogan Gunthorpe if (rc) { 84691fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 84791fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 848fa073216SChristoph Hellwig goto out_free_sg; 84991fb2b60SLogan Gunthorpe } 850ba1ca37eSChristoph Hellwig 85170479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 852955b1b5aSMinwoo Im if (iod->use_sgl) 85391fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 854a7a7cbe3SChaitanya Kulkarni else 855a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8564aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 857fa073216SChristoph Hellwig goto out_unmap_sg; 858fa073216SChristoph Hellwig return BLK_STS_OK; 859fa073216SChristoph Hellwig 860fa073216SChristoph Hellwig out_unmap_sg: 86191fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 862fa073216SChristoph Hellwig out_free_sg: 86391fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 864ba1ca37eSChristoph Hellwig return ret; 86557dacad5SJay Sternberg } 86657dacad5SJay Sternberg 8674aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8684aedb705SChristoph Hellwig struct nvme_command *cmnd) 8694aedb705SChristoph Hellwig { 8704aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8714aedb705SChristoph Hellwig 8724aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8734aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8744aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8754aedb705SChristoph Hellwig return BLK_STS_IOERR; 8764aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 877359c1f88SBaolin Wang return BLK_STS_OK; 8784aedb705SChristoph Hellwig } 8794aedb705SChristoph Hellwig 88062451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 88162451a2bSJens Axboe { 88262451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 88362451a2bSJens Axboe blk_status_t ret; 88462451a2bSJens Axboe 88552da4f3fSKeith Busch iod->aborted = false; 886c372cdd1SKeith Busch iod->nr_allocations = -1; 88791fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 88862451a2bSJens Axboe 88962451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 89062451a2bSJens Axboe if (ret) 89162451a2bSJens Axboe return ret; 89262451a2bSJens Axboe 89362451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 89462451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 89562451a2bSJens Axboe if (ret) 89662451a2bSJens Axboe goto out_free_cmd; 89762451a2bSJens Axboe } 89862451a2bSJens Axboe 89962451a2bSJens Axboe if (blk_integrity_rq(req)) { 90062451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 90162451a2bSJens Axboe if (ret) 90262451a2bSJens Axboe goto out_unmap_data; 90362451a2bSJens Axboe } 90462451a2bSJens Axboe 90562451a2bSJens Axboe blk_mq_start_request(req); 90662451a2bSJens Axboe return BLK_STS_OK; 90762451a2bSJens Axboe out_unmap_data: 90862451a2bSJens Axboe nvme_unmap_data(dev, req); 90962451a2bSJens Axboe out_free_cmd: 91062451a2bSJens Axboe nvme_cleanup_cmd(req); 91162451a2bSJens Axboe return ret; 91262451a2bSJens Axboe } 91362451a2bSJens Axboe 91457dacad5SJay Sternberg /* 91557dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91657dacad5SJay Sternberg */ 917fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91857dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91957dacad5SJay Sternberg { 92057dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92257dacad5SJay Sternberg struct request *req = bd->rq; 9239b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 924ebe6d874SChristoph Hellwig blk_status_t ret; 92557dacad5SJay Sternberg 926d1f06f4aSJens Axboe /* 927d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 928d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 929d1f06f4aSJens Axboe */ 9304e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 931d1f06f4aSJens Axboe return BLK_STS_IOERR; 932d1f06f4aSJens Axboe 93362451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 934d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 935d4060d2bSTao Chiu 93662451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 93762451a2bSJens Axboe if (unlikely(ret)) 938f4800d6dSChristoph Hellwig return ret; 9393233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9403233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9413233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9423233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 943fc17b653SChristoph Hellwig return BLK_STS_OK; 94457dacad5SJay Sternberg } 94557dacad5SJay Sternberg 946d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 947d62cbcf6SJens Axboe { 948d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 949d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 950d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 951d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 952d62cbcf6SJens Axboe 953d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 954d62cbcf6SJens Axboe } 955d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 956d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 957d62cbcf6SJens Axboe } 958d62cbcf6SJens Axboe 959d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 960d62cbcf6SJens Axboe { 961d62cbcf6SJens Axboe /* 962d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 963d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 964d62cbcf6SJens Axboe */ 965d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 966d62cbcf6SJens Axboe return false; 967d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 968d62cbcf6SJens Axboe return false; 969d62cbcf6SJens Axboe 970d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 971d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 972d62cbcf6SJens Axboe } 973d62cbcf6SJens Axboe 974d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 975d62cbcf6SJens Axboe { 9766bfec799SKeith Busch struct request *req, *next, *prev = NULL; 977d62cbcf6SJens Axboe struct request *requeue_list = NULL; 978d62cbcf6SJens Axboe 9796bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 980d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 981d62cbcf6SJens Axboe 982d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 983d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9846bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9856bfec799SKeith Busch 9866bfec799SKeith Busch req = prev; 9876bfec799SKeith Busch if (!req) 9886bfec799SKeith Busch continue; 989d62cbcf6SJens Axboe } 990d62cbcf6SJens Axboe 9916bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 992d62cbcf6SJens Axboe /* detach rest of list, and submit */ 9936bfec799SKeith Busch req->rq_next = NULL; 994d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 9956bfec799SKeith Busch *rqlist = next; 9966bfec799SKeith Busch prev = NULL; 9976bfec799SKeith Busch } else 9986bfec799SKeith Busch prev = req; 999d62cbcf6SJens Axboe } 1000d62cbcf6SJens Axboe 1001d62cbcf6SJens Axboe *rqlist = requeue_list; 1002d62cbcf6SJens Axboe } 1003d62cbcf6SJens Axboe 1004c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1005eee417b0SChristoph Hellwig { 1006a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1007a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 1008eee417b0SChristoph Hellwig 1009a53232cbSKeith Busch if (blk_integrity_rq(req)) { 1010a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1011a53232cbSKeith Busch 10124aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10134aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1014a53232cbSKeith Busch } 1015a53232cbSKeith Busch 1016b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10174aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1018c234a653SJens Axboe } 1019c234a653SJens Axboe 1020c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1021c234a653SJens Axboe { 1022c234a653SJens Axboe nvme_pci_unmap_rq(req); 102377f02a7aSChristoph Hellwig nvme_complete_rq(req); 102457dacad5SJay Sternberg } 102557dacad5SJay Sternberg 1026c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1027c234a653SJens Axboe { 1028c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1029c234a653SJens Axboe } 1030c234a653SJens Axboe 1031d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1032750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1033d783e0bdSMarta Rybczynska { 103474943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 103574943d45SKeith Busch 103674943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1037d783e0bdSMarta Rybczynska } 1038d783e0bdSMarta Rybczynska 1039eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 104057dacad5SJay Sternberg { 1041eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 104257dacad5SJay Sternberg 1043eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1044eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1045eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1046eb281c82SSagi Grimberg } 1047adf68f21SChristoph Hellwig 1048cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1049cfa27356SChristoph Hellwig { 1050cfa27356SChristoph Hellwig if (!nvmeq->qid) 1051cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1052cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1053cfa27356SChristoph Hellwig } 1054cfa27356SChristoph Hellwig 1055c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1056c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 105757dacad5SJay Sternberg { 105874943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 105962df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 106057dacad5SJay Sternberg struct request *req; 1061adf68f21SChristoph Hellwig 1062adf68f21SChristoph Hellwig /* 1063adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1064adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1065adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1066adf68f21SChristoph Hellwig * for them but rather special case them here. 1067adf68f21SChristoph Hellwig */ 106862df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10697bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 107083a12fb7SSagi Grimberg cqe->status, &cqe->result); 1071a0fa9647SJens Axboe return; 107257dacad5SJay Sternberg } 107357dacad5SJay Sternberg 1074e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 107550b7c243SXianting Tian if (unlikely(!req)) { 107650b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 107750b7c243SXianting Tian "invalid id %d completed on queue %d\n", 107862df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 107950b7c243SXianting Tian return; 108050b7c243SXianting Tian } 108150b7c243SXianting Tian 1082604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1083c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1084c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1085c234a653SJens Axboe nvme_pci_complete_batch)) 1086ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 108783a12fb7SSagi Grimberg } 108857dacad5SJay Sternberg 10895cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10905cb525c8SJens Axboe { 1091a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1092a8de6639SAlexey Dobriyan 1093a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1094920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1095e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1096a8de6639SAlexey Dobriyan } else { 1097a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1098920d13a8SSagi Grimberg } 1099a0fa9647SJens Axboe } 1100a0fa9647SJens Axboe 1101c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1102c234a653SJens Axboe struct io_comp_batch *iob) 1103a0fa9647SJens Axboe { 11041052b8acSJens Axboe int found = 0; 110583a12fb7SSagi Grimberg 11061052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11071052b8acSJens Axboe found++; 1108b69e2ef2SKeith Busch /* 1109b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1110b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1111b69e2ef2SKeith Busch */ 1112b69e2ef2SKeith Busch dma_rmb(); 1113c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11145cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 111557dacad5SJay Sternberg } 111657dacad5SJay Sternberg 1117324b494cSKeith Busch if (found) 1118eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11195cb525c8SJens Axboe return found; 112057dacad5SJay Sternberg } 112157dacad5SJay Sternberg 112257dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 112357dacad5SJay Sternberg { 112457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11254f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11265cb525c8SJens Axboe 11274f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11284f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11294f502245SJens Axboe nvme_pci_complete_batch(&iob); 113005fae499SChaitanya Kulkarni return IRQ_HANDLED; 11314f502245SJens Axboe } 113205fae499SChaitanya Kulkarni return IRQ_NONE; 113357dacad5SJay Sternberg } 113457dacad5SJay Sternberg 113557dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 113657dacad5SJay Sternberg { 113757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11384e523547SBaolin Wang 1139750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 114057dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1141d783e0bdSMarta Rybczynska return IRQ_NONE; 114257dacad5SJay Sternberg } 114357dacad5SJay Sternberg 11440b2a8a9fSChristoph Hellwig /* 1145fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11460b2a8a9fSChristoph Hellwig * Can be called from any context. 11470b2a8a9fSChristoph Hellwig */ 1148fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1149a0fa9647SJens Axboe { 11503a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1151a0fa9647SJens Axboe 1152fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1153fa059b85SKeith Busch 11543a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1155c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11563a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 115791a509f8SChristoph Hellwig } 1158442e19b7SSagi Grimberg 11595a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11607776db1cSKeith Busch { 11617776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1162dabcefabSJens Axboe bool found; 1163dabcefabSJens Axboe 1164dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1165dabcefabSJens Axboe return 0; 1166dabcefabSJens Axboe 11673a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1168c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11693a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1170dabcefabSJens Axboe 1171dabcefabSJens Axboe return found; 1172dabcefabSJens Axboe } 1173dabcefabSJens Axboe 1174ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 117557dacad5SJay Sternberg { 1176f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1177147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1178f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 117957dacad5SJay Sternberg 118057dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1181ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11823233b94cSJens Axboe 11833233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11843233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11853233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11863233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 118757dacad5SJay Sternberg } 118857dacad5SJay Sternberg 118957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 119057dacad5SJay Sternberg { 1191f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 119257dacad5SJay Sternberg 119357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 119457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 119557dacad5SJay Sternberg 11961c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 119757dacad5SJay Sternberg } 119857dacad5SJay Sternberg 119957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1200a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 120157dacad5SJay Sternberg { 1202f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12034b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12044b04cc6aSJens Axboe 12057c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12064b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 120757dacad5SJay Sternberg 120857dacad5SJay Sternberg /* 120916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 121057dacad5SJay Sternberg * is attached to the request. 121157dacad5SJay Sternberg */ 121257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 121357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 121457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 121557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 121657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1217a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 121857dacad5SJay Sternberg 12191c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122057dacad5SJay Sternberg } 122157dacad5SJay Sternberg 122257dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 122357dacad5SJay Sternberg struct nvme_queue *nvmeq) 122457dacad5SJay Sternberg { 12259abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1226f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 122781c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 122857dacad5SJay Sternberg 122957dacad5SJay Sternberg /* 12309abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12319abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12329abd68efSJens Axboe * URGENT. 12339abd68efSJens Axboe */ 12349abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12359abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12369abd68efSJens Axboe 12379abd68efSJens Axboe /* 123816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 123957dacad5SJay Sternberg * is attached to the request. 124057dacad5SJay Sternberg */ 124157dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 124257dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 124357dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 124457dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 124557dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 124657dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 124757dacad5SJay Sternberg 12481c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 124957dacad5SJay Sternberg } 125057dacad5SJay Sternberg 125157dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 125257dacad5SJay Sternberg { 125357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 125457dacad5SJay Sternberg } 125557dacad5SJay Sternberg 125657dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 125757dacad5SJay Sternberg { 125857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 125957dacad5SJay Sternberg } 126057dacad5SJay Sternberg 1261de671d61SJens Axboe static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 126257dacad5SJay Sternberg { 1263a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 126457dacad5SJay Sternberg 126527fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 126627fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1267e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1268e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 1269de671d61SJens Axboe return RQ_END_IO_NONE; 127057dacad5SJay Sternberg } 127157dacad5SJay Sternberg 1272b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1273b2a0eb1aSKeith Busch { 1274b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1275b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1276b2a0eb1aSKeith Busch */ 1277b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1278b2a0eb1aSKeith Busch 1279ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1280ad70062cSJianchao Wang switch (dev->ctrl.state) { 1281ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1282ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1283b2a0eb1aSKeith Busch return false; 1284ad70062cSJianchao Wang default: 1285ad70062cSJianchao Wang break; 1286ad70062cSJianchao Wang } 1287b2a0eb1aSKeith Busch 1288b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1289b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1290b2a0eb1aSKeith Busch */ 1291b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1292b2a0eb1aSKeith Busch return false; 1293b2a0eb1aSKeith Busch 1294b2a0eb1aSKeith Busch return true; 1295b2a0eb1aSKeith Busch } 1296b2a0eb1aSKeith Busch 1297b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1298b2a0eb1aSKeith Busch { 1299b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1300b2a0eb1aSKeith Busch u16 pci_status; 1301b2a0eb1aSKeith Busch int result; 1302b2a0eb1aSKeith Busch 1303b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1304b2a0eb1aSKeith Busch &pci_status); 1305b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1306b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1307b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1308b2a0eb1aSKeith Busch csts, pci_status); 1309b2a0eb1aSKeith Busch else 1310b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1311b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1312b2a0eb1aSKeith Busch csts, result); 13134641a8e6SKeith Busch 13144641a8e6SKeith Busch if (csts != ~0) 13154641a8e6SKeith Busch return; 13164641a8e6SKeith Busch 13174641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13184641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 13194641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13204641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1321b2a0eb1aSKeith Busch } 1322b2a0eb1aSKeith Busch 13239bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 132457dacad5SJay Sternberg { 1325f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1326a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 132757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 132857dacad5SJay Sternberg struct request *abort_req; 1329f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1330b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1331b2a0eb1aSKeith Busch 1332651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1333651438bbSWen Xiong * the recovery mechanism will surely fail. 1334651438bbSWen Xiong */ 1335651438bbSWen Xiong mb(); 1336651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1337651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1338651438bbSWen Xiong 1339b2a0eb1aSKeith Busch /* 1340b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1341b2a0eb1aSKeith Busch */ 1342b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1343b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1344b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1345d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1346db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1347b2a0eb1aSKeith Busch } 134857dacad5SJay Sternberg 134931c7c7d2SChristoph Hellwig /* 13507776db1cSKeith Busch * Did we miss an interrupt? 13517776db1cSKeith Busch */ 1352fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13535a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1354fa059b85SKeith Busch else 1355bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1356fa059b85SKeith Busch 1357bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13587776db1cSKeith Busch dev_warn(dev->ctrl.device, 13597776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13607776db1cSKeith Busch req->tag, nvmeq->qid); 1361db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13627776db1cSKeith Busch } 13637776db1cSKeith Busch 13647776db1cSKeith Busch /* 1365fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1366fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1367fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1368db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1369fd634f41SChristoph Hellwig */ 13704244140dSKeith Busch switch (dev->ctrl.state) { 13714244140dSKeith Busch case NVME_CTRL_CONNECTING: 13722036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1373df561f66SGustavo A. R. Silva fallthrough; 13742036f726SKeith Busch case NVME_CTRL_DELETING: 1375b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1376fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1377fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 137827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13797ad92f65STong Zhang nvme_dev_disable(dev, true); 1380db8c48e4SChristoph Hellwig return BLK_EH_DONE; 138139a9dd81SKeith Busch case NVME_CTRL_RESETTING: 138239a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13834244140dSKeith Busch default: 13844244140dSKeith Busch break; 1385fd634f41SChristoph Hellwig } 1386fd634f41SChristoph Hellwig 1387fd634f41SChristoph Hellwig /* 1388e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1389e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1390e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 139131c7c7d2SChristoph Hellwig */ 1392f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13931b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 139457dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 139557dacad5SJay Sternberg req->tag, nvmeq->qid); 13967ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1397a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1398d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1399e1569a16SKeith Busch 1400db8c48e4SChristoph Hellwig return BLK_EH_DONE; 140157dacad5SJay Sternberg } 140257dacad5SJay Sternberg 1403e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1404e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1405e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1406e7a2a87dSChristoph Hellwig } 140752da4f3fSKeith Busch iod->aborted = true; 140857dacad5SJay Sternberg 140957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 141085f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 141157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 141257dacad5SJay Sternberg 14131b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 141486141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 141586141440SChristoph Hellwig req->tag, 141686141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 141786141440SChristoph Hellwig nvmeq->qid); 1418e7a2a87dSChristoph Hellwig 1419e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 142039dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14216bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14226bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 142331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 142457dacad5SJay Sternberg } 1425e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 142657dacad5SJay Sternberg 1427e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1428e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1429128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1430e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 143157dacad5SJay Sternberg 143257dacad5SJay Sternberg /* 143357dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 143457dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 143557dacad5SJay Sternberg * as the device then is in a faulty state. 143657dacad5SJay Sternberg */ 143757dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 143857dacad5SJay Sternberg } 143957dacad5SJay Sternberg 144057dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 144157dacad5SJay Sternberg { 14428a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 144357dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 144463223078SChristoph Hellwig if (!nvmeq->sq_cmds) 144563223078SChristoph Hellwig return; 14460f238ff5SLogan Gunthorpe 144763223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 144888a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14498a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 145063223078SChristoph Hellwig } else { 14518a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 145263223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14530f238ff5SLogan Gunthorpe } 145457dacad5SJay Sternberg } 145557dacad5SJay Sternberg 145657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 145757dacad5SJay Sternberg { 145857dacad5SJay Sternberg int i; 145957dacad5SJay Sternberg 1460d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1461d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1462147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 146357dacad5SJay Sternberg } 146457dacad5SJay Sternberg } 146557dacad5SJay Sternberg 146657dacad5SJay Sternberg /** 146757dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 146840581d1aSBart Van Assche * @nvmeq: queue to suspend 146957dacad5SJay Sternberg */ 147057dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 147157dacad5SJay Sternberg { 14724e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 147357dacad5SJay Sternberg return 1; 147457dacad5SJay Sternberg 14754e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1476d1f06f4aSJens Axboe mb(); 147757dacad5SJay Sternberg 14784e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14791c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14806ca1d902SMing Lei nvme_stop_admin_queue(&nvmeq->dev->ctrl); 14817c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14824e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 148357dacad5SJay Sternberg return 0; 148457dacad5SJay Sternberg } 148557dacad5SJay Sternberg 14868fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14878fae268bSKeith Busch { 14888fae268bSKeith Busch int i; 14898fae268bSKeith Busch 14908fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14918fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14928fae268bSKeith Busch } 14938fae268bSKeith Busch 1494a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 149557dacad5SJay Sternberg { 1496147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 149757dacad5SJay Sternberg 1498a5cdb68cSKeith Busch if (shutdown) 1499a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1500a5cdb68cSKeith Busch else 1501b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 150257dacad5SJay Sternberg 1503bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 150457dacad5SJay Sternberg } 150557dacad5SJay Sternberg 1506fa46c6fbSKeith Busch /* 1507fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15089210c075SDongli Zhang * that can check this device's completion queues have synced, except 15099210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15109210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1511fa46c6fbSKeith Busch */ 1512fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1513fa46c6fbSKeith Busch { 1514fa46c6fbSKeith Busch int i; 1515fa46c6fbSKeith Busch 15169210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15179210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1518c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15199210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15209210c075SDongli Zhang } 1521fa46c6fbSKeith Busch } 1522fa46c6fbSKeith Busch 152357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 152457dacad5SJay Sternberg int entry_size) 152557dacad5SJay Sternberg { 152657dacad5SJay Sternberg int q_depth = dev->q_depth; 15275fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15286c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 152957dacad5SJay Sternberg 153057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 153157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15324e523547SBaolin Wang 15336c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 153457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 153557dacad5SJay Sternberg 153657dacad5SJay Sternberg /* 153757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 153857dacad5SJay Sternberg * would be better to map queues in system memory with the 153957dacad5SJay Sternberg * original depth 154057dacad5SJay Sternberg */ 154157dacad5SJay Sternberg if (q_depth < 64) 154257dacad5SJay Sternberg return -ENOMEM; 154357dacad5SJay Sternberg } 154457dacad5SJay Sternberg 154557dacad5SJay Sternberg return q_depth; 154657dacad5SJay Sternberg } 154757dacad5SJay Sternberg 154857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15498a1d09a6SBenjamin Herrenschmidt int qid) 155057dacad5SJay Sternberg { 15510f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1552815c6704SKeith Busch 15530f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15548a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1555bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15560f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15570f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 155863223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 155963223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 156063223078SChristoph Hellwig return 0; 156163223078SChristoph Hellwig } 1562bfac8e9fSAlan Mikhak 15638a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1564bfac8e9fSAlan Mikhak } 15650f238ff5SLogan Gunthorpe } 15660f238ff5SLogan Gunthorpe 15678a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 156857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 156957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 157057dacad5SJay Sternberg return -ENOMEM; 157157dacad5SJay Sternberg return 0; 157257dacad5SJay Sternberg } 157357dacad5SJay Sternberg 1574a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 157557dacad5SJay Sternberg { 1576147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 157757dacad5SJay Sternberg 157862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 157962314e40SKeith Busch return 0; 158057dacad5SJay Sternberg 1581c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15828a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15838a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 158457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 158557dacad5SJay Sternberg if (!nvmeq->cqes) 158657dacad5SJay Sternberg goto free_nvmeq; 158757dacad5SJay Sternberg 15888a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 158957dacad5SJay Sternberg goto free_cqdma; 159057dacad5SJay Sternberg 159157dacad5SJay Sternberg nvmeq->dev = dev; 15921ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15933a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 159457dacad5SJay Sternberg nvmeq->cq_head = 0; 159557dacad5SJay Sternberg nvmeq->cq_phase = 1; 159657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 159757dacad5SJay Sternberg nvmeq->qid = qid; 1598d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 159957dacad5SJay Sternberg 1600147b27e4SSagi Grimberg return 0; 160157dacad5SJay Sternberg 160257dacad5SJay Sternberg free_cqdma: 16038a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 160457dacad5SJay Sternberg nvmeq->cq_dma_addr); 160557dacad5SJay Sternberg free_nvmeq: 1606147b27e4SSagi Grimberg return -ENOMEM; 160757dacad5SJay Sternberg } 160857dacad5SJay Sternberg 1609dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 161057dacad5SJay Sternberg { 16110ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16120ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16130ff199cbSChristoph Hellwig 16140ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16150ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16160ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16170ff199cbSChristoph Hellwig } else { 16180ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16190ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16200ff199cbSChristoph Hellwig } 162157dacad5SJay Sternberg } 162257dacad5SJay Sternberg 162357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 162457dacad5SJay Sternberg { 162557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 162657dacad5SJay Sternberg 162757dacad5SJay Sternberg nvmeq->sq_tail = 0; 162838210800SKeith Busch nvmeq->last_sq_tail = 0; 162957dacad5SJay Sternberg nvmeq->cq_head = 0; 163057dacad5SJay Sternberg nvmeq->cq_phase = 1; 163157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16328a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1633f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 163457dacad5SJay Sternberg dev->online_queues++; 16353a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 163657dacad5SJay Sternberg } 163757dacad5SJay Sternberg 1638e4b9852aSCasey Chen /* 1639e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1640e4b9852aSCasey Chen */ 1641e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1642e4b9852aSCasey Chen { 1643e4b9852aSCasey Chen /* 1644e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1645e4b9852aSCasey Chen */ 1646e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1647e4b9852aSCasey Chen return -ENODEV; 1648e4b9852aSCasey Chen 1649e4b9852aSCasey Chen /* 1650e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1651e4b9852aSCasey Chen */ 1652e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1653e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1654e4b9852aSCasey Chen return -ENODEV; 1655e4b9852aSCasey Chen } 1656e4b9852aSCasey Chen 1657e4b9852aSCasey Chen return 0; 1658e4b9852aSCasey Chen } 1659e4b9852aSCasey Chen 16604b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 166157dacad5SJay Sternberg { 166257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 166357dacad5SJay Sternberg int result; 16647c349ddeSKeith Busch u16 vector = 0; 166557dacad5SJay Sternberg 1666d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1667d1ed6aa1SChristoph Hellwig 166822b55601SKeith Busch /* 166922b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 167022b55601SKeith Busch * has only one vector available. 167122b55601SKeith Busch */ 16724b04cc6aSJens Axboe if (!polled) 1673a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16744b04cc6aSJens Axboe else 16757c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16764b04cc6aSJens Axboe 1677a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1678ded45505SKeith Busch if (result) 1679ded45505SKeith Busch return result; 168057dacad5SJay Sternberg 168157dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 168257dacad5SJay Sternberg if (result < 0) 1683ded45505SKeith Busch return result; 1684c80b36cdSEdmund Nadolski if (result) 168557dacad5SJay Sternberg goto release_cq; 168657dacad5SJay Sternberg 1687a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16884b04cc6aSJens Axboe 1689e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1690e4b9852aSCasey Chen if (result) 1691e4b9852aSCasey Chen return result; 1692e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16937c349ddeSKeith Busch if (!polled) { 1694dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 169557dacad5SJay Sternberg if (result < 0) 169657dacad5SJay Sternberg goto release_sq; 16974b04cc6aSJens Axboe } 169857dacad5SJay Sternberg 16994e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1700e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 170157dacad5SJay Sternberg return result; 170257dacad5SJay Sternberg 170357dacad5SJay Sternberg release_sq: 1704f25a2dfcSJianchao Wang dev->online_queues--; 1705e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 170657dacad5SJay Sternberg adapter_delete_sq(dev, qid); 170757dacad5SJay Sternberg release_cq: 170857dacad5SJay Sternberg adapter_delete_cq(dev, qid); 170957dacad5SJay Sternberg return result; 171057dacad5SJay Sternberg } 171157dacad5SJay Sternberg 1712f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 171357dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 171477f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 171557dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1716e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 171757dacad5SJay Sternberg .timeout = nvme_timeout, 171857dacad5SJay Sternberg }; 171957dacad5SJay Sternberg 1720f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1721376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1722d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1723376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1724376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1725376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1726e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1727376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1728376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1729c6d962aeSChristoph Hellwig .poll = nvme_poll, 1730dabcefabSJens Axboe }; 1731dabcefabSJens Axboe 173257dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 173357dacad5SJay Sternberg { 17341c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 173569d9a99cSKeith Busch /* 173669d9a99cSKeith Busch * If the controller was reset during removal, it's possible 173769d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 173869d9a99cSKeith Busch * queue to flush these to completion. 173969d9a99cSKeith Busch */ 17406ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 17416f8191fdSChristoph Hellwig blk_mq_destroy_queue(dev->ctrl.admin_q); 174296ef1be5SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 174357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 174457dacad5SJay Sternberg } 174557dacad5SJay Sternberg } 174657dacad5SJay Sternberg 1747f91b727cSChristoph Hellwig static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 174857dacad5SJay Sternberg { 1749f91b727cSChristoph Hellwig struct blk_mq_tag_set *set = &dev->admin_tagset; 1750e3e9d50cSKeith Busch 1751f91b727cSChristoph Hellwig set->ops = &nvme_mq_admin_ops; 1752f91b727cSChristoph Hellwig set->nr_hw_queues = 1; 175357dacad5SJay Sternberg 1754f91b727cSChristoph Hellwig set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1755f91b727cSChristoph Hellwig set->timeout = NVME_ADMIN_TIMEOUT; 1756f91b727cSChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 1757f91b727cSChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 1758f91b727cSChristoph Hellwig set->flags = BLK_MQ_F_NO_SCHED; 1759f91b727cSChristoph Hellwig set->driver_data = dev; 1760f91b727cSChristoph Hellwig 1761f91b727cSChristoph Hellwig if (blk_mq_alloc_tag_set(set)) 176257dacad5SJay Sternberg return -ENOMEM; 1763f91b727cSChristoph Hellwig dev->ctrl.admin_tagset = set; 176457dacad5SJay Sternberg 1765f91b727cSChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(set); 17661c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 1767f91b727cSChristoph Hellwig blk_mq_free_tag_set(set); 1768da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 176957dacad5SJay Sternberg return -ENOMEM; 177057dacad5SJay Sternberg } 177157dacad5SJay Sternberg return 0; 177257dacad5SJay Sternberg } 177357dacad5SJay Sternberg 177497f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 177597f6ef64SXu Yu { 177697f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 177797f6ef64SXu Yu } 177897f6ef64SXu Yu 177997f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 178097f6ef64SXu Yu { 178197f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 178297f6ef64SXu Yu 178397f6ef64SXu Yu if (size <= dev->bar_mapped_size) 178497f6ef64SXu Yu return 0; 178597f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 178697f6ef64SXu Yu return -ENOMEM; 178797f6ef64SXu Yu if (dev->bar) 178897f6ef64SXu Yu iounmap(dev->bar); 178997f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 179097f6ef64SXu Yu if (!dev->bar) { 179197f6ef64SXu Yu dev->bar_mapped_size = 0; 179297f6ef64SXu Yu return -ENOMEM; 179397f6ef64SXu Yu } 179497f6ef64SXu Yu dev->bar_mapped_size = size; 179597f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 179697f6ef64SXu Yu 179797f6ef64SXu Yu return 0; 179897f6ef64SXu Yu } 179997f6ef64SXu Yu 180001ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 180157dacad5SJay Sternberg { 180257dacad5SJay Sternberg int result; 180357dacad5SJay Sternberg u32 aqa; 180457dacad5SJay Sternberg struct nvme_queue *nvmeq; 180557dacad5SJay Sternberg 180697f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 180797f6ef64SXu Yu if (result < 0) 180897f6ef64SXu Yu return result; 180997f6ef64SXu Yu 18108ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 181120d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 181257dacad5SJay Sternberg 18137a67cbeaSChristoph Hellwig if (dev->subsystem && 18147a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18157a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 181657dacad5SJay Sternberg 1817b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 181857dacad5SJay Sternberg if (result < 0) 181957dacad5SJay Sternberg return result; 182057dacad5SJay Sternberg 1821a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1822147b27e4SSagi Grimberg if (result) 1823147b27e4SSagi Grimberg return result; 182457dacad5SJay Sternberg 1825635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1826635333e4SMax Gurtovoy 1827147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 182857dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 182957dacad5SJay Sternberg aqa |= aqa << 16; 183057dacad5SJay Sternberg 18317a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18327a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18337a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 183457dacad5SJay Sternberg 1835c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 183657dacad5SJay Sternberg if (result) 1837d4875622SKeith Busch return result; 183857dacad5SJay Sternberg 183957dacad5SJay Sternberg nvmeq->cq_vector = 0; 1840161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1841dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 184257dacad5SJay Sternberg if (result) { 18437c349ddeSKeith Busch dev->online_queues--; 1844d4875622SKeith Busch return result; 184557dacad5SJay Sternberg } 184657dacad5SJay Sternberg 18474e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 184857dacad5SJay Sternberg return result; 184957dacad5SJay Sternberg } 185057dacad5SJay Sternberg 1851749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 185257dacad5SJay Sternberg { 18534b04cc6aSJens Axboe unsigned i, max, rw_queues; 1854749941f2SChristoph Hellwig int ret = 0; 185557dacad5SJay Sternberg 1856d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1857a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1858749941f2SChristoph Hellwig ret = -ENOMEM; 185957dacad5SJay Sternberg break; 1860749941f2SChristoph Hellwig } 1861749941f2SChristoph Hellwig } 186257dacad5SJay Sternberg 1863d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1864e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1865e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1866e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18674b04cc6aSJens Axboe } else { 18684b04cc6aSJens Axboe rw_queues = max; 18694b04cc6aSJens Axboe } 18704b04cc6aSJens Axboe 1871949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18724b04cc6aSJens Axboe bool polled = i > rw_queues; 18734b04cc6aSJens Axboe 18744b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1875d4875622SKeith Busch if (ret) 187657dacad5SJay Sternberg break; 187757dacad5SJay Sternberg } 187857dacad5SJay Sternberg 1879749941f2SChristoph Hellwig /* 1880749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18818adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18828adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1883749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1884749941f2SChristoph Hellwig */ 1885749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 188657dacad5SJay Sternberg } 188757dacad5SJay Sternberg 188888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 188957dacad5SJay Sternberg { 189088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 189188de4598SChristoph Hellwig 189288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 189388de4598SChristoph Hellwig } 189488de4598SChristoph Hellwig 189588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 189688de4598SChristoph Hellwig { 189788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 189888de4598SChristoph Hellwig } 189988de4598SChristoph Hellwig 1900f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 190157dacad5SJay Sternberg { 190288de4598SChristoph Hellwig u64 size, offset; 190357dacad5SJay Sternberg resource_size_t bar_size; 190457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19058969f1f8SChristoph Hellwig int bar; 190657dacad5SJay Sternberg 19079fe5c59fSKeith Busch if (dev->cmb_size) 19089fe5c59fSKeith Busch return; 19099fe5c59fSKeith Busch 191020d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 191120d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 191220d3bb92SKlaus Jensen 19137a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1914f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1915f65efd6dSChristoph Hellwig return; 1916202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 191757dacad5SJay Sternberg 191888de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 191988de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19208969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19218969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 192257dacad5SJay Sternberg 192357dacad5SJay Sternberg if (offset > bar_size) 1924f65efd6dSChristoph Hellwig return; 192557dacad5SJay Sternberg 192657dacad5SJay Sternberg /* 192720d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 192820d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 192920d3bb92SKlaus Jensen */ 193020d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 193120d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 193220d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 193320d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 193420d3bb92SKlaus Jensen } 193520d3bb92SKlaus Jensen 193620d3bb92SKlaus Jensen /* 193757dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 193857dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 193957dacad5SJay Sternberg * the reported size of the BAR 194057dacad5SJay Sternberg */ 194157dacad5SJay Sternberg if (size > bar_size - offset) 194257dacad5SJay Sternberg size = bar_size - offset; 194357dacad5SJay Sternberg 19440f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19450f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19460f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1947f65efd6dSChristoph Hellwig return; 19480f238ff5SLogan Gunthorpe } 19490f238ff5SLogan Gunthorpe 195057dacad5SJay Sternberg dev->cmb_size = size; 19510f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19520f238ff5SLogan Gunthorpe 19530f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19540f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19550f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 195657dacad5SJay Sternberg } 195757dacad5SJay Sternberg 195887ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 195957dacad5SJay Sternberg { 19606c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19614033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1962f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 196387ad72a5SChristoph Hellwig int ret; 196487ad72a5SChristoph Hellwig 196587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 196687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 196787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19686c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 196987ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 197087ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 197187ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 197287ad72a5SChristoph Hellwig 197387ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 197487ad72a5SChristoph Hellwig if (ret) { 197587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 197687ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 197787ad72a5SChristoph Hellwig ret, bits); 1978a5df5e79SKeith Busch } else 1979a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1980a5df5e79SKeith Busch 198187ad72a5SChristoph Hellwig return ret; 198287ad72a5SChristoph Hellwig } 198387ad72a5SChristoph Hellwig 198487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 198587ad72a5SChristoph Hellwig { 198687ad72a5SChristoph Hellwig int i; 198787ad72a5SChristoph Hellwig 198887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 198987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19906c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 199187ad72a5SChristoph Hellwig 1992cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1993cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1994cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 199587ad72a5SChristoph Hellwig } 199687ad72a5SChristoph Hellwig 199787ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 199887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19994033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20004033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20014033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 200287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20037e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 200487ad72a5SChristoph Hellwig } 200587ad72a5SChristoph Hellwig 200692dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 200792dc6895SChristoph Hellwig u32 chunk_size) 200887ad72a5SChristoph Hellwig { 200987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 201092dc6895SChristoph Hellwig u32 max_entries, len; 20114033f35dSChristoph Hellwig dma_addr_t descs_dma; 20122ee0e4edSDan Carpenter int i = 0; 201387ad72a5SChristoph Hellwig void **bufs; 20146fbcde66SMinwoo Im u64 size, tmp; 201587ad72a5SChristoph Hellwig 201687ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 201787ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 201887ad72a5SChristoph Hellwig max_entries = tmp; 2019044a9df1SChristoph Hellwig 2020044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2021044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2022044a9df1SChristoph Hellwig 2023750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20244033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 202587ad72a5SChristoph Hellwig if (!descs) 202687ad72a5SChristoph Hellwig goto out; 202787ad72a5SChristoph Hellwig 202887ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 202987ad72a5SChristoph Hellwig if (!bufs) 203087ad72a5SChristoph Hellwig goto out_free_descs; 203187ad72a5SChristoph Hellwig 2032244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 203387ad72a5SChristoph Hellwig dma_addr_t dma_addr; 203487ad72a5SChristoph Hellwig 203550cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 203687ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 203787ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 203887ad72a5SChristoph Hellwig if (!bufs[i]) 203987ad72a5SChristoph Hellwig break; 204087ad72a5SChristoph Hellwig 204187ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20426c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 204387ad72a5SChristoph Hellwig i++; 204487ad72a5SChristoph Hellwig } 204587ad72a5SChristoph Hellwig 204692dc6895SChristoph Hellwig if (!size) 204787ad72a5SChristoph Hellwig goto out_free_bufs; 204887ad72a5SChristoph Hellwig 204987ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 205087ad72a5SChristoph Hellwig dev->host_mem_size = size; 205187ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20524033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 205387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 205487ad72a5SChristoph Hellwig return 0; 205587ad72a5SChristoph Hellwig 205687ad72a5SChristoph Hellwig out_free_bufs: 205787ad72a5SChristoph Hellwig while (--i >= 0) { 20586c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 205987ad72a5SChristoph Hellwig 2060cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2061cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2062cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 206387ad72a5SChristoph Hellwig } 206487ad72a5SChristoph Hellwig 206587ad72a5SChristoph Hellwig kfree(bufs); 206687ad72a5SChristoph Hellwig out_free_descs: 20674033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20684033f35dSChristoph Hellwig descs_dma); 206987ad72a5SChristoph Hellwig out: 207087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 207187ad72a5SChristoph Hellwig return -ENOMEM; 207287ad72a5SChristoph Hellwig } 207387ad72a5SChristoph Hellwig 207492dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 207592dc6895SChristoph Hellwig { 20769dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20779dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20789dc54a0dSChaitanya Kulkarni u64 chunk_size; 207992dc6895SChristoph Hellwig 208092dc6895SChristoph Hellwig /* start big and work our way down */ 20819dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 208292dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 208392dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 208492dc6895SChristoph Hellwig return 0; 208592dc6895SChristoph Hellwig nvme_free_host_mem(dev); 208692dc6895SChristoph Hellwig } 208792dc6895SChristoph Hellwig } 208892dc6895SChristoph Hellwig 208992dc6895SChristoph Hellwig return -ENOMEM; 209092dc6895SChristoph Hellwig } 209192dc6895SChristoph Hellwig 20929620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 209387ad72a5SChristoph Hellwig { 209487ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 209587ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 209687ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 209787ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20986fbcde66SMinwoo Im int ret; 209987ad72a5SChristoph Hellwig 210087ad72a5SChristoph Hellwig preferred = min(preferred, max); 210187ad72a5SChristoph Hellwig if (min > max) { 210287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 210387ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 210487ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 210587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21069620cfbaSChristoph Hellwig return 0; 210787ad72a5SChristoph Hellwig } 210887ad72a5SChristoph Hellwig 210987ad72a5SChristoph Hellwig /* 211087ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 211187ad72a5SChristoph Hellwig */ 211287ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 211387ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 211487ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 211587ad72a5SChristoph Hellwig else 211687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 211787ad72a5SChristoph Hellwig } 211887ad72a5SChristoph Hellwig 211987ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 212092dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 212192dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 212292dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21239620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 212487ad72a5SChristoph Hellwig } 212587ad72a5SChristoph Hellwig 212692dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 212792dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 212892dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 212992dc6895SChristoph Hellwig } 213092dc6895SChristoph Hellwig 21319620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21329620cfbaSChristoph Hellwig if (ret) 213387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21349620cfbaSChristoph Hellwig return ret; 213557dacad5SJay Sternberg } 213657dacad5SJay Sternberg 21370521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21380521905eSKeith Busch char *buf) 21390521905eSKeith Busch { 21400521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21410521905eSKeith Busch 21420521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21430521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21440521905eSKeith Busch } 21450521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21460521905eSKeith Busch 21471751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21481751e97aSKeith Busch char *buf) 21491751e97aSKeith Busch { 21501751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21511751e97aSKeith Busch 21521751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21531751e97aSKeith Busch } 21541751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21551751e97aSKeith Busch 21561751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21571751e97aSKeith Busch char *buf) 21581751e97aSKeith Busch { 21591751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21601751e97aSKeith Busch 21611751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21621751e97aSKeith Busch } 21631751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21641751e97aSKeith Busch 2165a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2166a5df5e79SKeith Busch char *buf) 2167a5df5e79SKeith Busch { 2168a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2169a5df5e79SKeith Busch 2170a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2171a5df5e79SKeith Busch } 2172a5df5e79SKeith Busch 2173a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2174a5df5e79SKeith Busch const char *buf, size_t count) 2175a5df5e79SKeith Busch { 2176a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2177a5df5e79SKeith Busch bool new; 2178a5df5e79SKeith Busch int ret; 2179a5df5e79SKeith Busch 2180a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2181a5df5e79SKeith Busch return -EINVAL; 2182a5df5e79SKeith Busch 2183a5df5e79SKeith Busch if (new == ndev->hmb) 2184a5df5e79SKeith Busch return count; 2185a5df5e79SKeith Busch 2186a5df5e79SKeith Busch if (new) { 2187a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2188a5df5e79SKeith Busch } else { 2189a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2190a5df5e79SKeith Busch if (!ret) 2191a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2192a5df5e79SKeith Busch } 2193a5df5e79SKeith Busch 2194a5df5e79SKeith Busch if (ret < 0) 2195a5df5e79SKeith Busch return ret; 2196a5df5e79SKeith Busch 2197a5df5e79SKeith Busch return count; 2198a5df5e79SKeith Busch } 2199a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2200a5df5e79SKeith Busch 22010521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22020521905eSKeith Busch struct attribute *a, int n) 22030521905eSKeith Busch { 22040521905eSKeith Busch struct nvme_ctrl *ctrl = 22050521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22060521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22070521905eSKeith Busch 22081751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22091751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22101751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22111751e97aSKeith Busch if (!dev->cmbsz) 22120521905eSKeith Busch return 0; 22131751e97aSKeith Busch } 2214a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2215a5df5e79SKeith Busch return 0; 2216a5df5e79SKeith Busch 22170521905eSKeith Busch return a->mode; 22180521905eSKeith Busch } 22190521905eSKeith Busch 22200521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22210521905eSKeith Busch &dev_attr_cmb.attr, 22221751e97aSKeith Busch &dev_attr_cmbloc.attr, 22231751e97aSKeith Busch &dev_attr_cmbsz.attr, 2224a5df5e79SKeith Busch &dev_attr_hmb.attr, 22250521905eSKeith Busch NULL, 22260521905eSKeith Busch }; 22270521905eSKeith Busch 222886adbf0cSChristoph Hellwig static const struct attribute_group nvme_pci_dev_attrs_group = { 22290521905eSKeith Busch .attrs = nvme_pci_attrs, 22300521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22310521905eSKeith Busch }; 22320521905eSKeith Busch 223386adbf0cSChristoph Hellwig static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 223486adbf0cSChristoph Hellwig &nvme_dev_attrs_group, 223586adbf0cSChristoph Hellwig &nvme_pci_dev_attrs_group, 223686adbf0cSChristoph Hellwig NULL, 223786adbf0cSChristoph Hellwig }; 223886adbf0cSChristoph Hellwig 2239612b7286SMing Lei /* 2240612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2241612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2242612b7286SMing Lei */ 2243612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22443b6592f7SJens Axboe { 2245612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22462a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2247c45b1fa2SMing Lei 22483b6592f7SJens Axboe /* 2249ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2250612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2251612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2252612b7286SMing Lei * 2253612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2254612b7286SMing Lei * write and read queues. 2255612b7286SMing Lei * 2256612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2257612b7286SMing Lei * queue. 22583b6592f7SJens Axboe */ 2259612b7286SMing Lei if (!nrirqs) { 2260612b7286SMing Lei nrirqs = 1; 2261612b7286SMing Lei nr_read_queues = 0; 22622a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2263612b7286SMing Lei nr_read_queues = 0; 22642a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2265612b7286SMing Lei nr_read_queues = 1; 22663b6592f7SJens Axboe } else { 22672a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22683b6592f7SJens Axboe } 2269612b7286SMing Lei 2270612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2271612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2272612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2273612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2274612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22753b6592f7SJens Axboe } 22763b6592f7SJens Axboe 22776451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22783b6592f7SJens Axboe { 22793b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22803b6592f7SJens Axboe struct irq_affinity affd = { 22813b6592f7SJens Axboe .pre_vectors = 1, 2282612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2283612b7286SMing Lei .priv = dev, 22843b6592f7SJens Axboe }; 228521cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22866451fe73SJens Axboe 22876451fe73SJens Axboe /* 228821cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 228921cc2f3fSJeffle Xu * left over for non-polled I/O. 22906451fe73SJens Axboe */ 229121cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 229221cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22933b6592f7SJens Axboe 229421cc2f3fSJeffle Xu /* 229521cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 229621cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 229721cc2f3fSJeffle Xu */ 2298612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2299612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23003b6592f7SJens Axboe 230166341331SBenjamin Herrenschmidt /* 230221cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 230321cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 230421cc2f3fSJeffle Xu * vector. 230566341331SBenjamin Herrenschmidt */ 230666341331SBenjamin Herrenschmidt irq_queues = 1; 230721cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 230821cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2309612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23103b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23113b6592f7SJens Axboe } 23123b6592f7SJens Axboe 23138fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23148fae268bSKeith Busch { 23158fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23168fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23178fae268bSKeith Busch } 23188fae268bSKeith Busch 23192a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23202a5bcfddSWeiping Zhang { 2321e3aef095SNiklas Schnelle /* 2322e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2323e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2324e3aef095SNiklas Schnelle */ 2325e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2326e3aef095SNiklas Schnelle return 1; 23272a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23282a5bcfddSWeiping Zhang } 23292a5bcfddSWeiping Zhang 233057dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 233157dacad5SJay Sternberg { 2332147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 233357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23342a5bcfddSWeiping Zhang unsigned int nr_io_queues; 233597f6ef64SXu Yu unsigned long size; 23362a5bcfddSWeiping Zhang int result; 233757dacad5SJay Sternberg 23382a5bcfddSWeiping Zhang /* 23392a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23402a5bcfddSWeiping Zhang * stable values to work with. 23412a5bcfddSWeiping Zhang */ 23422a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23432a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2344d38e9f04SBenjamin Herrenschmidt 2345ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23469a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23479a0be7abSChristoph Hellwig if (result < 0) 234857dacad5SJay Sternberg return result; 23499a0be7abSChristoph Hellwig 2350f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2351a5229050SKeith Busch return 0; 235257dacad5SJay Sternberg 2353e4b9852aSCasey Chen /* 2354e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2355e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2356e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2357e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2358e4b9852aSCasey Chen * nvme_dev_disable() path. 2359e4b9852aSCasey Chen */ 2360e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2361e4b9852aSCasey Chen if (result) 2362e4b9852aSCasey Chen return result; 2363e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2364e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23654e224106SChristoph Hellwig 23660f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 236757dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 236857dacad5SJay Sternberg sizeof(struct nvme_command)); 236957dacad5SJay Sternberg if (result > 0) 237057dacad5SJay Sternberg dev->q_depth = result; 237157dacad5SJay Sternberg else 23720f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 237357dacad5SJay Sternberg } 237457dacad5SJay Sternberg 237557dacad5SJay Sternberg do { 237697f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 237797f6ef64SXu Yu result = nvme_remap_bar(dev, size); 237897f6ef64SXu Yu if (!result) 237957dacad5SJay Sternberg break; 2380e4b9852aSCasey Chen if (!--nr_io_queues) { 2381e4b9852aSCasey Chen result = -ENOMEM; 2382e4b9852aSCasey Chen goto out_unlock; 2383e4b9852aSCasey Chen } 238457dacad5SJay Sternberg } while (1); 238557dacad5SJay Sternberg adminq->q_db = dev->dbs; 238657dacad5SJay Sternberg 23878fae268bSKeith Busch retry: 238857dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2389e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23900ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 239157dacad5SJay Sternberg 239257dacad5SJay Sternberg /* 239357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 239457dacad5SJay Sternberg * setting up the full range we need. 239557dacad5SJay Sternberg */ 2396dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 23973b6592f7SJens Axboe 23983b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2399e4b9852aSCasey Chen if (result <= 0) { 2400e4b9852aSCasey Chen result = -EIO; 2401e4b9852aSCasey Chen goto out_unlock; 2402e4b9852aSCasey Chen } 24033b6592f7SJens Axboe 240422b55601SKeith Busch dev->num_vecs = result; 24054b04cc6aSJens Axboe result = max(result - 1, 1); 2406e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 240757dacad5SJay Sternberg 240857dacad5SJay Sternberg /* 240957dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 241057dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 241157dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 241257dacad5SJay Sternberg * number of interrupts. 241357dacad5SJay Sternberg */ 2414dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24157c349ddeSKeith Busch if (result) 2416e4b9852aSCasey Chen goto out_unlock; 24174e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2418e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24198fae268bSKeith Busch 24208fae268bSKeith Busch result = nvme_create_io_queues(dev); 24218fae268bSKeith Busch if (result || dev->online_queues < 2) 24228fae268bSKeith Busch return result; 24238fae268bSKeith Busch 24248fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24258fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24268fae268bSKeith Busch nvme_disable_io_queues(dev); 2427e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2428e4b9852aSCasey Chen if (result) 2429e4b9852aSCasey Chen return result; 24308fae268bSKeith Busch nvme_suspend_io_queues(dev); 24318fae268bSKeith Busch goto retry; 24328fae268bSKeith Busch } 24338fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24348fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24358fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24368fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24378fae268bSKeith Busch return 0; 2438e4b9852aSCasey Chen out_unlock: 2439e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2440e4b9852aSCasey Chen return result; 244157dacad5SJay Sternberg } 244257dacad5SJay Sternberg 2443de671d61SJens Axboe static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2444de671d61SJens Axboe blk_status_t error) 2445db3cbfffSKeith Busch { 2446db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2447db3cbfffSKeith Busch 2448db3cbfffSKeith Busch blk_mq_free_request(req); 2449d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2450de671d61SJens Axboe return RQ_END_IO_NONE; 2451db3cbfffSKeith Busch } 2452db3cbfffSKeith Busch 2453de671d61SJens Axboe static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2454de671d61SJens Axboe blk_status_t error) 2455db3cbfffSKeith Busch { 2456db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2457db3cbfffSKeith Busch 2458d1ed6aa1SChristoph Hellwig if (error) 2459d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2460db3cbfffSKeith Busch 2461de671d61SJens Axboe return nvme_del_queue_end(req, error); 2462db3cbfffSKeith Busch } 2463db3cbfffSKeith Busch 2464db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2465db3cbfffSKeith Busch { 2466db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2467db3cbfffSKeith Busch struct request *req; 2468f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2469db3cbfffSKeith Busch 2470db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2471db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2472db3cbfffSKeith Busch 2473e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2474db3cbfffSKeith Busch if (IS_ERR(req)) 2475db3cbfffSKeith Busch return PTR_ERR(req); 2476e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2477db3cbfffSKeith Busch 2478e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2479e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2480e2e53086SChristoph Hellwig else 2481e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2482db3cbfffSKeith Busch req->end_io_data = nvmeq; 2483db3cbfffSKeith Busch 2484d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2485128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2486e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2487db3cbfffSKeith Busch return 0; 2488db3cbfffSKeith Busch } 2489db3cbfffSKeith Busch 24908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2491db3cbfffSKeith Busch { 24925271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2493db3cbfffSKeith Busch unsigned long timeout; 2494db3cbfffSKeith Busch 2495db3cbfffSKeith Busch retry: 2496dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24975271edd4SChristoph Hellwig while (nr_queues > 0) { 24985271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2499db3cbfffSKeith Busch break; 25005271edd4SChristoph Hellwig nr_queues--; 25015271edd4SChristoph Hellwig sent++; 25025271edd4SChristoph Hellwig } 2503d1ed6aa1SChristoph Hellwig while (sent) { 2504d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2505d1ed6aa1SChristoph Hellwig 2506d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25075271edd4SChristoph Hellwig timeout); 2508db3cbfffSKeith Busch if (timeout == 0) 25095271edd4SChristoph Hellwig return false; 2510d1ed6aa1SChristoph Hellwig 2511d1ed6aa1SChristoph Hellwig sent--; 25125271edd4SChristoph Hellwig if (nr_queues) 2513db3cbfffSKeith Busch goto retry; 2514db3cbfffSKeith Busch } 25155271edd4SChristoph Hellwig return true; 2516db3cbfffSKeith Busch } 2517db3cbfffSKeith Busch 25182455a4b7SChristoph Hellwig static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 251957dacad5SJay Sternberg { 25202455a4b7SChristoph Hellwig struct blk_mq_tag_set * set = &dev->tagset; 25212b1b7e78SJianchao Wang int ret; 25222b1b7e78SJianchao Wang 25232455a4b7SChristoph Hellwig set->ops = &nvme_mq_ops; 25242455a4b7SChristoph Hellwig set->nr_hw_queues = dev->online_queues - 1; 25256ee742faSKeith Busch set->nr_maps = 1; 25266ee742faSKeith Busch if (dev->io_queues[HCTX_TYPE_READ]) 25276ee742faSKeith Busch set->nr_maps = 2; 2528ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 25296ee742faSKeith Busch set->nr_maps = 3; 25302455a4b7SChristoph Hellwig set->timeout = NVME_IO_TIMEOUT; 25312455a4b7SChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 25322455a4b7SChristoph Hellwig set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 25332455a4b7SChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 25342455a4b7SChristoph Hellwig set->flags = BLK_MQ_F_SHOULD_MERGE; 25352455a4b7SChristoph Hellwig set->driver_data = dev; 253657dacad5SJay Sternberg 2537d38e9f04SBenjamin Herrenschmidt /* 2538d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2539d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2540d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2541d38e9f04SBenjamin Herrenschmidt */ 2542d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 25432455a4b7SChristoph Hellwig set->reserved_tags = NVME_AQ_DEPTH; 2544d38e9f04SBenjamin Herrenschmidt 25452455a4b7SChristoph Hellwig ret = blk_mq_alloc_tag_set(set); 25462b1b7e78SJianchao Wang if (ret) { 25472b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25482b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25495d02a5c1SKeith Busch return; 25502b1b7e78SJianchao Wang } 25512455a4b7SChristoph Hellwig dev->ctrl.tagset = set; 255257dacad5SJay Sternberg } 2553949928c1SKeith Busch 25542455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 25552455a4b7SChristoph Hellwig { 25562455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 25572455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 25582455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 255957dacad5SJay Sternberg } 256057dacad5SJay Sternberg 2561b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 256257dacad5SJay Sternberg { 2563b00a726aSKeith Busch int result = -ENOMEM; 256457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25654bdf2603SFilippo Sironi int dma_address_bits = 64; 256657dacad5SJay Sternberg 256757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 256857dacad5SJay Sternberg return result; 256957dacad5SJay Sternberg 257057dacad5SJay Sternberg pci_set_master(pdev); 257157dacad5SJay Sternberg 25724bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25734bdf2603SFilippo Sironi dma_address_bits = 48; 25744bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 257557dacad5SJay Sternberg goto disable; 257657dacad5SJay Sternberg 25777a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 257857dacad5SJay Sternberg result = -ENODEV; 2579b00a726aSKeith Busch goto disable; 258057dacad5SJay Sternberg } 258157dacad5SJay Sternberg 258257dacad5SJay Sternberg /* 2583a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2584a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2585a5229050SKeith Busch * adjust this later. 258657dacad5SJay Sternberg */ 2587dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2588dca51e78SChristoph Hellwig if (result < 0) 2589dca51e78SChristoph Hellwig return result; 259057dacad5SJay Sternberg 259120d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25927a67cbeaSChristoph Hellwig 25937442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2594b27c1e68Sweiping zhang io_queue_depth); 2595aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 259620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 25977a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 25981f390c1fSStephan Günther 25991f390c1fSStephan Günther /* 260066341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260166341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 260266341331SBenjamin Herrenschmidt * so we don't bother updating it here. 260366341331SBenjamin Herrenschmidt */ 260466341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 260566341331SBenjamin Herrenschmidt dev->io_sqes = 7; 260666341331SBenjamin Herrenschmidt else 2607c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26081f390c1fSStephan Günther 26091f390c1fSStephan Günther /* 26101f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26111f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26121f390c1fSStephan Günther */ 26131f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26141f390c1fSStephan Günther dev->q_depth = 2; 26159bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26169bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26171f390c1fSStephan Günther dev->q_depth); 2618d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2619d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2621d554b5e1SMartin K. Petersen dev->q_depth = 64; 2622d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2623d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26241f390c1fSStephan Günther } 26251f390c1fSStephan Günther 2626d38e9f04SBenjamin Herrenschmidt /* 2627d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2628d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2629d38e9f04SBenjamin Herrenschmidt */ 2630d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2631d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2632d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2633d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2634d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2635d38e9f04SBenjamin Herrenschmidt } 2636d38e9f04SBenjamin Herrenschmidt 2637d38e9f04SBenjamin Herrenschmidt 2638f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2639202021c1SStephen Bates 2640a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2641a0a3408eSKeith Busch pci_save_state(pdev); 2642*a6ee7f19SChristoph Hellwig 2643*a6ee7f19SChristoph Hellwig return nvme_pci_configure_admin_queue(dev); 264457dacad5SJay Sternberg 264557dacad5SJay Sternberg disable: 264657dacad5SJay Sternberg pci_disable_device(pdev); 264757dacad5SJay Sternberg return result; 264857dacad5SJay Sternberg } 264957dacad5SJay Sternberg 265057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265157dacad5SJay Sternberg { 2652b00a726aSKeith Busch if (dev->bar) 2653b00a726aSKeith Busch iounmap(dev->bar); 2654a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2655b00a726aSKeith Busch } 2656b00a726aSKeith Busch 2657b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2658b00a726aSKeith Busch { 265957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266057dacad5SJay Sternberg 2661dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 266257dacad5SJay Sternberg 2663a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2664a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 266557dacad5SJay Sternberg pci_disable_device(pdev); 266657dacad5SJay Sternberg } 2667a0a3408eSKeith Busch } 266857dacad5SJay Sternberg 2669a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 267057dacad5SJay Sternberg { 2671e43269e6SKeith Busch bool dead = true, freeze = false; 2672302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 267357dacad5SJay Sternberg 267477bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2675081f5e75SKeith Busch if (pci_is_enabled(pdev)) { 2676081f5e75SKeith Busch u32 csts; 2677081f5e75SKeith Busch 2678081f5e75SKeith Busch if (pci_device_is_present(pdev)) 2679081f5e75SKeith Busch csts = readl(dev->bar + NVME_REG_CSTS); 2680081f5e75SKeith Busch else 2681081f5e75SKeith Busch csts = ~0; 2682302ad8ccSKeith Busch 2683ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2684e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2685e43269e6SKeith Busch freeze = true; 2686302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2687e43269e6SKeith Busch } 2688302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2689302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 269057dacad5SJay Sternberg } 2691c21377f8SGabriel Krisman Bertazi 2692302ad8ccSKeith Busch /* 2693302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2694302ad8ccSKeith Busch * doing a safe shutdown. 2695302ad8ccSKeith Busch */ 2696e43269e6SKeith Busch if (!dead && shutdown && freeze) 2697302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 269887ad72a5SChristoph Hellwig 26999a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 27009a915a5bSJianchao Wang 270164ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 27028fae268bSKeith Busch nvme_disable_io_queues(dev); 2703a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 270457dacad5SJay Sternberg } 27058fae268bSKeith Busch nvme_suspend_io_queues(dev); 27068fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2707b00a726aSKeith Busch nvme_pci_disable(dev); 2708fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 270957dacad5SJay Sternberg 27101fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 27111fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2712302ad8ccSKeith Busch 2713302ad8ccSKeith Busch /* 2714302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2715302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2716302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2717302ad8ccSKeith Busch */ 2718c8e9e9b7SKeith Busch if (shutdown) { 2719302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2720c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27216ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 2722c8e9e9b7SKeith Busch } 272377bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 272457dacad5SJay Sternberg } 272557dacad5SJay Sternberg 2726c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2727c1ac9a4bSKeith Busch { 2728c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2729c1ac9a4bSKeith Busch return -EBUSY; 2730c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2731c1ac9a4bSKeith Busch return 0; 2732c1ac9a4bSKeith Busch } 2733c1ac9a4bSKeith Busch 273457dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 273557dacad5SJay Sternberg { 273657dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2737c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2738c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 273957dacad5SJay Sternberg if (!dev->prp_page_pool) 274057dacad5SJay Sternberg return -ENOMEM; 274157dacad5SJay Sternberg 274257dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 274357dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 274457dacad5SJay Sternberg 256, 256, 0); 274557dacad5SJay Sternberg if (!dev->prp_small_pool) { 274657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 274757dacad5SJay Sternberg return -ENOMEM; 274857dacad5SJay Sternberg } 274957dacad5SJay Sternberg return 0; 275057dacad5SJay Sternberg } 275157dacad5SJay Sternberg 275257dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 275357dacad5SJay Sternberg { 275457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275557dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 275657dacad5SJay Sternberg } 275757dacad5SJay Sternberg 2758081a7d95SChristoph Hellwig static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2759081a7d95SChristoph Hellwig { 2760081a7d95SChristoph Hellwig size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 2761081a7d95SChristoph Hellwig size_t alloc_size = sizeof(__le64 *) * npages + 2762081a7d95SChristoph Hellwig sizeof(struct scatterlist) * NVME_MAX_SEGS; 2763081a7d95SChristoph Hellwig 2764081a7d95SChristoph Hellwig WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2765081a7d95SChristoph Hellwig dev->iod_mempool = mempool_create_node(1, 2766081a7d95SChristoph Hellwig mempool_kmalloc, mempool_kfree, 2767081a7d95SChristoph Hellwig (void *)alloc_size, GFP_KERNEL, 2768081a7d95SChristoph Hellwig dev_to_node(dev->dev)); 2769081a7d95SChristoph Hellwig if (!dev->iod_mempool) 2770081a7d95SChristoph Hellwig return -ENOMEM; 2771081a7d95SChristoph Hellwig return 0; 2772081a7d95SChristoph Hellwig } 2773081a7d95SChristoph Hellwig 2774770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2775770597ecSKeith Busch { 2776770597ecSKeith Busch if (dev->tagset.tags) 2777770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2778770597ecSKeith Busch dev->ctrl.tagset = NULL; 2779770597ecSKeith Busch } 2780770597ecSKeith Busch 27812e87570bSChristoph Hellwig /* pairs with nvme_pci_alloc_dev */ 27821673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 278357dacad5SJay Sternberg { 27841673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 278557dacad5SJay Sternberg 2786770597ecSKeith Busch nvme_free_tagset(dev); 2787253fd4acSIsrael Rukshin put_device(dev->dev); 2788253fd4acSIsrael Rukshin kfree(dev->queues); 278957dacad5SJay Sternberg kfree(dev); 279057dacad5SJay Sternberg } 279157dacad5SJay Sternberg 27927c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2793f58944e2SKeith Busch { 2794c1ac9a4bSKeith Busch /* 2795c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2796c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2797c1ac9a4bSKeith Busch */ 2798c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2799d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 280069d9a99cSKeith Busch nvme_dev_disable(dev, false); 2801cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 280203e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2803f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2804f58944e2SKeith Busch } 2805f58944e2SKeith Busch 2806fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 280757dacad5SJay Sternberg { 2808d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2809d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2810a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2811e71afda4SChaitanya Kulkarni int result; 281257dacad5SJay Sternberg 28137764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 28147764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 28157764656bSZhihao Cheng dev->ctrl.state); 2816e71afda4SChaitanya Kulkarni result = -ENODEV; 2817fd634f41SChristoph Hellwig goto out; 2818e71afda4SChaitanya Kulkarni } 2819fd634f41SChristoph Hellwig 2820fd634f41SChristoph Hellwig /* 2821fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2822fd634f41SChristoph Hellwig * moving on. 2823fd634f41SChristoph Hellwig */ 2824b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2825a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2826d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2827fd634f41SChristoph Hellwig 28285c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2829b00a726aSKeith Busch result = nvme_pci_enable(dev); 283057dacad5SJay Sternberg if (result) 28314726bcf3SKeith Busch goto out_unlock; 283257dacad5SJay Sternberg 2833f91b727cSChristoph Hellwig if (!dev->ctrl.admin_q) { 2834f91b727cSChristoph Hellwig result = nvme_pci_alloc_admin_tag_set(dev); 283557dacad5SJay Sternberg if (result) 28364726bcf3SKeith Busch goto out_unlock; 2837f91b727cSChristoph Hellwig } else { 2838f91b727cSChristoph Hellwig nvme_start_admin_queue(&dev->ctrl); 2839f91b727cSChristoph Hellwig } 284057dacad5SJay Sternberg 28415c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28425c959d73SKeith Busch 28435c959d73SKeith Busch /* 28445c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28455c959d73SKeith Busch * initializing procedure here. 28465c959d73SKeith Busch */ 28475c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28485c959d73SKeith Busch dev_warn(dev->ctrl.device, 28495c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2850cee6c269SMinwoo Im result = -EBUSY; 28515c959d73SKeith Busch goto out; 28525c959d73SKeith Busch } 2853943e942eSJens Axboe 285494cc781fSChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2855ce4541f4SChristoph Hellwig if (result) 2856f58944e2SKeith Busch goto out; 2857ce4541f4SChristoph Hellwig 2858f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2859f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2860f9f38e33SHelen Koike if (result) 2861f9f38e33SHelen Koike dev_warn(dev->dev, 2862f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2863f9f38e33SHelen Koike } 2864f9f38e33SHelen Koike 28659620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 28669620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28679620cfbaSChristoph Hellwig if (result < 0) 28689620cfbaSChristoph Hellwig goto out; 28699620cfbaSChristoph Hellwig } 287087ad72a5SChristoph Hellwig 287157dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 287257dacad5SJay Sternberg if (result) 2873f58944e2SKeith Busch goto out; 287457dacad5SJay Sternberg 28750ffc7e98SChristoph Hellwig if (dev->ctrl.tagset) { 287621f033f7SKeith Busch /* 28770ffc7e98SChristoph Hellwig * This is a controller reset and we already have a tagset. 28780ffc7e98SChristoph Hellwig * Freeze and update the number of I/O queues as thos might have 28790ffc7e98SChristoph Hellwig * changed. If there are no I/O queues left after this reset, 28800ffc7e98SChristoph Hellwig * keep the controller around but remove all namespaces. 288157dacad5SJay Sternberg */ 28820ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 288325646264SKeith Busch nvme_start_queues(&dev->ctrl); 2884302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 28852455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 28862455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2887302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 28880ffc7e98SChristoph Hellwig } else { 28890ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues lost\n"); 2890cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 2891cd50f9b2SChristoph Hellwig nvme_start_queues(&dev->ctrl); 28920ffc7e98SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 28930ffc7e98SChristoph Hellwig nvme_free_tagset(dev); 28940ffc7e98SChristoph Hellwig } 28950ffc7e98SChristoph Hellwig } else { 28960ffc7e98SChristoph Hellwig /* 28970ffc7e98SChristoph Hellwig * First probe. Still allow the controller to show up even if 28980ffc7e98SChristoph Hellwig * there are no namespaces. 28990ffc7e98SChristoph Hellwig */ 29000ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 29010ffc7e98SChristoph Hellwig nvme_pci_alloc_tag_set(dev); 29020ffc7e98SChristoph Hellwig nvme_dbbuf_set(dev); 29030ffc7e98SChristoph Hellwig } else { 29040ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues not created\n"); 29050ffc7e98SChristoph Hellwig } 290657dacad5SJay Sternberg } 290757dacad5SJay Sternberg 29082b1b7e78SJianchao Wang /* 29092b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 29102b1b7e78SJianchao Wang * recovery. 29112b1b7e78SJianchao Wang */ 29125d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 29132b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 29145d02a5c1SKeith Busch "failed to mark controller live state\n"); 2915e71afda4SChaitanya Kulkarni result = -ENODEV; 2916bb8d261eSChristoph Hellwig goto out; 2917bb8d261eSChristoph Hellwig } 291892911a55SChristoph Hellwig 2919d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 292057dacad5SJay Sternberg return; 292157dacad5SJay Sternberg 29224726bcf3SKeith Busch out_unlock: 29234726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 292457dacad5SJay Sternberg out: 29257c1ce408SChaitanya Kulkarni if (result) 29267c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 29277c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 29287c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 292957dacad5SJay Sternberg } 293057dacad5SJay Sternberg 29315c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 293257dacad5SJay Sternberg { 29335c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 293457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 293557dacad5SJay Sternberg 293657dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2937921920abSKeith Busch device_release_driver(&pdev->dev); 29381673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 293957dacad5SJay Sternberg } 294057dacad5SJay Sternberg 29411c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 294257dacad5SJay Sternberg { 29431c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29441c63dc66SChristoph Hellwig return 0; 294557dacad5SJay Sternberg } 29461c63dc66SChristoph Hellwig 29475fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29485fd4ce1bSChristoph Hellwig { 29495fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29505fd4ce1bSChristoph Hellwig return 0; 29515fd4ce1bSChristoph Hellwig } 29525fd4ce1bSChristoph Hellwig 29537fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29547fd8930fSChristoph Hellwig { 29553a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29567fd8930fSChristoph Hellwig return 0; 29577fd8930fSChristoph Hellwig } 29587fd8930fSChristoph Hellwig 295997c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 296097c12223SKeith Busch { 296197c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 296297c12223SKeith Busch 29632db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 296497c12223SKeith Busch } 296597c12223SKeith Busch 29662f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 29672f0dad17SKeith Busch { 29682f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 29692f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 29702f0dad17SKeith Busch 29712f0dad17SKeith Busch dev_err(ctrl->device, 29722f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 29732f0dad17SKeith Busch pdev->vendor, pdev->device, 29742f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 29752f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 29762f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 29772f0dad17SKeith Busch subsys->firmware_rev); 29782f0dad17SKeith Busch } 29792f0dad17SKeith Busch 29802f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 29812f859441SLogan Gunthorpe { 29822f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 29832f859441SLogan Gunthorpe 29842f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 29852f859441SLogan Gunthorpe } 29862f859441SLogan Gunthorpe 29871c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29881a353d85SMing Lin .name = "pcie", 2989e439bb12SSagi Grimberg .module = THIS_MODULE, 29902f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 299186adbf0cSChristoph Hellwig .dev_attr_groups = nvme_pci_dev_attr_groups, 29921c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29935fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29947fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29951673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2996f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 299797c12223SKeith Busch .get_address = nvme_pci_get_address, 29982f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 29992f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 30001c63dc66SChristoph Hellwig }; 300157dacad5SJay Sternberg 3002b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 3003b00a726aSKeith Busch { 3004b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 3005b00a726aSKeith Busch 3006a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 3007b00a726aSKeith Busch return -ENODEV; 3008b00a726aSKeith Busch 300997f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 3010b00a726aSKeith Busch goto release; 3011b00a726aSKeith Busch 3012b00a726aSKeith Busch return 0; 3013b00a726aSKeith Busch release: 3014a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 3015b00a726aSKeith Busch return -ENODEV; 3016b00a726aSKeith Busch } 3017b00a726aSKeith Busch 30188427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 3019ff5350a8SAndy Lutomirski { 3020ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3021ff5350a8SAndy Lutomirski /* 3022ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 3023ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 3024ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3025ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3026ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 3027ff5350a8SAndy Lutomirski * laptops. 3028ff5350a8SAndy Lutomirski */ 3029ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3030ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3031ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3032ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 30338427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 30348427bbc2SKai-Heng Feng /* 30358427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 3036467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3037467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 3038467c77d4SJarosław Janik * ASUS PRIME Z370-A 30398427bbc2SKai-Heng Feng */ 30408427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3041467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3042467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30438427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30441fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30451fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30461fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30471fae37acSShyjumon N /* 30481fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30491fae37acSShyjumon N * lowest idle power with quick resume latency on 30501fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30511fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30521fae37acSShyjumon N */ 30531fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30541fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30551fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3056ff5350a8SAndy Lutomirski } 3057ff5350a8SAndy Lutomirski 3058ff5350a8SAndy Lutomirski return 0; 3059ff5350a8SAndy Lutomirski } 3060ff5350a8SAndy Lutomirski 306118119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 306218119775SKeith Busch { 306318119775SKeith Busch struct nvme_dev *dev = data; 306480f513b5SKeith Busch 3065bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 306618119775SKeith Busch flush_work(&dev->ctrl.scan_work); 306780f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 306818119775SKeith Busch } 306918119775SKeith Busch 30702e87570bSChristoph Hellwig static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 30712e87570bSChristoph Hellwig const struct pci_device_id *id) 307257dacad5SJay Sternberg { 3073ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 30742e87570bSChristoph Hellwig int node = dev_to_node(&pdev->dev); 30752e87570bSChristoph Hellwig struct nvme_dev *dev; 30762e87570bSChristoph Hellwig int ret = -ENOMEM; 307757dacad5SJay Sternberg 307857dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30792fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 308057dacad5SJay Sternberg 308157dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 308257dacad5SJay Sternberg if (!dev) 30832e87570bSChristoph Hellwig return NULL; 30842e87570bSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30852e87570bSChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 30862e87570bSChristoph Hellwig mutex_init(&dev->shutdown_lock); 3087147b27e4SSagi Grimberg 30882a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30892a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 30902a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 30912a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30922a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 309357dacad5SJay Sternberg if (!dev->queues) 30942e87570bSChristoph Hellwig goto out_free_dev; 309557dacad5SJay Sternberg 309657dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 3097f3ca80fcSChristoph Hellwig 30988427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 30992744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3100df4f9bc4SDavid E. Box /* 3101df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3102df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3103df4f9bc4SDavid E. Box */ 3104df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3105df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3106df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3107df4f9bc4SDavid E. Box } 31082e87570bSChristoph Hellwig ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 31092e87570bSChristoph Hellwig quirks); 31102e87570bSChristoph Hellwig if (ret) 31112e87570bSChristoph Hellwig goto out_put_device; 31123f30a79cSChristoph Hellwig 31133f30a79cSChristoph Hellwig dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 31143f30a79cSChristoph Hellwig dma_set_max_seg_size(&pdev->dev, 0xffffffff); 31153f30a79cSChristoph Hellwig 31163f30a79cSChristoph Hellwig /* 31173f30a79cSChristoph Hellwig * Limit the max command size to prevent iod->sg allocations going 31183f30a79cSChristoph Hellwig * over a single page. 31193f30a79cSChristoph Hellwig */ 31203f30a79cSChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 31213f30a79cSChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 31223f30a79cSChristoph Hellwig dev->ctrl.max_segments = NVME_MAX_SEGS; 31233f30a79cSChristoph Hellwig 31243f30a79cSChristoph Hellwig /* 31253f30a79cSChristoph Hellwig * There is no support for SGLs for metadata (yet), so we are limited to 31263f30a79cSChristoph Hellwig * a single integrity segment for the separate metadata pointer. 31273f30a79cSChristoph Hellwig */ 31283f30a79cSChristoph Hellwig dev->ctrl.max_integrity_segments = 1; 31292e87570bSChristoph Hellwig return dev; 31302e87570bSChristoph Hellwig 31312e87570bSChristoph Hellwig out_put_device: 31322e87570bSChristoph Hellwig put_device(dev->dev); 31332e87570bSChristoph Hellwig kfree(dev->queues); 31342e87570bSChristoph Hellwig out_free_dev: 31352e87570bSChristoph Hellwig kfree(dev); 31362e87570bSChristoph Hellwig return ERR_PTR(ret); 31372e87570bSChristoph Hellwig } 31382e87570bSChristoph Hellwig 31392e87570bSChristoph Hellwig static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 31402e87570bSChristoph Hellwig { 31412e87570bSChristoph Hellwig struct nvme_dev *dev; 31422e87570bSChristoph Hellwig int result = -ENOMEM; 31432e87570bSChristoph Hellwig 31442e87570bSChristoph Hellwig dev = nvme_pci_alloc_dev(pdev, id); 31452e87570bSChristoph Hellwig if (!dev) 31462e87570bSChristoph Hellwig return -ENOMEM; 31472e87570bSChristoph Hellwig 31482e87570bSChristoph Hellwig result = nvme_dev_map(dev); 31492e87570bSChristoph Hellwig if (result) 31502e87570bSChristoph Hellwig goto out_uninit_ctrl; 31512e87570bSChristoph Hellwig 31522e87570bSChristoph Hellwig result = nvme_setup_prp_pools(dev); 31532e87570bSChristoph Hellwig if (result) 31542e87570bSChristoph Hellwig goto out_dev_unmap; 3155df4f9bc4SDavid E. Box 3156081a7d95SChristoph Hellwig result = nvme_pci_alloc_iod_mempool(dev); 3157081a7d95SChristoph Hellwig if (result) 31582e87570bSChristoph Hellwig goto out_release_prp_pools; 3159b6e44b4cSKeith Busch 31601b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 31612e87570bSChristoph Hellwig pci_set_drvdata(pdev, dev); 31621b3c47c1SSagi Grimberg 3163bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 316418119775SKeith Busch async_schedule(nvme_async_probe, dev); 316557dacad5SJay Sternberg return 0; 316657dacad5SJay Sternberg 31672e87570bSChristoph Hellwig out_release_prp_pools: 316857dacad5SJay Sternberg nvme_release_prp_pools(dev); 31692e87570bSChristoph Hellwig out_dev_unmap: 3170b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 31712e87570bSChristoph Hellwig out_uninit_ctrl: 31722e87570bSChristoph Hellwig nvme_uninit_ctrl(&dev->ctrl); 317357dacad5SJay Sternberg return result; 317457dacad5SJay Sternberg } 317557dacad5SJay Sternberg 3176775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 317757dacad5SJay Sternberg { 317857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3179c1ac9a4bSKeith Busch 3180c1ac9a4bSKeith Busch /* 3181c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3182c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3183c1ac9a4bSKeith Busch * with ->remove(). 3184c1ac9a4bSKeith Busch */ 3185c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3186c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3187775755edSChristoph Hellwig } 318857dacad5SJay Sternberg 3189775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3190775755edSChristoph Hellwig { 3191f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3192c1ac9a4bSKeith Busch 3193c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3194c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 319557dacad5SJay Sternberg } 319657dacad5SJay Sternberg 319757dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 319857dacad5SJay Sternberg { 319957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 32004e523547SBaolin Wang 3201c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 320257dacad5SJay Sternberg } 320357dacad5SJay Sternberg 3204f58944e2SKeith Busch /* 3205f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3206f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3207f58944e2SKeith Busch * order to proceed. 3208f58944e2SKeith Busch */ 320957dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 321057dacad5SJay Sternberg { 321157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 321257dacad5SJay Sternberg 3213bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 321457dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 32150ff9d4e1SKeith Busch 32166db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 32170ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 32181d39e692SKeith Busch nvme_dev_disable(dev, true); 32196db28edaSKeith Busch } 32200ff9d4e1SKeith Busch 3221d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3222d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3223d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3224a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 322587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 322657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 3227c11b7716SChristoph Hellwig nvme_dbbuf_dma_free(dev); 322857dacad5SJay Sternberg nvme_free_queues(dev, 0); 3229c11b7716SChristoph Hellwig mempool_destroy(dev->iod_mempool); 323057dacad5SJay Sternberg nvme_release_prp_pools(dev); 3231b00a726aSKeith Busch nvme_dev_unmap(dev); 3232726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 323357dacad5SJay Sternberg } 323457dacad5SJay Sternberg 323557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3236d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3237d916b1beSKeith Busch { 3238d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3239d916b1beSKeith Busch } 3240d916b1beSKeith Busch 3241d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3242d916b1beSKeith Busch { 3243d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3244d916b1beSKeith Busch } 3245d916b1beSKeith Busch 3246d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3247d916b1beSKeith Busch { 3248d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3249d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3250d916b1beSKeith Busch 32514eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3252d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3253e5ad96f3SKeith Busch goto reset; 3254e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3255e5ad96f3SKeith Busch goto reset; 3256e5ad96f3SKeith Busch 3257d916b1beSKeith Busch return 0; 3258e5ad96f3SKeith Busch reset: 3259e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3260d916b1beSKeith Busch } 3261d916b1beSKeith Busch 326257dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 326357dacad5SJay Sternberg { 326457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 326557dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3266d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3267d916b1beSKeith Busch int ret = -EBUSY; 3268d916b1beSKeith Busch 32694eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32704eaefe8cSRafael J. Wysocki 3271d916b1beSKeith Busch /* 3272d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3273d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3274d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3275d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3276d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3277d916b1beSKeith Busch * device fully. 32784eaefe8cSRafael J. Wysocki * 32794eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32804eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32814eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32824eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3283d916b1beSKeith Busch */ 32844eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3285cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3286c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3287c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3288d916b1beSKeith Busch 3289d916b1beSKeith Busch nvme_start_freeze(ctrl); 3290d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3291d916b1beSKeith Busch nvme_sync_queues(ctrl); 3292d916b1beSKeith Busch 32935d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3294d916b1beSKeith Busch goto unfreeze; 3295d916b1beSKeith Busch 3296e5ad96f3SKeith Busch /* 3297e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3298e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3299e5ad96f3SKeith Busch * non-operational power state. 3300e5ad96f3SKeith Busch */ 3301e5ad96f3SKeith Busch if (ndev->hmb) { 3302e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3303e5ad96f3SKeith Busch if (ret < 0) 3304e5ad96f3SKeith Busch goto unfreeze; 3305e5ad96f3SKeith Busch } 3306e5ad96f3SKeith Busch 3307d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3308d916b1beSKeith Busch if (ret < 0) 3309d916b1beSKeith Busch goto unfreeze; 3310d916b1beSKeith Busch 33117cbb5c6fSMario Limonciello /* 33127cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 33137cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 33147cbb5c6fSMario Limonciello * want pci interfering. 33157cbb5c6fSMario Limonciello */ 33167cbb5c6fSMario Limonciello pci_save_state(pdev); 33177cbb5c6fSMario Limonciello 3318d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3319d916b1beSKeith Busch if (ret < 0) 3320d916b1beSKeith Busch goto unfreeze; 3321d916b1beSKeith Busch 3322d916b1beSKeith Busch if (ret) { 33237cbb5c6fSMario Limonciello /* discard the saved state */ 33247cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33257cbb5c6fSMario Limonciello 3326d916b1beSKeith Busch /* 3327d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 332805d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3329d916b1beSKeith Busch */ 3330c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3331d916b1beSKeith Busch ctrl->npss = 0; 3332d916b1beSKeith Busch } 3333d916b1beSKeith Busch unfreeze: 3334d916b1beSKeith Busch nvme_unfreeze(ctrl); 3335d916b1beSKeith Busch return ret; 3336d916b1beSKeith Busch } 3337d916b1beSKeith Busch 3338d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3339d916b1beSKeith Busch { 3340d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33414e523547SBaolin Wang 3342c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 334357dacad5SJay Sternberg } 334457dacad5SJay Sternberg 3345d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 334657dacad5SJay Sternberg { 334757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 334857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 334957dacad5SJay Sternberg 3350c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 335157dacad5SJay Sternberg } 335257dacad5SJay Sternberg 335321774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3354d916b1beSKeith Busch .suspend = nvme_suspend, 3355d916b1beSKeith Busch .resume = nvme_resume, 3356d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3357d916b1beSKeith Busch .thaw = nvme_simple_resume, 3358d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3359d916b1beSKeith Busch .restore = nvme_simple_resume, 3360d916b1beSKeith Busch }; 3361d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 336257dacad5SJay Sternberg 3363a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3364a0a3408eSKeith Busch pci_channel_state_t state) 3365a0a3408eSKeith Busch { 3366a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3367a0a3408eSKeith Busch 3368a0a3408eSKeith Busch /* 3369a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3370a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3371a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3372a0a3408eSKeith Busch */ 3373a0a3408eSKeith Busch switch (state) { 3374a0a3408eSKeith Busch case pci_channel_io_normal: 3375a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3376a0a3408eSKeith Busch case pci_channel_io_frozen: 3377d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3378d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3379a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3380a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3381a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3382d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3383d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3384a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3385a0a3408eSKeith Busch } 3386a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3387a0a3408eSKeith Busch } 3388a0a3408eSKeith Busch 3389a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3390a0a3408eSKeith Busch { 3391a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3392a0a3408eSKeith Busch 33931b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3394a0a3408eSKeith Busch pci_restore_state(pdev); 3395d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3396a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3397a0a3408eSKeith Busch } 3398a0a3408eSKeith Busch 3399a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3400a0a3408eSKeith Busch { 340172cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 340272cd4cc2SKeith Busch 340372cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3404a0a3408eSKeith Busch } 3405a0a3408eSKeith Busch 340657dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 340757dacad5SJay Sternberg .error_detected = nvme_error_detected, 340857dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 340957dacad5SJay Sternberg .resume = nvme_error_resume, 3410775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3411775755edSChristoph Hellwig .reset_done = nvme_reset_done, 341257dacad5SJay Sternberg }; 341357dacad5SJay Sternberg 341457dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3415972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 341608095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3417e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3418972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 341999466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3420e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3421972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 342299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 342325e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 342425e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3425972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3426f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3427f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 342850af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34299abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34306c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3431ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3432ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34336299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34346299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3435540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34367b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 343766dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 343866dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 343966dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 344066dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34415bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3442c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3443c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 34440302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34455e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34465e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 344754adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 344854adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34498c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34508c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3451015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3452015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3453d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3454d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3455d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34567ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3457abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34587ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34592cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 34602cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3461c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 346273029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 346373029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 3464d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3465d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3466d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3467d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34686e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34696e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34706e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3471e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3472e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 347308b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 34741629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 34751629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3476f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3477f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3478f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 347941f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 348041f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 34815611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34825611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3483c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3484c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 348502ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 348602ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348789919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 348889919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348943047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 349043047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349143047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 349243047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349343047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 349443047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349543047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 349643047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3497dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3498dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3499538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3500538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3501ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3502ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3503ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3504ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3505ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3506ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3507ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3508ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3509ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3510ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 351170ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 351270ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3513a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3514a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3515a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3516a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 35173765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 35183765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3519f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3520f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 3521d5d3c100SXi Ruoyao { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3522d5d3c100SXi Ruoyao .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 35236b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 35246b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3525d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3526d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 3527200dccd0SShyamin Ayesh { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3528200dccd0SShyamin Ayesh .driver_data = NVME_QUIRK_BOGUS_NID, }, 352980b26240SAbhijit { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 353080b26240SAbhijit .driver_data = NVME_QUIRK_BOGUS_NID, }, 35314bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 35324bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35334bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 35344bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35354bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 35364bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35374bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 35384bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35394bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 35404bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35414bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 35424bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 354398f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 354498f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3545124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 354666341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 354766341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3548d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3549a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3550a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 35510b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 355257dacad5SJay Sternberg { 0, } 355357dacad5SJay Sternberg }; 355457dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 355557dacad5SJay Sternberg 355657dacad5SJay Sternberg static struct pci_driver nvme_driver = { 355757dacad5SJay Sternberg .name = "nvme", 355857dacad5SJay Sternberg .id_table = nvme_id_table, 355957dacad5SJay Sternberg .probe = nvme_probe, 356057dacad5SJay Sternberg .remove = nvme_remove, 356157dacad5SJay Sternberg .shutdown = nvme_shutdown, 3562d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 356357dacad5SJay Sternberg .driver = { 356457dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 356557dacad5SJay Sternberg }, 3566d916b1beSKeith Busch #endif 356774d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 356857dacad5SJay Sternberg .err_handler = &nvme_err_handler, 356957dacad5SJay Sternberg }; 357057dacad5SJay Sternberg 357157dacad5SJay Sternberg static int __init nvme_init(void) 357257dacad5SJay Sternberg { 357381101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 357481101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 357581101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3576612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3577c372cdd1SKeith Busch BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > 3578c372cdd1SKeith Busch S8_MAX); 357917c33167SKeith Busch 35809a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 358157dacad5SJay Sternberg } 358257dacad5SJay Sternberg 358357dacad5SJay Sternberg static void __exit nvme_exit(void) 358457dacad5SJay Sternberg { 358557dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 358603e0f3a6SMing Lei flush_workqueue(nvme_wq); 358757dacad5SJay Sternberg } 358857dacad5SJay Sternberg 358957dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 359057dacad5SJay Sternberg MODULE_LICENSE("GPL"); 359157dacad5SJay Sternberg MODULE_VERSION("1.0"); 359257dacad5SJay Sternberg module_init(nvme_init); 359357dacad5SJay Sternberg module_exit(nvme_exit); 3594