15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1457dacad5SJay Sternberg #include <linux/init.h> 1557dacad5SJay Sternberg #include <linux/interrupt.h> 1657dacad5SJay Sternberg #include <linux/io.h> 1757dacad5SJay Sternberg #include <linux/mm.h> 1857dacad5SJay Sternberg #include <linux/module.h> 1977bf25eaSKeith Busch #include <linux/mutex.h> 20d0877473SKeith Busch #include <linux/once.h> 2157dacad5SJay Sternberg #include <linux/pci.h> 22d916b1beSKeith Busch #include <linux/suspend.h> 2357dacad5SJay Sternberg #include <linux/t10-pi.h> 2457dacad5SJay Sternberg #include <linux/types.h> 259cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2620d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 27a98e58e5SScott Bauer #include <linux/sed-opal.h> 280f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2957dacad5SJay Sternberg 30604c01d5Syupeng #include "trace.h" 3157dacad5SJay Sternberg #include "nvme.h" 3257dacad5SJay Sternberg 33c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 348a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3557dacad5SJay Sternberg 36a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 37adf68f21SChristoph Hellwig 38943e942eSJens Axboe /* 39943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 40943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 41943e942eSJens Axboe */ 42943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 43943e942eSJens Axboe #define NVME_MAX_SEGS 127 44943e942eSJens Axboe 4557dacad5SJay Sternberg static int use_threaded_interrupts; 4657dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4757dacad5SJay Sternberg 4857dacad5SJay Sternberg static bool use_cmb_sqes = true; 4969f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5057dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5157dacad5SJay Sternberg 5287ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5387ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5487ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5587ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5657dacad5SJay Sternberg 57a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 58a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 59a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 60a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 61a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 62a7a7cbe3SChaitanya Kulkarni 6327453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6427453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 65b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 66b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 67b27c1e68Sweiping zhang .set = io_queue_depth_set, 6861f3b896SChaitanya Kulkarni .get = param_get_uint, 69b27c1e68Sweiping zhang }; 70b27c1e68Sweiping zhang 7161f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 72b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7327453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 74b27c1e68Sweiping zhang 759c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 769c9e76d5SWeiping Zhang { 779c9e76d5SWeiping Zhang unsigned int n; 789c9e76d5SWeiping Zhang int ret; 799c9e76d5SWeiping Zhang 809c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 819c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 829c9e76d5SWeiping Zhang return -EINVAL; 839c9e76d5SWeiping Zhang return param_set_uint(val, kp); 849c9e76d5SWeiping Zhang } 859c9e76d5SWeiping Zhang 869c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 879c9e76d5SWeiping Zhang .set = io_queue_count_set, 889c9e76d5SWeiping Zhang .get = param_get_uint, 899c9e76d5SWeiping Zhang }; 909c9e76d5SWeiping Zhang 913f68baf7SKeith Busch static unsigned int write_queues; 929c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 933b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 943b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 953b6592f7SJens Axboe "will share a queue set."); 963b6592f7SJens Axboe 973f68baf7SKeith Busch static unsigned int poll_queues; 989c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 994b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1004b04cc6aSJens Axboe 101df4f9bc4SDavid E. Box static bool noacpi; 102df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 103df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 104df4f9bc4SDavid E. Box 1051c63dc66SChristoph Hellwig struct nvme_dev; 1061c63dc66SChristoph Hellwig struct nvme_queue; 10757dacad5SJay Sternberg 108a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1098fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11057dacad5SJay Sternberg 11157dacad5SJay Sternberg /* 1121c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1131c63dc66SChristoph Hellwig */ 1141c63dc66SChristoph Hellwig struct nvme_dev { 115147b27e4SSagi Grimberg struct nvme_queue *queues; 1161c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1171c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1181c63dc66SChristoph Hellwig u32 __iomem *dbs; 1191c63dc66SChristoph Hellwig struct device *dev; 1201c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1211c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1221c63dc66SChristoph Hellwig unsigned online_queues; 1231c63dc66SChristoph Hellwig unsigned max_qid; 124e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12522b55601SKeith Busch unsigned int num_vecs; 1267442ddceSJohn Garry u32 q_depth; 127c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1281c63dc66SChristoph Hellwig u32 db_stride; 1291c63dc66SChristoph Hellwig void __iomem *bar; 13097f6ef64SXu Yu unsigned long bar_mapped_size; 1315c8809e6SChristoph Hellwig struct work_struct remove_work; 13277bf25eaSKeith Busch struct mutex shutdown_lock; 1331c63dc66SChristoph Hellwig bool subsystem; 1341c63dc66SChristoph Hellwig u64 cmb_size; 1350f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1361c63dc66SChristoph Hellwig u32 cmbsz; 137202021c1SStephen Bates u32 cmbloc; 1381c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 139d916b1beSKeith Busch u32 last_ps; 140a5df5e79SKeith Busch bool hmb; 14187ad72a5SChristoph Hellwig 142943e942eSJens Axboe mempool_t *iod_mempool; 143943e942eSJens Axboe 14487ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 145f9f38e33SHelen Koike u32 *dbbuf_dbs; 146f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 147f9f38e33SHelen Koike u32 *dbbuf_eis; 148f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 14987ad72a5SChristoph Hellwig 15087ad72a5SChristoph Hellwig /* host memory buffer support: */ 15187ad72a5SChristoph Hellwig u64 host_mem_size; 15287ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1534033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15587ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1562a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1572a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1582a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 1590521905eSKeith Busch 1600521905eSKeith Busch bool attrs_added; 16157dacad5SJay Sternberg }; 16257dacad5SJay Sternberg 163b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 164b27c1e68Sweiping zhang { 16527453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16627453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 167b27c1e68Sweiping zhang } 168b27c1e68Sweiping zhang 169f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return qid * 2 * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 174f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175f9f38e33SHelen Koike { 176f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 177f9f38e33SHelen Koike } 178f9f38e33SHelen Koike 1791c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1801c63dc66SChristoph Hellwig { 1811c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1821c63dc66SChristoph Hellwig } 1831c63dc66SChristoph Hellwig 18457dacad5SJay Sternberg /* 18557dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18657dacad5SJay Sternberg * commands and one for I/O commands). 18757dacad5SJay Sternberg */ 18857dacad5SJay Sternberg struct nvme_queue { 18957dacad5SJay Sternberg struct nvme_dev *dev; 1901ab0cd69SJens Axboe spinlock_t sq_lock; 191c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1923a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1933a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19474943d45SKeith Busch struct nvme_completion *cqes; 19557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19757dacad5SJay Sternberg u32 __iomem *q_db; 1987442ddceSJohn Garry u32 q_depth; 1997c349ddeSKeith Busch u16 cq_vector; 20057dacad5SJay Sternberg u16 sq_tail; 20138210800SKeith Busch u16 last_sq_tail; 20257dacad5SJay Sternberg u16 cq_head; 20357dacad5SJay Sternberg u16 qid; 20457dacad5SJay Sternberg u8 cq_phase; 205c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2064e224106SChristoph Hellwig unsigned long flags; 2074e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20863223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 209d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2107c349ddeSKeith Busch #define NVMEQ_POLLED 3 211f9f38e33SHelen Koike u32 *dbbuf_sq_db; 212f9f38e33SHelen Koike u32 *dbbuf_cq_db; 213f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 214f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 215d1ed6aa1SChristoph Hellwig struct completion delete_done; 21657dacad5SJay Sternberg }; 21757dacad5SJay Sternberg 21857dacad5SJay Sternberg /* 2199b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2209b048119SChristoph Hellwig * 2219b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2229b048119SChristoph Hellwig * to the actual struct scatterlist. 22371bd150cSChristoph Hellwig */ 22471bd150cSChristoph Hellwig struct nvme_iod { 225d49187e9SChristoph Hellwig struct nvme_request req; 226af7fae85SKeith Busch struct nvme_command cmd; 227f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 228a7a7cbe3SChaitanya Kulkarni bool use_sgl; 229f4800d6dSChristoph Hellwig int aborted; 23071bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23171bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23271bd150cSChristoph Hellwig dma_addr_t first_dma; 233dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 234783b94bdSChristoph Hellwig dma_addr_t meta_dma; 235f4800d6dSChristoph Hellwig struct scatterlist *sg; 23657dacad5SJay Sternberg }; 23757dacad5SJay Sternberg 2382a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2393b6592f7SJens Axboe { 2402a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 241f9f38e33SHelen Koike } 242f9f38e33SHelen Koike 243f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 244f9f38e33SHelen Koike { 2452a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 246f9f38e33SHelen Koike 247f9f38e33SHelen Koike if (dev->dbbuf_dbs) 248f9f38e33SHelen Koike return 0; 249f9f38e33SHelen Koike 250f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 251f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 252f9f38e33SHelen Koike GFP_KERNEL); 253f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 254f9f38e33SHelen Koike return -ENOMEM; 255f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 256f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 257f9f38e33SHelen Koike GFP_KERNEL); 258f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 259f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 261f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 262f9f38e33SHelen Koike return -ENOMEM; 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike return 0; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 269f9f38e33SHelen Koike { 2702a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 273f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 274f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 275f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 276f9f38e33SHelen Koike } 277f9f38e33SHelen Koike if (dev->dbbuf_eis) { 278f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 279f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 280f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 281f9f38e33SHelen Koike } 282f9f38e33SHelen Koike } 283f9f38e33SHelen Koike 284f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 285f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 286f9f38e33SHelen Koike { 287f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 288f9f38e33SHelen Koike return; 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 291f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 292f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 293f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 294f9f38e33SHelen Koike } 295f9f38e33SHelen Koike 2960f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 2970f0d2c87SMinwoo Im { 2980f0d2c87SMinwoo Im if (!nvmeq->qid) 2990f0d2c87SMinwoo Im return; 3000f0d2c87SMinwoo Im 3010f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3020f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3030f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3040f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3050f0d2c87SMinwoo Im } 3060f0d2c87SMinwoo Im 307f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 308f9f38e33SHelen Koike { 309f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3100f0d2c87SMinwoo Im unsigned int i; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 313f9f38e33SHelen Koike return; 314f9f38e33SHelen Koike 315f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 316f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 317f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3209bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 321f9f38e33SHelen Koike /* Free memory and continue on */ 322f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3230f0d2c87SMinwoo Im 3240f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3250f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 326f9f38e33SHelen Koike } 327f9f38e33SHelen Koike } 328f9f38e33SHelen Koike 329f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 330f9f38e33SHelen Koike { 331f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 332f9f38e33SHelen Koike } 333f9f38e33SHelen Koike 334f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 335f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 336f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 337f9f38e33SHelen Koike { 338f9f38e33SHelen Koike if (dbbuf_db) { 339f9f38e33SHelen Koike u16 old_value; 340f9f38e33SHelen Koike 341f9f38e33SHelen Koike /* 342f9f38e33SHelen Koike * Ensure that the queue is written before updating 343f9f38e33SHelen Koike * the doorbell in memory 344f9f38e33SHelen Koike */ 345f9f38e33SHelen Koike wmb(); 346f9f38e33SHelen Koike 347f9f38e33SHelen Koike old_value = *dbbuf_db; 348f9f38e33SHelen Koike *dbbuf_db = value; 349f9f38e33SHelen Koike 350f1ed3df2SMichal Wnukowski /* 351f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 352f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 353f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 354f1ed3df2SMichal Wnukowski * the doorbell. 355f1ed3df2SMichal Wnukowski */ 356f1ed3df2SMichal Wnukowski mb(); 357f1ed3df2SMichal Wnukowski 358f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 359f9f38e33SHelen Koike return false; 360f9f38e33SHelen Koike } 361f9f38e33SHelen Koike 362f9f38e33SHelen Koike return true; 36357dacad5SJay Sternberg } 36457dacad5SJay Sternberg 36557dacad5SJay Sternberg /* 36657dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 36757dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 36857dacad5SJay Sternberg * the I/O. 36957dacad5SJay Sternberg */ 370b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 37157dacad5SJay Sternberg { 372b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3736c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 37457dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 37557dacad5SJay Sternberg } 37657dacad5SJay Sternberg 377a7a7cbe3SChaitanya Kulkarni /* 378a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 379a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 380a7a7cbe3SChaitanya Kulkarni */ 381b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 382f4800d6dSChristoph Hellwig { 383b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 384b13c6393SChaitanya Kulkarni PAGE_SIZE); 385f4800d6dSChristoph Hellwig } 386f4800d6dSChristoph Hellwig 387b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 38857dacad5SJay Sternberg { 389b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 390a7a7cbe3SChaitanya Kulkarni 391b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 392b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 393a7a7cbe3SChaitanya Kulkarni } 394a7a7cbe3SChaitanya Kulkarni 39557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39657dacad5SJay Sternberg unsigned int hctx_idx) 39757dacad5SJay Sternberg { 39857dacad5SJay Sternberg struct nvme_dev *dev = data; 399147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40057dacad5SJay Sternberg 40157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40357dacad5SJay Sternberg 40457dacad5SJay Sternberg hctx->driver_data = nvmeq; 40557dacad5SJay Sternberg return 0; 40657dacad5SJay Sternberg } 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40957dacad5SJay Sternberg unsigned int hctx_idx) 41057dacad5SJay Sternberg { 41157dacad5SJay Sternberg struct nvme_dev *dev = data; 412147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41557dacad5SJay Sternberg hctx->driver_data = nvmeq; 41657dacad5SJay Sternberg return 0; 41757dacad5SJay Sternberg } 41857dacad5SJay Sternberg 419d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 420d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42157dacad5SJay Sternberg { 422d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 423f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4240350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 425147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg BUG_ON(!nvmeq); 428f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 42959e29ce6SSagi Grimberg 43059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 431f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 43257dacad5SJay Sternberg return 0; 43357dacad5SJay Sternberg } 43457dacad5SJay Sternberg 4353b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4363b6592f7SJens Axboe { 4373b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4383b6592f7SJens Axboe if (dev->num_vecs > 1) 4393b6592f7SJens Axboe return 1; 4403b6592f7SJens Axboe 4413b6592f7SJens Axboe return 0; 4423b6592f7SJens Axboe } 4433b6592f7SJens Axboe 444dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 445dca51e78SChristoph Hellwig { 446dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4473b6592f7SJens Axboe int i, qoff, offset; 448dca51e78SChristoph Hellwig 4493b6592f7SJens Axboe offset = queue_irq_offset(dev); 4503b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4513b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4523b6592f7SJens Axboe 4533b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4543b6592f7SJens Axboe if (!map->nr_queues) { 455e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4567e849dd9SChristoph Hellwig continue; 4573b6592f7SJens Axboe } 4583b6592f7SJens Axboe 4594b04cc6aSJens Axboe /* 4604b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4614b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4624b04cc6aSJens Axboe */ 4633b6592f7SJens Axboe map->queue_offset = qoff; 464cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4653b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4664b04cc6aSJens Axboe else 4674b04cc6aSJens Axboe blk_mq_map_queues(map); 4683b6592f7SJens Axboe qoff += map->nr_queues; 4693b6592f7SJens Axboe offset += map->nr_queues; 4703b6592f7SJens Axboe } 4713b6592f7SJens Axboe 4723b6592f7SJens Axboe return 0; 473dca51e78SChristoph Hellwig } 474dca51e78SChristoph Hellwig 47538210800SKeith Busch /* 47638210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47738210800SKeith Busch */ 47838210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47904f3eafdSJens Axboe { 48038210800SKeith Busch if (!write_sq) { 48138210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 48238210800SKeith Busch 48338210800SKeith Busch if (next_tail == nvmeq->q_depth) 48438210800SKeith Busch next_tail = 0; 48538210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48638210800SKeith Busch return; 48738210800SKeith Busch } 48838210800SKeith Busch 48904f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 49004f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 49104f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 49238210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49304f3eafdSJens Axboe } 49404f3eafdSJens Axboe 49557dacad5SJay Sternberg /** 49690ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 49757dacad5SJay Sternberg * @nvmeq: The queue to use 49857dacad5SJay Sternberg * @cmd: The command to send 49904f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 50057dacad5SJay Sternberg */ 50104f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 50204f3eafdSJens Axboe bool write_sq) 50357dacad5SJay Sternberg { 50490ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 505c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 506c1e0cc7eSBenjamin Herrenschmidt cmd, sizeof(*cmd)); 50790ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 50890ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 50938210800SKeith Busch nvme_write_sq_db(nvmeq, write_sq); 51004f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 51104f3eafdSJens Axboe } 51204f3eafdSJens Axboe 51304f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51404f3eafdSJens Axboe { 51504f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51604f3eafdSJens Axboe 51704f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51838210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 51938210800SKeith Busch nvme_write_sq_db(nvmeq, true); 52090ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52157dacad5SJay Sternberg } 52257dacad5SJay Sternberg 523a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52457dacad5SJay Sternberg { 525f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 526a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52757dacad5SJay Sternberg } 52857dacad5SJay Sternberg 529955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 530955b1b5aSMinwoo Im { 531955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53220469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 533955b1b5aSMinwoo Im unsigned int avg_seg_size; 534955b1b5aSMinwoo Im 53520469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 536955b1b5aSMinwoo Im 537253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 538955b1b5aSMinwoo Im return false; 539955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 540955b1b5aSMinwoo Im return false; 541955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 542955b1b5aSMinwoo Im return false; 543955b1b5aSMinwoo Im return true; 544955b1b5aSMinwoo Im } 545955b1b5aSMinwoo Im 5469275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54757dacad5SJay Sternberg { 5486c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5499275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5509275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 55157dacad5SJay Sternberg int i; 55257dacad5SJay Sternberg 5539275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5549275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5559275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5569275c206SChristoph Hellwig 5579275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5589275c206SChristoph Hellwig dma_addr = next_dma_addr; 559dff824b2SChristoph Hellwig } 5609275c206SChristoph Hellwig } 5619275c206SChristoph Hellwig 5629275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5639275c206SChristoph Hellwig { 5649275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5659275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5669275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5679275c206SChristoph Hellwig int i; 5689275c206SChristoph Hellwig 5699275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5709275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5719275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5729275c206SChristoph Hellwig 5739275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5749275c206SChristoph Hellwig dma_addr = next_dma_addr; 5759275c206SChristoph Hellwig } 5769275c206SChristoph Hellwig } 5779275c206SChristoph Hellwig 5789275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5799275c206SChristoph Hellwig { 5809275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 581dff824b2SChristoph Hellwig 5827f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5837f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5847f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5857f73eac3SLogan Gunthorpe else 586dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5879275c206SChristoph Hellwig } 5887fe07d14SChristoph Hellwig 5899275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5909275c206SChristoph Hellwig { 5919275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5927fe07d14SChristoph Hellwig 5939275c206SChristoph Hellwig if (iod->dma_len) { 5949275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5959275c206SChristoph Hellwig rq_dma_dir(req)); 5969275c206SChristoph Hellwig return; 5979275c206SChristoph Hellwig } 5989275c206SChristoph Hellwig 5999275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 6009275c206SChristoph Hellwig 6019275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 60257dacad5SJay Sternberg if (iod->npages == 0) 603a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6049275c206SChristoph Hellwig iod->first_dma); 6059275c206SChristoph Hellwig else if (iod->use_sgl) 6069275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6079275c206SChristoph Hellwig else 6089275c206SChristoph Hellwig nvme_free_prps(dev, req); 609943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61057dacad5SJay Sternberg } 61157dacad5SJay Sternberg 612d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 613d0877473SKeith Busch { 614d0877473SKeith Busch int i; 615d0877473SKeith Busch struct scatterlist *sg; 616d0877473SKeith Busch 617d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 618d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 619d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 620d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 621d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 622d0877473SKeith Busch sg_dma_len(sg)); 623d0877473SKeith Busch } 624d0877473SKeith Busch } 625d0877473SKeith Busch 626a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 627a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62857dacad5SJay Sternberg { 629f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63057dacad5SJay Sternberg struct dma_pool *pool; 631b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63257dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63357dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63457dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6356c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63657dacad5SJay Sternberg __le64 *prp_list; 637a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63857dacad5SJay Sternberg dma_addr_t prp_dma; 63957dacad5SJay Sternberg int nprps, i; 64057dacad5SJay Sternberg 6416c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6425228b328SJan H. Schönherr if (length <= 0) { 6435228b328SJan H. Schönherr iod->first_dma = 0; 644a7a7cbe3SChaitanya Kulkarni goto done; 6455228b328SJan H. Schönherr } 64657dacad5SJay Sternberg 6476c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 64857dacad5SJay Sternberg if (dma_len) { 6496c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 65057dacad5SJay Sternberg } else { 65157dacad5SJay Sternberg sg = sg_next(sg); 65257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65457dacad5SJay Sternberg } 65557dacad5SJay Sternberg 6566c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65757dacad5SJay Sternberg iod->first_dma = dma_addr; 658a7a7cbe3SChaitanya Kulkarni goto done; 65957dacad5SJay Sternberg } 66057dacad5SJay Sternberg 6616c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 66257dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66357dacad5SJay Sternberg pool = dev->prp_small_pool; 66457dacad5SJay Sternberg iod->npages = 0; 66557dacad5SJay Sternberg } else { 66657dacad5SJay Sternberg pool = dev->prp_page_pool; 66757dacad5SJay Sternberg iod->npages = 1; 66857dacad5SJay Sternberg } 66957dacad5SJay Sternberg 67069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67157dacad5SJay Sternberg if (!prp_list) { 67257dacad5SJay Sternberg iod->first_dma = dma_addr; 67357dacad5SJay Sternberg iod->npages = -1; 67486eea289SKeith Busch return BLK_STS_RESOURCE; 67557dacad5SJay Sternberg } 67657dacad5SJay Sternberg list[0] = prp_list; 67757dacad5SJay Sternberg iod->first_dma = prp_dma; 67857dacad5SJay Sternberg i = 0; 67957dacad5SJay Sternberg for (;;) { 6806c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 68157dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68357dacad5SJay Sternberg if (!prp_list) 684fa073216SChristoph Hellwig goto free_prps; 68557dacad5SJay Sternberg list[iod->npages++] = prp_list; 68657dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68757dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68857dacad5SJay Sternberg i = 1; 68957dacad5SJay Sternberg } 69057dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6916c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6926c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6936c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69457dacad5SJay Sternberg if (length <= 0) 69557dacad5SJay Sternberg break; 69657dacad5SJay Sternberg if (dma_len > 0) 69757dacad5SJay Sternberg continue; 69886eea289SKeith Busch if (unlikely(dma_len < 0)) 69986eea289SKeith Busch goto bad_sgl; 70057dacad5SJay Sternberg sg = sg_next(sg); 70157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70357dacad5SJay Sternberg } 704a7a7cbe3SChaitanya Kulkarni done: 705a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 706a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70786eea289SKeith Busch return BLK_STS_OK; 708fa073216SChristoph Hellwig free_prps: 709fa073216SChristoph Hellwig nvme_free_prps(dev, req); 710fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 71186eea289SKeith Busch bad_sgl: 712d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 713d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 714d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71586eea289SKeith Busch return BLK_STS_IOERR; 71657dacad5SJay Sternberg } 71757dacad5SJay Sternberg 718a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 719a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 720a7a7cbe3SChaitanya Kulkarni { 721a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 722a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 723a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 724a7a7cbe3SChaitanya Kulkarni } 725a7a7cbe3SChaitanya Kulkarni 726a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 727a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 728a7a7cbe3SChaitanya Kulkarni { 729a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 730a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 731a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 732a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 733a7a7cbe3SChaitanya Kulkarni } else { 734a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 735a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 736a7a7cbe3SChaitanya Kulkarni } 737a7a7cbe3SChaitanya Kulkarni } 738a7a7cbe3SChaitanya Kulkarni 739a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 740b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 741a7a7cbe3SChaitanya Kulkarni { 742a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 743a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 744a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 745a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 746a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 747b0f2853bSChristoph Hellwig int i = 0; 748a7a7cbe3SChaitanya Kulkarni 749a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 750a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 751a7a7cbe3SChaitanya Kulkarni 752b0f2853bSChristoph Hellwig if (entries == 1) { 753a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 754a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 755a7a7cbe3SChaitanya Kulkarni } 756a7a7cbe3SChaitanya Kulkarni 757a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 758a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 759a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 760a7a7cbe3SChaitanya Kulkarni } else { 761a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 762a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 763a7a7cbe3SChaitanya Kulkarni } 764a7a7cbe3SChaitanya Kulkarni 765a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 766a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 767a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 768a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 769a7a7cbe3SChaitanya Kulkarni } 770a7a7cbe3SChaitanya Kulkarni 771a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 772a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 773a7a7cbe3SChaitanya Kulkarni 774a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 775a7a7cbe3SChaitanya Kulkarni 776a7a7cbe3SChaitanya Kulkarni do { 777a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 778a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 779a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 780a7a7cbe3SChaitanya Kulkarni 781a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 782a7a7cbe3SChaitanya Kulkarni if (!sg_list) 783fa073216SChristoph Hellwig goto free_sgls; 784a7a7cbe3SChaitanya Kulkarni 785a7a7cbe3SChaitanya Kulkarni i = 0; 786a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 787a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 788a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 789a7a7cbe3SChaitanya Kulkarni } 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 792a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 793b0f2853bSChristoph Hellwig } while (--entries > 0); 794a7a7cbe3SChaitanya Kulkarni 795a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 796fa073216SChristoph Hellwig free_sgls: 797fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 798fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 799a7a7cbe3SChaitanya Kulkarni } 800a7a7cbe3SChaitanya Kulkarni 801dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 802dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 803dff824b2SChristoph Hellwig struct bio_vec *bv) 804dff824b2SChristoph Hellwig { 805dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8066c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8076c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 808dff824b2SChristoph Hellwig 809dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 810dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 811dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 812dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 813dff824b2SChristoph Hellwig 814dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 815dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 816dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 817359c1f88SBaolin Wang return BLK_STS_OK; 818dff824b2SChristoph Hellwig } 819dff824b2SChristoph Hellwig 82029791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82129791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82229791057SChristoph Hellwig struct bio_vec *bv) 82329791057SChristoph Hellwig { 82429791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82529791057SChristoph Hellwig 82629791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82729791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 82829791057SChristoph Hellwig return BLK_STS_RESOURCE; 82929791057SChristoph Hellwig iod->dma_len = bv->bv_len; 83029791057SChristoph Hellwig 831049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 83229791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83329791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83429791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 835359c1f88SBaolin Wang return BLK_STS_OK; 83629791057SChristoph Hellwig } 83729791057SChristoph Hellwig 838fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 839b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84057dacad5SJay Sternberg { 841f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84270479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 843b0f2853bSChristoph Hellwig int nr_mapped; 84457dacad5SJay Sternberg 845dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 846dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 847dff824b2SChristoph Hellwig 848dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8496c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 850dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 851dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85229791057SChristoph Hellwig 853e51183beSNiklas Cassel if (iod->nvmeq->qid && sgl_threshold && 854253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 85529791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85629791057SChristoph Hellwig &cmnd->rw, &bv); 857dff824b2SChristoph Hellwig } 858dff824b2SChristoph Hellwig } 859dff824b2SChristoph Hellwig 860dff824b2SChristoph Hellwig iod->dma_len = 0; 8619b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8629b048119SChristoph Hellwig if (!iod->sg) 8639b048119SChristoph Hellwig return BLK_STS_RESOURCE; 864f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86570479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 866ba1ca37eSChristoph Hellwig if (!iod->nents) 867fa073216SChristoph Hellwig goto out_free_sg; 868ba1ca37eSChristoph Hellwig 869e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8702b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8712b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 872e0596ab2SLogan Gunthorpe else 873e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87470479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 875b0f2853bSChristoph Hellwig if (!nr_mapped) 876fa073216SChristoph Hellwig goto out_free_sg; 877ba1ca37eSChristoph Hellwig 87870479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 879955b1b5aSMinwoo Im if (iod->use_sgl) 880b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 881a7a7cbe3SChaitanya Kulkarni else 882a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8834aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 884fa073216SChristoph Hellwig goto out_unmap_sg; 885fa073216SChristoph Hellwig return BLK_STS_OK; 886fa073216SChristoph Hellwig 887fa073216SChristoph Hellwig out_unmap_sg: 888fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 889fa073216SChristoph Hellwig out_free_sg: 890fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 891ba1ca37eSChristoph Hellwig return ret; 89257dacad5SJay Sternberg } 89357dacad5SJay Sternberg 8944aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8954aedb705SChristoph Hellwig struct nvme_command *cmnd) 8964aedb705SChristoph Hellwig { 8974aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8984aedb705SChristoph Hellwig 8994aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 9004aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9014aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9024aedb705SChristoph Hellwig return BLK_STS_IOERR; 9034aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 904359c1f88SBaolin Wang return BLK_STS_OK; 9054aedb705SChristoph Hellwig } 9064aedb705SChristoph Hellwig 90757dacad5SJay Sternberg /* 90857dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 90957dacad5SJay Sternberg */ 910fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91157dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91257dacad5SJay Sternberg { 91357dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 91557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 91657dacad5SJay Sternberg struct request *req = bd->rq; 9179b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 918af7fae85SKeith Busch struct nvme_command *cmnd = &iod->cmd; 919ebe6d874SChristoph Hellwig blk_status_t ret; 92057dacad5SJay Sternberg 9219b048119SChristoph Hellwig iod->aborted = 0; 9229b048119SChristoph Hellwig iod->npages = -1; 9239b048119SChristoph Hellwig iod->nents = 0; 9249b048119SChristoph Hellwig 925d1f06f4aSJens Axboe /* 926d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 927d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 928d1f06f4aSJens Axboe */ 9294e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 930d1f06f4aSJens Axboe return BLK_STS_IOERR; 931d1f06f4aSJens Axboe 932d4060d2bSTao Chiu if (!nvme_check_ready(&dev->ctrl, req, true)) 933d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 934d4060d2bSTao Chiu 935f4b9e6c9SKeith Busch ret = nvme_setup_cmd(ns, req); 936fc17b653SChristoph Hellwig if (ret) 937f4800d6dSChristoph Hellwig return ret; 93857dacad5SJay Sternberg 939fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 940af7fae85SKeith Busch ret = nvme_map_data(dev, req, cmnd); 941fc17b653SChristoph Hellwig if (ret) 9429b048119SChristoph Hellwig goto out_free_cmd; 943fc17b653SChristoph Hellwig } 944ba1ca37eSChristoph Hellwig 9454aedb705SChristoph Hellwig if (blk_integrity_rq(req)) { 946af7fae85SKeith Busch ret = nvme_map_metadata(dev, req, cmnd); 9474aedb705SChristoph Hellwig if (ret) 9484aedb705SChristoph Hellwig goto out_unmap_data; 9494aedb705SChristoph Hellwig } 9504aedb705SChristoph Hellwig 951aae239e1SChristoph Hellwig blk_mq_start_request(req); 952af7fae85SKeith Busch nvme_submit_cmd(nvmeq, cmnd, bd->last); 953fc17b653SChristoph Hellwig return BLK_STS_OK; 9544aedb705SChristoph Hellwig out_unmap_data: 9554aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 956f9d03f96SChristoph Hellwig out_free_cmd: 957f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 958ba1ca37eSChristoph Hellwig return ret; 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 96177f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 962eee417b0SChristoph Hellwig { 963f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 9644aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 965eee417b0SChristoph Hellwig 9664aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 9674aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9684aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 969b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9704aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 97177f02a7aSChristoph Hellwig nvme_complete_rq(req); 97257dacad5SJay Sternberg } 97357dacad5SJay Sternberg 974d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 975750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 976d783e0bdSMarta Rybczynska { 97774943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 97874943d45SKeith Busch 97974943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 980d783e0bdSMarta Rybczynska } 981d783e0bdSMarta Rybczynska 982eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 98357dacad5SJay Sternberg { 984eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 98557dacad5SJay Sternberg 986eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 987eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 988eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 989eb281c82SSagi Grimberg } 990adf68f21SChristoph Hellwig 991cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 992cfa27356SChristoph Hellwig { 993cfa27356SChristoph Hellwig if (!nvmeq->qid) 994cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 995cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 996cfa27356SChristoph Hellwig } 997cfa27356SChristoph Hellwig 9985cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 99957dacad5SJay Sternberg { 100074943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 100162df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 100257dacad5SJay Sternberg struct request *req; 1003adf68f21SChristoph Hellwig 1004adf68f21SChristoph Hellwig /* 1005adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1006adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1007adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1008adf68f21SChristoph Hellwig * for them but rather special case them here. 1009adf68f21SChristoph Hellwig */ 101062df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10117bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 101283a12fb7SSagi Grimberg cqe->status, &cqe->result); 1013a0fa9647SJens Axboe return; 101457dacad5SJay Sternberg } 101557dacad5SJay Sternberg 1016e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 101750b7c243SXianting Tian if (unlikely(!req)) { 101850b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 101950b7c243SXianting Tian "invalid id %d completed on queue %d\n", 102062df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 102150b7c243SXianting Tian return; 102250b7c243SXianting Tian } 102350b7c243SXianting Tian 1024604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 10252eb81a33SChristoph Hellwig if (!nvme_try_complete_req(req, cqe->status, cqe->result)) 1026ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 102783a12fb7SSagi Grimberg } 102857dacad5SJay Sternberg 10295cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10305cb525c8SJens Axboe { 1031a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1032a8de6639SAlexey Dobriyan 1033a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1034920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1035e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1036a8de6639SAlexey Dobriyan } else { 1037a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1038920d13a8SSagi Grimberg } 1039a0fa9647SJens Axboe } 1040a0fa9647SJens Axboe 1041324b494cSKeith Busch static inline int nvme_process_cq(struct nvme_queue *nvmeq) 1042a0fa9647SJens Axboe { 10431052b8acSJens Axboe int found = 0; 104483a12fb7SSagi Grimberg 10451052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10461052b8acSJens Axboe found++; 1047b69e2ef2SKeith Busch /* 1048b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1049b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1050b69e2ef2SKeith Busch */ 1051b69e2ef2SKeith Busch dma_rmb(); 1052324b494cSKeith Busch nvme_handle_cqe(nvmeq, nvmeq->cq_head); 10535cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 105457dacad5SJay Sternberg } 105557dacad5SJay Sternberg 1056324b494cSKeith Busch if (found) 1057eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10585cb525c8SJens Axboe return found; 105957dacad5SJay Sternberg } 106057dacad5SJay Sternberg 106157dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 106257dacad5SJay Sternberg { 106357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10645cb525c8SJens Axboe 1065324b494cSKeith Busch if (nvme_process_cq(nvmeq)) 106605fae499SChaitanya Kulkarni return IRQ_HANDLED; 106705fae499SChaitanya Kulkarni return IRQ_NONE; 106857dacad5SJay Sternberg } 106957dacad5SJay Sternberg 107057dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 107157dacad5SJay Sternberg { 107257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10734e523547SBaolin Wang 1074750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1076d783e0bdSMarta Rybczynska return IRQ_NONE; 107757dacad5SJay Sternberg } 107857dacad5SJay Sternberg 10790b2a8a9fSChristoph Hellwig /* 1080fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 10810b2a8a9fSChristoph Hellwig * Can be called from any context. 10820b2a8a9fSChristoph Hellwig */ 1083fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1084a0fa9647SJens Axboe { 10853a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1086a0fa9647SJens Axboe 1087fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1088fa059b85SKeith Busch 10893a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1090fa059b85SKeith Busch nvme_process_cq(nvmeq); 10913a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 109291a509f8SChristoph Hellwig } 1093442e19b7SSagi Grimberg 10949743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10957776db1cSKeith Busch { 10967776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1097dabcefabSJens Axboe bool found; 1098dabcefabSJens Axboe 1099dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1100dabcefabSJens Axboe return 0; 1101dabcefabSJens Axboe 11023a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1103324b494cSKeith Busch found = nvme_process_cq(nvmeq); 11043a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1105dabcefabSJens Axboe 1106dabcefabSJens Axboe return found; 1107dabcefabSJens Axboe } 1108dabcefabSJens Axboe 1109ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 111057dacad5SJay Sternberg { 1111f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1112147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1113f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 111457dacad5SJay Sternberg 111557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1116ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 111704f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 111857dacad5SJay Sternberg } 111957dacad5SJay Sternberg 112057dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 112157dacad5SJay Sternberg { 1122f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 112357dacad5SJay Sternberg 112457dacad5SJay Sternberg c.delete_queue.opcode = opcode; 112557dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 112657dacad5SJay Sternberg 11271c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112857dacad5SJay Sternberg } 112957dacad5SJay Sternberg 113057dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1131a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 113257dacad5SJay Sternberg { 1133f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 11344b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11354b04cc6aSJens Axboe 11367c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11374b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 113857dacad5SJay Sternberg 113957dacad5SJay Sternberg /* 114016772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 114157dacad5SJay Sternberg * is attached to the request. 114257dacad5SJay Sternberg */ 114357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 114457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 114557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 114657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 114757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1148a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 114957dacad5SJay Sternberg 11501c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115157dacad5SJay Sternberg } 115257dacad5SJay Sternberg 115357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 115457dacad5SJay Sternberg struct nvme_queue *nvmeq) 115557dacad5SJay Sternberg { 11569abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1157f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 115881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 115957dacad5SJay Sternberg 116057dacad5SJay Sternberg /* 11619abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11629abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11639abd68efSJens Axboe * URGENT. 11649abd68efSJens Axboe */ 11659abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11669abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11679abd68efSJens Axboe 11689abd68efSJens Axboe /* 116916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117057dacad5SJay Sternberg * is attached to the request. 117157dacad5SJay Sternberg */ 117257dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 117357dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 117457dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 117557dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117657dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 117757dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 117857dacad5SJay Sternberg 11791c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 118057dacad5SJay Sternberg } 118157dacad5SJay Sternberg 118257dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 118357dacad5SJay Sternberg { 118457dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 118557dacad5SJay Sternberg } 118657dacad5SJay Sternberg 118757dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 118857dacad5SJay Sternberg { 118957dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 119057dacad5SJay Sternberg } 119157dacad5SJay Sternberg 11922a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 119357dacad5SJay Sternberg { 1194f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1195f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119657dacad5SJay Sternberg 119727fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 119827fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1199e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1200e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 120157dacad5SJay Sternberg } 120257dacad5SJay Sternberg 1203b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1204b2a0eb1aSKeith Busch { 1205b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1206b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1207b2a0eb1aSKeith Busch */ 1208b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1209b2a0eb1aSKeith Busch 1210ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1211ad70062cSJianchao Wang switch (dev->ctrl.state) { 1212ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1213ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1214b2a0eb1aSKeith Busch return false; 1215ad70062cSJianchao Wang default: 1216ad70062cSJianchao Wang break; 1217ad70062cSJianchao Wang } 1218b2a0eb1aSKeith Busch 1219b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1220b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1221b2a0eb1aSKeith Busch */ 1222b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1223b2a0eb1aSKeith Busch return false; 1224b2a0eb1aSKeith Busch 1225b2a0eb1aSKeith Busch return true; 1226b2a0eb1aSKeith Busch } 1227b2a0eb1aSKeith Busch 1228b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1229b2a0eb1aSKeith Busch { 1230b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1231b2a0eb1aSKeith Busch u16 pci_status; 1232b2a0eb1aSKeith Busch int result; 1233b2a0eb1aSKeith Busch 1234b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1235b2a0eb1aSKeith Busch &pci_status); 1236b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1237b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1238b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1239b2a0eb1aSKeith Busch csts, pci_status); 1240b2a0eb1aSKeith Busch else 1241b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1242b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1243b2a0eb1aSKeith Busch csts, result); 1244b2a0eb1aSKeith Busch } 1245b2a0eb1aSKeith Busch 124631c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 124757dacad5SJay Sternberg { 1248f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1249f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 125057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 125157dacad5SJay Sternberg struct request *abort_req; 1252f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1253b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1254b2a0eb1aSKeith Busch 1255651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1256651438bbSWen Xiong * the recovery mechanism will surely fail. 1257651438bbSWen Xiong */ 1258651438bbSWen Xiong mb(); 1259651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1260651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1261651438bbSWen Xiong 1262b2a0eb1aSKeith Busch /* 1263b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1264b2a0eb1aSKeith Busch */ 1265b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1266b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1267b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1268d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1269db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1270b2a0eb1aSKeith Busch } 127157dacad5SJay Sternberg 127231c7c7d2SChristoph Hellwig /* 12737776db1cSKeith Busch * Did we miss an interrupt? 12747776db1cSKeith Busch */ 1275fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 1276fa059b85SKeith Busch nvme_poll(req->mq_hctx); 1277fa059b85SKeith Busch else 1278bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1279fa059b85SKeith Busch 1280bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 12817776db1cSKeith Busch dev_warn(dev->ctrl.device, 12827776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12837776db1cSKeith Busch req->tag, nvmeq->qid); 1284db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12857776db1cSKeith Busch } 12867776db1cSKeith Busch 12877776db1cSKeith Busch /* 1288fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1289fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1290fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1291db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1292fd634f41SChristoph Hellwig */ 12934244140dSKeith Busch switch (dev->ctrl.state) { 12944244140dSKeith Busch case NVME_CTRL_CONNECTING: 12952036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1296df561f66SGustavo A. R. Silva fallthrough; 12972036f726SKeith Busch case NVME_CTRL_DELETING: 1298b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1299fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1300fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 130127fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13027ad92f65STong Zhang nvme_dev_disable(dev, true); 1303db8c48e4SChristoph Hellwig return BLK_EH_DONE; 130439a9dd81SKeith Busch case NVME_CTRL_RESETTING: 130539a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13064244140dSKeith Busch default: 13074244140dSKeith Busch break; 1308fd634f41SChristoph Hellwig } 1309fd634f41SChristoph Hellwig 1310fd634f41SChristoph Hellwig /* 1311e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1312e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1313e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 131431c7c7d2SChristoph Hellwig */ 1315f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13161b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 131757dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 131857dacad5SJay Sternberg req->tag, nvmeq->qid); 13197ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1320a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1321d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1322e1569a16SKeith Busch 1323db8c48e4SChristoph Hellwig return BLK_EH_DONE; 132457dacad5SJay Sternberg } 132557dacad5SJay Sternberg 1326e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1327e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1328e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1329e7a2a87dSChristoph Hellwig } 13307bf7d778SKeith Busch iod->aborted = 1; 133157dacad5SJay Sternberg 133257dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 133357dacad5SJay Sternberg cmd.abort.cid = req->tag; 133457dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 133557dacad5SJay Sternberg 13361b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13371b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 133857dacad5SJay Sternberg req->tag, nvmeq->qid); 1339e7a2a87dSChristoph Hellwig 1340e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 134139dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13426bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13436bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 134431c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 134557dacad5SJay Sternberg } 134657dacad5SJay Sternberg 1347e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 13488eeed0b5SGuoqing Jiang blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio); 134957dacad5SJay Sternberg 135057dacad5SJay Sternberg /* 135157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 135257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 135357dacad5SJay Sternberg * as the device then is in a faulty state. 135457dacad5SJay Sternberg */ 135557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 135657dacad5SJay Sternberg } 135757dacad5SJay Sternberg 135857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 135957dacad5SJay Sternberg { 13608a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 136157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 136263223078SChristoph Hellwig if (!nvmeq->sq_cmds) 136363223078SChristoph Hellwig return; 13640f238ff5SLogan Gunthorpe 136563223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 136688a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 13678a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 136863223078SChristoph Hellwig } else { 13698a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 137063223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13710f238ff5SLogan Gunthorpe } 137257dacad5SJay Sternberg } 137357dacad5SJay Sternberg 137457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 137557dacad5SJay Sternberg { 137657dacad5SJay Sternberg int i; 137757dacad5SJay Sternberg 1378d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1379d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1380147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 138157dacad5SJay Sternberg } 138257dacad5SJay Sternberg } 138357dacad5SJay Sternberg 138457dacad5SJay Sternberg /** 138557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 138640581d1aSBart Van Assche * @nvmeq: queue to suspend 138757dacad5SJay Sternberg */ 138857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 138957dacad5SJay Sternberg { 13904e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 139157dacad5SJay Sternberg return 1; 139257dacad5SJay Sternberg 13934e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1394d1f06f4aSJens Axboe mb(); 139557dacad5SJay Sternberg 13964e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13971c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1398c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13997c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14004e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 140157dacad5SJay Sternberg return 0; 140257dacad5SJay Sternberg } 140357dacad5SJay Sternberg 14048fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14058fae268bSKeith Busch { 14068fae268bSKeith Busch int i; 14078fae268bSKeith Busch 14088fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14098fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14108fae268bSKeith Busch } 14118fae268bSKeith Busch 1412a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 141357dacad5SJay Sternberg { 1414147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 141557dacad5SJay Sternberg 1416a5cdb68cSKeith Busch if (shutdown) 1417a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1418a5cdb68cSKeith Busch else 1419b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 142057dacad5SJay Sternberg 1421bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 142257dacad5SJay Sternberg } 142357dacad5SJay Sternberg 1424fa46c6fbSKeith Busch /* 1425fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14269210c075SDongli Zhang * that can check this device's completion queues have synced, except 14279210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14289210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1429fa46c6fbSKeith Busch */ 1430fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1431fa46c6fbSKeith Busch { 1432fa46c6fbSKeith Busch int i; 1433fa46c6fbSKeith Busch 14349210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14359210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1436324b494cSKeith Busch nvme_process_cq(&dev->queues[i]); 14379210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14389210c075SDongli Zhang } 1439fa46c6fbSKeith Busch } 1440fa46c6fbSKeith Busch 144157dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 144257dacad5SJay Sternberg int entry_size) 144357dacad5SJay Sternberg { 144457dacad5SJay Sternberg int q_depth = dev->q_depth; 14455fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14466c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 144757dacad5SJay Sternberg 144857dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 144957dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14504e523547SBaolin Wang 14516c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 145257dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 145357dacad5SJay Sternberg 145457dacad5SJay Sternberg /* 145557dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 145657dacad5SJay Sternberg * would be better to map queues in system memory with the 145757dacad5SJay Sternberg * original depth 145857dacad5SJay Sternberg */ 145957dacad5SJay Sternberg if (q_depth < 64) 146057dacad5SJay Sternberg return -ENOMEM; 146157dacad5SJay Sternberg } 146257dacad5SJay Sternberg 146357dacad5SJay Sternberg return q_depth; 146457dacad5SJay Sternberg } 146557dacad5SJay Sternberg 146657dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14678a1d09a6SBenjamin Herrenschmidt int qid) 146857dacad5SJay Sternberg { 14690f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1470815c6704SKeith Busch 14710f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14728a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1473bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 14740f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14750f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 147663223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 147763223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 147863223078SChristoph Hellwig return 0; 147963223078SChristoph Hellwig } 1480bfac8e9fSAlan Mikhak 14818a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1482bfac8e9fSAlan Mikhak } 14830f238ff5SLogan Gunthorpe } 14840f238ff5SLogan Gunthorpe 14858a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 148657dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 148757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 148857dacad5SJay Sternberg return -ENOMEM; 148957dacad5SJay Sternberg return 0; 149057dacad5SJay Sternberg } 149157dacad5SJay Sternberg 1492a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 149357dacad5SJay Sternberg { 1494147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 149557dacad5SJay Sternberg 149662314e40SKeith Busch if (dev->ctrl.queue_count > qid) 149762314e40SKeith Busch return 0; 149857dacad5SJay Sternberg 1499c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15008a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15018a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 150257dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 150357dacad5SJay Sternberg if (!nvmeq->cqes) 150457dacad5SJay Sternberg goto free_nvmeq; 150557dacad5SJay Sternberg 15068a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 150757dacad5SJay Sternberg goto free_cqdma; 150857dacad5SJay Sternberg 150957dacad5SJay Sternberg nvmeq->dev = dev; 15101ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15113a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 151257dacad5SJay Sternberg nvmeq->cq_head = 0; 151357dacad5SJay Sternberg nvmeq->cq_phase = 1; 151457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 151557dacad5SJay Sternberg nvmeq->qid = qid; 1516d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 151757dacad5SJay Sternberg 1518147b27e4SSagi Grimberg return 0; 151957dacad5SJay Sternberg 152057dacad5SJay Sternberg free_cqdma: 15218a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 152257dacad5SJay Sternberg nvmeq->cq_dma_addr); 152357dacad5SJay Sternberg free_nvmeq: 1524147b27e4SSagi Grimberg return -ENOMEM; 152557dacad5SJay Sternberg } 152657dacad5SJay Sternberg 1527dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 152857dacad5SJay Sternberg { 15290ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15300ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15310ff199cbSChristoph Hellwig 15320ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15330ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15340ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15350ff199cbSChristoph Hellwig } else { 15360ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15370ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15380ff199cbSChristoph Hellwig } 153957dacad5SJay Sternberg } 154057dacad5SJay Sternberg 154157dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 154257dacad5SJay Sternberg { 154357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154457dacad5SJay Sternberg 154557dacad5SJay Sternberg nvmeq->sq_tail = 0; 154638210800SKeith Busch nvmeq->last_sq_tail = 0; 154757dacad5SJay Sternberg nvmeq->cq_head = 0; 154857dacad5SJay Sternberg nvmeq->cq_phase = 1; 154957dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15508a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1551f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 155257dacad5SJay Sternberg dev->online_queues++; 15533a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 155457dacad5SJay Sternberg } 155557dacad5SJay Sternberg 1556e4b9852aSCasey Chen /* 1557e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1558e4b9852aSCasey Chen */ 1559e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1560e4b9852aSCasey Chen { 1561e4b9852aSCasey Chen /* 1562e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1563e4b9852aSCasey Chen */ 1564e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1565e4b9852aSCasey Chen return -ENODEV; 1566e4b9852aSCasey Chen 1567e4b9852aSCasey Chen /* 1568e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1569e4b9852aSCasey Chen */ 1570e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1571e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1572e4b9852aSCasey Chen return -ENODEV; 1573e4b9852aSCasey Chen } 1574e4b9852aSCasey Chen 1575e4b9852aSCasey Chen return 0; 1576e4b9852aSCasey Chen } 1577e4b9852aSCasey Chen 15784b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 157957dacad5SJay Sternberg { 158057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 158157dacad5SJay Sternberg int result; 15827c349ddeSKeith Busch u16 vector = 0; 158357dacad5SJay Sternberg 1584d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1585d1ed6aa1SChristoph Hellwig 158622b55601SKeith Busch /* 158722b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 158822b55601SKeith Busch * has only one vector available. 158922b55601SKeith Busch */ 15904b04cc6aSJens Axboe if (!polled) 1591a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15924b04cc6aSJens Axboe else 15937c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15944b04cc6aSJens Axboe 1595a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1596ded45505SKeith Busch if (result) 1597ded45505SKeith Busch return result; 159857dacad5SJay Sternberg 159957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 160057dacad5SJay Sternberg if (result < 0) 1601ded45505SKeith Busch return result; 1602c80b36cdSEdmund Nadolski if (result) 160357dacad5SJay Sternberg goto release_cq; 160457dacad5SJay Sternberg 1605a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16064b04cc6aSJens Axboe 1607e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1608e4b9852aSCasey Chen if (result) 1609e4b9852aSCasey Chen return result; 1610e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16117c349ddeSKeith Busch if (!polled) { 1612dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 161357dacad5SJay Sternberg if (result < 0) 161457dacad5SJay Sternberg goto release_sq; 16154b04cc6aSJens Axboe } 161657dacad5SJay Sternberg 16174e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1618e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 161957dacad5SJay Sternberg return result; 162057dacad5SJay Sternberg 162157dacad5SJay Sternberg release_sq: 1622f25a2dfcSJianchao Wang dev->online_queues--; 1623e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 162457dacad5SJay Sternberg adapter_delete_sq(dev, qid); 162557dacad5SJay Sternberg release_cq: 162657dacad5SJay Sternberg adapter_delete_cq(dev, qid); 162757dacad5SJay Sternberg return result; 162857dacad5SJay Sternberg } 162957dacad5SJay Sternberg 1630f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 163157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 163277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 163357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 16340350815aSChristoph Hellwig .init_request = nvme_init_request, 163557dacad5SJay Sternberg .timeout = nvme_timeout, 163657dacad5SJay Sternberg }; 163757dacad5SJay Sternberg 1638f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1639376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1640376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1641376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1642376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1643376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1644376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1645376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1646c6d962aeSChristoph Hellwig .poll = nvme_poll, 1647dabcefabSJens Axboe }; 1648dabcefabSJens Axboe 164957dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 165057dacad5SJay Sternberg { 16511c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 165269d9a99cSKeith Busch /* 165369d9a99cSKeith Busch * If the controller was reset during removal, it's possible 165469d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 165569d9a99cSKeith Busch * queue to flush these to completion. 165669d9a99cSKeith Busch */ 1657c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16581c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 165957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 166057dacad5SJay Sternberg } 166157dacad5SJay Sternberg } 166257dacad5SJay Sternberg 166357dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 166457dacad5SJay Sternberg { 16651c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 166657dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 166757dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1668e3e9d50cSKeith Busch 166938dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1670dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1671d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1672d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1673d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 167457dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 167557dacad5SJay Sternberg 167657dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 167757dacad5SJay Sternberg return -ENOMEM; 167834b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 167957dacad5SJay Sternberg 16801c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16811c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 168257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 168357dacad5SJay Sternberg return -ENOMEM; 168457dacad5SJay Sternberg } 16851c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 168657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16871c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 168857dacad5SJay Sternberg return -ENODEV; 168957dacad5SJay Sternberg } 169057dacad5SJay Sternberg } else 1691c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 169257dacad5SJay Sternberg 169357dacad5SJay Sternberg return 0; 169457dacad5SJay Sternberg } 169557dacad5SJay Sternberg 169697f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 169797f6ef64SXu Yu { 169897f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 169997f6ef64SXu Yu } 170097f6ef64SXu Yu 170197f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 170297f6ef64SXu Yu { 170397f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 170497f6ef64SXu Yu 170597f6ef64SXu Yu if (size <= dev->bar_mapped_size) 170697f6ef64SXu Yu return 0; 170797f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 170897f6ef64SXu Yu return -ENOMEM; 170997f6ef64SXu Yu if (dev->bar) 171097f6ef64SXu Yu iounmap(dev->bar); 171197f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 171297f6ef64SXu Yu if (!dev->bar) { 171397f6ef64SXu Yu dev->bar_mapped_size = 0; 171497f6ef64SXu Yu return -ENOMEM; 171597f6ef64SXu Yu } 171697f6ef64SXu Yu dev->bar_mapped_size = size; 171797f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 171897f6ef64SXu Yu 171997f6ef64SXu Yu return 0; 172097f6ef64SXu Yu } 172197f6ef64SXu Yu 172201ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 172357dacad5SJay Sternberg { 172457dacad5SJay Sternberg int result; 172557dacad5SJay Sternberg u32 aqa; 172657dacad5SJay Sternberg struct nvme_queue *nvmeq; 172757dacad5SJay Sternberg 172897f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 172997f6ef64SXu Yu if (result < 0) 173097f6ef64SXu Yu return result; 173197f6ef64SXu Yu 17328ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 173320d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 173457dacad5SJay Sternberg 17357a67cbeaSChristoph Hellwig if (dev->subsystem && 17367a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17377a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 173857dacad5SJay Sternberg 1739b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 174057dacad5SJay Sternberg if (result < 0) 174157dacad5SJay Sternberg return result; 174257dacad5SJay Sternberg 1743a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1744147b27e4SSagi Grimberg if (result) 1745147b27e4SSagi Grimberg return result; 174657dacad5SJay Sternberg 1747635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1748635333e4SMax Gurtovoy 1749147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 175057dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 175157dacad5SJay Sternberg aqa |= aqa << 16; 175257dacad5SJay Sternberg 17537a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17547a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17557a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 175657dacad5SJay Sternberg 1757c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 175857dacad5SJay Sternberg if (result) 1759d4875622SKeith Busch return result; 176057dacad5SJay Sternberg 176157dacad5SJay Sternberg nvmeq->cq_vector = 0; 1762161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1763dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 176457dacad5SJay Sternberg if (result) { 17657c349ddeSKeith Busch dev->online_queues--; 1766d4875622SKeith Busch return result; 176757dacad5SJay Sternberg } 176857dacad5SJay Sternberg 17694e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 177057dacad5SJay Sternberg return result; 177157dacad5SJay Sternberg } 177257dacad5SJay Sternberg 1773749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 177457dacad5SJay Sternberg { 17754b04cc6aSJens Axboe unsigned i, max, rw_queues; 1776749941f2SChristoph Hellwig int ret = 0; 177757dacad5SJay Sternberg 1778d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1779a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1780749941f2SChristoph Hellwig ret = -ENOMEM; 178157dacad5SJay Sternberg break; 1782749941f2SChristoph Hellwig } 1783749941f2SChristoph Hellwig } 178457dacad5SJay Sternberg 1785d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1786e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1787e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1788e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17894b04cc6aSJens Axboe } else { 17904b04cc6aSJens Axboe rw_queues = max; 17914b04cc6aSJens Axboe } 17924b04cc6aSJens Axboe 1793949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17944b04cc6aSJens Axboe bool polled = i > rw_queues; 17954b04cc6aSJens Axboe 17964b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1797d4875622SKeith Busch if (ret) 179857dacad5SJay Sternberg break; 179957dacad5SJay Sternberg } 180057dacad5SJay Sternberg 1801749941f2SChristoph Hellwig /* 1802749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18038adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18048adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1805749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1806749941f2SChristoph Hellwig */ 1807749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 180857dacad5SJay Sternberg } 180957dacad5SJay Sternberg 181088de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 181157dacad5SJay Sternberg { 181288de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 181388de4598SChristoph Hellwig 181488de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 181588de4598SChristoph Hellwig } 181688de4598SChristoph Hellwig 181788de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 181888de4598SChristoph Hellwig { 181988de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 182088de4598SChristoph Hellwig } 182188de4598SChristoph Hellwig 1822f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 182357dacad5SJay Sternberg { 182488de4598SChristoph Hellwig u64 size, offset; 182557dacad5SJay Sternberg resource_size_t bar_size; 182657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18278969f1f8SChristoph Hellwig int bar; 182857dacad5SJay Sternberg 18299fe5c59fSKeith Busch if (dev->cmb_size) 18309fe5c59fSKeith Busch return; 18319fe5c59fSKeith Busch 183220d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 183320d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 183420d3bb92SKlaus Jensen 18357a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1836f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1837f65efd6dSChristoph Hellwig return; 1838202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 183957dacad5SJay Sternberg 184088de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 184188de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18428969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18438969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 184457dacad5SJay Sternberg 184557dacad5SJay Sternberg if (offset > bar_size) 1846f65efd6dSChristoph Hellwig return; 184757dacad5SJay Sternberg 184857dacad5SJay Sternberg /* 184920d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 185020d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 185120d3bb92SKlaus Jensen */ 185220d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 185320d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 185420d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 185520d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 185620d3bb92SKlaus Jensen } 185720d3bb92SKlaus Jensen 185820d3bb92SKlaus Jensen /* 185957dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 186057dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 186157dacad5SJay Sternberg * the reported size of the BAR 186257dacad5SJay Sternberg */ 186357dacad5SJay Sternberg if (size > bar_size - offset) 186457dacad5SJay Sternberg size = bar_size - offset; 186557dacad5SJay Sternberg 18660f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18670f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18680f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1869f65efd6dSChristoph Hellwig return; 18700f238ff5SLogan Gunthorpe } 18710f238ff5SLogan Gunthorpe 187257dacad5SJay Sternberg dev->cmb_size = size; 18730f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18740f238ff5SLogan Gunthorpe 18750f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18760f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18770f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 187857dacad5SJay Sternberg } 187957dacad5SJay Sternberg 188087ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 188157dacad5SJay Sternberg { 18826c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18834033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1884f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 188587ad72a5SChristoph Hellwig int ret; 188687ad72a5SChristoph Hellwig 188787ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 188887ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 188987ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 18906c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 189187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 189287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 189387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 189487ad72a5SChristoph Hellwig 189587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 189687ad72a5SChristoph Hellwig if (ret) { 189787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 189887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 189987ad72a5SChristoph Hellwig ret, bits); 1900a5df5e79SKeith Busch } else 1901a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1902a5df5e79SKeith Busch 190387ad72a5SChristoph Hellwig return ret; 190487ad72a5SChristoph Hellwig } 190587ad72a5SChristoph Hellwig 190687ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 190787ad72a5SChristoph Hellwig { 190887ad72a5SChristoph Hellwig int i; 190987ad72a5SChristoph Hellwig 191087ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 191187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19126c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 191387ad72a5SChristoph Hellwig 1914cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1915cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1916cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191787ad72a5SChristoph Hellwig } 191887ad72a5SChristoph Hellwig 191987ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 192087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19214033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19224033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19234033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 192487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19257e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 192687ad72a5SChristoph Hellwig } 192787ad72a5SChristoph Hellwig 192892dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 192992dc6895SChristoph Hellwig u32 chunk_size) 193087ad72a5SChristoph Hellwig { 193187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 193292dc6895SChristoph Hellwig u32 max_entries, len; 19334033f35dSChristoph Hellwig dma_addr_t descs_dma; 19342ee0e4edSDan Carpenter int i = 0; 193587ad72a5SChristoph Hellwig void **bufs; 19366fbcde66SMinwoo Im u64 size, tmp; 193787ad72a5SChristoph Hellwig 193887ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 193987ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 194087ad72a5SChristoph Hellwig max_entries = tmp; 1941044a9df1SChristoph Hellwig 1942044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1943044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1944044a9df1SChristoph Hellwig 1945750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19464033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 194787ad72a5SChristoph Hellwig if (!descs) 194887ad72a5SChristoph Hellwig goto out; 194987ad72a5SChristoph Hellwig 195087ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 195187ad72a5SChristoph Hellwig if (!bufs) 195287ad72a5SChristoph Hellwig goto out_free_descs; 195387ad72a5SChristoph Hellwig 1954244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 195587ad72a5SChristoph Hellwig dma_addr_t dma_addr; 195687ad72a5SChristoph Hellwig 195750cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 195887ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 195987ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 196087ad72a5SChristoph Hellwig if (!bufs[i]) 196187ad72a5SChristoph Hellwig break; 196287ad72a5SChristoph Hellwig 196387ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19646c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 196587ad72a5SChristoph Hellwig i++; 196687ad72a5SChristoph Hellwig } 196787ad72a5SChristoph Hellwig 196892dc6895SChristoph Hellwig if (!size) 196987ad72a5SChristoph Hellwig goto out_free_bufs; 197087ad72a5SChristoph Hellwig 197187ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 197287ad72a5SChristoph Hellwig dev->host_mem_size = size; 197387ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19744033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 197587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 197687ad72a5SChristoph Hellwig return 0; 197787ad72a5SChristoph Hellwig 197887ad72a5SChristoph Hellwig out_free_bufs: 197987ad72a5SChristoph Hellwig while (--i >= 0) { 19806c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 198187ad72a5SChristoph Hellwig 1982cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1983cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1984cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 198587ad72a5SChristoph Hellwig } 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig kfree(bufs); 198887ad72a5SChristoph Hellwig out_free_descs: 19894033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19904033f35dSChristoph Hellwig descs_dma); 199187ad72a5SChristoph Hellwig out: 199287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 199387ad72a5SChristoph Hellwig return -ENOMEM; 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199692dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 199792dc6895SChristoph Hellwig { 19989dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 19999dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20009dc54a0dSChaitanya Kulkarni u64 chunk_size; 200192dc6895SChristoph Hellwig 200292dc6895SChristoph Hellwig /* start big and work our way down */ 20039dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 200492dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 200592dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 200692dc6895SChristoph Hellwig return 0; 200792dc6895SChristoph Hellwig nvme_free_host_mem(dev); 200892dc6895SChristoph Hellwig } 200992dc6895SChristoph Hellwig } 201092dc6895SChristoph Hellwig 201192dc6895SChristoph Hellwig return -ENOMEM; 201292dc6895SChristoph Hellwig } 201392dc6895SChristoph Hellwig 20149620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 201587ad72a5SChristoph Hellwig { 201687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 201787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 201887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 201987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20206fbcde66SMinwoo Im int ret; 202187ad72a5SChristoph Hellwig 202287ad72a5SChristoph Hellwig preferred = min(preferred, max); 202387ad72a5SChristoph Hellwig if (min > max) { 202487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 202587ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 202687ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 202787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20289620cfbaSChristoph Hellwig return 0; 202987ad72a5SChristoph Hellwig } 203087ad72a5SChristoph Hellwig 203187ad72a5SChristoph Hellwig /* 203287ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 203387ad72a5SChristoph Hellwig */ 203487ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 203587ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 203687ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 203787ad72a5SChristoph Hellwig else 203887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 203987ad72a5SChristoph Hellwig } 204087ad72a5SChristoph Hellwig 204187ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 204292dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 204392dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 204492dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20459620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 204687ad72a5SChristoph Hellwig } 204787ad72a5SChristoph Hellwig 204892dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 204992dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 205092dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 205192dc6895SChristoph Hellwig } 205292dc6895SChristoph Hellwig 20539620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20549620cfbaSChristoph Hellwig if (ret) 205587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20569620cfbaSChristoph Hellwig return ret; 205757dacad5SJay Sternberg } 205857dacad5SJay Sternberg 20590521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 20600521905eSKeith Busch char *buf) 20610521905eSKeith Busch { 20620521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20630521905eSKeith Busch 20640521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 20650521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 20660521905eSKeith Busch } 20670521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 20680521905eSKeith Busch 20691751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 20701751e97aSKeith Busch char *buf) 20711751e97aSKeith Busch { 20721751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20731751e97aSKeith Busch 20741751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 20751751e97aSKeith Busch } 20761751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 20771751e97aSKeith Busch 20781751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 20791751e97aSKeith Busch char *buf) 20801751e97aSKeith Busch { 20811751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20821751e97aSKeith Busch 20831751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 20841751e97aSKeith Busch } 20851751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 20861751e97aSKeith Busch 2087a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2088a5df5e79SKeith Busch char *buf) 2089a5df5e79SKeith Busch { 2090a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2091a5df5e79SKeith Busch 2092a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2093a5df5e79SKeith Busch } 2094a5df5e79SKeith Busch 2095a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2096a5df5e79SKeith Busch const char *buf, size_t count) 2097a5df5e79SKeith Busch { 2098a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2099a5df5e79SKeith Busch bool new; 2100a5df5e79SKeith Busch int ret; 2101a5df5e79SKeith Busch 2102a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2103a5df5e79SKeith Busch return -EINVAL; 2104a5df5e79SKeith Busch 2105a5df5e79SKeith Busch if (new == ndev->hmb) 2106a5df5e79SKeith Busch return count; 2107a5df5e79SKeith Busch 2108a5df5e79SKeith Busch if (new) { 2109a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2110a5df5e79SKeith Busch } else { 2111a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2112a5df5e79SKeith Busch if (!ret) 2113a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2114a5df5e79SKeith Busch } 2115a5df5e79SKeith Busch 2116a5df5e79SKeith Busch if (ret < 0) 2117a5df5e79SKeith Busch return ret; 2118a5df5e79SKeith Busch 2119a5df5e79SKeith Busch return count; 2120a5df5e79SKeith Busch } 2121a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2122a5df5e79SKeith Busch 21230521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 21240521905eSKeith Busch struct attribute *a, int n) 21250521905eSKeith Busch { 21260521905eSKeith Busch struct nvme_ctrl *ctrl = 21270521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 21280521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 21290521905eSKeith Busch 21301751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 21311751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 21321751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 21331751e97aSKeith Busch if (!dev->cmbsz) 21340521905eSKeith Busch return 0; 21351751e97aSKeith Busch } 2136a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2137a5df5e79SKeith Busch return 0; 2138a5df5e79SKeith Busch 21390521905eSKeith Busch return a->mode; 21400521905eSKeith Busch } 21410521905eSKeith Busch 21420521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 21430521905eSKeith Busch &dev_attr_cmb.attr, 21441751e97aSKeith Busch &dev_attr_cmbloc.attr, 21451751e97aSKeith Busch &dev_attr_cmbsz.attr, 2146a5df5e79SKeith Busch &dev_attr_hmb.attr, 21470521905eSKeith Busch NULL, 21480521905eSKeith Busch }; 21490521905eSKeith Busch 21500521905eSKeith Busch static const struct attribute_group nvme_pci_attr_group = { 21510521905eSKeith Busch .attrs = nvme_pci_attrs, 21520521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 21530521905eSKeith Busch }; 21540521905eSKeith Busch 2155612b7286SMing Lei /* 2156612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2157612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2158612b7286SMing Lei */ 2159612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 21603b6592f7SJens Axboe { 2161612b7286SMing Lei struct nvme_dev *dev = affd->priv; 21622a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2163c45b1fa2SMing Lei 21643b6592f7SJens Axboe /* 2165ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2166612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2167612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2168612b7286SMing Lei * 2169612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2170612b7286SMing Lei * write and read queues. 2171612b7286SMing Lei * 2172612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2173612b7286SMing Lei * queue. 21743b6592f7SJens Axboe */ 2175612b7286SMing Lei if (!nrirqs) { 2176612b7286SMing Lei nrirqs = 1; 2177612b7286SMing Lei nr_read_queues = 0; 21782a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2179612b7286SMing Lei nr_read_queues = 0; 21802a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2181612b7286SMing Lei nr_read_queues = 1; 21823b6592f7SJens Axboe } else { 21832a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 21843b6592f7SJens Axboe } 2185612b7286SMing Lei 2186612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2187612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2188612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2189612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2190612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 21913b6592f7SJens Axboe } 21923b6592f7SJens Axboe 21936451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 21943b6592f7SJens Axboe { 21953b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 21963b6592f7SJens Axboe struct irq_affinity affd = { 21973b6592f7SJens Axboe .pre_vectors = 1, 2198612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2199612b7286SMing Lei .priv = dev, 22003b6592f7SJens Axboe }; 220121cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22026451fe73SJens Axboe 22036451fe73SJens Axboe /* 220421cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 220521cc2f3fSJeffle Xu * left over for non-polled I/O. 22066451fe73SJens Axboe */ 220721cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 220821cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22093b6592f7SJens Axboe 221021cc2f3fSJeffle Xu /* 221121cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 221221cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 221321cc2f3fSJeffle Xu */ 2214612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2215612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 22163b6592f7SJens Axboe 221766341331SBenjamin Herrenschmidt /* 221821cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 221921cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 222021cc2f3fSJeffle Xu * vector. 222166341331SBenjamin Herrenschmidt */ 222266341331SBenjamin Herrenschmidt irq_queues = 1; 222321cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 222421cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2225612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 22263b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 22273b6592f7SJens Axboe } 22283b6592f7SJens Axboe 22298fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 22308fae268bSKeith Busch { 22318fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 22328fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 22338fae268bSKeith Busch } 22348fae268bSKeith Busch 22352a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 22362a5bcfddSWeiping Zhang { 2237e3aef095SNiklas Schnelle /* 2238e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2239e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2240e3aef095SNiklas Schnelle */ 2241e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2242e3aef095SNiklas Schnelle return 1; 22432a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 22442a5bcfddSWeiping Zhang } 22452a5bcfddSWeiping Zhang 224657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 224757dacad5SJay Sternberg { 2248147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 224957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 22502a5bcfddSWeiping Zhang unsigned int nr_io_queues; 225197f6ef64SXu Yu unsigned long size; 22522a5bcfddSWeiping Zhang int result; 225357dacad5SJay Sternberg 22542a5bcfddSWeiping Zhang /* 22552a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 22562a5bcfddSWeiping Zhang * stable values to work with. 22572a5bcfddSWeiping Zhang */ 22582a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 22592a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2260d38e9f04SBenjamin Herrenschmidt 2261ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 22629a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 22639a0be7abSChristoph Hellwig if (result < 0) 226457dacad5SJay Sternberg return result; 22659a0be7abSChristoph Hellwig 2266f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2267a5229050SKeith Busch return 0; 226857dacad5SJay Sternberg 2269e4b9852aSCasey Chen /* 2270e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2271e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2272e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2273e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2274e4b9852aSCasey Chen * nvme_dev_disable() path. 2275e4b9852aSCasey Chen */ 2276e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2277e4b9852aSCasey Chen if (result) 2278e4b9852aSCasey Chen return result; 2279e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2280e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 22814e224106SChristoph Hellwig 22820f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 228357dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 228457dacad5SJay Sternberg sizeof(struct nvme_command)); 228557dacad5SJay Sternberg if (result > 0) 228657dacad5SJay Sternberg dev->q_depth = result; 228757dacad5SJay Sternberg else 22880f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 228957dacad5SJay Sternberg } 229057dacad5SJay Sternberg 229157dacad5SJay Sternberg do { 229297f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 229397f6ef64SXu Yu result = nvme_remap_bar(dev, size); 229497f6ef64SXu Yu if (!result) 229557dacad5SJay Sternberg break; 2296e4b9852aSCasey Chen if (!--nr_io_queues) { 2297e4b9852aSCasey Chen result = -ENOMEM; 2298e4b9852aSCasey Chen goto out_unlock; 2299e4b9852aSCasey Chen } 230057dacad5SJay Sternberg } while (1); 230157dacad5SJay Sternberg adminq->q_db = dev->dbs; 230257dacad5SJay Sternberg 23038fae268bSKeith Busch retry: 230457dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2305e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23060ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 230757dacad5SJay Sternberg 230857dacad5SJay Sternberg /* 230957dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 231057dacad5SJay Sternberg * setting up the full range we need. 231157dacad5SJay Sternberg */ 2312dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 23133b6592f7SJens Axboe 23143b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2315e4b9852aSCasey Chen if (result <= 0) { 2316e4b9852aSCasey Chen result = -EIO; 2317e4b9852aSCasey Chen goto out_unlock; 2318e4b9852aSCasey Chen } 23193b6592f7SJens Axboe 232022b55601SKeith Busch dev->num_vecs = result; 23214b04cc6aSJens Axboe result = max(result - 1, 1); 2322e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 232357dacad5SJay Sternberg 232457dacad5SJay Sternberg /* 232557dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 232657dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 232757dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 232857dacad5SJay Sternberg * number of interrupts. 232957dacad5SJay Sternberg */ 2330dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 23317c349ddeSKeith Busch if (result) 2332e4b9852aSCasey Chen goto out_unlock; 23334e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2334e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 23358fae268bSKeith Busch 23368fae268bSKeith Busch result = nvme_create_io_queues(dev); 23378fae268bSKeith Busch if (result || dev->online_queues < 2) 23388fae268bSKeith Busch return result; 23398fae268bSKeith Busch 23408fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 23418fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 23428fae268bSKeith Busch nvme_disable_io_queues(dev); 2343e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2344e4b9852aSCasey Chen if (result) 2345e4b9852aSCasey Chen return result; 23468fae268bSKeith Busch nvme_suspend_io_queues(dev); 23478fae268bSKeith Busch goto retry; 23488fae268bSKeith Busch } 23498fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 23508fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 23518fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 23528fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 23538fae268bSKeith Busch return 0; 2354e4b9852aSCasey Chen out_unlock: 2355e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2356e4b9852aSCasey Chen return result; 235757dacad5SJay Sternberg } 235857dacad5SJay Sternberg 23592a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2360db3cbfffSKeith Busch { 2361db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2362db3cbfffSKeith Busch 2363db3cbfffSKeith Busch blk_mq_free_request(req); 2364d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2365db3cbfffSKeith Busch } 2366db3cbfffSKeith Busch 23672a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2368db3cbfffSKeith Busch { 2369db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2370db3cbfffSKeith Busch 2371d1ed6aa1SChristoph Hellwig if (error) 2372d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2373db3cbfffSKeith Busch 2374db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2375db3cbfffSKeith Busch } 2376db3cbfffSKeith Busch 2377db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2378db3cbfffSKeith Busch { 2379db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2380db3cbfffSKeith Busch struct request *req; 2381f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2382db3cbfffSKeith Busch 2383db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2384db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2385db3cbfffSKeith Busch 238639dfe844SChaitanya Kulkarni req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT); 2387db3cbfffSKeith Busch if (IS_ERR(req)) 2388db3cbfffSKeith Busch return PTR_ERR(req); 2389db3cbfffSKeith Busch 2390db3cbfffSKeith Busch req->end_io_data = nvmeq; 2391db3cbfffSKeith Busch 2392d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 23938eeed0b5SGuoqing Jiang blk_execute_rq_nowait(NULL, req, false, 2394db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2395db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2396db3cbfffSKeith Busch return 0; 2397db3cbfffSKeith Busch } 2398db3cbfffSKeith Busch 23998fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2400db3cbfffSKeith Busch { 24015271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2402db3cbfffSKeith Busch unsigned long timeout; 2403db3cbfffSKeith Busch 2404db3cbfffSKeith Busch retry: 2405dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24065271edd4SChristoph Hellwig while (nr_queues > 0) { 24075271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2408db3cbfffSKeith Busch break; 24095271edd4SChristoph Hellwig nr_queues--; 24105271edd4SChristoph Hellwig sent++; 24115271edd4SChristoph Hellwig } 2412d1ed6aa1SChristoph Hellwig while (sent) { 2413d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2414d1ed6aa1SChristoph Hellwig 2415d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 24165271edd4SChristoph Hellwig timeout); 2417db3cbfffSKeith Busch if (timeout == 0) 24185271edd4SChristoph Hellwig return false; 2419d1ed6aa1SChristoph Hellwig 2420d1ed6aa1SChristoph Hellwig sent--; 24215271edd4SChristoph Hellwig if (nr_queues) 2422db3cbfffSKeith Busch goto retry; 2423db3cbfffSKeith Busch } 24245271edd4SChristoph Hellwig return true; 2425db3cbfffSKeith Busch } 2426db3cbfffSKeith Busch 24275d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 242857dacad5SJay Sternberg { 24292b1b7e78SJianchao Wang int ret; 24302b1b7e78SJianchao Wang 24315bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2432c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 243357dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 24348fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2435ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2436ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 243757dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2438d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 243961f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 244061f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2441d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 244257dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 244357dacad5SJay Sternberg dev->tagset.driver_data = dev; 244457dacad5SJay Sternberg 2445d38e9f04SBenjamin Herrenschmidt /* 2446d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2447d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2448d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2449d38e9f04SBenjamin Herrenschmidt */ 2450d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2451d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2452d38e9f04SBenjamin Herrenschmidt 24532b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 24542b1b7e78SJianchao Wang if (ret) { 24552b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 24562b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 24575d02a5c1SKeith Busch return; 24582b1b7e78SJianchao Wang } 24595bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2460949928c1SKeith Busch } else { 2461949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2462949928c1SKeith Busch 2463949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2464949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 246557dacad5SJay Sternberg } 2466949928c1SKeith Busch 2467e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 246857dacad5SJay Sternberg } 246957dacad5SJay Sternberg 2470b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 247157dacad5SJay Sternberg { 2472b00a726aSKeith Busch int result = -ENOMEM; 247357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 24744bdf2603SFilippo Sironi int dma_address_bits = 64; 247557dacad5SJay Sternberg 247657dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 247757dacad5SJay Sternberg return result; 247857dacad5SJay Sternberg 247957dacad5SJay Sternberg pci_set_master(pdev); 248057dacad5SJay Sternberg 24814bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 24824bdf2603SFilippo Sironi dma_address_bits = 48; 24834bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 248457dacad5SJay Sternberg goto disable; 248557dacad5SJay Sternberg 24867a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 248757dacad5SJay Sternberg result = -ENODEV; 2488b00a726aSKeith Busch goto disable; 248957dacad5SJay Sternberg } 249057dacad5SJay Sternberg 249157dacad5SJay Sternberg /* 2492a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2493a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2494a5229050SKeith Busch * adjust this later. 249557dacad5SJay Sternberg */ 2496dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2497dca51e78SChristoph Hellwig if (result < 0) 2498dca51e78SChristoph Hellwig return result; 249957dacad5SJay Sternberg 250020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25017a67cbeaSChristoph Hellwig 25027442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2503b27c1e68Sweiping zhang io_queue_depth); 2504aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 250520d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 25067a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 25071f390c1fSStephan Günther 25081f390c1fSStephan Günther /* 250966341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 251066341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 251166341331SBenjamin Herrenschmidt * so we don't bother updating it here. 251266341331SBenjamin Herrenschmidt */ 251366341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 251466341331SBenjamin Herrenschmidt dev->io_sqes = 7; 251566341331SBenjamin Herrenschmidt else 2516c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 25171f390c1fSStephan Günther 25181f390c1fSStephan Günther /* 25191f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 25201f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 25211f390c1fSStephan Günther */ 25221f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 25231f390c1fSStephan Günther dev->q_depth = 2; 25249bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 25259bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 25261f390c1fSStephan Günther dev->q_depth); 2527d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2528d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 252920d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2530d554b5e1SMartin K. Petersen dev->q_depth = 64; 2531d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2532d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 25331f390c1fSStephan Günther } 25341f390c1fSStephan Günther 2535d38e9f04SBenjamin Herrenschmidt /* 2536d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2537d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2538d38e9f04SBenjamin Herrenschmidt */ 2539d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2540d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2541d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2542d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2543d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2544d38e9f04SBenjamin Herrenschmidt } 2545d38e9f04SBenjamin Herrenschmidt 2546d38e9f04SBenjamin Herrenschmidt 2547f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2548202021c1SStephen Bates 2549a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2550a0a3408eSKeith Busch pci_save_state(pdev); 255157dacad5SJay Sternberg return 0; 255257dacad5SJay Sternberg 255357dacad5SJay Sternberg disable: 255457dacad5SJay Sternberg pci_disable_device(pdev); 255557dacad5SJay Sternberg return result; 255657dacad5SJay Sternberg } 255757dacad5SJay Sternberg 255857dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 255957dacad5SJay Sternberg { 2560b00a726aSKeith Busch if (dev->bar) 2561b00a726aSKeith Busch iounmap(dev->bar); 2562a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2563b00a726aSKeith Busch } 2564b00a726aSKeith Busch 2565b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2566b00a726aSKeith Busch { 256757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 256857dacad5SJay Sternberg 2569dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 257057dacad5SJay Sternberg 2571a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2572a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 257357dacad5SJay Sternberg pci_disable_device(pdev); 257457dacad5SJay Sternberg } 2575a0a3408eSKeith Busch } 257657dacad5SJay Sternberg 2577a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 257857dacad5SJay Sternberg { 2579e43269e6SKeith Busch bool dead = true, freeze = false; 2580302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 258157dacad5SJay Sternberg 258277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2583302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2584302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2585302ad8ccSKeith Busch 2586ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2587e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2588e43269e6SKeith Busch freeze = true; 2589302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2590e43269e6SKeith Busch } 2591302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2592302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 259357dacad5SJay Sternberg } 2594c21377f8SGabriel Krisman Bertazi 2595302ad8ccSKeith Busch /* 2596302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2597302ad8ccSKeith Busch * doing a safe shutdown. 2598302ad8ccSKeith Busch */ 2599e43269e6SKeith Busch if (!dead && shutdown && freeze) 2600302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 260187ad72a5SChristoph Hellwig 26029a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 26039a915a5bSJianchao Wang 260464ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 26058fae268bSKeith Busch nvme_disable_io_queues(dev); 2606a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 260757dacad5SJay Sternberg } 26088fae268bSKeith Busch nvme_suspend_io_queues(dev); 26098fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2610b00a726aSKeith Busch nvme_pci_disable(dev); 2611fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 261257dacad5SJay Sternberg 2613e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2614e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2615622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2616622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2617302ad8ccSKeith Busch 2618302ad8ccSKeith Busch /* 2619302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2620302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2621302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2622302ad8ccSKeith Busch */ 2623c8e9e9b7SKeith Busch if (shutdown) { 2624302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2625c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2626c8e9e9b7SKeith Busch blk_mq_unquiesce_queue(dev->ctrl.admin_q); 2627c8e9e9b7SKeith Busch } 262877bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 262957dacad5SJay Sternberg } 263057dacad5SJay Sternberg 2631c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2632c1ac9a4bSKeith Busch { 2633c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2634c1ac9a4bSKeith Busch return -EBUSY; 2635c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2636c1ac9a4bSKeith Busch return 0; 2637c1ac9a4bSKeith Busch } 2638c1ac9a4bSKeith Busch 263957dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 264057dacad5SJay Sternberg { 264157dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2642c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2643c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 264457dacad5SJay Sternberg if (!dev->prp_page_pool) 264557dacad5SJay Sternberg return -ENOMEM; 264657dacad5SJay Sternberg 264757dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 264857dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 264957dacad5SJay Sternberg 256, 256, 0); 265057dacad5SJay Sternberg if (!dev->prp_small_pool) { 265157dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 265257dacad5SJay Sternberg return -ENOMEM; 265357dacad5SJay Sternberg } 265457dacad5SJay Sternberg return 0; 265557dacad5SJay Sternberg } 265657dacad5SJay Sternberg 265757dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 265857dacad5SJay Sternberg { 265957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 266057dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 266157dacad5SJay Sternberg } 266257dacad5SJay Sternberg 2663770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2664770597ecSKeith Busch { 2665770597ecSKeith Busch if (dev->tagset.tags) 2666770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2667770597ecSKeith Busch dev->ctrl.tagset = NULL; 2668770597ecSKeith Busch } 2669770597ecSKeith Busch 26701673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 267157dacad5SJay Sternberg { 26721673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 267357dacad5SJay Sternberg 2674f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2675770597ecSKeith Busch nvme_free_tagset(dev); 26761c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 26771c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2678e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2679943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2680253fd4acSIsrael Rukshin put_device(dev->dev); 2681253fd4acSIsrael Rukshin kfree(dev->queues); 268257dacad5SJay Sternberg kfree(dev); 268357dacad5SJay Sternberg } 268457dacad5SJay Sternberg 26857c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2686f58944e2SKeith Busch { 2687c1ac9a4bSKeith Busch /* 2688c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2689c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2690c1ac9a4bSKeith Busch */ 2691c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2692d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 269369d9a99cSKeith Busch nvme_dev_disable(dev, false); 26949f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 269503e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2696f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2697f58944e2SKeith Busch } 2698f58944e2SKeith Busch 2699fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 270057dacad5SJay Sternberg { 2701d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2702d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2703a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2704e71afda4SChaitanya Kulkarni int result; 270557dacad5SJay Sternberg 27067764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 27077764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 27087764656bSZhihao Cheng dev->ctrl.state); 2709e71afda4SChaitanya Kulkarni result = -ENODEV; 2710fd634f41SChristoph Hellwig goto out; 2711e71afda4SChaitanya Kulkarni } 2712fd634f41SChristoph Hellwig 2713fd634f41SChristoph Hellwig /* 2714fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2715fd634f41SChristoph Hellwig * moving on. 2716fd634f41SChristoph Hellwig */ 2717b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2718a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2719d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2720fd634f41SChristoph Hellwig 27215c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2722b00a726aSKeith Busch result = nvme_pci_enable(dev); 272357dacad5SJay Sternberg if (result) 27244726bcf3SKeith Busch goto out_unlock; 272557dacad5SJay Sternberg 272601ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 272757dacad5SJay Sternberg if (result) 27284726bcf3SKeith Busch goto out_unlock; 272957dacad5SJay Sternberg 273057dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 273157dacad5SJay Sternberg if (result) 27324726bcf3SKeith Busch goto out_unlock; 273357dacad5SJay Sternberg 2734943e942eSJens Axboe /* 2735943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2736943e942eSJens Axboe * over a single page. 2737943e942eSJens Axboe */ 27387637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 27397637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2740943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2741a48bc520SChristoph Hellwig 2742a48bc520SChristoph Hellwig /* 2743a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2744a48bc520SChristoph Hellwig */ 2745a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 27463d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2747a48bc520SChristoph Hellwig 27485c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 27495c959d73SKeith Busch 27505c959d73SKeith Busch /* 27515c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 27525c959d73SKeith Busch * initializing procedure here. 27535c959d73SKeith Busch */ 27545c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 27555c959d73SKeith Busch dev_warn(dev->ctrl.device, 27565c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2757cee6c269SMinwoo Im result = -EBUSY; 27585c959d73SKeith Busch goto out; 27595c959d73SKeith Busch } 2760943e942eSJens Axboe 276195093350SMax Gurtovoy /* 276295093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 276395093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 276495093350SMax Gurtovoy */ 276595093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 276695093350SMax Gurtovoy 2767f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2768ce4541f4SChristoph Hellwig if (result) 2769f58944e2SKeith Busch goto out; 2770ce4541f4SChristoph Hellwig 2771e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2772e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 27734f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 27744f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2775e286bcfcSScott Bauer else if (was_suspend) 27764f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2777e286bcfcSScott Bauer } else { 2778e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2779e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2780e286bcfcSScott Bauer } 2781a98e58e5SScott Bauer 2782f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2783f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2784f9f38e33SHelen Koike if (result) 2785f9f38e33SHelen Koike dev_warn(dev->dev, 2786f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2787f9f38e33SHelen Koike } 2788f9f38e33SHelen Koike 27899620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 27909620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 27919620cfbaSChristoph Hellwig if (result < 0) 27929620cfbaSChristoph Hellwig goto out; 27939620cfbaSChristoph Hellwig } 279487ad72a5SChristoph Hellwig 279557dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 279657dacad5SJay Sternberg if (result) 2797f58944e2SKeith Busch goto out; 279857dacad5SJay Sternberg 279921f033f7SKeith Busch /* 280057dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 280157dacad5SJay Sternberg * any working I/O queue. 280257dacad5SJay Sternberg */ 280357dacad5SJay Sternberg if (dev->online_queues < 2) { 28041b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 28053b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 28065bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2807770597ecSKeith Busch nvme_free_tagset(dev); 280857dacad5SJay Sternberg } else { 280925646264SKeith Busch nvme_start_queues(&dev->ctrl); 2810302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 28115d02a5c1SKeith Busch nvme_dev_add(dev); 2812302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 281357dacad5SJay Sternberg } 281457dacad5SJay Sternberg 28152b1b7e78SJianchao Wang /* 28162b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 28172b1b7e78SJianchao Wang * recovery. 28182b1b7e78SJianchao Wang */ 28195d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 28202b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 28215d02a5c1SKeith Busch "failed to mark controller live state\n"); 2822e71afda4SChaitanya Kulkarni result = -ENODEV; 2823bb8d261eSChristoph Hellwig goto out; 2824bb8d261eSChristoph Hellwig } 282592911a55SChristoph Hellwig 28260521905eSKeith Busch if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 28270521905eSKeith Busch &nvme_pci_attr_group)) 28280521905eSKeith Busch dev->attrs_added = true; 28290521905eSKeith Busch 2830d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 283157dacad5SJay Sternberg return; 283257dacad5SJay Sternberg 28334726bcf3SKeith Busch out_unlock: 28344726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 283557dacad5SJay Sternberg out: 28367c1ce408SChaitanya Kulkarni if (result) 28377c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 28387c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 28397c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 284057dacad5SJay Sternberg } 284157dacad5SJay Sternberg 28425c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 284357dacad5SJay Sternberg { 28445c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 284557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 284657dacad5SJay Sternberg 284757dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2848921920abSKeith Busch device_release_driver(&pdev->dev); 28491673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 285057dacad5SJay Sternberg } 285157dacad5SJay Sternberg 28521c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 285357dacad5SJay Sternberg { 28541c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 28551c63dc66SChristoph Hellwig return 0; 285657dacad5SJay Sternberg } 28571c63dc66SChristoph Hellwig 28585fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 28595fd4ce1bSChristoph Hellwig { 28605fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 28615fd4ce1bSChristoph Hellwig return 0; 28625fd4ce1bSChristoph Hellwig } 28635fd4ce1bSChristoph Hellwig 28647fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 28657fd8930fSChristoph Hellwig { 28663a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 28677fd8930fSChristoph Hellwig return 0; 28687fd8930fSChristoph Hellwig } 28697fd8930fSChristoph Hellwig 287097c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 287197c12223SKeith Busch { 287297c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 287397c12223SKeith Busch 28742db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 287597c12223SKeith Busch } 287697c12223SKeith Busch 28771c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 28781a353d85SMing Lin .name = "pcie", 2879e439bb12SSagi Grimberg .module = THIS_MODULE, 2880e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2881e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 28821c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 28835fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 28847fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 28851673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2886f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 288797c12223SKeith Busch .get_address = nvme_pci_get_address, 28881c63dc66SChristoph Hellwig }; 288957dacad5SJay Sternberg 2890b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2891b00a726aSKeith Busch { 2892b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2893b00a726aSKeith Busch 2894a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2895b00a726aSKeith Busch return -ENODEV; 2896b00a726aSKeith Busch 289797f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2898b00a726aSKeith Busch goto release; 2899b00a726aSKeith Busch 2900b00a726aSKeith Busch return 0; 2901b00a726aSKeith Busch release: 2902a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2903b00a726aSKeith Busch return -ENODEV; 2904b00a726aSKeith Busch } 2905b00a726aSKeith Busch 29068427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2907ff5350a8SAndy Lutomirski { 2908ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2909ff5350a8SAndy Lutomirski /* 2910ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2911ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2912ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2913ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2914ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2915ff5350a8SAndy Lutomirski * laptops. 2916ff5350a8SAndy Lutomirski */ 2917ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2918ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2919ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2920ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 29218427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 29228427bbc2SKai-Heng Feng /* 29238427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2924467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2925467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2926467c77d4SJarosław Janik * ASUS PRIME Z370-A 29278427bbc2SKai-Heng Feng */ 29288427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2929467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2930467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 29318427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 29321fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 29331fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 29341fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 29351fae37acSShyjumon N /* 29361fae37acSShyjumon N * Forcing to use host managed nvme power settings for 29371fae37acSShyjumon N * lowest idle power with quick resume latency on 29381fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 29391fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 29401fae37acSShyjumon N */ 29411fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 29421fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 29431fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2944ff5350a8SAndy Lutomirski } 2945ff5350a8SAndy Lutomirski 2946ff5350a8SAndy Lutomirski return 0; 2947ff5350a8SAndy Lutomirski } 2948ff5350a8SAndy Lutomirski 294918119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 295018119775SKeith Busch { 295118119775SKeith Busch struct nvme_dev *dev = data; 295280f513b5SKeith Busch 2953bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 295418119775SKeith Busch flush_work(&dev->ctrl.scan_work); 295580f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 295618119775SKeith Busch } 295718119775SKeith Busch 295857dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 295957dacad5SJay Sternberg { 296057dacad5SJay Sternberg int node, result = -ENOMEM; 296157dacad5SJay Sternberg struct nvme_dev *dev; 2962ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2963943e942eSJens Axboe size_t alloc_size; 296457dacad5SJay Sternberg 296557dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 296657dacad5SJay Sternberg if (node == NUMA_NO_NODE) 29672fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 296857dacad5SJay Sternberg 296957dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 297057dacad5SJay Sternberg if (!dev) 297157dacad5SJay Sternberg return -ENOMEM; 2972147b27e4SSagi Grimberg 29732a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 29742a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 29752a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 29762a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 29772a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 297857dacad5SJay Sternberg if (!dev->queues) 297957dacad5SJay Sternberg goto free; 298057dacad5SJay Sternberg 298157dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 298257dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 298357dacad5SJay Sternberg 2984b00a726aSKeith Busch result = nvme_dev_map(dev); 2985b00a726aSKeith Busch if (result) 2986b00c9b7aSChristophe JAILLET goto put_pci; 2987b00a726aSKeith Busch 2988d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 29895c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 299077bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2991f3ca80fcSChristoph Hellwig 2992f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2993f3ca80fcSChristoph Hellwig if (result) 2994b00c9b7aSChristophe JAILLET goto unmap; 2995f3ca80fcSChristoph Hellwig 29968427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2997ff5350a8SAndy Lutomirski 29982744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2999df4f9bc4SDavid E. Box /* 3000df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3001df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3002df4f9bc4SDavid E. Box */ 3003df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3004df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3005df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3006df4f9bc4SDavid E. Box } 3007df4f9bc4SDavid E. Box 3008943e942eSJens Axboe /* 3009943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 3010943e942eSJens Axboe * command we support. 3011943e942eSJens Axboe */ 3012b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 3013943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3014943e942eSJens Axboe 3015943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3016943e942eSJens Axboe mempool_kfree, 3017943e942eSJens Axboe (void *) alloc_size, 3018943e942eSJens Axboe GFP_KERNEL, node); 3019943e942eSJens Axboe if (!dev->iod_mempool) { 3020943e942eSJens Axboe result = -ENOMEM; 3021943e942eSJens Axboe goto release_pools; 3022943e942eSJens Axboe } 3023943e942eSJens Axboe 3024b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3025b6e44b4cSKeith Busch quirks); 3026b6e44b4cSKeith Busch if (result) 3027b6e44b4cSKeith Busch goto release_mempool; 3028b6e44b4cSKeith Busch 30291b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 30301b3c47c1SSagi Grimberg 3031bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 303218119775SKeith Busch async_schedule(nvme_async_probe, dev); 30334caff8fcSSagi Grimberg 303457dacad5SJay Sternberg return 0; 303557dacad5SJay Sternberg 3036b6e44b4cSKeith Busch release_mempool: 3037b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 303857dacad5SJay Sternberg release_pools: 303957dacad5SJay Sternberg nvme_release_prp_pools(dev); 3040b00c9b7aSChristophe JAILLET unmap: 3041b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 304257dacad5SJay Sternberg put_pci: 304357dacad5SJay Sternberg put_device(dev->dev); 304457dacad5SJay Sternberg free: 304557dacad5SJay Sternberg kfree(dev->queues); 304657dacad5SJay Sternberg kfree(dev); 304757dacad5SJay Sternberg return result; 304857dacad5SJay Sternberg } 304957dacad5SJay Sternberg 3050775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 305157dacad5SJay Sternberg { 305257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3053c1ac9a4bSKeith Busch 3054c1ac9a4bSKeith Busch /* 3055c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3056c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3057c1ac9a4bSKeith Busch * with ->remove(). 3058c1ac9a4bSKeith Busch */ 3059c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3060c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3061775755edSChristoph Hellwig } 306257dacad5SJay Sternberg 3063775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3064775755edSChristoph Hellwig { 3065f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3066c1ac9a4bSKeith Busch 3067c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3068c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 306957dacad5SJay Sternberg } 307057dacad5SJay Sternberg 307157dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 307257dacad5SJay Sternberg { 307357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 30744e523547SBaolin Wang 3075c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 307657dacad5SJay Sternberg } 307757dacad5SJay Sternberg 30780521905eSKeith Busch static void nvme_remove_attrs(struct nvme_dev *dev) 30790521905eSKeith Busch { 30800521905eSKeith Busch if (dev->attrs_added) 30810521905eSKeith Busch sysfs_remove_group(&dev->ctrl.device->kobj, 30820521905eSKeith Busch &nvme_pci_attr_group); 30830521905eSKeith Busch } 30840521905eSKeith Busch 3085f58944e2SKeith Busch /* 3086f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3087f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3088f58944e2SKeith Busch * order to proceed. 3089f58944e2SKeith Busch */ 309057dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 309157dacad5SJay Sternberg { 309257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 309357dacad5SJay Sternberg 3094bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 309557dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 30960ff9d4e1SKeith Busch 30976db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 30980ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 30991d39e692SKeith Busch nvme_dev_disable(dev, true); 31006db28edaSKeith Busch } 31010ff9d4e1SKeith Busch 3102d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3103d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3104d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3105a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 31060521905eSKeith Busch nvme_remove_attrs(dev); 310787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 310857dacad5SJay Sternberg nvme_dev_remove_admin(dev); 310957dacad5SJay Sternberg nvme_free_queues(dev, 0); 311057dacad5SJay Sternberg nvme_release_prp_pools(dev); 3111b00a726aSKeith Busch nvme_dev_unmap(dev); 3112726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 311357dacad5SJay Sternberg } 311457dacad5SJay Sternberg 311557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3116d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3117d916b1beSKeith Busch { 3118d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3119d916b1beSKeith Busch } 3120d916b1beSKeith Busch 3121d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3122d916b1beSKeith Busch { 3123d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3124d916b1beSKeith Busch } 3125d916b1beSKeith Busch 3126d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3127d916b1beSKeith Busch { 3128d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3129d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3130d916b1beSKeith Busch 31314eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3132d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3133e5ad96f3SKeith Busch goto reset; 3134e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3135e5ad96f3SKeith Busch goto reset; 3136e5ad96f3SKeith Busch 3137d916b1beSKeith Busch return 0; 3138e5ad96f3SKeith Busch reset: 3139e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3140d916b1beSKeith Busch } 3141d916b1beSKeith Busch 314257dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 314357dacad5SJay Sternberg { 314457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 314557dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3146d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3147d916b1beSKeith Busch int ret = -EBUSY; 3148d916b1beSKeith Busch 31494eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 31504eaefe8cSRafael J. Wysocki 3151d916b1beSKeith Busch /* 3152d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3153d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3154d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3155d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3156d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3157d916b1beSKeith Busch * device fully. 31584eaefe8cSRafael J. Wysocki * 31594eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 31604eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 31614eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 31624eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3163d916b1beSKeith Busch */ 31644eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3165cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3166c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3167c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3168d916b1beSKeith Busch 3169d916b1beSKeith Busch nvme_start_freeze(ctrl); 3170d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3171d916b1beSKeith Busch nvme_sync_queues(ctrl); 3172d916b1beSKeith Busch 31735d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3174d916b1beSKeith Busch goto unfreeze; 3175d916b1beSKeith Busch 3176e5ad96f3SKeith Busch /* 3177e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3178e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3179e5ad96f3SKeith Busch * non-operational power state. 3180e5ad96f3SKeith Busch */ 3181e5ad96f3SKeith Busch if (ndev->hmb) { 3182e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3183e5ad96f3SKeith Busch if (ret < 0) 3184e5ad96f3SKeith Busch goto unfreeze; 3185e5ad96f3SKeith Busch } 3186e5ad96f3SKeith Busch 3187d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3188d916b1beSKeith Busch if (ret < 0) 3189d916b1beSKeith Busch goto unfreeze; 3190d916b1beSKeith Busch 31917cbb5c6fSMario Limonciello /* 31927cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 31937cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 31947cbb5c6fSMario Limonciello * want pci interfering. 31957cbb5c6fSMario Limonciello */ 31967cbb5c6fSMario Limonciello pci_save_state(pdev); 31977cbb5c6fSMario Limonciello 3198d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3199d916b1beSKeith Busch if (ret < 0) 3200d916b1beSKeith Busch goto unfreeze; 3201d916b1beSKeith Busch 3202d916b1beSKeith Busch if (ret) { 32037cbb5c6fSMario Limonciello /* discard the saved state */ 32047cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 32057cbb5c6fSMario Limonciello 3206d916b1beSKeith Busch /* 3207d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 320805d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3209d916b1beSKeith Busch */ 3210c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3211d916b1beSKeith Busch ctrl->npss = 0; 3212d916b1beSKeith Busch } 3213d916b1beSKeith Busch unfreeze: 3214d916b1beSKeith Busch nvme_unfreeze(ctrl); 3215d916b1beSKeith Busch return ret; 3216d916b1beSKeith Busch } 3217d916b1beSKeith Busch 3218d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3219d916b1beSKeith Busch { 3220d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 32214e523547SBaolin Wang 3222c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 322357dacad5SJay Sternberg } 322457dacad5SJay Sternberg 3225d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 322657dacad5SJay Sternberg { 322757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 322857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 322957dacad5SJay Sternberg 3230c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 323157dacad5SJay Sternberg } 323257dacad5SJay Sternberg 323321774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3234d916b1beSKeith Busch .suspend = nvme_suspend, 3235d916b1beSKeith Busch .resume = nvme_resume, 3236d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3237d916b1beSKeith Busch .thaw = nvme_simple_resume, 3238d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3239d916b1beSKeith Busch .restore = nvme_simple_resume, 3240d916b1beSKeith Busch }; 3241d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 324257dacad5SJay Sternberg 3243a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3244a0a3408eSKeith Busch pci_channel_state_t state) 3245a0a3408eSKeith Busch { 3246a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3247a0a3408eSKeith Busch 3248a0a3408eSKeith Busch /* 3249a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3250a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3251a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3252a0a3408eSKeith Busch */ 3253a0a3408eSKeith Busch switch (state) { 3254a0a3408eSKeith Busch case pci_channel_io_normal: 3255a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3256a0a3408eSKeith Busch case pci_channel_io_frozen: 3257d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3258d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3259a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3260a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3261a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3262d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3263d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3264a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3265a0a3408eSKeith Busch } 3266a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3267a0a3408eSKeith Busch } 3268a0a3408eSKeith Busch 3269a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3270a0a3408eSKeith Busch { 3271a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3272a0a3408eSKeith Busch 32731b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3274a0a3408eSKeith Busch pci_restore_state(pdev); 3275d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3276a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3277a0a3408eSKeith Busch } 3278a0a3408eSKeith Busch 3279a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3280a0a3408eSKeith Busch { 328172cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 328272cd4cc2SKeith Busch 328372cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3284a0a3408eSKeith Busch } 3285a0a3408eSKeith Busch 328657dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 328757dacad5SJay Sternberg .error_detected = nvme_error_detected, 328857dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 328957dacad5SJay Sternberg .resume = nvme_error_resume, 3290775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3291775755edSChristoph Hellwig .reset_done = nvme_reset_done, 329257dacad5SJay Sternberg }; 329357dacad5SJay Sternberg 329457dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3295972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 329608095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3297e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3298972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 329999466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3300e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3301972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 330299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3303e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3304972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3305f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3306f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 330750af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 33089abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 33096c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3310ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3311ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33126299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 33136299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3314540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 33157b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 33167b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33175bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 33185bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 33190302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 33205e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 33215e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 332254adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 332354adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 33248c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 33258c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3326015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3327015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3328d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3329d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3330d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 33317ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3332abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 33337ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3334c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3335c9e95c39SClaus Stovgaard .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 33366e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 33376e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 33386e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 333908b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 334008b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3341f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3342f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3343f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 33445611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 33455611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 334602ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 334702ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 334889919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 334989919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3350dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3351dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3352538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3353538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 33544bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 33554bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33564bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 33574bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33584bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 33594bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33604bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 33614bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33624bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 33634bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 33644bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 33654bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 336698f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 336798f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3368124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 336966341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 337066341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3371d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3372*a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3373*a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 33740b85f59dSAndy Shevchenko 33750b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 337657dacad5SJay Sternberg { 0, } 337757dacad5SJay Sternberg }; 337857dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 337957dacad5SJay Sternberg 338057dacad5SJay Sternberg static struct pci_driver nvme_driver = { 338157dacad5SJay Sternberg .name = "nvme", 338257dacad5SJay Sternberg .id_table = nvme_id_table, 338357dacad5SJay Sternberg .probe = nvme_probe, 338457dacad5SJay Sternberg .remove = nvme_remove, 338557dacad5SJay Sternberg .shutdown = nvme_shutdown, 3386d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 338757dacad5SJay Sternberg .driver = { 338857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 338957dacad5SJay Sternberg }, 3390d916b1beSKeith Busch #endif 339174d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 339257dacad5SJay Sternberg .err_handler = &nvme_err_handler, 339357dacad5SJay Sternberg }; 339457dacad5SJay Sternberg 339557dacad5SJay Sternberg static int __init nvme_init(void) 339657dacad5SJay Sternberg { 339781101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 339881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 339981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3400612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 340117c33167SKeith Busch 34029a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 340357dacad5SJay Sternberg } 340457dacad5SJay Sternberg 340557dacad5SJay Sternberg static void __exit nvme_exit(void) 340657dacad5SJay Sternberg { 340757dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 340803e0f3a6SMing Lei flush_workqueue(nvme_wq); 340957dacad5SJay Sternberg } 341057dacad5SJay Sternberg 341157dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 341257dacad5SJay Sternberg MODULE_LICENSE("GPL"); 341357dacad5SJay Sternberg MODULE_VERSION("1.0"); 341457dacad5SJay Sternberg module_init(nvme_init); 341557dacad5SJay Sternberg module_exit(nvme_exit); 3416