157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #include "nvme.h" 3657dacad5SJay Sternberg 3757dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3857dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3957dacad5SJay Sternberg 40a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 41adf68f21SChristoph Hellwig 42943e942eSJens Axboe /* 43943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 44943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 45943e942eSJens Axboe */ 46943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 47943e942eSJens Axboe #define NVME_MAX_SEGS 127 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 5057dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 70b27c1e68Sweiping zhang .get = param_get_int, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 73b27c1e68Sweiping zhang static int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 76b27c1e68Sweiping zhang 771c63dc66SChristoph Hellwig struct nvme_dev; 781c63dc66SChristoph Hellwig struct nvme_queue; 7957dacad5SJay Sternberg 80a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 8157dacad5SJay Sternberg 8257dacad5SJay Sternberg /* 831c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 841c63dc66SChristoph Hellwig */ 851c63dc66SChristoph Hellwig struct nvme_dev { 86147b27e4SSagi Grimberg struct nvme_queue *queues; 871c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 881c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 891c63dc66SChristoph Hellwig u32 __iomem *dbs; 901c63dc66SChristoph Hellwig struct device *dev; 911c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 921c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 931c63dc66SChristoph Hellwig unsigned online_queues; 941c63dc66SChristoph Hellwig unsigned max_qid; 9522b55601SKeith Busch unsigned int num_vecs; 961c63dc66SChristoph Hellwig int q_depth; 971c63dc66SChristoph Hellwig u32 db_stride; 981c63dc66SChristoph Hellwig void __iomem *bar; 9997f6ef64SXu Yu unsigned long bar_mapped_size; 1005c8809e6SChristoph Hellwig struct work_struct remove_work; 10177bf25eaSKeith Busch struct mutex shutdown_lock; 1021c63dc66SChristoph Hellwig bool subsystem; 1031c63dc66SChristoph Hellwig u64 cmb_size; 1040f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1051c63dc66SChristoph Hellwig u32 cmbsz; 106202021c1SStephen Bates u32 cmbloc; 1071c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 108db3cbfffSKeith Busch struct completion ioq_wait; 10987ad72a5SChristoph Hellwig 110943e942eSJens Axboe mempool_t *iod_mempool; 111943e942eSJens Axboe 11287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 113f9f38e33SHelen Koike u32 *dbbuf_dbs; 114f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 115f9f38e33SHelen Koike u32 *dbbuf_eis; 116f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 11787ad72a5SChristoph Hellwig 11887ad72a5SChristoph Hellwig /* host memory buffer support: */ 11987ad72a5SChristoph Hellwig u64 host_mem_size; 12087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1214033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 12287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 12387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 12457dacad5SJay Sternberg }; 12557dacad5SJay Sternberg 126b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 127b27c1e68Sweiping zhang { 128b27c1e68Sweiping zhang int n = 0, ret; 129b27c1e68Sweiping zhang 130b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 131b27c1e68Sweiping zhang if (ret != 0 || n < 2) 132b27c1e68Sweiping zhang return -EINVAL; 133b27c1e68Sweiping zhang 134b27c1e68Sweiping zhang return param_set_int(val, kp); 135b27c1e68Sweiping zhang } 136b27c1e68Sweiping zhang 137f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 138f9f38e33SHelen Koike { 139f9f38e33SHelen Koike return qid * 2 * stride; 140f9f38e33SHelen Koike } 141f9f38e33SHelen Koike 142f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 143f9f38e33SHelen Koike { 144f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 145f9f38e33SHelen Koike } 146f9f38e33SHelen Koike 1471c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1481c63dc66SChristoph Hellwig { 1491c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1501c63dc66SChristoph Hellwig } 1511c63dc66SChristoph Hellwig 15257dacad5SJay Sternberg /* 15357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 15457dacad5SJay Sternberg * commands and one for I/O commands). 15557dacad5SJay Sternberg */ 15657dacad5SJay Sternberg struct nvme_queue { 15757dacad5SJay Sternberg struct device *q_dmadev; 15857dacad5SJay Sternberg struct nvme_dev *dev; 1591ab0cd69SJens Axboe spinlock_t sq_lock; 16057dacad5SJay Sternberg struct nvme_command *sq_cmds; 1610f238ff5SLogan Gunthorpe bool sq_cmds_is_io; 1621ab0cd69SJens Axboe spinlock_t cq_lock ____cacheline_aligned_in_smp; 16357dacad5SJay Sternberg volatile struct nvme_completion *cqes; 16457dacad5SJay Sternberg struct blk_mq_tags **tags; 16557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 16657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 16757dacad5SJay Sternberg u32 __iomem *q_db; 16857dacad5SJay Sternberg u16 q_depth; 16957dacad5SJay Sternberg s16 cq_vector; 17057dacad5SJay Sternberg u16 sq_tail; 17157dacad5SJay Sternberg u16 cq_head; 17268fa9dbeSJens Axboe u16 last_cq_head; 17357dacad5SJay Sternberg u16 qid; 17457dacad5SJay Sternberg u8 cq_phase; 175f9f38e33SHelen Koike u32 *dbbuf_sq_db; 176f9f38e33SHelen Koike u32 *dbbuf_cq_db; 177f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 178f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 17957dacad5SJay Sternberg }; 18057dacad5SJay Sternberg 18157dacad5SJay Sternberg /* 18271bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 18371bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 184f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 18571bd150cSChristoph Hellwig * allocated to store the PRP list. 18671bd150cSChristoph Hellwig */ 18771bd150cSChristoph Hellwig struct nvme_iod { 188d49187e9SChristoph Hellwig struct nvme_request req; 189f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 190a7a7cbe3SChaitanya Kulkarni bool use_sgl; 191f4800d6dSChristoph Hellwig int aborted; 19271bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 19371bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 19471bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 19571bd150cSChristoph Hellwig dma_addr_t first_dma; 196bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 197f4800d6dSChristoph Hellwig struct scatterlist *sg; 198f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 19957dacad5SJay Sternberg }; 20057dacad5SJay Sternberg 20157dacad5SJay Sternberg /* 20257dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 20357dacad5SJay Sternberg */ 20457dacad5SJay Sternberg static inline void _nvme_check_size(void) 20557dacad5SJay Sternberg { 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 20757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 20857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 20957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 21057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 21157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 21257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 21357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2140add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2150add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 21657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 21757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 218f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 219f9f38e33SHelen Koike } 220f9f38e33SHelen Koike 221f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 222f9f38e33SHelen Koike { 223f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 224f9f38e33SHelen Koike } 225f9f38e33SHelen Koike 226f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 227f9f38e33SHelen Koike { 228f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 229f9f38e33SHelen Koike 230f9f38e33SHelen Koike if (dev->dbbuf_dbs) 231f9f38e33SHelen Koike return 0; 232f9f38e33SHelen Koike 233f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 234f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 235f9f38e33SHelen Koike GFP_KERNEL); 236f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 237f9f38e33SHelen Koike return -ENOMEM; 238f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 239f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 240f9f38e33SHelen Koike GFP_KERNEL); 241f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 242f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 243f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 244f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 245f9f38e33SHelen Koike return -ENOMEM; 246f9f38e33SHelen Koike } 247f9f38e33SHelen Koike 248f9f38e33SHelen Koike return 0; 249f9f38e33SHelen Koike } 250f9f38e33SHelen Koike 251f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 252f9f38e33SHelen Koike { 253f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 254f9f38e33SHelen Koike 255f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 256f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 257f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 258f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 259f9f38e33SHelen Koike } 260f9f38e33SHelen Koike if (dev->dbbuf_eis) { 261f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 262f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 263f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 264f9f38e33SHelen Koike } 265f9f38e33SHelen Koike } 266f9f38e33SHelen Koike 267f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 268f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 271f9f38e33SHelen Koike return; 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 274f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 275f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 276f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 277f9f38e33SHelen Koike } 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 280f9f38e33SHelen Koike { 281f9f38e33SHelen Koike struct nvme_command c; 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 284f9f38e33SHelen Koike return; 285f9f38e33SHelen Koike 286f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 287f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 288f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 289f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2929bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 293f9f38e33SHelen Koike /* Free memory and continue on */ 294f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 295f9f38e33SHelen Koike } 296f9f38e33SHelen Koike } 297f9f38e33SHelen Koike 298f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 299f9f38e33SHelen Koike { 300f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 301f9f38e33SHelen Koike } 302f9f38e33SHelen Koike 303f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 304f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 305f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 306f9f38e33SHelen Koike { 307f9f38e33SHelen Koike if (dbbuf_db) { 308f9f38e33SHelen Koike u16 old_value; 309f9f38e33SHelen Koike 310f9f38e33SHelen Koike /* 311f9f38e33SHelen Koike * Ensure that the queue is written before updating 312f9f38e33SHelen Koike * the doorbell in memory 313f9f38e33SHelen Koike */ 314f9f38e33SHelen Koike wmb(); 315f9f38e33SHelen Koike 316f9f38e33SHelen Koike old_value = *dbbuf_db; 317f9f38e33SHelen Koike *dbbuf_db = value; 318f9f38e33SHelen Koike 319f1ed3df2SMichal Wnukowski /* 320f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 321f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 322f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 323f1ed3df2SMichal Wnukowski * the doorbell. 324f1ed3df2SMichal Wnukowski */ 325f1ed3df2SMichal Wnukowski mb(); 326f1ed3df2SMichal Wnukowski 327f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 328f9f38e33SHelen Koike return false; 329f9f38e33SHelen Koike } 330f9f38e33SHelen Koike 331f9f38e33SHelen Koike return true; 33257dacad5SJay Sternberg } 33357dacad5SJay Sternberg 33457dacad5SJay Sternberg /* 33557dacad5SJay Sternberg * Max size of iod being embedded in the request payload 33657dacad5SJay Sternberg */ 33757dacad5SJay Sternberg #define NVME_INT_PAGES 2 3385fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 33957dacad5SJay Sternberg 34057dacad5SJay Sternberg /* 34157dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 34257dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 34357dacad5SJay Sternberg * the I/O. 34457dacad5SJay Sternberg */ 34557dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 34657dacad5SJay Sternberg { 3475fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3485fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 34957dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 35057dacad5SJay Sternberg } 35157dacad5SJay Sternberg 352a7a7cbe3SChaitanya Kulkarni /* 353a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 354a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 355a7a7cbe3SChaitanya Kulkarni */ 356a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 357f4800d6dSChristoph Hellwig { 358a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 359f4800d6dSChristoph Hellwig } 360f4800d6dSChristoph Hellwig 361a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 362a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 36357dacad5SJay Sternberg { 364a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 365a7a7cbe3SChaitanya Kulkarni 366a7a7cbe3SChaitanya Kulkarni if (use_sgl) 367a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 368a7a7cbe3SChaitanya Kulkarni else 369a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 370a7a7cbe3SChaitanya Kulkarni 371a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 372a7a7cbe3SChaitanya Kulkarni } 373a7a7cbe3SChaitanya Kulkarni 374a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 375a7a7cbe3SChaitanya Kulkarni { 376a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 377a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 378a7a7cbe3SChaitanya Kulkarni use_sgl); 379a7a7cbe3SChaitanya Kulkarni 380a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 38157dacad5SJay Sternberg } 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38457dacad5SJay Sternberg unsigned int hctx_idx) 38557dacad5SJay Sternberg { 38657dacad5SJay Sternberg struct nvme_dev *dev = data; 387147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 38857dacad5SJay Sternberg 38957dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 39057dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 39157dacad5SJay Sternberg WARN_ON(nvmeq->tags); 39257dacad5SJay Sternberg 39357dacad5SJay Sternberg hctx->driver_data = nvmeq; 39457dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 39557dacad5SJay Sternberg return 0; 39657dacad5SJay Sternberg } 39757dacad5SJay Sternberg 39857dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 39957dacad5SJay Sternberg { 40057dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg nvmeq->tags = NULL; 40357dacad5SJay Sternberg } 40457dacad5SJay Sternberg 40557dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40657dacad5SJay Sternberg unsigned int hctx_idx) 40757dacad5SJay Sternberg { 40857dacad5SJay Sternberg struct nvme_dev *dev = data; 409147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg if (!nvmeq->tags) 41257dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 41357dacad5SJay Sternberg 41457dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41557dacad5SJay Sternberg hctx->driver_data = nvmeq; 41657dacad5SJay Sternberg return 0; 41757dacad5SJay Sternberg } 41857dacad5SJay Sternberg 419d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 420d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 42157dacad5SJay Sternberg { 422d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 423f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4240350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 425147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg BUG_ON(!nvmeq); 428f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 42959e29ce6SSagi Grimberg 43059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 43157dacad5SJay Sternberg return 0; 43257dacad5SJay Sternberg } 43357dacad5SJay Sternberg 434dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 435dca51e78SChristoph Hellwig { 436dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 437dca51e78SChristoph Hellwig 43822b55601SKeith Busch return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 43922b55601SKeith Busch dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 440dca51e78SChristoph Hellwig } 441dca51e78SChristoph Hellwig 44257dacad5SJay Sternberg /** 44390ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 44457dacad5SJay Sternberg * @nvmeq: The queue to use 44557dacad5SJay Sternberg * @cmd: The command to send 44657dacad5SJay Sternberg */ 44790ea5ca4SChristoph Hellwig static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd) 44857dacad5SJay Sternberg { 44990ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 4500f238ff5SLogan Gunthorpe 45190ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 45257dacad5SJay Sternberg 45390ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 45490ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 45590ea5ca4SChristoph Hellwig if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 45690ea5ca4SChristoph Hellwig nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 45790ea5ca4SChristoph Hellwig writel(nvmeq->sq_tail, nvmeq->q_db); 45890ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 45957dacad5SJay Sternberg } 46057dacad5SJay Sternberg 461a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 46257dacad5SJay Sternberg { 463f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 464a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 46557dacad5SJay Sternberg } 46657dacad5SJay Sternberg 467955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 468955b1b5aSMinwoo Im { 469955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 47020469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 471955b1b5aSMinwoo Im unsigned int avg_seg_size; 472955b1b5aSMinwoo Im 47320469a37SKeith Busch if (nseg == 0) 47420469a37SKeith Busch return false; 47520469a37SKeith Busch 47620469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 477955b1b5aSMinwoo Im 478955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 479955b1b5aSMinwoo Im return false; 480955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 481955b1b5aSMinwoo Im return false; 482955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 483955b1b5aSMinwoo Im return false; 484955b1b5aSMinwoo Im return true; 485955b1b5aSMinwoo Im } 486955b1b5aSMinwoo Im 487fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 48857dacad5SJay Sternberg { 489f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 490f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 491b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 492f4800d6dSChristoph Hellwig 493955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 494955b1b5aSMinwoo Im 495f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 496943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 497f4800d6dSChristoph Hellwig if (!iod->sg) 498fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 499f4800d6dSChristoph Hellwig } else { 500f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 50157dacad5SJay Sternberg } 50257dacad5SJay Sternberg 503f4800d6dSChristoph Hellwig iod->aborted = 0; 50457dacad5SJay Sternberg iod->npages = -1; 50557dacad5SJay Sternberg iod->nents = 0; 506f4800d6dSChristoph Hellwig iod->length = size; 507f80ec966SKeith Busch 508fc17b653SChristoph Hellwig return BLK_STS_OK; 50957dacad5SJay Sternberg } 51057dacad5SJay Sternberg 511f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 51257dacad5SJay Sternberg { 513f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 514a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 515a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 516a7a7cbe3SChaitanya Kulkarni 51757dacad5SJay Sternberg int i; 51857dacad5SJay Sternberg 51957dacad5SJay Sternberg if (iod->npages == 0) 520a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 521a7a7cbe3SChaitanya Kulkarni dma_addr); 522a7a7cbe3SChaitanya Kulkarni 52357dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 524a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 525a7a7cbe3SChaitanya Kulkarni 526a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 527a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 528a7a7cbe3SChaitanya Kulkarni 529a7a7cbe3SChaitanya Kulkarni next_dma_addr = 530a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 531a7a7cbe3SChaitanya Kulkarni } else { 532a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 533a7a7cbe3SChaitanya Kulkarni 534a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 535a7a7cbe3SChaitanya Kulkarni } 536a7a7cbe3SChaitanya Kulkarni 537a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 538a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 53957dacad5SJay Sternberg } 54057dacad5SJay Sternberg 541f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 542943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 54357dacad5SJay Sternberg } 54457dacad5SJay Sternberg 545d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 546d0877473SKeith Busch { 547d0877473SKeith Busch int i; 548d0877473SKeith Busch struct scatterlist *sg; 549d0877473SKeith Busch 550d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 551d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 552d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 553d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 554d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 555d0877473SKeith Busch sg_dma_len(sg)); 556d0877473SKeith Busch } 557d0877473SKeith Busch } 558d0877473SKeith Busch 559a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 560a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 56157dacad5SJay Sternberg { 562f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 56357dacad5SJay Sternberg struct dma_pool *pool; 564b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 56557dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 56657dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 56757dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5685fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 56957dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 57057dacad5SJay Sternberg __le64 *prp_list; 571a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 57257dacad5SJay Sternberg dma_addr_t prp_dma; 57357dacad5SJay Sternberg int nprps, i; 57457dacad5SJay Sternberg 57557dacad5SJay Sternberg length -= (page_size - offset); 5765228b328SJan H. Schönherr if (length <= 0) { 5775228b328SJan H. Schönherr iod->first_dma = 0; 578a7a7cbe3SChaitanya Kulkarni goto done; 5795228b328SJan H. Schönherr } 58057dacad5SJay Sternberg 58157dacad5SJay Sternberg dma_len -= (page_size - offset); 58257dacad5SJay Sternberg if (dma_len) { 58357dacad5SJay Sternberg dma_addr += (page_size - offset); 58457dacad5SJay Sternberg } else { 58557dacad5SJay Sternberg sg = sg_next(sg); 58657dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 58757dacad5SJay Sternberg dma_len = sg_dma_len(sg); 58857dacad5SJay Sternberg } 58957dacad5SJay Sternberg 59057dacad5SJay Sternberg if (length <= page_size) { 59157dacad5SJay Sternberg iod->first_dma = dma_addr; 592a7a7cbe3SChaitanya Kulkarni goto done; 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg 59557dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 59657dacad5SJay Sternberg if (nprps <= (256 / 8)) { 59757dacad5SJay Sternberg pool = dev->prp_small_pool; 59857dacad5SJay Sternberg iod->npages = 0; 59957dacad5SJay Sternberg } else { 60057dacad5SJay Sternberg pool = dev->prp_page_pool; 60157dacad5SJay Sternberg iod->npages = 1; 60257dacad5SJay Sternberg } 60357dacad5SJay Sternberg 60469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 60557dacad5SJay Sternberg if (!prp_list) { 60657dacad5SJay Sternberg iod->first_dma = dma_addr; 60757dacad5SJay Sternberg iod->npages = -1; 60886eea289SKeith Busch return BLK_STS_RESOURCE; 60957dacad5SJay Sternberg } 61057dacad5SJay Sternberg list[0] = prp_list; 61157dacad5SJay Sternberg iod->first_dma = prp_dma; 61257dacad5SJay Sternberg i = 0; 61357dacad5SJay Sternberg for (;;) { 61457dacad5SJay Sternberg if (i == page_size >> 3) { 61557dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 61669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 61757dacad5SJay Sternberg if (!prp_list) 61886eea289SKeith Busch return BLK_STS_RESOURCE; 61957dacad5SJay Sternberg list[iod->npages++] = prp_list; 62057dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 62157dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 62257dacad5SJay Sternberg i = 1; 62357dacad5SJay Sternberg } 62457dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 62557dacad5SJay Sternberg dma_len -= page_size; 62657dacad5SJay Sternberg dma_addr += page_size; 62757dacad5SJay Sternberg length -= page_size; 62857dacad5SJay Sternberg if (length <= 0) 62957dacad5SJay Sternberg break; 63057dacad5SJay Sternberg if (dma_len > 0) 63157dacad5SJay Sternberg continue; 63286eea289SKeith Busch if (unlikely(dma_len < 0)) 63386eea289SKeith Busch goto bad_sgl; 63457dacad5SJay Sternberg sg = sg_next(sg); 63557dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63657dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63757dacad5SJay Sternberg } 63857dacad5SJay Sternberg 639a7a7cbe3SChaitanya Kulkarni done: 640a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 641a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 642a7a7cbe3SChaitanya Kulkarni 64386eea289SKeith Busch return BLK_STS_OK; 64486eea289SKeith Busch 64586eea289SKeith Busch bad_sgl: 646d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 647d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 648d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 64986eea289SKeith Busch return BLK_STS_IOERR; 65057dacad5SJay Sternberg } 65157dacad5SJay Sternberg 652a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 653a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 654a7a7cbe3SChaitanya Kulkarni { 655a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 656a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 657a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 658a7a7cbe3SChaitanya Kulkarni } 659a7a7cbe3SChaitanya Kulkarni 660a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 661a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 662a7a7cbe3SChaitanya Kulkarni { 663a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 664a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 665a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 666a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 667a7a7cbe3SChaitanya Kulkarni } else { 668a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 669a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 670a7a7cbe3SChaitanya Kulkarni } 671a7a7cbe3SChaitanya Kulkarni } 672a7a7cbe3SChaitanya Kulkarni 673a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 674b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 675a7a7cbe3SChaitanya Kulkarni { 676a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 677a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 678a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 679a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 680a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 681b0f2853bSChristoph Hellwig int i = 0; 682a7a7cbe3SChaitanya Kulkarni 683a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 684a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 685a7a7cbe3SChaitanya Kulkarni 686b0f2853bSChristoph Hellwig if (entries == 1) { 687a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 688a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 689a7a7cbe3SChaitanya Kulkarni } 690a7a7cbe3SChaitanya Kulkarni 691a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 692a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 693a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 694a7a7cbe3SChaitanya Kulkarni } else { 695a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 696a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 697a7a7cbe3SChaitanya Kulkarni } 698a7a7cbe3SChaitanya Kulkarni 699a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 700a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 701a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 702a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 703a7a7cbe3SChaitanya Kulkarni } 704a7a7cbe3SChaitanya Kulkarni 705a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 706a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 707a7a7cbe3SChaitanya Kulkarni 708a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 709a7a7cbe3SChaitanya Kulkarni 710a7a7cbe3SChaitanya Kulkarni do { 711a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 712a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 713a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 714a7a7cbe3SChaitanya Kulkarni 715a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 716a7a7cbe3SChaitanya Kulkarni if (!sg_list) 717a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 718a7a7cbe3SChaitanya Kulkarni 719a7a7cbe3SChaitanya Kulkarni i = 0; 720a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 721a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 722a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 723a7a7cbe3SChaitanya Kulkarni } 724a7a7cbe3SChaitanya Kulkarni 725a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 726a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 727b0f2853bSChristoph Hellwig } while (--entries > 0); 728a7a7cbe3SChaitanya Kulkarni 729a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 730a7a7cbe3SChaitanya Kulkarni } 731a7a7cbe3SChaitanya Kulkarni 732fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 733b131c61dSChristoph Hellwig struct nvme_command *cmnd) 73457dacad5SJay Sternberg { 735f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 736ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 737ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 738ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 739fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 740b0f2853bSChristoph Hellwig int nr_mapped; 74157dacad5SJay Sternberg 742f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 743ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 744ba1ca37eSChristoph Hellwig if (!iod->nents) 745ba1ca37eSChristoph Hellwig goto out; 746ba1ca37eSChristoph Hellwig 747fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 748e0596ab2SLogan Gunthorpe 749e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 750e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 751e0596ab2SLogan Gunthorpe dma_dir); 752e0596ab2SLogan Gunthorpe else 753e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 754e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 755b0f2853bSChristoph Hellwig if (!nr_mapped) 756ba1ca37eSChristoph Hellwig goto out; 757ba1ca37eSChristoph Hellwig 758955b1b5aSMinwoo Im if (iod->use_sgl) 759b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 760a7a7cbe3SChaitanya Kulkarni else 761a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 762a7a7cbe3SChaitanya Kulkarni 76386eea289SKeith Busch if (ret != BLK_STS_OK) 764ba1ca37eSChristoph Hellwig goto out_unmap; 765ba1ca37eSChristoph Hellwig 766fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 767ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 768ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 769ba1ca37eSChristoph Hellwig goto out_unmap; 770ba1ca37eSChristoph Hellwig 771bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 772bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 773ba1ca37eSChristoph Hellwig goto out_unmap; 774ba1ca37eSChristoph Hellwig 775bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 776ba1ca37eSChristoph Hellwig goto out_unmap; 7773045c0d0SChaitanya Kulkarni 7783045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 77957dacad5SJay Sternberg } 78057dacad5SJay Sternberg 781fc17b653SChristoph Hellwig return BLK_STS_OK; 782ba1ca37eSChristoph Hellwig 783ba1ca37eSChristoph Hellwig out_unmap: 784ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 785ba1ca37eSChristoph Hellwig out: 786ba1ca37eSChristoph Hellwig return ret; 78757dacad5SJay Sternberg } 78857dacad5SJay Sternberg 789f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 790d4f6c3abSChristoph Hellwig { 791f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 792d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 793d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 794d4f6c3abSChristoph Hellwig 795d4f6c3abSChristoph Hellwig if (iod->nents) { 796e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 797e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 798d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 799e0596ab2SLogan Gunthorpe 800f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 801bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 802d4f6c3abSChristoph Hellwig } 803d4f6c3abSChristoph Hellwig 804f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 805f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 80657dacad5SJay Sternberg } 80757dacad5SJay Sternberg 80857dacad5SJay Sternberg /* 80957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 81057dacad5SJay Sternberg */ 811fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 81257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 81357dacad5SJay Sternberg { 81457dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 81557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 81657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 81757dacad5SJay Sternberg struct request *req = bd->rq; 818ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 819ebe6d874SChristoph Hellwig blk_status_t ret; 82057dacad5SJay Sternberg 821d1f06f4aSJens Axboe /* 822d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 823d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 824d1f06f4aSJens Axboe */ 825d1f06f4aSJens Axboe if (unlikely(nvmeq->cq_vector < 0)) 826d1f06f4aSJens Axboe return BLK_STS_IOERR; 827d1f06f4aSJens Axboe 828f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 829fc17b653SChristoph Hellwig if (ret) 830f4800d6dSChristoph Hellwig return ret; 83157dacad5SJay Sternberg 832b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 833fc17b653SChristoph Hellwig if (ret) 834f9d03f96SChristoph Hellwig goto out_free_cmd; 83557dacad5SJay Sternberg 836fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 837b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 838fc17b653SChristoph Hellwig if (ret) 839f9d03f96SChristoph Hellwig goto out_cleanup_iod; 840fc17b653SChristoph Hellwig } 841ba1ca37eSChristoph Hellwig 842aae239e1SChristoph Hellwig blk_mq_start_request(req); 84390ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &cmnd); 844fc17b653SChristoph Hellwig return BLK_STS_OK; 845f9d03f96SChristoph Hellwig out_cleanup_iod: 846f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 847f9d03f96SChristoph Hellwig out_free_cmd: 848f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 849ba1ca37eSChristoph Hellwig return ret; 85057dacad5SJay Sternberg } 85157dacad5SJay Sternberg 85277f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 853eee417b0SChristoph Hellwig { 854f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 855eee417b0SChristoph Hellwig 85677f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 85777f02a7aSChristoph Hellwig nvme_complete_rq(req); 85857dacad5SJay Sternberg } 85957dacad5SJay Sternberg 860d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 861750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 862d783e0bdSMarta Rybczynska { 863750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 864750dde44SChristoph Hellwig nvmeq->cq_phase; 865d783e0bdSMarta Rybczynska } 866d783e0bdSMarta Rybczynska 867eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 86857dacad5SJay Sternberg { 869eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 87057dacad5SJay Sternberg 871eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 872eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 873eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 874eb281c82SSagi Grimberg } 875adf68f21SChristoph Hellwig 8765cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 87757dacad5SJay Sternberg { 8785cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 87957dacad5SJay Sternberg struct request *req; 880adf68f21SChristoph Hellwig 88183a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 8821b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 883aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 88483a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 88583a12fb7SSagi Grimberg return; 886aae239e1SChristoph Hellwig } 887aae239e1SChristoph Hellwig 888adf68f21SChristoph Hellwig /* 889adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 890adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 891adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 892adf68f21SChristoph Hellwig * for them but rather special case them here. 893adf68f21SChristoph Hellwig */ 894adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 89538dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 8967bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 89783a12fb7SSagi Grimberg cqe->status, &cqe->result); 898a0fa9647SJens Axboe return; 89957dacad5SJay Sternberg } 90057dacad5SJay Sternberg 90183a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 90283a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 90383a12fb7SSagi Grimberg } 90457dacad5SJay Sternberg 9055cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 90683a12fb7SSagi Grimberg { 9075cb525c8SJens Axboe while (start != end) { 9085cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9095cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9105cb525c8SJens Axboe start = 0; 9115cb525c8SJens Axboe } 9125cb525c8SJens Axboe } 91383a12fb7SSagi Grimberg 9145cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 9155cb525c8SJens Axboe { 916920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 917920d13a8SSagi Grimberg nvmeq->cq_head = 0; 918920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 919920d13a8SSagi Grimberg } 920a0fa9647SJens Axboe } 921a0fa9647SJens Axboe 9225cb525c8SJens Axboe static inline bool nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 9235cb525c8SJens Axboe u16 *end, int tag) 924a0fa9647SJens Axboe { 9255cb525c8SJens Axboe bool found = false; 92683a12fb7SSagi Grimberg 9275cb525c8SJens Axboe *start = nvmeq->cq_head; 9285cb525c8SJens Axboe while (!found && nvme_cqe_pending(nvmeq)) { 9295cb525c8SJens Axboe if (nvmeq->cqes[nvmeq->cq_head].command_id == tag) 9305cb525c8SJens Axboe found = true; 9315cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 93257dacad5SJay Sternberg } 9335cb525c8SJens Axboe *end = nvmeq->cq_head; 93457dacad5SJay Sternberg 9355cb525c8SJens Axboe if (*start != *end) 936eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 9375cb525c8SJens Axboe return found; 93857dacad5SJay Sternberg } 93957dacad5SJay Sternberg 94057dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 94157dacad5SJay Sternberg { 94257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 94368fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 9445cb525c8SJens Axboe u16 start, end; 9455cb525c8SJens Axboe 9461ab0cd69SJens Axboe spin_lock(&nvmeq->cq_lock); 94768fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 94868fa9dbeSJens Axboe ret = IRQ_HANDLED; 9495cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 95068fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 9511ab0cd69SJens Axboe spin_unlock(&nvmeq->cq_lock); 9525cb525c8SJens Axboe 95368fa9dbeSJens Axboe if (start != end) { 9545cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 9555cb525c8SJens Axboe return IRQ_HANDLED; 95657dacad5SJay Sternberg } 95757dacad5SJay Sternberg 95868fa9dbeSJens Axboe return ret; 95957dacad5SJay Sternberg } 96057dacad5SJay Sternberg 96157dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 96257dacad5SJay Sternberg { 96357dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 964750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 96557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 966d783e0bdSMarta Rybczynska return IRQ_NONE; 96757dacad5SJay Sternberg } 96857dacad5SJay Sternberg 9697776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 970a0fa9647SJens Axboe { 9715cb525c8SJens Axboe u16 start, end; 9725cb525c8SJens Axboe bool found; 973a0fa9647SJens Axboe 974750dde44SChristoph Hellwig if (!nvme_cqe_pending(nvmeq)) 975442e19b7SSagi Grimberg return 0; 976442e19b7SSagi Grimberg 9771ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 9785cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 9791ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 980442e19b7SSagi Grimberg 9815cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 982442e19b7SSagi Grimberg return found; 983a0fa9647SJens Axboe } 984a0fa9647SJens Axboe 9857776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 9867776db1cSKeith Busch { 9877776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 9887776db1cSKeith Busch 9897776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 9907776db1cSKeith Busch } 9917776db1cSKeith Busch 992ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 99357dacad5SJay Sternberg { 994f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 995147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 99657dacad5SJay Sternberg struct nvme_command c; 99757dacad5SJay Sternberg 99857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 99957dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1000ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 100190ea5ca4SChristoph Hellwig nvme_submit_cmd(nvmeq, &c); 100257dacad5SJay Sternberg } 100357dacad5SJay Sternberg 100457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 100557dacad5SJay Sternberg { 100657dacad5SJay Sternberg struct nvme_command c; 100757dacad5SJay Sternberg 100857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 100957dacad5SJay Sternberg c.delete_queue.opcode = opcode; 101057dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 101157dacad5SJay Sternberg 10121c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 101357dacad5SJay Sternberg } 101457dacad5SJay Sternberg 101557dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1016a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 101757dacad5SJay Sternberg { 101857dacad5SJay Sternberg struct nvme_command c; 101957dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 102057dacad5SJay Sternberg 102157dacad5SJay Sternberg /* 102216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 102357dacad5SJay Sternberg * is attached to the request. 102457dacad5SJay Sternberg */ 102557dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 102657dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 102757dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 102857dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 102957dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 103057dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1031a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 103257dacad5SJay Sternberg 10331c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 103457dacad5SJay Sternberg } 103557dacad5SJay Sternberg 103657dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 103757dacad5SJay Sternberg struct nvme_queue *nvmeq) 103857dacad5SJay Sternberg { 10399abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 104057dacad5SJay Sternberg struct nvme_command c; 104181c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 104257dacad5SJay Sternberg 104357dacad5SJay Sternberg /* 10449abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 10459abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 10469abd68efSJens Axboe * URGENT. 10479abd68efSJens Axboe */ 10489abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 10499abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 10509abd68efSJens Axboe 10519abd68efSJens Axboe /* 105216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 105357dacad5SJay Sternberg * is attached to the request. 105457dacad5SJay Sternberg */ 105557dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105657dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 105757dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 105857dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 105957dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 106057dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 106157dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 106257dacad5SJay Sternberg 10631c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 106457dacad5SJay Sternberg } 106557dacad5SJay Sternberg 106657dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 106757dacad5SJay Sternberg { 106857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 106957dacad5SJay Sternberg } 107057dacad5SJay Sternberg 107157dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 107257dacad5SJay Sternberg { 107357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 107457dacad5SJay Sternberg } 107557dacad5SJay Sternberg 10762a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 107757dacad5SJay Sternberg { 1078f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1079f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 108057dacad5SJay Sternberg 108127fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 108227fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1083e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1084e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 108557dacad5SJay Sternberg } 108657dacad5SJay Sternberg 1087b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1088b2a0eb1aSKeith Busch { 1089b2a0eb1aSKeith Busch 1090b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1091b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1092b2a0eb1aSKeith Busch */ 1093b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1094b2a0eb1aSKeith Busch 1095ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1096ad70062cSJianchao Wang switch (dev->ctrl.state) { 1097ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1098ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1099b2a0eb1aSKeith Busch return false; 1100ad70062cSJianchao Wang default: 1101ad70062cSJianchao Wang break; 1102ad70062cSJianchao Wang } 1103b2a0eb1aSKeith Busch 1104b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1105b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1106b2a0eb1aSKeith Busch */ 1107b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1108b2a0eb1aSKeith Busch return false; 1109b2a0eb1aSKeith Busch 1110b2a0eb1aSKeith Busch return true; 1111b2a0eb1aSKeith Busch } 1112b2a0eb1aSKeith Busch 1113b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1114b2a0eb1aSKeith Busch { 1115b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1116b2a0eb1aSKeith Busch u16 pci_status; 1117b2a0eb1aSKeith Busch int result; 1118b2a0eb1aSKeith Busch 1119b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1120b2a0eb1aSKeith Busch &pci_status); 1121b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1122b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1123b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1124b2a0eb1aSKeith Busch csts, pci_status); 1125b2a0eb1aSKeith Busch else 1126b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1127b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1128b2a0eb1aSKeith Busch csts, result); 1129b2a0eb1aSKeith Busch } 1130b2a0eb1aSKeith Busch 113131c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 113257dacad5SJay Sternberg { 1133f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1134f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 113557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 113657dacad5SJay Sternberg struct request *abort_req; 113757dacad5SJay Sternberg struct nvme_command cmd; 1138b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1139b2a0eb1aSKeith Busch 1140651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1141651438bbSWen Xiong * the recovery mechanism will surely fail. 1142651438bbSWen Xiong */ 1143651438bbSWen Xiong mb(); 1144651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1145651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1146651438bbSWen Xiong 1147b2a0eb1aSKeith Busch /* 1148b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1149b2a0eb1aSKeith Busch */ 1150b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1151b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1152b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1153d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1154db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1155b2a0eb1aSKeith Busch } 115657dacad5SJay Sternberg 115731c7c7d2SChristoph Hellwig /* 11587776db1cSKeith Busch * Did we miss an interrupt? 11597776db1cSKeith Busch */ 11607776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 11617776db1cSKeith Busch dev_warn(dev->ctrl.device, 11627776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 11637776db1cSKeith Busch req->tag, nvmeq->qid); 1164db8c48e4SChristoph Hellwig return BLK_EH_DONE; 11657776db1cSKeith Busch } 11667776db1cSKeith Busch 11677776db1cSKeith Busch /* 1168fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1169fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1170fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1171db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1172fd634f41SChristoph Hellwig */ 11734244140dSKeith Busch switch (dev->ctrl.state) { 11744244140dSKeith Busch case NVME_CTRL_CONNECTING: 11754244140dSKeith Busch case NVME_CTRL_RESETTING: 1176b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1177fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1178fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1179a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 118027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1181db8c48e4SChristoph Hellwig return BLK_EH_DONE; 11824244140dSKeith Busch default: 11834244140dSKeith Busch break; 1184fd634f41SChristoph Hellwig } 1185fd634f41SChristoph Hellwig 1186fd634f41SChristoph Hellwig /* 1187e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1188e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1189e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 119031c7c7d2SChristoph Hellwig */ 1191f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 11921b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 119357dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 119457dacad5SJay Sternberg req->tag, nvmeq->qid); 1195a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1196d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1197e1569a16SKeith Busch 119827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1199db8c48e4SChristoph Hellwig return BLK_EH_DONE; 120057dacad5SJay Sternberg } 120157dacad5SJay Sternberg 1202e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1203e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1204e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1205e7a2a87dSChristoph Hellwig } 12067bf7d778SKeith Busch iod->aborted = 1; 120757dacad5SJay Sternberg 120857dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 120957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 121057dacad5SJay Sternberg cmd.abort.cid = req->tag; 121157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 121257dacad5SJay Sternberg 12131b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12141b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 121557dacad5SJay Sternberg req->tag, nvmeq->qid); 1216e7a2a87dSChristoph Hellwig 1217e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1218eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12196bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12206bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 122131c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 122257dacad5SJay Sternberg } 122357dacad5SJay Sternberg 1224e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1225e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1226e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 122757dacad5SJay Sternberg 122857dacad5SJay Sternberg /* 122957dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 123057dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 123157dacad5SJay Sternberg * as the device then is in a faulty state. 123257dacad5SJay Sternberg */ 123357dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 123457dacad5SJay Sternberg } 123557dacad5SJay Sternberg 123657dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 123757dacad5SJay Sternberg { 123857dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 123957dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 12400f238ff5SLogan Gunthorpe 12410f238ff5SLogan Gunthorpe if (nvmeq->sq_cmds) { 12420f238ff5SLogan Gunthorpe if (nvmeq->sq_cmds_is_io) 12430f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 12440f238ff5SLogan Gunthorpe nvmeq->sq_cmds, 12450f238ff5SLogan Gunthorpe SQ_SIZE(nvmeq->q_depth)); 12460f238ff5SLogan Gunthorpe else 12470f238ff5SLogan Gunthorpe dma_free_coherent(nvmeq->q_dmadev, 12480f238ff5SLogan Gunthorpe SQ_SIZE(nvmeq->q_depth), 12490f238ff5SLogan Gunthorpe nvmeq->sq_cmds, 12500f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr); 12510f238ff5SLogan Gunthorpe } 125257dacad5SJay Sternberg } 125357dacad5SJay Sternberg 125457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 125557dacad5SJay Sternberg { 125657dacad5SJay Sternberg int i; 125757dacad5SJay Sternberg 1258d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1259d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1260147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 126157dacad5SJay Sternberg } 126257dacad5SJay Sternberg } 126357dacad5SJay Sternberg 126457dacad5SJay Sternberg /** 126557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 126640581d1aSBart Van Assche * @nvmeq: queue to suspend 126757dacad5SJay Sternberg */ 126857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 126957dacad5SJay Sternberg { 127057dacad5SJay Sternberg int vector; 127157dacad5SJay Sternberg 12721ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 127357dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 12741ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 127557dacad5SJay Sternberg return 1; 127657dacad5SJay Sternberg } 12770ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 127857dacad5SJay Sternberg nvmeq->dev->online_queues--; 127957dacad5SJay Sternberg nvmeq->cq_vector = -1; 12801ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 128157dacad5SJay Sternberg 1282d1f06f4aSJens Axboe /* 1283d1f06f4aSJens Axboe * Ensure that nvme_queue_rq() sees it ->cq_vector == -1 without 1284d1f06f4aSJens Axboe * having to grab the lock. 1285d1f06f4aSJens Axboe */ 1286d1f06f4aSJens Axboe mb(); 128757dacad5SJay Sternberg 12881c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1289c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 129057dacad5SJay Sternberg 12910ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 129257dacad5SJay Sternberg 129357dacad5SJay Sternberg return 0; 129457dacad5SJay Sternberg } 129557dacad5SJay Sternberg 1296a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 129757dacad5SJay Sternberg { 1298147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 12995cb525c8SJens Axboe u16 start, end; 130057dacad5SJay Sternberg 1301a5cdb68cSKeith Busch if (shutdown) 1302a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1303a5cdb68cSKeith Busch else 130420d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 130557dacad5SJay Sternberg 13061ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 13075cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 13081ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 13095cb525c8SJens Axboe 13105cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 131157dacad5SJay Sternberg } 131257dacad5SJay Sternberg 131357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 131457dacad5SJay Sternberg int entry_size) 131557dacad5SJay Sternberg { 131657dacad5SJay Sternberg int q_depth = dev->q_depth; 13175fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13185fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 131957dacad5SJay Sternberg 132057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 132157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13225fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 132357dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 132457dacad5SJay Sternberg 132557dacad5SJay Sternberg /* 132657dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 132757dacad5SJay Sternberg * would be better to map queues in system memory with the 132857dacad5SJay Sternberg * original depth 132957dacad5SJay Sternberg */ 133057dacad5SJay Sternberg if (q_depth < 64) 133157dacad5SJay Sternberg return -ENOMEM; 133257dacad5SJay Sternberg } 133357dacad5SJay Sternberg 133457dacad5SJay Sternberg return q_depth; 133557dacad5SJay Sternberg } 133657dacad5SJay Sternberg 133757dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 133857dacad5SJay Sternberg int qid, int depth) 133957dacad5SJay Sternberg { 13400f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1341815c6704SKeith Busch 13420f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 13430f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 13440f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 13450f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 13460f238ff5SLogan Gunthorpe nvmeq->sq_cmds_is_io = true; 13470f238ff5SLogan Gunthorpe } 13480f238ff5SLogan Gunthorpe 13490f238ff5SLogan Gunthorpe if (!nvmeq->sq_cmds) { 135057dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 135157dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 13520f238ff5SLogan Gunthorpe nvmeq->sq_cmds_is_io = false; 13530f238ff5SLogan Gunthorpe } 13540f238ff5SLogan Gunthorpe 135557dacad5SJay Sternberg if (!nvmeq->sq_cmds) 135657dacad5SJay Sternberg return -ENOMEM; 135757dacad5SJay Sternberg return 0; 135857dacad5SJay Sternberg } 135957dacad5SJay Sternberg 1360a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 136157dacad5SJay Sternberg { 1362147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 136357dacad5SJay Sternberg 136462314e40SKeith Busch if (dev->ctrl.queue_count > qid) 136562314e40SKeith Busch return 0; 136657dacad5SJay Sternberg 136757dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 136857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 136957dacad5SJay Sternberg if (!nvmeq->cqes) 137057dacad5SJay Sternberg goto free_nvmeq; 137157dacad5SJay Sternberg 137257dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 137357dacad5SJay Sternberg goto free_cqdma; 137457dacad5SJay Sternberg 137557dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 137657dacad5SJay Sternberg nvmeq->dev = dev; 13771ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 13781ab0cd69SJens Axboe spin_lock_init(&nvmeq->cq_lock); 137957dacad5SJay Sternberg nvmeq->cq_head = 0; 138057dacad5SJay Sternberg nvmeq->cq_phase = 1; 138157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 138257dacad5SJay Sternberg nvmeq->q_depth = depth; 138357dacad5SJay Sternberg nvmeq->qid = qid; 138457dacad5SJay Sternberg nvmeq->cq_vector = -1; 1385d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 138657dacad5SJay Sternberg 1387147b27e4SSagi Grimberg return 0; 138857dacad5SJay Sternberg 138957dacad5SJay Sternberg free_cqdma: 139057dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 139157dacad5SJay Sternberg nvmeq->cq_dma_addr); 139257dacad5SJay Sternberg free_nvmeq: 1393147b27e4SSagi Grimberg return -ENOMEM; 139457dacad5SJay Sternberg } 139557dacad5SJay Sternberg 1396dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 139757dacad5SJay Sternberg { 13980ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 13990ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14000ff199cbSChristoph Hellwig 14010ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14020ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14030ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14040ff199cbSChristoph Hellwig } else { 14050ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14060ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14070ff199cbSChristoph Hellwig } 140857dacad5SJay Sternberg } 140957dacad5SJay Sternberg 141057dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 141157dacad5SJay Sternberg { 141257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 141357dacad5SJay Sternberg 14141ab0cd69SJens Axboe spin_lock_irq(&nvmeq->cq_lock); 141557dacad5SJay Sternberg nvmeq->sq_tail = 0; 141657dacad5SJay Sternberg nvmeq->cq_head = 0; 141757dacad5SJay Sternberg nvmeq->cq_phase = 1; 141857dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 141957dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1420f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 142157dacad5SJay Sternberg dev->online_queues++; 14221ab0cd69SJens Axboe spin_unlock_irq(&nvmeq->cq_lock); 142357dacad5SJay Sternberg } 142457dacad5SJay Sternberg 142557dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 142657dacad5SJay Sternberg { 142757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 142857dacad5SJay Sternberg int result; 1429a8e3e0bbSJianchao Wang s16 vector; 143057dacad5SJay Sternberg 143122b55601SKeith Busch /* 143222b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 143322b55601SKeith Busch * has only one vector available. 143422b55601SKeith Busch */ 1435a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 1436a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1437ded45505SKeith Busch if (result) 1438ded45505SKeith Busch return result; 143957dacad5SJay Sternberg 144057dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 144157dacad5SJay Sternberg if (result < 0) 1442ded45505SKeith Busch return result; 1443ded45505SKeith Busch else if (result) 144457dacad5SJay Sternberg goto release_cq; 144557dacad5SJay Sternberg 1446a8e3e0bbSJianchao Wang /* 1447a8e3e0bbSJianchao Wang * Set cq_vector after alloc cq/sq, otherwise nvme_suspend_queue will 1448a8e3e0bbSJianchao Wang * invoke free_irq for it and cause a 'Trying to free already-free IRQ 1449a8e3e0bbSJianchao Wang * xxx' warning if the create CQ/SQ command times out. 1450a8e3e0bbSJianchao Wang */ 1451a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1452161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1453dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 145457dacad5SJay Sternberg if (result < 0) 145557dacad5SJay Sternberg goto release_sq; 145657dacad5SJay Sternberg 145757dacad5SJay Sternberg return result; 145857dacad5SJay Sternberg 145957dacad5SJay Sternberg release_sq: 1460a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1461f25a2dfcSJianchao Wang dev->online_queues--; 146257dacad5SJay Sternberg adapter_delete_sq(dev, qid); 146357dacad5SJay Sternberg release_cq: 146457dacad5SJay Sternberg adapter_delete_cq(dev, qid); 146557dacad5SJay Sternberg return result; 146657dacad5SJay Sternberg } 146757dacad5SJay Sternberg 1468f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 146957dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 147077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 147157dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 147257dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 14730350815aSChristoph Hellwig .init_request = nvme_init_request, 147457dacad5SJay Sternberg .timeout = nvme_timeout, 147557dacad5SJay Sternberg }; 147657dacad5SJay Sternberg 1477f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 147857dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 147977f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 148057dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 148157dacad5SJay Sternberg .init_request = nvme_init_request, 1482dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 148357dacad5SJay Sternberg .timeout = nvme_timeout, 1484a0fa9647SJens Axboe .poll = nvme_poll, 148557dacad5SJay Sternberg }; 148657dacad5SJay Sternberg 148757dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 148857dacad5SJay Sternberg { 14891c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 149069d9a99cSKeith Busch /* 149169d9a99cSKeith Busch * If the controller was reset during removal, it's possible 149269d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 149369d9a99cSKeith Busch * queue to flush these to completion. 149469d9a99cSKeith Busch */ 1495c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 14961c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 149757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 149857dacad5SJay Sternberg } 149957dacad5SJay Sternberg } 150057dacad5SJay Sternberg 150157dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 150257dacad5SJay Sternberg { 15031c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 150457dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 150557dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1506e3e9d50cSKeith Busch 150738dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 150857dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 150957dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1510a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1511d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 151257dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 151357dacad5SJay Sternberg 151457dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 151557dacad5SJay Sternberg return -ENOMEM; 151634b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 151757dacad5SJay Sternberg 15181c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15191c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 152057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 152157dacad5SJay Sternberg return -ENOMEM; 152257dacad5SJay Sternberg } 15231c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 152457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15251c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 152657dacad5SJay Sternberg return -ENODEV; 152757dacad5SJay Sternberg } 152857dacad5SJay Sternberg } else 1529c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 153057dacad5SJay Sternberg 153157dacad5SJay Sternberg return 0; 153257dacad5SJay Sternberg } 153357dacad5SJay Sternberg 153497f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 153597f6ef64SXu Yu { 153697f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 153797f6ef64SXu Yu } 153897f6ef64SXu Yu 153997f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 154097f6ef64SXu Yu { 154197f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 154297f6ef64SXu Yu 154397f6ef64SXu Yu if (size <= dev->bar_mapped_size) 154497f6ef64SXu Yu return 0; 154597f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 154697f6ef64SXu Yu return -ENOMEM; 154797f6ef64SXu Yu if (dev->bar) 154897f6ef64SXu Yu iounmap(dev->bar); 154997f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 155097f6ef64SXu Yu if (!dev->bar) { 155197f6ef64SXu Yu dev->bar_mapped_size = 0; 155297f6ef64SXu Yu return -ENOMEM; 155397f6ef64SXu Yu } 155497f6ef64SXu Yu dev->bar_mapped_size = size; 155597f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 155697f6ef64SXu Yu 155797f6ef64SXu Yu return 0; 155897f6ef64SXu Yu } 155997f6ef64SXu Yu 156001ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 156157dacad5SJay Sternberg { 156257dacad5SJay Sternberg int result; 156357dacad5SJay Sternberg u32 aqa; 156457dacad5SJay Sternberg struct nvme_queue *nvmeq; 156557dacad5SJay Sternberg 156697f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 156797f6ef64SXu Yu if (result < 0) 156897f6ef64SXu Yu return result; 156997f6ef64SXu Yu 15708ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 157120d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 157257dacad5SJay Sternberg 15737a67cbeaSChristoph Hellwig if (dev->subsystem && 15747a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 15757a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 157657dacad5SJay Sternberg 157720d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 157857dacad5SJay Sternberg if (result < 0) 157957dacad5SJay Sternberg return result; 158057dacad5SJay Sternberg 1581a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1582147b27e4SSagi Grimberg if (result) 1583147b27e4SSagi Grimberg return result; 158457dacad5SJay Sternberg 1585147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 158657dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 158757dacad5SJay Sternberg aqa |= aqa << 16; 158857dacad5SJay Sternberg 15897a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 15907a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 15917a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 159257dacad5SJay Sternberg 159320d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 159457dacad5SJay Sternberg if (result) 1595d4875622SKeith Busch return result; 159657dacad5SJay Sternberg 159757dacad5SJay Sternberg nvmeq->cq_vector = 0; 1598161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1599dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 160057dacad5SJay Sternberg if (result) { 160157dacad5SJay Sternberg nvmeq->cq_vector = -1; 1602d4875622SKeith Busch return result; 160357dacad5SJay Sternberg } 160457dacad5SJay Sternberg 160557dacad5SJay Sternberg return result; 160657dacad5SJay Sternberg } 160757dacad5SJay Sternberg 1608749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 160957dacad5SJay Sternberg { 1610949928c1SKeith Busch unsigned i, max; 1611749941f2SChristoph Hellwig int ret = 0; 161257dacad5SJay Sternberg 1613d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1614a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1615749941f2SChristoph Hellwig ret = -ENOMEM; 161657dacad5SJay Sternberg break; 1617749941f2SChristoph Hellwig } 1618749941f2SChristoph Hellwig } 161957dacad5SJay Sternberg 1620d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1621949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1622147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1623d4875622SKeith Busch if (ret) 162457dacad5SJay Sternberg break; 162557dacad5SJay Sternberg } 162657dacad5SJay Sternberg 1627749941f2SChristoph Hellwig /* 1628749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16298adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16308adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1631749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1632749941f2SChristoph Hellwig */ 1633749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 163457dacad5SJay Sternberg } 163557dacad5SJay Sternberg 1636202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1637202021c1SStephen Bates struct device_attribute *attr, 1638202021c1SStephen Bates char *buf) 1639202021c1SStephen Bates { 1640202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1641202021c1SStephen Bates 1642c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1643202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1644202021c1SStephen Bates } 1645202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1646202021c1SStephen Bates 164788de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 164857dacad5SJay Sternberg { 164988de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 165088de4598SChristoph Hellwig 165188de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 165288de4598SChristoph Hellwig } 165388de4598SChristoph Hellwig 165488de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 165588de4598SChristoph Hellwig { 165688de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 165788de4598SChristoph Hellwig } 165888de4598SChristoph Hellwig 1659f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 166057dacad5SJay Sternberg { 166188de4598SChristoph Hellwig u64 size, offset; 166257dacad5SJay Sternberg resource_size_t bar_size; 166357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 16648969f1f8SChristoph Hellwig int bar; 166557dacad5SJay Sternberg 16669fe5c59fSKeith Busch if (dev->cmb_size) 16679fe5c59fSKeith Busch return; 16689fe5c59fSKeith Busch 16697a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1670f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1671f65efd6dSChristoph Hellwig return; 1672202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 167357dacad5SJay Sternberg 167488de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 167588de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 16768969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 16778969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 167857dacad5SJay Sternberg 167957dacad5SJay Sternberg if (offset > bar_size) 1680f65efd6dSChristoph Hellwig return; 168157dacad5SJay Sternberg 168257dacad5SJay Sternberg /* 168357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 168457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 168557dacad5SJay Sternberg * the reported size of the BAR 168657dacad5SJay Sternberg */ 168757dacad5SJay Sternberg if (size > bar_size - offset) 168857dacad5SJay Sternberg size = bar_size - offset; 168957dacad5SJay Sternberg 16900f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 16910f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 16920f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1693f65efd6dSChristoph Hellwig return; 16940f238ff5SLogan Gunthorpe } 16950f238ff5SLogan Gunthorpe 169657dacad5SJay Sternberg dev->cmb_size = size; 16970f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 16980f238ff5SLogan Gunthorpe 16990f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 17000f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 17010f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1702f65efd6dSChristoph Hellwig 1703f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1704f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1705f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1706f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 170757dacad5SJay Sternberg } 170857dacad5SJay Sternberg 170957dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 171057dacad5SJay Sternberg { 17110f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1712f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1713f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 17140f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1715f63572dfSJon Derrick } 171657dacad5SJay Sternberg } 171757dacad5SJay Sternberg 171887ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 171957dacad5SJay Sternberg { 17204033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 172187ad72a5SChristoph Hellwig struct nvme_command c; 172287ad72a5SChristoph Hellwig int ret; 172387ad72a5SChristoph Hellwig 172487ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 172587ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 172687ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 172787ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 172887ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 172987ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 173087ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 173187ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 173287ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 173387ad72a5SChristoph Hellwig 173487ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 173587ad72a5SChristoph Hellwig if (ret) { 173687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 173787ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 173887ad72a5SChristoph Hellwig ret, bits); 173987ad72a5SChristoph Hellwig } 174087ad72a5SChristoph Hellwig return ret; 174187ad72a5SChristoph Hellwig } 174287ad72a5SChristoph Hellwig 174387ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 174487ad72a5SChristoph Hellwig { 174587ad72a5SChristoph Hellwig int i; 174687ad72a5SChristoph Hellwig 174787ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 174887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 174987ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 175087ad72a5SChristoph Hellwig 175187ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 175287ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 175387ad72a5SChristoph Hellwig } 175487ad72a5SChristoph Hellwig 175587ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 175687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17574033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17584033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 17594033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 176087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 17617e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 176287ad72a5SChristoph Hellwig } 176387ad72a5SChristoph Hellwig 176492dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 176592dc6895SChristoph Hellwig u32 chunk_size) 176687ad72a5SChristoph Hellwig { 176787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 176892dc6895SChristoph Hellwig u32 max_entries, len; 17694033f35dSChristoph Hellwig dma_addr_t descs_dma; 17702ee0e4edSDan Carpenter int i = 0; 177187ad72a5SChristoph Hellwig void **bufs; 17726fbcde66SMinwoo Im u64 size, tmp; 177387ad72a5SChristoph Hellwig 177487ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 177587ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 177687ad72a5SChristoph Hellwig max_entries = tmp; 1777044a9df1SChristoph Hellwig 1778044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1779044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1780044a9df1SChristoph Hellwig 17814033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 17824033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 178387ad72a5SChristoph Hellwig if (!descs) 178487ad72a5SChristoph Hellwig goto out; 178587ad72a5SChristoph Hellwig 178687ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 178787ad72a5SChristoph Hellwig if (!bufs) 178887ad72a5SChristoph Hellwig goto out_free_descs; 178987ad72a5SChristoph Hellwig 1790244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 179187ad72a5SChristoph Hellwig dma_addr_t dma_addr; 179287ad72a5SChristoph Hellwig 179350cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 179487ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 179587ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 179687ad72a5SChristoph Hellwig if (!bufs[i]) 179787ad72a5SChristoph Hellwig break; 179887ad72a5SChristoph Hellwig 179987ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 180087ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 180187ad72a5SChristoph Hellwig i++; 180287ad72a5SChristoph Hellwig } 180387ad72a5SChristoph Hellwig 180492dc6895SChristoph Hellwig if (!size) 180587ad72a5SChristoph Hellwig goto out_free_bufs; 180687ad72a5SChristoph Hellwig 180787ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 180887ad72a5SChristoph Hellwig dev->host_mem_size = size; 180987ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 18104033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 181187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 181287ad72a5SChristoph Hellwig return 0; 181387ad72a5SChristoph Hellwig 181487ad72a5SChristoph Hellwig out_free_bufs: 181587ad72a5SChristoph Hellwig while (--i >= 0) { 181687ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 181787ad72a5SChristoph Hellwig 181887ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 181987ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 182087ad72a5SChristoph Hellwig } 182187ad72a5SChristoph Hellwig 182287ad72a5SChristoph Hellwig kfree(bufs); 182387ad72a5SChristoph Hellwig out_free_descs: 18244033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18254033f35dSChristoph Hellwig descs_dma); 182687ad72a5SChristoph Hellwig out: 182787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 182887ad72a5SChristoph Hellwig return -ENOMEM; 182987ad72a5SChristoph Hellwig } 183087ad72a5SChristoph Hellwig 183192dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 183292dc6895SChristoph Hellwig { 183392dc6895SChristoph Hellwig u32 chunk_size; 183492dc6895SChristoph Hellwig 183592dc6895SChristoph Hellwig /* start big and work our way down */ 183630f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1837044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 183892dc6895SChristoph Hellwig chunk_size /= 2) { 183992dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 184092dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 184192dc6895SChristoph Hellwig return 0; 184292dc6895SChristoph Hellwig nvme_free_host_mem(dev); 184392dc6895SChristoph Hellwig } 184492dc6895SChristoph Hellwig } 184592dc6895SChristoph Hellwig 184692dc6895SChristoph Hellwig return -ENOMEM; 184792dc6895SChristoph Hellwig } 184892dc6895SChristoph Hellwig 18499620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 185087ad72a5SChristoph Hellwig { 185187ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 185287ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 185387ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 185487ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18556fbcde66SMinwoo Im int ret; 185687ad72a5SChristoph Hellwig 185787ad72a5SChristoph Hellwig preferred = min(preferred, max); 185887ad72a5SChristoph Hellwig if (min > max) { 185987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 186087ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 186187ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 186287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18639620cfbaSChristoph Hellwig return 0; 186487ad72a5SChristoph Hellwig } 186587ad72a5SChristoph Hellwig 186687ad72a5SChristoph Hellwig /* 186787ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 186887ad72a5SChristoph Hellwig */ 186987ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 187087ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 187187ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 187287ad72a5SChristoph Hellwig else 187387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 187487ad72a5SChristoph Hellwig } 187587ad72a5SChristoph Hellwig 187687ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 187792dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 187892dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 187992dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 18809620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 188187ad72a5SChristoph Hellwig } 188287ad72a5SChristoph Hellwig 188392dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 188492dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 188592dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 188692dc6895SChristoph Hellwig } 188792dc6895SChristoph Hellwig 18889620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 18899620cfbaSChristoph Hellwig if (ret) 189087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18919620cfbaSChristoph Hellwig return ret; 189257dacad5SJay Sternberg } 189357dacad5SJay Sternberg 189457dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 189557dacad5SJay Sternberg { 1896147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 189757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 189897f6ef64SXu Yu int result, nr_io_queues; 189997f6ef64SXu Yu unsigned long size; 190057dacad5SJay Sternberg 190122b55601SKeith Busch struct irq_affinity affd = { 190222b55601SKeith Busch .pre_vectors = 1 190322b55601SKeith Busch }; 190422b55601SKeith Busch 190516ccfff2SMing Lei nr_io_queues = num_possible_cpus(); 19069a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 19079a0be7abSChristoph Hellwig if (result < 0) 190857dacad5SJay Sternberg return result; 19099a0be7abSChristoph Hellwig 1910f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1911a5229050SKeith Busch return 0; 191257dacad5SJay Sternberg 19130f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 191457dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 191557dacad5SJay Sternberg sizeof(struct nvme_command)); 191657dacad5SJay Sternberg if (result > 0) 191757dacad5SJay Sternberg dev->q_depth = result; 191857dacad5SJay Sternberg else 19190f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 192057dacad5SJay Sternberg } 192157dacad5SJay Sternberg 192257dacad5SJay Sternberg do { 192397f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 192497f6ef64SXu Yu result = nvme_remap_bar(dev, size); 192597f6ef64SXu Yu if (!result) 192657dacad5SJay Sternberg break; 192757dacad5SJay Sternberg if (!--nr_io_queues) 192857dacad5SJay Sternberg return -ENOMEM; 192957dacad5SJay Sternberg } while (1); 193057dacad5SJay Sternberg adminq->q_db = dev->dbs; 193157dacad5SJay Sternberg 193257dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19330ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 193457dacad5SJay Sternberg 193557dacad5SJay Sternberg /* 193657dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 193757dacad5SJay Sternberg * setting up the full range we need. 193857dacad5SJay Sternberg */ 1939dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 194022b55601SKeith Busch result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 194122b55601SKeith Busch PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 194222b55601SKeith Busch if (result <= 0) 1943dca51e78SChristoph Hellwig return -EIO; 194422b55601SKeith Busch dev->num_vecs = result; 194522b55601SKeith Busch dev->max_qid = max(result - 1, 1); 194657dacad5SJay Sternberg 194757dacad5SJay Sternberg /* 194857dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 194957dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 195057dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 195157dacad5SJay Sternberg * number of interrupts. 195257dacad5SJay Sternberg */ 195357dacad5SJay Sternberg 1954dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 195557dacad5SJay Sternberg if (result) { 195657dacad5SJay Sternberg adminq->cq_vector = -1; 1957d4875622SKeith Busch return result; 195857dacad5SJay Sternberg } 1959749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 196057dacad5SJay Sternberg } 196157dacad5SJay Sternberg 19622a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1963db3cbfffSKeith Busch { 1964db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1965db3cbfffSKeith Busch 1966db3cbfffSKeith Busch blk_mq_free_request(req); 1967db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1968db3cbfffSKeith Busch } 1969db3cbfffSKeith Busch 19702a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1971db3cbfffSKeith Busch { 1972db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 19735cb525c8SJens Axboe u16 start, end; 1974db3cbfffSKeith Busch 1975db3cbfffSKeith Busch if (!error) { 1976db3cbfffSKeith Busch unsigned long flags; 1977db3cbfffSKeith Busch 19780bc88192SKeith Busch spin_lock_irqsave(&nvmeq->cq_lock, flags); 19795cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 19801ab0cd69SJens Axboe spin_unlock_irqrestore(&nvmeq->cq_lock, flags); 19815cb525c8SJens Axboe 19825cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1983db3cbfffSKeith Busch } 1984db3cbfffSKeith Busch 1985db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1986db3cbfffSKeith Busch } 1987db3cbfffSKeith Busch 1988db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1989db3cbfffSKeith Busch { 1990db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1991db3cbfffSKeith Busch struct request *req; 1992db3cbfffSKeith Busch struct nvme_command cmd; 1993db3cbfffSKeith Busch 1994db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1995db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1996db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1997db3cbfffSKeith Busch 1998eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1999db3cbfffSKeith Busch if (IS_ERR(req)) 2000db3cbfffSKeith Busch return PTR_ERR(req); 2001db3cbfffSKeith Busch 2002db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2003db3cbfffSKeith Busch req->end_io_data = nvmeq; 2004db3cbfffSKeith Busch 2005db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2006db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2007db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2008db3cbfffSKeith Busch return 0; 2009db3cbfffSKeith Busch } 2010db3cbfffSKeith Busch 2011ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2012db3cbfffSKeith Busch { 2013ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2014db3cbfffSKeith Busch unsigned long timeout; 2015db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2016db3cbfffSKeith Busch 2017db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2018014a0d60SKeith Busch int sent = 0, i = queues; 2019db3cbfffSKeith Busch 2020db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2021db3cbfffSKeith Busch retry: 2022db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2023c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2024147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2025db3cbfffSKeith Busch break; 2026c21377f8SGabriel Krisman Bertazi 2027db3cbfffSKeith Busch while (sent--) { 2028db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2029db3cbfffSKeith Busch if (timeout == 0) 2030db3cbfffSKeith Busch return; 2031db3cbfffSKeith Busch if (i) 2032db3cbfffSKeith Busch goto retry; 2033db3cbfffSKeith Busch } 2034db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2035db3cbfffSKeith Busch } 2036db3cbfffSKeith Busch } 2037db3cbfffSKeith Busch 203857dacad5SJay Sternberg /* 20392b1b7e78SJianchao Wang * return error value only when tagset allocation failed 204057dacad5SJay Sternberg */ 204157dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 204257dacad5SJay Sternberg { 20432b1b7e78SJianchao Wang int ret; 20442b1b7e78SJianchao Wang 20455bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 204657dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 204757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 204857dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 204957dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 205057dacad5SJay Sternberg dev->tagset.queue_depth = 205157dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2052a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2053a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2054a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2055a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2056a7a7cbe3SChaitanya Kulkarni } 205757dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 205857dacad5SJay Sternberg dev->tagset.driver_data = dev; 205957dacad5SJay Sternberg 20602b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 20612b1b7e78SJianchao Wang if (ret) { 20622b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 20632b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 20642b1b7e78SJianchao Wang return ret; 20652b1b7e78SJianchao Wang } 20665bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2067f9f38e33SHelen Koike 2068f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2069949928c1SKeith Busch } else { 2070949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2071949928c1SKeith Busch 2072949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2073949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 207457dacad5SJay Sternberg } 2075949928c1SKeith Busch 207657dacad5SJay Sternberg return 0; 207757dacad5SJay Sternberg } 207857dacad5SJay Sternberg 2079b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 208057dacad5SJay Sternberg { 2081b00a726aSKeith Busch int result = -ENOMEM; 208257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 208357dacad5SJay Sternberg 208457dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 208557dacad5SJay Sternberg return result; 208657dacad5SJay Sternberg 208757dacad5SJay Sternberg pci_set_master(pdev); 208857dacad5SJay Sternberg 208957dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 209057dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 209157dacad5SJay Sternberg goto disable; 209257dacad5SJay Sternberg 20937a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 209457dacad5SJay Sternberg result = -ENODEV; 2095b00a726aSKeith Busch goto disable; 209657dacad5SJay Sternberg } 209757dacad5SJay Sternberg 209857dacad5SJay Sternberg /* 2099a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2100a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2101a5229050SKeith Busch * adjust this later. 210257dacad5SJay Sternberg */ 2103dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2104dca51e78SChristoph Hellwig if (result < 0) 2105dca51e78SChristoph Hellwig return result; 210657dacad5SJay Sternberg 210720d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 21087a67cbeaSChristoph Hellwig 210920d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2110b27c1e68Sweiping zhang io_queue_depth); 211120d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21127a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21131f390c1fSStephan Günther 21141f390c1fSStephan Günther /* 21151f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21161f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21171f390c1fSStephan Günther */ 21181f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21191f390c1fSStephan Günther dev->q_depth = 2; 21209bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21219bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21221f390c1fSStephan Günther dev->q_depth); 2123d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2124d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 212520d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2126d554b5e1SMartin K. Petersen dev->q_depth = 64; 2127d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2128d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21291f390c1fSStephan Günther } 21301f390c1fSStephan Günther 2131f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2132202021c1SStephen Bates 2133a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2134a0a3408eSKeith Busch pci_save_state(pdev); 213557dacad5SJay Sternberg return 0; 213657dacad5SJay Sternberg 213757dacad5SJay Sternberg disable: 213857dacad5SJay Sternberg pci_disable_device(pdev); 213957dacad5SJay Sternberg return result; 214057dacad5SJay Sternberg } 214157dacad5SJay Sternberg 214257dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 214357dacad5SJay Sternberg { 2144b00a726aSKeith Busch if (dev->bar) 2145b00a726aSKeith Busch iounmap(dev->bar); 2146a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2147b00a726aSKeith Busch } 2148b00a726aSKeith Busch 2149b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2150b00a726aSKeith Busch { 215157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 215257dacad5SJay Sternberg 2153dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 215457dacad5SJay Sternberg 2155a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2156a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 215757dacad5SJay Sternberg pci_disable_device(pdev); 215857dacad5SJay Sternberg } 2159a0a3408eSKeith Busch } 216057dacad5SJay Sternberg 2161a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 216257dacad5SJay Sternberg { 2163ee9aebb2SKeith Busch int i; 2164302ad8ccSKeith Busch bool dead = true; 2165302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 216657dacad5SJay Sternberg 216777bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2168302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2169302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2170302ad8ccSKeith Busch 2171ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2172ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2173302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2174302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2175302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 217657dacad5SJay Sternberg } 2177c21377f8SGabriel Krisman Bertazi 2178302ad8ccSKeith Busch /* 2179302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2180302ad8ccSKeith Busch * doing a safe shutdown. 2181302ad8ccSKeith Busch */ 218287ad72a5SChristoph Hellwig if (!dead) { 218387ad72a5SChristoph Hellwig if (shutdown) 2184302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 21859a915a5bSJianchao Wang } 218687ad72a5SChristoph Hellwig 21879a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 21889a915a5bSJianchao Wang 218964ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 2190ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2191a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 219257dacad5SJay Sternberg } 2193ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2194ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2195ee9aebb2SKeith Busch 2196b00a726aSKeith Busch nvme_pci_disable(dev); 219757dacad5SJay Sternberg 2198e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2199e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2200302ad8ccSKeith Busch 2201302ad8ccSKeith Busch /* 2202302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2203302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2204302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2205302ad8ccSKeith Busch */ 2206302ad8ccSKeith Busch if (shutdown) 2207302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 220877bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 220957dacad5SJay Sternberg } 221057dacad5SJay Sternberg 221157dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 221257dacad5SJay Sternberg { 221357dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 221457dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 221557dacad5SJay Sternberg if (!dev->prp_page_pool) 221657dacad5SJay Sternberg return -ENOMEM; 221757dacad5SJay Sternberg 221857dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 221957dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 222057dacad5SJay Sternberg 256, 256, 0); 222157dacad5SJay Sternberg if (!dev->prp_small_pool) { 222257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 222357dacad5SJay Sternberg return -ENOMEM; 222457dacad5SJay Sternberg } 222557dacad5SJay Sternberg return 0; 222657dacad5SJay Sternberg } 222757dacad5SJay Sternberg 222857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 222957dacad5SJay Sternberg { 223057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 223157dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 223257dacad5SJay Sternberg } 223357dacad5SJay Sternberg 22341673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 223557dacad5SJay Sternberg { 22361673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 223757dacad5SJay Sternberg 2238f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 223957dacad5SJay Sternberg put_device(dev->dev); 224057dacad5SJay Sternberg if (dev->tagset.tags) 224157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22421c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22431c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 224457dacad5SJay Sternberg kfree(dev->queues); 2245e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2246943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 224757dacad5SJay Sternberg kfree(dev); 224857dacad5SJay Sternberg } 224957dacad5SJay Sternberg 2250f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2251f58944e2SKeith Busch { 2252237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2253f58944e2SKeith Busch 2254d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 225569d9a99cSKeith Busch nvme_dev_disable(dev, false); 22569f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 225703e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2258f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2259f58944e2SKeith Busch } 2260f58944e2SKeith Busch 2261fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 226257dacad5SJay Sternberg { 2263d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2264d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2265a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2266f58944e2SKeith Busch int result = -ENODEV; 22672b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 226857dacad5SJay Sternberg 226982b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2270fd634f41SChristoph Hellwig goto out; 2271fd634f41SChristoph Hellwig 2272fd634f41SChristoph Hellwig /* 2273fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2274fd634f41SChristoph Hellwig * moving on. 2275fd634f41SChristoph Hellwig */ 2276b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2277a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2278fd634f41SChristoph Hellwig 2279ad70062cSJianchao Wang /* 2280ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2281ad70062cSJianchao Wang * initializing procedure here. 2282ad70062cSJianchao Wang */ 2283ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2284ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2285ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2286ad70062cSJianchao Wang goto out; 2287ad70062cSJianchao Wang } 2288ad70062cSJianchao Wang 2289b00a726aSKeith Busch result = nvme_pci_enable(dev); 229057dacad5SJay Sternberg if (result) 229157dacad5SJay Sternberg goto out; 229257dacad5SJay Sternberg 229301ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 229457dacad5SJay Sternberg if (result) 2295f58944e2SKeith Busch goto out; 229657dacad5SJay Sternberg 229757dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 229857dacad5SJay Sternberg if (result) 2299f58944e2SKeith Busch goto out; 230057dacad5SJay Sternberg 2301943e942eSJens Axboe /* 2302943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2303943e942eSJens Axboe * over a single page. 2304943e942eSJens Axboe */ 2305943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2306943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2307943e942eSJens Axboe 2308ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2309ce4541f4SChristoph Hellwig if (result) 2310f58944e2SKeith Busch goto out; 2311ce4541f4SChristoph Hellwig 2312e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2313e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23144f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23154f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2316e286bcfcSScott Bauer else if (was_suspend) 23174f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2318e286bcfcSScott Bauer } else { 2319e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2320e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2321e286bcfcSScott Bauer } 2322a98e58e5SScott Bauer 2323f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2324f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2325f9f38e33SHelen Koike if (result) 2326f9f38e33SHelen Koike dev_warn(dev->dev, 2327f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2328f9f38e33SHelen Koike } 2329f9f38e33SHelen Koike 23309620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23319620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23329620cfbaSChristoph Hellwig if (result < 0) 23339620cfbaSChristoph Hellwig goto out; 23349620cfbaSChristoph Hellwig } 233587ad72a5SChristoph Hellwig 233657dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 233757dacad5SJay Sternberg if (result) 2338f58944e2SKeith Busch goto out; 233957dacad5SJay Sternberg 234021f033f7SKeith Busch /* 234157dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 234257dacad5SJay Sternberg * any working I/O queue. 234357dacad5SJay Sternberg */ 234457dacad5SJay Sternberg if (dev->online_queues < 2) { 23451b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23463b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23475bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23482b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 234957dacad5SJay Sternberg } else { 235025646264SKeith Busch nvme_start_queues(&dev->ctrl); 2351302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23522b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23532b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23542b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2355302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 235657dacad5SJay Sternberg } 235757dacad5SJay Sternberg 23582b1b7e78SJianchao Wang /* 23592b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 23602b1b7e78SJianchao Wang * recovery. 23612b1b7e78SJianchao Wang */ 23622b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 23632b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23642b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2365bb8d261eSChristoph Hellwig goto out; 2366bb8d261eSChristoph Hellwig } 236792911a55SChristoph Hellwig 2368d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 236957dacad5SJay Sternberg return; 237057dacad5SJay Sternberg 237157dacad5SJay Sternberg out: 2372f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 237357dacad5SJay Sternberg } 237457dacad5SJay Sternberg 23755c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 237657dacad5SJay Sternberg { 23775c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 237857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 237957dacad5SJay Sternberg 238057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2381921920abSKeith Busch device_release_driver(&pdev->dev); 23821673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 238357dacad5SJay Sternberg } 238457dacad5SJay Sternberg 23851c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 238657dacad5SJay Sternberg { 23871c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 23881c63dc66SChristoph Hellwig return 0; 238957dacad5SJay Sternberg } 23901c63dc66SChristoph Hellwig 23915fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 23925fd4ce1bSChristoph Hellwig { 23935fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 23945fd4ce1bSChristoph Hellwig return 0; 23955fd4ce1bSChristoph Hellwig } 23965fd4ce1bSChristoph Hellwig 23977fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 23987fd8930fSChristoph Hellwig { 23997fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24007fd8930fSChristoph Hellwig return 0; 24017fd8930fSChristoph Hellwig } 24027fd8930fSChristoph Hellwig 240397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 240497c12223SKeith Busch { 240597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 240697c12223SKeith Busch 240797c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 240897c12223SKeith Busch } 240997c12223SKeith Busch 24101c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24111a353d85SMing Lin .name = "pcie", 2412e439bb12SSagi Grimberg .module = THIS_MODULE, 2413e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2414e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 24151c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24165fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24177fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24181673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2419f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 242097c12223SKeith Busch .get_address = nvme_pci_get_address, 24211c63dc66SChristoph Hellwig }; 242257dacad5SJay Sternberg 2423b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2424b00a726aSKeith Busch { 2425b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2426b00a726aSKeith Busch 2427a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2428b00a726aSKeith Busch return -ENODEV; 2429b00a726aSKeith Busch 243097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2431b00a726aSKeith Busch goto release; 2432b00a726aSKeith Busch 2433b00a726aSKeith Busch return 0; 2434b00a726aSKeith Busch release: 2435a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2436b00a726aSKeith Busch return -ENODEV; 2437b00a726aSKeith Busch } 2438b00a726aSKeith Busch 24398427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2440ff5350a8SAndy Lutomirski { 2441ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2442ff5350a8SAndy Lutomirski /* 2443ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2444ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2445ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2446ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2447ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2448ff5350a8SAndy Lutomirski * laptops. 2449ff5350a8SAndy Lutomirski */ 2450ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2451ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2452ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2453ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24548427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24558427bbc2SKai-Heng Feng /* 24568427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2457467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2458467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2459467c77d4SJarosław Janik * ASUS PRIME Z370-A 24608427bbc2SKai-Heng Feng */ 24618427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2462467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2463467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 24648427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2465ff5350a8SAndy Lutomirski } 2466ff5350a8SAndy Lutomirski 2467ff5350a8SAndy Lutomirski return 0; 2468ff5350a8SAndy Lutomirski } 2469ff5350a8SAndy Lutomirski 247018119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 247118119775SKeith Busch { 247218119775SKeith Busch struct nvme_dev *dev = data; 247380f513b5SKeith Busch 247418119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 247518119775SKeith Busch flush_work(&dev->ctrl.scan_work); 247680f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 247718119775SKeith Busch } 247818119775SKeith Busch 247957dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 248057dacad5SJay Sternberg { 248157dacad5SJay Sternberg int node, result = -ENOMEM; 248257dacad5SJay Sternberg struct nvme_dev *dev; 2483ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2484943e942eSJens Axboe size_t alloc_size; 248557dacad5SJay Sternberg 248657dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 248757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 24882fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 248957dacad5SJay Sternberg 249057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 249157dacad5SJay Sternberg if (!dev) 249257dacad5SJay Sternberg return -ENOMEM; 2493147b27e4SSagi Grimberg 2494147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2495147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 249657dacad5SJay Sternberg if (!dev->queues) 249757dacad5SJay Sternberg goto free; 249857dacad5SJay Sternberg 249957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 250057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 250157dacad5SJay Sternberg 2502b00a726aSKeith Busch result = nvme_dev_map(dev); 2503b00a726aSKeith Busch if (result) 2504b00c9b7aSChristophe JAILLET goto put_pci; 2505b00a726aSKeith Busch 2506d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 25075c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 250877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2509db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2510f3ca80fcSChristoph Hellwig 2511f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2512f3ca80fcSChristoph Hellwig if (result) 2513b00c9b7aSChristophe JAILLET goto unmap; 2514f3ca80fcSChristoph Hellwig 25158427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2516ff5350a8SAndy Lutomirski 2517943e942eSJens Axboe /* 2518943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2519943e942eSJens Axboe * command we support. 2520943e942eSJens Axboe */ 2521943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2522943e942eSJens Axboe NVME_MAX_SEGS, true); 2523943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2524943e942eSJens Axboe 2525943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2526943e942eSJens Axboe mempool_kfree, 2527943e942eSJens Axboe (void *) alloc_size, 2528943e942eSJens Axboe GFP_KERNEL, node); 2529943e942eSJens Axboe if (!dev->iod_mempool) { 2530943e942eSJens Axboe result = -ENOMEM; 2531943e942eSJens Axboe goto release_pools; 2532943e942eSJens Axboe } 2533943e942eSJens Axboe 2534b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2535b6e44b4cSKeith Busch quirks); 2536b6e44b4cSKeith Busch if (result) 2537b6e44b4cSKeith Busch goto release_mempool; 2538b6e44b4cSKeith Busch 25391b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25401b3c47c1SSagi Grimberg 254180f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 254218119775SKeith Busch async_schedule(nvme_async_probe, dev); 25434caff8fcSSagi Grimberg 254457dacad5SJay Sternberg return 0; 254557dacad5SJay Sternberg 2546b6e44b4cSKeith Busch release_mempool: 2547b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 254857dacad5SJay Sternberg release_pools: 254957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2550b00c9b7aSChristophe JAILLET unmap: 2551b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 255257dacad5SJay Sternberg put_pci: 255357dacad5SJay Sternberg put_device(dev->dev); 255457dacad5SJay Sternberg free: 255557dacad5SJay Sternberg kfree(dev->queues); 255657dacad5SJay Sternberg kfree(dev); 255757dacad5SJay Sternberg return result; 255857dacad5SJay Sternberg } 255957dacad5SJay Sternberg 2560775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 256157dacad5SJay Sternberg { 256257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2563a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2564775755edSChristoph Hellwig } 256557dacad5SJay Sternberg 2566775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2567775755edSChristoph Hellwig { 2568f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 256979c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 257057dacad5SJay Sternberg } 257157dacad5SJay Sternberg 257257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 257357dacad5SJay Sternberg { 257457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2575a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 257657dacad5SJay Sternberg } 257757dacad5SJay Sternberg 2578f58944e2SKeith Busch /* 2579f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2580f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2581f58944e2SKeith Busch * order to proceed. 2582f58944e2SKeith Busch */ 258357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 258457dacad5SJay Sternberg { 258557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 258657dacad5SJay Sternberg 2587bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 258857dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 25890ff9d4e1SKeith Busch 25906db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 25910ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 25921d39e692SKeith Busch nvme_dev_disable(dev, true); 2593cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 25946db28edaSKeith Busch } 25950ff9d4e1SKeith Busch 2596d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2597d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2598d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2599a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 26009fe5c59fSKeith Busch nvme_release_cmb(dev); 260187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 260257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 260357dacad5SJay Sternberg nvme_free_queues(dev, 0); 2604d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 260557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2606b00a726aSKeith Busch nvme_dev_unmap(dev); 26071673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 260857dacad5SJay Sternberg } 260957dacad5SJay Sternberg 261057dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 261157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 261257dacad5SJay Sternberg { 261357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 261457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 261557dacad5SJay Sternberg 2616a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 261757dacad5SJay Sternberg return 0; 261857dacad5SJay Sternberg } 261957dacad5SJay Sternberg 262057dacad5SJay Sternberg static int nvme_resume(struct device *dev) 262157dacad5SJay Sternberg { 262257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 262357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 262457dacad5SJay Sternberg 2625d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 262657dacad5SJay Sternberg return 0; 262757dacad5SJay Sternberg } 262857dacad5SJay Sternberg #endif 262957dacad5SJay Sternberg 263057dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 263157dacad5SJay Sternberg 2632a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2633a0a3408eSKeith Busch pci_channel_state_t state) 2634a0a3408eSKeith Busch { 2635a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2636a0a3408eSKeith Busch 2637a0a3408eSKeith Busch /* 2638a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2639a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2640a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2641a0a3408eSKeith Busch */ 2642a0a3408eSKeith Busch switch (state) { 2643a0a3408eSKeith Busch case pci_channel_io_normal: 2644a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2645a0a3408eSKeith Busch case pci_channel_io_frozen: 2646d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2647d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2648a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2649a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2650a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2651d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2652d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2653a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2654a0a3408eSKeith Busch } 2655a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2656a0a3408eSKeith Busch } 2657a0a3408eSKeith Busch 2658a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2659a0a3408eSKeith Busch { 2660a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2661a0a3408eSKeith Busch 26621b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2663a0a3408eSKeith Busch pci_restore_state(pdev); 2664d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2665a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2666a0a3408eSKeith Busch } 2667a0a3408eSKeith Busch 2668a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2669a0a3408eSKeith Busch { 267072cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 267172cd4cc2SKeith Busch 267272cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2673a0a3408eSKeith Busch } 2674a0a3408eSKeith Busch 267557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 267657dacad5SJay Sternberg .error_detected = nvme_error_detected, 267757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 267857dacad5SJay Sternberg .resume = nvme_error_resume, 2679775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2680775755edSChristoph Hellwig .reset_done = nvme_reset_done, 268157dacad5SJay Sternberg }; 268257dacad5SJay Sternberg 268357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2684106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 268508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2686e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 268799466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 268899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2689e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 269099466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 269199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2692e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2693f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2694f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2695f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 269650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 26979abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 26989abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2699540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2700540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 27010302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 27020302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 270354adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 270454adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 27058c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 27068c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2707015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2708015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2709d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2710d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2711d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2712d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2713608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2714608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2715608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2716608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2717ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2718ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 271957dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2720c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2721124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 272257dacad5SJay Sternberg { 0, } 272357dacad5SJay Sternberg }; 272457dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 272557dacad5SJay Sternberg 272657dacad5SJay Sternberg static struct pci_driver nvme_driver = { 272757dacad5SJay Sternberg .name = "nvme", 272857dacad5SJay Sternberg .id_table = nvme_id_table, 272957dacad5SJay Sternberg .probe = nvme_probe, 273057dacad5SJay Sternberg .remove = nvme_remove, 273157dacad5SJay Sternberg .shutdown = nvme_shutdown, 273257dacad5SJay Sternberg .driver = { 273357dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 273457dacad5SJay Sternberg }, 273574d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 273657dacad5SJay Sternberg .err_handler = &nvme_err_handler, 273757dacad5SJay Sternberg }; 273857dacad5SJay Sternberg 273957dacad5SJay Sternberg static int __init nvme_init(void) 274057dacad5SJay Sternberg { 27419a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 274257dacad5SJay Sternberg } 274357dacad5SJay Sternberg 274457dacad5SJay Sternberg static void __exit nvme_exit(void) 274557dacad5SJay Sternberg { 274657dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 274703e0f3a6SMing Lei flush_workqueue(nvme_wq); 274857dacad5SJay Sternberg _nvme_check_size(); 274957dacad5SJay Sternberg } 275057dacad5SJay Sternberg 275157dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 275257dacad5SJay Sternberg MODULE_LICENSE("GPL"); 275357dacad5SJay Sternberg MODULE_VERSION("1.0"); 275457dacad5SJay Sternberg module_init(nvme_init); 275557dacad5SJay Sternberg module_exit(nvme_exit); 2756