15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 18dc90f084SChristoph Hellwig #include <linux/memremap.h> 1957dacad5SJay Sternberg #include <linux/mm.h> 2057dacad5SJay Sternberg #include <linux/module.h> 2177bf25eaSKeith Busch #include <linux/mutex.h> 22d0877473SKeith Busch #include <linux/once.h> 2357dacad5SJay Sternberg #include <linux/pci.h> 24d916b1beSKeith Busch #include <linux/suspend.h> 2557dacad5SJay Sternberg #include <linux/t10-pi.h> 2657dacad5SJay Sternberg #include <linux/types.h> 279cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2820d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 29a98e58e5SScott Bauer #include <linux/sed-opal.h> 300f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3157dacad5SJay Sternberg 32604c01d5Syupeng #include "trace.h" 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 35c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 368a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 40943e942eSJens Axboe /* 41943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 42943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 43943e942eSJens Axboe */ 44943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 45943e942eSJens Axboe #define NVME_MAX_SEGS 127 46943e942eSJens Axboe 4757dacad5SJay Sternberg static int use_threaded_interrupts; 482e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5169f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 60a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 61a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 62a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 63a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 64a7a7cbe3SChaitanya Kulkarni 6527453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6627453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 7061f3b896SChaitanya Kulkarni .get = param_get_uint, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 7361f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7527453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76b27c1e68Sweiping zhang 779c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 789c9e76d5SWeiping Zhang { 799c9e76d5SWeiping Zhang unsigned int n; 809c9e76d5SWeiping Zhang int ret; 819c9e76d5SWeiping Zhang 829c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 839c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 849c9e76d5SWeiping Zhang return -EINVAL; 859c9e76d5SWeiping Zhang return param_set_uint(val, kp); 869c9e76d5SWeiping Zhang } 879c9e76d5SWeiping Zhang 889c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 899c9e76d5SWeiping Zhang .set = io_queue_count_set, 909c9e76d5SWeiping Zhang .get = param_get_uint, 919c9e76d5SWeiping Zhang }; 929c9e76d5SWeiping Zhang 933f68baf7SKeith Busch static unsigned int write_queues; 949c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 953b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 963b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 973b6592f7SJens Axboe "will share a queue set."); 983b6592f7SJens Axboe 993f68baf7SKeith Busch static unsigned int poll_queues; 1009c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1014b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1024b04cc6aSJens Axboe 103df4f9bc4SDavid E. Box static bool noacpi; 104df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 105df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106df4f9bc4SDavid E. Box 1071c63dc66SChristoph Hellwig struct nvme_dev; 1081c63dc66SChristoph Hellwig struct nvme_queue; 10957dacad5SJay Sternberg 110a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1118fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11257dacad5SJay Sternberg 11357dacad5SJay Sternberg /* 1141c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1151c63dc66SChristoph Hellwig */ 1161c63dc66SChristoph Hellwig struct nvme_dev { 117147b27e4SSagi Grimberg struct nvme_queue *queues; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1201c63dc66SChristoph Hellwig u32 __iomem *dbs; 1211c63dc66SChristoph Hellwig struct device *dev; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1241c63dc66SChristoph Hellwig unsigned online_queues; 1251c63dc66SChristoph Hellwig unsigned max_qid; 126e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12722b55601SKeith Busch unsigned int num_vecs; 1287442ddceSJohn Garry u32 q_depth; 129c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1301c63dc66SChristoph Hellwig u32 db_stride; 1311c63dc66SChristoph Hellwig void __iomem *bar; 13297f6ef64SXu Yu unsigned long bar_mapped_size; 13377bf25eaSKeith Busch struct mutex shutdown_lock; 1341c63dc66SChristoph Hellwig bool subsystem; 1351c63dc66SChristoph Hellwig u64 cmb_size; 1360f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1371c63dc66SChristoph Hellwig u32 cmbsz; 138202021c1SStephen Bates u32 cmbloc; 1391c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 140d916b1beSKeith Busch u32 last_ps; 141a5df5e79SKeith Busch bool hmb; 14287ad72a5SChristoph Hellwig 143943e942eSJens Axboe mempool_t *iod_mempool; 144943e942eSJens Axboe 14587ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 146f9f38e33SHelen Koike u32 *dbbuf_dbs; 147f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 148f9f38e33SHelen Koike u32 *dbbuf_eis; 149f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15087ad72a5SChristoph Hellwig 15187ad72a5SChristoph Hellwig /* host memory buffer support: */ 15287ad72a5SChristoph Hellwig u64 host_mem_size; 15387ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1544033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15687ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1572a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1582a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 16057dacad5SJay Sternberg }; 16157dacad5SJay Sternberg 162b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 163b27c1e68Sweiping zhang { 16427453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16527453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 166b27c1e68Sweiping zhang } 167b27c1e68Sweiping zhang 168f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 169f9f38e33SHelen Koike { 170f9f38e33SHelen Koike return qid * 2 * stride; 171f9f38e33SHelen Koike } 172f9f38e33SHelen Koike 173f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 174f9f38e33SHelen Koike { 175f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 176f9f38e33SHelen Koike } 177f9f38e33SHelen Koike 1781c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1791c63dc66SChristoph Hellwig { 1801c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1811c63dc66SChristoph Hellwig } 1821c63dc66SChristoph Hellwig 18357dacad5SJay Sternberg /* 18457dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18557dacad5SJay Sternberg * commands and one for I/O commands). 18657dacad5SJay Sternberg */ 18757dacad5SJay Sternberg struct nvme_queue { 18857dacad5SJay Sternberg struct nvme_dev *dev; 1891ab0cd69SJens Axboe spinlock_t sq_lock; 190c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1913a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1923a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19374943d45SKeith Busch struct nvme_completion *cqes; 19457dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19557dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19657dacad5SJay Sternberg u32 __iomem *q_db; 1977442ddceSJohn Garry u32 q_depth; 1987c349ddeSKeith Busch u16 cq_vector; 19957dacad5SJay Sternberg u16 sq_tail; 20038210800SKeith Busch u16 last_sq_tail; 20157dacad5SJay Sternberg u16 cq_head; 20257dacad5SJay Sternberg u16 qid; 20357dacad5SJay Sternberg u8 cq_phase; 204c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2054e224106SChristoph Hellwig unsigned long flags; 2064e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20763223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 208d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2097c349ddeSKeith Busch #define NVMEQ_POLLED 3 210f9f38e33SHelen Koike u32 *dbbuf_sq_db; 211f9f38e33SHelen Koike u32 *dbbuf_cq_db; 212f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 213f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 214d1ed6aa1SChristoph Hellwig struct completion delete_done; 21557dacad5SJay Sternberg }; 21657dacad5SJay Sternberg 21757dacad5SJay Sternberg /* 2189b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2199b048119SChristoph Hellwig * 2209b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2219b048119SChristoph Hellwig * to the actual struct scatterlist. 22271bd150cSChristoph Hellwig */ 22371bd150cSChristoph Hellwig struct nvme_iod { 224d49187e9SChristoph Hellwig struct nvme_request req; 225af7fae85SKeith Busch struct nvme_command cmd; 226a7a7cbe3SChaitanya Kulkarni bool use_sgl; 22752da4f3fSKeith Busch bool aborted; 228c372cdd1SKeith Busch s8 nr_allocations; /* PRP list pool allocations. 0 means small 229c372cdd1SKeith Busch pool in use */ 230dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 231c4c22c52SKeith Busch dma_addr_t first_dma; 232783b94bdSChristoph Hellwig dma_addr_t meta_dma; 23391fb2b60SLogan Gunthorpe struct sg_table sgt; 23457dacad5SJay Sternberg }; 23557dacad5SJay Sternberg 2362a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2373b6592f7SJens Axboe { 2382a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 239f9f38e33SHelen Koike } 240f9f38e33SHelen Koike 24165a54646SChristoph Hellwig static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 242f9f38e33SHelen Koike { 2432a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 244f9f38e33SHelen Koike 24565a54646SChristoph Hellwig if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 24665a54646SChristoph Hellwig return; 24765a54646SChristoph Hellwig 24858847f12SKeith Busch if (dev->dbbuf_dbs) { 24958847f12SKeith Busch /* 25058847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25158847f12SKeith Busch * values from the previous instantiation. 25258847f12SKeith Busch */ 25358847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25458847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 25565a54646SChristoph Hellwig return; 25658847f12SKeith Busch } 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 259f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 260f9f38e33SHelen Koike GFP_KERNEL); 261f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 26265a54646SChristoph Hellwig goto fail; 263f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 264f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 265f9f38e33SHelen Koike GFP_KERNEL); 26665a54646SChristoph Hellwig if (!dev->dbbuf_eis) 26765a54646SChristoph Hellwig goto fail_free_dbbuf_dbs; 26865a54646SChristoph Hellwig return; 269f9f38e33SHelen Koike 27065a54646SChristoph Hellwig fail_free_dbbuf_dbs: 27165a54646SChristoph Hellwig dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 27265a54646SChristoph Hellwig dev->dbbuf_dbs_dma_addr); 27365a54646SChristoph Hellwig dev->dbbuf_dbs = NULL; 27465a54646SChristoph Hellwig fail: 27565a54646SChristoph Hellwig dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 276f9f38e33SHelen Koike } 277f9f38e33SHelen Koike 278f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 279f9f38e33SHelen Koike { 2802a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 281f9f38e33SHelen Koike 282f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 283f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 284f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 285f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike if (dev->dbbuf_eis) { 288f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 289f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 290f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 291f9f38e33SHelen Koike } 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 295f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 296f9f38e33SHelen Koike { 297f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 298f9f38e33SHelen Koike return; 299f9f38e33SHelen Koike 300f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 301f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 303f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 304f9f38e33SHelen Koike } 305f9f38e33SHelen Koike 3060f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3070f0d2c87SMinwoo Im { 3080f0d2c87SMinwoo Im if (!nvmeq->qid) 3090f0d2c87SMinwoo Im return; 3100f0d2c87SMinwoo Im 3110f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3120f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3130f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3140f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3150f0d2c87SMinwoo Im } 3160f0d2c87SMinwoo Im 317f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 318f9f38e33SHelen Koike { 319f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3200f0d2c87SMinwoo Im unsigned int i; 321f9f38e33SHelen Koike 322f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 323f9f38e33SHelen Koike return; 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 326f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 327f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 328f9f38e33SHelen Koike 329f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3309bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 331f9f38e33SHelen Koike /* Free memory and continue on */ 332f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3330f0d2c87SMinwoo Im 3340f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3350f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 336f9f38e33SHelen Koike } 337f9f38e33SHelen Koike } 338f9f38e33SHelen Koike 339f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 340f9f38e33SHelen Koike { 341f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 342f9f38e33SHelen Koike } 343f9f38e33SHelen Koike 344f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 345f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 346f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 347f9f38e33SHelen Koike { 348f9f38e33SHelen Koike if (dbbuf_db) { 349f9f38e33SHelen Koike u16 old_value; 350f9f38e33SHelen Koike 351f9f38e33SHelen Koike /* 352f9f38e33SHelen Koike * Ensure that the queue is written before updating 353f9f38e33SHelen Koike * the doorbell in memory 354f9f38e33SHelen Koike */ 355f9f38e33SHelen Koike wmb(); 356f9f38e33SHelen Koike 357f9f38e33SHelen Koike old_value = *dbbuf_db; 358f9f38e33SHelen Koike *dbbuf_db = value; 359f9f38e33SHelen Koike 360f1ed3df2SMichal Wnukowski /* 361f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 362f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 363f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 364f1ed3df2SMichal Wnukowski * the doorbell. 365f1ed3df2SMichal Wnukowski */ 366f1ed3df2SMichal Wnukowski mb(); 367f1ed3df2SMichal Wnukowski 368f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 369f9f38e33SHelen Koike return false; 370f9f38e33SHelen Koike } 371f9f38e33SHelen Koike 372f9f38e33SHelen Koike return true; 37357dacad5SJay Sternberg } 37457dacad5SJay Sternberg 37557dacad5SJay Sternberg /* 37657dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37757dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37857dacad5SJay Sternberg * the I/O. 37957dacad5SJay Sternberg */ 380b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 38157dacad5SJay Sternberg { 382b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3836c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38457dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38557dacad5SJay Sternberg } 38657dacad5SJay Sternberg 387a7a7cbe3SChaitanya Kulkarni /* 388a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 389a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 390a7a7cbe3SChaitanya Kulkarni */ 391b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 392f4800d6dSChristoph Hellwig { 393b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 394b13c6393SChaitanya Kulkarni PAGE_SIZE); 395f4800d6dSChristoph Hellwig } 396f4800d6dSChristoph Hellwig 39757dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39857dacad5SJay Sternberg unsigned int hctx_idx) 39957dacad5SJay Sternberg { 40057dacad5SJay Sternberg struct nvme_dev *dev = data; 401147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40257dacad5SJay Sternberg 40357dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40457dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40557dacad5SJay Sternberg 40657dacad5SJay Sternberg hctx->driver_data = nvmeq; 40757dacad5SJay Sternberg return 0; 40857dacad5SJay Sternberg } 40957dacad5SJay Sternberg 41057dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41157dacad5SJay Sternberg unsigned int hctx_idx) 41257dacad5SJay Sternberg { 41357dacad5SJay Sternberg struct nvme_dev *dev = data; 414147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41557dacad5SJay Sternberg 41657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41757dacad5SJay Sternberg hctx->driver_data = nvmeq; 41857dacad5SJay Sternberg return 0; 41957dacad5SJay Sternberg } 42057dacad5SJay Sternberg 421e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 422e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 423e559398fSChristoph Hellwig unsigned int numa_node) 42457dacad5SJay Sternberg { 425d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 426f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 42759e29ce6SSagi Grimberg 42859e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 429f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 43057dacad5SJay Sternberg return 0; 43157dacad5SJay Sternberg } 43257dacad5SJay Sternberg 4333b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4343b6592f7SJens Axboe { 4353b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4363b6592f7SJens Axboe if (dev->num_vecs > 1) 4373b6592f7SJens Axboe return 1; 4383b6592f7SJens Axboe 4393b6592f7SJens Axboe return 0; 4403b6592f7SJens Axboe } 4413b6592f7SJens Axboe 442a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 443dca51e78SChristoph Hellwig { 444dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4453b6592f7SJens Axboe int i, qoff, offset; 446dca51e78SChristoph Hellwig 4473b6592f7SJens Axboe offset = queue_irq_offset(dev); 4483b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4493b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4503b6592f7SJens Axboe 4513b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4523b6592f7SJens Axboe if (!map->nr_queues) { 453e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4547e849dd9SChristoph Hellwig continue; 4553b6592f7SJens Axboe } 4563b6592f7SJens Axboe 4574b04cc6aSJens Axboe /* 4584b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4594b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4604b04cc6aSJens Axboe */ 4613b6592f7SJens Axboe map->queue_offset = qoff; 462cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4633b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4644b04cc6aSJens Axboe else 4654b04cc6aSJens Axboe blk_mq_map_queues(map); 4663b6592f7SJens Axboe qoff += map->nr_queues; 4673b6592f7SJens Axboe offset += map->nr_queues; 4683b6592f7SJens Axboe } 469dca51e78SChristoph Hellwig } 470dca51e78SChristoph Hellwig 47138210800SKeith Busch /* 47238210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47338210800SKeith Busch */ 47438210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47504f3eafdSJens Axboe { 47638210800SKeith Busch if (!write_sq) { 47738210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47838210800SKeith Busch 47938210800SKeith Busch if (next_tail == nvmeq->q_depth) 48038210800SKeith Busch next_tail = 0; 48138210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48238210800SKeith Busch return; 48338210800SKeith Busch } 48438210800SKeith Busch 48504f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48604f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48704f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48838210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 48904f3eafdSJens Axboe } 49004f3eafdSJens Axboe 4913233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4923233b94cSJens Axboe struct nvme_command *cmd) 49357dacad5SJay Sternberg { 494c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 4953233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 49690ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49790ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49804f3eafdSJens Axboe } 49904f3eafdSJens Axboe 50004f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 50104f3eafdSJens Axboe { 50204f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50304f3eafdSJens Axboe 50404f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50538210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50638210800SKeith Busch nvme_write_sq_db(nvmeq, true); 50790ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50857dacad5SJay Sternberg } 50957dacad5SJay Sternberg 510a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 51157dacad5SJay Sternberg { 512f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 51391fb2b60SLogan Gunthorpe return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 51457dacad5SJay Sternberg } 51557dacad5SJay Sternberg 516955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 517955b1b5aSMinwoo Im { 518a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 51920469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 520955b1b5aSMinwoo Im unsigned int avg_seg_size; 521955b1b5aSMinwoo Im 52220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 523955b1b5aSMinwoo Im 524253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 525955b1b5aSMinwoo Im return false; 526a53232cbSKeith Busch if (!nvmeq->qid) 527955b1b5aSMinwoo Im return false; 528955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 529955b1b5aSMinwoo Im return false; 530955b1b5aSMinwoo Im return true; 531955b1b5aSMinwoo Im } 532955b1b5aSMinwoo Im 5339275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 53457dacad5SJay Sternberg { 5356c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5369275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5379275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 53857dacad5SJay Sternberg int i; 53957dacad5SJay Sternberg 540c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5419275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5429275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5439275c206SChristoph Hellwig 5449275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5459275c206SChristoph Hellwig dma_addr = next_dma_addr; 546dff824b2SChristoph Hellwig } 5479275c206SChristoph Hellwig } 5489275c206SChristoph Hellwig 5499275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5509275c206SChristoph Hellwig { 5519275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5529275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5539275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5549275c206SChristoph Hellwig int i; 5559275c206SChristoph Hellwig 556c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5579275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5589275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5599275c206SChristoph Hellwig 5609275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5619275c206SChristoph Hellwig dma_addr = next_dma_addr; 5629275c206SChristoph Hellwig } 5639275c206SChristoph Hellwig } 5649275c206SChristoph Hellwig 5659275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5669275c206SChristoph Hellwig { 5679275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5687fe07d14SChristoph Hellwig 5699275c206SChristoph Hellwig if (iod->dma_len) { 5709275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5719275c206SChristoph Hellwig rq_dma_dir(req)); 5729275c206SChristoph Hellwig return; 5739275c206SChristoph Hellwig } 5749275c206SChristoph Hellwig 57591fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5769275c206SChristoph Hellwig 57791fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 57891fb2b60SLogan Gunthorpe 579c372cdd1SKeith Busch if (iod->nr_allocations == 0) 580a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 5819275c206SChristoph Hellwig iod->first_dma); 5829275c206SChristoph Hellwig else if (iod->use_sgl) 5839275c206SChristoph Hellwig nvme_free_sgls(dev, req); 5849275c206SChristoph Hellwig else 5859275c206SChristoph Hellwig nvme_free_prps(dev, req); 58691fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 58757dacad5SJay Sternberg } 58857dacad5SJay Sternberg 589d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 590d0877473SKeith Busch { 591d0877473SKeith Busch int i; 592d0877473SKeith Busch struct scatterlist *sg; 593d0877473SKeith Busch 594d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 595d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 596d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 597d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 598d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 599d0877473SKeith Busch sg_dma_len(sg)); 600d0877473SKeith Busch } 601d0877473SKeith Busch } 602d0877473SKeith Busch 603a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 604a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 60557dacad5SJay Sternberg { 606f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 60757dacad5SJay Sternberg struct dma_pool *pool; 608b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 60991fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 61057dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 61157dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6126c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 61357dacad5SJay Sternberg __le64 *prp_list; 614a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 61557dacad5SJay Sternberg dma_addr_t prp_dma; 61657dacad5SJay Sternberg int nprps, i; 61757dacad5SJay Sternberg 6186c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6195228b328SJan H. Schönherr if (length <= 0) { 6205228b328SJan H. Schönherr iod->first_dma = 0; 621a7a7cbe3SChaitanya Kulkarni goto done; 6225228b328SJan H. Schönherr } 62357dacad5SJay Sternberg 6246c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 62557dacad5SJay Sternberg if (dma_len) { 6266c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 62757dacad5SJay Sternberg } else { 62857dacad5SJay Sternberg sg = sg_next(sg); 62957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63157dacad5SJay Sternberg } 63257dacad5SJay Sternberg 6336c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 63457dacad5SJay Sternberg iod->first_dma = dma_addr; 635a7a7cbe3SChaitanya Kulkarni goto done; 63657dacad5SJay Sternberg } 63757dacad5SJay Sternberg 6386c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 63957dacad5SJay Sternberg if (nprps <= (256 / 8)) { 64057dacad5SJay Sternberg pool = dev->prp_small_pool; 641c372cdd1SKeith Busch iod->nr_allocations = 0; 64257dacad5SJay Sternberg } else { 64357dacad5SJay Sternberg pool = dev->prp_page_pool; 644c372cdd1SKeith Busch iod->nr_allocations = 1; 64557dacad5SJay Sternberg } 64657dacad5SJay Sternberg 64769d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64857dacad5SJay Sternberg if (!prp_list) { 649c372cdd1SKeith Busch iod->nr_allocations = -1; 65086eea289SKeith Busch return BLK_STS_RESOURCE; 65157dacad5SJay Sternberg } 65257dacad5SJay Sternberg list[0] = prp_list; 65357dacad5SJay Sternberg iod->first_dma = prp_dma; 65457dacad5SJay Sternberg i = 0; 65557dacad5SJay Sternberg for (;;) { 6566c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 65757dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65957dacad5SJay Sternberg if (!prp_list) 660fa073216SChristoph Hellwig goto free_prps; 661c372cdd1SKeith Busch list[iod->nr_allocations++] = prp_list; 66257dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 66357dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 66457dacad5SJay Sternberg i = 1; 66557dacad5SJay Sternberg } 66657dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6676c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6686c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6696c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 67057dacad5SJay Sternberg if (length <= 0) 67157dacad5SJay Sternberg break; 67257dacad5SJay Sternberg if (dma_len > 0) 67357dacad5SJay Sternberg continue; 67486eea289SKeith Busch if (unlikely(dma_len < 0)) 67586eea289SKeith Busch goto bad_sgl; 67657dacad5SJay Sternberg sg = sg_next(sg); 67757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 67957dacad5SJay Sternberg } 680a7a7cbe3SChaitanya Kulkarni done: 68191fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 682a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 68386eea289SKeith Busch return BLK_STS_OK; 684fa073216SChristoph Hellwig free_prps: 685fa073216SChristoph Hellwig nvme_free_prps(dev, req); 686fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 68786eea289SKeith Busch bad_sgl: 68891fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 689d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 69091fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 69186eea289SKeith Busch return BLK_STS_IOERR; 69257dacad5SJay Sternberg } 69357dacad5SJay Sternberg 694a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 695a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 696a7a7cbe3SChaitanya Kulkarni { 697a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 698a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 699a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 700a7a7cbe3SChaitanya Kulkarni } 701a7a7cbe3SChaitanya Kulkarni 702a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 703a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 704a7a7cbe3SChaitanya Kulkarni { 705a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 706a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 707a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 708a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 709a7a7cbe3SChaitanya Kulkarni } else { 710a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 711a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 712a7a7cbe3SChaitanya Kulkarni } 713a7a7cbe3SChaitanya Kulkarni } 714a7a7cbe3SChaitanya Kulkarni 715a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 71691fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 717a7a7cbe3SChaitanya Kulkarni { 718a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 719a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 720a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 72191fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 72291fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 723a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 724b0f2853bSChristoph Hellwig int i = 0; 725a7a7cbe3SChaitanya Kulkarni 726a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 727a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 728a7a7cbe3SChaitanya Kulkarni 729b0f2853bSChristoph Hellwig if (entries == 1) { 730a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 731a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 732a7a7cbe3SChaitanya Kulkarni } 733a7a7cbe3SChaitanya Kulkarni 734a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 735a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 736c372cdd1SKeith Busch iod->nr_allocations = 0; 737a7a7cbe3SChaitanya Kulkarni } else { 738a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 739c372cdd1SKeith Busch iod->nr_allocations = 1; 740a7a7cbe3SChaitanya Kulkarni } 741a7a7cbe3SChaitanya Kulkarni 742a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 743a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 744c372cdd1SKeith Busch iod->nr_allocations = -1; 745a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 746a7a7cbe3SChaitanya Kulkarni } 747a7a7cbe3SChaitanya Kulkarni 748a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 749a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 750a7a7cbe3SChaitanya Kulkarni 751a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 752a7a7cbe3SChaitanya Kulkarni 753a7a7cbe3SChaitanya Kulkarni do { 754a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 755a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 756a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 757a7a7cbe3SChaitanya Kulkarni 758a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 759a7a7cbe3SChaitanya Kulkarni if (!sg_list) 760fa073216SChristoph Hellwig goto free_sgls; 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni i = 0; 763c372cdd1SKeith Busch nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; 764a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 765a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 766a7a7cbe3SChaitanya Kulkarni } 767a7a7cbe3SChaitanya Kulkarni 768a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 769a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 770b0f2853bSChristoph Hellwig } while (--entries > 0); 771a7a7cbe3SChaitanya Kulkarni 772a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 773fa073216SChristoph Hellwig free_sgls: 774fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 775fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 776a7a7cbe3SChaitanya Kulkarni } 777a7a7cbe3SChaitanya Kulkarni 778dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 779dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 780dff824b2SChristoph Hellwig struct bio_vec *bv) 781dff824b2SChristoph Hellwig { 782dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7836c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7846c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 785dff824b2SChristoph Hellwig 786dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 787dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 788dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 789dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 790dff824b2SChristoph Hellwig 791dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 792dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 793dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 794359c1f88SBaolin Wang return BLK_STS_OK; 795dff824b2SChristoph Hellwig } 796dff824b2SChristoph Hellwig 79729791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 79829791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 79929791057SChristoph Hellwig struct bio_vec *bv) 80029791057SChristoph Hellwig { 80129791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80229791057SChristoph Hellwig 80329791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 80429791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 80529791057SChristoph Hellwig return BLK_STS_RESOURCE; 80629791057SChristoph Hellwig iod->dma_len = bv->bv_len; 80729791057SChristoph Hellwig 808049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 80929791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 81029791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 81129791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 812359c1f88SBaolin Wang return BLK_STS_OK; 81329791057SChristoph Hellwig } 81429791057SChristoph Hellwig 815fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 816b131c61dSChristoph Hellwig struct nvme_command *cmnd) 81757dacad5SJay Sternberg { 818f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 81970479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 82091fb2b60SLogan Gunthorpe int rc; 82157dacad5SJay Sternberg 822dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 823a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 824dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 825dff824b2SChristoph Hellwig 826dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8276c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 828dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 829dff824b2SChristoph Hellwig &cmnd->rw, &bv); 83029791057SChristoph Hellwig 831a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 832253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 83329791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 83429791057SChristoph Hellwig &cmnd->rw, &bv); 835dff824b2SChristoph Hellwig } 836dff824b2SChristoph Hellwig } 837dff824b2SChristoph Hellwig 838dff824b2SChristoph Hellwig iod->dma_len = 0; 83991fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 84091fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 8419b048119SChristoph Hellwig return BLK_STS_RESOURCE; 84291fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 84391fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 84491fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 845fa073216SChristoph Hellwig goto out_free_sg; 846ba1ca37eSChristoph Hellwig 84791fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 84891fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 84991fb2b60SLogan Gunthorpe if (rc) { 85091fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 85191fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 852fa073216SChristoph Hellwig goto out_free_sg; 85391fb2b60SLogan Gunthorpe } 854ba1ca37eSChristoph Hellwig 85570479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 856955b1b5aSMinwoo Im if (iod->use_sgl) 85791fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 858a7a7cbe3SChaitanya Kulkarni else 859a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8604aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 861fa073216SChristoph Hellwig goto out_unmap_sg; 862fa073216SChristoph Hellwig return BLK_STS_OK; 863fa073216SChristoph Hellwig 864fa073216SChristoph Hellwig out_unmap_sg: 86591fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 866fa073216SChristoph Hellwig out_free_sg: 86791fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 868ba1ca37eSChristoph Hellwig return ret; 86957dacad5SJay Sternberg } 87057dacad5SJay Sternberg 8714aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8724aedb705SChristoph Hellwig struct nvme_command *cmnd) 8734aedb705SChristoph Hellwig { 8744aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8754aedb705SChristoph Hellwig 8764aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8774aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8784aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8794aedb705SChristoph Hellwig return BLK_STS_IOERR; 8804aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 881359c1f88SBaolin Wang return BLK_STS_OK; 8824aedb705SChristoph Hellwig } 8834aedb705SChristoph Hellwig 88462451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 88562451a2bSJens Axboe { 88662451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 88762451a2bSJens Axboe blk_status_t ret; 88862451a2bSJens Axboe 88952da4f3fSKeith Busch iod->aborted = false; 890c372cdd1SKeith Busch iod->nr_allocations = -1; 89191fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 89262451a2bSJens Axboe 89362451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 89462451a2bSJens Axboe if (ret) 89562451a2bSJens Axboe return ret; 89662451a2bSJens Axboe 89762451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 89862451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 89962451a2bSJens Axboe if (ret) 90062451a2bSJens Axboe goto out_free_cmd; 90162451a2bSJens Axboe } 90262451a2bSJens Axboe 90362451a2bSJens Axboe if (blk_integrity_rq(req)) { 90462451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 90562451a2bSJens Axboe if (ret) 90662451a2bSJens Axboe goto out_unmap_data; 90762451a2bSJens Axboe } 90862451a2bSJens Axboe 90962451a2bSJens Axboe blk_mq_start_request(req); 91062451a2bSJens Axboe return BLK_STS_OK; 91162451a2bSJens Axboe out_unmap_data: 91262451a2bSJens Axboe nvme_unmap_data(dev, req); 91362451a2bSJens Axboe out_free_cmd: 91462451a2bSJens Axboe nvme_cleanup_cmd(req); 91562451a2bSJens Axboe return ret; 91662451a2bSJens Axboe } 91762451a2bSJens Axboe 91857dacad5SJay Sternberg /* 91957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 92057dacad5SJay Sternberg */ 921fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 92257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 92357dacad5SJay Sternberg { 92457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92657dacad5SJay Sternberg struct request *req = bd->rq; 9279b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 928ebe6d874SChristoph Hellwig blk_status_t ret; 92957dacad5SJay Sternberg 930d1f06f4aSJens Axboe /* 931d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 932d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 933d1f06f4aSJens Axboe */ 9344e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 935d1f06f4aSJens Axboe return BLK_STS_IOERR; 936d1f06f4aSJens Axboe 93762451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 938d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 939d4060d2bSTao Chiu 94062451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 94162451a2bSJens Axboe if (unlikely(ret)) 942f4800d6dSChristoph Hellwig return ret; 9433233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9443233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9453233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9463233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 947fc17b653SChristoph Hellwig return BLK_STS_OK; 94857dacad5SJay Sternberg } 94957dacad5SJay Sternberg 950d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 951d62cbcf6SJens Axboe { 952d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 953d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 954d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 955d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 956d62cbcf6SJens Axboe 957d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 958d62cbcf6SJens Axboe } 959d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 960d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 961d62cbcf6SJens Axboe } 962d62cbcf6SJens Axboe 963d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 964d62cbcf6SJens Axboe { 965d62cbcf6SJens Axboe /* 966d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 967d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 968d62cbcf6SJens Axboe */ 969d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 970d62cbcf6SJens Axboe return false; 971d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 972d62cbcf6SJens Axboe return false; 973d62cbcf6SJens Axboe 974d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 975d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 976d62cbcf6SJens Axboe } 977d62cbcf6SJens Axboe 978d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 979d62cbcf6SJens Axboe { 9806bfec799SKeith Busch struct request *req, *next, *prev = NULL; 981d62cbcf6SJens Axboe struct request *requeue_list = NULL; 982d62cbcf6SJens Axboe 9836bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 984d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 985d62cbcf6SJens Axboe 986d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 987d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9886bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9896bfec799SKeith Busch 9906bfec799SKeith Busch req = prev; 9916bfec799SKeith Busch if (!req) 9926bfec799SKeith Busch continue; 993d62cbcf6SJens Axboe } 994d62cbcf6SJens Axboe 9956bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 996d62cbcf6SJens Axboe /* detach rest of list, and submit */ 9976bfec799SKeith Busch req->rq_next = NULL; 998d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 9996bfec799SKeith Busch *rqlist = next; 10006bfec799SKeith Busch prev = NULL; 10016bfec799SKeith Busch } else 10026bfec799SKeith Busch prev = req; 1003d62cbcf6SJens Axboe } 1004d62cbcf6SJens Axboe 1005d62cbcf6SJens Axboe *rqlist = requeue_list; 1006d62cbcf6SJens Axboe } 1007d62cbcf6SJens Axboe 1008c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1009eee417b0SChristoph Hellwig { 1010a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1011a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 1012eee417b0SChristoph Hellwig 1013a53232cbSKeith Busch if (blk_integrity_rq(req)) { 1014a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1015a53232cbSKeith Busch 10164aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10174aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1018a53232cbSKeith Busch } 1019a53232cbSKeith Busch 1020b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10214aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1022c234a653SJens Axboe } 1023c234a653SJens Axboe 1024c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1025c234a653SJens Axboe { 1026c234a653SJens Axboe nvme_pci_unmap_rq(req); 102777f02a7aSChristoph Hellwig nvme_complete_rq(req); 102857dacad5SJay Sternberg } 102957dacad5SJay Sternberg 1030c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1031c234a653SJens Axboe { 1032c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1033c234a653SJens Axboe } 1034c234a653SJens Axboe 1035d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1036750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1037d783e0bdSMarta Rybczynska { 103874943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 103974943d45SKeith Busch 104074943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1041d783e0bdSMarta Rybczynska } 1042d783e0bdSMarta Rybczynska 1043eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 104457dacad5SJay Sternberg { 1045eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 104657dacad5SJay Sternberg 1047eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1048eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1049eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1050eb281c82SSagi Grimberg } 1051adf68f21SChristoph Hellwig 1052cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1053cfa27356SChristoph Hellwig { 1054cfa27356SChristoph Hellwig if (!nvmeq->qid) 1055cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1056cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1057cfa27356SChristoph Hellwig } 1058cfa27356SChristoph Hellwig 1059c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1060c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 106157dacad5SJay Sternberg { 106274943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 106362df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 106457dacad5SJay Sternberg struct request *req; 1065adf68f21SChristoph Hellwig 1066adf68f21SChristoph Hellwig /* 1067adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1068adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1069adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1070adf68f21SChristoph Hellwig * for them but rather special case them here. 1071adf68f21SChristoph Hellwig */ 107262df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10737bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 107483a12fb7SSagi Grimberg cqe->status, &cqe->result); 1075a0fa9647SJens Axboe return; 107657dacad5SJay Sternberg } 107757dacad5SJay Sternberg 1078e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 107950b7c243SXianting Tian if (unlikely(!req)) { 108050b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 108150b7c243SXianting Tian "invalid id %d completed on queue %d\n", 108262df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 108350b7c243SXianting Tian return; 108450b7c243SXianting Tian } 108550b7c243SXianting Tian 1086604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1087c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1088c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1089c234a653SJens Axboe nvme_pci_complete_batch)) 1090ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 109183a12fb7SSagi Grimberg } 109257dacad5SJay Sternberg 10935cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10945cb525c8SJens Axboe { 1095a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1096a8de6639SAlexey Dobriyan 1097a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1098920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1099e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1100a8de6639SAlexey Dobriyan } else { 1101a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1102920d13a8SSagi Grimberg } 1103a0fa9647SJens Axboe } 1104a0fa9647SJens Axboe 1105c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1106c234a653SJens Axboe struct io_comp_batch *iob) 1107a0fa9647SJens Axboe { 11081052b8acSJens Axboe int found = 0; 110983a12fb7SSagi Grimberg 11101052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11111052b8acSJens Axboe found++; 1112b69e2ef2SKeith Busch /* 1113b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1114b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1115b69e2ef2SKeith Busch */ 1116b69e2ef2SKeith Busch dma_rmb(); 1117c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11185cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 111957dacad5SJay Sternberg } 112057dacad5SJay Sternberg 1121324b494cSKeith Busch if (found) 1122eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11235cb525c8SJens Axboe return found; 112457dacad5SJay Sternberg } 112557dacad5SJay Sternberg 112657dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 112757dacad5SJay Sternberg { 112857dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11294f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11305cb525c8SJens Axboe 11314f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11324f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11334f502245SJens Axboe nvme_pci_complete_batch(&iob); 113405fae499SChaitanya Kulkarni return IRQ_HANDLED; 11354f502245SJens Axboe } 113605fae499SChaitanya Kulkarni return IRQ_NONE; 113757dacad5SJay Sternberg } 113857dacad5SJay Sternberg 113957dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 114057dacad5SJay Sternberg { 114157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11424e523547SBaolin Wang 1143750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 114457dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1145d783e0bdSMarta Rybczynska return IRQ_NONE; 114657dacad5SJay Sternberg } 114757dacad5SJay Sternberg 11480b2a8a9fSChristoph Hellwig /* 1149fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11500b2a8a9fSChristoph Hellwig * Can be called from any context. 11510b2a8a9fSChristoph Hellwig */ 1152fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1153a0fa9647SJens Axboe { 11543a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1155a0fa9647SJens Axboe 1156fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1157fa059b85SKeith Busch 11583a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1159c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11603a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 116191a509f8SChristoph Hellwig } 1162442e19b7SSagi Grimberg 11635a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11647776db1cSKeith Busch { 11657776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1166dabcefabSJens Axboe bool found; 1167dabcefabSJens Axboe 1168dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1169dabcefabSJens Axboe return 0; 1170dabcefabSJens Axboe 11713a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1172c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11733a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1174dabcefabSJens Axboe 1175dabcefabSJens Axboe return found; 1176dabcefabSJens Axboe } 1177dabcefabSJens Axboe 1178ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 117957dacad5SJay Sternberg { 1180f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1181147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1182f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118357dacad5SJay Sternberg 118457dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1185ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11863233b94cSJens Axboe 11873233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11883233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11893233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11903233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 119157dacad5SJay Sternberg } 119257dacad5SJay Sternberg 119357dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 119457dacad5SJay Sternberg { 1195f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 119657dacad5SJay Sternberg 119757dacad5SJay Sternberg c.delete_queue.opcode = opcode; 119857dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 119957dacad5SJay Sternberg 12001c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120157dacad5SJay Sternberg } 120257dacad5SJay Sternberg 120357dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1204a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 120557dacad5SJay Sternberg { 1206f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12074b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12084b04cc6aSJens Axboe 12097c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12104b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 121157dacad5SJay Sternberg 121257dacad5SJay Sternberg /* 121316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 121457dacad5SJay Sternberg * is attached to the request. 121557dacad5SJay Sternberg */ 121657dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 121757dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 121857dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 121957dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 122057dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1221a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 122257dacad5SJay Sternberg 12231c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122457dacad5SJay Sternberg } 122557dacad5SJay Sternberg 122657dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 122757dacad5SJay Sternberg struct nvme_queue *nvmeq) 122857dacad5SJay Sternberg { 12299abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1230f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 123181c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 123257dacad5SJay Sternberg 123357dacad5SJay Sternberg /* 12349abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12359abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12369abd68efSJens Axboe * URGENT. 12379abd68efSJens Axboe */ 12389abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12399abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12409abd68efSJens Axboe 12419abd68efSJens Axboe /* 124216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 124357dacad5SJay Sternberg * is attached to the request. 124457dacad5SJay Sternberg */ 124557dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 124657dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 124757dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 124857dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 124957dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 125057dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 125157dacad5SJay Sternberg 12521c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 125357dacad5SJay Sternberg } 125457dacad5SJay Sternberg 125557dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 125657dacad5SJay Sternberg { 125757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 125857dacad5SJay Sternberg } 125957dacad5SJay Sternberg 126057dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 126157dacad5SJay Sternberg { 126257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 126357dacad5SJay Sternberg } 126457dacad5SJay Sternberg 1265de671d61SJens Axboe static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 126657dacad5SJay Sternberg { 1267a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 126857dacad5SJay Sternberg 126927fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 127027fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1271e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1272e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 1273de671d61SJens Axboe return RQ_END_IO_NONE; 127457dacad5SJay Sternberg } 127557dacad5SJay Sternberg 1276b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1277b2a0eb1aSKeith Busch { 1278b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1279b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1280b2a0eb1aSKeith Busch */ 1281b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1282b2a0eb1aSKeith Busch 1283ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1284ad70062cSJianchao Wang switch (dev->ctrl.state) { 1285ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1286ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1287b2a0eb1aSKeith Busch return false; 1288ad70062cSJianchao Wang default: 1289ad70062cSJianchao Wang break; 1290ad70062cSJianchao Wang } 1291b2a0eb1aSKeith Busch 1292b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1293b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1294b2a0eb1aSKeith Busch */ 1295b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1296b2a0eb1aSKeith Busch return false; 1297b2a0eb1aSKeith Busch 1298b2a0eb1aSKeith Busch return true; 1299b2a0eb1aSKeith Busch } 1300b2a0eb1aSKeith Busch 1301b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1302b2a0eb1aSKeith Busch { 1303b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1304b2a0eb1aSKeith Busch u16 pci_status; 1305b2a0eb1aSKeith Busch int result; 1306b2a0eb1aSKeith Busch 1307b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1308b2a0eb1aSKeith Busch &pci_status); 1309b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1310b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1311b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1312b2a0eb1aSKeith Busch csts, pci_status); 1313b2a0eb1aSKeith Busch else 1314b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1315b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1316b2a0eb1aSKeith Busch csts, result); 13174641a8e6SKeith Busch 13184641a8e6SKeith Busch if (csts != ~0) 13194641a8e6SKeith Busch return; 13204641a8e6SKeith Busch 13214641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13224641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 13234641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13244641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1325b2a0eb1aSKeith Busch } 1326b2a0eb1aSKeith Busch 13279bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 132857dacad5SJay Sternberg { 1329f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1330a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 133157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 133257dacad5SJay Sternberg struct request *abort_req; 1333f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1334b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1335b2a0eb1aSKeith Busch 1336651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1337651438bbSWen Xiong * the recovery mechanism will surely fail. 1338651438bbSWen Xiong */ 1339651438bbSWen Xiong mb(); 1340651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1341651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1342651438bbSWen Xiong 1343b2a0eb1aSKeith Busch /* 1344b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1345b2a0eb1aSKeith Busch */ 1346b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1347b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1348b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1349d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1350db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1351b2a0eb1aSKeith Busch } 135257dacad5SJay Sternberg 135331c7c7d2SChristoph Hellwig /* 13547776db1cSKeith Busch * Did we miss an interrupt? 13557776db1cSKeith Busch */ 1356fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13575a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1358fa059b85SKeith Busch else 1359bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1360fa059b85SKeith Busch 1361bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13627776db1cSKeith Busch dev_warn(dev->ctrl.device, 13637776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13647776db1cSKeith Busch req->tag, nvmeq->qid); 1365db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13667776db1cSKeith Busch } 13677776db1cSKeith Busch 13687776db1cSKeith Busch /* 1369fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1370fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1371fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1372db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1373fd634f41SChristoph Hellwig */ 13744244140dSKeith Busch switch (dev->ctrl.state) { 13754244140dSKeith Busch case NVME_CTRL_CONNECTING: 13762036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1377df561f66SGustavo A. R. Silva fallthrough; 13782036f726SKeith Busch case NVME_CTRL_DELETING: 1379b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1380fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1381fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 138227fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13837ad92f65STong Zhang nvme_dev_disable(dev, true); 1384db8c48e4SChristoph Hellwig return BLK_EH_DONE; 138539a9dd81SKeith Busch case NVME_CTRL_RESETTING: 138639a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13874244140dSKeith Busch default: 13884244140dSKeith Busch break; 1389fd634f41SChristoph Hellwig } 1390fd634f41SChristoph Hellwig 1391fd634f41SChristoph Hellwig /* 1392e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1393e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1394e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 139531c7c7d2SChristoph Hellwig */ 1396f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13971b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 139857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 139957dacad5SJay Sternberg req->tag, nvmeq->qid); 14007ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1401a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1402d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1403e1569a16SKeith Busch 1404db8c48e4SChristoph Hellwig return BLK_EH_DONE; 140557dacad5SJay Sternberg } 140657dacad5SJay Sternberg 1407e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1408e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1409e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1410e7a2a87dSChristoph Hellwig } 141152da4f3fSKeith Busch iod->aborted = true; 141257dacad5SJay Sternberg 141357dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 141485f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 141557dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 141657dacad5SJay Sternberg 14171b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 141886141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 141986141440SChristoph Hellwig req->tag, 142086141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 142186141440SChristoph Hellwig nvmeq->qid); 1422e7a2a87dSChristoph Hellwig 1423e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 142439dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14256bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14266bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 142731c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 142857dacad5SJay Sternberg } 1429e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 143057dacad5SJay Sternberg 1431e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1432e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1433128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1434e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 143557dacad5SJay Sternberg 143657dacad5SJay Sternberg /* 143757dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 143857dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 143957dacad5SJay Sternberg * as the device then is in a faulty state. 144057dacad5SJay Sternberg */ 144157dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 144257dacad5SJay Sternberg } 144357dacad5SJay Sternberg 144457dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 144557dacad5SJay Sternberg { 14468a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 144757dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 144863223078SChristoph Hellwig if (!nvmeq->sq_cmds) 144963223078SChristoph Hellwig return; 14500f238ff5SLogan Gunthorpe 145163223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 145288a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14538a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 145463223078SChristoph Hellwig } else { 14558a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 145663223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14570f238ff5SLogan Gunthorpe } 145857dacad5SJay Sternberg } 145957dacad5SJay Sternberg 146057dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 146157dacad5SJay Sternberg { 146257dacad5SJay Sternberg int i; 146357dacad5SJay Sternberg 1464d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1465d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1466147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 146757dacad5SJay Sternberg } 146857dacad5SJay Sternberg } 146957dacad5SJay Sternberg 147057dacad5SJay Sternberg /** 147157dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 147240581d1aSBart Van Assche * @nvmeq: queue to suspend 147357dacad5SJay Sternberg */ 147457dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 147557dacad5SJay Sternberg { 14764e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 147757dacad5SJay Sternberg return 1; 147857dacad5SJay Sternberg 14794e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1480d1f06f4aSJens Axboe mb(); 148157dacad5SJay Sternberg 14824e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14831c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1484*9f27bd70SChristoph Hellwig nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 14857c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14864e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 148757dacad5SJay Sternberg return 0; 148857dacad5SJay Sternberg } 148957dacad5SJay Sternberg 14908fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14918fae268bSKeith Busch { 14928fae268bSKeith Busch int i; 14938fae268bSKeith Busch 14948fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14958fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14968fae268bSKeith Busch } 14978fae268bSKeith Busch 1498a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 149957dacad5SJay Sternberg { 1500147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 150157dacad5SJay Sternberg 1502a5cdb68cSKeith Busch if (shutdown) 1503a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1504a5cdb68cSKeith Busch else 1505b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 150657dacad5SJay Sternberg 1507bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 150857dacad5SJay Sternberg } 150957dacad5SJay Sternberg 1510fa46c6fbSKeith Busch /* 1511fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15129210c075SDongli Zhang * that can check this device's completion queues have synced, except 15139210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15149210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1515fa46c6fbSKeith Busch */ 1516fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1517fa46c6fbSKeith Busch { 1518fa46c6fbSKeith Busch int i; 1519fa46c6fbSKeith Busch 15209210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15219210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1522c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15239210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15249210c075SDongli Zhang } 1525fa46c6fbSKeith Busch } 1526fa46c6fbSKeith Busch 152757dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 152857dacad5SJay Sternberg int entry_size) 152957dacad5SJay Sternberg { 153057dacad5SJay Sternberg int q_depth = dev->q_depth; 15315fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15326c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 153357dacad5SJay Sternberg 153457dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 153557dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15364e523547SBaolin Wang 15376c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 153857dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 153957dacad5SJay Sternberg 154057dacad5SJay Sternberg /* 154157dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 154257dacad5SJay Sternberg * would be better to map queues in system memory with the 154357dacad5SJay Sternberg * original depth 154457dacad5SJay Sternberg */ 154557dacad5SJay Sternberg if (q_depth < 64) 154657dacad5SJay Sternberg return -ENOMEM; 154757dacad5SJay Sternberg } 154857dacad5SJay Sternberg 154957dacad5SJay Sternberg return q_depth; 155057dacad5SJay Sternberg } 155157dacad5SJay Sternberg 155257dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15538a1d09a6SBenjamin Herrenschmidt int qid) 155457dacad5SJay Sternberg { 15550f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1556815c6704SKeith Busch 15570f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15588a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1559bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15600f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15610f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 156263223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 156363223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 156463223078SChristoph Hellwig return 0; 156563223078SChristoph Hellwig } 1566bfac8e9fSAlan Mikhak 15678a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1568bfac8e9fSAlan Mikhak } 15690f238ff5SLogan Gunthorpe } 15700f238ff5SLogan Gunthorpe 15718a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 157257dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 157357dacad5SJay Sternberg if (!nvmeq->sq_cmds) 157457dacad5SJay Sternberg return -ENOMEM; 157557dacad5SJay Sternberg return 0; 157657dacad5SJay Sternberg } 157757dacad5SJay Sternberg 1578a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 157957dacad5SJay Sternberg { 1580147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 158157dacad5SJay Sternberg 158262314e40SKeith Busch if (dev->ctrl.queue_count > qid) 158362314e40SKeith Busch return 0; 158457dacad5SJay Sternberg 1585c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15868a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15878a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 158857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 158957dacad5SJay Sternberg if (!nvmeq->cqes) 159057dacad5SJay Sternberg goto free_nvmeq; 159157dacad5SJay Sternberg 15928a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 159357dacad5SJay Sternberg goto free_cqdma; 159457dacad5SJay Sternberg 159557dacad5SJay Sternberg nvmeq->dev = dev; 15961ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15973a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 159857dacad5SJay Sternberg nvmeq->cq_head = 0; 159957dacad5SJay Sternberg nvmeq->cq_phase = 1; 160057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 160157dacad5SJay Sternberg nvmeq->qid = qid; 1602d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 160357dacad5SJay Sternberg 1604147b27e4SSagi Grimberg return 0; 160557dacad5SJay Sternberg 160657dacad5SJay Sternberg free_cqdma: 16078a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 160857dacad5SJay Sternberg nvmeq->cq_dma_addr); 160957dacad5SJay Sternberg free_nvmeq: 1610147b27e4SSagi Grimberg return -ENOMEM; 161157dacad5SJay Sternberg } 161257dacad5SJay Sternberg 1613dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 161457dacad5SJay Sternberg { 16150ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16160ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16170ff199cbSChristoph Hellwig 16180ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16190ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16200ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16210ff199cbSChristoph Hellwig } else { 16220ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16230ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16240ff199cbSChristoph Hellwig } 162557dacad5SJay Sternberg } 162657dacad5SJay Sternberg 162757dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 162857dacad5SJay Sternberg { 162957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 163057dacad5SJay Sternberg 163157dacad5SJay Sternberg nvmeq->sq_tail = 0; 163238210800SKeith Busch nvmeq->last_sq_tail = 0; 163357dacad5SJay Sternberg nvmeq->cq_head = 0; 163457dacad5SJay Sternberg nvmeq->cq_phase = 1; 163557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16368a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1637f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 163857dacad5SJay Sternberg dev->online_queues++; 16393a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 164057dacad5SJay Sternberg } 164157dacad5SJay Sternberg 1642e4b9852aSCasey Chen /* 1643e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1644e4b9852aSCasey Chen */ 1645e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1646e4b9852aSCasey Chen { 1647e4b9852aSCasey Chen /* 1648e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1649e4b9852aSCasey Chen */ 1650e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1651e4b9852aSCasey Chen return -ENODEV; 1652e4b9852aSCasey Chen 1653e4b9852aSCasey Chen /* 1654e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1655e4b9852aSCasey Chen */ 1656e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1657e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1658e4b9852aSCasey Chen return -ENODEV; 1659e4b9852aSCasey Chen } 1660e4b9852aSCasey Chen 1661e4b9852aSCasey Chen return 0; 1662e4b9852aSCasey Chen } 1663e4b9852aSCasey Chen 16644b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 166557dacad5SJay Sternberg { 166657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 166757dacad5SJay Sternberg int result; 16687c349ddeSKeith Busch u16 vector = 0; 166957dacad5SJay Sternberg 1670d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1671d1ed6aa1SChristoph Hellwig 167222b55601SKeith Busch /* 167322b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 167422b55601SKeith Busch * has only one vector available. 167522b55601SKeith Busch */ 16764b04cc6aSJens Axboe if (!polled) 1677a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16784b04cc6aSJens Axboe else 16797c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16804b04cc6aSJens Axboe 1681a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1682ded45505SKeith Busch if (result) 1683ded45505SKeith Busch return result; 168457dacad5SJay Sternberg 168557dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 168657dacad5SJay Sternberg if (result < 0) 1687ded45505SKeith Busch return result; 1688c80b36cdSEdmund Nadolski if (result) 168957dacad5SJay Sternberg goto release_cq; 169057dacad5SJay Sternberg 1691a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16924b04cc6aSJens Axboe 1693e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1694e4b9852aSCasey Chen if (result) 1695e4b9852aSCasey Chen return result; 1696e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16977c349ddeSKeith Busch if (!polled) { 1698dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 169957dacad5SJay Sternberg if (result < 0) 170057dacad5SJay Sternberg goto release_sq; 17014b04cc6aSJens Axboe } 170257dacad5SJay Sternberg 17034e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1704e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 170557dacad5SJay Sternberg return result; 170657dacad5SJay Sternberg 170757dacad5SJay Sternberg release_sq: 1708f25a2dfcSJianchao Wang dev->online_queues--; 1709e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171057dacad5SJay Sternberg adapter_delete_sq(dev, qid); 171157dacad5SJay Sternberg release_cq: 171257dacad5SJay Sternberg adapter_delete_cq(dev, qid); 171357dacad5SJay Sternberg return result; 171457dacad5SJay Sternberg } 171557dacad5SJay Sternberg 1716f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 171757dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 171877f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 171957dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1720e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 172157dacad5SJay Sternberg .timeout = nvme_timeout, 172257dacad5SJay Sternberg }; 172357dacad5SJay Sternberg 1724f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1725376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1726d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1727376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1728376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1729376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1730e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1731376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1732376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1733c6d962aeSChristoph Hellwig .poll = nvme_poll, 1734dabcefabSJens Axboe }; 1735dabcefabSJens Axboe 173657dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 173757dacad5SJay Sternberg { 17381c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 173969d9a99cSKeith Busch /* 174069d9a99cSKeith Busch * If the controller was reset during removal, it's possible 174169d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 174269d9a99cSKeith Busch * queue to flush these to completion. 174369d9a99cSKeith Busch */ 1744*9f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 17456f8191fdSChristoph Hellwig blk_mq_destroy_queue(dev->ctrl.admin_q); 174696ef1be5SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 174757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 174857dacad5SJay Sternberg } 174957dacad5SJay Sternberg } 175057dacad5SJay Sternberg 1751f91b727cSChristoph Hellwig static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 175257dacad5SJay Sternberg { 1753f91b727cSChristoph Hellwig struct blk_mq_tag_set *set = &dev->admin_tagset; 1754e3e9d50cSKeith Busch 1755f91b727cSChristoph Hellwig set->ops = &nvme_mq_admin_ops; 1756f91b727cSChristoph Hellwig set->nr_hw_queues = 1; 175757dacad5SJay Sternberg 1758f91b727cSChristoph Hellwig set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1759f91b727cSChristoph Hellwig set->timeout = NVME_ADMIN_TIMEOUT; 1760f91b727cSChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 1761f91b727cSChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 1762f91b727cSChristoph Hellwig set->flags = BLK_MQ_F_NO_SCHED; 1763f91b727cSChristoph Hellwig set->driver_data = dev; 1764f91b727cSChristoph Hellwig 1765f91b727cSChristoph Hellwig if (blk_mq_alloc_tag_set(set)) 176657dacad5SJay Sternberg return -ENOMEM; 1767f91b727cSChristoph Hellwig dev->ctrl.admin_tagset = set; 176857dacad5SJay Sternberg 1769f91b727cSChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(set); 17701c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 1771f91b727cSChristoph Hellwig blk_mq_free_tag_set(set); 1772da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 177357dacad5SJay Sternberg return -ENOMEM; 177457dacad5SJay Sternberg } 177557dacad5SJay Sternberg return 0; 177657dacad5SJay Sternberg } 177757dacad5SJay Sternberg 177897f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 177997f6ef64SXu Yu { 178097f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 178197f6ef64SXu Yu } 178297f6ef64SXu Yu 178397f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 178497f6ef64SXu Yu { 178597f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 178697f6ef64SXu Yu 178797f6ef64SXu Yu if (size <= dev->bar_mapped_size) 178897f6ef64SXu Yu return 0; 178997f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 179097f6ef64SXu Yu return -ENOMEM; 179197f6ef64SXu Yu if (dev->bar) 179297f6ef64SXu Yu iounmap(dev->bar); 179397f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 179497f6ef64SXu Yu if (!dev->bar) { 179597f6ef64SXu Yu dev->bar_mapped_size = 0; 179697f6ef64SXu Yu return -ENOMEM; 179797f6ef64SXu Yu } 179897f6ef64SXu Yu dev->bar_mapped_size = size; 179997f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 180097f6ef64SXu Yu 180197f6ef64SXu Yu return 0; 180297f6ef64SXu Yu } 180397f6ef64SXu Yu 180401ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 180557dacad5SJay Sternberg { 180657dacad5SJay Sternberg int result; 180757dacad5SJay Sternberg u32 aqa; 180857dacad5SJay Sternberg struct nvme_queue *nvmeq; 180957dacad5SJay Sternberg 181097f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 181197f6ef64SXu Yu if (result < 0) 181297f6ef64SXu Yu return result; 181397f6ef64SXu Yu 18148ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 181520d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 181657dacad5SJay Sternberg 18177a67cbeaSChristoph Hellwig if (dev->subsystem && 18187a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18197a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 182057dacad5SJay Sternberg 1821b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 182257dacad5SJay Sternberg if (result < 0) 182357dacad5SJay Sternberg return result; 182457dacad5SJay Sternberg 1825a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1826147b27e4SSagi Grimberg if (result) 1827147b27e4SSagi Grimberg return result; 182857dacad5SJay Sternberg 1829635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1830635333e4SMax Gurtovoy 1831147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 183257dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 183357dacad5SJay Sternberg aqa |= aqa << 16; 183457dacad5SJay Sternberg 18357a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18367a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18377a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 183857dacad5SJay Sternberg 1839c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 184057dacad5SJay Sternberg if (result) 1841d4875622SKeith Busch return result; 184257dacad5SJay Sternberg 184357dacad5SJay Sternberg nvmeq->cq_vector = 0; 1844161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1845dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 184657dacad5SJay Sternberg if (result) { 18477c349ddeSKeith Busch dev->online_queues--; 1848d4875622SKeith Busch return result; 184957dacad5SJay Sternberg } 185057dacad5SJay Sternberg 18514e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 185257dacad5SJay Sternberg return result; 185357dacad5SJay Sternberg } 185457dacad5SJay Sternberg 1855749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 185657dacad5SJay Sternberg { 18574b04cc6aSJens Axboe unsigned i, max, rw_queues; 1858749941f2SChristoph Hellwig int ret = 0; 185957dacad5SJay Sternberg 1860d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1861a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1862749941f2SChristoph Hellwig ret = -ENOMEM; 186357dacad5SJay Sternberg break; 1864749941f2SChristoph Hellwig } 1865749941f2SChristoph Hellwig } 186657dacad5SJay Sternberg 1867d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1868e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1869e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1870e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18714b04cc6aSJens Axboe } else { 18724b04cc6aSJens Axboe rw_queues = max; 18734b04cc6aSJens Axboe } 18744b04cc6aSJens Axboe 1875949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18764b04cc6aSJens Axboe bool polled = i > rw_queues; 18774b04cc6aSJens Axboe 18784b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1879d4875622SKeith Busch if (ret) 188057dacad5SJay Sternberg break; 188157dacad5SJay Sternberg } 188257dacad5SJay Sternberg 1883749941f2SChristoph Hellwig /* 1884749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18858adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18868adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1887749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1888749941f2SChristoph Hellwig */ 1889749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 189057dacad5SJay Sternberg } 189157dacad5SJay Sternberg 189288de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 189357dacad5SJay Sternberg { 189488de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 189588de4598SChristoph Hellwig 189688de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 189788de4598SChristoph Hellwig } 189888de4598SChristoph Hellwig 189988de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 190088de4598SChristoph Hellwig { 190188de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 190288de4598SChristoph Hellwig } 190388de4598SChristoph Hellwig 1904f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 190557dacad5SJay Sternberg { 190688de4598SChristoph Hellwig u64 size, offset; 190757dacad5SJay Sternberg resource_size_t bar_size; 190857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19098969f1f8SChristoph Hellwig int bar; 191057dacad5SJay Sternberg 19119fe5c59fSKeith Busch if (dev->cmb_size) 19129fe5c59fSKeith Busch return; 19139fe5c59fSKeith Busch 191420d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 191520d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 191620d3bb92SKlaus Jensen 19177a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1918f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1919f65efd6dSChristoph Hellwig return; 1920202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 192157dacad5SJay Sternberg 192288de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 192388de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19248969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19258969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 192657dacad5SJay Sternberg 192757dacad5SJay Sternberg if (offset > bar_size) 1928f65efd6dSChristoph Hellwig return; 192957dacad5SJay Sternberg 193057dacad5SJay Sternberg /* 193120d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 193220d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 193320d3bb92SKlaus Jensen */ 193420d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 193520d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 193620d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 193720d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 193820d3bb92SKlaus Jensen } 193920d3bb92SKlaus Jensen 194020d3bb92SKlaus Jensen /* 194157dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 194257dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 194357dacad5SJay Sternberg * the reported size of the BAR 194457dacad5SJay Sternberg */ 194557dacad5SJay Sternberg if (size > bar_size - offset) 194657dacad5SJay Sternberg size = bar_size - offset; 194757dacad5SJay Sternberg 19480f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19490f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19500f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1951f65efd6dSChristoph Hellwig return; 19520f238ff5SLogan Gunthorpe } 19530f238ff5SLogan Gunthorpe 195457dacad5SJay Sternberg dev->cmb_size = size; 19550f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19560f238ff5SLogan Gunthorpe 19570f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19580f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19590f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 196057dacad5SJay Sternberg } 196157dacad5SJay Sternberg 196287ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 196357dacad5SJay Sternberg { 19646c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19654033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1966f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 196787ad72a5SChristoph Hellwig int ret; 196887ad72a5SChristoph Hellwig 196987ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 197087ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 197187ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19726c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 197387ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 197487ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 197587ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 197687ad72a5SChristoph Hellwig 197787ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 197887ad72a5SChristoph Hellwig if (ret) { 197987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 198087ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 198187ad72a5SChristoph Hellwig ret, bits); 1982a5df5e79SKeith Busch } else 1983a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1984a5df5e79SKeith Busch 198587ad72a5SChristoph Hellwig return ret; 198687ad72a5SChristoph Hellwig } 198787ad72a5SChristoph Hellwig 198887ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 198987ad72a5SChristoph Hellwig { 199087ad72a5SChristoph Hellwig int i; 199187ad72a5SChristoph Hellwig 199287ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 199387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19946c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 199587ad72a5SChristoph Hellwig 1996cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1997cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1998cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 199987ad72a5SChristoph Hellwig } 200087ad72a5SChristoph Hellwig 200187ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 200287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 20034033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20044033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20054033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 200687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20077e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 200887ad72a5SChristoph Hellwig } 200987ad72a5SChristoph Hellwig 201092dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 201192dc6895SChristoph Hellwig u32 chunk_size) 201287ad72a5SChristoph Hellwig { 201387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 201492dc6895SChristoph Hellwig u32 max_entries, len; 20154033f35dSChristoph Hellwig dma_addr_t descs_dma; 20162ee0e4edSDan Carpenter int i = 0; 201787ad72a5SChristoph Hellwig void **bufs; 20186fbcde66SMinwoo Im u64 size, tmp; 201987ad72a5SChristoph Hellwig 202087ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 202187ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 202287ad72a5SChristoph Hellwig max_entries = tmp; 2023044a9df1SChristoph Hellwig 2024044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2025044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2026044a9df1SChristoph Hellwig 2027750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20284033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 202987ad72a5SChristoph Hellwig if (!descs) 203087ad72a5SChristoph Hellwig goto out; 203187ad72a5SChristoph Hellwig 203287ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 203387ad72a5SChristoph Hellwig if (!bufs) 203487ad72a5SChristoph Hellwig goto out_free_descs; 203587ad72a5SChristoph Hellwig 2036244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 203787ad72a5SChristoph Hellwig dma_addr_t dma_addr; 203887ad72a5SChristoph Hellwig 203950cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 204087ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 204187ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 204287ad72a5SChristoph Hellwig if (!bufs[i]) 204387ad72a5SChristoph Hellwig break; 204487ad72a5SChristoph Hellwig 204587ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20466c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 204787ad72a5SChristoph Hellwig i++; 204887ad72a5SChristoph Hellwig } 204987ad72a5SChristoph Hellwig 205092dc6895SChristoph Hellwig if (!size) 205187ad72a5SChristoph Hellwig goto out_free_bufs; 205287ad72a5SChristoph Hellwig 205387ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 205487ad72a5SChristoph Hellwig dev->host_mem_size = size; 205587ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20564033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 205787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 205887ad72a5SChristoph Hellwig return 0; 205987ad72a5SChristoph Hellwig 206087ad72a5SChristoph Hellwig out_free_bufs: 206187ad72a5SChristoph Hellwig while (--i >= 0) { 20626c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 206387ad72a5SChristoph Hellwig 2064cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2065cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2066cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 206787ad72a5SChristoph Hellwig } 206887ad72a5SChristoph Hellwig 206987ad72a5SChristoph Hellwig kfree(bufs); 207087ad72a5SChristoph Hellwig out_free_descs: 20714033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20724033f35dSChristoph Hellwig descs_dma); 207387ad72a5SChristoph Hellwig out: 207487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 207587ad72a5SChristoph Hellwig return -ENOMEM; 207687ad72a5SChristoph Hellwig } 207787ad72a5SChristoph Hellwig 207892dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 207992dc6895SChristoph Hellwig { 20809dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20819dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20829dc54a0dSChaitanya Kulkarni u64 chunk_size; 208392dc6895SChristoph Hellwig 208492dc6895SChristoph Hellwig /* start big and work our way down */ 20859dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 208692dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 208792dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 208892dc6895SChristoph Hellwig return 0; 208992dc6895SChristoph Hellwig nvme_free_host_mem(dev); 209092dc6895SChristoph Hellwig } 209192dc6895SChristoph Hellwig } 209292dc6895SChristoph Hellwig 209392dc6895SChristoph Hellwig return -ENOMEM; 209492dc6895SChristoph Hellwig } 209592dc6895SChristoph Hellwig 20969620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 209787ad72a5SChristoph Hellwig { 209887ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 209987ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 210087ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 210187ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 21026fbcde66SMinwoo Im int ret; 210387ad72a5SChristoph Hellwig 2104acb71e53SChristoph Hellwig if (!dev->ctrl.hmpre) 2105acb71e53SChristoph Hellwig return 0; 2106acb71e53SChristoph Hellwig 210787ad72a5SChristoph Hellwig preferred = min(preferred, max); 210887ad72a5SChristoph Hellwig if (min > max) { 210987ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 211087ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 211187ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 211287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21139620cfbaSChristoph Hellwig return 0; 211487ad72a5SChristoph Hellwig } 211587ad72a5SChristoph Hellwig 211687ad72a5SChristoph Hellwig /* 211787ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 211887ad72a5SChristoph Hellwig */ 211987ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 212087ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 212187ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 212287ad72a5SChristoph Hellwig else 212387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 212487ad72a5SChristoph Hellwig } 212587ad72a5SChristoph Hellwig 212687ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 212792dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 212892dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 212992dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21309620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 213187ad72a5SChristoph Hellwig } 213287ad72a5SChristoph Hellwig 213392dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 213492dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 213592dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 213692dc6895SChristoph Hellwig } 213792dc6895SChristoph Hellwig 21389620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21399620cfbaSChristoph Hellwig if (ret) 214087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21419620cfbaSChristoph Hellwig return ret; 214257dacad5SJay Sternberg } 214357dacad5SJay Sternberg 21440521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21450521905eSKeith Busch char *buf) 21460521905eSKeith Busch { 21470521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21480521905eSKeith Busch 21490521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21500521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21510521905eSKeith Busch } 21520521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21530521905eSKeith Busch 21541751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21551751e97aSKeith Busch char *buf) 21561751e97aSKeith Busch { 21571751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21581751e97aSKeith Busch 21591751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21601751e97aSKeith Busch } 21611751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21621751e97aSKeith Busch 21631751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21641751e97aSKeith Busch char *buf) 21651751e97aSKeith Busch { 21661751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21671751e97aSKeith Busch 21681751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21691751e97aSKeith Busch } 21701751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21711751e97aSKeith Busch 2172a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2173a5df5e79SKeith Busch char *buf) 2174a5df5e79SKeith Busch { 2175a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2176a5df5e79SKeith Busch 2177a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2178a5df5e79SKeith Busch } 2179a5df5e79SKeith Busch 2180a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2181a5df5e79SKeith Busch const char *buf, size_t count) 2182a5df5e79SKeith Busch { 2183a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2184a5df5e79SKeith Busch bool new; 2185a5df5e79SKeith Busch int ret; 2186a5df5e79SKeith Busch 2187a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2188a5df5e79SKeith Busch return -EINVAL; 2189a5df5e79SKeith Busch 2190a5df5e79SKeith Busch if (new == ndev->hmb) 2191a5df5e79SKeith Busch return count; 2192a5df5e79SKeith Busch 2193a5df5e79SKeith Busch if (new) { 2194a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2195a5df5e79SKeith Busch } else { 2196a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2197a5df5e79SKeith Busch if (!ret) 2198a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2199a5df5e79SKeith Busch } 2200a5df5e79SKeith Busch 2201a5df5e79SKeith Busch if (ret < 0) 2202a5df5e79SKeith Busch return ret; 2203a5df5e79SKeith Busch 2204a5df5e79SKeith Busch return count; 2205a5df5e79SKeith Busch } 2206a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2207a5df5e79SKeith Busch 22080521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22090521905eSKeith Busch struct attribute *a, int n) 22100521905eSKeith Busch { 22110521905eSKeith Busch struct nvme_ctrl *ctrl = 22120521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22130521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22140521905eSKeith Busch 22151751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22161751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22171751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22181751e97aSKeith Busch if (!dev->cmbsz) 22190521905eSKeith Busch return 0; 22201751e97aSKeith Busch } 2221a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2222a5df5e79SKeith Busch return 0; 2223a5df5e79SKeith Busch 22240521905eSKeith Busch return a->mode; 22250521905eSKeith Busch } 22260521905eSKeith Busch 22270521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22280521905eSKeith Busch &dev_attr_cmb.attr, 22291751e97aSKeith Busch &dev_attr_cmbloc.attr, 22301751e97aSKeith Busch &dev_attr_cmbsz.attr, 2231a5df5e79SKeith Busch &dev_attr_hmb.attr, 22320521905eSKeith Busch NULL, 22330521905eSKeith Busch }; 22340521905eSKeith Busch 223586adbf0cSChristoph Hellwig static const struct attribute_group nvme_pci_dev_attrs_group = { 22360521905eSKeith Busch .attrs = nvme_pci_attrs, 22370521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22380521905eSKeith Busch }; 22390521905eSKeith Busch 224086adbf0cSChristoph Hellwig static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 224186adbf0cSChristoph Hellwig &nvme_dev_attrs_group, 224286adbf0cSChristoph Hellwig &nvme_pci_dev_attrs_group, 224386adbf0cSChristoph Hellwig NULL, 224486adbf0cSChristoph Hellwig }; 224586adbf0cSChristoph Hellwig 2246612b7286SMing Lei /* 2247612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2248612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2249612b7286SMing Lei */ 2250612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22513b6592f7SJens Axboe { 2252612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22532a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2254c45b1fa2SMing Lei 22553b6592f7SJens Axboe /* 2256ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2257612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2258612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2259612b7286SMing Lei * 2260612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2261612b7286SMing Lei * write and read queues. 2262612b7286SMing Lei * 2263612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2264612b7286SMing Lei * queue. 22653b6592f7SJens Axboe */ 2266612b7286SMing Lei if (!nrirqs) { 2267612b7286SMing Lei nrirqs = 1; 2268612b7286SMing Lei nr_read_queues = 0; 22692a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2270612b7286SMing Lei nr_read_queues = 0; 22712a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2272612b7286SMing Lei nr_read_queues = 1; 22733b6592f7SJens Axboe } else { 22742a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22753b6592f7SJens Axboe } 2276612b7286SMing Lei 2277612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2278612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2279612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2280612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2281612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22823b6592f7SJens Axboe } 22833b6592f7SJens Axboe 22846451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22853b6592f7SJens Axboe { 22863b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22873b6592f7SJens Axboe struct irq_affinity affd = { 22883b6592f7SJens Axboe .pre_vectors = 1, 2289612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2290612b7286SMing Lei .priv = dev, 22913b6592f7SJens Axboe }; 229221cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22936451fe73SJens Axboe 22946451fe73SJens Axboe /* 229521cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 229621cc2f3fSJeffle Xu * left over for non-polled I/O. 22976451fe73SJens Axboe */ 229821cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 229921cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 23003b6592f7SJens Axboe 230121cc2f3fSJeffle Xu /* 230221cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 230321cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 230421cc2f3fSJeffle Xu */ 2305612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2306612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23073b6592f7SJens Axboe 230866341331SBenjamin Herrenschmidt /* 230921cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 231021cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 231121cc2f3fSJeffle Xu * vector. 231266341331SBenjamin Herrenschmidt */ 231366341331SBenjamin Herrenschmidt irq_queues = 1; 231421cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 231521cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2316612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23173b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23183b6592f7SJens Axboe } 23193b6592f7SJens Axboe 23208fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23218fae268bSKeith Busch { 23228fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23238fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23248fae268bSKeith Busch } 23258fae268bSKeith Busch 23262a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23272a5bcfddSWeiping Zhang { 2328e3aef095SNiklas Schnelle /* 2329e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2330e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2331e3aef095SNiklas Schnelle */ 2332e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2333e3aef095SNiklas Schnelle return 1; 23342a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23352a5bcfddSWeiping Zhang } 23362a5bcfddSWeiping Zhang 233757dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 233857dacad5SJay Sternberg { 2339147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 234057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23412a5bcfddSWeiping Zhang unsigned int nr_io_queues; 234297f6ef64SXu Yu unsigned long size; 23432a5bcfddSWeiping Zhang int result; 234457dacad5SJay Sternberg 23452a5bcfddSWeiping Zhang /* 23462a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23472a5bcfddSWeiping Zhang * stable values to work with. 23482a5bcfddSWeiping Zhang */ 23492a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23502a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2351d38e9f04SBenjamin Herrenschmidt 2352ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23539a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23549a0be7abSChristoph Hellwig if (result < 0) 235557dacad5SJay Sternberg return result; 23569a0be7abSChristoph Hellwig 2357f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2358a5229050SKeith Busch return 0; 235957dacad5SJay Sternberg 2360e4b9852aSCasey Chen /* 2361e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2362e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2363e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2364e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2365e4b9852aSCasey Chen * nvme_dev_disable() path. 2366e4b9852aSCasey Chen */ 2367e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2368e4b9852aSCasey Chen if (result) 2369e4b9852aSCasey Chen return result; 2370e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2371e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23724e224106SChristoph Hellwig 23730f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 237457dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 237557dacad5SJay Sternberg sizeof(struct nvme_command)); 237657dacad5SJay Sternberg if (result > 0) 237757dacad5SJay Sternberg dev->q_depth = result; 237857dacad5SJay Sternberg else 23790f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 238057dacad5SJay Sternberg } 238157dacad5SJay Sternberg 238257dacad5SJay Sternberg do { 238397f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 238497f6ef64SXu Yu result = nvme_remap_bar(dev, size); 238597f6ef64SXu Yu if (!result) 238657dacad5SJay Sternberg break; 2387e4b9852aSCasey Chen if (!--nr_io_queues) { 2388e4b9852aSCasey Chen result = -ENOMEM; 2389e4b9852aSCasey Chen goto out_unlock; 2390e4b9852aSCasey Chen } 239157dacad5SJay Sternberg } while (1); 239257dacad5SJay Sternberg adminq->q_db = dev->dbs; 239357dacad5SJay Sternberg 23948fae268bSKeith Busch retry: 239557dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2396e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23970ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 239857dacad5SJay Sternberg 239957dacad5SJay Sternberg /* 240057dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 240157dacad5SJay Sternberg * setting up the full range we need. 240257dacad5SJay Sternberg */ 2403dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 24043b6592f7SJens Axboe 24053b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2406e4b9852aSCasey Chen if (result <= 0) { 2407e4b9852aSCasey Chen result = -EIO; 2408e4b9852aSCasey Chen goto out_unlock; 2409e4b9852aSCasey Chen } 24103b6592f7SJens Axboe 241122b55601SKeith Busch dev->num_vecs = result; 24124b04cc6aSJens Axboe result = max(result - 1, 1); 2413e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 241457dacad5SJay Sternberg 241557dacad5SJay Sternberg /* 241657dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 241757dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 241857dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 241957dacad5SJay Sternberg * number of interrupts. 242057dacad5SJay Sternberg */ 2421dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24227c349ddeSKeith Busch if (result) 2423e4b9852aSCasey Chen goto out_unlock; 24244e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2425e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24268fae268bSKeith Busch 24278fae268bSKeith Busch result = nvme_create_io_queues(dev); 24288fae268bSKeith Busch if (result || dev->online_queues < 2) 24298fae268bSKeith Busch return result; 24308fae268bSKeith Busch 24318fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24328fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24338fae268bSKeith Busch nvme_disable_io_queues(dev); 2434e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2435e4b9852aSCasey Chen if (result) 2436e4b9852aSCasey Chen return result; 24378fae268bSKeith Busch nvme_suspend_io_queues(dev); 24388fae268bSKeith Busch goto retry; 24398fae268bSKeith Busch } 24408fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24418fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24428fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24438fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24448fae268bSKeith Busch return 0; 2445e4b9852aSCasey Chen out_unlock: 2446e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2447e4b9852aSCasey Chen return result; 244857dacad5SJay Sternberg } 244957dacad5SJay Sternberg 2450de671d61SJens Axboe static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2451de671d61SJens Axboe blk_status_t error) 2452db3cbfffSKeith Busch { 2453db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2454db3cbfffSKeith Busch 2455db3cbfffSKeith Busch blk_mq_free_request(req); 2456d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2457de671d61SJens Axboe return RQ_END_IO_NONE; 2458db3cbfffSKeith Busch } 2459db3cbfffSKeith Busch 2460de671d61SJens Axboe static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2461de671d61SJens Axboe blk_status_t error) 2462db3cbfffSKeith Busch { 2463db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2464db3cbfffSKeith Busch 2465d1ed6aa1SChristoph Hellwig if (error) 2466d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2467db3cbfffSKeith Busch 2468de671d61SJens Axboe return nvme_del_queue_end(req, error); 2469db3cbfffSKeith Busch } 2470db3cbfffSKeith Busch 2471db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2472db3cbfffSKeith Busch { 2473db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2474db3cbfffSKeith Busch struct request *req; 2475f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2476db3cbfffSKeith Busch 2477db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2478db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2479db3cbfffSKeith Busch 2480e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2481db3cbfffSKeith Busch if (IS_ERR(req)) 2482db3cbfffSKeith Busch return PTR_ERR(req); 2483e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2484db3cbfffSKeith Busch 2485e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2486e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2487e2e53086SChristoph Hellwig else 2488e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2489db3cbfffSKeith Busch req->end_io_data = nvmeq; 2490db3cbfffSKeith Busch 2491d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2492128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2493e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2494db3cbfffSKeith Busch return 0; 2495db3cbfffSKeith Busch } 2496db3cbfffSKeith Busch 24978fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2498db3cbfffSKeith Busch { 24995271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2500db3cbfffSKeith Busch unsigned long timeout; 2501db3cbfffSKeith Busch 2502db3cbfffSKeith Busch retry: 2503dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 25045271edd4SChristoph Hellwig while (nr_queues > 0) { 25055271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2506db3cbfffSKeith Busch break; 25075271edd4SChristoph Hellwig nr_queues--; 25085271edd4SChristoph Hellwig sent++; 25095271edd4SChristoph Hellwig } 2510d1ed6aa1SChristoph Hellwig while (sent) { 2511d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2512d1ed6aa1SChristoph Hellwig 2513d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25145271edd4SChristoph Hellwig timeout); 2515db3cbfffSKeith Busch if (timeout == 0) 25165271edd4SChristoph Hellwig return false; 2517d1ed6aa1SChristoph Hellwig 2518d1ed6aa1SChristoph Hellwig sent--; 25195271edd4SChristoph Hellwig if (nr_queues) 2520db3cbfffSKeith Busch goto retry; 2521db3cbfffSKeith Busch } 25225271edd4SChristoph Hellwig return true; 2523db3cbfffSKeith Busch } 2524db3cbfffSKeith Busch 25252455a4b7SChristoph Hellwig static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 252657dacad5SJay Sternberg { 25272455a4b7SChristoph Hellwig struct blk_mq_tag_set * set = &dev->tagset; 25282b1b7e78SJianchao Wang int ret; 25292b1b7e78SJianchao Wang 25302455a4b7SChristoph Hellwig set->ops = &nvme_mq_ops; 25312455a4b7SChristoph Hellwig set->nr_hw_queues = dev->online_queues - 1; 25326ee742faSKeith Busch set->nr_maps = 1; 25336ee742faSKeith Busch if (dev->io_queues[HCTX_TYPE_READ]) 25346ee742faSKeith Busch set->nr_maps = 2; 2535ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 25366ee742faSKeith Busch set->nr_maps = 3; 25372455a4b7SChristoph Hellwig set->timeout = NVME_IO_TIMEOUT; 25382455a4b7SChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 25392455a4b7SChristoph Hellwig set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 25402455a4b7SChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 25412455a4b7SChristoph Hellwig set->flags = BLK_MQ_F_SHOULD_MERGE; 25422455a4b7SChristoph Hellwig set->driver_data = dev; 254357dacad5SJay Sternberg 2544d38e9f04SBenjamin Herrenschmidt /* 2545d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2546d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2547d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2548d38e9f04SBenjamin Herrenschmidt */ 2549d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 25502455a4b7SChristoph Hellwig set->reserved_tags = NVME_AQ_DEPTH; 2551d38e9f04SBenjamin Herrenschmidt 25522455a4b7SChristoph Hellwig ret = blk_mq_alloc_tag_set(set); 25532b1b7e78SJianchao Wang if (ret) { 25542b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25552b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25565d02a5c1SKeith Busch return; 25572b1b7e78SJianchao Wang } 25582455a4b7SChristoph Hellwig dev->ctrl.tagset = set; 255957dacad5SJay Sternberg } 2560949928c1SKeith Busch 25612455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 25622455a4b7SChristoph Hellwig { 25632455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 25642455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 25652455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 256657dacad5SJay Sternberg } 256757dacad5SJay Sternberg 2568b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 256957dacad5SJay Sternberg { 2570b00a726aSKeith Busch int result = -ENOMEM; 257157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25724bdf2603SFilippo Sironi int dma_address_bits = 64; 257357dacad5SJay Sternberg 257457dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 257557dacad5SJay Sternberg return result; 257657dacad5SJay Sternberg 257757dacad5SJay Sternberg pci_set_master(pdev); 257857dacad5SJay Sternberg 25794bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25804bdf2603SFilippo Sironi dma_address_bits = 48; 25814bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 258257dacad5SJay Sternberg goto disable; 258357dacad5SJay Sternberg 25847a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 258557dacad5SJay Sternberg result = -ENODEV; 2586b00a726aSKeith Busch goto disable; 258757dacad5SJay Sternberg } 258857dacad5SJay Sternberg 258957dacad5SJay Sternberg /* 2590a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2591a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2592a5229050SKeith Busch * adjust this later. 259357dacad5SJay Sternberg */ 2594dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2595dca51e78SChristoph Hellwig if (result < 0) 2596dca51e78SChristoph Hellwig return result; 259757dacad5SJay Sternberg 259820d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25997a67cbeaSChristoph Hellwig 26007442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2601b27c1e68Sweiping zhang io_queue_depth); 2602aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 260320d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 26047a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 26051f390c1fSStephan Günther 26061f390c1fSStephan Günther /* 260766341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260866341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 260966341331SBenjamin Herrenschmidt * so we don't bother updating it here. 261066341331SBenjamin Herrenschmidt */ 261166341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 261266341331SBenjamin Herrenschmidt dev->io_sqes = 7; 261366341331SBenjamin Herrenschmidt else 2614c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26151f390c1fSStephan Günther 26161f390c1fSStephan Günther /* 26171f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26181f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26191f390c1fSStephan Günther */ 26201f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26211f390c1fSStephan Günther dev->q_depth = 2; 26229bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26239bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26241f390c1fSStephan Günther dev->q_depth); 2625d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2626d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262720d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2628d554b5e1SMartin K. Petersen dev->q_depth = 64; 2629d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2630d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26311f390c1fSStephan Günther } 26321f390c1fSStephan Günther 2633d38e9f04SBenjamin Herrenschmidt /* 2634d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2635d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2636d38e9f04SBenjamin Herrenschmidt */ 2637d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2638d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2639d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2640d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2641d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2642d38e9f04SBenjamin Herrenschmidt } 2643d38e9f04SBenjamin Herrenschmidt 2644d38e9f04SBenjamin Herrenschmidt 2645f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2646202021c1SStephen Bates 2647a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2648a0a3408eSKeith Busch pci_save_state(pdev); 2649a6ee7f19SChristoph Hellwig 2650a6ee7f19SChristoph Hellwig return nvme_pci_configure_admin_queue(dev); 265157dacad5SJay Sternberg 265257dacad5SJay Sternberg disable: 265357dacad5SJay Sternberg pci_disable_device(pdev); 265457dacad5SJay Sternberg return result; 265557dacad5SJay Sternberg } 265657dacad5SJay Sternberg 265757dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265857dacad5SJay Sternberg { 2659b00a726aSKeith Busch if (dev->bar) 2660b00a726aSKeith Busch iounmap(dev->bar); 2661a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2662b00a726aSKeith Busch } 2663b00a726aSKeith Busch 2664b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2665b00a726aSKeith Busch { 266657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266757dacad5SJay Sternberg 2668dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 266957dacad5SJay Sternberg 2670a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2671a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 267257dacad5SJay Sternberg pci_disable_device(pdev); 267357dacad5SJay Sternberg } 2674a0a3408eSKeith Busch } 267557dacad5SJay Sternberg 2676a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 267757dacad5SJay Sternberg { 2678e43269e6SKeith Busch bool dead = true, freeze = false; 2679302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 268057dacad5SJay Sternberg 268177bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2682081f5e75SKeith Busch if (pci_is_enabled(pdev)) { 2683081f5e75SKeith Busch u32 csts; 2684081f5e75SKeith Busch 2685081f5e75SKeith Busch if (pci_device_is_present(pdev)) 2686081f5e75SKeith Busch csts = readl(dev->bar + NVME_REG_CSTS); 2687081f5e75SKeith Busch else 2688081f5e75SKeith Busch csts = ~0; 2689302ad8ccSKeith Busch 2690ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2691e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2692e43269e6SKeith Busch freeze = true; 2693302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2694e43269e6SKeith Busch } 2695302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2696302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 269757dacad5SJay Sternberg } 2698c21377f8SGabriel Krisman Bertazi 2699302ad8ccSKeith Busch /* 2700302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2701302ad8ccSKeith Busch * doing a safe shutdown. 2702302ad8ccSKeith Busch */ 2703e43269e6SKeith Busch if (!dead && shutdown && freeze) 2704302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 270587ad72a5SChristoph Hellwig 2706*9f27bd70SChristoph Hellwig nvme_quiesce_io_queues(&dev->ctrl); 27079a915a5bSJianchao Wang 270864ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 27098fae268bSKeith Busch nvme_disable_io_queues(dev); 2710a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 271157dacad5SJay Sternberg } 27128fae268bSKeith Busch nvme_suspend_io_queues(dev); 27138fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2714b00a726aSKeith Busch nvme_pci_disable(dev); 2715fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 271657dacad5SJay Sternberg 27171fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 27181fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2719302ad8ccSKeith Busch 2720302ad8ccSKeith Busch /* 2721302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2722302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2723302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2724302ad8ccSKeith Busch */ 2725c8e9e9b7SKeith Busch if (shutdown) { 2726*9f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2727c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 2728*9f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 2729c8e9e9b7SKeith Busch } 273077bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 273157dacad5SJay Sternberg } 273257dacad5SJay Sternberg 2733c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2734c1ac9a4bSKeith Busch { 2735c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2736c1ac9a4bSKeith Busch return -EBUSY; 2737c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2738c1ac9a4bSKeith Busch return 0; 2739c1ac9a4bSKeith Busch } 2740c1ac9a4bSKeith Busch 274157dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 274257dacad5SJay Sternberg { 274357dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2744c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2745c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 274657dacad5SJay Sternberg if (!dev->prp_page_pool) 274757dacad5SJay Sternberg return -ENOMEM; 274857dacad5SJay Sternberg 274957dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 275057dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 275157dacad5SJay Sternberg 256, 256, 0); 275257dacad5SJay Sternberg if (!dev->prp_small_pool) { 275357dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275457dacad5SJay Sternberg return -ENOMEM; 275557dacad5SJay Sternberg } 275657dacad5SJay Sternberg return 0; 275757dacad5SJay Sternberg } 275857dacad5SJay Sternberg 275957dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 276057dacad5SJay Sternberg { 276157dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 276257dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 276357dacad5SJay Sternberg } 276457dacad5SJay Sternberg 2765081a7d95SChristoph Hellwig static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2766081a7d95SChristoph Hellwig { 2767081a7d95SChristoph Hellwig size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 2768081a7d95SChristoph Hellwig size_t alloc_size = sizeof(__le64 *) * npages + 2769081a7d95SChristoph Hellwig sizeof(struct scatterlist) * NVME_MAX_SEGS; 2770081a7d95SChristoph Hellwig 2771081a7d95SChristoph Hellwig WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2772081a7d95SChristoph Hellwig dev->iod_mempool = mempool_create_node(1, 2773081a7d95SChristoph Hellwig mempool_kmalloc, mempool_kfree, 2774081a7d95SChristoph Hellwig (void *)alloc_size, GFP_KERNEL, 2775081a7d95SChristoph Hellwig dev_to_node(dev->dev)); 2776081a7d95SChristoph Hellwig if (!dev->iod_mempool) 2777081a7d95SChristoph Hellwig return -ENOMEM; 2778081a7d95SChristoph Hellwig return 0; 2779081a7d95SChristoph Hellwig } 2780081a7d95SChristoph Hellwig 2781770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2782770597ecSKeith Busch { 2783770597ecSKeith Busch if (dev->tagset.tags) 2784770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2785770597ecSKeith Busch dev->ctrl.tagset = NULL; 2786770597ecSKeith Busch } 2787770597ecSKeith Busch 27882e87570bSChristoph Hellwig /* pairs with nvme_pci_alloc_dev */ 27891673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 279057dacad5SJay Sternberg { 27911673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 279257dacad5SJay Sternberg 2793770597ecSKeith Busch nvme_free_tagset(dev); 2794253fd4acSIsrael Rukshin put_device(dev->dev); 2795253fd4acSIsrael Rukshin kfree(dev->queues); 279657dacad5SJay Sternberg kfree(dev); 279757dacad5SJay Sternberg } 279857dacad5SJay Sternberg 2799fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 280057dacad5SJay Sternberg { 2801d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2802d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2803a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2804e71afda4SChaitanya Kulkarni int result; 280557dacad5SJay Sternberg 28067764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 28077764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 28087764656bSZhihao Cheng dev->ctrl.state); 2809e71afda4SChaitanya Kulkarni result = -ENODEV; 2810fd634f41SChristoph Hellwig goto out; 2811e71afda4SChaitanya Kulkarni } 2812fd634f41SChristoph Hellwig 2813fd634f41SChristoph Hellwig /* 2814fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2815fd634f41SChristoph Hellwig * moving on. 2816fd634f41SChristoph Hellwig */ 2817b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2818a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2819d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2820fd634f41SChristoph Hellwig 28215c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2822b00a726aSKeith Busch result = nvme_pci_enable(dev); 282357dacad5SJay Sternberg if (result) 28244726bcf3SKeith Busch goto out_unlock; 2825*9f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 28265c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28275c959d73SKeith Busch 28285c959d73SKeith Busch /* 28295c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28305c959d73SKeith Busch * initializing procedure here. 28315c959d73SKeith Busch */ 28325c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28335c959d73SKeith Busch dev_warn(dev->ctrl.device, 28345c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2835cee6c269SMinwoo Im result = -EBUSY; 28365c959d73SKeith Busch goto out; 28375c959d73SKeith Busch } 2838943e942eSJens Axboe 283994cc781fSChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2840ce4541f4SChristoph Hellwig if (result) 2841f58944e2SKeith Busch goto out; 2842ce4541f4SChristoph Hellwig 284365a54646SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 2844f9f38e33SHelen Koike 28459620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28469620cfbaSChristoph Hellwig if (result < 0) 28479620cfbaSChristoph Hellwig goto out; 284887ad72a5SChristoph Hellwig 284957dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 285057dacad5SJay Sternberg if (result) 2851f58944e2SKeith Busch goto out; 285257dacad5SJay Sternberg 285321f033f7SKeith Busch /* 28540ffc7e98SChristoph Hellwig * Freeze and update the number of I/O queues as thos might have 2855eac3ef26SChristoph Hellwig * changed. If there are no I/O queues left after this reset, keep the 2856eac3ef26SChristoph Hellwig * controller around but remove all namespaces. 285757dacad5SJay Sternberg */ 28580ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 2859*9f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2860302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 28612455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 28622455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2863302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 28640ffc7e98SChristoph Hellwig } else { 28650ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues lost\n"); 2866cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 2867*9f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 28680ffc7e98SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 28690ffc7e98SChristoph Hellwig nvme_free_tagset(dev); 28700ffc7e98SChristoph Hellwig } 287157dacad5SJay Sternberg 28722b1b7e78SJianchao Wang /* 28732b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 28742b1b7e78SJianchao Wang * recovery. 28752b1b7e78SJianchao Wang */ 28765d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 28772b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 28785d02a5c1SKeith Busch "failed to mark controller live state\n"); 2879e71afda4SChaitanya Kulkarni result = -ENODEV; 2880bb8d261eSChristoph Hellwig goto out; 2881bb8d261eSChristoph Hellwig } 288292911a55SChristoph Hellwig 2883d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 288457dacad5SJay Sternberg return; 288557dacad5SJay Sternberg 28864726bcf3SKeith Busch out_unlock: 28874726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 288857dacad5SJay Sternberg out: 2889c7c16c5bSChristoph Hellwig /* 2890c7c16c5bSChristoph Hellwig * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2891c7c16c5bSChristoph Hellwig * may be holding this pci_dev's device lock. 2892c7c16c5bSChristoph Hellwig */ 2893c7c16c5bSChristoph Hellwig dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2894c7c16c5bSChristoph Hellwig result); 2895c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2896c7c16c5bSChristoph Hellwig nvme_dev_disable(dev, true); 2897c7c16c5bSChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 2898c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 289957dacad5SJay Sternberg } 290057dacad5SJay Sternberg 29011c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 290257dacad5SJay Sternberg { 29031c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29041c63dc66SChristoph Hellwig return 0; 290557dacad5SJay Sternberg } 29061c63dc66SChristoph Hellwig 29075fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29085fd4ce1bSChristoph Hellwig { 29095fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29105fd4ce1bSChristoph Hellwig return 0; 29115fd4ce1bSChristoph Hellwig } 29125fd4ce1bSChristoph Hellwig 29137fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29147fd8930fSChristoph Hellwig { 29153a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29167fd8930fSChristoph Hellwig return 0; 29177fd8930fSChristoph Hellwig } 29187fd8930fSChristoph Hellwig 291997c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 292097c12223SKeith Busch { 292197c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 292297c12223SKeith Busch 29232db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 292497c12223SKeith Busch } 292597c12223SKeith Busch 29262f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 29272f0dad17SKeith Busch { 29282f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 29292f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 29302f0dad17SKeith Busch 29312f0dad17SKeith Busch dev_err(ctrl->device, 29322f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 29332f0dad17SKeith Busch pdev->vendor, pdev->device, 29342f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 29352f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 29362f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 29372f0dad17SKeith Busch subsys->firmware_rev); 29382f0dad17SKeith Busch } 29392f0dad17SKeith Busch 29402f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 29412f859441SLogan Gunthorpe { 29422f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 29432f859441SLogan Gunthorpe 29442f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 29452f859441SLogan Gunthorpe } 29462f859441SLogan Gunthorpe 29471c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29481a353d85SMing Lin .name = "pcie", 2949e439bb12SSagi Grimberg .module = THIS_MODULE, 29502f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 295186adbf0cSChristoph Hellwig .dev_attr_groups = nvme_pci_dev_attr_groups, 29521c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29535fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29547fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29551673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2956f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 295797c12223SKeith Busch .get_address = nvme_pci_get_address, 29582f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 29592f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 29601c63dc66SChristoph Hellwig }; 296157dacad5SJay Sternberg 2962b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2963b00a726aSKeith Busch { 2964b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2965b00a726aSKeith Busch 2966a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2967b00a726aSKeith Busch return -ENODEV; 2968b00a726aSKeith Busch 296997f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2970b00a726aSKeith Busch goto release; 2971b00a726aSKeith Busch 2972b00a726aSKeith Busch return 0; 2973b00a726aSKeith Busch release: 2974a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2975b00a726aSKeith Busch return -ENODEV; 2976b00a726aSKeith Busch } 2977b00a726aSKeith Busch 29788427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2979ff5350a8SAndy Lutomirski { 2980ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2981ff5350a8SAndy Lutomirski /* 2982ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2983ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2984ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2985ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2986ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2987ff5350a8SAndy Lutomirski * laptops. 2988ff5350a8SAndy Lutomirski */ 2989ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2990ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2991ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2992ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 29938427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 29948427bbc2SKai-Heng Feng /* 29958427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2996467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2997467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2998467c77d4SJarosław Janik * ASUS PRIME Z370-A 29998427bbc2SKai-Heng Feng */ 30008427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3001467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3002467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30038427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30041fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30051fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30061fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30071fae37acSShyjumon N /* 30081fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30091fae37acSShyjumon N * lowest idle power with quick resume latency on 30101fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30111fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30121fae37acSShyjumon N */ 30131fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30141fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30151fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3016ff5350a8SAndy Lutomirski } 3017ff5350a8SAndy Lutomirski 3018ff5350a8SAndy Lutomirski return 0; 3019ff5350a8SAndy Lutomirski } 3020ff5350a8SAndy Lutomirski 30212e87570bSChristoph Hellwig static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 30222e87570bSChristoph Hellwig const struct pci_device_id *id) 302357dacad5SJay Sternberg { 3024ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 30252e87570bSChristoph Hellwig int node = dev_to_node(&pdev->dev); 30262e87570bSChristoph Hellwig struct nvme_dev *dev; 30272e87570bSChristoph Hellwig int ret = -ENOMEM; 302857dacad5SJay Sternberg 302957dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30302fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 303157dacad5SJay Sternberg 303257dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 303357dacad5SJay Sternberg if (!dev) 30342e87570bSChristoph Hellwig return NULL; 30352e87570bSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30362e87570bSChristoph Hellwig mutex_init(&dev->shutdown_lock); 3037147b27e4SSagi Grimberg 30382a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30392a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 30402a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 30412a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30422a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 304357dacad5SJay Sternberg if (!dev->queues) 30442e87570bSChristoph Hellwig goto out_free_dev; 304557dacad5SJay Sternberg 304657dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 3047f3ca80fcSChristoph Hellwig 30488427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 30492744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3050df4f9bc4SDavid E. Box /* 3051df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3052df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3053df4f9bc4SDavid E. Box */ 3054df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3055df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3056df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3057df4f9bc4SDavid E. Box } 30582e87570bSChristoph Hellwig ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 30592e87570bSChristoph Hellwig quirks); 30602e87570bSChristoph Hellwig if (ret) 30612e87570bSChristoph Hellwig goto out_put_device; 30623f30a79cSChristoph Hellwig 30633f30a79cSChristoph Hellwig dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 30643f30a79cSChristoph Hellwig dma_set_max_seg_size(&pdev->dev, 0xffffffff); 30653f30a79cSChristoph Hellwig 30663f30a79cSChristoph Hellwig /* 30673f30a79cSChristoph Hellwig * Limit the max command size to prevent iod->sg allocations going 30683f30a79cSChristoph Hellwig * over a single page. 30693f30a79cSChristoph Hellwig */ 30703f30a79cSChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 30713f30a79cSChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 30723f30a79cSChristoph Hellwig dev->ctrl.max_segments = NVME_MAX_SEGS; 30733f30a79cSChristoph Hellwig 30743f30a79cSChristoph Hellwig /* 30753f30a79cSChristoph Hellwig * There is no support for SGLs for metadata (yet), so we are limited to 30763f30a79cSChristoph Hellwig * a single integrity segment for the separate metadata pointer. 30773f30a79cSChristoph Hellwig */ 30783f30a79cSChristoph Hellwig dev->ctrl.max_integrity_segments = 1; 30792e87570bSChristoph Hellwig return dev; 30802e87570bSChristoph Hellwig 30812e87570bSChristoph Hellwig out_put_device: 30822e87570bSChristoph Hellwig put_device(dev->dev); 30832e87570bSChristoph Hellwig kfree(dev->queues); 30842e87570bSChristoph Hellwig out_free_dev: 30852e87570bSChristoph Hellwig kfree(dev); 30862e87570bSChristoph Hellwig return ERR_PTR(ret); 30872e87570bSChristoph Hellwig } 30882e87570bSChristoph Hellwig 30892e87570bSChristoph Hellwig static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 30902e87570bSChristoph Hellwig { 30912e87570bSChristoph Hellwig struct nvme_dev *dev; 30922e87570bSChristoph Hellwig int result = -ENOMEM; 30932e87570bSChristoph Hellwig 30942e87570bSChristoph Hellwig dev = nvme_pci_alloc_dev(pdev, id); 30952e87570bSChristoph Hellwig if (!dev) 30962e87570bSChristoph Hellwig return -ENOMEM; 30972e87570bSChristoph Hellwig 30982e87570bSChristoph Hellwig result = nvme_dev_map(dev); 30992e87570bSChristoph Hellwig if (result) 31002e87570bSChristoph Hellwig goto out_uninit_ctrl; 31012e87570bSChristoph Hellwig 31022e87570bSChristoph Hellwig result = nvme_setup_prp_pools(dev); 31032e87570bSChristoph Hellwig if (result) 31042e87570bSChristoph Hellwig goto out_dev_unmap; 3105df4f9bc4SDavid E. Box 3106081a7d95SChristoph Hellwig result = nvme_pci_alloc_iod_mempool(dev); 3107081a7d95SChristoph Hellwig if (result) 31082e87570bSChristoph Hellwig goto out_release_prp_pools; 3109b6e44b4cSKeith Busch 31101b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3111eac3ef26SChristoph Hellwig 3112eac3ef26SChristoph Hellwig result = nvme_pci_enable(dev); 3113eac3ef26SChristoph Hellwig if (result) 3114eac3ef26SChristoph Hellwig goto out_release_iod_mempool; 3115eac3ef26SChristoph Hellwig 3116eac3ef26SChristoph Hellwig result = nvme_pci_alloc_admin_tag_set(dev); 3117eac3ef26SChristoph Hellwig if (result) 3118eac3ef26SChristoph Hellwig goto out_disable; 3119eac3ef26SChristoph Hellwig 3120eac3ef26SChristoph Hellwig /* 3121eac3ef26SChristoph Hellwig * Mark the controller as connecting before sending admin commands to 3122eac3ef26SChristoph Hellwig * allow the timeout handler to do the right thing. 3123eac3ef26SChristoph Hellwig */ 3124eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3125eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3126eac3ef26SChristoph Hellwig "failed to mark controller CONNECTING\n"); 3127eac3ef26SChristoph Hellwig result = -EBUSY; 3128eac3ef26SChristoph Hellwig goto out_disable; 3129eac3ef26SChristoph Hellwig } 3130eac3ef26SChristoph Hellwig 3131eac3ef26SChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, false); 3132eac3ef26SChristoph Hellwig if (result) 3133eac3ef26SChristoph Hellwig goto out_disable; 3134eac3ef26SChristoph Hellwig 3135eac3ef26SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 3136eac3ef26SChristoph Hellwig 3137eac3ef26SChristoph Hellwig result = nvme_setup_host_mem(dev); 3138eac3ef26SChristoph Hellwig if (result < 0) 3139eac3ef26SChristoph Hellwig goto out_disable; 3140eac3ef26SChristoph Hellwig 3141eac3ef26SChristoph Hellwig result = nvme_setup_io_queues(dev); 3142eac3ef26SChristoph Hellwig if (result) 3143eac3ef26SChristoph Hellwig goto out_disable; 3144eac3ef26SChristoph Hellwig 3145eac3ef26SChristoph Hellwig if (dev->online_queues > 1) { 3146eac3ef26SChristoph Hellwig nvme_pci_alloc_tag_set(dev); 3147eac3ef26SChristoph Hellwig nvme_dbbuf_set(dev); 3148eac3ef26SChristoph Hellwig } else { 3149eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues not created\n"); 3150eac3ef26SChristoph Hellwig } 3151eac3ef26SChristoph Hellwig 3152eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3153eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3154eac3ef26SChristoph Hellwig "failed to mark controller live state\n"); 3155eac3ef26SChristoph Hellwig result = -ENODEV; 3156eac3ef26SChristoph Hellwig goto out_disable; 3157eac3ef26SChristoph Hellwig } 3158eac3ef26SChristoph Hellwig 31592e87570bSChristoph Hellwig pci_set_drvdata(pdev, dev); 31601b3c47c1SSagi Grimberg 3161eac3ef26SChristoph Hellwig nvme_start_ctrl(&dev->ctrl); 3162eac3ef26SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 316357dacad5SJay Sternberg return 0; 316457dacad5SJay Sternberg 3165eac3ef26SChristoph Hellwig out_disable: 3166eac3ef26SChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3167eac3ef26SChristoph Hellwig nvme_dev_disable(dev, true); 3168eac3ef26SChristoph Hellwig nvme_free_host_mem(dev); 3169eac3ef26SChristoph Hellwig nvme_dev_remove_admin(dev); 3170eac3ef26SChristoph Hellwig nvme_dbbuf_dma_free(dev); 3171eac3ef26SChristoph Hellwig nvme_free_queues(dev, 0); 3172eac3ef26SChristoph Hellwig out_release_iod_mempool: 3173eac3ef26SChristoph Hellwig mempool_destroy(dev->iod_mempool); 31742e87570bSChristoph Hellwig out_release_prp_pools: 317557dacad5SJay Sternberg nvme_release_prp_pools(dev); 31762e87570bSChristoph Hellwig out_dev_unmap: 3177b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 31782e87570bSChristoph Hellwig out_uninit_ctrl: 31792e87570bSChristoph Hellwig nvme_uninit_ctrl(&dev->ctrl); 318057dacad5SJay Sternberg return result; 318157dacad5SJay Sternberg } 318257dacad5SJay Sternberg 3183775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 318457dacad5SJay Sternberg { 318557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3186c1ac9a4bSKeith Busch 3187c1ac9a4bSKeith Busch /* 3188c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3189c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3190c1ac9a4bSKeith Busch * with ->remove(). 3191c1ac9a4bSKeith Busch */ 3192c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3193c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3194775755edSChristoph Hellwig } 319557dacad5SJay Sternberg 3196775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3197775755edSChristoph Hellwig { 3198f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3199c1ac9a4bSKeith Busch 3200c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3201c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 320257dacad5SJay Sternberg } 320357dacad5SJay Sternberg 320457dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 320557dacad5SJay Sternberg { 320657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 32074e523547SBaolin Wang 3208c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 320957dacad5SJay Sternberg } 321057dacad5SJay Sternberg 3211f58944e2SKeith Busch /* 3212f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3213f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3214f58944e2SKeith Busch * order to proceed. 3215f58944e2SKeith Busch */ 321657dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 321757dacad5SJay Sternberg { 321857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 321957dacad5SJay Sternberg 3220bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 322157dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 32220ff9d4e1SKeith Busch 32236db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 32240ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 32251d39e692SKeith Busch nvme_dev_disable(dev, true); 32266db28edaSKeith Busch } 32270ff9d4e1SKeith Busch 3228d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3229d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3230d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3231a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 323287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 323357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 3234c11b7716SChristoph Hellwig nvme_dbbuf_dma_free(dev); 323557dacad5SJay Sternberg nvme_free_queues(dev, 0); 3236c11b7716SChristoph Hellwig mempool_destroy(dev->iod_mempool); 323757dacad5SJay Sternberg nvme_release_prp_pools(dev); 3238b00a726aSKeith Busch nvme_dev_unmap(dev); 3239726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 324057dacad5SJay Sternberg } 324157dacad5SJay Sternberg 324257dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3243d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3244d916b1beSKeith Busch { 3245d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3246d916b1beSKeith Busch } 3247d916b1beSKeith Busch 3248d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3249d916b1beSKeith Busch { 3250d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3251d916b1beSKeith Busch } 3252d916b1beSKeith Busch 3253d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3254d916b1beSKeith Busch { 3255d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3256d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3257d916b1beSKeith Busch 32584eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3259d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3260e5ad96f3SKeith Busch goto reset; 3261e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3262e5ad96f3SKeith Busch goto reset; 3263e5ad96f3SKeith Busch 3264d916b1beSKeith Busch return 0; 3265e5ad96f3SKeith Busch reset: 3266e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3267d916b1beSKeith Busch } 3268d916b1beSKeith Busch 326957dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 327057dacad5SJay Sternberg { 327157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 327257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3273d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3274d916b1beSKeith Busch int ret = -EBUSY; 3275d916b1beSKeith Busch 32764eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32774eaefe8cSRafael J. Wysocki 3278d916b1beSKeith Busch /* 3279d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3280d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3281d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3282d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3283d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3284d916b1beSKeith Busch * device fully. 32854eaefe8cSRafael J. Wysocki * 32864eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32874eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32884eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32894eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3290d916b1beSKeith Busch */ 32914eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3292cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3293c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3294c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3295d916b1beSKeith Busch 3296d916b1beSKeith Busch nvme_start_freeze(ctrl); 3297d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3298d916b1beSKeith Busch nvme_sync_queues(ctrl); 3299d916b1beSKeith Busch 33005d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3301d916b1beSKeith Busch goto unfreeze; 3302d916b1beSKeith Busch 3303e5ad96f3SKeith Busch /* 3304e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3305e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3306e5ad96f3SKeith Busch * non-operational power state. 3307e5ad96f3SKeith Busch */ 3308e5ad96f3SKeith Busch if (ndev->hmb) { 3309e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3310e5ad96f3SKeith Busch if (ret < 0) 3311e5ad96f3SKeith Busch goto unfreeze; 3312e5ad96f3SKeith Busch } 3313e5ad96f3SKeith Busch 3314d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3315d916b1beSKeith Busch if (ret < 0) 3316d916b1beSKeith Busch goto unfreeze; 3317d916b1beSKeith Busch 33187cbb5c6fSMario Limonciello /* 33197cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 33207cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 33217cbb5c6fSMario Limonciello * want pci interfering. 33227cbb5c6fSMario Limonciello */ 33237cbb5c6fSMario Limonciello pci_save_state(pdev); 33247cbb5c6fSMario Limonciello 3325d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3326d916b1beSKeith Busch if (ret < 0) 3327d916b1beSKeith Busch goto unfreeze; 3328d916b1beSKeith Busch 3329d916b1beSKeith Busch if (ret) { 33307cbb5c6fSMario Limonciello /* discard the saved state */ 33317cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33327cbb5c6fSMario Limonciello 3333d916b1beSKeith Busch /* 3334d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 333505d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3336d916b1beSKeith Busch */ 3337c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3338d916b1beSKeith Busch ctrl->npss = 0; 3339d916b1beSKeith Busch } 3340d916b1beSKeith Busch unfreeze: 3341d916b1beSKeith Busch nvme_unfreeze(ctrl); 3342d916b1beSKeith Busch return ret; 3343d916b1beSKeith Busch } 3344d916b1beSKeith Busch 3345d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3346d916b1beSKeith Busch { 3347d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33484e523547SBaolin Wang 3349c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 335057dacad5SJay Sternberg } 335157dacad5SJay Sternberg 3352d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 335357dacad5SJay Sternberg { 335457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 335557dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 335657dacad5SJay Sternberg 3357c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 335857dacad5SJay Sternberg } 335957dacad5SJay Sternberg 336021774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3361d916b1beSKeith Busch .suspend = nvme_suspend, 3362d916b1beSKeith Busch .resume = nvme_resume, 3363d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3364d916b1beSKeith Busch .thaw = nvme_simple_resume, 3365d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3366d916b1beSKeith Busch .restore = nvme_simple_resume, 3367d916b1beSKeith Busch }; 3368d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 336957dacad5SJay Sternberg 3370a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3371a0a3408eSKeith Busch pci_channel_state_t state) 3372a0a3408eSKeith Busch { 3373a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3374a0a3408eSKeith Busch 3375a0a3408eSKeith Busch /* 3376a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3377a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3378a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3379a0a3408eSKeith Busch */ 3380a0a3408eSKeith Busch switch (state) { 3381a0a3408eSKeith Busch case pci_channel_io_normal: 3382a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3383a0a3408eSKeith Busch case pci_channel_io_frozen: 3384d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3385d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3386a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3387a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3388a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3389d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3390d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3391a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3392a0a3408eSKeith Busch } 3393a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3394a0a3408eSKeith Busch } 3395a0a3408eSKeith Busch 3396a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3397a0a3408eSKeith Busch { 3398a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3399a0a3408eSKeith Busch 34001b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3401a0a3408eSKeith Busch pci_restore_state(pdev); 3402d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3403a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3404a0a3408eSKeith Busch } 3405a0a3408eSKeith Busch 3406a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3407a0a3408eSKeith Busch { 340872cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 340972cd4cc2SKeith Busch 341072cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3411a0a3408eSKeith Busch } 3412a0a3408eSKeith Busch 341357dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 341457dacad5SJay Sternberg .error_detected = nvme_error_detected, 341557dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 341657dacad5SJay Sternberg .resume = nvme_error_resume, 3417775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3418775755edSChristoph Hellwig .reset_done = nvme_reset_done, 341957dacad5SJay Sternberg }; 342057dacad5SJay Sternberg 342157dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3422972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 342308095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3424e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3425972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 342699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3427e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3428972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 342999466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 343025e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 343125e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3432972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3433f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3434f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 343550af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34369abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34376c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3438ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3439ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34406299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34416299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3442540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34437b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 344466dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 344566dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 344666dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 344766dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34485bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3449c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3450c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 34510302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34525e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34535e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 345454adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 345554adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34568c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34578c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3458015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3459015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3460d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3461d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3462d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34637ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3464abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34657ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34662cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 34672cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3468c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 346973029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 347073029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 3471d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3472d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3473d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3474d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34756e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34766e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34776e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3478e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3479e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 348008b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 34811629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 34821629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3483f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3484f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3485f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 348641f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 348741f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 34885611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34895611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3490c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3491c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 349202ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 349302ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349489919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 349589919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349643047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 349743047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 349843047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 349943047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 350043047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 350143047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 350243047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 350343047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3504dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3505dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3506538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3507538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3508ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3509ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3510ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3511ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3512ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3513ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3514ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3515ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3516ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3517ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 351870ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 351970ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3520a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3521a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3522a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3523a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 35243765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 35253765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3526f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3527f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 3528d5d3c100SXi Ruoyao { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3529d5d3c100SXi Ruoyao .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 35306b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 35316b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3532d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3533d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 3534200dccd0SShyamin Ayesh { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3535200dccd0SShyamin Ayesh .driver_data = NVME_QUIRK_BOGUS_NID, }, 353680b26240SAbhijit { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 353780b26240SAbhijit .driver_data = NVME_QUIRK_BOGUS_NID, }, 35384bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 35394bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35404bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 35414bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35424bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 35434bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35444bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 35454bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35464bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 35474bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35484bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 35494bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 355098f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 355198f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3552124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 355366341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 355466341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3555d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3556a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3557a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 35580b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 355957dacad5SJay Sternberg { 0, } 356057dacad5SJay Sternberg }; 356157dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 356257dacad5SJay Sternberg 356357dacad5SJay Sternberg static struct pci_driver nvme_driver = { 356457dacad5SJay Sternberg .name = "nvme", 356557dacad5SJay Sternberg .id_table = nvme_id_table, 356657dacad5SJay Sternberg .probe = nvme_probe, 356757dacad5SJay Sternberg .remove = nvme_remove, 356857dacad5SJay Sternberg .shutdown = nvme_shutdown, 356957dacad5SJay Sternberg .driver = { 3570eac3ef26SChristoph Hellwig .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3571eac3ef26SChristoph Hellwig #ifdef CONFIG_PM_SLEEP 357257dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 3573d916b1beSKeith Busch #endif 3574eac3ef26SChristoph Hellwig }, 357574d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 357657dacad5SJay Sternberg .err_handler = &nvme_err_handler, 357757dacad5SJay Sternberg }; 357857dacad5SJay Sternberg 357957dacad5SJay Sternberg static int __init nvme_init(void) 358057dacad5SJay Sternberg { 358181101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 358281101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 358381101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3584612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3585c372cdd1SKeith Busch BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > 3586c372cdd1SKeith Busch S8_MAX); 358717c33167SKeith Busch 35889a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 358957dacad5SJay Sternberg } 359057dacad5SJay Sternberg 359157dacad5SJay Sternberg static void __exit nvme_exit(void) 359257dacad5SJay Sternberg { 359357dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 359403e0f3a6SMing Lei flush_workqueue(nvme_wq); 359557dacad5SJay Sternberg } 359657dacad5SJay Sternberg 359757dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 359857dacad5SJay Sternberg MODULE_LICENSE("GPL"); 359957dacad5SJay Sternberg MODULE_VERSION("1.0"); 360057dacad5SJay Sternberg module_init(nvme_init); 360157dacad5SJay Sternberg module_exit(nvme_exit); 3602