15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 2157dacad5SJay Sternberg #include <linux/t10-pi.h> 2257dacad5SJay Sternberg #include <linux/types.h> 239cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 24a98e58e5SScott Bauer #include <linux/sed-opal.h> 250f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2657dacad5SJay Sternberg 27604c01d5Syupeng #include "trace.h" 2857dacad5SJay Sternberg #include "nvme.h" 2957dacad5SJay Sternberg 3057dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3157dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3257dacad5SJay Sternberg 33a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 34adf68f21SChristoph Hellwig 35943e942eSJens Axboe /* 36943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 37943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 38943e942eSJens Axboe */ 39943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 40943e942eSJens Axboe #define NVME_MAX_SEGS 127 41943e942eSJens Axboe 4257dacad5SJay Sternberg static int use_threaded_interrupts; 4357dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4457dacad5SJay Sternberg 4557dacad5SJay Sternberg static bool use_cmb_sqes = true; 4669f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4757dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4857dacad5SJay Sternberg 4987ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5087ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5187ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5287ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5357dacad5SJay Sternberg 54a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 55a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 56a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 57a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 58a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 59a7a7cbe3SChaitanya Kulkarni 60b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 61b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 62b27c1e68Sweiping zhang .set = io_queue_depth_set, 63b27c1e68Sweiping zhang .get = param_get_int, 64b27c1e68Sweiping zhang }; 65b27c1e68Sweiping zhang 66b27c1e68Sweiping zhang static int io_queue_depth = 1024; 67b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 68b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 69b27c1e68Sweiping zhang 703b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 713b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 723b6592f7SJens Axboe .set = queue_count_set, 733b6592f7SJens Axboe .get = param_get_int, 743b6592f7SJens Axboe }; 753b6592f7SJens Axboe 763b6592f7SJens Axboe static int write_queues; 773b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 783b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 793b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 803b6592f7SJens Axboe "will share a queue set."); 813b6592f7SJens Axboe 82a4668d9bSJens Axboe static int poll_queues = 0; 834b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 844b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 854b04cc6aSJens Axboe 861c63dc66SChristoph Hellwig struct nvme_dev; 871c63dc66SChristoph Hellwig struct nvme_queue; 8857dacad5SJay Sternberg 89a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 9157dacad5SJay Sternberg 9257dacad5SJay Sternberg /* 931c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 941c63dc66SChristoph Hellwig */ 951c63dc66SChristoph Hellwig struct nvme_dev { 96147b27e4SSagi Grimberg struct nvme_queue *queues; 971c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 981c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 991c63dc66SChristoph Hellwig u32 __iomem *dbs; 1001c63dc66SChristoph Hellwig struct device *dev; 1011c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1021c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1031c63dc66SChristoph Hellwig unsigned online_queues; 1041c63dc66SChristoph Hellwig unsigned max_qid; 105e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10622b55601SKeith Busch unsigned int num_vecs; 1071c63dc66SChristoph Hellwig int q_depth; 1081c63dc66SChristoph Hellwig u32 db_stride; 1091c63dc66SChristoph Hellwig void __iomem *bar; 11097f6ef64SXu Yu unsigned long bar_mapped_size; 1115c8809e6SChristoph Hellwig struct work_struct remove_work; 11277bf25eaSKeith Busch struct mutex shutdown_lock; 1131c63dc66SChristoph Hellwig bool subsystem; 1141c63dc66SChristoph Hellwig u64 cmb_size; 1150f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1161c63dc66SChristoph Hellwig u32 cmbsz; 117202021c1SStephen Bates u32 cmbloc; 1181c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 11987ad72a5SChristoph Hellwig 120943e942eSJens Axboe mempool_t *iod_mempool; 121943e942eSJens Axboe 12287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 123f9f38e33SHelen Koike u32 *dbbuf_dbs; 124f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 125f9f38e33SHelen Koike u32 *dbbuf_eis; 126f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12787ad72a5SChristoph Hellwig 12887ad72a5SChristoph Hellwig /* host memory buffer support: */ 12987ad72a5SChristoph Hellwig u64 host_mem_size; 13087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1314033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13457dacad5SJay Sternberg }; 13557dacad5SJay Sternberg 136b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 137b27c1e68Sweiping zhang { 138b27c1e68Sweiping zhang int n = 0, ret; 139b27c1e68Sweiping zhang 140b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 141b27c1e68Sweiping zhang if (ret != 0 || n < 2) 142b27c1e68Sweiping zhang return -EINVAL; 143b27c1e68Sweiping zhang 144b27c1e68Sweiping zhang return param_set_int(val, kp); 145b27c1e68Sweiping zhang } 146b27c1e68Sweiping zhang 1473b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1483b6592f7SJens Axboe { 1493b6592f7SJens Axboe int n = 0, ret; 1503b6592f7SJens Axboe 1513b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 152e895fedfSBart Van Assche if (ret) 153e895fedfSBart Van Assche return ret; 1543b6592f7SJens Axboe if (n > num_possible_cpus()) 1553b6592f7SJens Axboe n = num_possible_cpus(); 1563b6592f7SJens Axboe 1573b6592f7SJens Axboe return param_set_int(val, kp); 1583b6592f7SJens Axboe } 1593b6592f7SJens Axboe 160f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 161f9f38e33SHelen Koike { 162f9f38e33SHelen Koike return qid * 2 * stride; 163f9f38e33SHelen Koike } 164f9f38e33SHelen Koike 165f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 166f9f38e33SHelen Koike { 167f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 168f9f38e33SHelen Koike } 169f9f38e33SHelen Koike 1701c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1711c63dc66SChristoph Hellwig { 1721c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1731c63dc66SChristoph Hellwig } 1741c63dc66SChristoph Hellwig 17557dacad5SJay Sternberg /* 17657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 17757dacad5SJay Sternberg * commands and one for I/O commands). 17857dacad5SJay Sternberg */ 17957dacad5SJay Sternberg struct nvme_queue { 18057dacad5SJay Sternberg struct nvme_dev *dev; 1811ab0cd69SJens Axboe spinlock_t sq_lock; 18257dacad5SJay Sternberg struct nvme_command *sq_cmds; 1833a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1843a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 18557dacad5SJay Sternberg volatile struct nvme_completion *cqes; 18657dacad5SJay Sternberg struct blk_mq_tags **tags; 18757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 18857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 18957dacad5SJay Sternberg u32 __iomem *q_db; 19057dacad5SJay Sternberg u16 q_depth; 1917c349ddeSKeith Busch u16 cq_vector; 19257dacad5SJay Sternberg u16 sq_tail; 19304f3eafdSJens Axboe u16 last_sq_tail; 19457dacad5SJay Sternberg u16 cq_head; 19568fa9dbeSJens Axboe u16 last_cq_head; 19657dacad5SJay Sternberg u16 qid; 19757dacad5SJay Sternberg u8 cq_phase; 1984e224106SChristoph Hellwig unsigned long flags; 1994e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 201d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2027c349ddeSKeith Busch #define NVMEQ_POLLED 3 203f9f38e33SHelen Koike u32 *dbbuf_sq_db; 204f9f38e33SHelen Koike u32 *dbbuf_cq_db; 205f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 206f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 207d1ed6aa1SChristoph Hellwig struct completion delete_done; 20857dacad5SJay Sternberg }; 20957dacad5SJay Sternberg 21057dacad5SJay Sternberg /* 2119b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2129b048119SChristoph Hellwig * 2139b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2149b048119SChristoph Hellwig * to the actual struct scatterlist. 21571bd150cSChristoph Hellwig */ 21671bd150cSChristoph Hellwig struct nvme_iod { 217d49187e9SChristoph Hellwig struct nvme_request req; 218f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 219a7a7cbe3SChaitanya Kulkarni bool use_sgl; 220f4800d6dSChristoph Hellwig int aborted; 22171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22371bd150cSChristoph Hellwig dma_addr_t first_dma; 224bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 225f4800d6dSChristoph Hellwig struct scatterlist *sg; 226f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 22757dacad5SJay Sternberg }; 22857dacad5SJay Sternberg 22957dacad5SJay Sternberg /* 23057dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23157dacad5SJay Sternberg */ 23257dacad5SJay Sternberg static inline void _nvme_check_size(void) 23357dacad5SJay Sternberg { 23457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 23557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 23657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 23757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 23857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2420add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2430add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 246f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 247f9f38e33SHelen Koike } 248f9f38e33SHelen Koike 2493b6592f7SJens Axboe static unsigned int max_io_queues(void) 2503b6592f7SJens Axboe { 2514b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2523b6592f7SJens Axboe } 2533b6592f7SJens Axboe 2543b6592f7SJens Axboe static unsigned int max_queue_count(void) 2553b6592f7SJens Axboe { 2563b6592f7SJens Axboe /* IO queues + admin queue */ 2573b6592f7SJens Axboe return 1 + max_io_queues(); 2583b6592f7SJens Axboe } 2593b6592f7SJens Axboe 260f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 261f9f38e33SHelen Koike { 2623b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 263f9f38e33SHelen Koike } 264f9f38e33SHelen Koike 265f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 266f9f38e33SHelen Koike { 267f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike if (dev->dbbuf_dbs) 270f9f38e33SHelen Koike return 0; 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 273f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 274f9f38e33SHelen Koike GFP_KERNEL); 275f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 276f9f38e33SHelen Koike return -ENOMEM; 277f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 279f9f38e33SHelen Koike GFP_KERNEL); 280f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 281f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 282f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 283f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 284f9f38e33SHelen Koike return -ENOMEM; 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike return 0; 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 291f9f38e33SHelen Koike { 292f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 293f9f38e33SHelen Koike 294f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 295f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 296f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 297f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 298f9f38e33SHelen Koike } 299f9f38e33SHelen Koike if (dev->dbbuf_eis) { 300f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 301f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 302f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike } 305f9f38e33SHelen Koike 306f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 307f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 308f9f38e33SHelen Koike { 309f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 310f9f38e33SHelen Koike return; 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 313f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 314f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 315f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 316f9f38e33SHelen Koike } 317f9f38e33SHelen Koike 318f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 319f9f38e33SHelen Koike { 320f9f38e33SHelen Koike struct nvme_command c; 321f9f38e33SHelen Koike 322f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 323f9f38e33SHelen Koike return; 324f9f38e33SHelen Koike 325f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 326f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 327f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 328f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3319bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 332f9f38e33SHelen Koike /* Free memory and continue on */ 333f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 334f9f38e33SHelen Koike } 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 338f9f38e33SHelen Koike { 339f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 343f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 344f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 345f9f38e33SHelen Koike { 346f9f38e33SHelen Koike if (dbbuf_db) { 347f9f38e33SHelen Koike u16 old_value; 348f9f38e33SHelen Koike 349f9f38e33SHelen Koike /* 350f9f38e33SHelen Koike * Ensure that the queue is written before updating 351f9f38e33SHelen Koike * the doorbell in memory 352f9f38e33SHelen Koike */ 353f9f38e33SHelen Koike wmb(); 354f9f38e33SHelen Koike 355f9f38e33SHelen Koike old_value = *dbbuf_db; 356f9f38e33SHelen Koike *dbbuf_db = value; 357f9f38e33SHelen Koike 358f1ed3df2SMichal Wnukowski /* 359f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 360f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 361f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 362f1ed3df2SMichal Wnukowski * the doorbell. 363f1ed3df2SMichal Wnukowski */ 364f1ed3df2SMichal Wnukowski mb(); 365f1ed3df2SMichal Wnukowski 366f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 367f9f38e33SHelen Koike return false; 368f9f38e33SHelen Koike } 369f9f38e33SHelen Koike 370f9f38e33SHelen Koike return true; 37157dacad5SJay Sternberg } 37257dacad5SJay Sternberg 37357dacad5SJay Sternberg /* 37457dacad5SJay Sternberg * Max size of iod being embedded in the request payload 37557dacad5SJay Sternberg */ 37657dacad5SJay Sternberg #define NVME_INT_PAGES 2 3775fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 37857dacad5SJay Sternberg 37957dacad5SJay Sternberg /* 38057dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38157dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38257dacad5SJay Sternberg * the I/O. 38357dacad5SJay Sternberg */ 38457dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 38557dacad5SJay Sternberg { 3865fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3875fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 38857dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38957dacad5SJay Sternberg } 39057dacad5SJay Sternberg 391a7a7cbe3SChaitanya Kulkarni /* 392a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 393a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 394a7a7cbe3SChaitanya Kulkarni */ 395a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 396f4800d6dSChristoph Hellwig { 397a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 398f4800d6dSChristoph Hellwig } 399f4800d6dSChristoph Hellwig 400a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 401a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 40257dacad5SJay Sternberg { 403a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 404a7a7cbe3SChaitanya Kulkarni 405a7a7cbe3SChaitanya Kulkarni if (use_sgl) 406a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 407a7a7cbe3SChaitanya Kulkarni else 408a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 409a7a7cbe3SChaitanya Kulkarni 410a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 411a7a7cbe3SChaitanya Kulkarni } 412a7a7cbe3SChaitanya Kulkarni 413a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 414a7a7cbe3SChaitanya Kulkarni { 415a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 416a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 417a7a7cbe3SChaitanya Kulkarni use_sgl); 418a7a7cbe3SChaitanya Kulkarni 419a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42057dacad5SJay Sternberg } 42157dacad5SJay Sternberg 42257dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 42357dacad5SJay Sternberg unsigned int hctx_idx) 42457dacad5SJay Sternberg { 42557dacad5SJay Sternberg struct nvme_dev *dev = data; 426147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 42757dacad5SJay Sternberg 42857dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 42957dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43057dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43157dacad5SJay Sternberg 43257dacad5SJay Sternberg hctx->driver_data = nvmeq; 43357dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 43457dacad5SJay Sternberg return 0; 43557dacad5SJay Sternberg } 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 43857dacad5SJay Sternberg { 43957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44057dacad5SJay Sternberg 44157dacad5SJay Sternberg nvmeq->tags = NULL; 44257dacad5SJay Sternberg } 44357dacad5SJay Sternberg 44457dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 44557dacad5SJay Sternberg unsigned int hctx_idx) 44657dacad5SJay Sternberg { 44757dacad5SJay Sternberg struct nvme_dev *dev = data; 448147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 44957dacad5SJay Sternberg 45057dacad5SJay Sternberg if (!nvmeq->tags) 45157dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 45257dacad5SJay Sternberg 45357dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 45457dacad5SJay Sternberg hctx->driver_data = nvmeq; 45557dacad5SJay Sternberg return 0; 45657dacad5SJay Sternberg } 45757dacad5SJay Sternberg 458d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 459d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46057dacad5SJay Sternberg { 461d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 462f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4630350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 464147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 46557dacad5SJay Sternberg 46657dacad5SJay Sternberg BUG_ON(!nvmeq); 467f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 46859e29ce6SSagi Grimberg 46959e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47057dacad5SJay Sternberg return 0; 47157dacad5SJay Sternberg } 47257dacad5SJay Sternberg 4733b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4743b6592f7SJens Axboe { 4753b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4763b6592f7SJens Axboe if (dev->num_vecs > 1) 4773b6592f7SJens Axboe return 1; 4783b6592f7SJens Axboe 4793b6592f7SJens Axboe return 0; 4803b6592f7SJens Axboe } 4813b6592f7SJens Axboe 482dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 483dca51e78SChristoph Hellwig { 484dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4853b6592f7SJens Axboe int i, qoff, offset; 486dca51e78SChristoph Hellwig 4873b6592f7SJens Axboe offset = queue_irq_offset(dev); 4883b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4893b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4903b6592f7SJens Axboe 4913b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4923b6592f7SJens Axboe if (!map->nr_queues) { 493e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4947e849dd9SChristoph Hellwig continue; 4953b6592f7SJens Axboe } 4963b6592f7SJens Axboe 4974b04cc6aSJens Axboe /* 4984b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4994b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5004b04cc6aSJens Axboe */ 5013b6592f7SJens Axboe map->queue_offset = qoff; 502e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 5033b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5044b04cc6aSJens Axboe else 5054b04cc6aSJens Axboe blk_mq_map_queues(map); 5063b6592f7SJens Axboe qoff += map->nr_queues; 5073b6592f7SJens Axboe offset += map->nr_queues; 5083b6592f7SJens Axboe } 5093b6592f7SJens Axboe 5103b6592f7SJens Axboe return 0; 511dca51e78SChristoph Hellwig } 512dca51e78SChristoph Hellwig 51304f3eafdSJens Axboe /* 51404f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 51504f3eafdSJens Axboe */ 51604f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 51704f3eafdSJens Axboe { 51804f3eafdSJens Axboe if (!write_sq) { 51904f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 52004f3eafdSJens Axboe 52104f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 52204f3eafdSJens Axboe next_tail = 0; 52304f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 52404f3eafdSJens Axboe return; 52504f3eafdSJens Axboe } 52604f3eafdSJens Axboe 52704f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 52804f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 52904f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 53004f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 53104f3eafdSJens Axboe } 53204f3eafdSJens Axboe 53357dacad5SJay Sternberg /** 53490ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 53557dacad5SJay Sternberg * @nvmeq: The queue to use 53657dacad5SJay Sternberg * @cmd: The command to send 53704f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 53857dacad5SJay Sternberg */ 53904f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 54004f3eafdSJens Axboe bool write_sq) 54157dacad5SJay Sternberg { 54290ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 54390ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 54490ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 54590ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 54604f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 54704f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 54804f3eafdSJens Axboe } 54904f3eafdSJens Axboe 55004f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 55104f3eafdSJens Axboe { 55204f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 55304f3eafdSJens Axboe 55404f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 55504f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 55604f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 55790ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 55857dacad5SJay Sternberg } 55957dacad5SJay Sternberg 560a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 56157dacad5SJay Sternberg { 562f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 563a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 56457dacad5SJay Sternberg } 56557dacad5SJay Sternberg 566955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 567955b1b5aSMinwoo Im { 568955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 56920469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 570955b1b5aSMinwoo Im unsigned int avg_seg_size; 571955b1b5aSMinwoo Im 57220469a37SKeith Busch if (nseg == 0) 57320469a37SKeith Busch return false; 57420469a37SKeith Busch 57520469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 576955b1b5aSMinwoo Im 577955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 578955b1b5aSMinwoo Im return false; 579955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 580955b1b5aSMinwoo Im return false; 581955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 582955b1b5aSMinwoo Im return false; 583955b1b5aSMinwoo Im return true; 584955b1b5aSMinwoo Im } 585955b1b5aSMinwoo Im 586f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 58757dacad5SJay Sternberg { 588f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 589a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 590a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 591a7a7cbe3SChaitanya Kulkarni 59257dacad5SJay Sternberg int i; 59357dacad5SJay Sternberg 59457dacad5SJay Sternberg if (iod->npages == 0) 595a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 596a7a7cbe3SChaitanya Kulkarni dma_addr); 597a7a7cbe3SChaitanya Kulkarni 59857dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 599a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 600a7a7cbe3SChaitanya Kulkarni 601a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 602a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 603a7a7cbe3SChaitanya Kulkarni 604a7a7cbe3SChaitanya Kulkarni next_dma_addr = 605a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 606a7a7cbe3SChaitanya Kulkarni } else { 607a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 608a7a7cbe3SChaitanya Kulkarni 609a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 610a7a7cbe3SChaitanya Kulkarni } 611a7a7cbe3SChaitanya Kulkarni 612a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 613a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 61457dacad5SJay Sternberg } 61557dacad5SJay Sternberg 616f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 617943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61857dacad5SJay Sternberg } 61957dacad5SJay Sternberg 620d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 621d0877473SKeith Busch { 622d0877473SKeith Busch int i; 623d0877473SKeith Busch struct scatterlist *sg; 624d0877473SKeith Busch 625d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 626d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 627d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 628d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 629d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 630d0877473SKeith Busch sg_dma_len(sg)); 631d0877473SKeith Busch } 632d0877473SKeith Busch } 633d0877473SKeith Busch 634a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 635a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 63657dacad5SJay Sternberg { 637f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63857dacad5SJay Sternberg struct dma_pool *pool; 639b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 64057dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 64157dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 64257dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6435fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 64457dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 64557dacad5SJay Sternberg __le64 *prp_list; 646a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 64757dacad5SJay Sternberg dma_addr_t prp_dma; 64857dacad5SJay Sternberg int nprps, i; 64957dacad5SJay Sternberg 65057dacad5SJay Sternberg length -= (page_size - offset); 6515228b328SJan H. Schönherr if (length <= 0) { 6525228b328SJan H. Schönherr iod->first_dma = 0; 653a7a7cbe3SChaitanya Kulkarni goto done; 6545228b328SJan H. Schönherr } 65557dacad5SJay Sternberg 65657dacad5SJay Sternberg dma_len -= (page_size - offset); 65757dacad5SJay Sternberg if (dma_len) { 65857dacad5SJay Sternberg dma_addr += (page_size - offset); 65957dacad5SJay Sternberg } else { 66057dacad5SJay Sternberg sg = sg_next(sg); 66157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 66257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 66357dacad5SJay Sternberg } 66457dacad5SJay Sternberg 66557dacad5SJay Sternberg if (length <= page_size) { 66657dacad5SJay Sternberg iod->first_dma = dma_addr; 667a7a7cbe3SChaitanya Kulkarni goto done; 66857dacad5SJay Sternberg } 66957dacad5SJay Sternberg 67057dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 67157dacad5SJay Sternberg if (nprps <= (256 / 8)) { 67257dacad5SJay Sternberg pool = dev->prp_small_pool; 67357dacad5SJay Sternberg iod->npages = 0; 67457dacad5SJay Sternberg } else { 67557dacad5SJay Sternberg pool = dev->prp_page_pool; 67657dacad5SJay Sternberg iod->npages = 1; 67757dacad5SJay Sternberg } 67857dacad5SJay Sternberg 67969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68057dacad5SJay Sternberg if (!prp_list) { 68157dacad5SJay Sternberg iod->first_dma = dma_addr; 68257dacad5SJay Sternberg iod->npages = -1; 68386eea289SKeith Busch return BLK_STS_RESOURCE; 68457dacad5SJay Sternberg } 68557dacad5SJay Sternberg list[0] = prp_list; 68657dacad5SJay Sternberg iod->first_dma = prp_dma; 68757dacad5SJay Sternberg i = 0; 68857dacad5SJay Sternberg for (;;) { 68957dacad5SJay Sternberg if (i == page_size >> 3) { 69057dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 69169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 69257dacad5SJay Sternberg if (!prp_list) 69386eea289SKeith Busch return BLK_STS_RESOURCE; 69457dacad5SJay Sternberg list[iod->npages++] = prp_list; 69557dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 69657dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 69757dacad5SJay Sternberg i = 1; 69857dacad5SJay Sternberg } 69957dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 70057dacad5SJay Sternberg dma_len -= page_size; 70157dacad5SJay Sternberg dma_addr += page_size; 70257dacad5SJay Sternberg length -= page_size; 70357dacad5SJay Sternberg if (length <= 0) 70457dacad5SJay Sternberg break; 70557dacad5SJay Sternberg if (dma_len > 0) 70657dacad5SJay Sternberg continue; 70786eea289SKeith Busch if (unlikely(dma_len < 0)) 70886eea289SKeith Busch goto bad_sgl; 70957dacad5SJay Sternberg sg = sg_next(sg); 71057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 71157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 71257dacad5SJay Sternberg } 71357dacad5SJay Sternberg 714a7a7cbe3SChaitanya Kulkarni done: 715a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 716a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 717a7a7cbe3SChaitanya Kulkarni 71886eea289SKeith Busch return BLK_STS_OK; 71986eea289SKeith Busch 72086eea289SKeith Busch bad_sgl: 721d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 722d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 723d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 72486eea289SKeith Busch return BLK_STS_IOERR; 72557dacad5SJay Sternberg } 72657dacad5SJay Sternberg 727a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 728a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 729a7a7cbe3SChaitanya Kulkarni { 730a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 731a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 732a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 733a7a7cbe3SChaitanya Kulkarni } 734a7a7cbe3SChaitanya Kulkarni 735a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 736a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 737a7a7cbe3SChaitanya Kulkarni { 738a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 739a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 740a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 741a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 742a7a7cbe3SChaitanya Kulkarni } else { 743a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 744a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 745a7a7cbe3SChaitanya Kulkarni } 746a7a7cbe3SChaitanya Kulkarni } 747a7a7cbe3SChaitanya Kulkarni 748a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 749b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 750a7a7cbe3SChaitanya Kulkarni { 751a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 752a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 753a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 754a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 755a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 756b0f2853bSChristoph Hellwig int i = 0; 757a7a7cbe3SChaitanya Kulkarni 758a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 759a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 760a7a7cbe3SChaitanya Kulkarni 761b0f2853bSChristoph Hellwig if (entries == 1) { 762a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 763a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 764a7a7cbe3SChaitanya Kulkarni } 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 767a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 768a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 769a7a7cbe3SChaitanya Kulkarni } else { 770a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 771a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 772a7a7cbe3SChaitanya Kulkarni } 773a7a7cbe3SChaitanya Kulkarni 774a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 775a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 776a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 777a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 778a7a7cbe3SChaitanya Kulkarni } 779a7a7cbe3SChaitanya Kulkarni 780a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 781a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 782a7a7cbe3SChaitanya Kulkarni 783a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 784a7a7cbe3SChaitanya Kulkarni 785a7a7cbe3SChaitanya Kulkarni do { 786a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 787a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 788a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 789a7a7cbe3SChaitanya Kulkarni 790a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 791a7a7cbe3SChaitanya Kulkarni if (!sg_list) 792a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 793a7a7cbe3SChaitanya Kulkarni 794a7a7cbe3SChaitanya Kulkarni i = 0; 795a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 796a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 797a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 798a7a7cbe3SChaitanya Kulkarni } 799a7a7cbe3SChaitanya Kulkarni 800a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 801a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 802b0f2853bSChristoph Hellwig } while (--entries > 0); 803a7a7cbe3SChaitanya Kulkarni 804a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 805a7a7cbe3SChaitanya Kulkarni } 806a7a7cbe3SChaitanya Kulkarni 807fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 808b131c61dSChristoph Hellwig struct nvme_command *cmnd) 80957dacad5SJay Sternberg { 810f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 811ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 812ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 813ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 814fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 815b0f2853bSChristoph Hellwig int nr_mapped; 81657dacad5SJay Sternberg 8179b048119SChristoph Hellwig if (blk_rq_payload_bytes(req) > NVME_INT_BYTES(dev) || 8189b048119SChristoph Hellwig blk_rq_nr_phys_segments(req) > NVME_INT_PAGES) { 8199b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8209b048119SChristoph Hellwig if (!iod->sg) 8219b048119SChristoph Hellwig return BLK_STS_RESOURCE; 8229b048119SChristoph Hellwig } else { 8239b048119SChristoph Hellwig iod->sg = iod->inline_sg; 8249b048119SChristoph Hellwig } 8259b048119SChristoph Hellwig 8269b048119SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 8279b048119SChristoph Hellwig 828f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 829ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 830ba1ca37eSChristoph Hellwig if (!iod->nents) 831ba1ca37eSChristoph Hellwig goto out; 832ba1ca37eSChristoph Hellwig 833fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 834e0596ab2SLogan Gunthorpe 835e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 836e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 837e0596ab2SLogan Gunthorpe dma_dir); 838e0596ab2SLogan Gunthorpe else 839e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 840e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 841b0f2853bSChristoph Hellwig if (!nr_mapped) 842ba1ca37eSChristoph Hellwig goto out; 843ba1ca37eSChristoph Hellwig 844955b1b5aSMinwoo Im if (iod->use_sgl) 845b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 846a7a7cbe3SChaitanya Kulkarni else 847a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 848a7a7cbe3SChaitanya Kulkarni 84986eea289SKeith Busch if (ret != BLK_STS_OK) 850ba1ca37eSChristoph Hellwig goto out_unmap; 851ba1ca37eSChristoph Hellwig 852fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 853ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 854ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 855ba1ca37eSChristoph Hellwig goto out_unmap; 856ba1ca37eSChristoph Hellwig 857bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 858bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 859ba1ca37eSChristoph Hellwig goto out_unmap; 860ba1ca37eSChristoph Hellwig 861bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 862ba1ca37eSChristoph Hellwig goto out_unmap; 8633045c0d0SChaitanya Kulkarni 8643045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 86557dacad5SJay Sternberg } 86657dacad5SJay Sternberg 867fc17b653SChristoph Hellwig return BLK_STS_OK; 868ba1ca37eSChristoph Hellwig 869ba1ca37eSChristoph Hellwig out_unmap: 870ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 871ba1ca37eSChristoph Hellwig out: 8729b048119SChristoph Hellwig nvme_free_iod(dev, req); 873ba1ca37eSChristoph Hellwig return ret; 87457dacad5SJay Sternberg } 87557dacad5SJay Sternberg 876f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 877d4f6c3abSChristoph Hellwig { 878f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 879d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 880d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 881d4f6c3abSChristoph Hellwig 882d4f6c3abSChristoph Hellwig if (iod->nents) { 883e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 884e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 885d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 886e0596ab2SLogan Gunthorpe 887f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 888bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 889d4f6c3abSChristoph Hellwig } 890d4f6c3abSChristoph Hellwig 891f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 892f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 89357dacad5SJay Sternberg } 89457dacad5SJay Sternberg 89557dacad5SJay Sternberg /* 89657dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 89757dacad5SJay Sternberg */ 898fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 89957dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 90057dacad5SJay Sternberg { 90157dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 90257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 90357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 90457dacad5SJay Sternberg struct request *req = bd->rq; 9059b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 906ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 907ebe6d874SChristoph Hellwig blk_status_t ret; 90857dacad5SJay Sternberg 9099b048119SChristoph Hellwig iod->aborted = 0; 9109b048119SChristoph Hellwig iod->npages = -1; 9119b048119SChristoph Hellwig iod->nents = 0; 9129b048119SChristoph Hellwig 913d1f06f4aSJens Axboe /* 914d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 915d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 916d1f06f4aSJens Axboe */ 9174e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 918d1f06f4aSJens Axboe return BLK_STS_IOERR; 919d1f06f4aSJens Axboe 920f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 921fc17b653SChristoph Hellwig if (ret) 922f4800d6dSChristoph Hellwig return ret; 92357dacad5SJay Sternberg 924fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 925b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 926fc17b653SChristoph Hellwig if (ret) 9279b048119SChristoph Hellwig goto out_free_cmd; 928fc17b653SChristoph Hellwig } 929ba1ca37eSChristoph Hellwig 930aae239e1SChristoph Hellwig blk_mq_start_request(req); 93104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 932fc17b653SChristoph Hellwig return BLK_STS_OK; 933f9d03f96SChristoph Hellwig out_free_cmd: 934f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 935ba1ca37eSChristoph Hellwig return ret; 93657dacad5SJay Sternberg } 93757dacad5SJay Sternberg 93877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 939eee417b0SChristoph Hellwig { 940f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 941eee417b0SChristoph Hellwig 94277f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 94377f02a7aSChristoph Hellwig nvme_complete_rq(req); 94457dacad5SJay Sternberg } 94557dacad5SJay Sternberg 946d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 947750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 948d783e0bdSMarta Rybczynska { 949750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 950750dde44SChristoph Hellwig nvmeq->cq_phase; 951d783e0bdSMarta Rybczynska } 952d783e0bdSMarta Rybczynska 953eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 95457dacad5SJay Sternberg { 955eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 95657dacad5SJay Sternberg 957eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 958eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 959eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 960eb281c82SSagi Grimberg } 961adf68f21SChristoph Hellwig 9625cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 96357dacad5SJay Sternberg { 9645cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 96557dacad5SJay Sternberg struct request *req; 966adf68f21SChristoph Hellwig 96783a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9681b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 969aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 97083a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 97183a12fb7SSagi Grimberg return; 972aae239e1SChristoph Hellwig } 973aae239e1SChristoph Hellwig 974adf68f21SChristoph Hellwig /* 975adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 976adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 977adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 978adf68f21SChristoph Hellwig * for them but rather special case them here. 979adf68f21SChristoph Hellwig */ 980adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 98138dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9827bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 98383a12fb7SSagi Grimberg cqe->status, &cqe->result); 984a0fa9647SJens Axboe return; 98557dacad5SJay Sternberg } 98657dacad5SJay Sternberg 98783a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 988604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 98983a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 99083a12fb7SSagi Grimberg } 99157dacad5SJay Sternberg 9925cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 99383a12fb7SSagi Grimberg { 9945cb525c8SJens Axboe while (start != end) { 9955cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 9965cb525c8SJens Axboe if (++start == nvmeq->q_depth) 9975cb525c8SJens Axboe start = 0; 9985cb525c8SJens Axboe } 9995cb525c8SJens Axboe } 100083a12fb7SSagi Grimberg 10015cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10025cb525c8SJens Axboe { 1003dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1004920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1005920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1006dcca1662SHongbo Yao } else { 1007dcca1662SHongbo Yao nvmeq->cq_head++; 1008920d13a8SSagi Grimberg } 1009a0fa9647SJens Axboe } 1010a0fa9647SJens Axboe 10111052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10121052b8acSJens Axboe u16 *end, unsigned int tag) 1013a0fa9647SJens Axboe { 10141052b8acSJens Axboe int found = 0; 101583a12fb7SSagi Grimberg 10165cb525c8SJens Axboe *start = nvmeq->cq_head; 10171052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10181052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10191052b8acSJens Axboe found++; 10205cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 102157dacad5SJay Sternberg } 10225cb525c8SJens Axboe *end = nvmeq->cq_head; 102357dacad5SJay Sternberg 10245cb525c8SJens Axboe if (*start != *end) 1025eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10265cb525c8SJens Axboe return found; 102757dacad5SJay Sternberg } 102857dacad5SJay Sternberg 102957dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 103057dacad5SJay Sternberg { 103157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 103268fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10335cb525c8SJens Axboe u16 start, end; 10345cb525c8SJens Axboe 10353a7afd8eSChristoph Hellwig /* 10363a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10373a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10383a7afd8eSChristoph Hellwig */ 10393a7afd8eSChristoph Hellwig rmb(); 104068fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 104168fa9dbeSJens Axboe ret = IRQ_HANDLED; 10425cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 104368fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10443a7afd8eSChristoph Hellwig wmb(); 10455cb525c8SJens Axboe 104668fa9dbeSJens Axboe if (start != end) { 10475cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10485cb525c8SJens Axboe return IRQ_HANDLED; 104957dacad5SJay Sternberg } 105057dacad5SJay Sternberg 105168fa9dbeSJens Axboe return ret; 105257dacad5SJay Sternberg } 105357dacad5SJay Sternberg 105457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 105557dacad5SJay Sternberg { 105657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1057750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 105857dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1059d783e0bdSMarta Rybczynska return IRQ_NONE; 106057dacad5SJay Sternberg } 106157dacad5SJay Sternberg 10620b2a8a9fSChristoph Hellwig /* 10630b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10640b2a8a9fSChristoph Hellwig * Can be called from any context. 10650b2a8a9fSChristoph Hellwig */ 10660b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1067a0fa9647SJens Axboe { 10683a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10695cb525c8SJens Axboe u16 start, end; 10701052b8acSJens Axboe int found; 1071a0fa9647SJens Axboe 10723a7afd8eSChristoph Hellwig /* 10733a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10743a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10753a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10763a7afd8eSChristoph Hellwig */ 10777c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10783a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 107991a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 108091a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 108191a509f8SChristoph Hellwig } else { 10823a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10835cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10843a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 108591a509f8SChristoph Hellwig } 1086442e19b7SSagi Grimberg 10875cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1088442e19b7SSagi Grimberg return found; 1089a0fa9647SJens Axboe } 1090a0fa9647SJens Axboe 10919743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 10927776db1cSKeith Busch { 10937776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1094dabcefabSJens Axboe u16 start, end; 1095dabcefabSJens Axboe bool found; 1096dabcefabSJens Axboe 1097dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1098dabcefabSJens Axboe return 0; 1099dabcefabSJens Axboe 11003a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11019743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11023a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1103dabcefabSJens Axboe 1104dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1105dabcefabSJens Axboe return found; 1106dabcefabSJens Axboe } 1107dabcefabSJens Axboe 1108ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 110957dacad5SJay Sternberg { 1110f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1111147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 111257dacad5SJay Sternberg struct nvme_command c; 111357dacad5SJay Sternberg 111457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1116ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 111704f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 111857dacad5SJay Sternberg } 111957dacad5SJay Sternberg 112057dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 112157dacad5SJay Sternberg { 112257dacad5SJay Sternberg struct nvme_command c; 112357dacad5SJay Sternberg 112457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112557dacad5SJay Sternberg c.delete_queue.opcode = opcode; 112657dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 112757dacad5SJay Sternberg 11281c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112957dacad5SJay Sternberg } 113057dacad5SJay Sternberg 113157dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1132a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 113357dacad5SJay Sternberg { 113457dacad5SJay Sternberg struct nvme_command c; 11354b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11364b04cc6aSJens Axboe 11377c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11384b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg /* 114116772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 114257dacad5SJay Sternberg * is attached to the request. 114357dacad5SJay Sternberg */ 114457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 114557dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 114657dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 114757dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 114857dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 114957dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1150a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 115157dacad5SJay Sternberg 11521c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115357dacad5SJay Sternberg } 115457dacad5SJay Sternberg 115557dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 115657dacad5SJay Sternberg struct nvme_queue *nvmeq) 115757dacad5SJay Sternberg { 11589abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 115957dacad5SJay Sternberg struct nvme_command c; 116081c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 116157dacad5SJay Sternberg 116257dacad5SJay Sternberg /* 11639abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11649abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11659abd68efSJens Axboe * URGENT. 11669abd68efSJens Axboe */ 11679abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11689abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11699abd68efSJens Axboe 11709abd68efSJens Axboe /* 117116772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117257dacad5SJay Sternberg * is attached to the request. 117357dacad5SJay Sternberg */ 117457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 117557dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 117657dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 117757dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 117857dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117957dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 118057dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 118157dacad5SJay Sternberg 11821c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 118357dacad5SJay Sternberg } 118457dacad5SJay Sternberg 118557dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 118657dacad5SJay Sternberg { 118757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 118857dacad5SJay Sternberg } 118957dacad5SJay Sternberg 119057dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 119157dacad5SJay Sternberg { 119257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 119357dacad5SJay Sternberg } 119457dacad5SJay Sternberg 11952a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 119657dacad5SJay Sternberg { 1197f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1198f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119957dacad5SJay Sternberg 120027fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 120127fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1202e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1203e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 120457dacad5SJay Sternberg } 120557dacad5SJay Sternberg 1206b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1207b2a0eb1aSKeith Busch { 1208b2a0eb1aSKeith Busch 1209b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1210b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1211b2a0eb1aSKeith Busch */ 1212b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1213b2a0eb1aSKeith Busch 1214ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1215ad70062cSJianchao Wang switch (dev->ctrl.state) { 1216ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1217ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1218b2a0eb1aSKeith Busch return false; 1219ad70062cSJianchao Wang default: 1220ad70062cSJianchao Wang break; 1221ad70062cSJianchao Wang } 1222b2a0eb1aSKeith Busch 1223b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1224b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1225b2a0eb1aSKeith Busch */ 1226b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1227b2a0eb1aSKeith Busch return false; 1228b2a0eb1aSKeith Busch 1229b2a0eb1aSKeith Busch return true; 1230b2a0eb1aSKeith Busch } 1231b2a0eb1aSKeith Busch 1232b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1233b2a0eb1aSKeith Busch { 1234b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1235b2a0eb1aSKeith Busch u16 pci_status; 1236b2a0eb1aSKeith Busch int result; 1237b2a0eb1aSKeith Busch 1238b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1239b2a0eb1aSKeith Busch &pci_status); 1240b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1241b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1242b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1243b2a0eb1aSKeith Busch csts, pci_status); 1244b2a0eb1aSKeith Busch else 1245b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1246b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1247b2a0eb1aSKeith Busch csts, result); 1248b2a0eb1aSKeith Busch } 1249b2a0eb1aSKeith Busch 125031c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 125157dacad5SJay Sternberg { 1252f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1253f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 125457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 125557dacad5SJay Sternberg struct request *abort_req; 125657dacad5SJay Sternberg struct nvme_command cmd; 1257b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1258b2a0eb1aSKeith Busch 1259651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1260651438bbSWen Xiong * the recovery mechanism will surely fail. 1261651438bbSWen Xiong */ 1262651438bbSWen Xiong mb(); 1263651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1264651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1265651438bbSWen Xiong 1266b2a0eb1aSKeith Busch /* 1267b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1268b2a0eb1aSKeith Busch */ 1269b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1270b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1271b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1272d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1273db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1274b2a0eb1aSKeith Busch } 127557dacad5SJay Sternberg 127631c7c7d2SChristoph Hellwig /* 12777776db1cSKeith Busch * Did we miss an interrupt? 12787776db1cSKeith Busch */ 12790b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12807776db1cSKeith Busch dev_warn(dev->ctrl.device, 12817776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12827776db1cSKeith Busch req->tag, nvmeq->qid); 1283db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12847776db1cSKeith Busch } 12857776db1cSKeith Busch 12867776db1cSKeith Busch /* 1287fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1288fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1289fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1290db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1291fd634f41SChristoph Hellwig */ 12924244140dSKeith Busch switch (dev->ctrl.state) { 12934244140dSKeith Busch case NVME_CTRL_CONNECTING: 12944244140dSKeith Busch case NVME_CTRL_RESETTING: 1295b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1296fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1297fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1298a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 129927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1300db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13014244140dSKeith Busch default: 13024244140dSKeith Busch break; 1303fd634f41SChristoph Hellwig } 1304fd634f41SChristoph Hellwig 1305fd634f41SChristoph Hellwig /* 1306e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1307e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1308e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 130931c7c7d2SChristoph Hellwig */ 1310f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13111b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 131257dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 131357dacad5SJay Sternberg req->tag, nvmeq->qid); 1314a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1315d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1316e1569a16SKeith Busch 131727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1318db8c48e4SChristoph Hellwig return BLK_EH_DONE; 131957dacad5SJay Sternberg } 132057dacad5SJay Sternberg 1321e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1322e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1323e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1324e7a2a87dSChristoph Hellwig } 13257bf7d778SKeith Busch iod->aborted = 1; 132657dacad5SJay Sternberg 132757dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 132857dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 132957dacad5SJay Sternberg cmd.abort.cid = req->tag; 133057dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 133157dacad5SJay Sternberg 13321b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13331b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 133457dacad5SJay Sternberg req->tag, nvmeq->qid); 1335e7a2a87dSChristoph Hellwig 1336e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1337eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13386bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13396bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 134031c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 134157dacad5SJay Sternberg } 134257dacad5SJay Sternberg 1343e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1344e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1345e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 134657dacad5SJay Sternberg 134757dacad5SJay Sternberg /* 134857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 134957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 135057dacad5SJay Sternberg * as the device then is in a faulty state. 135157dacad5SJay Sternberg */ 135257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 135357dacad5SJay Sternberg } 135457dacad5SJay Sternberg 135557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 135657dacad5SJay Sternberg { 135788a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 135857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 135963223078SChristoph Hellwig if (!nvmeq->sq_cmds) 136063223078SChristoph Hellwig return; 13610f238ff5SLogan Gunthorpe 136263223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 136388a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 136463223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 136563223078SChristoph Hellwig } else { 136688a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 136763223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13680f238ff5SLogan Gunthorpe } 136957dacad5SJay Sternberg } 137057dacad5SJay Sternberg 137157dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 137257dacad5SJay Sternberg { 137357dacad5SJay Sternberg int i; 137457dacad5SJay Sternberg 1375d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1376d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1377147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 137857dacad5SJay Sternberg } 137957dacad5SJay Sternberg } 138057dacad5SJay Sternberg 138157dacad5SJay Sternberg /** 138257dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 138340581d1aSBart Van Assche * @nvmeq: queue to suspend 138457dacad5SJay Sternberg */ 138557dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 138657dacad5SJay Sternberg { 13874e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 138857dacad5SJay Sternberg return 1; 138957dacad5SJay Sternberg 13904e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1391d1f06f4aSJens Axboe mb(); 139257dacad5SJay Sternberg 13934e224106SChristoph Hellwig nvmeq->dev->online_queues--; 13941c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1395c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 13967c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 13974e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 139857dacad5SJay Sternberg return 0; 139957dacad5SJay Sternberg } 140057dacad5SJay Sternberg 14018fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14028fae268bSKeith Busch { 14038fae268bSKeith Busch int i; 14048fae268bSKeith Busch 14058fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14068fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14078fae268bSKeith Busch } 14088fae268bSKeith Busch 1409a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 141057dacad5SJay Sternberg { 1411147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 141257dacad5SJay Sternberg 1413a5cdb68cSKeith Busch if (shutdown) 1414a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1415a5cdb68cSKeith Busch else 141620d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 141757dacad5SJay Sternberg 14180b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 141957dacad5SJay Sternberg } 142057dacad5SJay Sternberg 142157dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 142257dacad5SJay Sternberg int entry_size) 142357dacad5SJay Sternberg { 142457dacad5SJay Sternberg int q_depth = dev->q_depth; 14255fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14265fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 142757dacad5SJay Sternberg 142857dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 142957dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14305fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 143157dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 143257dacad5SJay Sternberg 143357dacad5SJay Sternberg /* 143457dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 143557dacad5SJay Sternberg * would be better to map queues in system memory with the 143657dacad5SJay Sternberg * original depth 143757dacad5SJay Sternberg */ 143857dacad5SJay Sternberg if (q_depth < 64) 143957dacad5SJay Sternberg return -ENOMEM; 144057dacad5SJay Sternberg } 144157dacad5SJay Sternberg 144257dacad5SJay Sternberg return q_depth; 144357dacad5SJay Sternberg } 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 144657dacad5SJay Sternberg int qid, int depth) 144757dacad5SJay Sternberg { 14480f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1449815c6704SKeith Busch 14500f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14510f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14520f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14530f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 145463223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 145563223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 145663223078SChristoph Hellwig return 0; 145763223078SChristoph Hellwig } 14580f238ff5SLogan Gunthorpe } 14590f238ff5SLogan Gunthorpe 146057dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 146157dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 146257dacad5SJay Sternberg if (!nvmeq->sq_cmds) 146357dacad5SJay Sternberg return -ENOMEM; 146457dacad5SJay Sternberg return 0; 146557dacad5SJay Sternberg } 146657dacad5SJay Sternberg 1467a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 146857dacad5SJay Sternberg { 1469147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 147057dacad5SJay Sternberg 147162314e40SKeith Busch if (dev->ctrl.queue_count > qid) 147262314e40SKeith Busch return 0; 147357dacad5SJay Sternberg 1474750afb08SLuis Chamberlain nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 147557dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 147657dacad5SJay Sternberg if (!nvmeq->cqes) 147757dacad5SJay Sternberg goto free_nvmeq; 147857dacad5SJay Sternberg 147957dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 148057dacad5SJay Sternberg goto free_cqdma; 148157dacad5SJay Sternberg 148257dacad5SJay Sternberg nvmeq->dev = dev; 14831ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14843a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 148557dacad5SJay Sternberg nvmeq->cq_head = 0; 148657dacad5SJay Sternberg nvmeq->cq_phase = 1; 148757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 148857dacad5SJay Sternberg nvmeq->q_depth = depth; 148957dacad5SJay Sternberg nvmeq->qid = qid; 1490d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 149157dacad5SJay Sternberg 1492147b27e4SSagi Grimberg return 0; 149357dacad5SJay Sternberg 149457dacad5SJay Sternberg free_cqdma: 149557dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 149657dacad5SJay Sternberg nvmeq->cq_dma_addr); 149757dacad5SJay Sternberg free_nvmeq: 1498147b27e4SSagi Grimberg return -ENOMEM; 149957dacad5SJay Sternberg } 150057dacad5SJay Sternberg 1501dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 150257dacad5SJay Sternberg { 15030ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15040ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15050ff199cbSChristoph Hellwig 15060ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15070ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15080ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15090ff199cbSChristoph Hellwig } else { 15100ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15110ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15120ff199cbSChristoph Hellwig } 151357dacad5SJay Sternberg } 151457dacad5SJay Sternberg 151557dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 151657dacad5SJay Sternberg { 151757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 151857dacad5SJay Sternberg 151957dacad5SJay Sternberg nvmeq->sq_tail = 0; 152004f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 152157dacad5SJay Sternberg nvmeq->cq_head = 0; 152257dacad5SJay Sternberg nvmeq->cq_phase = 1; 152357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 152457dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1525f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 152657dacad5SJay Sternberg dev->online_queues++; 15273a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 152857dacad5SJay Sternberg } 152957dacad5SJay Sternberg 15304b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 153157dacad5SJay Sternberg { 153257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153357dacad5SJay Sternberg int result; 15347c349ddeSKeith Busch u16 vector = 0; 153557dacad5SJay Sternberg 1536d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1537d1ed6aa1SChristoph Hellwig 153822b55601SKeith Busch /* 153922b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 154022b55601SKeith Busch * has only one vector available. 154122b55601SKeith Busch */ 15424b04cc6aSJens Axboe if (!polled) 1543a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15444b04cc6aSJens Axboe else 15457c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15464b04cc6aSJens Axboe 1547a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1548ded45505SKeith Busch if (result) 1549ded45505SKeith Busch return result; 155057dacad5SJay Sternberg 155157dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 155257dacad5SJay Sternberg if (result < 0) 1553ded45505SKeith Busch return result; 1554ded45505SKeith Busch else if (result) 155557dacad5SJay Sternberg goto release_cq; 155657dacad5SJay Sternberg 1557a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1558161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15594b04cc6aSJens Axboe 15607c349ddeSKeith Busch if (!polled) { 15617c349ddeSKeith Busch nvmeq->cq_vector = vector; 1562dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 156357dacad5SJay Sternberg if (result < 0) 156457dacad5SJay Sternberg goto release_sq; 15654b04cc6aSJens Axboe } 156657dacad5SJay Sternberg 15674e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 156857dacad5SJay Sternberg return result; 156957dacad5SJay Sternberg 157057dacad5SJay Sternberg release_sq: 1571f25a2dfcSJianchao Wang dev->online_queues--; 157257dacad5SJay Sternberg adapter_delete_sq(dev, qid); 157357dacad5SJay Sternberg release_cq: 157457dacad5SJay Sternberg adapter_delete_cq(dev, qid); 157557dacad5SJay Sternberg return result; 157657dacad5SJay Sternberg } 157757dacad5SJay Sternberg 1578f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 157957dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 158077f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 158157dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 158257dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15830350815aSChristoph Hellwig .init_request = nvme_init_request, 158457dacad5SJay Sternberg .timeout = nvme_timeout, 158557dacad5SJay Sternberg }; 158657dacad5SJay Sternberg 1587f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1588376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1589376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1590376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1591376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1592376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1593376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1594376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1595c6d962aeSChristoph Hellwig .poll = nvme_poll, 1596dabcefabSJens Axboe }; 1597dabcefabSJens Axboe 159857dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 159957dacad5SJay Sternberg { 16001c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 160169d9a99cSKeith Busch /* 160269d9a99cSKeith Busch * If the controller was reset during removal, it's possible 160369d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 160469d9a99cSKeith Busch * queue to flush these to completion. 160569d9a99cSKeith Busch */ 1606c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16071c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 160857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 160957dacad5SJay Sternberg } 161057dacad5SJay Sternberg } 161157dacad5SJay Sternberg 161257dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 161357dacad5SJay Sternberg { 16141c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 161557dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 161657dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1617e3e9d50cSKeith Busch 161838dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 161957dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 162057dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1621a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1622d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 162357dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 162457dacad5SJay Sternberg 162557dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 162657dacad5SJay Sternberg return -ENOMEM; 162734b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 162857dacad5SJay Sternberg 16291c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16301c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 163157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 163257dacad5SJay Sternberg return -ENOMEM; 163357dacad5SJay Sternberg } 16341c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 163557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16361c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 163757dacad5SJay Sternberg return -ENODEV; 163857dacad5SJay Sternberg } 163957dacad5SJay Sternberg } else 1640c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 164157dacad5SJay Sternberg 164257dacad5SJay Sternberg return 0; 164357dacad5SJay Sternberg } 164457dacad5SJay Sternberg 164597f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 164697f6ef64SXu Yu { 164797f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 164897f6ef64SXu Yu } 164997f6ef64SXu Yu 165097f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 165197f6ef64SXu Yu { 165297f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 165397f6ef64SXu Yu 165497f6ef64SXu Yu if (size <= dev->bar_mapped_size) 165597f6ef64SXu Yu return 0; 165697f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 165797f6ef64SXu Yu return -ENOMEM; 165897f6ef64SXu Yu if (dev->bar) 165997f6ef64SXu Yu iounmap(dev->bar); 166097f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 166197f6ef64SXu Yu if (!dev->bar) { 166297f6ef64SXu Yu dev->bar_mapped_size = 0; 166397f6ef64SXu Yu return -ENOMEM; 166497f6ef64SXu Yu } 166597f6ef64SXu Yu dev->bar_mapped_size = size; 166697f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 166797f6ef64SXu Yu 166897f6ef64SXu Yu return 0; 166997f6ef64SXu Yu } 167097f6ef64SXu Yu 167101ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 167257dacad5SJay Sternberg { 167357dacad5SJay Sternberg int result; 167457dacad5SJay Sternberg u32 aqa; 167557dacad5SJay Sternberg struct nvme_queue *nvmeq; 167657dacad5SJay Sternberg 167797f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 167897f6ef64SXu Yu if (result < 0) 167997f6ef64SXu Yu return result; 168097f6ef64SXu Yu 16818ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 168220d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 168357dacad5SJay Sternberg 16847a67cbeaSChristoph Hellwig if (dev->subsystem && 16857a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16867a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 168757dacad5SJay Sternberg 168820d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 168957dacad5SJay Sternberg if (result < 0) 169057dacad5SJay Sternberg return result; 169157dacad5SJay Sternberg 1692a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1693147b27e4SSagi Grimberg if (result) 1694147b27e4SSagi Grimberg return result; 169557dacad5SJay Sternberg 1696147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 169757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 169857dacad5SJay Sternberg aqa |= aqa << 16; 169957dacad5SJay Sternberg 17007a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17017a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17027a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 170357dacad5SJay Sternberg 170420d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 170557dacad5SJay Sternberg if (result) 1706d4875622SKeith Busch return result; 170757dacad5SJay Sternberg 170857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1709161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1710dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 171157dacad5SJay Sternberg if (result) { 17127c349ddeSKeith Busch dev->online_queues--; 1713d4875622SKeith Busch return result; 171457dacad5SJay Sternberg } 171557dacad5SJay Sternberg 17164e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 171757dacad5SJay Sternberg return result; 171857dacad5SJay Sternberg } 171957dacad5SJay Sternberg 1720749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 172157dacad5SJay Sternberg { 17224b04cc6aSJens Axboe unsigned i, max, rw_queues; 1723749941f2SChristoph Hellwig int ret = 0; 172457dacad5SJay Sternberg 1725d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1726a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1727749941f2SChristoph Hellwig ret = -ENOMEM; 172857dacad5SJay Sternberg break; 1729749941f2SChristoph Hellwig } 1730749941f2SChristoph Hellwig } 173157dacad5SJay Sternberg 1732d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1733e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1734e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1735e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17364b04cc6aSJens Axboe } else { 17374b04cc6aSJens Axboe rw_queues = max; 17384b04cc6aSJens Axboe } 17394b04cc6aSJens Axboe 1740949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17414b04cc6aSJens Axboe bool polled = i > rw_queues; 17424b04cc6aSJens Axboe 17434b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1744d4875622SKeith Busch if (ret) 174557dacad5SJay Sternberg break; 174657dacad5SJay Sternberg } 174757dacad5SJay Sternberg 1748749941f2SChristoph Hellwig /* 1749749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17508adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17518adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1752749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1753749941f2SChristoph Hellwig */ 1754749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 175557dacad5SJay Sternberg } 175657dacad5SJay Sternberg 1757202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1758202021c1SStephen Bates struct device_attribute *attr, 1759202021c1SStephen Bates char *buf) 1760202021c1SStephen Bates { 1761202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1762202021c1SStephen Bates 1763c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1764202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1765202021c1SStephen Bates } 1766202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1767202021c1SStephen Bates 176888de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 176957dacad5SJay Sternberg { 177088de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 177188de4598SChristoph Hellwig 177288de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 177388de4598SChristoph Hellwig } 177488de4598SChristoph Hellwig 177588de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 177688de4598SChristoph Hellwig { 177788de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 177888de4598SChristoph Hellwig } 177988de4598SChristoph Hellwig 1780f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 178157dacad5SJay Sternberg { 178288de4598SChristoph Hellwig u64 size, offset; 178357dacad5SJay Sternberg resource_size_t bar_size; 178457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17858969f1f8SChristoph Hellwig int bar; 178657dacad5SJay Sternberg 17879fe5c59fSKeith Busch if (dev->cmb_size) 17889fe5c59fSKeith Busch return; 17899fe5c59fSKeith Busch 17907a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1791f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1792f65efd6dSChristoph Hellwig return; 1793202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 179457dacad5SJay Sternberg 179588de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 179688de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17978969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17988969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 179957dacad5SJay Sternberg 180057dacad5SJay Sternberg if (offset > bar_size) 1801f65efd6dSChristoph Hellwig return; 180257dacad5SJay Sternberg 180357dacad5SJay Sternberg /* 180457dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 180557dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 180657dacad5SJay Sternberg * the reported size of the BAR 180757dacad5SJay Sternberg */ 180857dacad5SJay Sternberg if (size > bar_size - offset) 180957dacad5SJay Sternberg size = bar_size - offset; 181057dacad5SJay Sternberg 18110f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18120f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18130f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1814f65efd6dSChristoph Hellwig return; 18150f238ff5SLogan Gunthorpe } 18160f238ff5SLogan Gunthorpe 181757dacad5SJay Sternberg dev->cmb_size = size; 18180f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18190f238ff5SLogan Gunthorpe 18200f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18210f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18220f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1823f65efd6dSChristoph Hellwig 1824f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1825f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1826f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1827f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 182857dacad5SJay Sternberg } 182957dacad5SJay Sternberg 183057dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 183157dacad5SJay Sternberg { 18320f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1833f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1834f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18350f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1836f63572dfSJon Derrick } 183757dacad5SJay Sternberg } 183857dacad5SJay Sternberg 183987ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 184057dacad5SJay Sternberg { 18414033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 184287ad72a5SChristoph Hellwig struct nvme_command c; 184387ad72a5SChristoph Hellwig int ret; 184487ad72a5SChristoph Hellwig 184587ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 184687ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 184787ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 184887ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 184987ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 185087ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 185187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 185287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 185387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 185487ad72a5SChristoph Hellwig 185587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 185687ad72a5SChristoph Hellwig if (ret) { 185787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 185887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 185987ad72a5SChristoph Hellwig ret, bits); 186087ad72a5SChristoph Hellwig } 186187ad72a5SChristoph Hellwig return ret; 186287ad72a5SChristoph Hellwig } 186387ad72a5SChristoph Hellwig 186487ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 186587ad72a5SChristoph Hellwig { 186687ad72a5SChristoph Hellwig int i; 186787ad72a5SChristoph Hellwig 186887ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 186987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 187087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 187187ad72a5SChristoph Hellwig 1872cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1873cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1874cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 187587ad72a5SChristoph Hellwig } 187687ad72a5SChristoph Hellwig 187787ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 187887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18794033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18804033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18814033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 188287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18837e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 188487ad72a5SChristoph Hellwig } 188587ad72a5SChristoph Hellwig 188692dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 188792dc6895SChristoph Hellwig u32 chunk_size) 188887ad72a5SChristoph Hellwig { 188987ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 189092dc6895SChristoph Hellwig u32 max_entries, len; 18914033f35dSChristoph Hellwig dma_addr_t descs_dma; 18922ee0e4edSDan Carpenter int i = 0; 189387ad72a5SChristoph Hellwig void **bufs; 18946fbcde66SMinwoo Im u64 size, tmp; 189587ad72a5SChristoph Hellwig 189687ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 189787ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 189887ad72a5SChristoph Hellwig max_entries = tmp; 1899044a9df1SChristoph Hellwig 1900044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1901044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1902044a9df1SChristoph Hellwig 1903750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19044033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 190587ad72a5SChristoph Hellwig if (!descs) 190687ad72a5SChristoph Hellwig goto out; 190787ad72a5SChristoph Hellwig 190887ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 190987ad72a5SChristoph Hellwig if (!bufs) 191087ad72a5SChristoph Hellwig goto out_free_descs; 191187ad72a5SChristoph Hellwig 1912244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 191387ad72a5SChristoph Hellwig dma_addr_t dma_addr; 191487ad72a5SChristoph Hellwig 191550cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 191687ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 191787ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191887ad72a5SChristoph Hellwig if (!bufs[i]) 191987ad72a5SChristoph Hellwig break; 192087ad72a5SChristoph Hellwig 192187ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 192287ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 192387ad72a5SChristoph Hellwig i++; 192487ad72a5SChristoph Hellwig } 192587ad72a5SChristoph Hellwig 192692dc6895SChristoph Hellwig if (!size) 192787ad72a5SChristoph Hellwig goto out_free_bufs; 192887ad72a5SChristoph Hellwig 192987ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 193087ad72a5SChristoph Hellwig dev->host_mem_size = size; 193187ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19324033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 193387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 193487ad72a5SChristoph Hellwig return 0; 193587ad72a5SChristoph Hellwig 193687ad72a5SChristoph Hellwig out_free_bufs: 193787ad72a5SChristoph Hellwig while (--i >= 0) { 193887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 193987ad72a5SChristoph Hellwig 1940cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1941cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1942cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 194387ad72a5SChristoph Hellwig } 194487ad72a5SChristoph Hellwig 194587ad72a5SChristoph Hellwig kfree(bufs); 194687ad72a5SChristoph Hellwig out_free_descs: 19474033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19484033f35dSChristoph Hellwig descs_dma); 194987ad72a5SChristoph Hellwig out: 195087ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 195187ad72a5SChristoph Hellwig return -ENOMEM; 195287ad72a5SChristoph Hellwig } 195387ad72a5SChristoph Hellwig 195492dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 195592dc6895SChristoph Hellwig { 195692dc6895SChristoph Hellwig u32 chunk_size; 195792dc6895SChristoph Hellwig 195892dc6895SChristoph Hellwig /* start big and work our way down */ 195930f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1960044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 196192dc6895SChristoph Hellwig chunk_size /= 2) { 196292dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 196392dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 196492dc6895SChristoph Hellwig return 0; 196592dc6895SChristoph Hellwig nvme_free_host_mem(dev); 196692dc6895SChristoph Hellwig } 196792dc6895SChristoph Hellwig } 196892dc6895SChristoph Hellwig 196992dc6895SChristoph Hellwig return -ENOMEM; 197092dc6895SChristoph Hellwig } 197192dc6895SChristoph Hellwig 19729620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 197387ad72a5SChristoph Hellwig { 197487ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 197587ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 197687ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 197787ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19786fbcde66SMinwoo Im int ret; 197987ad72a5SChristoph Hellwig 198087ad72a5SChristoph Hellwig preferred = min(preferred, max); 198187ad72a5SChristoph Hellwig if (min > max) { 198287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 198387ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 198487ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 198587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19869620cfbaSChristoph Hellwig return 0; 198787ad72a5SChristoph Hellwig } 198887ad72a5SChristoph Hellwig 198987ad72a5SChristoph Hellwig /* 199087ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 199187ad72a5SChristoph Hellwig */ 199287ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 199387ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 199487ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 199587ad72a5SChristoph Hellwig else 199687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 199787ad72a5SChristoph Hellwig } 199887ad72a5SChristoph Hellwig 199987ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 200092dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 200192dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 200292dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20039620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 200487ad72a5SChristoph Hellwig } 200587ad72a5SChristoph Hellwig 200692dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 200792dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 200892dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 200992dc6895SChristoph Hellwig } 201092dc6895SChristoph Hellwig 20119620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20129620cfbaSChristoph Hellwig if (ret) 201387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20149620cfbaSChristoph Hellwig return ret; 201557dacad5SJay Sternberg } 201657dacad5SJay Sternberg 2017612b7286SMing Lei /* 2018612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2019612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2020612b7286SMing Lei */ 2021612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20223b6592f7SJens Axboe { 2023612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2024612b7286SMing Lei unsigned int nr_read_queues; 2025c45b1fa2SMing Lei 20263b6592f7SJens Axboe /* 2027612b7286SMing Lei * If there is no interupt available for queues, ensure that 2028612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2029612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2030612b7286SMing Lei * 2031612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2032612b7286SMing Lei * write and read queues. 2033612b7286SMing Lei * 2034612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2035612b7286SMing Lei * queue. 20363b6592f7SJens Axboe */ 2037612b7286SMing Lei if (!nrirqs) { 2038612b7286SMing Lei nrirqs = 1; 2039612b7286SMing Lei nr_read_queues = 0; 2040612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2041612b7286SMing Lei nr_read_queues = 0; 2042612b7286SMing Lei } else if (write_queues >= nrirqs) { 2043612b7286SMing Lei nr_read_queues = 1; 20443b6592f7SJens Axboe } else { 2045612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20463b6592f7SJens Axboe } 2047612b7286SMing Lei 2048612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2049612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2050612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2051612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2052612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20533b6592f7SJens Axboe } 20543b6592f7SJens Axboe 20556451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20563b6592f7SJens Axboe { 20573b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20583b6592f7SJens Axboe struct irq_affinity affd = { 20593b6592f7SJens Axboe .pre_vectors = 1, 2060612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2061612b7286SMing Lei .priv = dev, 20623b6592f7SJens Axboe }; 20636451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20646451fe73SJens Axboe 20656451fe73SJens Axboe /* 20666451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20676451fe73SJens Axboe * queue left over for non-polled IO. 20686451fe73SJens Axboe */ 20696451fe73SJens Axboe this_p_queues = poll_queues; 20706451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20716451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20726451fe73SJens Axboe irq_queues = 1; 20736451fe73SJens Axboe } else { 2074c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20756451fe73SJens Axboe } 20766451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20773b6592f7SJens Axboe 2078612b7286SMing Lei /* Initialize for the single interrupt case */ 2079612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2080612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20813b6592f7SJens Axboe 2082612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20833b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20843b6592f7SJens Axboe } 20853b6592f7SJens Axboe 20868fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 20878fae268bSKeith Busch { 20888fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 20898fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 20908fae268bSKeith Busch } 20918fae268bSKeith Busch 209257dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 209357dacad5SJay Sternberg { 2094147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 209557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 209697f6ef64SXu Yu int result, nr_io_queues; 209797f6ef64SXu Yu unsigned long size; 209857dacad5SJay Sternberg 20993b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21009a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21019a0be7abSChristoph Hellwig if (result < 0) 210257dacad5SJay Sternberg return result; 21039a0be7abSChristoph Hellwig 2104f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2105a5229050SKeith Busch return 0; 210657dacad5SJay Sternberg 21074e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21084e224106SChristoph Hellwig 21090f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 211057dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 211157dacad5SJay Sternberg sizeof(struct nvme_command)); 211257dacad5SJay Sternberg if (result > 0) 211357dacad5SJay Sternberg dev->q_depth = result; 211457dacad5SJay Sternberg else 21150f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 211657dacad5SJay Sternberg } 211757dacad5SJay Sternberg 211857dacad5SJay Sternberg do { 211997f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 212097f6ef64SXu Yu result = nvme_remap_bar(dev, size); 212197f6ef64SXu Yu if (!result) 212257dacad5SJay Sternberg break; 212357dacad5SJay Sternberg if (!--nr_io_queues) 212457dacad5SJay Sternberg return -ENOMEM; 212557dacad5SJay Sternberg } while (1); 212657dacad5SJay Sternberg adminq->q_db = dev->dbs; 212757dacad5SJay Sternberg 21288fae268bSKeith Busch retry: 212957dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21300ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 213157dacad5SJay Sternberg 213257dacad5SJay Sternberg /* 213357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 213457dacad5SJay Sternberg * setting up the full range we need. 213557dacad5SJay Sternberg */ 2136dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21373b6592f7SJens Axboe 21383b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 213922b55601SKeith Busch if (result <= 0) 2140dca51e78SChristoph Hellwig return -EIO; 21413b6592f7SJens Axboe 214222b55601SKeith Busch dev->num_vecs = result; 21434b04cc6aSJens Axboe result = max(result - 1, 1); 2144e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 214557dacad5SJay Sternberg 214657dacad5SJay Sternberg /* 214757dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 214857dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 214957dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 215057dacad5SJay Sternberg * number of interrupts. 215157dacad5SJay Sternberg */ 2152dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21537c349ddeSKeith Busch if (result) 2154d4875622SKeith Busch return result; 21554e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21568fae268bSKeith Busch 21578fae268bSKeith Busch result = nvme_create_io_queues(dev); 21588fae268bSKeith Busch if (result || dev->online_queues < 2) 21598fae268bSKeith Busch return result; 21608fae268bSKeith Busch 21618fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21628fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21638fae268bSKeith Busch nvme_disable_io_queues(dev); 21648fae268bSKeith Busch nvme_suspend_io_queues(dev); 21658fae268bSKeith Busch goto retry; 21668fae268bSKeith Busch } 21678fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21688fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21698fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21708fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21718fae268bSKeith Busch return 0; 217257dacad5SJay Sternberg } 217357dacad5SJay Sternberg 21742a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2175db3cbfffSKeith Busch { 2176db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2177db3cbfffSKeith Busch 2178db3cbfffSKeith Busch blk_mq_free_request(req); 2179d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2180db3cbfffSKeith Busch } 2181db3cbfffSKeith Busch 21822a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2183db3cbfffSKeith Busch { 2184db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2185db3cbfffSKeith Busch 2186d1ed6aa1SChristoph Hellwig if (error) 2187d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2188db3cbfffSKeith Busch 2189db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2190db3cbfffSKeith Busch } 2191db3cbfffSKeith Busch 2192db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2193db3cbfffSKeith Busch { 2194db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2195db3cbfffSKeith Busch struct request *req; 2196db3cbfffSKeith Busch struct nvme_command cmd; 2197db3cbfffSKeith Busch 2198db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2199db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2200db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2201db3cbfffSKeith Busch 2202eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2203db3cbfffSKeith Busch if (IS_ERR(req)) 2204db3cbfffSKeith Busch return PTR_ERR(req); 2205db3cbfffSKeith Busch 2206db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2207db3cbfffSKeith Busch req->end_io_data = nvmeq; 2208db3cbfffSKeith Busch 2209d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2210db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2211db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2212db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2213db3cbfffSKeith Busch return 0; 2214db3cbfffSKeith Busch } 2215db3cbfffSKeith Busch 22168fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2217db3cbfffSKeith Busch { 22185271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2219db3cbfffSKeith Busch unsigned long timeout; 2220db3cbfffSKeith Busch 2221db3cbfffSKeith Busch retry: 2222db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22235271edd4SChristoph Hellwig while (nr_queues > 0) { 22245271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2225db3cbfffSKeith Busch break; 22265271edd4SChristoph Hellwig nr_queues--; 22275271edd4SChristoph Hellwig sent++; 22285271edd4SChristoph Hellwig } 2229d1ed6aa1SChristoph Hellwig while (sent) { 2230d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2231d1ed6aa1SChristoph Hellwig 2232d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22335271edd4SChristoph Hellwig timeout); 2234db3cbfffSKeith Busch if (timeout == 0) 22355271edd4SChristoph Hellwig return false; 2236d1ed6aa1SChristoph Hellwig 2237d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2238d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2239d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2240d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2241d1ed6aa1SChristoph Hellwig 2242d1ed6aa1SChristoph Hellwig sent--; 22435271edd4SChristoph Hellwig if (nr_queues) 2244db3cbfffSKeith Busch goto retry; 2245db3cbfffSKeith Busch } 22465271edd4SChristoph Hellwig return true; 2247db3cbfffSKeith Busch } 2248db3cbfffSKeith Busch 224957dacad5SJay Sternberg /* 22502b1b7e78SJianchao Wang * return error value only when tagset allocation failed 225157dacad5SJay Sternberg */ 225257dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 225357dacad5SJay Sternberg { 22542b1b7e78SJianchao Wang int ret; 22552b1b7e78SJianchao Wang 22565bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2257c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 225857dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2259ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2260ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2261ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 226257dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 226357dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 226457dacad5SJay Sternberg dev->tagset.queue_depth = 226557dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2266a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2267a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2268a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2269a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2270a7a7cbe3SChaitanya Kulkarni } 227157dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 227257dacad5SJay Sternberg dev->tagset.driver_data = dev; 227357dacad5SJay Sternberg 22742b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22752b1b7e78SJianchao Wang if (ret) { 22762b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22772b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22782b1b7e78SJianchao Wang return ret; 22792b1b7e78SJianchao Wang } 22805bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2281f9f38e33SHelen Koike 2282f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2283949928c1SKeith Busch } else { 2284949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2285949928c1SKeith Busch 2286949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2287949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 228857dacad5SJay Sternberg } 2289949928c1SKeith Busch 229057dacad5SJay Sternberg return 0; 229157dacad5SJay Sternberg } 229257dacad5SJay Sternberg 2293b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 229457dacad5SJay Sternberg { 2295b00a726aSKeith Busch int result = -ENOMEM; 229657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 229757dacad5SJay Sternberg 229857dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 229957dacad5SJay Sternberg return result; 230057dacad5SJay Sternberg 230157dacad5SJay Sternberg pci_set_master(pdev); 230257dacad5SJay Sternberg 230357dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 230457dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 230557dacad5SJay Sternberg goto disable; 230657dacad5SJay Sternberg 23077a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 230857dacad5SJay Sternberg result = -ENODEV; 2309b00a726aSKeith Busch goto disable; 231057dacad5SJay Sternberg } 231157dacad5SJay Sternberg 231257dacad5SJay Sternberg /* 2313a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2314a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2315a5229050SKeith Busch * adjust this later. 231657dacad5SJay Sternberg */ 2317dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2318dca51e78SChristoph Hellwig if (result < 0) 2319dca51e78SChristoph Hellwig return result; 232057dacad5SJay Sternberg 232120d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23227a67cbeaSChristoph Hellwig 232320d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2324b27c1e68Sweiping zhang io_queue_depth); 232520d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23267a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23271f390c1fSStephan Günther 23281f390c1fSStephan Günther /* 23291f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23301f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23311f390c1fSStephan Günther */ 23321f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23331f390c1fSStephan Günther dev->q_depth = 2; 23349bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23359bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23361f390c1fSStephan Günther dev->q_depth); 2337d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2338d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 233920d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2340d554b5e1SMartin K. Petersen dev->q_depth = 64; 2341d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2342d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23431f390c1fSStephan Günther } 23441f390c1fSStephan Günther 2345f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2346202021c1SStephen Bates 2347a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2348a0a3408eSKeith Busch pci_save_state(pdev); 234957dacad5SJay Sternberg return 0; 235057dacad5SJay Sternberg 235157dacad5SJay Sternberg disable: 235257dacad5SJay Sternberg pci_disable_device(pdev); 235357dacad5SJay Sternberg return result; 235457dacad5SJay Sternberg } 235557dacad5SJay Sternberg 235657dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 235757dacad5SJay Sternberg { 2358b00a726aSKeith Busch if (dev->bar) 2359b00a726aSKeith Busch iounmap(dev->bar); 2360a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2361b00a726aSKeith Busch } 2362b00a726aSKeith Busch 2363b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2364b00a726aSKeith Busch { 236557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 236657dacad5SJay Sternberg 2367dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 236857dacad5SJay Sternberg 2369a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2370a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 237157dacad5SJay Sternberg pci_disable_device(pdev); 237257dacad5SJay Sternberg } 2373a0a3408eSKeith Busch } 237457dacad5SJay Sternberg 2375a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 237657dacad5SJay Sternberg { 2377302ad8ccSKeith Busch bool dead = true; 2378302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 237957dacad5SJay Sternberg 238077bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2381302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2382302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2383302ad8ccSKeith Busch 2384ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2385ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2386302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2387302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2388302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 238957dacad5SJay Sternberg } 2390c21377f8SGabriel Krisman Bertazi 2391302ad8ccSKeith Busch /* 2392302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2393302ad8ccSKeith Busch * doing a safe shutdown. 2394302ad8ccSKeith Busch */ 239587ad72a5SChristoph Hellwig if (!dead) { 239687ad72a5SChristoph Hellwig if (shutdown) 2397302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 23989a915a5bSJianchao Wang } 239987ad72a5SChristoph Hellwig 24009a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24019a915a5bSJianchao Wang 240264ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24038fae268bSKeith Busch nvme_disable_io_queues(dev); 2404a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 240557dacad5SJay Sternberg } 24068fae268bSKeith Busch nvme_suspend_io_queues(dev); 24078fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2408b00a726aSKeith Busch nvme_pci_disable(dev); 240957dacad5SJay Sternberg 2410e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2411e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2412302ad8ccSKeith Busch 2413302ad8ccSKeith Busch /* 2414302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2415302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2416302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2417302ad8ccSKeith Busch */ 2418302ad8ccSKeith Busch if (shutdown) 2419302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 242077bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 242157dacad5SJay Sternberg } 242257dacad5SJay Sternberg 242357dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 242457dacad5SJay Sternberg { 242557dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 242657dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 242757dacad5SJay Sternberg if (!dev->prp_page_pool) 242857dacad5SJay Sternberg return -ENOMEM; 242957dacad5SJay Sternberg 243057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 243157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 243257dacad5SJay Sternberg 256, 256, 0); 243357dacad5SJay Sternberg if (!dev->prp_small_pool) { 243457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 243557dacad5SJay Sternberg return -ENOMEM; 243657dacad5SJay Sternberg } 243757dacad5SJay Sternberg return 0; 243857dacad5SJay Sternberg } 243957dacad5SJay Sternberg 244057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 244157dacad5SJay Sternberg { 244257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 244357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 244457dacad5SJay Sternberg } 244557dacad5SJay Sternberg 24461673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 244757dacad5SJay Sternberg { 24481673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 244957dacad5SJay Sternberg 2450f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 245157dacad5SJay Sternberg put_device(dev->dev); 245257dacad5SJay Sternberg if (dev->tagset.tags) 245357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24541c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24551c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 245657dacad5SJay Sternberg kfree(dev->queues); 2457e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2458943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 245957dacad5SJay Sternberg kfree(dev); 246057dacad5SJay Sternberg } 246157dacad5SJay Sternberg 2462f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2463f58944e2SKeith Busch { 2464237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2465f58944e2SKeith Busch 2466d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 246769d9a99cSKeith Busch nvme_dev_disable(dev, false); 24689f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 246903e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2470f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2471f58944e2SKeith Busch } 2472f58944e2SKeith Busch 2473fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 247457dacad5SJay Sternberg { 2475d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2476d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2477a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2478f58944e2SKeith Busch int result = -ENODEV; 24792b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 248057dacad5SJay Sternberg 248182b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2482fd634f41SChristoph Hellwig goto out; 2483fd634f41SChristoph Hellwig 2484fd634f41SChristoph Hellwig /* 2485fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2486fd634f41SChristoph Hellwig * moving on. 2487fd634f41SChristoph Hellwig */ 2488b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2489a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2490fd634f41SChristoph Hellwig 24915c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2492b00a726aSKeith Busch result = nvme_pci_enable(dev); 249357dacad5SJay Sternberg if (result) 24944726bcf3SKeith Busch goto out_unlock; 249557dacad5SJay Sternberg 249601ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 249757dacad5SJay Sternberg if (result) 24984726bcf3SKeith Busch goto out_unlock; 249957dacad5SJay Sternberg 250057dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 250157dacad5SJay Sternberg if (result) 25024726bcf3SKeith Busch goto out_unlock; 250357dacad5SJay Sternberg 2504943e942eSJens Axboe /* 2505943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2506943e942eSJens Axboe * over a single page. 2507943e942eSJens Axboe */ 2508943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2509943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 25105c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25115c959d73SKeith Busch 25125c959d73SKeith Busch /* 25135c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25145c959d73SKeith Busch * initializing procedure here. 25155c959d73SKeith Busch */ 25165c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25175c959d73SKeith Busch dev_warn(dev->ctrl.device, 25185c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 25195c959d73SKeith Busch goto out; 25205c959d73SKeith Busch } 2521943e942eSJens Axboe 2522ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2523ce4541f4SChristoph Hellwig if (result) 2524f58944e2SKeith Busch goto out; 2525ce4541f4SChristoph Hellwig 2526e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2527e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25284f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25294f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2530e286bcfcSScott Bauer else if (was_suspend) 25314f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2532e286bcfcSScott Bauer } else { 2533e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2534e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2535e286bcfcSScott Bauer } 2536a98e58e5SScott Bauer 2537f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2538f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2539f9f38e33SHelen Koike if (result) 2540f9f38e33SHelen Koike dev_warn(dev->dev, 2541f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2542f9f38e33SHelen Koike } 2543f9f38e33SHelen Koike 25449620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25459620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25469620cfbaSChristoph Hellwig if (result < 0) 25479620cfbaSChristoph Hellwig goto out; 25489620cfbaSChristoph Hellwig } 254987ad72a5SChristoph Hellwig 255057dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 255157dacad5SJay Sternberg if (result) 2552f58944e2SKeith Busch goto out; 255357dacad5SJay Sternberg 255421f033f7SKeith Busch /* 255557dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 255657dacad5SJay Sternberg * any working I/O queue. 255757dacad5SJay Sternberg */ 255857dacad5SJay Sternberg if (dev->online_queues < 2) { 25591b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25603b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25615bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25622b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 256357dacad5SJay Sternberg } else { 256425646264SKeith Busch nvme_start_queues(&dev->ctrl); 2565302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25662b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25672b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25682b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2569302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 257057dacad5SJay Sternberg } 257157dacad5SJay Sternberg 25722b1b7e78SJianchao Wang /* 25732b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25742b1b7e78SJianchao Wang * recovery. 25752b1b7e78SJianchao Wang */ 25762b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 25772b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25782b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2579bb8d261eSChristoph Hellwig goto out; 2580bb8d261eSChristoph Hellwig } 258192911a55SChristoph Hellwig 2582d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 258357dacad5SJay Sternberg return; 258457dacad5SJay Sternberg 25854726bcf3SKeith Busch out_unlock: 25864726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 258757dacad5SJay Sternberg out: 2588f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 258957dacad5SJay Sternberg } 259057dacad5SJay Sternberg 25915c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 259257dacad5SJay Sternberg { 25935c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 259457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 259557dacad5SJay Sternberg 259657dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2597921920abSKeith Busch device_release_driver(&pdev->dev); 25981673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 259957dacad5SJay Sternberg } 260057dacad5SJay Sternberg 26011c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 260257dacad5SJay Sternberg { 26031c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26041c63dc66SChristoph Hellwig return 0; 260557dacad5SJay Sternberg } 26061c63dc66SChristoph Hellwig 26075fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26085fd4ce1bSChristoph Hellwig { 26095fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26105fd4ce1bSChristoph Hellwig return 0; 26115fd4ce1bSChristoph Hellwig } 26125fd4ce1bSChristoph Hellwig 26137fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26147fd8930fSChristoph Hellwig { 26157fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26167fd8930fSChristoph Hellwig return 0; 26177fd8930fSChristoph Hellwig } 26187fd8930fSChristoph Hellwig 261997c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 262097c12223SKeith Busch { 262197c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 262297c12223SKeith Busch 262397c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 262497c12223SKeith Busch } 262597c12223SKeith Busch 26261c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26271a353d85SMing Lin .name = "pcie", 2628e439bb12SSagi Grimberg .module = THIS_MODULE, 2629e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2630e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26311c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26325fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26337fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26341673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2635f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 263697c12223SKeith Busch .get_address = nvme_pci_get_address, 26371c63dc66SChristoph Hellwig }; 263857dacad5SJay Sternberg 2639b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2640b00a726aSKeith Busch { 2641b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2642b00a726aSKeith Busch 2643a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2644b00a726aSKeith Busch return -ENODEV; 2645b00a726aSKeith Busch 264697f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2647b00a726aSKeith Busch goto release; 2648b00a726aSKeith Busch 2649b00a726aSKeith Busch return 0; 2650b00a726aSKeith Busch release: 2651a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2652b00a726aSKeith Busch return -ENODEV; 2653b00a726aSKeith Busch } 2654b00a726aSKeith Busch 26558427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2656ff5350a8SAndy Lutomirski { 2657ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2658ff5350a8SAndy Lutomirski /* 2659ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2660ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2661ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2662ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2663ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2664ff5350a8SAndy Lutomirski * laptops. 2665ff5350a8SAndy Lutomirski */ 2666ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2667ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2668ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2669ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26708427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26718427bbc2SKai-Heng Feng /* 26728427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2673467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2674467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2675467c77d4SJarosław Janik * ASUS PRIME Z370-A 26768427bbc2SKai-Heng Feng */ 26778427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2678467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2679467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 26808427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2681ff5350a8SAndy Lutomirski } 2682ff5350a8SAndy Lutomirski 2683ff5350a8SAndy Lutomirski return 0; 2684ff5350a8SAndy Lutomirski } 2685ff5350a8SAndy Lutomirski 268618119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 268718119775SKeith Busch { 268818119775SKeith Busch struct nvme_dev *dev = data; 268980f513b5SKeith Busch 269018119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 269118119775SKeith Busch flush_work(&dev->ctrl.scan_work); 269280f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 269318119775SKeith Busch } 269418119775SKeith Busch 269557dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 269657dacad5SJay Sternberg { 269757dacad5SJay Sternberg int node, result = -ENOMEM; 269857dacad5SJay Sternberg struct nvme_dev *dev; 2699ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2700943e942eSJens Axboe size_t alloc_size; 270157dacad5SJay Sternberg 270257dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 270357dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27042fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 270557dacad5SJay Sternberg 270657dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 270757dacad5SJay Sternberg if (!dev) 270857dacad5SJay Sternberg return -ENOMEM; 2709147b27e4SSagi Grimberg 27103b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27113b6592f7SJens Axboe GFP_KERNEL, node); 271257dacad5SJay Sternberg if (!dev->queues) 271357dacad5SJay Sternberg goto free; 271457dacad5SJay Sternberg 271557dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 271657dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 271757dacad5SJay Sternberg 2718b00a726aSKeith Busch result = nvme_dev_map(dev); 2719b00a726aSKeith Busch if (result) 2720b00c9b7aSChristophe JAILLET goto put_pci; 2721b00a726aSKeith Busch 2722d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27235c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 272477bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2725f3ca80fcSChristoph Hellwig 2726f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2727f3ca80fcSChristoph Hellwig if (result) 2728b00c9b7aSChristophe JAILLET goto unmap; 2729f3ca80fcSChristoph Hellwig 27308427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2731ff5350a8SAndy Lutomirski 2732943e942eSJens Axboe /* 2733943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2734943e942eSJens Axboe * command we support. 2735943e942eSJens Axboe */ 2736943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2737943e942eSJens Axboe NVME_MAX_SEGS, true); 2738943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2739943e942eSJens Axboe 2740943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2741943e942eSJens Axboe mempool_kfree, 2742943e942eSJens Axboe (void *) alloc_size, 2743943e942eSJens Axboe GFP_KERNEL, node); 2744943e942eSJens Axboe if (!dev->iod_mempool) { 2745943e942eSJens Axboe result = -ENOMEM; 2746943e942eSJens Axboe goto release_pools; 2747943e942eSJens Axboe } 2748943e942eSJens Axboe 2749b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2750b6e44b4cSKeith Busch quirks); 2751b6e44b4cSKeith Busch if (result) 2752b6e44b4cSKeith Busch goto release_mempool; 2753b6e44b4cSKeith Busch 27541b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27551b3c47c1SSagi Grimberg 275680f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 275718119775SKeith Busch async_schedule(nvme_async_probe, dev); 27584caff8fcSSagi Grimberg 275957dacad5SJay Sternberg return 0; 276057dacad5SJay Sternberg 2761b6e44b4cSKeith Busch release_mempool: 2762b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 276357dacad5SJay Sternberg release_pools: 276457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2765b00c9b7aSChristophe JAILLET unmap: 2766b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 276757dacad5SJay Sternberg put_pci: 276857dacad5SJay Sternberg put_device(dev->dev); 276957dacad5SJay Sternberg free: 277057dacad5SJay Sternberg kfree(dev->queues); 277157dacad5SJay Sternberg kfree(dev); 277257dacad5SJay Sternberg return result; 277357dacad5SJay Sternberg } 277457dacad5SJay Sternberg 2775775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 277657dacad5SJay Sternberg { 277757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2778a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2779775755edSChristoph Hellwig } 278057dacad5SJay Sternberg 2781775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2782775755edSChristoph Hellwig { 2783f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 278479c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 278557dacad5SJay Sternberg } 278657dacad5SJay Sternberg 278757dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 278857dacad5SJay Sternberg { 278957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2790a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 279157dacad5SJay Sternberg } 279257dacad5SJay Sternberg 2793f58944e2SKeith Busch /* 2794f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2795f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2796f58944e2SKeith Busch * order to proceed. 2797f58944e2SKeith Busch */ 279857dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 279957dacad5SJay Sternberg { 280057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 280157dacad5SJay Sternberg 2802bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 280357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28040ff9d4e1SKeith Busch 28056db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28060ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28071d39e692SKeith Busch nvme_dev_disable(dev, true); 2808cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28096db28edaSKeith Busch } 28100ff9d4e1SKeith Busch 2811d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2812d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2813d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2814a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28159fe5c59fSKeith Busch nvme_release_cmb(dev); 281687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 281757dacad5SJay Sternberg nvme_dev_remove_admin(dev); 281857dacad5SJay Sternberg nvme_free_queues(dev, 0); 2819d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 282057dacad5SJay Sternberg nvme_release_prp_pools(dev); 2821b00a726aSKeith Busch nvme_dev_unmap(dev); 28221673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 282357dacad5SJay Sternberg } 282457dacad5SJay Sternberg 282557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 282657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 282757dacad5SJay Sternberg { 282857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 282957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 283057dacad5SJay Sternberg 2831a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 283257dacad5SJay Sternberg return 0; 283357dacad5SJay Sternberg } 283457dacad5SJay Sternberg 283557dacad5SJay Sternberg static int nvme_resume(struct device *dev) 283657dacad5SJay Sternberg { 283757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 283857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 283957dacad5SJay Sternberg 2840d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 284157dacad5SJay Sternberg return 0; 284257dacad5SJay Sternberg } 284357dacad5SJay Sternberg #endif 284457dacad5SJay Sternberg 284557dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 284657dacad5SJay Sternberg 2847a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2848a0a3408eSKeith Busch pci_channel_state_t state) 2849a0a3408eSKeith Busch { 2850a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2851a0a3408eSKeith Busch 2852a0a3408eSKeith Busch /* 2853a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2854a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2855a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2856a0a3408eSKeith Busch */ 2857a0a3408eSKeith Busch switch (state) { 2858a0a3408eSKeith Busch case pci_channel_io_normal: 2859a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2860a0a3408eSKeith Busch case pci_channel_io_frozen: 2861d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2862d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2863a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2864a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2865a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2866d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2867d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2868a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2869a0a3408eSKeith Busch } 2870a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2871a0a3408eSKeith Busch } 2872a0a3408eSKeith Busch 2873a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2874a0a3408eSKeith Busch { 2875a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2876a0a3408eSKeith Busch 28771b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2878a0a3408eSKeith Busch pci_restore_state(pdev); 2879d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2880a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2881a0a3408eSKeith Busch } 2882a0a3408eSKeith Busch 2883a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2884a0a3408eSKeith Busch { 288572cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 288672cd4cc2SKeith Busch 288772cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2888a0a3408eSKeith Busch } 2889a0a3408eSKeith Busch 289057dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 289157dacad5SJay Sternberg .error_detected = nvme_error_detected, 289257dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 289357dacad5SJay Sternberg .resume = nvme_error_resume, 2894775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2895775755edSChristoph Hellwig .reset_done = nvme_reset_done, 289657dacad5SJay Sternberg }; 289757dacad5SJay Sternberg 289857dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2899106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 290008095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2901e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 290299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 290399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2904e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 290599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 290699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2907e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2908f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2909f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2910f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 291150af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29129abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29139abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 29146299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 29156299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2916540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 29177b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 29187b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 29190302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29200302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 292154adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 292254adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29238c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29248c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2925015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2926015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2927d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2928d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2929d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2930d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2931608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2932608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2933608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2934608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2935ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2936ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 293757dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2938c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2939124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 294057dacad5SJay Sternberg { 0, } 294157dacad5SJay Sternberg }; 294257dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 294357dacad5SJay Sternberg 294457dacad5SJay Sternberg static struct pci_driver nvme_driver = { 294557dacad5SJay Sternberg .name = "nvme", 294657dacad5SJay Sternberg .id_table = nvme_id_table, 294757dacad5SJay Sternberg .probe = nvme_probe, 294857dacad5SJay Sternberg .remove = nvme_remove, 294957dacad5SJay Sternberg .shutdown = nvme_shutdown, 295057dacad5SJay Sternberg .driver = { 295157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 295257dacad5SJay Sternberg }, 295374d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 295457dacad5SJay Sternberg .err_handler = &nvme_err_handler, 295557dacad5SJay Sternberg }; 295657dacad5SJay Sternberg 295757dacad5SJay Sternberg static int __init nvme_init(void) 295857dacad5SJay Sternberg { 2959612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 29609a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 296157dacad5SJay Sternberg } 296257dacad5SJay Sternberg 296357dacad5SJay Sternberg static void __exit nvme_exit(void) 296457dacad5SJay Sternberg { 296557dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 296603e0f3a6SMing Lei flush_workqueue(nvme_wq); 296757dacad5SJay Sternberg _nvme_check_size(); 296857dacad5SJay Sternberg } 296957dacad5SJay Sternberg 297057dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 297157dacad5SJay Sternberg MODULE_LICENSE("GPL"); 297257dacad5SJay Sternberg MODULE_VERSION("1.0"); 297357dacad5SJay Sternberg module_init(nvme_init); 297457dacad5SJay Sternberg module_exit(nvme_exit); 2975