157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/blkdev.h> 1757dacad5SJay Sternberg #include <linux/blk-mq.h> 18dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 19ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2057dacad5SJay Sternberg #include <linux/init.h> 2157dacad5SJay Sternberg #include <linux/interrupt.h> 2257dacad5SJay Sternberg #include <linux/io.h> 2357dacad5SJay Sternberg #include <linux/mm.h> 2457dacad5SJay Sternberg #include <linux/module.h> 2577bf25eaSKeith Busch #include <linux/mutex.h> 26d0877473SKeith Busch #include <linux/once.h> 2757dacad5SJay Sternberg #include <linux/pci.h> 2857dacad5SJay Sternberg #include <linux/t10-pi.h> 2957dacad5SJay Sternberg #include <linux/types.h> 309cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 31a98e58e5SScott Bauer #include <linux/sed-opal.h> 3257dacad5SJay Sternberg 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3657dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 4057dacad5SJay Sternberg static int use_threaded_interrupts; 4157dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4257dacad5SJay Sternberg 4357dacad5SJay Sternberg static bool use_cmb_sqes = true; 4457dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 4557dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4657dacad5SJay Sternberg 4787ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 4887ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 4987ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5087ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5157dacad5SJay Sternberg 52a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 53a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 54a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 55a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 56a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 57a7a7cbe3SChaitanya Kulkarni 58b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 59b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 60b27c1e68Sweiping zhang .set = io_queue_depth_set, 61b27c1e68Sweiping zhang .get = param_get_int, 62b27c1e68Sweiping zhang }; 63b27c1e68Sweiping zhang 64b27c1e68Sweiping zhang static int io_queue_depth = 1024; 65b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 66b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 67b27c1e68Sweiping zhang 681c63dc66SChristoph Hellwig struct nvme_dev; 691c63dc66SChristoph Hellwig struct nvme_queue; 7057dacad5SJay Sternberg 71a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 72a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7357dacad5SJay Sternberg 7457dacad5SJay Sternberg /* 751c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 761c63dc66SChristoph Hellwig */ 771c63dc66SChristoph Hellwig struct nvme_dev { 78147b27e4SSagi Grimberg struct nvme_queue *queues; 791c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 811c63dc66SChristoph Hellwig u32 __iomem *dbs; 821c63dc66SChristoph Hellwig struct device *dev; 831c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 841c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 851c63dc66SChristoph Hellwig unsigned online_queues; 861c63dc66SChristoph Hellwig unsigned max_qid; 8722b55601SKeith Busch unsigned int num_vecs; 881c63dc66SChristoph Hellwig int q_depth; 891c63dc66SChristoph Hellwig u32 db_stride; 901c63dc66SChristoph Hellwig void __iomem *bar; 9197f6ef64SXu Yu unsigned long bar_mapped_size; 925c8809e6SChristoph Hellwig struct work_struct remove_work; 9377bf25eaSKeith Busch struct mutex shutdown_lock; 941c63dc66SChristoph Hellwig bool subsystem; 951c63dc66SChristoph Hellwig void __iomem *cmb; 968969f1f8SChristoph Hellwig pci_bus_addr_t cmb_bus_addr; 971c63dc66SChristoph Hellwig u64 cmb_size; 981c63dc66SChristoph Hellwig u32 cmbsz; 99202021c1SStephen Bates u32 cmbloc; 1001c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 101db3cbfffSKeith Busch struct completion ioq_wait; 10287ad72a5SChristoph Hellwig 10387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 104f9f38e33SHelen Koike u32 *dbbuf_dbs; 105f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 106f9f38e33SHelen Koike u32 *dbbuf_eis; 107f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10887ad72a5SChristoph Hellwig 10987ad72a5SChristoph Hellwig /* host memory buffer support: */ 11087ad72a5SChristoph Hellwig u64 host_mem_size; 11187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1124033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 11387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11487ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11557dacad5SJay Sternberg }; 11657dacad5SJay Sternberg 117b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 118b27c1e68Sweiping zhang { 119b27c1e68Sweiping zhang int n = 0, ret; 120b27c1e68Sweiping zhang 121b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 122b27c1e68Sweiping zhang if (ret != 0 || n < 2) 123b27c1e68Sweiping zhang return -EINVAL; 124b27c1e68Sweiping zhang 125b27c1e68Sweiping zhang return param_set_int(val, kp); 126b27c1e68Sweiping zhang } 127b27c1e68Sweiping zhang 128f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 129f9f38e33SHelen Koike { 130f9f38e33SHelen Koike return qid * 2 * stride; 131f9f38e33SHelen Koike } 132f9f38e33SHelen Koike 133f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 134f9f38e33SHelen Koike { 135f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 136f9f38e33SHelen Koike } 137f9f38e33SHelen Koike 1381c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1391c63dc66SChristoph Hellwig { 1401c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1411c63dc66SChristoph Hellwig } 1421c63dc66SChristoph Hellwig 14357dacad5SJay Sternberg /* 14457dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14557dacad5SJay Sternberg * commands and one for I/O commands). 14657dacad5SJay Sternberg */ 14757dacad5SJay Sternberg struct nvme_queue { 14857dacad5SJay Sternberg struct device *q_dmadev; 14957dacad5SJay Sternberg struct nvme_dev *dev; 15057dacad5SJay Sternberg spinlock_t q_lock; 15157dacad5SJay Sternberg struct nvme_command *sq_cmds; 15257dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15357dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15457dacad5SJay Sternberg struct blk_mq_tags **tags; 15557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15757dacad5SJay Sternberg u32 __iomem *q_db; 15857dacad5SJay Sternberg u16 q_depth; 15957dacad5SJay Sternberg s16 cq_vector; 16057dacad5SJay Sternberg u16 sq_tail; 16157dacad5SJay Sternberg u16 cq_head; 16257dacad5SJay Sternberg u16 qid; 16357dacad5SJay Sternberg u8 cq_phase; 16457dacad5SJay Sternberg u8 cqe_seen; 165f9f38e33SHelen Koike u32 *dbbuf_sq_db; 166f9f38e33SHelen Koike u32 *dbbuf_cq_db; 167f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 168f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16957dacad5SJay Sternberg }; 17057dacad5SJay Sternberg 17157dacad5SJay Sternberg /* 17271bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17371bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 174f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17571bd150cSChristoph Hellwig * allocated to store the PRP list. 17671bd150cSChristoph Hellwig */ 17771bd150cSChristoph Hellwig struct nvme_iod { 178d49187e9SChristoph Hellwig struct nvme_request req; 179f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 180a7a7cbe3SChaitanya Kulkarni bool use_sgl; 181f4800d6dSChristoph Hellwig int aborted; 18271bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18371bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18471bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18571bd150cSChristoph Hellwig dma_addr_t first_dma; 186bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 187f4800d6dSChristoph Hellwig struct scatterlist *sg; 188f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18957dacad5SJay Sternberg }; 19057dacad5SJay Sternberg 19157dacad5SJay Sternberg /* 19257dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19357dacad5SJay Sternberg */ 19457dacad5SJay Sternberg static inline void _nvme_check_size(void) 19557dacad5SJay Sternberg { 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2040add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2050add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 208f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 209f9f38e33SHelen Koike } 210f9f38e33SHelen Koike 211f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 212f9f38e33SHelen Koike { 213f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 214f9f38e33SHelen Koike } 215f9f38e33SHelen Koike 216f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 217f9f38e33SHelen Koike { 218f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 219f9f38e33SHelen Koike 220f9f38e33SHelen Koike if (dev->dbbuf_dbs) 221f9f38e33SHelen Koike return 0; 222f9f38e33SHelen Koike 223f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 224f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 225f9f38e33SHelen Koike GFP_KERNEL); 226f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 227f9f38e33SHelen Koike return -ENOMEM; 228f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 229f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 230f9f38e33SHelen Koike GFP_KERNEL); 231f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 232f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 233f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 234f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 235f9f38e33SHelen Koike return -ENOMEM; 236f9f38e33SHelen Koike } 237f9f38e33SHelen Koike 238f9f38e33SHelen Koike return 0; 239f9f38e33SHelen Koike } 240f9f38e33SHelen Koike 241f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 242f9f38e33SHelen Koike { 243f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 244f9f38e33SHelen Koike 245f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 246f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 247f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 248f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 249f9f38e33SHelen Koike } 250f9f38e33SHelen Koike if (dev->dbbuf_eis) { 251f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 252f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 253f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 254f9f38e33SHelen Koike } 255f9f38e33SHelen Koike } 256f9f38e33SHelen Koike 257f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 258f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 259f9f38e33SHelen Koike { 260f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 261f9f38e33SHelen Koike return; 262f9f38e33SHelen Koike 263f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 266f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 267f9f38e33SHelen Koike } 268f9f38e33SHelen Koike 269f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 270f9f38e33SHelen Koike { 271f9f38e33SHelen Koike struct nvme_command c; 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 274f9f38e33SHelen Koike return; 275f9f38e33SHelen Koike 276f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 277f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 278f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 279f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2829bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 283f9f38e33SHelen Koike /* Free memory and continue on */ 284f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 289f9f38e33SHelen Koike { 290f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 291f9f38e33SHelen Koike } 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 294f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 295f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 296f9f38e33SHelen Koike { 297f9f38e33SHelen Koike if (dbbuf_db) { 298f9f38e33SHelen Koike u16 old_value; 299f9f38e33SHelen Koike 300f9f38e33SHelen Koike /* 301f9f38e33SHelen Koike * Ensure that the queue is written before updating 302f9f38e33SHelen Koike * the doorbell in memory 303f9f38e33SHelen Koike */ 304f9f38e33SHelen Koike wmb(); 305f9f38e33SHelen Koike 306f9f38e33SHelen Koike old_value = *dbbuf_db; 307f9f38e33SHelen Koike *dbbuf_db = value; 308f9f38e33SHelen Koike 309f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 310f9f38e33SHelen Koike return false; 311f9f38e33SHelen Koike } 312f9f38e33SHelen Koike 313f9f38e33SHelen Koike return true; 31457dacad5SJay Sternberg } 31557dacad5SJay Sternberg 31657dacad5SJay Sternberg /* 31757dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31857dacad5SJay Sternberg */ 31957dacad5SJay Sternberg #define NVME_INT_PAGES 2 3205fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 32157dacad5SJay Sternberg 32257dacad5SJay Sternberg /* 32357dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32457dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32557dacad5SJay Sternberg * the I/O. 32657dacad5SJay Sternberg */ 32757dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32857dacad5SJay Sternberg { 3295fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3305fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 33157dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33257dacad5SJay Sternberg } 33357dacad5SJay Sternberg 334a7a7cbe3SChaitanya Kulkarni /* 335a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 336a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 337a7a7cbe3SChaitanya Kulkarni */ 338a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 339f4800d6dSChristoph Hellwig { 340a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 341f4800d6dSChristoph Hellwig } 342f4800d6dSChristoph Hellwig 343a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 344a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 34557dacad5SJay Sternberg { 346a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 347a7a7cbe3SChaitanya Kulkarni 348a7a7cbe3SChaitanya Kulkarni if (use_sgl) 349a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 350a7a7cbe3SChaitanya Kulkarni else 351a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 352a7a7cbe3SChaitanya Kulkarni 353a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 354a7a7cbe3SChaitanya Kulkarni } 355a7a7cbe3SChaitanya Kulkarni 356a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 357a7a7cbe3SChaitanya Kulkarni { 358a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 359a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 360a7a7cbe3SChaitanya Kulkarni use_sgl); 361a7a7cbe3SChaitanya Kulkarni 362a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 36357dacad5SJay Sternberg } 36457dacad5SJay Sternberg 36557dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36657dacad5SJay Sternberg unsigned int hctx_idx) 36757dacad5SJay Sternberg { 36857dacad5SJay Sternberg struct nvme_dev *dev = data; 369147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 37057dacad5SJay Sternberg 37157dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37257dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37357dacad5SJay Sternberg WARN_ON(nvmeq->tags); 37457dacad5SJay Sternberg 37557dacad5SJay Sternberg hctx->driver_data = nvmeq; 37657dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 37757dacad5SJay Sternberg return 0; 37857dacad5SJay Sternberg } 37957dacad5SJay Sternberg 38057dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38157dacad5SJay Sternberg { 38257dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 38357dacad5SJay Sternberg 38457dacad5SJay Sternberg nvmeq->tags = NULL; 38557dacad5SJay Sternberg } 38657dacad5SJay Sternberg 38757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38857dacad5SJay Sternberg unsigned int hctx_idx) 38957dacad5SJay Sternberg { 39057dacad5SJay Sternberg struct nvme_dev *dev = data; 391147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39257dacad5SJay Sternberg 39357dacad5SJay Sternberg if (!nvmeq->tags) 39457dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 39557dacad5SJay Sternberg 39657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39757dacad5SJay Sternberg hctx->driver_data = nvmeq; 39857dacad5SJay Sternberg return 0; 39957dacad5SJay Sternberg } 40057dacad5SJay Sternberg 401d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 402d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40357dacad5SJay Sternberg { 404d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 405f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4060350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 407147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40857dacad5SJay Sternberg 40957dacad5SJay Sternberg BUG_ON(!nvmeq); 410f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41157dacad5SJay Sternberg return 0; 41257dacad5SJay Sternberg } 41357dacad5SJay Sternberg 414dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 415dca51e78SChristoph Hellwig { 416dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 417dca51e78SChristoph Hellwig 41822b55601SKeith Busch return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev), 41922b55601SKeith Busch dev->num_vecs > 1 ? 1 /* admin queue */ : 0); 420dca51e78SChristoph Hellwig } 421dca51e78SChristoph Hellwig 42257dacad5SJay Sternberg /** 423adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 42457dacad5SJay Sternberg * @nvmeq: The queue to use 42557dacad5SJay Sternberg * @cmd: The command to send 42657dacad5SJay Sternberg * 42757dacad5SJay Sternberg * Safe to use from interrupt context 42857dacad5SJay Sternberg */ 42957dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 43057dacad5SJay Sternberg struct nvme_command *cmd) 43157dacad5SJay Sternberg { 43257dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 43357dacad5SJay Sternberg 43457dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 43557dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 43657dacad5SJay Sternberg else 43757dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 43857dacad5SJay Sternberg 43957dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 44057dacad5SJay Sternberg tail = 0; 441f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 442f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 44357dacad5SJay Sternberg writel(tail, nvmeq->q_db); 44457dacad5SJay Sternberg nvmeq->sq_tail = tail; 44557dacad5SJay Sternberg } 44657dacad5SJay Sternberg 447a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 44857dacad5SJay Sternberg { 449f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 450a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 45157dacad5SJay Sternberg } 45257dacad5SJay Sternberg 453955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 454955b1b5aSMinwoo Im { 455955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 45620469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 457955b1b5aSMinwoo Im unsigned int avg_seg_size; 458955b1b5aSMinwoo Im 45920469a37SKeith Busch if (nseg == 0) 46020469a37SKeith Busch return false; 46120469a37SKeith Busch 46220469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 463955b1b5aSMinwoo Im 464955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 465955b1b5aSMinwoo Im return false; 466955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 467955b1b5aSMinwoo Im return false; 468955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 469955b1b5aSMinwoo Im return false; 470955b1b5aSMinwoo Im return true; 471955b1b5aSMinwoo Im } 472955b1b5aSMinwoo Im 473fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 47457dacad5SJay Sternberg { 475f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 476f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 477b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 478f4800d6dSChristoph Hellwig 479955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 480955b1b5aSMinwoo Im 481f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 482a7a7cbe3SChaitanya Kulkarni size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, 483a7a7cbe3SChaitanya Kulkarni iod->use_sgl); 484a7a7cbe3SChaitanya Kulkarni 485a7a7cbe3SChaitanya Kulkarni iod->sg = kmalloc(alloc_size, GFP_ATOMIC); 486f4800d6dSChristoph Hellwig if (!iod->sg) 487fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 488f4800d6dSChristoph Hellwig } else { 489f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 49057dacad5SJay Sternberg } 49157dacad5SJay Sternberg 492f4800d6dSChristoph Hellwig iod->aborted = 0; 49357dacad5SJay Sternberg iod->npages = -1; 49457dacad5SJay Sternberg iod->nents = 0; 495f4800d6dSChristoph Hellwig iod->length = size; 496f80ec966SKeith Busch 497fc17b653SChristoph Hellwig return BLK_STS_OK; 49857dacad5SJay Sternberg } 49957dacad5SJay Sternberg 500f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 50157dacad5SJay Sternberg { 502f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 503a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 504a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 505a7a7cbe3SChaitanya Kulkarni 50657dacad5SJay Sternberg int i; 50757dacad5SJay Sternberg 50857dacad5SJay Sternberg if (iod->npages == 0) 509a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 510a7a7cbe3SChaitanya Kulkarni dma_addr); 511a7a7cbe3SChaitanya Kulkarni 51257dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 513a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 514a7a7cbe3SChaitanya Kulkarni 515a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 516a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 517a7a7cbe3SChaitanya Kulkarni 518a7a7cbe3SChaitanya Kulkarni next_dma_addr = 519a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 520a7a7cbe3SChaitanya Kulkarni } else { 521a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 522a7a7cbe3SChaitanya Kulkarni 523a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 524a7a7cbe3SChaitanya Kulkarni } 525a7a7cbe3SChaitanya Kulkarni 526a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 527a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 52857dacad5SJay Sternberg } 52957dacad5SJay Sternberg 530f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 531f4800d6dSChristoph Hellwig kfree(iod->sg); 53257dacad5SJay Sternberg } 53357dacad5SJay Sternberg 53457dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 53557dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53657dacad5SJay Sternberg { 53757dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 53857dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 53957dacad5SJay Sternberg } 54057dacad5SJay Sternberg 54157dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54257dacad5SJay Sternberg { 54357dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 54457dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 54557dacad5SJay Sternberg } 54657dacad5SJay Sternberg 54757dacad5SJay Sternberg /** 54857dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 54957dacad5SJay Sternberg * 55057dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 55157dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 55257dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 55357dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 55457dacad5SJay Sternberg * 55557dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 55657dacad5SJay Sternberg */ 55757dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 55857dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 55957dacad5SJay Sternberg { 56057dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 56157dacad5SJay Sternberg struct bio_integrity_payload *bip; 56257dacad5SJay Sternberg struct t10_pi_tuple *pi; 56357dacad5SJay Sternberg void *p, *pmap; 56457dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 56557dacad5SJay Sternberg 56657dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 56757dacad5SJay Sternberg return; 56857dacad5SJay Sternberg 56957dacad5SJay Sternberg bip = bio_integrity(req->bio); 57057dacad5SJay Sternberg if (!bip) 57157dacad5SJay Sternberg return; 57257dacad5SJay Sternberg 57357dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 57457dacad5SJay Sternberg 57557dacad5SJay Sternberg p = pmap; 57657dacad5SJay Sternberg virt = bip_get_seed(bip); 57757dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 57857dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 579ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 58057dacad5SJay Sternberg 58157dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 58257dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 58357dacad5SJay Sternberg dif_swap(phys, virt, pi); 58457dacad5SJay Sternberg p += ts; 58557dacad5SJay Sternberg } 58657dacad5SJay Sternberg kunmap_atomic(pmap); 58757dacad5SJay Sternberg } 58857dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 58957dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 59057dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 59157dacad5SJay Sternberg { 59257dacad5SJay Sternberg } 59357dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 59457dacad5SJay Sternberg { 59557dacad5SJay Sternberg } 59657dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 59757dacad5SJay Sternberg { 59857dacad5SJay Sternberg } 59957dacad5SJay Sternberg #endif 60057dacad5SJay Sternberg 601d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 602d0877473SKeith Busch { 603d0877473SKeith Busch int i; 604d0877473SKeith Busch struct scatterlist *sg; 605d0877473SKeith Busch 606d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 607d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 608d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 609d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 610d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 611d0877473SKeith Busch sg_dma_len(sg)); 612d0877473SKeith Busch } 613d0877473SKeith Busch } 614d0877473SKeith Busch 615a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 616a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 61757dacad5SJay Sternberg { 618f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 61957dacad5SJay Sternberg struct dma_pool *pool; 620b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 62157dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 62257dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 62357dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6245fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 62557dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 62657dacad5SJay Sternberg __le64 *prp_list; 627a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 62857dacad5SJay Sternberg dma_addr_t prp_dma; 62957dacad5SJay Sternberg int nprps, i; 63057dacad5SJay Sternberg 63157dacad5SJay Sternberg length -= (page_size - offset); 6325228b328SJan H. Schönherr if (length <= 0) { 6335228b328SJan H. Schönherr iod->first_dma = 0; 634a7a7cbe3SChaitanya Kulkarni goto done; 6355228b328SJan H. Schönherr } 63657dacad5SJay Sternberg 63757dacad5SJay Sternberg dma_len -= (page_size - offset); 63857dacad5SJay Sternberg if (dma_len) { 63957dacad5SJay Sternberg dma_addr += (page_size - offset); 64057dacad5SJay Sternberg } else { 64157dacad5SJay Sternberg sg = sg_next(sg); 64257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 64457dacad5SJay Sternberg } 64557dacad5SJay Sternberg 64657dacad5SJay Sternberg if (length <= page_size) { 64757dacad5SJay Sternberg iod->first_dma = dma_addr; 648a7a7cbe3SChaitanya Kulkarni goto done; 64957dacad5SJay Sternberg } 65057dacad5SJay Sternberg 65157dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 65257dacad5SJay Sternberg if (nprps <= (256 / 8)) { 65357dacad5SJay Sternberg pool = dev->prp_small_pool; 65457dacad5SJay Sternberg iod->npages = 0; 65557dacad5SJay Sternberg } else { 65657dacad5SJay Sternberg pool = dev->prp_page_pool; 65757dacad5SJay Sternberg iod->npages = 1; 65857dacad5SJay Sternberg } 65957dacad5SJay Sternberg 66069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66157dacad5SJay Sternberg if (!prp_list) { 66257dacad5SJay Sternberg iod->first_dma = dma_addr; 66357dacad5SJay Sternberg iod->npages = -1; 66486eea289SKeith Busch return BLK_STS_RESOURCE; 66557dacad5SJay Sternberg } 66657dacad5SJay Sternberg list[0] = prp_list; 66757dacad5SJay Sternberg iod->first_dma = prp_dma; 66857dacad5SJay Sternberg i = 0; 66957dacad5SJay Sternberg for (;;) { 67057dacad5SJay Sternberg if (i == page_size >> 3) { 67157dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67269d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67357dacad5SJay Sternberg if (!prp_list) 67486eea289SKeith Busch return BLK_STS_RESOURCE; 67557dacad5SJay Sternberg list[iod->npages++] = prp_list; 67657dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 67757dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 67857dacad5SJay Sternberg i = 1; 67957dacad5SJay Sternberg } 68057dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 68157dacad5SJay Sternberg dma_len -= page_size; 68257dacad5SJay Sternberg dma_addr += page_size; 68357dacad5SJay Sternberg length -= page_size; 68457dacad5SJay Sternberg if (length <= 0) 68557dacad5SJay Sternberg break; 68657dacad5SJay Sternberg if (dma_len > 0) 68757dacad5SJay Sternberg continue; 68886eea289SKeith Busch if (unlikely(dma_len < 0)) 68986eea289SKeith Busch goto bad_sgl; 69057dacad5SJay Sternberg sg = sg_next(sg); 69157dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69257dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69357dacad5SJay Sternberg } 69457dacad5SJay Sternberg 695a7a7cbe3SChaitanya Kulkarni done: 696a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 697a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 698a7a7cbe3SChaitanya Kulkarni 69986eea289SKeith Busch return BLK_STS_OK; 70086eea289SKeith Busch 70186eea289SKeith Busch bad_sgl: 702d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 703d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 704d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 70586eea289SKeith Busch return BLK_STS_IOERR; 70657dacad5SJay Sternberg } 70757dacad5SJay Sternberg 708a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 709a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 710a7a7cbe3SChaitanya Kulkarni { 711a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 712a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 713a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 714a7a7cbe3SChaitanya Kulkarni } 715a7a7cbe3SChaitanya Kulkarni 716a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 717a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 718a7a7cbe3SChaitanya Kulkarni { 719a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 720a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 721a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 722a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 723a7a7cbe3SChaitanya Kulkarni } else { 724a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 725a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 726a7a7cbe3SChaitanya Kulkarni } 727a7a7cbe3SChaitanya Kulkarni } 728a7a7cbe3SChaitanya Kulkarni 729a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 730b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 731a7a7cbe3SChaitanya Kulkarni { 732a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 733a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 734a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 735a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 736a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 737b0f2853bSChristoph Hellwig int i = 0; 738a7a7cbe3SChaitanya Kulkarni 739a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 740a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 741a7a7cbe3SChaitanya Kulkarni 742b0f2853bSChristoph Hellwig if (entries == 1) { 743a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 744a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 745a7a7cbe3SChaitanya Kulkarni } 746a7a7cbe3SChaitanya Kulkarni 747a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 748a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 749a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 750a7a7cbe3SChaitanya Kulkarni } else { 751a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 752a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 753a7a7cbe3SChaitanya Kulkarni } 754a7a7cbe3SChaitanya Kulkarni 755a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 756a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 757a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 758a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 759a7a7cbe3SChaitanya Kulkarni } 760a7a7cbe3SChaitanya Kulkarni 761a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 762a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni do { 767a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 768a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 769a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 770a7a7cbe3SChaitanya Kulkarni 771a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 772a7a7cbe3SChaitanya Kulkarni if (!sg_list) 773a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 774a7a7cbe3SChaitanya Kulkarni 775a7a7cbe3SChaitanya Kulkarni i = 0; 776a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 777a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 778a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 779a7a7cbe3SChaitanya Kulkarni } 780a7a7cbe3SChaitanya Kulkarni 781a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 782a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 783b0f2853bSChristoph Hellwig } while (--entries > 0); 784a7a7cbe3SChaitanya Kulkarni 785a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 786a7a7cbe3SChaitanya Kulkarni } 787a7a7cbe3SChaitanya Kulkarni 788fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 789b131c61dSChristoph Hellwig struct nvme_command *cmnd) 79057dacad5SJay Sternberg { 791f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 792ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 793ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 794ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 795fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 796b0f2853bSChristoph Hellwig int nr_mapped; 79757dacad5SJay Sternberg 798f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 799ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 800ba1ca37eSChristoph Hellwig if (!iod->nents) 801ba1ca37eSChristoph Hellwig goto out; 802ba1ca37eSChristoph Hellwig 803fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 804b0f2853bSChristoph Hellwig nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 805b0f2853bSChristoph Hellwig DMA_ATTR_NO_WARN); 806b0f2853bSChristoph Hellwig if (!nr_mapped) 807ba1ca37eSChristoph Hellwig goto out; 808ba1ca37eSChristoph Hellwig 809955b1b5aSMinwoo Im if (iod->use_sgl) 810b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 811a7a7cbe3SChaitanya Kulkarni else 812a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 813a7a7cbe3SChaitanya Kulkarni 81486eea289SKeith Busch if (ret != BLK_STS_OK) 815ba1ca37eSChristoph Hellwig goto out_unmap; 816ba1ca37eSChristoph Hellwig 817fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 818ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 819ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 820ba1ca37eSChristoph Hellwig goto out_unmap; 821ba1ca37eSChristoph Hellwig 822bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 823bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 824ba1ca37eSChristoph Hellwig goto out_unmap; 825ba1ca37eSChristoph Hellwig 826b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 827ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 828ba1ca37eSChristoph Hellwig 829bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 830ba1ca37eSChristoph Hellwig goto out_unmap; 83157dacad5SJay Sternberg } 83257dacad5SJay Sternberg 833ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 834bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 835fc17b653SChristoph Hellwig return BLK_STS_OK; 836ba1ca37eSChristoph Hellwig 837ba1ca37eSChristoph Hellwig out_unmap: 838ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 839ba1ca37eSChristoph Hellwig out: 840ba1ca37eSChristoph Hellwig return ret; 84157dacad5SJay Sternberg } 84257dacad5SJay Sternberg 843f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 844d4f6c3abSChristoph Hellwig { 845f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 846d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 847d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 848d4f6c3abSChristoph Hellwig 849d4f6c3abSChristoph Hellwig if (iod->nents) { 850d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 851d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 852b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 853d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 854bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 855d4f6c3abSChristoph Hellwig } 856d4f6c3abSChristoph Hellwig } 857d4f6c3abSChristoph Hellwig 858f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 859f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 86057dacad5SJay Sternberg } 86157dacad5SJay Sternberg 86257dacad5SJay Sternberg /* 86357dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86457dacad5SJay Sternberg */ 865fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86657dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86757dacad5SJay Sternberg { 86857dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 86957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87157dacad5SJay Sternberg struct request *req = bd->rq; 872ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 873ebe6d874SChristoph Hellwig blk_status_t ret; 87457dacad5SJay Sternberg 875f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 876fc17b653SChristoph Hellwig if (ret) 877f4800d6dSChristoph Hellwig return ret; 87857dacad5SJay Sternberg 879b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 880fc17b653SChristoph Hellwig if (ret) 881f9d03f96SChristoph Hellwig goto out_free_cmd; 88257dacad5SJay Sternberg 883fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 884b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 885fc17b653SChristoph Hellwig if (ret) 886f9d03f96SChristoph Hellwig goto out_cleanup_iod; 887fc17b653SChristoph Hellwig } 888ba1ca37eSChristoph Hellwig 889aae239e1SChristoph Hellwig blk_mq_start_request(req); 890ba1ca37eSChristoph Hellwig 891ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 892ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 893fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 894ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 895f9d03f96SChristoph Hellwig goto out_cleanup_iod; 896ae1fba20SKeith Busch } 897ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 89857dacad5SJay Sternberg nvme_process_cq(nvmeq); 89957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 900fc17b653SChristoph Hellwig return BLK_STS_OK; 901f9d03f96SChristoph Hellwig out_cleanup_iod: 902f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 903f9d03f96SChristoph Hellwig out_free_cmd: 904f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 905ba1ca37eSChristoph Hellwig return ret; 90657dacad5SJay Sternberg } 90757dacad5SJay Sternberg 90877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 909eee417b0SChristoph Hellwig { 910f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 911eee417b0SChristoph Hellwig 91277f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 91377f02a7aSChristoph Hellwig nvme_complete_rq(req); 91457dacad5SJay Sternberg } 91557dacad5SJay Sternberg 916d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 917d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 918d783e0bdSMarta Rybczynska u16 phase) 919d783e0bdSMarta Rybczynska { 920d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 921d783e0bdSMarta Rybczynska } 922d783e0bdSMarta Rybczynska 923eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92457dacad5SJay Sternberg { 925eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92657dacad5SJay Sternberg 927eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 928eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 929eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 930eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 931eb281c82SSagi Grimberg } 93257dacad5SJay Sternberg } 933adf68f21SChristoph Hellwig 93483a12fb7SSagi Grimberg static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 93583a12fb7SSagi Grimberg struct nvme_completion *cqe) 93657dacad5SJay Sternberg { 93757dacad5SJay Sternberg struct request *req; 938adf68f21SChristoph Hellwig 93983a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9401b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 941aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94283a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94383a12fb7SSagi Grimberg return; 944aae239e1SChristoph Hellwig } 945aae239e1SChristoph Hellwig 946adf68f21SChristoph Hellwig /* 947adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 948adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 949adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 950adf68f21SChristoph Hellwig * for them but rather special case them here. 951adf68f21SChristoph Hellwig */ 952adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 95338dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9547bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95583a12fb7SSagi Grimberg cqe->status, &cqe->result); 956a0fa9647SJens Axboe return; 95757dacad5SJay Sternberg } 95857dacad5SJay Sternberg 959e9d8a0fdSKeith Busch nvmeq->cqe_seen = 1; 96083a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 96183a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 96283a12fb7SSagi Grimberg } 96357dacad5SJay Sternberg 964920d13a8SSagi Grimberg static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, 965920d13a8SSagi Grimberg struct nvme_completion *cqe) 96683a12fb7SSagi Grimberg { 967920d13a8SSagi Grimberg if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 968920d13a8SSagi Grimberg *cqe = nvmeq->cqes[nvmeq->cq_head]; 96983a12fb7SSagi Grimberg 970920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 971920d13a8SSagi Grimberg nvmeq->cq_head = 0; 972920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 973920d13a8SSagi Grimberg } 974920d13a8SSagi Grimberg return true; 975920d13a8SSagi Grimberg } 976920d13a8SSagi Grimberg return false; 977a0fa9647SJens Axboe } 978a0fa9647SJens Axboe 979a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 980a0fa9647SJens Axboe { 981920d13a8SSagi Grimberg struct nvme_completion cqe; 982920d13a8SSagi Grimberg int consumed = 0; 98383a12fb7SSagi Grimberg 984920d13a8SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 98583a12fb7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 986920d13a8SSagi Grimberg consumed++; 98757dacad5SJay Sternberg } 98857dacad5SJay Sternberg 989e9d8a0fdSKeith Busch if (consumed) 990eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 99157dacad5SJay Sternberg } 99257dacad5SJay Sternberg 99357dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 99457dacad5SJay Sternberg { 99557dacad5SJay Sternberg irqreturn_t result; 99657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 99757dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 99857dacad5SJay Sternberg nvme_process_cq(nvmeq); 99957dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 100057dacad5SJay Sternberg nvmeq->cqe_seen = 0; 100157dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 100257dacad5SJay Sternberg return result; 100357dacad5SJay Sternberg } 100457dacad5SJay Sternberg 100557dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 100657dacad5SJay Sternberg { 100757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1008d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 100957dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1010d783e0bdSMarta Rybczynska return IRQ_NONE; 101157dacad5SJay Sternberg } 101257dacad5SJay Sternberg 10137776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1014a0fa9647SJens Axboe { 1015442e19b7SSagi Grimberg struct nvme_completion cqe; 1016442e19b7SSagi Grimberg int found = 0, consumed = 0; 1017a0fa9647SJens Axboe 1018442e19b7SSagi Grimberg if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 1019442e19b7SSagi Grimberg return 0; 1020442e19b7SSagi Grimberg 1021442e19b7SSagi Grimberg spin_lock_irq(&nvmeq->q_lock); 1022442e19b7SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 1023442e19b7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 1024442e19b7SSagi Grimberg consumed++; 1025442e19b7SSagi Grimberg 1026442e19b7SSagi Grimberg if (tag == cqe.command_id) { 1027442e19b7SSagi Grimberg found = 1; 1028442e19b7SSagi Grimberg break; 1029442e19b7SSagi Grimberg } 1030a0fa9647SJens Axboe } 1031a0fa9647SJens Axboe 1032442e19b7SSagi Grimberg if (consumed) 1033442e19b7SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 1034442e19b7SSagi Grimberg spin_unlock_irq(&nvmeq->q_lock); 1035442e19b7SSagi Grimberg 1036442e19b7SSagi Grimberg return found; 1037a0fa9647SJens Axboe } 1038a0fa9647SJens Axboe 10397776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10407776db1cSKeith Busch { 10417776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10427776db1cSKeith Busch 10437776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10447776db1cSKeith Busch } 10457776db1cSKeith Busch 1046ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 104757dacad5SJay Sternberg { 1048f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1049147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 105057dacad5SJay Sternberg struct nvme_command c; 105157dacad5SJay Sternberg 105257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105357dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1054ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 105557dacad5SJay Sternberg 10569396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 10579396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 10589396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 105957dacad5SJay Sternberg } 106057dacad5SJay Sternberg 106157dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106257dacad5SJay Sternberg { 106357dacad5SJay Sternberg struct nvme_command c; 106457dacad5SJay Sternberg 106557dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106657dacad5SJay Sternberg c.delete_queue.opcode = opcode; 106757dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 106857dacad5SJay Sternberg 10691c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107057dacad5SJay Sternberg } 107157dacad5SJay Sternberg 107257dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 107357dacad5SJay Sternberg struct nvme_queue *nvmeq) 107457dacad5SJay Sternberg { 107557dacad5SJay Sternberg struct nvme_command c; 107657dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 107757dacad5SJay Sternberg 107857dacad5SJay Sternberg /* 107916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 108057dacad5SJay Sternberg * is attached to the request. 108157dacad5SJay Sternberg */ 108257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 108457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 108557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 108657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 108757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 108857dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 108957dacad5SJay Sternberg 10901c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 109157dacad5SJay Sternberg } 109257dacad5SJay Sternberg 109357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 109457dacad5SJay Sternberg struct nvme_queue *nvmeq) 109557dacad5SJay Sternberg { 10969abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 109757dacad5SJay Sternberg struct nvme_command c; 109881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 109957dacad5SJay Sternberg 110057dacad5SJay Sternberg /* 11019abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11029abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11039abd68efSJens Axboe * URGENT. 11049abd68efSJens Axboe */ 11059abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11069abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11079abd68efSJens Axboe 11089abd68efSJens Axboe /* 110916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 111057dacad5SJay Sternberg * is attached to the request. 111157dacad5SJay Sternberg */ 111257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 111357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 111457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 111557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 111657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 111757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 111857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 111957dacad5SJay Sternberg 11201c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 112157dacad5SJay Sternberg } 112257dacad5SJay Sternberg 112357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 112457dacad5SJay Sternberg { 112557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 112657dacad5SJay Sternberg } 112757dacad5SJay Sternberg 112857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 112957dacad5SJay Sternberg { 113057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 113157dacad5SJay Sternberg } 113257dacad5SJay Sternberg 11332a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 113457dacad5SJay Sternberg { 1135f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1136f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 113757dacad5SJay Sternberg 113827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 113927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1140e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1141e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 114257dacad5SJay Sternberg } 114357dacad5SJay Sternberg 1144b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1145b2a0eb1aSKeith Busch { 1146b2a0eb1aSKeith Busch 1147b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1148b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1149b2a0eb1aSKeith Busch */ 1150b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1151b2a0eb1aSKeith Busch 1152ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1153ad70062cSJianchao Wang switch (dev->ctrl.state) { 1154ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1155ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1156b2a0eb1aSKeith Busch return false; 1157ad70062cSJianchao Wang default: 1158ad70062cSJianchao Wang break; 1159ad70062cSJianchao Wang } 1160b2a0eb1aSKeith Busch 1161b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1162b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1163b2a0eb1aSKeith Busch */ 1164b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1165b2a0eb1aSKeith Busch return false; 1166b2a0eb1aSKeith Busch 1167b2a0eb1aSKeith Busch return true; 1168b2a0eb1aSKeith Busch } 1169b2a0eb1aSKeith Busch 1170b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1171b2a0eb1aSKeith Busch { 1172b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1173b2a0eb1aSKeith Busch u16 pci_status; 1174b2a0eb1aSKeith Busch int result; 1175b2a0eb1aSKeith Busch 1176b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1177b2a0eb1aSKeith Busch &pci_status); 1178b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1179b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1180b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1181b2a0eb1aSKeith Busch csts, pci_status); 1182b2a0eb1aSKeith Busch else 1183b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1184b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1185b2a0eb1aSKeith Busch csts, result); 1186b2a0eb1aSKeith Busch } 1187b2a0eb1aSKeith Busch 118831c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 118957dacad5SJay Sternberg { 1190f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1191f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 119257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 119357dacad5SJay Sternberg struct request *abort_req; 119457dacad5SJay Sternberg struct nvme_command cmd; 1195b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1196b2a0eb1aSKeith Busch 1197651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1198651438bbSWen Xiong * the recovery mechanism will surely fail. 1199651438bbSWen Xiong */ 1200651438bbSWen Xiong mb(); 1201651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1202651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1203651438bbSWen Xiong 1204b2a0eb1aSKeith Busch /* 1205b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1206b2a0eb1aSKeith Busch */ 1207b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1208b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1209b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1210d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1211b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1212b2a0eb1aSKeith Busch } 121357dacad5SJay Sternberg 121431c7c7d2SChristoph Hellwig /* 12157776db1cSKeith Busch * Did we miss an interrupt? 12167776db1cSKeith Busch */ 12177776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12187776db1cSKeith Busch dev_warn(dev->ctrl.device, 12197776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12207776db1cSKeith Busch req->tag, nvmeq->qid); 12217776db1cSKeith Busch return BLK_EH_HANDLED; 12227776db1cSKeith Busch } 12237776db1cSKeith Busch 12247776db1cSKeith Busch /* 1225fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1226fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1227fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1228fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1229fd634f41SChristoph Hellwig */ 12304244140dSKeith Busch switch (dev->ctrl.state) { 12314244140dSKeith Busch case NVME_CTRL_CONNECTING: 12324244140dSKeith Busch case NVME_CTRL_RESETTING: 12331b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1234fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1235fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1236a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 123727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1238fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 12394244140dSKeith Busch default: 12404244140dSKeith Busch break; 1241fd634f41SChristoph Hellwig } 1242fd634f41SChristoph Hellwig 1243fd634f41SChristoph Hellwig /* 1244e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1245e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1246e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 124731c7c7d2SChristoph Hellwig */ 1248f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12491b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 125057dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 125157dacad5SJay Sternberg req->tag, nvmeq->qid); 1252a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1253d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1254e1569a16SKeith Busch 1255e1569a16SKeith Busch /* 1256e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1257e1569a16SKeith Busch * forces all outstanding requests to complete. 1258e1569a16SKeith Busch */ 125927fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1260e1569a16SKeith Busch return BLK_EH_HANDLED; 126157dacad5SJay Sternberg } 126257dacad5SJay Sternberg 1263e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1264e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1265e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1266e7a2a87dSChristoph Hellwig } 12677bf7d778SKeith Busch iod->aborted = 1; 126857dacad5SJay Sternberg 126957dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 127057dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 127157dacad5SJay Sternberg cmd.abort.cid = req->tag; 127257dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 127357dacad5SJay Sternberg 12741b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12751b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 127657dacad5SJay Sternberg req->tag, nvmeq->qid); 1277e7a2a87dSChristoph Hellwig 1278e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1279eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12806bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12816bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 128231c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 128357dacad5SJay Sternberg } 128457dacad5SJay Sternberg 1285e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1286e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1287e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 128857dacad5SJay Sternberg 128957dacad5SJay Sternberg /* 129057dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 129157dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 129257dacad5SJay Sternberg * as the device then is in a faulty state. 129357dacad5SJay Sternberg */ 129457dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 129557dacad5SJay Sternberg } 129657dacad5SJay Sternberg 129757dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 129857dacad5SJay Sternberg { 129957dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 130057dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 130157dacad5SJay Sternberg if (nvmeq->sq_cmds) 130257dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 130357dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 130457dacad5SJay Sternberg } 130557dacad5SJay Sternberg 130657dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 130757dacad5SJay Sternberg { 130857dacad5SJay Sternberg int i; 130957dacad5SJay Sternberg 1310d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1311d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1312147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 131357dacad5SJay Sternberg } 131457dacad5SJay Sternberg } 131557dacad5SJay Sternberg 131657dacad5SJay Sternberg /** 131757dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 131857dacad5SJay Sternberg * @nvmeq - queue to suspend 131957dacad5SJay Sternberg */ 132057dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 132157dacad5SJay Sternberg { 132257dacad5SJay Sternberg int vector; 132357dacad5SJay Sternberg 132457dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 132557dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 132657dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 132757dacad5SJay Sternberg return 1; 132857dacad5SJay Sternberg } 13290ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 133057dacad5SJay Sternberg nvmeq->dev->online_queues--; 133157dacad5SJay Sternberg nvmeq->cq_vector = -1; 133257dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 133357dacad5SJay Sternberg 13341c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1335c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 133657dacad5SJay Sternberg 13370ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 133857dacad5SJay Sternberg 133957dacad5SJay Sternberg return 0; 134057dacad5SJay Sternberg } 134157dacad5SJay Sternberg 1342a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 134357dacad5SJay Sternberg { 1344147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 134557dacad5SJay Sternberg 1346a5cdb68cSKeith Busch if (shutdown) 1347a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1348a5cdb68cSKeith Busch else 134920d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 135057dacad5SJay Sternberg 135157dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 135257dacad5SJay Sternberg nvme_process_cq(nvmeq); 135357dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 135457dacad5SJay Sternberg } 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 135757dacad5SJay Sternberg int entry_size) 135857dacad5SJay Sternberg { 135957dacad5SJay Sternberg int q_depth = dev->q_depth; 13605fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13615fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 136257dacad5SJay Sternberg 136357dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 136457dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13655fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 136657dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 136757dacad5SJay Sternberg 136857dacad5SJay Sternberg /* 136957dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 137057dacad5SJay Sternberg * would be better to map queues in system memory with the 137157dacad5SJay Sternberg * original depth 137257dacad5SJay Sternberg */ 137357dacad5SJay Sternberg if (q_depth < 64) 137457dacad5SJay Sternberg return -ENOMEM; 137557dacad5SJay Sternberg } 137657dacad5SJay Sternberg 137757dacad5SJay Sternberg return q_depth; 137857dacad5SJay Sternberg } 137957dacad5SJay Sternberg 138057dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 138157dacad5SJay Sternberg int qid, int depth) 138257dacad5SJay Sternberg { 1383815c6704SKeith Busch /* CMB SQEs will be mapped before creation */ 1384815c6704SKeith Busch if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1385815c6704SKeith Busch return 0; 1386815c6704SKeith Busch 138757dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 138857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 138957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 139057dacad5SJay Sternberg return -ENOMEM; 139157dacad5SJay Sternberg return 0; 139257dacad5SJay Sternberg } 139357dacad5SJay Sternberg 1394a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 139557dacad5SJay Sternberg { 1396147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 139757dacad5SJay Sternberg 139862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 139962314e40SKeith Busch return 0; 140057dacad5SJay Sternberg 140157dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 140257dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 140357dacad5SJay Sternberg if (!nvmeq->cqes) 140457dacad5SJay Sternberg goto free_nvmeq; 140557dacad5SJay Sternberg 140657dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 140757dacad5SJay Sternberg goto free_cqdma; 140857dacad5SJay Sternberg 140957dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 141057dacad5SJay Sternberg nvmeq->dev = dev; 141157dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 141257dacad5SJay Sternberg nvmeq->cq_head = 0; 141357dacad5SJay Sternberg nvmeq->cq_phase = 1; 141457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 141557dacad5SJay Sternberg nvmeq->q_depth = depth; 141657dacad5SJay Sternberg nvmeq->qid = qid; 141757dacad5SJay Sternberg nvmeq->cq_vector = -1; 1418d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 141957dacad5SJay Sternberg 1420147b27e4SSagi Grimberg return 0; 142157dacad5SJay Sternberg 142257dacad5SJay Sternberg free_cqdma: 142357dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 142457dacad5SJay Sternberg nvmeq->cq_dma_addr); 142557dacad5SJay Sternberg free_nvmeq: 1426147b27e4SSagi Grimberg return -ENOMEM; 142757dacad5SJay Sternberg } 142857dacad5SJay Sternberg 1429dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 143057dacad5SJay Sternberg { 14310ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14320ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14330ff199cbSChristoph Hellwig 14340ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14350ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14360ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14370ff199cbSChristoph Hellwig } else { 14380ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14390ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14400ff199cbSChristoph Hellwig } 144157dacad5SJay Sternberg } 144257dacad5SJay Sternberg 144357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 144457dacad5SJay Sternberg { 144557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 144657dacad5SJay Sternberg 144757dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 144857dacad5SJay Sternberg nvmeq->sq_tail = 0; 144957dacad5SJay Sternberg nvmeq->cq_head = 0; 145057dacad5SJay Sternberg nvmeq->cq_phase = 1; 145157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 145257dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1453f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 145457dacad5SJay Sternberg dev->online_queues++; 145557dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 145657dacad5SJay Sternberg } 145757dacad5SJay Sternberg 145857dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 145957dacad5SJay Sternberg { 146057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 146157dacad5SJay Sternberg int result; 146257dacad5SJay Sternberg 1463815c6704SKeith Busch if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1464815c6704SKeith Busch unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1465815c6704SKeith Busch dev->ctrl.page_size); 1466815c6704SKeith Busch nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1467815c6704SKeith Busch nvmeq->sq_cmds_io = dev->cmb + offset; 1468815c6704SKeith Busch } 1469815c6704SKeith Busch 147022b55601SKeith Busch /* 147122b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 147222b55601SKeith Busch * has only one vector available. 147322b55601SKeith Busch */ 147422b55601SKeith Busch nvmeq->cq_vector = dev->num_vecs == 1 ? 0 : qid; 147557dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 147657dacad5SJay Sternberg if (result < 0) 1477f25a2dfcSJianchao Wang goto release_vector; 147857dacad5SJay Sternberg 147957dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 148057dacad5SJay Sternberg if (result < 0) 148157dacad5SJay Sternberg goto release_cq; 148257dacad5SJay Sternberg 1483161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1484dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 148557dacad5SJay Sternberg if (result < 0) 148657dacad5SJay Sternberg goto release_sq; 148757dacad5SJay Sternberg 148857dacad5SJay Sternberg return result; 148957dacad5SJay Sternberg 149057dacad5SJay Sternberg release_sq: 1491f25a2dfcSJianchao Wang dev->online_queues--; 149257dacad5SJay Sternberg adapter_delete_sq(dev, qid); 149357dacad5SJay Sternberg release_cq: 149457dacad5SJay Sternberg adapter_delete_cq(dev, qid); 1495f25a2dfcSJianchao Wang release_vector: 1496f25a2dfcSJianchao Wang nvmeq->cq_vector = -1; 149757dacad5SJay Sternberg return result; 149857dacad5SJay Sternberg } 149957dacad5SJay Sternberg 1500f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 150157dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 150277f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 150357dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 150457dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15050350815aSChristoph Hellwig .init_request = nvme_init_request, 150657dacad5SJay Sternberg .timeout = nvme_timeout, 150757dacad5SJay Sternberg }; 150857dacad5SJay Sternberg 1509f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 151057dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 151177f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 151257dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 151357dacad5SJay Sternberg .init_request = nvme_init_request, 1514dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 151557dacad5SJay Sternberg .timeout = nvme_timeout, 1516a0fa9647SJens Axboe .poll = nvme_poll, 151757dacad5SJay Sternberg }; 151857dacad5SJay Sternberg 151957dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 152057dacad5SJay Sternberg { 15211c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 152269d9a99cSKeith Busch /* 152369d9a99cSKeith Busch * If the controller was reset during removal, it's possible 152469d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 152569d9a99cSKeith Busch * queue to flush these to completion. 152669d9a99cSKeith Busch */ 1527c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15281c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 152957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 153057dacad5SJay Sternberg } 153157dacad5SJay Sternberg } 153257dacad5SJay Sternberg 153357dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 153457dacad5SJay Sternberg { 15351c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 153657dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 153757dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1538e3e9d50cSKeith Busch 153938dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 154057dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 154157dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1542a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1543d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 154457dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 154557dacad5SJay Sternberg 154657dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 154757dacad5SJay Sternberg return -ENOMEM; 154834b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 154957dacad5SJay Sternberg 15501c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15511c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 155257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 155357dacad5SJay Sternberg return -ENOMEM; 155457dacad5SJay Sternberg } 15551c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 155657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15571c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 155857dacad5SJay Sternberg return -ENODEV; 155957dacad5SJay Sternberg } 156057dacad5SJay Sternberg } else 1561c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 156257dacad5SJay Sternberg 156357dacad5SJay Sternberg return 0; 156457dacad5SJay Sternberg } 156557dacad5SJay Sternberg 156697f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 156797f6ef64SXu Yu { 156897f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 156997f6ef64SXu Yu } 157097f6ef64SXu Yu 157197f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 157297f6ef64SXu Yu { 157397f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 157497f6ef64SXu Yu 157597f6ef64SXu Yu if (size <= dev->bar_mapped_size) 157697f6ef64SXu Yu return 0; 157797f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 157897f6ef64SXu Yu return -ENOMEM; 157997f6ef64SXu Yu if (dev->bar) 158097f6ef64SXu Yu iounmap(dev->bar); 158197f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 158297f6ef64SXu Yu if (!dev->bar) { 158397f6ef64SXu Yu dev->bar_mapped_size = 0; 158497f6ef64SXu Yu return -ENOMEM; 158597f6ef64SXu Yu } 158697f6ef64SXu Yu dev->bar_mapped_size = size; 158797f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 158897f6ef64SXu Yu 158997f6ef64SXu Yu return 0; 159097f6ef64SXu Yu } 159197f6ef64SXu Yu 159201ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 159357dacad5SJay Sternberg { 159457dacad5SJay Sternberg int result; 159557dacad5SJay Sternberg u32 aqa; 159657dacad5SJay Sternberg struct nvme_queue *nvmeq; 159757dacad5SJay Sternberg 159897f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 159997f6ef64SXu Yu if (result < 0) 160097f6ef64SXu Yu return result; 160197f6ef64SXu Yu 16028ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 160320d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 160457dacad5SJay Sternberg 16057a67cbeaSChristoph Hellwig if (dev->subsystem && 16067a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 16077a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 160857dacad5SJay Sternberg 160920d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 161057dacad5SJay Sternberg if (result < 0) 161157dacad5SJay Sternberg return result; 161257dacad5SJay Sternberg 1613a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1614147b27e4SSagi Grimberg if (result) 1615147b27e4SSagi Grimberg return result; 161657dacad5SJay Sternberg 1617147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 161857dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 161957dacad5SJay Sternberg aqa |= aqa << 16; 162057dacad5SJay Sternberg 16217a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16227a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16237a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 162457dacad5SJay Sternberg 162520d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 162657dacad5SJay Sternberg if (result) 1627d4875622SKeith Busch return result; 162857dacad5SJay Sternberg 162957dacad5SJay Sternberg nvmeq->cq_vector = 0; 1630161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1631dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 163257dacad5SJay Sternberg if (result) { 163357dacad5SJay Sternberg nvmeq->cq_vector = -1; 1634d4875622SKeith Busch return result; 163557dacad5SJay Sternberg } 163657dacad5SJay Sternberg 163757dacad5SJay Sternberg return result; 163857dacad5SJay Sternberg } 163957dacad5SJay Sternberg 1640749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 164157dacad5SJay Sternberg { 1642949928c1SKeith Busch unsigned i, max; 1643749941f2SChristoph Hellwig int ret = 0; 164457dacad5SJay Sternberg 1645d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1646a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1647749941f2SChristoph Hellwig ret = -ENOMEM; 164857dacad5SJay Sternberg break; 1649749941f2SChristoph Hellwig } 1650749941f2SChristoph Hellwig } 165157dacad5SJay Sternberg 1652d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1653949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1654147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1655d4875622SKeith Busch if (ret) 165657dacad5SJay Sternberg break; 165757dacad5SJay Sternberg } 165857dacad5SJay Sternberg 1659749941f2SChristoph Hellwig /* 1660749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16618adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16628adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1663749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1664749941f2SChristoph Hellwig */ 1665749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 166657dacad5SJay Sternberg } 166757dacad5SJay Sternberg 1668202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1669202021c1SStephen Bates struct device_attribute *attr, 1670202021c1SStephen Bates char *buf) 1671202021c1SStephen Bates { 1672202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1673202021c1SStephen Bates 1674c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1675202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1676202021c1SStephen Bates } 1677202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1678202021c1SStephen Bates 167988de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 168057dacad5SJay Sternberg { 168188de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 168288de4598SChristoph Hellwig 168388de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 168488de4598SChristoph Hellwig } 168588de4598SChristoph Hellwig 168688de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 168788de4598SChristoph Hellwig { 168888de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 168988de4598SChristoph Hellwig } 169088de4598SChristoph Hellwig 1691f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 169257dacad5SJay Sternberg { 169388de4598SChristoph Hellwig u64 size, offset; 169457dacad5SJay Sternberg resource_size_t bar_size; 169557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 16968969f1f8SChristoph Hellwig int bar; 169757dacad5SJay Sternberg 16987a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1699f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1700f65efd6dSChristoph Hellwig return; 1701202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 170257dacad5SJay Sternberg 1703202021c1SStephen Bates if (!use_cmb_sqes) 1704f65efd6dSChristoph Hellwig return; 170557dacad5SJay Sternberg 170688de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 170788de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 17088969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 17098969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 171057dacad5SJay Sternberg 171157dacad5SJay Sternberg if (offset > bar_size) 1712f65efd6dSChristoph Hellwig return; 171357dacad5SJay Sternberg 171457dacad5SJay Sternberg /* 171557dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 171657dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 171757dacad5SJay Sternberg * the reported size of the BAR 171857dacad5SJay Sternberg */ 171957dacad5SJay Sternberg if (size > bar_size - offset) 172057dacad5SJay Sternberg size = bar_size - offset; 172157dacad5SJay Sternberg 1722f65efd6dSChristoph Hellwig dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1723f65efd6dSChristoph Hellwig if (!dev->cmb) 1724f65efd6dSChristoph Hellwig return; 17258969f1f8SChristoph Hellwig dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 172657dacad5SJay Sternberg dev->cmb_size = size; 1727f65efd6dSChristoph Hellwig 1728f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1729f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1730f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1731f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 173257dacad5SJay Sternberg } 173357dacad5SJay Sternberg 173457dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 173557dacad5SJay Sternberg { 173657dacad5SJay Sternberg if (dev->cmb) { 173757dacad5SJay Sternberg iounmap(dev->cmb); 173857dacad5SJay Sternberg dev->cmb = NULL; 1739f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1740f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1741f63572dfSJon Derrick dev->cmbsz = 0; 1742f63572dfSJon Derrick } 174357dacad5SJay Sternberg } 174457dacad5SJay Sternberg 174587ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 174657dacad5SJay Sternberg { 17474033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 174887ad72a5SChristoph Hellwig struct nvme_command c; 174987ad72a5SChristoph Hellwig int ret; 175087ad72a5SChristoph Hellwig 175187ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 175287ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 175387ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 175487ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 175587ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 175687ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 175787ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 175887ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 175987ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 176087ad72a5SChristoph Hellwig 176187ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 176287ad72a5SChristoph Hellwig if (ret) { 176387ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 176487ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 176587ad72a5SChristoph Hellwig ret, bits); 176687ad72a5SChristoph Hellwig } 176787ad72a5SChristoph Hellwig return ret; 176887ad72a5SChristoph Hellwig } 176987ad72a5SChristoph Hellwig 177087ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 177187ad72a5SChristoph Hellwig { 177287ad72a5SChristoph Hellwig int i; 177387ad72a5SChristoph Hellwig 177487ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 177587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 177687ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 177787ad72a5SChristoph Hellwig 177887ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 177987ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 178087ad72a5SChristoph Hellwig } 178187ad72a5SChristoph Hellwig 178287ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 178387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17844033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17854033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 17864033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 178787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 17887e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 178987ad72a5SChristoph Hellwig } 179087ad72a5SChristoph Hellwig 179192dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 179292dc6895SChristoph Hellwig u32 chunk_size) 179387ad72a5SChristoph Hellwig { 179487ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 179592dc6895SChristoph Hellwig u32 max_entries, len; 17964033f35dSChristoph Hellwig dma_addr_t descs_dma; 17972ee0e4edSDan Carpenter int i = 0; 179887ad72a5SChristoph Hellwig void **bufs; 17996fbcde66SMinwoo Im u64 size, tmp; 180087ad72a5SChristoph Hellwig 180187ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 180287ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 180387ad72a5SChristoph Hellwig max_entries = tmp; 1804044a9df1SChristoph Hellwig 1805044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1806044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1807044a9df1SChristoph Hellwig 18084033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 18094033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 181087ad72a5SChristoph Hellwig if (!descs) 181187ad72a5SChristoph Hellwig goto out; 181287ad72a5SChristoph Hellwig 181387ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 181487ad72a5SChristoph Hellwig if (!bufs) 181587ad72a5SChristoph Hellwig goto out_free_descs; 181687ad72a5SChristoph Hellwig 1817244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 181887ad72a5SChristoph Hellwig dma_addr_t dma_addr; 181987ad72a5SChristoph Hellwig 182050cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 182187ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 182287ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 182387ad72a5SChristoph Hellwig if (!bufs[i]) 182487ad72a5SChristoph Hellwig break; 182587ad72a5SChristoph Hellwig 182687ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 182787ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 182887ad72a5SChristoph Hellwig i++; 182987ad72a5SChristoph Hellwig } 183087ad72a5SChristoph Hellwig 183192dc6895SChristoph Hellwig if (!size) 183287ad72a5SChristoph Hellwig goto out_free_bufs; 183387ad72a5SChristoph Hellwig 183487ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 183587ad72a5SChristoph Hellwig dev->host_mem_size = size; 183687ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 18374033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 183887ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 183987ad72a5SChristoph Hellwig return 0; 184087ad72a5SChristoph Hellwig 184187ad72a5SChristoph Hellwig out_free_bufs: 184287ad72a5SChristoph Hellwig while (--i >= 0) { 184387ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 184487ad72a5SChristoph Hellwig 184587ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 184687ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 184787ad72a5SChristoph Hellwig } 184887ad72a5SChristoph Hellwig 184987ad72a5SChristoph Hellwig kfree(bufs); 185087ad72a5SChristoph Hellwig out_free_descs: 18514033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18524033f35dSChristoph Hellwig descs_dma); 185387ad72a5SChristoph Hellwig out: 185487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 185587ad72a5SChristoph Hellwig return -ENOMEM; 185687ad72a5SChristoph Hellwig } 185787ad72a5SChristoph Hellwig 185892dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 185992dc6895SChristoph Hellwig { 186092dc6895SChristoph Hellwig u32 chunk_size; 186192dc6895SChristoph Hellwig 186292dc6895SChristoph Hellwig /* start big and work our way down */ 186330f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1864044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 186592dc6895SChristoph Hellwig chunk_size /= 2) { 186692dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 186792dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 186892dc6895SChristoph Hellwig return 0; 186992dc6895SChristoph Hellwig nvme_free_host_mem(dev); 187092dc6895SChristoph Hellwig } 187192dc6895SChristoph Hellwig } 187292dc6895SChristoph Hellwig 187392dc6895SChristoph Hellwig return -ENOMEM; 187492dc6895SChristoph Hellwig } 187592dc6895SChristoph Hellwig 18769620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 187787ad72a5SChristoph Hellwig { 187887ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 187987ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 188087ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 188187ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18826fbcde66SMinwoo Im int ret; 188387ad72a5SChristoph Hellwig 188487ad72a5SChristoph Hellwig preferred = min(preferred, max); 188587ad72a5SChristoph Hellwig if (min > max) { 188687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 188787ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 188887ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 188987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18909620cfbaSChristoph Hellwig return 0; 189187ad72a5SChristoph Hellwig } 189287ad72a5SChristoph Hellwig 189387ad72a5SChristoph Hellwig /* 189487ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 189587ad72a5SChristoph Hellwig */ 189687ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 189787ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 189887ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 189987ad72a5SChristoph Hellwig else 190087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 190187ad72a5SChristoph Hellwig } 190287ad72a5SChristoph Hellwig 190387ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 190492dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 190592dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 190692dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 19079620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 190887ad72a5SChristoph Hellwig } 190987ad72a5SChristoph Hellwig 191092dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 191192dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 191292dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 191392dc6895SChristoph Hellwig } 191492dc6895SChristoph Hellwig 19159620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19169620cfbaSChristoph Hellwig if (ret) 191787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19189620cfbaSChristoph Hellwig return ret; 191957dacad5SJay Sternberg } 192057dacad5SJay Sternberg 192157dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 192257dacad5SJay Sternberg { 1923147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 192457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 192597f6ef64SXu Yu int result, nr_io_queues; 192697f6ef64SXu Yu unsigned long size; 192757dacad5SJay Sternberg 192822b55601SKeith Busch struct irq_affinity affd = { 192922b55601SKeith Busch .pre_vectors = 1 193022b55601SKeith Busch }; 193122b55601SKeith Busch 193216ccfff2SMing Lei nr_io_queues = num_possible_cpus(); 19339a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 19349a0be7abSChristoph Hellwig if (result < 0) 193557dacad5SJay Sternberg return result; 19369a0be7abSChristoph Hellwig 1937f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1938a5229050SKeith Busch return 0; 193957dacad5SJay Sternberg 194088de4598SChristoph Hellwig if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 194157dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 194257dacad5SJay Sternberg sizeof(struct nvme_command)); 194357dacad5SJay Sternberg if (result > 0) 194457dacad5SJay Sternberg dev->q_depth = result; 194557dacad5SJay Sternberg else 194657dacad5SJay Sternberg nvme_release_cmb(dev); 194757dacad5SJay Sternberg } 194857dacad5SJay Sternberg 194957dacad5SJay Sternberg do { 195097f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 195197f6ef64SXu Yu result = nvme_remap_bar(dev, size); 195297f6ef64SXu Yu if (!result) 195357dacad5SJay Sternberg break; 195457dacad5SJay Sternberg if (!--nr_io_queues) 195557dacad5SJay Sternberg return -ENOMEM; 195657dacad5SJay Sternberg } while (1); 195757dacad5SJay Sternberg adminq->q_db = dev->dbs; 195857dacad5SJay Sternberg 195957dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19600ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 196157dacad5SJay Sternberg 196257dacad5SJay Sternberg /* 196357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 196457dacad5SJay Sternberg * setting up the full range we need. 196557dacad5SJay Sternberg */ 1966dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 196722b55601SKeith Busch result = pci_alloc_irq_vectors_affinity(pdev, 1, nr_io_queues + 1, 196822b55601SKeith Busch PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 196922b55601SKeith Busch if (result <= 0) 1970dca51e78SChristoph Hellwig return -EIO; 197122b55601SKeith Busch dev->num_vecs = result; 197222b55601SKeith Busch dev->max_qid = max(result - 1, 1); 197357dacad5SJay Sternberg 197457dacad5SJay Sternberg /* 197557dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 197657dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 197757dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 197857dacad5SJay Sternberg * number of interrupts. 197957dacad5SJay Sternberg */ 198057dacad5SJay Sternberg 1981dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 198257dacad5SJay Sternberg if (result) { 198357dacad5SJay Sternberg adminq->cq_vector = -1; 1984d4875622SKeith Busch return result; 198557dacad5SJay Sternberg } 1986749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 198757dacad5SJay Sternberg } 198857dacad5SJay Sternberg 19892a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1990db3cbfffSKeith Busch { 1991db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1992db3cbfffSKeith Busch 1993db3cbfffSKeith Busch blk_mq_free_request(req); 1994db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1995db3cbfffSKeith Busch } 1996db3cbfffSKeith Busch 19972a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1998db3cbfffSKeith Busch { 1999db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2000db3cbfffSKeith Busch 2001db3cbfffSKeith Busch if (!error) { 2002db3cbfffSKeith Busch unsigned long flags; 2003db3cbfffSKeith Busch 20042e39e0f6SMing Lin /* 20052e39e0f6SMing Lin * We might be called with the AQ q_lock held 20062e39e0f6SMing Lin * and the I/O queue q_lock should always 20072e39e0f6SMing Lin * nest inside the AQ one. 20082e39e0f6SMing Lin */ 20092e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 20102e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 2011db3cbfffSKeith Busch nvme_process_cq(nvmeq); 2012db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 2013db3cbfffSKeith Busch } 2014db3cbfffSKeith Busch 2015db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2016db3cbfffSKeith Busch } 2017db3cbfffSKeith Busch 2018db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2019db3cbfffSKeith Busch { 2020db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2021db3cbfffSKeith Busch struct request *req; 2022db3cbfffSKeith Busch struct nvme_command cmd; 2023db3cbfffSKeith Busch 2024db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2025db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2026db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2027db3cbfffSKeith Busch 2028eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2029db3cbfffSKeith Busch if (IS_ERR(req)) 2030db3cbfffSKeith Busch return PTR_ERR(req); 2031db3cbfffSKeith Busch 2032db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2033db3cbfffSKeith Busch req->end_io_data = nvmeq; 2034db3cbfffSKeith Busch 2035db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2036db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2037db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2038db3cbfffSKeith Busch return 0; 2039db3cbfffSKeith Busch } 2040db3cbfffSKeith Busch 2041ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2042db3cbfffSKeith Busch { 2043ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2044db3cbfffSKeith Busch unsigned long timeout; 2045db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2046db3cbfffSKeith Busch 2047db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2048014a0d60SKeith Busch int sent = 0, i = queues; 2049db3cbfffSKeith Busch 2050db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2051db3cbfffSKeith Busch retry: 2052db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2053c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2054147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2055db3cbfffSKeith Busch break; 2056c21377f8SGabriel Krisman Bertazi 2057db3cbfffSKeith Busch while (sent--) { 2058db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2059db3cbfffSKeith Busch if (timeout == 0) 2060db3cbfffSKeith Busch return; 2061db3cbfffSKeith Busch if (i) 2062db3cbfffSKeith Busch goto retry; 2063db3cbfffSKeith Busch } 2064db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2065db3cbfffSKeith Busch } 2066db3cbfffSKeith Busch } 2067db3cbfffSKeith Busch 206857dacad5SJay Sternberg /* 20692b1b7e78SJianchao Wang * return error value only when tagset allocation failed 207057dacad5SJay Sternberg */ 207157dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 207257dacad5SJay Sternberg { 20732b1b7e78SJianchao Wang int ret; 20742b1b7e78SJianchao Wang 20755bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 207657dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 207757dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 207857dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 207957dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 208057dacad5SJay Sternberg dev->tagset.queue_depth = 208157dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2082a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2083a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2084a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2085a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2086a7a7cbe3SChaitanya Kulkarni } 208757dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 208857dacad5SJay Sternberg dev->tagset.driver_data = dev; 208957dacad5SJay Sternberg 20902b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 20912b1b7e78SJianchao Wang if (ret) { 20922b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 20932b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 20942b1b7e78SJianchao Wang return ret; 20952b1b7e78SJianchao Wang } 20965bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2097f9f38e33SHelen Koike 2098f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2099949928c1SKeith Busch } else { 2100949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2101949928c1SKeith Busch 2102949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2103949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 210457dacad5SJay Sternberg } 2105949928c1SKeith Busch 210657dacad5SJay Sternberg return 0; 210757dacad5SJay Sternberg } 210857dacad5SJay Sternberg 2109b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 211057dacad5SJay Sternberg { 2111b00a726aSKeith Busch int result = -ENOMEM; 211257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 211357dacad5SJay Sternberg 211457dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 211557dacad5SJay Sternberg return result; 211657dacad5SJay Sternberg 211757dacad5SJay Sternberg pci_set_master(pdev); 211857dacad5SJay Sternberg 211957dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 212057dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 212157dacad5SJay Sternberg goto disable; 212257dacad5SJay Sternberg 21237a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 212457dacad5SJay Sternberg result = -ENODEV; 2125b00a726aSKeith Busch goto disable; 212657dacad5SJay Sternberg } 212757dacad5SJay Sternberg 212857dacad5SJay Sternberg /* 2129a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2130a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2131a5229050SKeith Busch * adjust this later. 213257dacad5SJay Sternberg */ 2133dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2134dca51e78SChristoph Hellwig if (result < 0) 2135dca51e78SChristoph Hellwig return result; 213657dacad5SJay Sternberg 213720d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 21387a67cbeaSChristoph Hellwig 213920d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2140b27c1e68Sweiping zhang io_queue_depth); 214120d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21427a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21431f390c1fSStephan Günther 21441f390c1fSStephan Günther /* 21451f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21461f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21471f390c1fSStephan Günther */ 21481f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21491f390c1fSStephan Günther dev->q_depth = 2; 21509bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21519bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21521f390c1fSStephan Günther dev->q_depth); 2153d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2154d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 215520d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2156d554b5e1SMartin K. Petersen dev->q_depth = 64; 2157d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2158d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21591f390c1fSStephan Günther } 21601f390c1fSStephan Günther 2161f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2162202021c1SStephen Bates 2163a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2164a0a3408eSKeith Busch pci_save_state(pdev); 216557dacad5SJay Sternberg return 0; 216657dacad5SJay Sternberg 216757dacad5SJay Sternberg disable: 216857dacad5SJay Sternberg pci_disable_device(pdev); 216957dacad5SJay Sternberg return result; 217057dacad5SJay Sternberg } 217157dacad5SJay Sternberg 217257dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 217357dacad5SJay Sternberg { 2174b00a726aSKeith Busch if (dev->bar) 2175b00a726aSKeith Busch iounmap(dev->bar); 2176a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2177b00a726aSKeith Busch } 2178b00a726aSKeith Busch 2179b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2180b00a726aSKeith Busch { 218157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 218257dacad5SJay Sternberg 2183f63572dfSJon Derrick nvme_release_cmb(dev); 2184dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 218557dacad5SJay Sternberg 2186a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2187a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 218857dacad5SJay Sternberg pci_disable_device(pdev); 218957dacad5SJay Sternberg } 2190a0a3408eSKeith Busch } 219157dacad5SJay Sternberg 2192a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 219357dacad5SJay Sternberg { 2194ee9aebb2SKeith Busch int i; 2195302ad8ccSKeith Busch bool dead = true; 2196302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 219757dacad5SJay Sternberg 219877bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2199302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2200302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2201302ad8ccSKeith Busch 2202ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2203ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2204302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2205302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2206302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 220757dacad5SJay Sternberg } 2208c21377f8SGabriel Krisman Bertazi 2209302ad8ccSKeith Busch /* 2210302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2211302ad8ccSKeith Busch * doing a safe shutdown. 2212302ad8ccSKeith Busch */ 221387ad72a5SChristoph Hellwig if (!dead) { 221487ad72a5SChristoph Hellwig if (shutdown) 2215302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 22169a915a5bSJianchao Wang } 221787ad72a5SChristoph Hellwig 22189a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 22199a915a5bSJianchao Wang 222064ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 222187ad72a5SChristoph Hellwig /* 222287ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 222387ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 222487ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 222587ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 222687ad72a5SChristoph Hellwig */ 222787ad72a5SChristoph Hellwig if (dev->host_mem_descs) 222887ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 2229ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2230a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 223157dacad5SJay Sternberg } 2232ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2233ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2234ee9aebb2SKeith Busch 2235b00a726aSKeith Busch nvme_pci_disable(dev); 223657dacad5SJay Sternberg 2237e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2238e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2239302ad8ccSKeith Busch 2240302ad8ccSKeith Busch /* 2241302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2242302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2243302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2244302ad8ccSKeith Busch */ 2245302ad8ccSKeith Busch if (shutdown) 2246302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 224777bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 224857dacad5SJay Sternberg } 224957dacad5SJay Sternberg 225057dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 225157dacad5SJay Sternberg { 225257dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 225357dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 225457dacad5SJay Sternberg if (!dev->prp_page_pool) 225557dacad5SJay Sternberg return -ENOMEM; 225657dacad5SJay Sternberg 225757dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 225857dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 225957dacad5SJay Sternberg 256, 256, 0); 226057dacad5SJay Sternberg if (!dev->prp_small_pool) { 226157dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 226257dacad5SJay Sternberg return -ENOMEM; 226357dacad5SJay Sternberg } 226457dacad5SJay Sternberg return 0; 226557dacad5SJay Sternberg } 226657dacad5SJay Sternberg 226757dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 226857dacad5SJay Sternberg { 226957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 227057dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 227157dacad5SJay Sternberg } 227257dacad5SJay Sternberg 22731673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 227457dacad5SJay Sternberg { 22751673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 227657dacad5SJay Sternberg 2277f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 227857dacad5SJay Sternberg put_device(dev->dev); 227957dacad5SJay Sternberg if (dev->tagset.tags) 228057dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22811c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22821c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 228357dacad5SJay Sternberg kfree(dev->queues); 2284e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 228557dacad5SJay Sternberg kfree(dev); 228657dacad5SJay Sternberg } 228757dacad5SJay Sternberg 2288f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2289f58944e2SKeith Busch { 2290237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2291f58944e2SKeith Busch 2292d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 229369d9a99cSKeith Busch nvme_dev_disable(dev, false); 229403e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2295f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2296f58944e2SKeith Busch } 2297f58944e2SKeith Busch 2298fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 229957dacad5SJay Sternberg { 2300d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2301d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2302a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2303f58944e2SKeith Busch int result = -ENODEV; 23042b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 230557dacad5SJay Sternberg 230682b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2307fd634f41SChristoph Hellwig goto out; 2308fd634f41SChristoph Hellwig 2309fd634f41SChristoph Hellwig /* 2310fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2311fd634f41SChristoph Hellwig * moving on. 2312fd634f41SChristoph Hellwig */ 2313b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2314a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2315fd634f41SChristoph Hellwig 2316ad70062cSJianchao Wang /* 2317ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2318ad70062cSJianchao Wang * initializing procedure here. 2319ad70062cSJianchao Wang */ 2320ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2321ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2322ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2323ad70062cSJianchao Wang goto out; 2324ad70062cSJianchao Wang } 2325ad70062cSJianchao Wang 2326b00a726aSKeith Busch result = nvme_pci_enable(dev); 232757dacad5SJay Sternberg if (result) 232857dacad5SJay Sternberg goto out; 232957dacad5SJay Sternberg 233001ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 233157dacad5SJay Sternberg if (result) 2332f58944e2SKeith Busch goto out; 233357dacad5SJay Sternberg 233457dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 233557dacad5SJay Sternberg if (result) 2336f58944e2SKeith Busch goto out; 233757dacad5SJay Sternberg 2338ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2339ce4541f4SChristoph Hellwig if (result) 2340f58944e2SKeith Busch goto out; 2341ce4541f4SChristoph Hellwig 2342e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2343e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23444f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23454f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2346e286bcfcSScott Bauer else if (was_suspend) 23474f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2348e286bcfcSScott Bauer } else { 2349e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2350e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2351e286bcfcSScott Bauer } 2352a98e58e5SScott Bauer 2353f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2354f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2355f9f38e33SHelen Koike if (result) 2356f9f38e33SHelen Koike dev_warn(dev->dev, 2357f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2358f9f38e33SHelen Koike } 2359f9f38e33SHelen Koike 23609620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23619620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23629620cfbaSChristoph Hellwig if (result < 0) 23639620cfbaSChristoph Hellwig goto out; 23649620cfbaSChristoph Hellwig } 236587ad72a5SChristoph Hellwig 236657dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 236757dacad5SJay Sternberg if (result) 2368f58944e2SKeith Busch goto out; 236957dacad5SJay Sternberg 237021f033f7SKeith Busch /* 237157dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 237257dacad5SJay Sternberg * any working I/O queue. 237357dacad5SJay Sternberg */ 237457dacad5SJay Sternberg if (dev->online_queues < 2) { 23751b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23763b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23775bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23782b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 237957dacad5SJay Sternberg } else { 238025646264SKeith Busch nvme_start_queues(&dev->ctrl); 2381302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23822b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23832b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23842b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2385302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 238657dacad5SJay Sternberg } 238757dacad5SJay Sternberg 23882b1b7e78SJianchao Wang /* 23892b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 23902b1b7e78SJianchao Wang * recovery. 23912b1b7e78SJianchao Wang */ 23922b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 23932b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23942b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2395bb8d261eSChristoph Hellwig goto out; 2396bb8d261eSChristoph Hellwig } 239792911a55SChristoph Hellwig 2398d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 239957dacad5SJay Sternberg return; 240057dacad5SJay Sternberg 240157dacad5SJay Sternberg out: 2402f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 240357dacad5SJay Sternberg } 240457dacad5SJay Sternberg 24055c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 240657dacad5SJay Sternberg { 24075c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 240857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 240957dacad5SJay Sternberg 241069d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 241157dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2412921920abSKeith Busch device_release_driver(&pdev->dev); 24131673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 241457dacad5SJay Sternberg } 241557dacad5SJay Sternberg 24161c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 241757dacad5SJay Sternberg { 24181c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 24191c63dc66SChristoph Hellwig return 0; 242057dacad5SJay Sternberg } 24211c63dc66SChristoph Hellwig 24225fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 24235fd4ce1bSChristoph Hellwig { 24245fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 24255fd4ce1bSChristoph Hellwig return 0; 24265fd4ce1bSChristoph Hellwig } 24275fd4ce1bSChristoph Hellwig 24287fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 24297fd8930fSChristoph Hellwig { 24307fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24317fd8930fSChristoph Hellwig return 0; 24327fd8930fSChristoph Hellwig } 24337fd8930fSChristoph Hellwig 243497c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 243597c12223SKeith Busch { 243697c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 243797c12223SKeith Busch 243897c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 243997c12223SKeith Busch } 244097c12223SKeith Busch 24411c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24421a353d85SMing Lin .name = "pcie", 2443e439bb12SSagi Grimberg .module = THIS_MODULE, 2444c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24451c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24465fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24477fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24481673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2449f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 245097c12223SKeith Busch .get_address = nvme_pci_get_address, 24511c63dc66SChristoph Hellwig }; 245257dacad5SJay Sternberg 2453b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2454b00a726aSKeith Busch { 2455b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2456b00a726aSKeith Busch 2457a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2458b00a726aSKeith Busch return -ENODEV; 2459b00a726aSKeith Busch 246097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2461b00a726aSKeith Busch goto release; 2462b00a726aSKeith Busch 2463b00a726aSKeith Busch return 0; 2464b00a726aSKeith Busch release: 2465a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2466b00a726aSKeith Busch return -ENODEV; 2467b00a726aSKeith Busch } 2468b00a726aSKeith Busch 24698427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2470ff5350a8SAndy Lutomirski { 2471ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2472ff5350a8SAndy Lutomirski /* 2473ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2474ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2475ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2476ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2477ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2478ff5350a8SAndy Lutomirski * laptops. 2479ff5350a8SAndy Lutomirski */ 2480ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2481ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2482ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2483ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24848427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24858427bbc2SKai-Heng Feng /* 24868427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2487467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2488467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2489467c77d4SJarosław Janik * ASUS PRIME Z370-A 24908427bbc2SKai-Heng Feng */ 24918427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2492467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2493467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 24948427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2495ff5350a8SAndy Lutomirski } 2496ff5350a8SAndy Lutomirski 2497ff5350a8SAndy Lutomirski return 0; 2498ff5350a8SAndy Lutomirski } 2499ff5350a8SAndy Lutomirski 250057dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 250157dacad5SJay Sternberg { 250257dacad5SJay Sternberg int node, result = -ENOMEM; 250357dacad5SJay Sternberg struct nvme_dev *dev; 2504ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 250557dacad5SJay Sternberg 250657dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 250757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 25082fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 250957dacad5SJay Sternberg 251057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 251157dacad5SJay Sternberg if (!dev) 251257dacad5SJay Sternberg return -ENOMEM; 2513147b27e4SSagi Grimberg 2514147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2515147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 251657dacad5SJay Sternberg if (!dev->queues) 251757dacad5SJay Sternberg goto free; 251857dacad5SJay Sternberg 251957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 252057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 252157dacad5SJay Sternberg 2522b00a726aSKeith Busch result = nvme_dev_map(dev); 2523b00a726aSKeith Busch if (result) 2524b00c9b7aSChristophe JAILLET goto put_pci; 2525b00a726aSKeith Busch 2526d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 25275c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 252877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2529db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2530f3ca80fcSChristoph Hellwig 2531f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2532f3ca80fcSChristoph Hellwig if (result) 2533b00c9b7aSChristophe JAILLET goto unmap; 2534f3ca80fcSChristoph Hellwig 25358427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2536ff5350a8SAndy Lutomirski 2537f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2538ff5350a8SAndy Lutomirski quirks); 2539f3ca80fcSChristoph Hellwig if (result) 2540f3ca80fcSChristoph Hellwig goto release_pools; 2541f3ca80fcSChristoph Hellwig 25421b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25431b3c47c1SSagi Grimberg 25444caff8fcSSagi Grimberg nvme_reset_ctrl(&dev->ctrl); 25454caff8fcSSagi Grimberg 254657dacad5SJay Sternberg return 0; 254757dacad5SJay Sternberg 254857dacad5SJay Sternberg release_pools: 254957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2550b00c9b7aSChristophe JAILLET unmap: 2551b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 255257dacad5SJay Sternberg put_pci: 255357dacad5SJay Sternberg put_device(dev->dev); 255457dacad5SJay Sternberg free: 255557dacad5SJay Sternberg kfree(dev->queues); 255657dacad5SJay Sternberg kfree(dev); 255757dacad5SJay Sternberg return result; 255857dacad5SJay Sternberg } 255957dacad5SJay Sternberg 2560775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 256157dacad5SJay Sternberg { 256257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2563a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2564775755edSChristoph Hellwig } 256557dacad5SJay Sternberg 2566775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2567775755edSChristoph Hellwig { 2568f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 256979c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 257057dacad5SJay Sternberg } 257157dacad5SJay Sternberg 257257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 257357dacad5SJay Sternberg { 257457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2575a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 257657dacad5SJay Sternberg } 257757dacad5SJay Sternberg 2578f58944e2SKeith Busch /* 2579f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2580f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2581f58944e2SKeith Busch * order to proceed. 2582f58944e2SKeith Busch */ 258357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 258457dacad5SJay Sternberg { 258557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 258657dacad5SJay Sternberg 2587bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2588bb8d261eSChristoph Hellwig 2589d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 259057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 25910ff9d4e1SKeith Busch 25926db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 25930ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 25946db28edaSKeith Busch nvme_dev_disable(dev, false); 25956db28edaSKeith Busch } 25960ff9d4e1SKeith Busch 2597d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2598d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2599d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2600a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 260187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 260257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 260357dacad5SJay Sternberg nvme_free_queues(dev, 0); 2604d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 260557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2606b00a726aSKeith Busch nvme_dev_unmap(dev); 26071673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 260857dacad5SJay Sternberg } 260957dacad5SJay Sternberg 261013880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 261113880f5bSKeith Busch { 261213880f5bSKeith Busch int ret = 0; 261313880f5bSKeith Busch 261413880f5bSKeith Busch if (numvfs == 0) { 261513880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 261613880f5bSKeith Busch dev_warn(&pdev->dev, 261713880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 261813880f5bSKeith Busch return -EPERM; 261913880f5bSKeith Busch } 262013880f5bSKeith Busch pci_disable_sriov(pdev); 262113880f5bSKeith Busch return 0; 262213880f5bSKeith Busch } 262313880f5bSKeith Busch 262413880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 262513880f5bSKeith Busch return ret ? ret : numvfs; 262613880f5bSKeith Busch } 262713880f5bSKeith Busch 262857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 262957dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 263057dacad5SJay Sternberg { 263157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 263257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 263357dacad5SJay Sternberg 2634a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 263557dacad5SJay Sternberg return 0; 263657dacad5SJay Sternberg } 263757dacad5SJay Sternberg 263857dacad5SJay Sternberg static int nvme_resume(struct device *dev) 263957dacad5SJay Sternberg { 264057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 264157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 264257dacad5SJay Sternberg 2643d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 264457dacad5SJay Sternberg return 0; 264557dacad5SJay Sternberg } 264657dacad5SJay Sternberg #endif 264757dacad5SJay Sternberg 264857dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 264957dacad5SJay Sternberg 2650a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2651a0a3408eSKeith Busch pci_channel_state_t state) 2652a0a3408eSKeith Busch { 2653a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2654a0a3408eSKeith Busch 2655a0a3408eSKeith Busch /* 2656a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2657a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2658a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2659a0a3408eSKeith Busch */ 2660a0a3408eSKeith Busch switch (state) { 2661a0a3408eSKeith Busch case pci_channel_io_normal: 2662a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2663a0a3408eSKeith Busch case pci_channel_io_frozen: 2664d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2665d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2666a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2667a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2668a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2669d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2670d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2671a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2672a0a3408eSKeith Busch } 2673a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2674a0a3408eSKeith Busch } 2675a0a3408eSKeith Busch 2676a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2677a0a3408eSKeith Busch { 2678a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2679a0a3408eSKeith Busch 26801b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2681a0a3408eSKeith Busch pci_restore_state(pdev); 2682d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2683a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2684a0a3408eSKeith Busch } 2685a0a3408eSKeith Busch 2686a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2687a0a3408eSKeith Busch { 2688a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2689a0a3408eSKeith Busch } 2690a0a3408eSKeith Busch 269157dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 269257dacad5SJay Sternberg .error_detected = nvme_error_detected, 269357dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 269457dacad5SJay Sternberg .resume = nvme_error_resume, 2695775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2696775755edSChristoph Hellwig .reset_done = nvme_reset_done, 269757dacad5SJay Sternberg }; 269857dacad5SJay Sternberg 269957dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2700106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 270108095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2702e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 270399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 270499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2705e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 270699466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 270799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2708e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2709f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2710f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2711f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 271250af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 27139abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 27149abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2715540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2716540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 271754adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 271854adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 27198c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 27208c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2721015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2722015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2723d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2724d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2725d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2726d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2727608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2728608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2729608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2730608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 273157dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2732c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2733124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 273457dacad5SJay Sternberg { 0, } 273557dacad5SJay Sternberg }; 273657dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 273757dacad5SJay Sternberg 273857dacad5SJay Sternberg static struct pci_driver nvme_driver = { 273957dacad5SJay Sternberg .name = "nvme", 274057dacad5SJay Sternberg .id_table = nvme_id_table, 274157dacad5SJay Sternberg .probe = nvme_probe, 274257dacad5SJay Sternberg .remove = nvme_remove, 274357dacad5SJay Sternberg .shutdown = nvme_shutdown, 274457dacad5SJay Sternberg .driver = { 274557dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 274657dacad5SJay Sternberg }, 274713880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 274857dacad5SJay Sternberg .err_handler = &nvme_err_handler, 274957dacad5SJay Sternberg }; 275057dacad5SJay Sternberg 275157dacad5SJay Sternberg static int __init nvme_init(void) 275257dacad5SJay Sternberg { 27539a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 275457dacad5SJay Sternberg } 275557dacad5SJay Sternberg 275657dacad5SJay Sternberg static void __exit nvme_exit(void) 275757dacad5SJay Sternberg { 275857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 275903e0f3a6SMing Lei flush_workqueue(nvme_wq); 276057dacad5SJay Sternberg _nvme_check_size(); 276157dacad5SJay Sternberg } 276257dacad5SJay Sternberg 276357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 276457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 276557dacad5SJay Sternberg MODULE_VERSION("1.0"); 276657dacad5SJay Sternberg module_init(nvme_init); 276757dacad5SJay Sternberg module_exit(nvme_exit); 2768