157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/blkdev.h> 1757dacad5SJay Sternberg #include <linux/blk-mq.h> 18dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 19ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2057dacad5SJay Sternberg #include <linux/init.h> 2157dacad5SJay Sternberg #include <linux/interrupt.h> 2257dacad5SJay Sternberg #include <linux/io.h> 2357dacad5SJay Sternberg #include <linux/mm.h> 2457dacad5SJay Sternberg #include <linux/module.h> 2577bf25eaSKeith Busch #include <linux/mutex.h> 26d0877473SKeith Busch #include <linux/once.h> 2757dacad5SJay Sternberg #include <linux/pci.h> 2857dacad5SJay Sternberg #include <linux/t10-pi.h> 2957dacad5SJay Sternberg #include <linux/types.h> 309cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 31a98e58e5SScott Bauer #include <linux/sed-opal.h> 3257dacad5SJay Sternberg 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3657dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 4057dacad5SJay Sternberg static int use_threaded_interrupts; 4157dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4257dacad5SJay Sternberg 4357dacad5SJay Sternberg static bool use_cmb_sqes = true; 4457dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 4557dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4657dacad5SJay Sternberg 4787ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 4887ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 4987ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5087ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5157dacad5SJay Sternberg 52a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 53a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 54a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 55a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 56a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 57a7a7cbe3SChaitanya Kulkarni 58b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 59b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 60b27c1e68Sweiping zhang .set = io_queue_depth_set, 61b27c1e68Sweiping zhang .get = param_get_int, 62b27c1e68Sweiping zhang }; 63b27c1e68Sweiping zhang 64b27c1e68Sweiping zhang static int io_queue_depth = 1024; 65b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 66b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 67b27c1e68Sweiping zhang 681c63dc66SChristoph Hellwig struct nvme_dev; 691c63dc66SChristoph Hellwig struct nvme_queue; 7057dacad5SJay Sternberg 71a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 72a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7357dacad5SJay Sternberg 7457dacad5SJay Sternberg /* 751c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 761c63dc66SChristoph Hellwig */ 771c63dc66SChristoph Hellwig struct nvme_dev { 78147b27e4SSagi Grimberg struct nvme_queue *queues; 791c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 811c63dc66SChristoph Hellwig u32 __iomem *dbs; 821c63dc66SChristoph Hellwig struct device *dev; 831c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 841c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 851c63dc66SChristoph Hellwig unsigned online_queues; 861c63dc66SChristoph Hellwig unsigned max_qid; 871c63dc66SChristoph Hellwig int q_depth; 881c63dc66SChristoph Hellwig u32 db_stride; 891c63dc66SChristoph Hellwig void __iomem *bar; 9097f6ef64SXu Yu unsigned long bar_mapped_size; 915c8809e6SChristoph Hellwig struct work_struct remove_work; 9277bf25eaSKeith Busch struct mutex shutdown_lock; 931c63dc66SChristoph Hellwig bool subsystem; 941c63dc66SChristoph Hellwig void __iomem *cmb; 958969f1f8SChristoph Hellwig pci_bus_addr_t cmb_bus_addr; 961c63dc66SChristoph Hellwig u64 cmb_size; 971c63dc66SChristoph Hellwig u32 cmbsz; 98202021c1SStephen Bates u32 cmbloc; 991c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 100db3cbfffSKeith Busch struct completion ioq_wait; 10187ad72a5SChristoph Hellwig 10287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 103f9f38e33SHelen Koike u32 *dbbuf_dbs; 104f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 105f9f38e33SHelen Koike u32 *dbbuf_eis; 106f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10787ad72a5SChristoph Hellwig 10887ad72a5SChristoph Hellwig /* host memory buffer support: */ 10987ad72a5SChristoph Hellwig u64 host_mem_size; 11087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1114033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 11287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11457dacad5SJay Sternberg }; 11557dacad5SJay Sternberg 116b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 117b27c1e68Sweiping zhang { 118b27c1e68Sweiping zhang int n = 0, ret; 119b27c1e68Sweiping zhang 120b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 121b27c1e68Sweiping zhang if (ret != 0 || n < 2) 122b27c1e68Sweiping zhang return -EINVAL; 123b27c1e68Sweiping zhang 124b27c1e68Sweiping zhang return param_set_int(val, kp); 125b27c1e68Sweiping zhang } 126b27c1e68Sweiping zhang 127f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 128f9f38e33SHelen Koike { 129f9f38e33SHelen Koike return qid * 2 * stride; 130f9f38e33SHelen Koike } 131f9f38e33SHelen Koike 132f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 133f9f38e33SHelen Koike { 134f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 135f9f38e33SHelen Koike } 136f9f38e33SHelen Koike 1371c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1381c63dc66SChristoph Hellwig { 1391c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1401c63dc66SChristoph Hellwig } 1411c63dc66SChristoph Hellwig 14257dacad5SJay Sternberg /* 14357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14457dacad5SJay Sternberg * commands and one for I/O commands). 14557dacad5SJay Sternberg */ 14657dacad5SJay Sternberg struct nvme_queue { 14757dacad5SJay Sternberg struct device *q_dmadev; 14857dacad5SJay Sternberg struct nvme_dev *dev; 14957dacad5SJay Sternberg spinlock_t q_lock; 15057dacad5SJay Sternberg struct nvme_command *sq_cmds; 15157dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15257dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15357dacad5SJay Sternberg struct blk_mq_tags **tags; 15457dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15557dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15657dacad5SJay Sternberg u32 __iomem *q_db; 15757dacad5SJay Sternberg u16 q_depth; 15857dacad5SJay Sternberg s16 cq_vector; 15957dacad5SJay Sternberg u16 sq_tail; 16057dacad5SJay Sternberg u16 cq_head; 16157dacad5SJay Sternberg u16 qid; 16257dacad5SJay Sternberg u8 cq_phase; 16357dacad5SJay Sternberg u8 cqe_seen; 164f9f38e33SHelen Koike u32 *dbbuf_sq_db; 165f9f38e33SHelen Koike u32 *dbbuf_cq_db; 166f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 167f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16857dacad5SJay Sternberg }; 16957dacad5SJay Sternberg 17057dacad5SJay Sternberg /* 17171bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17271bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 173f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17471bd150cSChristoph Hellwig * allocated to store the PRP list. 17571bd150cSChristoph Hellwig */ 17671bd150cSChristoph Hellwig struct nvme_iod { 177d49187e9SChristoph Hellwig struct nvme_request req; 178f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 179a7a7cbe3SChaitanya Kulkarni bool use_sgl; 180f4800d6dSChristoph Hellwig int aborted; 18171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18371bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18471bd150cSChristoph Hellwig dma_addr_t first_dma; 185bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 186f4800d6dSChristoph Hellwig struct scatterlist *sg; 187f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18857dacad5SJay Sternberg }; 18957dacad5SJay Sternberg 19057dacad5SJay Sternberg /* 19157dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19257dacad5SJay Sternberg */ 19357dacad5SJay Sternberg static inline void _nvme_check_size(void) 19457dacad5SJay Sternberg { 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2030add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2040add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 207f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 208f9f38e33SHelen Koike } 209f9f38e33SHelen Koike 210f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 211f9f38e33SHelen Koike { 212f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 213f9f38e33SHelen Koike } 214f9f38e33SHelen Koike 215f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 216f9f38e33SHelen Koike { 217f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 218f9f38e33SHelen Koike 219f9f38e33SHelen Koike if (dev->dbbuf_dbs) 220f9f38e33SHelen Koike return 0; 221f9f38e33SHelen Koike 222f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 223f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 224f9f38e33SHelen Koike GFP_KERNEL); 225f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 226f9f38e33SHelen Koike return -ENOMEM; 227f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 228f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 229f9f38e33SHelen Koike GFP_KERNEL); 230f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 231f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 232f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 233f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 234f9f38e33SHelen Koike return -ENOMEM; 235f9f38e33SHelen Koike } 236f9f38e33SHelen Koike 237f9f38e33SHelen Koike return 0; 238f9f38e33SHelen Koike } 239f9f38e33SHelen Koike 240f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 241f9f38e33SHelen Koike { 242f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 243f9f38e33SHelen Koike 244f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 245f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 246f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 247f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike if (dev->dbbuf_eis) { 250f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 251f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 252f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 253f9f38e33SHelen Koike } 254f9f38e33SHelen Koike } 255f9f38e33SHelen Koike 256f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 257f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 258f9f38e33SHelen Koike { 259f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 260f9f38e33SHelen Koike return; 261f9f38e33SHelen Koike 262f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 263f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike struct nvme_command c; 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 273f9f38e33SHelen Koike return; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 276f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 277f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 278f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 279f9f38e33SHelen Koike 280f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2819bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 282f9f38e33SHelen Koike /* Free memory and continue on */ 283f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 288f9f38e33SHelen Koike { 289f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 293f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 294f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 295f9f38e33SHelen Koike { 296f9f38e33SHelen Koike if (dbbuf_db) { 297f9f38e33SHelen Koike u16 old_value; 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike /* 300f9f38e33SHelen Koike * Ensure that the queue is written before updating 301f9f38e33SHelen Koike * the doorbell in memory 302f9f38e33SHelen Koike */ 303f9f38e33SHelen Koike wmb(); 304f9f38e33SHelen Koike 305f9f38e33SHelen Koike old_value = *dbbuf_db; 306f9f38e33SHelen Koike *dbbuf_db = value; 307f9f38e33SHelen Koike 308f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 309f9f38e33SHelen Koike return false; 310f9f38e33SHelen Koike } 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike return true; 31357dacad5SJay Sternberg } 31457dacad5SJay Sternberg 31557dacad5SJay Sternberg /* 31657dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31757dacad5SJay Sternberg */ 31857dacad5SJay Sternberg #define NVME_INT_PAGES 2 3195fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 32057dacad5SJay Sternberg 32157dacad5SJay Sternberg /* 32257dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32357dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32457dacad5SJay Sternberg * the I/O. 32557dacad5SJay Sternberg */ 32657dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32757dacad5SJay Sternberg { 3285fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3295fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 33057dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33157dacad5SJay Sternberg } 33257dacad5SJay Sternberg 333a7a7cbe3SChaitanya Kulkarni /* 334a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 335a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 336a7a7cbe3SChaitanya Kulkarni */ 337a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 338f4800d6dSChristoph Hellwig { 339a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 340f4800d6dSChristoph Hellwig } 341f4800d6dSChristoph Hellwig 342a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 343a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 34457dacad5SJay Sternberg { 345a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 346a7a7cbe3SChaitanya Kulkarni 347a7a7cbe3SChaitanya Kulkarni if (use_sgl) 348a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 349a7a7cbe3SChaitanya Kulkarni else 350a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 351a7a7cbe3SChaitanya Kulkarni 352a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 353a7a7cbe3SChaitanya Kulkarni } 354a7a7cbe3SChaitanya Kulkarni 355a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 356a7a7cbe3SChaitanya Kulkarni { 357a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 358a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 359a7a7cbe3SChaitanya Kulkarni use_sgl); 360a7a7cbe3SChaitanya Kulkarni 361a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 36257dacad5SJay Sternberg } 36357dacad5SJay Sternberg 36457dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36557dacad5SJay Sternberg unsigned int hctx_idx) 36657dacad5SJay Sternberg { 36757dacad5SJay Sternberg struct nvme_dev *dev = data; 368147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 36957dacad5SJay Sternberg 37057dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37157dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37257dacad5SJay Sternberg WARN_ON(nvmeq->tags); 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg hctx->driver_data = nvmeq; 37557dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 37657dacad5SJay Sternberg return 0; 37757dacad5SJay Sternberg } 37857dacad5SJay Sternberg 37957dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38057dacad5SJay Sternberg { 38157dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg nvmeq->tags = NULL; 38457dacad5SJay Sternberg } 38557dacad5SJay Sternberg 38657dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38757dacad5SJay Sternberg unsigned int hctx_idx) 38857dacad5SJay Sternberg { 38957dacad5SJay Sternberg struct nvme_dev *dev = data; 390147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39157dacad5SJay Sternberg 39257dacad5SJay Sternberg if (!nvmeq->tags) 39357dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 39457dacad5SJay Sternberg 39557dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39657dacad5SJay Sternberg hctx->driver_data = nvmeq; 39757dacad5SJay Sternberg return 0; 39857dacad5SJay Sternberg } 39957dacad5SJay Sternberg 400d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 401d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40257dacad5SJay Sternberg { 403d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 404f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4050350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 406147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg BUG_ON(!nvmeq); 409f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41057dacad5SJay Sternberg return 0; 41157dacad5SJay Sternberg } 41257dacad5SJay Sternberg 413dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 414dca51e78SChristoph Hellwig { 415dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 416dca51e78SChristoph Hellwig 417dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 418dca51e78SChristoph Hellwig } 419dca51e78SChristoph Hellwig 42057dacad5SJay Sternberg /** 421adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 42257dacad5SJay Sternberg * @nvmeq: The queue to use 42357dacad5SJay Sternberg * @cmd: The command to send 42457dacad5SJay Sternberg * 42557dacad5SJay Sternberg * Safe to use from interrupt context 42657dacad5SJay Sternberg */ 42757dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 42857dacad5SJay Sternberg struct nvme_command *cmd) 42957dacad5SJay Sternberg { 43057dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 43157dacad5SJay Sternberg 43257dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 43357dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 43457dacad5SJay Sternberg else 43557dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 43857dacad5SJay Sternberg tail = 0; 439f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 440f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 44157dacad5SJay Sternberg writel(tail, nvmeq->q_db); 44257dacad5SJay Sternberg nvmeq->sq_tail = tail; 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 445a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 44657dacad5SJay Sternberg { 447f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 448a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 44957dacad5SJay Sternberg } 45057dacad5SJay Sternberg 451955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 452955b1b5aSMinwoo Im { 453955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 45420469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 455955b1b5aSMinwoo Im unsigned int avg_seg_size; 456955b1b5aSMinwoo Im 45720469a37SKeith Busch if (nseg == 0) 45820469a37SKeith Busch return false; 45920469a37SKeith Busch 46020469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 461955b1b5aSMinwoo Im 462955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 463955b1b5aSMinwoo Im return false; 464955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 465955b1b5aSMinwoo Im return false; 466955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 467955b1b5aSMinwoo Im return false; 468955b1b5aSMinwoo Im return true; 469955b1b5aSMinwoo Im } 470955b1b5aSMinwoo Im 471fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 47257dacad5SJay Sternberg { 473f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 474f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 475b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 476f4800d6dSChristoph Hellwig 477955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 478955b1b5aSMinwoo Im 479f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 480a7a7cbe3SChaitanya Kulkarni size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, 481a7a7cbe3SChaitanya Kulkarni iod->use_sgl); 482a7a7cbe3SChaitanya Kulkarni 483a7a7cbe3SChaitanya Kulkarni iod->sg = kmalloc(alloc_size, GFP_ATOMIC); 484f4800d6dSChristoph Hellwig if (!iod->sg) 485fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 486f4800d6dSChristoph Hellwig } else { 487f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 48857dacad5SJay Sternberg } 48957dacad5SJay Sternberg 490f4800d6dSChristoph Hellwig iod->aborted = 0; 49157dacad5SJay Sternberg iod->npages = -1; 49257dacad5SJay Sternberg iod->nents = 0; 493f4800d6dSChristoph Hellwig iod->length = size; 494f80ec966SKeith Busch 495fc17b653SChristoph Hellwig return BLK_STS_OK; 49657dacad5SJay Sternberg } 49757dacad5SJay Sternberg 498f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 49957dacad5SJay Sternberg { 500f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 501a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 502a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 503a7a7cbe3SChaitanya Kulkarni 50457dacad5SJay Sternberg int i; 50557dacad5SJay Sternberg 50657dacad5SJay Sternberg if (iod->npages == 0) 507a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 508a7a7cbe3SChaitanya Kulkarni dma_addr); 509a7a7cbe3SChaitanya Kulkarni 51057dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 511a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 512a7a7cbe3SChaitanya Kulkarni 513a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 514a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 515a7a7cbe3SChaitanya Kulkarni 516a7a7cbe3SChaitanya Kulkarni next_dma_addr = 517a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 518a7a7cbe3SChaitanya Kulkarni } else { 519a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 520a7a7cbe3SChaitanya Kulkarni 521a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 522a7a7cbe3SChaitanya Kulkarni } 523a7a7cbe3SChaitanya Kulkarni 524a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 525a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 52657dacad5SJay Sternberg } 52757dacad5SJay Sternberg 528f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 529f4800d6dSChristoph Hellwig kfree(iod->sg); 53057dacad5SJay Sternberg } 53157dacad5SJay Sternberg 53257dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 53357dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 53457dacad5SJay Sternberg { 53557dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 53657dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 53757dacad5SJay Sternberg } 53857dacad5SJay Sternberg 53957dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54057dacad5SJay Sternberg { 54157dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 54257dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 54357dacad5SJay Sternberg } 54457dacad5SJay Sternberg 54557dacad5SJay Sternberg /** 54657dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 54757dacad5SJay Sternberg * 54857dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 54957dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 55057dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 55157dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 55257dacad5SJay Sternberg * 55357dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 55457dacad5SJay Sternberg */ 55557dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 55657dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 55757dacad5SJay Sternberg { 55857dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 55957dacad5SJay Sternberg struct bio_integrity_payload *bip; 56057dacad5SJay Sternberg struct t10_pi_tuple *pi; 56157dacad5SJay Sternberg void *p, *pmap; 56257dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 56357dacad5SJay Sternberg 56457dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 56557dacad5SJay Sternberg return; 56657dacad5SJay Sternberg 56757dacad5SJay Sternberg bip = bio_integrity(req->bio); 56857dacad5SJay Sternberg if (!bip) 56957dacad5SJay Sternberg return; 57057dacad5SJay Sternberg 57157dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 57257dacad5SJay Sternberg 57357dacad5SJay Sternberg p = pmap; 57457dacad5SJay Sternberg virt = bip_get_seed(bip); 57557dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 57657dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 577ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 57857dacad5SJay Sternberg 57957dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 58057dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 58157dacad5SJay Sternberg dif_swap(phys, virt, pi); 58257dacad5SJay Sternberg p += ts; 58357dacad5SJay Sternberg } 58457dacad5SJay Sternberg kunmap_atomic(pmap); 58557dacad5SJay Sternberg } 58657dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 58757dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 58857dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 58957dacad5SJay Sternberg { 59057dacad5SJay Sternberg } 59157dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 59257dacad5SJay Sternberg { 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 59557dacad5SJay Sternberg { 59657dacad5SJay Sternberg } 59757dacad5SJay Sternberg #endif 59857dacad5SJay Sternberg 599d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 600d0877473SKeith Busch { 601d0877473SKeith Busch int i; 602d0877473SKeith Busch struct scatterlist *sg; 603d0877473SKeith Busch 604d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 605d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 606d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 607d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 608d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 609d0877473SKeith Busch sg_dma_len(sg)); 610d0877473SKeith Busch } 611d0877473SKeith Busch } 612d0877473SKeith Busch 613a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 614a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 61557dacad5SJay Sternberg { 616f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 61757dacad5SJay Sternberg struct dma_pool *pool; 618b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61957dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 62057dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 62157dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6225fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 62357dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 62457dacad5SJay Sternberg __le64 *prp_list; 625a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 62657dacad5SJay Sternberg dma_addr_t prp_dma; 62757dacad5SJay Sternberg int nprps, i; 62857dacad5SJay Sternberg 62957dacad5SJay Sternberg length -= (page_size - offset); 6305228b328SJan H. Schönherr if (length <= 0) { 6315228b328SJan H. Schönherr iod->first_dma = 0; 632a7a7cbe3SChaitanya Kulkarni goto done; 6335228b328SJan H. Schönherr } 63457dacad5SJay Sternberg 63557dacad5SJay Sternberg dma_len -= (page_size - offset); 63657dacad5SJay Sternberg if (dma_len) { 63757dacad5SJay Sternberg dma_addr += (page_size - offset); 63857dacad5SJay Sternberg } else { 63957dacad5SJay Sternberg sg = sg_next(sg); 64057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 64157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 64257dacad5SJay Sternberg } 64357dacad5SJay Sternberg 64457dacad5SJay Sternberg if (length <= page_size) { 64557dacad5SJay Sternberg iod->first_dma = dma_addr; 646a7a7cbe3SChaitanya Kulkarni goto done; 64757dacad5SJay Sternberg } 64857dacad5SJay Sternberg 64957dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 65057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 65157dacad5SJay Sternberg pool = dev->prp_small_pool; 65257dacad5SJay Sternberg iod->npages = 0; 65357dacad5SJay Sternberg } else { 65457dacad5SJay Sternberg pool = dev->prp_page_pool; 65557dacad5SJay Sternberg iod->npages = 1; 65657dacad5SJay Sternberg } 65757dacad5SJay Sternberg 65869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65957dacad5SJay Sternberg if (!prp_list) { 66057dacad5SJay Sternberg iod->first_dma = dma_addr; 66157dacad5SJay Sternberg iod->npages = -1; 66286eea289SKeith Busch return BLK_STS_RESOURCE; 66357dacad5SJay Sternberg } 66457dacad5SJay Sternberg list[0] = prp_list; 66557dacad5SJay Sternberg iod->first_dma = prp_dma; 66657dacad5SJay Sternberg i = 0; 66757dacad5SJay Sternberg for (;;) { 66857dacad5SJay Sternberg if (i == page_size >> 3) { 66957dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 67069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67157dacad5SJay Sternberg if (!prp_list) 67286eea289SKeith Busch return BLK_STS_RESOURCE; 67357dacad5SJay Sternberg list[iod->npages++] = prp_list; 67457dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 67557dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 67657dacad5SJay Sternberg i = 1; 67757dacad5SJay Sternberg } 67857dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 67957dacad5SJay Sternberg dma_len -= page_size; 68057dacad5SJay Sternberg dma_addr += page_size; 68157dacad5SJay Sternberg length -= page_size; 68257dacad5SJay Sternberg if (length <= 0) 68357dacad5SJay Sternberg break; 68457dacad5SJay Sternberg if (dma_len > 0) 68557dacad5SJay Sternberg continue; 68686eea289SKeith Busch if (unlikely(dma_len < 0)) 68786eea289SKeith Busch goto bad_sgl; 68857dacad5SJay Sternberg sg = sg_next(sg); 68957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69157dacad5SJay Sternberg } 69257dacad5SJay Sternberg 693a7a7cbe3SChaitanya Kulkarni done: 694a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 695a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 696a7a7cbe3SChaitanya Kulkarni 69786eea289SKeith Busch return BLK_STS_OK; 69886eea289SKeith Busch 69986eea289SKeith Busch bad_sgl: 700d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 701d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 702d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 70386eea289SKeith Busch return BLK_STS_IOERR; 70457dacad5SJay Sternberg } 70557dacad5SJay Sternberg 706a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 707a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 708a7a7cbe3SChaitanya Kulkarni { 709a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 710a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 711a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 712a7a7cbe3SChaitanya Kulkarni } 713a7a7cbe3SChaitanya Kulkarni 714a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 715a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 716a7a7cbe3SChaitanya Kulkarni { 717a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 718a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 719a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 720a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 721a7a7cbe3SChaitanya Kulkarni } else { 722a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 723a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 724a7a7cbe3SChaitanya Kulkarni } 725a7a7cbe3SChaitanya Kulkarni } 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 728b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 729a7a7cbe3SChaitanya Kulkarni { 730a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 731a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 732a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 733a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 734a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 735b0f2853bSChristoph Hellwig int i = 0; 736a7a7cbe3SChaitanya Kulkarni 737a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 738a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 739a7a7cbe3SChaitanya Kulkarni 740b0f2853bSChristoph Hellwig if (entries == 1) { 741a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 742a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 743a7a7cbe3SChaitanya Kulkarni } 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 746a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 747a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 748a7a7cbe3SChaitanya Kulkarni } else { 749a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 750a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 751a7a7cbe3SChaitanya Kulkarni } 752a7a7cbe3SChaitanya Kulkarni 753a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 754a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 755a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 756a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 757a7a7cbe3SChaitanya Kulkarni } 758a7a7cbe3SChaitanya Kulkarni 759a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 760a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni do { 765a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 766a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 767a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 768a7a7cbe3SChaitanya Kulkarni 769a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 770a7a7cbe3SChaitanya Kulkarni if (!sg_list) 771a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni i = 0; 774a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 775a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 776a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 780a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 781b0f2853bSChristoph Hellwig } while (--entries > 0); 782a7a7cbe3SChaitanya Kulkarni 783a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 784a7a7cbe3SChaitanya Kulkarni } 785a7a7cbe3SChaitanya Kulkarni 786fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 787b131c61dSChristoph Hellwig struct nvme_command *cmnd) 78857dacad5SJay Sternberg { 789f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 790ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 791ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 792ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 793fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 794b0f2853bSChristoph Hellwig int nr_mapped; 79557dacad5SJay Sternberg 796f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 797ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 798ba1ca37eSChristoph Hellwig if (!iod->nents) 799ba1ca37eSChristoph Hellwig goto out; 800ba1ca37eSChristoph Hellwig 801fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 802b0f2853bSChristoph Hellwig nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 803b0f2853bSChristoph Hellwig DMA_ATTR_NO_WARN); 804b0f2853bSChristoph Hellwig if (!nr_mapped) 805ba1ca37eSChristoph Hellwig goto out; 806ba1ca37eSChristoph Hellwig 807955b1b5aSMinwoo Im if (iod->use_sgl) 808b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 809a7a7cbe3SChaitanya Kulkarni else 810a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 811a7a7cbe3SChaitanya Kulkarni 81286eea289SKeith Busch if (ret != BLK_STS_OK) 813ba1ca37eSChristoph Hellwig goto out_unmap; 814ba1ca37eSChristoph Hellwig 815fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 816ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 817ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 818ba1ca37eSChristoph Hellwig goto out_unmap; 819ba1ca37eSChristoph Hellwig 820bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 821bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 822ba1ca37eSChristoph Hellwig goto out_unmap; 823ba1ca37eSChristoph Hellwig 824b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 825ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 826ba1ca37eSChristoph Hellwig 827bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 828ba1ca37eSChristoph Hellwig goto out_unmap; 82957dacad5SJay Sternberg } 83057dacad5SJay Sternberg 831ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 832bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 833fc17b653SChristoph Hellwig return BLK_STS_OK; 834ba1ca37eSChristoph Hellwig 835ba1ca37eSChristoph Hellwig out_unmap: 836ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 837ba1ca37eSChristoph Hellwig out: 838ba1ca37eSChristoph Hellwig return ret; 83957dacad5SJay Sternberg } 84057dacad5SJay Sternberg 841f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 842d4f6c3abSChristoph Hellwig { 843f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 844d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 845d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 846d4f6c3abSChristoph Hellwig 847d4f6c3abSChristoph Hellwig if (iod->nents) { 848d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 849d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 850b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 851d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 852bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 853d4f6c3abSChristoph Hellwig } 854d4f6c3abSChristoph Hellwig } 855d4f6c3abSChristoph Hellwig 856f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 857f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 85857dacad5SJay Sternberg } 85957dacad5SJay Sternberg 86057dacad5SJay Sternberg /* 86157dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86257dacad5SJay Sternberg */ 863fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86457dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86557dacad5SJay Sternberg { 86657dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 86757dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 86857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 86957dacad5SJay Sternberg struct request *req = bd->rq; 870ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 871ebe6d874SChristoph Hellwig blk_status_t ret; 87257dacad5SJay Sternberg 873f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 874fc17b653SChristoph Hellwig if (ret) 875f4800d6dSChristoph Hellwig return ret; 87657dacad5SJay Sternberg 877b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 878fc17b653SChristoph Hellwig if (ret) 879f9d03f96SChristoph Hellwig goto out_free_cmd; 88057dacad5SJay Sternberg 881fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 882b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 883fc17b653SChristoph Hellwig if (ret) 884f9d03f96SChristoph Hellwig goto out_cleanup_iod; 885fc17b653SChristoph Hellwig } 886ba1ca37eSChristoph Hellwig 887aae239e1SChristoph Hellwig blk_mq_start_request(req); 888ba1ca37eSChristoph Hellwig 889ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 890ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 891fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 892ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 893f9d03f96SChristoph Hellwig goto out_cleanup_iod; 894ae1fba20SKeith Busch } 895ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 89657dacad5SJay Sternberg nvme_process_cq(nvmeq); 89757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 898fc17b653SChristoph Hellwig return BLK_STS_OK; 899f9d03f96SChristoph Hellwig out_cleanup_iod: 900f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 901f9d03f96SChristoph Hellwig out_free_cmd: 902f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 903ba1ca37eSChristoph Hellwig return ret; 90457dacad5SJay Sternberg } 90557dacad5SJay Sternberg 90677f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 907eee417b0SChristoph Hellwig { 908f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 909eee417b0SChristoph Hellwig 91077f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 91177f02a7aSChristoph Hellwig nvme_complete_rq(req); 91257dacad5SJay Sternberg } 91357dacad5SJay Sternberg 914d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 915d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 916d783e0bdSMarta Rybczynska u16 phase) 917d783e0bdSMarta Rybczynska { 918d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 919d783e0bdSMarta Rybczynska } 920d783e0bdSMarta Rybczynska 921eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92257dacad5SJay Sternberg { 923eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92457dacad5SJay Sternberg 925eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 926eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 927eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 928eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 929eb281c82SSagi Grimberg } 93057dacad5SJay Sternberg } 931adf68f21SChristoph Hellwig 93283a12fb7SSagi Grimberg static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 93383a12fb7SSagi Grimberg struct nvme_completion *cqe) 93457dacad5SJay Sternberg { 93557dacad5SJay Sternberg struct request *req; 936adf68f21SChristoph Hellwig 93783a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9381b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 939aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94083a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94183a12fb7SSagi Grimberg return; 942aae239e1SChristoph Hellwig } 943aae239e1SChristoph Hellwig 944adf68f21SChristoph Hellwig /* 945adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 946adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 947adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 948adf68f21SChristoph Hellwig * for them but rather special case them here. 949adf68f21SChristoph Hellwig */ 950adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 95138dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9527bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95383a12fb7SSagi Grimberg cqe->status, &cqe->result); 954a0fa9647SJens Axboe return; 95557dacad5SJay Sternberg } 95657dacad5SJay Sternberg 957e9d8a0fdSKeith Busch nvmeq->cqe_seen = 1; 95883a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 95983a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 96083a12fb7SSagi Grimberg } 96157dacad5SJay Sternberg 962920d13a8SSagi Grimberg static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, 963920d13a8SSagi Grimberg struct nvme_completion *cqe) 96483a12fb7SSagi Grimberg { 965920d13a8SSagi Grimberg if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 966920d13a8SSagi Grimberg *cqe = nvmeq->cqes[nvmeq->cq_head]; 96783a12fb7SSagi Grimberg 968920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 969920d13a8SSagi Grimberg nvmeq->cq_head = 0; 970920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 971920d13a8SSagi Grimberg } 972920d13a8SSagi Grimberg return true; 973920d13a8SSagi Grimberg } 974920d13a8SSagi Grimberg return false; 975a0fa9647SJens Axboe } 976a0fa9647SJens Axboe 977a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 978a0fa9647SJens Axboe { 979920d13a8SSagi Grimberg struct nvme_completion cqe; 980920d13a8SSagi Grimberg int consumed = 0; 98183a12fb7SSagi Grimberg 982920d13a8SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 98383a12fb7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 984920d13a8SSagi Grimberg consumed++; 98557dacad5SJay Sternberg } 98657dacad5SJay Sternberg 987e9d8a0fdSKeith Busch if (consumed) 988eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 98957dacad5SJay Sternberg } 99057dacad5SJay Sternberg 99157dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 99257dacad5SJay Sternberg { 99357dacad5SJay Sternberg irqreturn_t result; 99457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 99557dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 99657dacad5SJay Sternberg nvme_process_cq(nvmeq); 99757dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 99857dacad5SJay Sternberg nvmeq->cqe_seen = 0; 99957dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 100057dacad5SJay Sternberg return result; 100157dacad5SJay Sternberg } 100257dacad5SJay Sternberg 100357dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 100457dacad5SJay Sternberg { 100557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1006d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 100757dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1008d783e0bdSMarta Rybczynska return IRQ_NONE; 100957dacad5SJay Sternberg } 101057dacad5SJay Sternberg 10117776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1012a0fa9647SJens Axboe { 1013442e19b7SSagi Grimberg struct nvme_completion cqe; 1014442e19b7SSagi Grimberg int found = 0, consumed = 0; 1015a0fa9647SJens Axboe 1016442e19b7SSagi Grimberg if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 1017442e19b7SSagi Grimberg return 0; 1018442e19b7SSagi Grimberg 1019442e19b7SSagi Grimberg spin_lock_irq(&nvmeq->q_lock); 1020442e19b7SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 1021442e19b7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 1022442e19b7SSagi Grimberg consumed++; 1023442e19b7SSagi Grimberg 1024442e19b7SSagi Grimberg if (tag == cqe.command_id) { 1025442e19b7SSagi Grimberg found = 1; 1026442e19b7SSagi Grimberg break; 1027442e19b7SSagi Grimberg } 1028a0fa9647SJens Axboe } 1029a0fa9647SJens Axboe 1030442e19b7SSagi Grimberg if (consumed) 1031442e19b7SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 1032442e19b7SSagi Grimberg spin_unlock_irq(&nvmeq->q_lock); 1033442e19b7SSagi Grimberg 1034442e19b7SSagi Grimberg return found; 1035a0fa9647SJens Axboe } 1036a0fa9647SJens Axboe 10377776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10387776db1cSKeith Busch { 10397776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10407776db1cSKeith Busch 10417776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10427776db1cSKeith Busch } 10437776db1cSKeith Busch 1044ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 104557dacad5SJay Sternberg { 1046f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1047147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 104857dacad5SJay Sternberg struct nvme_command c; 104957dacad5SJay Sternberg 105057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105157dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1052ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 105357dacad5SJay Sternberg 10549396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 10559396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 10569396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 105757dacad5SJay Sternberg } 105857dacad5SJay Sternberg 105957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106057dacad5SJay Sternberg { 106157dacad5SJay Sternberg struct nvme_command c; 106257dacad5SJay Sternberg 106357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106457dacad5SJay Sternberg c.delete_queue.opcode = opcode; 106557dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 106657dacad5SJay Sternberg 10671c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 106857dacad5SJay Sternberg } 106957dacad5SJay Sternberg 107057dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 107157dacad5SJay Sternberg struct nvme_queue *nvmeq) 107257dacad5SJay Sternberg { 107357dacad5SJay Sternberg struct nvme_command c; 107457dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 107557dacad5SJay Sternberg 107657dacad5SJay Sternberg /* 107716772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 107857dacad5SJay Sternberg * is attached to the request. 107957dacad5SJay Sternberg */ 108057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108157dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 108257dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 108357dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 108457dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 108557dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 108657dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 108757dacad5SJay Sternberg 10881c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 108957dacad5SJay Sternberg } 109057dacad5SJay Sternberg 109157dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 109257dacad5SJay Sternberg struct nvme_queue *nvmeq) 109357dacad5SJay Sternberg { 109457dacad5SJay Sternberg struct nvme_command c; 109581c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 109657dacad5SJay Sternberg 109757dacad5SJay Sternberg /* 109816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 109957dacad5SJay Sternberg * is attached to the request. 110057dacad5SJay Sternberg */ 110157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110257dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 110357dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 110457dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 110557dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 110657dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 110757dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 110857dacad5SJay Sternberg 11091c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 111057dacad5SJay Sternberg } 111157dacad5SJay Sternberg 111257dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 111357dacad5SJay Sternberg { 111457dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 111557dacad5SJay Sternberg } 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 111857dacad5SJay Sternberg { 111957dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 112057dacad5SJay Sternberg } 112157dacad5SJay Sternberg 11222a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 112357dacad5SJay Sternberg { 1124f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1125f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 112657dacad5SJay Sternberg 112727fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 112827fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1129e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1130e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 113157dacad5SJay Sternberg } 113257dacad5SJay Sternberg 1133b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1134b2a0eb1aSKeith Busch { 1135b2a0eb1aSKeith Busch 1136b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1137b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1138b2a0eb1aSKeith Busch */ 1139b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1140b2a0eb1aSKeith Busch 1141ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1142ad70062cSJianchao Wang switch (dev->ctrl.state) { 1143ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1144ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1145b2a0eb1aSKeith Busch return false; 1146ad70062cSJianchao Wang default: 1147ad70062cSJianchao Wang break; 1148ad70062cSJianchao Wang } 1149b2a0eb1aSKeith Busch 1150b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1151b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1152b2a0eb1aSKeith Busch */ 1153b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1154b2a0eb1aSKeith Busch return false; 1155b2a0eb1aSKeith Busch 1156b2a0eb1aSKeith Busch /* If PCI error recovery process is happening, we cannot reset or 1157b2a0eb1aSKeith Busch * the recovery mechanism will surely fail. 1158b2a0eb1aSKeith Busch */ 1159b2a0eb1aSKeith Busch if (pci_channel_offline(to_pci_dev(dev->dev))) 1160b2a0eb1aSKeith Busch return false; 1161b2a0eb1aSKeith Busch 1162b2a0eb1aSKeith Busch return true; 1163b2a0eb1aSKeith Busch } 1164b2a0eb1aSKeith Busch 1165b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1166b2a0eb1aSKeith Busch { 1167b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1168b2a0eb1aSKeith Busch u16 pci_status; 1169b2a0eb1aSKeith Busch int result; 1170b2a0eb1aSKeith Busch 1171b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1172b2a0eb1aSKeith Busch &pci_status); 1173b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1174b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1175b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1176b2a0eb1aSKeith Busch csts, pci_status); 1177b2a0eb1aSKeith Busch else 1178b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1179b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1180b2a0eb1aSKeith Busch csts, result); 1181b2a0eb1aSKeith Busch } 1182b2a0eb1aSKeith Busch 118331c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 118457dacad5SJay Sternberg { 1185f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1186f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 118757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 118857dacad5SJay Sternberg struct request *abort_req; 118957dacad5SJay Sternberg struct nvme_command cmd; 1190b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1191b2a0eb1aSKeith Busch 1192b2a0eb1aSKeith Busch /* 1193b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1194b2a0eb1aSKeith Busch */ 1195b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1196b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1197b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1198d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1199b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1200b2a0eb1aSKeith Busch } 120157dacad5SJay Sternberg 120231c7c7d2SChristoph Hellwig /* 12037776db1cSKeith Busch * Did we miss an interrupt? 12047776db1cSKeith Busch */ 12057776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12067776db1cSKeith Busch dev_warn(dev->ctrl.device, 12077776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12087776db1cSKeith Busch req->tag, nvmeq->qid); 12097776db1cSKeith Busch return BLK_EH_HANDLED; 12107776db1cSKeith Busch } 12117776db1cSKeith Busch 12127776db1cSKeith Busch /* 1213fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1214fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1215fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1216fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1217fd634f41SChristoph Hellwig */ 12184244140dSKeith Busch switch (dev->ctrl.state) { 12194244140dSKeith Busch case NVME_CTRL_CONNECTING: 12204244140dSKeith Busch case NVME_CTRL_RESETTING: 12211b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1222fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1223fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1224a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 122527fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1226fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 12274244140dSKeith Busch default: 12284244140dSKeith Busch break; 1229fd634f41SChristoph Hellwig } 1230fd634f41SChristoph Hellwig 1231fd634f41SChristoph Hellwig /* 1232e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1233e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1234e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 123531c7c7d2SChristoph Hellwig */ 1236f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12371b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 123857dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 123957dacad5SJay Sternberg req->tag, nvmeq->qid); 1240a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1241d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1242e1569a16SKeith Busch 1243e1569a16SKeith Busch /* 1244e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1245e1569a16SKeith Busch * forces all outstanding requests to complete. 1246e1569a16SKeith Busch */ 124727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1248e1569a16SKeith Busch return BLK_EH_HANDLED; 124957dacad5SJay Sternberg } 125057dacad5SJay Sternberg 1251e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1252e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1253e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1254e7a2a87dSChristoph Hellwig } 12557bf7d778SKeith Busch iod->aborted = 1; 125657dacad5SJay Sternberg 125757dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 125857dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 125957dacad5SJay Sternberg cmd.abort.cid = req->tag; 126057dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 126157dacad5SJay Sternberg 12621b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12631b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 126457dacad5SJay Sternberg req->tag, nvmeq->qid); 1265e7a2a87dSChristoph Hellwig 1266e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1267eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12686bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12696bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 127031c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 127157dacad5SJay Sternberg } 127257dacad5SJay Sternberg 1273e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1274e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1275e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 127657dacad5SJay Sternberg 127757dacad5SJay Sternberg /* 127857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 127957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 128057dacad5SJay Sternberg * as the device then is in a faulty state. 128157dacad5SJay Sternberg */ 128257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 128357dacad5SJay Sternberg } 128457dacad5SJay Sternberg 128557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 128657dacad5SJay Sternberg { 128757dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 128857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 128957dacad5SJay Sternberg if (nvmeq->sq_cmds) 129057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 129157dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 129257dacad5SJay Sternberg } 129357dacad5SJay Sternberg 129457dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 129557dacad5SJay Sternberg { 129657dacad5SJay Sternberg int i; 129757dacad5SJay Sternberg 1298d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1299d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1300147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 130157dacad5SJay Sternberg } 130257dacad5SJay Sternberg } 130357dacad5SJay Sternberg 130457dacad5SJay Sternberg /** 130557dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 130657dacad5SJay Sternberg * @nvmeq - queue to suspend 130757dacad5SJay Sternberg */ 130857dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 130957dacad5SJay Sternberg { 131057dacad5SJay Sternberg int vector; 131157dacad5SJay Sternberg 131257dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 131357dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 131457dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 131557dacad5SJay Sternberg return 1; 131657dacad5SJay Sternberg } 13170ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 131857dacad5SJay Sternberg nvmeq->dev->online_queues--; 131957dacad5SJay Sternberg nvmeq->cq_vector = -1; 132057dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 132157dacad5SJay Sternberg 13221c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1323c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 132457dacad5SJay Sternberg 13250ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 132657dacad5SJay Sternberg 132757dacad5SJay Sternberg return 0; 132857dacad5SJay Sternberg } 132957dacad5SJay Sternberg 1330a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 133157dacad5SJay Sternberg { 1332147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 133357dacad5SJay Sternberg 1334a5cdb68cSKeith Busch if (shutdown) 1335a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1336a5cdb68cSKeith Busch else 133720d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 133857dacad5SJay Sternberg 133957dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 134057dacad5SJay Sternberg nvme_process_cq(nvmeq); 134157dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 134257dacad5SJay Sternberg } 134357dacad5SJay Sternberg 134457dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 134557dacad5SJay Sternberg int entry_size) 134657dacad5SJay Sternberg { 134757dacad5SJay Sternberg int q_depth = dev->q_depth; 13485fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13495fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 135057dacad5SJay Sternberg 135157dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 135257dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13535fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 135457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 135557dacad5SJay Sternberg 135657dacad5SJay Sternberg /* 135757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 135857dacad5SJay Sternberg * would be better to map queues in system memory with the 135957dacad5SJay Sternberg * original depth 136057dacad5SJay Sternberg */ 136157dacad5SJay Sternberg if (q_depth < 64) 136257dacad5SJay Sternberg return -ENOMEM; 136357dacad5SJay Sternberg } 136457dacad5SJay Sternberg 136557dacad5SJay Sternberg return q_depth; 136657dacad5SJay Sternberg } 136757dacad5SJay Sternberg 136857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 136957dacad5SJay Sternberg int qid, int depth) 137057dacad5SJay Sternberg { 1371815c6704SKeith Busch /* CMB SQEs will be mapped before creation */ 1372815c6704SKeith Busch if (qid && dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) 1373815c6704SKeith Busch return 0; 1374815c6704SKeith Busch 137557dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 137657dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 137757dacad5SJay Sternberg if (!nvmeq->sq_cmds) 137857dacad5SJay Sternberg return -ENOMEM; 137957dacad5SJay Sternberg return 0; 138057dacad5SJay Sternberg } 138157dacad5SJay Sternberg 1382147b27e4SSagi Grimberg static int nvme_alloc_queue(struct nvme_dev *dev, int qid, 1383d3af3ecdSShaohua Li int depth, int node) 138457dacad5SJay Sternberg { 1385147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 138657dacad5SJay Sternberg 138762314e40SKeith Busch if (dev->ctrl.queue_count > qid) 138862314e40SKeith Busch return 0; 138957dacad5SJay Sternberg 139057dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 139157dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 139257dacad5SJay Sternberg if (!nvmeq->cqes) 139357dacad5SJay Sternberg goto free_nvmeq; 139457dacad5SJay Sternberg 139557dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 139657dacad5SJay Sternberg goto free_cqdma; 139757dacad5SJay Sternberg 139857dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 139957dacad5SJay Sternberg nvmeq->dev = dev; 140057dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 140157dacad5SJay Sternberg nvmeq->cq_head = 0; 140257dacad5SJay Sternberg nvmeq->cq_phase = 1; 140357dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 140457dacad5SJay Sternberg nvmeq->q_depth = depth; 140557dacad5SJay Sternberg nvmeq->qid = qid; 140657dacad5SJay Sternberg nvmeq->cq_vector = -1; 1407d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 140857dacad5SJay Sternberg 1409147b27e4SSagi Grimberg return 0; 141057dacad5SJay Sternberg 141157dacad5SJay Sternberg free_cqdma: 141257dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 141357dacad5SJay Sternberg nvmeq->cq_dma_addr); 141457dacad5SJay Sternberg free_nvmeq: 1415147b27e4SSagi Grimberg return -ENOMEM; 141657dacad5SJay Sternberg } 141757dacad5SJay Sternberg 1418dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 141957dacad5SJay Sternberg { 14200ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14210ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14220ff199cbSChristoph Hellwig 14230ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14240ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14250ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14260ff199cbSChristoph Hellwig } else { 14270ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14280ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14290ff199cbSChristoph Hellwig } 143057dacad5SJay Sternberg } 143157dacad5SJay Sternberg 143257dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 143357dacad5SJay Sternberg { 143457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 143557dacad5SJay Sternberg 143657dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 143757dacad5SJay Sternberg nvmeq->sq_tail = 0; 143857dacad5SJay Sternberg nvmeq->cq_head = 0; 143957dacad5SJay Sternberg nvmeq->cq_phase = 1; 144057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 144157dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1442f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 144357dacad5SJay Sternberg dev->online_queues++; 144457dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 144557dacad5SJay Sternberg } 144657dacad5SJay Sternberg 144757dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 144857dacad5SJay Sternberg { 144957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 145057dacad5SJay Sternberg int result; 145157dacad5SJay Sternberg 1452815c6704SKeith Busch if (dev->cmb && use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 1453815c6704SKeith Busch unsigned offset = (qid - 1) * roundup(SQ_SIZE(nvmeq->q_depth), 1454815c6704SKeith Busch dev->ctrl.page_size); 1455815c6704SKeith Busch nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 1456815c6704SKeith Busch nvmeq->sq_cmds_io = dev->cmb + offset; 1457815c6704SKeith Busch } 1458815c6704SKeith Busch 145957dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 146057dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 146157dacad5SJay Sternberg if (result < 0) 1462f25a2dfcSJianchao Wang goto release_vector; 146357dacad5SJay Sternberg 146457dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 146557dacad5SJay Sternberg if (result < 0) 146657dacad5SJay Sternberg goto release_cq; 146757dacad5SJay Sternberg 1468161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1469dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 147057dacad5SJay Sternberg if (result < 0) 147157dacad5SJay Sternberg goto release_sq; 147257dacad5SJay Sternberg 147357dacad5SJay Sternberg return result; 147457dacad5SJay Sternberg 147557dacad5SJay Sternberg release_sq: 1476f25a2dfcSJianchao Wang dev->online_queues--; 147757dacad5SJay Sternberg adapter_delete_sq(dev, qid); 147857dacad5SJay Sternberg release_cq: 147957dacad5SJay Sternberg adapter_delete_cq(dev, qid); 1480f25a2dfcSJianchao Wang release_vector: 1481f25a2dfcSJianchao Wang nvmeq->cq_vector = -1; 148257dacad5SJay Sternberg return result; 148357dacad5SJay Sternberg } 148457dacad5SJay Sternberg 1485f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 148657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 148777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 148857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 148957dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 14900350815aSChristoph Hellwig .init_request = nvme_init_request, 149157dacad5SJay Sternberg .timeout = nvme_timeout, 149257dacad5SJay Sternberg }; 149357dacad5SJay Sternberg 1494f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 149557dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 149677f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 149757dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 149857dacad5SJay Sternberg .init_request = nvme_init_request, 1499dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 150057dacad5SJay Sternberg .timeout = nvme_timeout, 1501a0fa9647SJens Axboe .poll = nvme_poll, 150257dacad5SJay Sternberg }; 150357dacad5SJay Sternberg 150457dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 150557dacad5SJay Sternberg { 15061c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 150769d9a99cSKeith Busch /* 150869d9a99cSKeith Busch * If the controller was reset during removal, it's possible 150969d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 151069d9a99cSKeith Busch * queue to flush these to completion. 151169d9a99cSKeith Busch */ 1512c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15131c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 151457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 151557dacad5SJay Sternberg } 151657dacad5SJay Sternberg } 151757dacad5SJay Sternberg 151857dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 151957dacad5SJay Sternberg { 15201c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 152157dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 152257dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1523e3e9d50cSKeith Busch 152438dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 152557dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 152657dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1527a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1528d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 152957dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 153057dacad5SJay Sternberg 153157dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 153257dacad5SJay Sternberg return -ENOMEM; 153334b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 153457dacad5SJay Sternberg 15351c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15361c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 153757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 153857dacad5SJay Sternberg return -ENOMEM; 153957dacad5SJay Sternberg } 15401c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 154157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15421c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 154357dacad5SJay Sternberg return -ENODEV; 154457dacad5SJay Sternberg } 154557dacad5SJay Sternberg } else 1546c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 154757dacad5SJay Sternberg 154857dacad5SJay Sternberg return 0; 154957dacad5SJay Sternberg } 155057dacad5SJay Sternberg 155197f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 155297f6ef64SXu Yu { 155397f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 155497f6ef64SXu Yu } 155597f6ef64SXu Yu 155697f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 155797f6ef64SXu Yu { 155897f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 155997f6ef64SXu Yu 156097f6ef64SXu Yu if (size <= dev->bar_mapped_size) 156197f6ef64SXu Yu return 0; 156297f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 156397f6ef64SXu Yu return -ENOMEM; 156497f6ef64SXu Yu if (dev->bar) 156597f6ef64SXu Yu iounmap(dev->bar); 156697f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 156797f6ef64SXu Yu if (!dev->bar) { 156897f6ef64SXu Yu dev->bar_mapped_size = 0; 156997f6ef64SXu Yu return -ENOMEM; 157097f6ef64SXu Yu } 157197f6ef64SXu Yu dev->bar_mapped_size = size; 157297f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 157397f6ef64SXu Yu 157497f6ef64SXu Yu return 0; 157597f6ef64SXu Yu } 157697f6ef64SXu Yu 157701ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 157857dacad5SJay Sternberg { 157957dacad5SJay Sternberg int result; 158057dacad5SJay Sternberg u32 aqa; 158157dacad5SJay Sternberg struct nvme_queue *nvmeq; 158257dacad5SJay Sternberg 158397f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 158497f6ef64SXu Yu if (result < 0) 158597f6ef64SXu Yu return result; 158697f6ef64SXu Yu 15878ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 158820d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 158957dacad5SJay Sternberg 15907a67cbeaSChristoph Hellwig if (dev->subsystem && 15917a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 15927a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 159357dacad5SJay Sternberg 159420d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 159557dacad5SJay Sternberg if (result < 0) 159657dacad5SJay Sternberg return result; 159757dacad5SJay Sternberg 1598147b27e4SSagi Grimberg result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1599d3af3ecdSShaohua Li dev_to_node(dev->dev)); 1600147b27e4SSagi Grimberg if (result) 1601147b27e4SSagi Grimberg return result; 160257dacad5SJay Sternberg 1603147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 160457dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 160557dacad5SJay Sternberg aqa |= aqa << 16; 160657dacad5SJay Sternberg 16077a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 16087a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 16097a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 161057dacad5SJay Sternberg 161120d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 161257dacad5SJay Sternberg if (result) 1613d4875622SKeith Busch return result; 161457dacad5SJay Sternberg 161557dacad5SJay Sternberg nvmeq->cq_vector = 0; 1616161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1617dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 161857dacad5SJay Sternberg if (result) { 161957dacad5SJay Sternberg nvmeq->cq_vector = -1; 1620d4875622SKeith Busch return result; 162157dacad5SJay Sternberg } 162257dacad5SJay Sternberg 162357dacad5SJay Sternberg return result; 162457dacad5SJay Sternberg } 162557dacad5SJay Sternberg 1626749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 162757dacad5SJay Sternberg { 1628949928c1SKeith Busch unsigned i, max; 1629749941f2SChristoph Hellwig int ret = 0; 163057dacad5SJay Sternberg 1631d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1632d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1633147b27e4SSagi Grimberg if (nvme_alloc_queue(dev, i, dev->q_depth, 1634d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1635749941f2SChristoph Hellwig ret = -ENOMEM; 163657dacad5SJay Sternberg break; 1637749941f2SChristoph Hellwig } 1638749941f2SChristoph Hellwig } 163957dacad5SJay Sternberg 1640d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1641949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1642147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1643d4875622SKeith Busch if (ret) 164457dacad5SJay Sternberg break; 164557dacad5SJay Sternberg } 164657dacad5SJay Sternberg 1647749941f2SChristoph Hellwig /* 1648749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16498adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16508adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1651749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1652749941f2SChristoph Hellwig */ 1653749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 165457dacad5SJay Sternberg } 165557dacad5SJay Sternberg 1656202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1657202021c1SStephen Bates struct device_attribute *attr, 1658202021c1SStephen Bates char *buf) 1659202021c1SStephen Bates { 1660202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1661202021c1SStephen Bates 1662c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1663202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1664202021c1SStephen Bates } 1665202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1666202021c1SStephen Bates 166788de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 166857dacad5SJay Sternberg { 166988de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 167088de4598SChristoph Hellwig 167188de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 167288de4598SChristoph Hellwig } 167388de4598SChristoph Hellwig 167488de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 167588de4598SChristoph Hellwig { 167688de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 167788de4598SChristoph Hellwig } 167888de4598SChristoph Hellwig 1679f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 168057dacad5SJay Sternberg { 168188de4598SChristoph Hellwig u64 size, offset; 168257dacad5SJay Sternberg resource_size_t bar_size; 168357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 16848969f1f8SChristoph Hellwig int bar; 168557dacad5SJay Sternberg 16867a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1687f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1688f65efd6dSChristoph Hellwig return; 1689202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 169057dacad5SJay Sternberg 1691202021c1SStephen Bates if (!use_cmb_sqes) 1692f65efd6dSChristoph Hellwig return; 169357dacad5SJay Sternberg 169488de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 169588de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 16968969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 16978969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 169857dacad5SJay Sternberg 169957dacad5SJay Sternberg if (offset > bar_size) 1700f65efd6dSChristoph Hellwig return; 170157dacad5SJay Sternberg 170257dacad5SJay Sternberg /* 170357dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 170457dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 170557dacad5SJay Sternberg * the reported size of the BAR 170657dacad5SJay Sternberg */ 170757dacad5SJay Sternberg if (size > bar_size - offset) 170857dacad5SJay Sternberg size = bar_size - offset; 170957dacad5SJay Sternberg 1710f65efd6dSChristoph Hellwig dev->cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 1711f65efd6dSChristoph Hellwig if (!dev->cmb) 1712f65efd6dSChristoph Hellwig return; 17138969f1f8SChristoph Hellwig dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 171457dacad5SJay Sternberg dev->cmb_size = size; 1715f65efd6dSChristoph Hellwig 1716f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1717f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1718f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1719f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 172057dacad5SJay Sternberg } 172157dacad5SJay Sternberg 172257dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 172357dacad5SJay Sternberg { 172457dacad5SJay Sternberg if (dev->cmb) { 172557dacad5SJay Sternberg iounmap(dev->cmb); 172657dacad5SJay Sternberg dev->cmb = NULL; 1727f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1728f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1729f63572dfSJon Derrick dev->cmbsz = 0; 1730f63572dfSJon Derrick } 173157dacad5SJay Sternberg } 173257dacad5SJay Sternberg 173387ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 173457dacad5SJay Sternberg { 17354033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 173687ad72a5SChristoph Hellwig struct nvme_command c; 173787ad72a5SChristoph Hellwig int ret; 173887ad72a5SChristoph Hellwig 173987ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 174087ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 174187ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 174287ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 174387ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 174487ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 174587ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 174687ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 174787ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 174887ad72a5SChristoph Hellwig 174987ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 175087ad72a5SChristoph Hellwig if (ret) { 175187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 175287ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 175387ad72a5SChristoph Hellwig ret, bits); 175487ad72a5SChristoph Hellwig } 175587ad72a5SChristoph Hellwig return ret; 175687ad72a5SChristoph Hellwig } 175787ad72a5SChristoph Hellwig 175887ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 175987ad72a5SChristoph Hellwig { 176087ad72a5SChristoph Hellwig int i; 176187ad72a5SChristoph Hellwig 176287ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 176387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 176487ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 176587ad72a5SChristoph Hellwig 176687ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 176787ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 176887ad72a5SChristoph Hellwig } 176987ad72a5SChristoph Hellwig 177087ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 177187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17724033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17734033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 17744033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 177587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 17767e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 177787ad72a5SChristoph Hellwig } 177887ad72a5SChristoph Hellwig 177992dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 178092dc6895SChristoph Hellwig u32 chunk_size) 178187ad72a5SChristoph Hellwig { 178287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 178392dc6895SChristoph Hellwig u32 max_entries, len; 17844033f35dSChristoph Hellwig dma_addr_t descs_dma; 17852ee0e4edSDan Carpenter int i = 0; 178687ad72a5SChristoph Hellwig void **bufs; 17876fbcde66SMinwoo Im u64 size, tmp; 178887ad72a5SChristoph Hellwig 178987ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 179087ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 179187ad72a5SChristoph Hellwig max_entries = tmp; 1792044a9df1SChristoph Hellwig 1793044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1794044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1795044a9df1SChristoph Hellwig 17964033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 17974033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 179887ad72a5SChristoph Hellwig if (!descs) 179987ad72a5SChristoph Hellwig goto out; 180087ad72a5SChristoph Hellwig 180187ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 180287ad72a5SChristoph Hellwig if (!bufs) 180387ad72a5SChristoph Hellwig goto out_free_descs; 180487ad72a5SChristoph Hellwig 1805244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 180687ad72a5SChristoph Hellwig dma_addr_t dma_addr; 180787ad72a5SChristoph Hellwig 180850cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 180987ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 181087ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 181187ad72a5SChristoph Hellwig if (!bufs[i]) 181287ad72a5SChristoph Hellwig break; 181387ad72a5SChristoph Hellwig 181487ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 181587ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 181687ad72a5SChristoph Hellwig i++; 181787ad72a5SChristoph Hellwig } 181887ad72a5SChristoph Hellwig 181992dc6895SChristoph Hellwig if (!size) 182087ad72a5SChristoph Hellwig goto out_free_bufs; 182187ad72a5SChristoph Hellwig 182287ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 182387ad72a5SChristoph Hellwig dev->host_mem_size = size; 182487ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 18254033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 182687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 182787ad72a5SChristoph Hellwig return 0; 182887ad72a5SChristoph Hellwig 182987ad72a5SChristoph Hellwig out_free_bufs: 183087ad72a5SChristoph Hellwig while (--i >= 0) { 183187ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 183287ad72a5SChristoph Hellwig 183387ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 183487ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 183587ad72a5SChristoph Hellwig } 183687ad72a5SChristoph Hellwig 183787ad72a5SChristoph Hellwig kfree(bufs); 183887ad72a5SChristoph Hellwig out_free_descs: 18394033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18404033f35dSChristoph Hellwig descs_dma); 184187ad72a5SChristoph Hellwig out: 184287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 184387ad72a5SChristoph Hellwig return -ENOMEM; 184487ad72a5SChristoph Hellwig } 184587ad72a5SChristoph Hellwig 184692dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 184792dc6895SChristoph Hellwig { 184892dc6895SChristoph Hellwig u32 chunk_size; 184992dc6895SChristoph Hellwig 185092dc6895SChristoph Hellwig /* start big and work our way down */ 185130f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1852044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 185392dc6895SChristoph Hellwig chunk_size /= 2) { 185492dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 185592dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 185692dc6895SChristoph Hellwig return 0; 185792dc6895SChristoph Hellwig nvme_free_host_mem(dev); 185892dc6895SChristoph Hellwig } 185992dc6895SChristoph Hellwig } 186092dc6895SChristoph Hellwig 186192dc6895SChristoph Hellwig return -ENOMEM; 186292dc6895SChristoph Hellwig } 186392dc6895SChristoph Hellwig 18649620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 186587ad72a5SChristoph Hellwig { 186687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 186787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 186887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 186987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18706fbcde66SMinwoo Im int ret; 187187ad72a5SChristoph Hellwig 187287ad72a5SChristoph Hellwig preferred = min(preferred, max); 187387ad72a5SChristoph Hellwig if (min > max) { 187487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 187587ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 187687ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 187787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18789620cfbaSChristoph Hellwig return 0; 187987ad72a5SChristoph Hellwig } 188087ad72a5SChristoph Hellwig 188187ad72a5SChristoph Hellwig /* 188287ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 188387ad72a5SChristoph Hellwig */ 188487ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 188587ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 188687ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 188787ad72a5SChristoph Hellwig else 188887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 188987ad72a5SChristoph Hellwig } 189087ad72a5SChristoph Hellwig 189187ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 189292dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 189392dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 189492dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 18959620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 189687ad72a5SChristoph Hellwig } 189787ad72a5SChristoph Hellwig 189892dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 189992dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 190092dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 190192dc6895SChristoph Hellwig } 190292dc6895SChristoph Hellwig 19039620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 19049620cfbaSChristoph Hellwig if (ret) 190587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19069620cfbaSChristoph Hellwig return ret; 190757dacad5SJay Sternberg } 190857dacad5SJay Sternberg 190957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 191057dacad5SJay Sternberg { 1911147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 191257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 191397f6ef64SXu Yu int result, nr_io_queues; 191497f6ef64SXu Yu unsigned long size; 191557dacad5SJay Sternberg 1916425a17cbSChristoph Hellwig nr_io_queues = num_present_cpus(); 19179a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 19189a0be7abSChristoph Hellwig if (result < 0) 191957dacad5SJay Sternberg return result; 19209a0be7abSChristoph Hellwig 1921f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1922a5229050SKeith Busch return 0; 192357dacad5SJay Sternberg 192488de4598SChristoph Hellwig if (dev->cmb && (dev->cmbsz & NVME_CMBSZ_SQS)) { 192557dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 192657dacad5SJay Sternberg sizeof(struct nvme_command)); 192757dacad5SJay Sternberg if (result > 0) 192857dacad5SJay Sternberg dev->q_depth = result; 192957dacad5SJay Sternberg else 193057dacad5SJay Sternberg nvme_release_cmb(dev); 193157dacad5SJay Sternberg } 193257dacad5SJay Sternberg 193357dacad5SJay Sternberg do { 193497f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 193597f6ef64SXu Yu result = nvme_remap_bar(dev, size); 193697f6ef64SXu Yu if (!result) 193757dacad5SJay Sternberg break; 193857dacad5SJay Sternberg if (!--nr_io_queues) 193957dacad5SJay Sternberg return -ENOMEM; 194057dacad5SJay Sternberg } while (1); 194157dacad5SJay Sternberg adminq->q_db = dev->dbs; 194257dacad5SJay Sternberg 194357dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19440ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 194557dacad5SJay Sternberg 194657dacad5SJay Sternberg /* 194757dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 194857dacad5SJay Sternberg * setting up the full range we need. 194957dacad5SJay Sternberg */ 1950dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1951dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1952dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1953dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1954dca51e78SChristoph Hellwig return -EIO; 1955dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 195657dacad5SJay Sternberg 195757dacad5SJay Sternberg /* 195857dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 195957dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 196057dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 196157dacad5SJay Sternberg * number of interrupts. 196257dacad5SJay Sternberg */ 196357dacad5SJay Sternberg 1964dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 196557dacad5SJay Sternberg if (result) { 196657dacad5SJay Sternberg adminq->cq_vector = -1; 1967d4875622SKeith Busch return result; 196857dacad5SJay Sternberg } 1969749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 197057dacad5SJay Sternberg } 197157dacad5SJay Sternberg 19722a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1973db3cbfffSKeith Busch { 1974db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1975db3cbfffSKeith Busch 1976db3cbfffSKeith Busch blk_mq_free_request(req); 1977db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1978db3cbfffSKeith Busch } 1979db3cbfffSKeith Busch 19802a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1981db3cbfffSKeith Busch { 1982db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1983db3cbfffSKeith Busch 1984db3cbfffSKeith Busch if (!error) { 1985db3cbfffSKeith Busch unsigned long flags; 1986db3cbfffSKeith Busch 19872e39e0f6SMing Lin /* 19882e39e0f6SMing Lin * We might be called with the AQ q_lock held 19892e39e0f6SMing Lin * and the I/O queue q_lock should always 19902e39e0f6SMing Lin * nest inside the AQ one. 19912e39e0f6SMing Lin */ 19922e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 19932e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1994db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1995db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1996db3cbfffSKeith Busch } 1997db3cbfffSKeith Busch 1998db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1999db3cbfffSKeith Busch } 2000db3cbfffSKeith Busch 2001db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2002db3cbfffSKeith Busch { 2003db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2004db3cbfffSKeith Busch struct request *req; 2005db3cbfffSKeith Busch struct nvme_command cmd; 2006db3cbfffSKeith Busch 2007db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2008db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2009db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2010db3cbfffSKeith Busch 2011eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2012db3cbfffSKeith Busch if (IS_ERR(req)) 2013db3cbfffSKeith Busch return PTR_ERR(req); 2014db3cbfffSKeith Busch 2015db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2016db3cbfffSKeith Busch req->end_io_data = nvmeq; 2017db3cbfffSKeith Busch 2018db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2019db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2020db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2021db3cbfffSKeith Busch return 0; 2022db3cbfffSKeith Busch } 2023db3cbfffSKeith Busch 2024ee9aebb2SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 2025db3cbfffSKeith Busch { 2026ee9aebb2SKeith Busch int pass, queues = dev->online_queues - 1; 2027db3cbfffSKeith Busch unsigned long timeout; 2028db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2029db3cbfffSKeith Busch 2030db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2031014a0d60SKeith Busch int sent = 0, i = queues; 2032db3cbfffSKeith Busch 2033db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2034db3cbfffSKeith Busch retry: 2035db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2036c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2037147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2038db3cbfffSKeith Busch break; 2039c21377f8SGabriel Krisman Bertazi 2040db3cbfffSKeith Busch while (sent--) { 2041db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2042db3cbfffSKeith Busch if (timeout == 0) 2043db3cbfffSKeith Busch return; 2044db3cbfffSKeith Busch if (i) 2045db3cbfffSKeith Busch goto retry; 2046db3cbfffSKeith Busch } 2047db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2048db3cbfffSKeith Busch } 2049db3cbfffSKeith Busch } 2050db3cbfffSKeith Busch 205157dacad5SJay Sternberg /* 20522b1b7e78SJianchao Wang * return error value only when tagset allocation failed 205357dacad5SJay Sternberg */ 205457dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 205557dacad5SJay Sternberg { 20562b1b7e78SJianchao Wang int ret; 20572b1b7e78SJianchao Wang 20585bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 205957dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 206057dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 206157dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 206257dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 206357dacad5SJay Sternberg dev->tagset.queue_depth = 206457dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2065a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2066a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2067a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2068a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2069a7a7cbe3SChaitanya Kulkarni } 207057dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 207157dacad5SJay Sternberg dev->tagset.driver_data = dev; 207257dacad5SJay Sternberg 20732b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 20742b1b7e78SJianchao Wang if (ret) { 20752b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 20762b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 20772b1b7e78SJianchao Wang return ret; 20782b1b7e78SJianchao Wang } 20795bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2080f9f38e33SHelen Koike 2081f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2082949928c1SKeith Busch } else { 2083949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2084949928c1SKeith Busch 2085949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2086949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 208757dacad5SJay Sternberg } 2088949928c1SKeith Busch 208957dacad5SJay Sternberg return 0; 209057dacad5SJay Sternberg } 209157dacad5SJay Sternberg 2092b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 209357dacad5SJay Sternberg { 2094b00a726aSKeith Busch int result = -ENOMEM; 209557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 209657dacad5SJay Sternberg 209757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 209857dacad5SJay Sternberg return result; 209957dacad5SJay Sternberg 210057dacad5SJay Sternberg pci_set_master(pdev); 210157dacad5SJay Sternberg 210257dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 210357dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 210457dacad5SJay Sternberg goto disable; 210557dacad5SJay Sternberg 21067a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 210757dacad5SJay Sternberg result = -ENODEV; 2108b00a726aSKeith Busch goto disable; 210957dacad5SJay Sternberg } 211057dacad5SJay Sternberg 211157dacad5SJay Sternberg /* 2112a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2113a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2114a5229050SKeith Busch * adjust this later. 211557dacad5SJay Sternberg */ 2116dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2117dca51e78SChristoph Hellwig if (result < 0) 2118dca51e78SChristoph Hellwig return result; 211957dacad5SJay Sternberg 212020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 21217a67cbeaSChristoph Hellwig 212220d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2123b27c1e68Sweiping zhang io_queue_depth); 212420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 21257a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21261f390c1fSStephan Günther 21271f390c1fSStephan Günther /* 21281f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21291f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21301f390c1fSStephan Günther */ 21311f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21321f390c1fSStephan Günther dev->q_depth = 2; 21339bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21349bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21351f390c1fSStephan Günther dev->q_depth); 2136d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2137d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 213820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2139d554b5e1SMartin K. Petersen dev->q_depth = 64; 2140d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2141d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21421f390c1fSStephan Günther } 21431f390c1fSStephan Günther 2144f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2145202021c1SStephen Bates 2146a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2147a0a3408eSKeith Busch pci_save_state(pdev); 214857dacad5SJay Sternberg return 0; 214957dacad5SJay Sternberg 215057dacad5SJay Sternberg disable: 215157dacad5SJay Sternberg pci_disable_device(pdev); 215257dacad5SJay Sternberg return result; 215357dacad5SJay Sternberg } 215457dacad5SJay Sternberg 215557dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 215657dacad5SJay Sternberg { 2157b00a726aSKeith Busch if (dev->bar) 2158b00a726aSKeith Busch iounmap(dev->bar); 2159a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2160b00a726aSKeith Busch } 2161b00a726aSKeith Busch 2162b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2163b00a726aSKeith Busch { 216457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 216557dacad5SJay Sternberg 2166f63572dfSJon Derrick nvme_release_cmb(dev); 2167dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 216857dacad5SJay Sternberg 2169a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2170a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 217157dacad5SJay Sternberg pci_disable_device(pdev); 217257dacad5SJay Sternberg } 2173a0a3408eSKeith Busch } 217457dacad5SJay Sternberg 2175a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 217657dacad5SJay Sternberg { 2177ee9aebb2SKeith Busch int i; 2178302ad8ccSKeith Busch bool dead = true; 2179302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 218057dacad5SJay Sternberg 218177bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2182302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2183302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2184302ad8ccSKeith Busch 2185ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2186ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2187302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2188302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2189302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 219057dacad5SJay Sternberg } 2191c21377f8SGabriel Krisman Bertazi 2192302ad8ccSKeith Busch /* 2193302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2194302ad8ccSKeith Busch * doing a safe shutdown. 2195302ad8ccSKeith Busch */ 219687ad72a5SChristoph Hellwig if (!dead) { 219787ad72a5SChristoph Hellwig if (shutdown) 2198302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 21999a915a5bSJianchao Wang } 220087ad72a5SChristoph Hellwig 22019a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 22029a915a5bSJianchao Wang 22039a915a5bSJianchao Wang if (!dead) { 220487ad72a5SChristoph Hellwig /* 220587ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 220687ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 220787ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 220887ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 220987ad72a5SChristoph Hellwig */ 221087ad72a5SChristoph Hellwig if (dev->host_mem_descs) 221187ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 2212ee9aebb2SKeith Busch nvme_disable_io_queues(dev); 2213a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 221457dacad5SJay Sternberg } 2215ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2216ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2217ee9aebb2SKeith Busch 2218b00a726aSKeith Busch nvme_pci_disable(dev); 221957dacad5SJay Sternberg 2220e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2221e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2222302ad8ccSKeith Busch 2223302ad8ccSKeith Busch /* 2224302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2225302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2226302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2227302ad8ccSKeith Busch */ 2228302ad8ccSKeith Busch if (shutdown) 2229302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 223077bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 223157dacad5SJay Sternberg } 223257dacad5SJay Sternberg 223357dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 223457dacad5SJay Sternberg { 223557dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 223657dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 223757dacad5SJay Sternberg if (!dev->prp_page_pool) 223857dacad5SJay Sternberg return -ENOMEM; 223957dacad5SJay Sternberg 224057dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 224157dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 224257dacad5SJay Sternberg 256, 256, 0); 224357dacad5SJay Sternberg if (!dev->prp_small_pool) { 224457dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 224557dacad5SJay Sternberg return -ENOMEM; 224657dacad5SJay Sternberg } 224757dacad5SJay Sternberg return 0; 224857dacad5SJay Sternberg } 224957dacad5SJay Sternberg 225057dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 225157dacad5SJay Sternberg { 225257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 225357dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 225457dacad5SJay Sternberg } 225557dacad5SJay Sternberg 22561673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 225757dacad5SJay Sternberg { 22581673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 225957dacad5SJay Sternberg 2260f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 226157dacad5SJay Sternberg put_device(dev->dev); 226257dacad5SJay Sternberg if (dev->tagset.tags) 226357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22641c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22651c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 226657dacad5SJay Sternberg kfree(dev->queues); 2267e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 226857dacad5SJay Sternberg kfree(dev); 226957dacad5SJay Sternberg } 227057dacad5SJay Sternberg 2271f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2272f58944e2SKeith Busch { 2273237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2274f58944e2SKeith Busch 2275d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 227669d9a99cSKeith Busch nvme_dev_disable(dev, false); 227703e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2278f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2279f58944e2SKeith Busch } 2280f58944e2SKeith Busch 2281fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 228257dacad5SJay Sternberg { 2283d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2284d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2285a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2286f58944e2SKeith Busch int result = -ENODEV; 22872b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 228857dacad5SJay Sternberg 228982b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2290fd634f41SChristoph Hellwig goto out; 2291fd634f41SChristoph Hellwig 2292fd634f41SChristoph Hellwig /* 2293fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2294fd634f41SChristoph Hellwig * moving on. 2295fd634f41SChristoph Hellwig */ 2296b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2297a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2298fd634f41SChristoph Hellwig 2299ad70062cSJianchao Wang /* 2300ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2301ad70062cSJianchao Wang * initializing procedure here. 2302ad70062cSJianchao Wang */ 2303ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2304ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2305ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2306ad70062cSJianchao Wang goto out; 2307ad70062cSJianchao Wang } 2308ad70062cSJianchao Wang 2309b00a726aSKeith Busch result = nvme_pci_enable(dev); 231057dacad5SJay Sternberg if (result) 231157dacad5SJay Sternberg goto out; 231257dacad5SJay Sternberg 231301ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 231457dacad5SJay Sternberg if (result) 2315f58944e2SKeith Busch goto out; 231657dacad5SJay Sternberg 231757dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 231857dacad5SJay Sternberg if (result) 2319f58944e2SKeith Busch goto out; 232057dacad5SJay Sternberg 2321ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2322ce4541f4SChristoph Hellwig if (result) 2323f58944e2SKeith Busch goto out; 2324ce4541f4SChristoph Hellwig 2325e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2326e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23274f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23284f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2329e286bcfcSScott Bauer else if (was_suspend) 23304f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2331e286bcfcSScott Bauer } else { 2332e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2333e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2334e286bcfcSScott Bauer } 2335a98e58e5SScott Bauer 2336f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2337f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2338f9f38e33SHelen Koike if (result) 2339f9f38e33SHelen Koike dev_warn(dev->dev, 2340f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2341f9f38e33SHelen Koike } 2342f9f38e33SHelen Koike 23439620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23449620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23459620cfbaSChristoph Hellwig if (result < 0) 23469620cfbaSChristoph Hellwig goto out; 23479620cfbaSChristoph Hellwig } 234887ad72a5SChristoph Hellwig 234957dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 235057dacad5SJay Sternberg if (result) 2351f58944e2SKeith Busch goto out; 235257dacad5SJay Sternberg 235321f033f7SKeith Busch /* 235457dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 235557dacad5SJay Sternberg * any working I/O queue. 235657dacad5SJay Sternberg */ 235757dacad5SJay Sternberg if (dev->online_queues < 2) { 23581b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23593b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23605bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23612b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 236257dacad5SJay Sternberg } else { 236325646264SKeith Busch nvme_start_queues(&dev->ctrl); 2364302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23652b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23662b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23672b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2368302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 236957dacad5SJay Sternberg } 237057dacad5SJay Sternberg 23712b1b7e78SJianchao Wang /* 23722b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 23732b1b7e78SJianchao Wang * recovery. 23742b1b7e78SJianchao Wang */ 23752b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 23762b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23772b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2378bb8d261eSChristoph Hellwig goto out; 2379bb8d261eSChristoph Hellwig } 238092911a55SChristoph Hellwig 2381d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 238257dacad5SJay Sternberg return; 238357dacad5SJay Sternberg 238457dacad5SJay Sternberg out: 2385f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 238657dacad5SJay Sternberg } 238757dacad5SJay Sternberg 23885c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 238957dacad5SJay Sternberg { 23905c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 239157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 239257dacad5SJay Sternberg 239369d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 239457dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2395921920abSKeith Busch device_release_driver(&pdev->dev); 23961673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 239757dacad5SJay Sternberg } 239857dacad5SJay Sternberg 23991c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 240057dacad5SJay Sternberg { 24011c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 24021c63dc66SChristoph Hellwig return 0; 240357dacad5SJay Sternberg } 24041c63dc66SChristoph Hellwig 24055fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 24065fd4ce1bSChristoph Hellwig { 24075fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 24085fd4ce1bSChristoph Hellwig return 0; 24095fd4ce1bSChristoph Hellwig } 24105fd4ce1bSChristoph Hellwig 24117fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 24127fd8930fSChristoph Hellwig { 24137fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24147fd8930fSChristoph Hellwig return 0; 24157fd8930fSChristoph Hellwig } 24167fd8930fSChristoph Hellwig 24171c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24181a353d85SMing Lin .name = "pcie", 2419e439bb12SSagi Grimberg .module = THIS_MODULE, 2420c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24211c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24225fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24237fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24241673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2425f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 24261c63dc66SChristoph Hellwig }; 242757dacad5SJay Sternberg 2428b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2429b00a726aSKeith Busch { 2430b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2431b00a726aSKeith Busch 2432a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2433b00a726aSKeith Busch return -ENODEV; 2434b00a726aSKeith Busch 243597f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2436b00a726aSKeith Busch goto release; 2437b00a726aSKeith Busch 2438b00a726aSKeith Busch return 0; 2439b00a726aSKeith Busch release: 2440a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2441b00a726aSKeith Busch return -ENODEV; 2442b00a726aSKeith Busch } 2443b00a726aSKeith Busch 24448427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2445ff5350a8SAndy Lutomirski { 2446ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2447ff5350a8SAndy Lutomirski /* 2448ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2449ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2450ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2451ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2452ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2453ff5350a8SAndy Lutomirski * laptops. 2454ff5350a8SAndy Lutomirski */ 2455ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2456ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2457ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2458ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24598427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24608427bbc2SKai-Heng Feng /* 24618427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 24628427bbc2SKai-Heng Feng * suspend on a Ryzen board, ASUS PRIME B350M-A. 24638427bbc2SKai-Heng Feng */ 24648427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 24658427bbc2SKai-Heng Feng dmi_match(DMI_BOARD_NAME, "PRIME B350M-A")) 24668427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2467ff5350a8SAndy Lutomirski } 2468ff5350a8SAndy Lutomirski 2469ff5350a8SAndy Lutomirski return 0; 2470ff5350a8SAndy Lutomirski } 2471ff5350a8SAndy Lutomirski 247257dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 247357dacad5SJay Sternberg { 247457dacad5SJay Sternberg int node, result = -ENOMEM; 247557dacad5SJay Sternberg struct nvme_dev *dev; 2476ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 247757dacad5SJay Sternberg 247857dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 247957dacad5SJay Sternberg if (node == NUMA_NO_NODE) 24802fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 248157dacad5SJay Sternberg 248257dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 248357dacad5SJay Sternberg if (!dev) 248457dacad5SJay Sternberg return -ENOMEM; 2485147b27e4SSagi Grimberg 2486147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2487147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 248857dacad5SJay Sternberg if (!dev->queues) 248957dacad5SJay Sternberg goto free; 249057dacad5SJay Sternberg 249157dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 249257dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 249357dacad5SJay Sternberg 2494b00a726aSKeith Busch result = nvme_dev_map(dev); 2495b00a726aSKeith Busch if (result) 2496b00c9b7aSChristophe JAILLET goto put_pci; 2497b00a726aSKeith Busch 2498d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 24995c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 250077bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2501db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2502f3ca80fcSChristoph Hellwig 2503f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2504f3ca80fcSChristoph Hellwig if (result) 2505b00c9b7aSChristophe JAILLET goto unmap; 2506f3ca80fcSChristoph Hellwig 25078427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2508ff5350a8SAndy Lutomirski 2509f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2510ff5350a8SAndy Lutomirski quirks); 2511f3ca80fcSChristoph Hellwig if (result) 2512f3ca80fcSChristoph Hellwig goto release_pools; 2513f3ca80fcSChristoph Hellwig 25141b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25151b3c47c1SSagi Grimberg 25164caff8fcSSagi Grimberg nvme_reset_ctrl(&dev->ctrl); 25174caff8fcSSagi Grimberg 251857dacad5SJay Sternberg return 0; 251957dacad5SJay Sternberg 252057dacad5SJay Sternberg release_pools: 252157dacad5SJay Sternberg nvme_release_prp_pools(dev); 2522b00c9b7aSChristophe JAILLET unmap: 2523b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 252457dacad5SJay Sternberg put_pci: 252557dacad5SJay Sternberg put_device(dev->dev); 252657dacad5SJay Sternberg free: 252757dacad5SJay Sternberg kfree(dev->queues); 252857dacad5SJay Sternberg kfree(dev); 252957dacad5SJay Sternberg return result; 253057dacad5SJay Sternberg } 253157dacad5SJay Sternberg 2532775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 253357dacad5SJay Sternberg { 253457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2535a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2536775755edSChristoph Hellwig } 253757dacad5SJay Sternberg 2538775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2539775755edSChristoph Hellwig { 2540f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 254179c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 254257dacad5SJay Sternberg } 254357dacad5SJay Sternberg 254457dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 254557dacad5SJay Sternberg { 254657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2547a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 254857dacad5SJay Sternberg } 254957dacad5SJay Sternberg 2550f58944e2SKeith Busch /* 2551f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2552f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2553f58944e2SKeith Busch * order to proceed. 2554f58944e2SKeith Busch */ 255557dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 255657dacad5SJay Sternberg { 255757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 255857dacad5SJay Sternberg 2559bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2560bb8d261eSChristoph Hellwig 2561d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 256257dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 25630ff9d4e1SKeith Busch 25646db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 25650ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 25666db28edaSKeith Busch nvme_dev_disable(dev, false); 25676db28edaSKeith Busch } 25680ff9d4e1SKeith Busch 2569d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2570d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2571d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2572a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 257387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 257457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 257557dacad5SJay Sternberg nvme_free_queues(dev, 0); 2576d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 257757dacad5SJay Sternberg nvme_release_prp_pools(dev); 2578b00a726aSKeith Busch nvme_dev_unmap(dev); 25791673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 258057dacad5SJay Sternberg } 258157dacad5SJay Sternberg 258213880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 258313880f5bSKeith Busch { 258413880f5bSKeith Busch int ret = 0; 258513880f5bSKeith Busch 258613880f5bSKeith Busch if (numvfs == 0) { 258713880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 258813880f5bSKeith Busch dev_warn(&pdev->dev, 258913880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 259013880f5bSKeith Busch return -EPERM; 259113880f5bSKeith Busch } 259213880f5bSKeith Busch pci_disable_sriov(pdev); 259313880f5bSKeith Busch return 0; 259413880f5bSKeith Busch } 259513880f5bSKeith Busch 259613880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 259713880f5bSKeith Busch return ret ? ret : numvfs; 259813880f5bSKeith Busch } 259913880f5bSKeith Busch 260057dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 260157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 260257dacad5SJay Sternberg { 260357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 260457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 260557dacad5SJay Sternberg 2606a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 260757dacad5SJay Sternberg return 0; 260857dacad5SJay Sternberg } 260957dacad5SJay Sternberg 261057dacad5SJay Sternberg static int nvme_resume(struct device *dev) 261157dacad5SJay Sternberg { 261257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 261357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 261457dacad5SJay Sternberg 2615d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 261657dacad5SJay Sternberg return 0; 261757dacad5SJay Sternberg } 261857dacad5SJay Sternberg #endif 261957dacad5SJay Sternberg 262057dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 262157dacad5SJay Sternberg 2622a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2623a0a3408eSKeith Busch pci_channel_state_t state) 2624a0a3408eSKeith Busch { 2625a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2626a0a3408eSKeith Busch 2627a0a3408eSKeith Busch /* 2628a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2629a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2630a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2631a0a3408eSKeith Busch */ 2632a0a3408eSKeith Busch switch (state) { 2633a0a3408eSKeith Busch case pci_channel_io_normal: 2634a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2635a0a3408eSKeith Busch case pci_channel_io_frozen: 2636d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2637d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2638a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2639a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2640a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2641d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2642d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2643a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2644a0a3408eSKeith Busch } 2645a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2646a0a3408eSKeith Busch } 2647a0a3408eSKeith Busch 2648a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2649a0a3408eSKeith Busch { 2650a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2651a0a3408eSKeith Busch 26521b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2653a0a3408eSKeith Busch pci_restore_state(pdev); 2654d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2655a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2656a0a3408eSKeith Busch } 2657a0a3408eSKeith Busch 2658a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2659a0a3408eSKeith Busch { 2660a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2661a0a3408eSKeith Busch } 2662a0a3408eSKeith Busch 266357dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 266457dacad5SJay Sternberg .error_detected = nvme_error_detected, 266557dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 266657dacad5SJay Sternberg .resume = nvme_error_resume, 2667775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2668775755edSChristoph Hellwig .reset_done = nvme_reset_done, 266957dacad5SJay Sternberg }; 267057dacad5SJay Sternberg 267157dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2672106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 267308095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2674e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 267599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 267699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2677e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 267899466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 267999466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2680e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2681f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2682f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2683f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 268450af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 268550af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2686540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2687540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 268854adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 268954adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 26908c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 26918c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2692015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2693015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2694d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2695d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2696d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2697d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2698608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2699608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2700608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2701608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 270257dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2703c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2704124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 270557dacad5SJay Sternberg { 0, } 270657dacad5SJay Sternberg }; 270757dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 270857dacad5SJay Sternberg 270957dacad5SJay Sternberg static struct pci_driver nvme_driver = { 271057dacad5SJay Sternberg .name = "nvme", 271157dacad5SJay Sternberg .id_table = nvme_id_table, 271257dacad5SJay Sternberg .probe = nvme_probe, 271357dacad5SJay Sternberg .remove = nvme_remove, 271457dacad5SJay Sternberg .shutdown = nvme_shutdown, 271557dacad5SJay Sternberg .driver = { 271657dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 271757dacad5SJay Sternberg }, 271813880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 271957dacad5SJay Sternberg .err_handler = &nvme_err_handler, 272057dacad5SJay Sternberg }; 272157dacad5SJay Sternberg 272257dacad5SJay Sternberg static int __init nvme_init(void) 272357dacad5SJay Sternberg { 27249a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 272557dacad5SJay Sternberg } 272657dacad5SJay Sternberg 272757dacad5SJay Sternberg static void __exit nvme_exit(void) 272857dacad5SJay Sternberg { 272957dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 273003e0f3a6SMing Lei flush_workqueue(nvme_wq); 273157dacad5SJay Sternberg _nvme_check_size(); 273257dacad5SJay Sternberg } 273357dacad5SJay Sternberg 273457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 273557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 273657dacad5SJay Sternberg MODULE_VERSION("1.0"); 273757dacad5SJay Sternberg module_init(nvme_init); 273857dacad5SJay Sternberg module_exit(nvme_exit); 2739