157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/bitops.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 2057dacad5SJay Sternberg #include <linux/cpu.h> 2157dacad5SJay Sternberg #include <linux/delay.h> 22ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2357dacad5SJay Sternberg #include <linux/errno.h> 2457dacad5SJay Sternberg #include <linux/fs.h> 2557dacad5SJay Sternberg #include <linux/genhd.h> 2657dacad5SJay Sternberg #include <linux/hdreg.h> 2757dacad5SJay Sternberg #include <linux/idr.h> 2857dacad5SJay Sternberg #include <linux/init.h> 2957dacad5SJay Sternberg #include <linux/interrupt.h> 3057dacad5SJay Sternberg #include <linux/io.h> 3157dacad5SJay Sternberg #include <linux/kdev_t.h> 3257dacad5SJay Sternberg #include <linux/kernel.h> 3357dacad5SJay Sternberg #include <linux/mm.h> 3457dacad5SJay Sternberg #include <linux/module.h> 3557dacad5SJay Sternberg #include <linux/moduleparam.h> 3677bf25eaSKeith Busch #include <linux/mutex.h> 3757dacad5SJay Sternberg #include <linux/pci.h> 3857dacad5SJay Sternberg #include <linux/poison.h> 3957dacad5SJay Sternberg #include <linux/ptrace.h> 4057dacad5SJay Sternberg #include <linux/sched.h> 4157dacad5SJay Sternberg #include <linux/slab.h> 4257dacad5SJay Sternberg #include <linux/t10-pi.h> 432d55cd5fSChristoph Hellwig #include <linux/timer.h> 4457dacad5SJay Sternberg #include <linux/types.h> 459cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 461d277a63SKeith Busch #include <asm/unaligned.h> 47a98e58e5SScott Bauer #include <linux/sed-opal.h> 4857dacad5SJay Sternberg 4957dacad5SJay Sternberg #include "nvme.h" 5057dacad5SJay Sternberg 5157dacad5SJay Sternberg #define NVME_Q_DEPTH 1024 5257dacad5SJay Sternberg #define NVME_AQ_DEPTH 256 5357dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 5457dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 5557dacad5SJay Sternberg 56adf68f21SChristoph Hellwig /* 57adf68f21SChristoph Hellwig * We handle AEN commands ourselves and don't even let the 58adf68f21SChristoph Hellwig * block layer know about them. 59adf68f21SChristoph Hellwig */ 60f866fc42SChristoph Hellwig #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) 61adf68f21SChristoph Hellwig 6257dacad5SJay Sternberg static int use_threaded_interrupts; 6357dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 6457dacad5SJay Sternberg 6557dacad5SJay Sternberg static bool use_cmb_sqes = true; 6657dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 6757dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 6857dacad5SJay Sternberg 6987ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 7087ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 7187ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 7287ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 7387ad72a5SChristoph Hellwig 741c63dc66SChristoph Hellwig struct nvme_dev; 751c63dc66SChristoph Hellwig struct nvme_queue; 7657dacad5SJay Sternberg 7757dacad5SJay Sternberg static int nvme_reset(struct nvme_dev *dev); 78a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 79a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 8057dacad5SJay Sternberg 8157dacad5SJay Sternberg /* 821c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 831c63dc66SChristoph Hellwig */ 841c63dc66SChristoph Hellwig struct nvme_dev { 851c63dc66SChristoph Hellwig struct nvme_queue **queues; 861c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 871c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 881c63dc66SChristoph Hellwig u32 __iomem *dbs; 891c63dc66SChristoph Hellwig struct device *dev; 901c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 911c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 921c63dc66SChristoph Hellwig unsigned queue_count; 931c63dc66SChristoph Hellwig unsigned online_queues; 941c63dc66SChristoph Hellwig unsigned max_qid; 951c63dc66SChristoph Hellwig int q_depth; 961c63dc66SChristoph Hellwig u32 db_stride; 971c63dc66SChristoph Hellwig void __iomem *bar; 981c63dc66SChristoph Hellwig struct work_struct reset_work; 995c8809e6SChristoph Hellwig struct work_struct remove_work; 1002d55cd5fSChristoph Hellwig struct timer_list watchdog_timer; 10177bf25eaSKeith Busch struct mutex shutdown_lock; 1021c63dc66SChristoph Hellwig bool subsystem; 1031c63dc66SChristoph Hellwig void __iomem *cmb; 1041c63dc66SChristoph Hellwig dma_addr_t cmb_dma_addr; 1051c63dc66SChristoph Hellwig u64 cmb_size; 1061c63dc66SChristoph Hellwig u32 cmbsz; 107202021c1SStephen Bates u32 cmbloc; 1081c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 109db3cbfffSKeith Busch struct completion ioq_wait; 11087ad72a5SChristoph Hellwig 11187ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 112f9f38e33SHelen Koike u32 *dbbuf_dbs; 113f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 114f9f38e33SHelen Koike u32 *dbbuf_eis; 115f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 11687ad72a5SChristoph Hellwig 11787ad72a5SChristoph Hellwig /* host memory buffer support: */ 11887ad72a5SChristoph Hellwig u64 host_mem_size; 11987ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 12087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 12187ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 12257dacad5SJay Sternberg }; 12357dacad5SJay Sternberg 124f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 125f9f38e33SHelen Koike { 126f9f38e33SHelen Koike return qid * 2 * stride; 127f9f38e33SHelen Koike } 128f9f38e33SHelen Koike 129f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 130f9f38e33SHelen Koike { 131f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 132f9f38e33SHelen Koike } 133f9f38e33SHelen Koike 1341c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1351c63dc66SChristoph Hellwig { 1361c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1371c63dc66SChristoph Hellwig } 1381c63dc66SChristoph Hellwig 13957dacad5SJay Sternberg /* 14057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14157dacad5SJay Sternberg * commands and one for I/O commands). 14257dacad5SJay Sternberg */ 14357dacad5SJay Sternberg struct nvme_queue { 14457dacad5SJay Sternberg struct device *q_dmadev; 14557dacad5SJay Sternberg struct nvme_dev *dev; 14657dacad5SJay Sternberg spinlock_t q_lock; 14757dacad5SJay Sternberg struct nvme_command *sq_cmds; 14857dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 14957dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15057dacad5SJay Sternberg struct blk_mq_tags **tags; 15157dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15257dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15357dacad5SJay Sternberg u32 __iomem *q_db; 15457dacad5SJay Sternberg u16 q_depth; 15557dacad5SJay Sternberg s16 cq_vector; 15657dacad5SJay Sternberg u16 sq_tail; 15757dacad5SJay Sternberg u16 cq_head; 15857dacad5SJay Sternberg u16 qid; 15957dacad5SJay Sternberg u8 cq_phase; 16057dacad5SJay Sternberg u8 cqe_seen; 161f9f38e33SHelen Koike u32 *dbbuf_sq_db; 162f9f38e33SHelen Koike u32 *dbbuf_cq_db; 163f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 164f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16557dacad5SJay Sternberg }; 16657dacad5SJay Sternberg 16757dacad5SJay Sternberg /* 16871bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 16971bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 170f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17171bd150cSChristoph Hellwig * allocated to store the PRP list. 17271bd150cSChristoph Hellwig */ 17371bd150cSChristoph Hellwig struct nvme_iod { 174d49187e9SChristoph Hellwig struct nvme_request req; 175f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 176f4800d6dSChristoph Hellwig int aborted; 17771bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 17871bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 17971bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18071bd150cSChristoph Hellwig dma_addr_t first_dma; 181bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 182f4800d6dSChristoph Hellwig struct scatterlist *sg; 183f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18457dacad5SJay Sternberg }; 18557dacad5SJay Sternberg 18657dacad5SJay Sternberg /* 18757dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 18857dacad5SJay Sternberg */ 18957dacad5SJay Sternberg static inline void _nvme_check_size(void) 19057dacad5SJay Sternberg { 19157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 203f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 204f9f38e33SHelen Koike } 205f9f38e33SHelen Koike 206f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 207f9f38e33SHelen Koike { 208f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 209f9f38e33SHelen Koike } 210f9f38e33SHelen Koike 211f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 212f9f38e33SHelen Koike { 213f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 214f9f38e33SHelen Koike 215f9f38e33SHelen Koike if (dev->dbbuf_dbs) 216f9f38e33SHelen Koike return 0; 217f9f38e33SHelen Koike 218f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 219f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 220f9f38e33SHelen Koike GFP_KERNEL); 221f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 222f9f38e33SHelen Koike return -ENOMEM; 223f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 224f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 225f9f38e33SHelen Koike GFP_KERNEL); 226f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 227f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 228f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 229f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 230f9f38e33SHelen Koike return -ENOMEM; 231f9f38e33SHelen Koike } 232f9f38e33SHelen Koike 233f9f38e33SHelen Koike return 0; 234f9f38e33SHelen Koike } 235f9f38e33SHelen Koike 236f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 237f9f38e33SHelen Koike { 238f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 239f9f38e33SHelen Koike 240f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 241f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 242f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 243f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 244f9f38e33SHelen Koike } 245f9f38e33SHelen Koike if (dev->dbbuf_eis) { 246f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 247f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 248f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 249f9f38e33SHelen Koike } 250f9f38e33SHelen Koike } 251f9f38e33SHelen Koike 252f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 253f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 254f9f38e33SHelen Koike { 255f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 256f9f38e33SHelen Koike return; 257f9f38e33SHelen Koike 258f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 259f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 260f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 261f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 262f9f38e33SHelen Koike } 263f9f38e33SHelen Koike 264f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 265f9f38e33SHelen Koike { 266f9f38e33SHelen Koike struct nvme_command c; 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 269f9f38e33SHelen Koike return; 270f9f38e33SHelen Koike 271f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 272f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 273f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 274f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 275f9f38e33SHelen Koike 276f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2779bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 278f9f38e33SHelen Koike /* Free memory and continue on */ 279f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 280f9f38e33SHelen Koike } 281f9f38e33SHelen Koike } 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 284f9f38e33SHelen Koike { 285f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 289f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 290f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 291f9f38e33SHelen Koike { 292f9f38e33SHelen Koike if (dbbuf_db) { 293f9f38e33SHelen Koike u16 old_value; 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike /* 296f9f38e33SHelen Koike * Ensure that the queue is written before updating 297f9f38e33SHelen Koike * the doorbell in memory 298f9f38e33SHelen Koike */ 299f9f38e33SHelen Koike wmb(); 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike old_value = *dbbuf_db; 302f9f38e33SHelen Koike *dbbuf_db = value; 303f9f38e33SHelen Koike 304f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 305f9f38e33SHelen Koike return false; 306f9f38e33SHelen Koike } 307f9f38e33SHelen Koike 308f9f38e33SHelen Koike return true; 30957dacad5SJay Sternberg } 31057dacad5SJay Sternberg 31157dacad5SJay Sternberg /* 31257dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31357dacad5SJay Sternberg */ 31457dacad5SJay Sternberg #define NVME_INT_PAGES 2 3155fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 31657dacad5SJay Sternberg 31757dacad5SJay Sternberg /* 31857dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 31957dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32057dacad5SJay Sternberg * the I/O. 32157dacad5SJay Sternberg */ 32257dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32357dacad5SJay Sternberg { 3245fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3255fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 32657dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 32757dacad5SJay Sternberg } 32857dacad5SJay Sternberg 329f4800d6dSChristoph Hellwig static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, 330f4800d6dSChristoph Hellwig unsigned int size, unsigned int nseg) 331f4800d6dSChristoph Hellwig { 332f4800d6dSChristoph Hellwig return sizeof(__le64 *) * nvme_npages(size, dev) + 333f4800d6dSChristoph Hellwig sizeof(struct scatterlist) * nseg; 334f4800d6dSChristoph Hellwig } 335f4800d6dSChristoph Hellwig 33657dacad5SJay Sternberg static unsigned int nvme_cmd_size(struct nvme_dev *dev) 33757dacad5SJay Sternberg { 338f4800d6dSChristoph Hellwig return sizeof(struct nvme_iod) + 339f4800d6dSChristoph Hellwig nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); 34057dacad5SJay Sternberg } 34157dacad5SJay Sternberg 34257dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 34357dacad5SJay Sternberg unsigned int hctx_idx) 34457dacad5SJay Sternberg { 34557dacad5SJay Sternberg struct nvme_dev *dev = data; 34657dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 34757dacad5SJay Sternberg 34857dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 34957dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 35057dacad5SJay Sternberg WARN_ON(nvmeq->tags); 35157dacad5SJay Sternberg 35257dacad5SJay Sternberg hctx->driver_data = nvmeq; 35357dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 35457dacad5SJay Sternberg return 0; 35557dacad5SJay Sternberg } 35657dacad5SJay Sternberg 35757dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 35857dacad5SJay Sternberg { 35957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 36057dacad5SJay Sternberg 36157dacad5SJay Sternberg nvmeq->tags = NULL; 36257dacad5SJay Sternberg } 36357dacad5SJay Sternberg 364d6296d39SChristoph Hellwig static int nvme_admin_init_request(struct blk_mq_tag_set *set, 365d6296d39SChristoph Hellwig struct request *req, unsigned int hctx_idx, 36657dacad5SJay Sternberg unsigned int numa_node) 36757dacad5SJay Sternberg { 368d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 369f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 37057dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 37157dacad5SJay Sternberg 37257dacad5SJay Sternberg BUG_ON(!nvmeq); 373f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 37457dacad5SJay Sternberg return 0; 37557dacad5SJay Sternberg } 37657dacad5SJay Sternberg 37757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 37857dacad5SJay Sternberg unsigned int hctx_idx) 37957dacad5SJay Sternberg { 38057dacad5SJay Sternberg struct nvme_dev *dev = data; 38157dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg if (!nvmeq->tags) 38457dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 38557dacad5SJay Sternberg 38657dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 38757dacad5SJay Sternberg hctx->driver_data = nvmeq; 38857dacad5SJay Sternberg return 0; 38957dacad5SJay Sternberg } 39057dacad5SJay Sternberg 391d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 392d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 39357dacad5SJay Sternberg { 394d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 395f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 39657dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 39757dacad5SJay Sternberg 39857dacad5SJay Sternberg BUG_ON(!nvmeq); 399f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 40057dacad5SJay Sternberg return 0; 40157dacad5SJay Sternberg } 40257dacad5SJay Sternberg 403dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 404dca51e78SChristoph Hellwig { 405dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 406dca51e78SChristoph Hellwig 407dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 408dca51e78SChristoph Hellwig } 409dca51e78SChristoph Hellwig 41057dacad5SJay Sternberg /** 411adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 41257dacad5SJay Sternberg * @nvmeq: The queue to use 41357dacad5SJay Sternberg * @cmd: The command to send 41457dacad5SJay Sternberg * 41557dacad5SJay Sternberg * Safe to use from interrupt context 41657dacad5SJay Sternberg */ 41757dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 41857dacad5SJay Sternberg struct nvme_command *cmd) 41957dacad5SJay Sternberg { 42057dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 42157dacad5SJay Sternberg 42257dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 42357dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 42457dacad5SJay Sternberg else 42557dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 42857dacad5SJay Sternberg tail = 0; 429f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 430f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 43157dacad5SJay Sternberg writel(tail, nvmeq->q_db); 43257dacad5SJay Sternberg nvmeq->sq_tail = tail; 43357dacad5SJay Sternberg } 43457dacad5SJay Sternberg 435f4800d6dSChristoph Hellwig static __le64 **iod_list(struct request *req) 43657dacad5SJay Sternberg { 437f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 438f9d03f96SChristoph Hellwig return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); 43957dacad5SJay Sternberg } 44057dacad5SJay Sternberg 441fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 44257dacad5SJay Sternberg { 443f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 444f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 445b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 446f4800d6dSChristoph Hellwig 447f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 448f4800d6dSChristoph Hellwig iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); 449f4800d6dSChristoph Hellwig if (!iod->sg) 450fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 451f4800d6dSChristoph Hellwig } else { 452f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 45357dacad5SJay Sternberg } 45457dacad5SJay Sternberg 455f4800d6dSChristoph Hellwig iod->aborted = 0; 45657dacad5SJay Sternberg iod->npages = -1; 45757dacad5SJay Sternberg iod->nents = 0; 458f4800d6dSChristoph Hellwig iod->length = size; 459f80ec966SKeith Busch 460fc17b653SChristoph Hellwig return BLK_STS_OK; 46157dacad5SJay Sternberg } 46257dacad5SJay Sternberg 463f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 46457dacad5SJay Sternberg { 465f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4665fd4ce1bSChristoph Hellwig const int last_prp = dev->ctrl.page_size / 8 - 1; 46757dacad5SJay Sternberg int i; 468f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 46957dacad5SJay Sternberg dma_addr_t prp_dma = iod->first_dma; 47057dacad5SJay Sternberg 47157dacad5SJay Sternberg if (iod->npages == 0) 47257dacad5SJay Sternberg dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 47357dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 47457dacad5SJay Sternberg __le64 *prp_list = list[i]; 47557dacad5SJay Sternberg dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 47657dacad5SJay Sternberg dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 47757dacad5SJay Sternberg prp_dma = next_prp_dma; 47857dacad5SJay Sternberg } 47957dacad5SJay Sternberg 480f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 481f4800d6dSChristoph Hellwig kfree(iod->sg); 48257dacad5SJay Sternberg } 48357dacad5SJay Sternberg 48457dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 48557dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 48657dacad5SJay Sternberg { 48757dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 48857dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 48957dacad5SJay Sternberg } 49057dacad5SJay Sternberg 49157dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 49257dacad5SJay Sternberg { 49357dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 49457dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 49557dacad5SJay Sternberg } 49657dacad5SJay Sternberg 49757dacad5SJay Sternberg /** 49857dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 49957dacad5SJay Sternberg * 50057dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 50157dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 50257dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 50357dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 50457dacad5SJay Sternberg * 50557dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 50657dacad5SJay Sternberg */ 50757dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 50857dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 50957dacad5SJay Sternberg { 51057dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 51157dacad5SJay Sternberg struct bio_integrity_payload *bip; 51257dacad5SJay Sternberg struct t10_pi_tuple *pi; 51357dacad5SJay Sternberg void *p, *pmap; 51457dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 51557dacad5SJay Sternberg 51657dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 51757dacad5SJay Sternberg return; 51857dacad5SJay Sternberg 51957dacad5SJay Sternberg bip = bio_integrity(req->bio); 52057dacad5SJay Sternberg if (!bip) 52157dacad5SJay Sternberg return; 52257dacad5SJay Sternberg 52357dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 52457dacad5SJay Sternberg 52557dacad5SJay Sternberg p = pmap; 52657dacad5SJay Sternberg virt = bip_get_seed(bip); 52757dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 52857dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 529ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 53057dacad5SJay Sternberg 53157dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 53257dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 53357dacad5SJay Sternberg dif_swap(phys, virt, pi); 53457dacad5SJay Sternberg p += ts; 53557dacad5SJay Sternberg } 53657dacad5SJay Sternberg kunmap_atomic(pmap); 53757dacad5SJay Sternberg } 53857dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 53957dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 54057dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 54157dacad5SJay Sternberg { 54257dacad5SJay Sternberg } 54357dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 54457dacad5SJay Sternberg { 54557dacad5SJay Sternberg } 54657dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54757dacad5SJay Sternberg { 54857dacad5SJay Sternberg } 54957dacad5SJay Sternberg #endif 55057dacad5SJay Sternberg 551b131c61dSChristoph Hellwig static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) 55257dacad5SJay Sternberg { 553f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 55457dacad5SJay Sternberg struct dma_pool *pool; 555b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 55657dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 55757dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 55857dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5595fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 56057dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 56157dacad5SJay Sternberg __le64 *prp_list; 562f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 56357dacad5SJay Sternberg dma_addr_t prp_dma; 56457dacad5SJay Sternberg int nprps, i; 56557dacad5SJay Sternberg 56657dacad5SJay Sternberg length -= (page_size - offset); 56757dacad5SJay Sternberg if (length <= 0) 56869d2b571SChristoph Hellwig return true; 56957dacad5SJay Sternberg 57057dacad5SJay Sternberg dma_len -= (page_size - offset); 57157dacad5SJay Sternberg if (dma_len) { 57257dacad5SJay Sternberg dma_addr += (page_size - offset); 57357dacad5SJay Sternberg } else { 57457dacad5SJay Sternberg sg = sg_next(sg); 57557dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 57657dacad5SJay Sternberg dma_len = sg_dma_len(sg); 57757dacad5SJay Sternberg } 57857dacad5SJay Sternberg 57957dacad5SJay Sternberg if (length <= page_size) { 58057dacad5SJay Sternberg iod->first_dma = dma_addr; 58169d2b571SChristoph Hellwig return true; 58257dacad5SJay Sternberg } 58357dacad5SJay Sternberg 58457dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 58557dacad5SJay Sternberg if (nprps <= (256 / 8)) { 58657dacad5SJay Sternberg pool = dev->prp_small_pool; 58757dacad5SJay Sternberg iod->npages = 0; 58857dacad5SJay Sternberg } else { 58957dacad5SJay Sternberg pool = dev->prp_page_pool; 59057dacad5SJay Sternberg iod->npages = 1; 59157dacad5SJay Sternberg } 59257dacad5SJay Sternberg 59369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 59457dacad5SJay Sternberg if (!prp_list) { 59557dacad5SJay Sternberg iod->first_dma = dma_addr; 59657dacad5SJay Sternberg iod->npages = -1; 59769d2b571SChristoph Hellwig return false; 59857dacad5SJay Sternberg } 59957dacad5SJay Sternberg list[0] = prp_list; 60057dacad5SJay Sternberg iod->first_dma = prp_dma; 60157dacad5SJay Sternberg i = 0; 60257dacad5SJay Sternberg for (;;) { 60357dacad5SJay Sternberg if (i == page_size >> 3) { 60457dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 60569d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 60657dacad5SJay Sternberg if (!prp_list) 60769d2b571SChristoph Hellwig return false; 60857dacad5SJay Sternberg list[iod->npages++] = prp_list; 60957dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 61057dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 61157dacad5SJay Sternberg i = 1; 61257dacad5SJay Sternberg } 61357dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 61457dacad5SJay Sternberg dma_len -= page_size; 61557dacad5SJay Sternberg dma_addr += page_size; 61657dacad5SJay Sternberg length -= page_size; 61757dacad5SJay Sternberg if (length <= 0) 61857dacad5SJay Sternberg break; 61957dacad5SJay Sternberg if (dma_len > 0) 62057dacad5SJay Sternberg continue; 62157dacad5SJay Sternberg BUG_ON(dma_len < 0); 62257dacad5SJay Sternberg sg = sg_next(sg); 62357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 62457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62557dacad5SJay Sternberg } 62657dacad5SJay Sternberg 62769d2b571SChristoph Hellwig return true; 62857dacad5SJay Sternberg } 62957dacad5SJay Sternberg 630fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 631b131c61dSChristoph Hellwig struct nvme_command *cmnd) 63257dacad5SJay Sternberg { 633f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 634ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 635ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 636ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 637fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 63857dacad5SJay Sternberg 639f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 640ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 641ba1ca37eSChristoph Hellwig if (!iod->nents) 642ba1ca37eSChristoph Hellwig goto out; 643ba1ca37eSChristoph Hellwig 644fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 6452b6b535dSMauricio Faria de Oliveira if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 6462b6b535dSMauricio Faria de Oliveira DMA_ATTR_NO_WARN)) 647ba1ca37eSChristoph Hellwig goto out; 648ba1ca37eSChristoph Hellwig 649b131c61dSChristoph Hellwig if (!nvme_setup_prps(dev, req)) 650ba1ca37eSChristoph Hellwig goto out_unmap; 651ba1ca37eSChristoph Hellwig 652fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 653ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 654ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 655ba1ca37eSChristoph Hellwig goto out_unmap; 656ba1ca37eSChristoph Hellwig 657bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 658bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 659ba1ca37eSChristoph Hellwig goto out_unmap; 660ba1ca37eSChristoph Hellwig 661ba1ca37eSChristoph Hellwig if (rq_data_dir(req)) 662ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 663ba1ca37eSChristoph Hellwig 664bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 665ba1ca37eSChristoph Hellwig goto out_unmap; 66657dacad5SJay Sternberg } 66757dacad5SJay Sternberg 668eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 669eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); 670ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 671bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 672fc17b653SChristoph Hellwig return BLK_STS_OK; 673ba1ca37eSChristoph Hellwig 674ba1ca37eSChristoph Hellwig out_unmap: 675ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 676ba1ca37eSChristoph Hellwig out: 677ba1ca37eSChristoph Hellwig return ret; 67857dacad5SJay Sternberg } 67957dacad5SJay Sternberg 680f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 681d4f6c3abSChristoph Hellwig { 682f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 683d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 684d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 685d4f6c3abSChristoph Hellwig 686d4f6c3abSChristoph Hellwig if (iod->nents) { 687d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 688d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 689d4f6c3abSChristoph Hellwig if (!rq_data_dir(req)) 690d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 691bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 692d4f6c3abSChristoph Hellwig } 693d4f6c3abSChristoph Hellwig } 694d4f6c3abSChristoph Hellwig 695f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 696f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 69757dacad5SJay Sternberg } 69857dacad5SJay Sternberg 69957dacad5SJay Sternberg /* 70057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 70157dacad5SJay Sternberg */ 702fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 70357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 70457dacad5SJay Sternberg { 70557dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 70657dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 70757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 70857dacad5SJay Sternberg struct request *req = bd->rq; 709ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 710fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_OK; 71157dacad5SJay Sternberg 71257dacad5SJay Sternberg /* 71357dacad5SJay Sternberg * If formated with metadata, require the block layer provide a buffer 71457dacad5SJay Sternberg * unless this namespace is formated such that the metadata can be 71557dacad5SJay Sternberg * stripped/generated by the controller with PRACT=1. 71657dacad5SJay Sternberg */ 71757dacad5SJay Sternberg if (ns && ns->ms && !blk_integrity_rq(req)) { 71857dacad5SJay Sternberg if (!(ns->pi_type && ns->ms == 8) && 719fc17b653SChristoph Hellwig !blk_rq_is_passthrough(req)) 720fc17b653SChristoph Hellwig return BLK_STS_NOTSUPP; 72157dacad5SJay Sternberg } 72257dacad5SJay Sternberg 723f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 724fc17b653SChristoph Hellwig if (ret) 725f4800d6dSChristoph Hellwig return ret; 72657dacad5SJay Sternberg 727b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 728fc17b653SChristoph Hellwig if (ret) 729f9d03f96SChristoph Hellwig goto out_free_cmd; 73057dacad5SJay Sternberg 731fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 732b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 733fc17b653SChristoph Hellwig if (ret) 734f9d03f96SChristoph Hellwig goto out_cleanup_iod; 735fc17b653SChristoph Hellwig } 736ba1ca37eSChristoph Hellwig 737aae239e1SChristoph Hellwig blk_mq_start_request(req); 738ba1ca37eSChristoph Hellwig 739ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 740ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 741fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 742ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 743f9d03f96SChristoph Hellwig goto out_cleanup_iod; 744ae1fba20SKeith Busch } 745ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 74657dacad5SJay Sternberg nvme_process_cq(nvmeq); 74757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 748fc17b653SChristoph Hellwig return BLK_STS_OK; 749f9d03f96SChristoph Hellwig out_cleanup_iod: 750f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 751f9d03f96SChristoph Hellwig out_free_cmd: 752f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 753ba1ca37eSChristoph Hellwig return ret; 75457dacad5SJay Sternberg } 75557dacad5SJay Sternberg 75677f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 757eee417b0SChristoph Hellwig { 758f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 759eee417b0SChristoph Hellwig 76077f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 76177f02a7aSChristoph Hellwig nvme_complete_rq(req); 76257dacad5SJay Sternberg } 76357dacad5SJay Sternberg 764d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 765d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 766d783e0bdSMarta Rybczynska u16 phase) 767d783e0bdSMarta Rybczynska { 768d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 769d783e0bdSMarta Rybczynska } 770d783e0bdSMarta Rybczynska 771a0fa9647SJens Axboe static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) 77257dacad5SJay Sternberg { 77357dacad5SJay Sternberg u16 head, phase; 77457dacad5SJay Sternberg 77557dacad5SJay Sternberg head = nvmeq->cq_head; 77657dacad5SJay Sternberg phase = nvmeq->cq_phase; 77757dacad5SJay Sternberg 778d783e0bdSMarta Rybczynska while (nvme_cqe_valid(nvmeq, head, phase)) { 77957dacad5SJay Sternberg struct nvme_completion cqe = nvmeq->cqes[head]; 780eee417b0SChristoph Hellwig struct request *req; 781adf68f21SChristoph Hellwig 78257dacad5SJay Sternberg if (++head == nvmeq->q_depth) { 78357dacad5SJay Sternberg head = 0; 78457dacad5SJay Sternberg phase = !phase; 78557dacad5SJay Sternberg } 786adf68f21SChristoph Hellwig 787a0fa9647SJens Axboe if (tag && *tag == cqe.command_id) 788a0fa9647SJens Axboe *tag = -1; 789adf68f21SChristoph Hellwig 790aae239e1SChristoph Hellwig if (unlikely(cqe.command_id >= nvmeq->q_depth)) { 7911b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 792aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 793aae239e1SChristoph Hellwig cqe.command_id, le16_to_cpu(cqe.sq_id)); 794aae239e1SChristoph Hellwig continue; 795aae239e1SChristoph Hellwig } 796aae239e1SChristoph Hellwig 797adf68f21SChristoph Hellwig /* 798adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 799adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 800adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 801adf68f21SChristoph Hellwig * for them but rather special case them here. 802adf68f21SChristoph Hellwig */ 803adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 804adf68f21SChristoph Hellwig cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { 8057bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 8067bf58533SChristoph Hellwig cqe.status, &cqe.result); 807adf68f21SChristoph Hellwig continue; 808adf68f21SChristoph Hellwig } 809adf68f21SChristoph Hellwig 810eee417b0SChristoph Hellwig req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); 81127fa9bc5SChristoph Hellwig nvme_end_request(req, cqe.status, cqe.result); 81257dacad5SJay Sternberg } 81357dacad5SJay Sternberg 81457dacad5SJay Sternberg if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) 815a0fa9647SJens Axboe return; 81657dacad5SJay Sternberg 817604e8c8dSKeith Busch if (likely(nvmeq->cq_vector >= 0)) 818f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 819f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei)) 82057dacad5SJay Sternberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 82157dacad5SJay Sternberg nvmeq->cq_head = head; 82257dacad5SJay Sternberg nvmeq->cq_phase = phase; 82357dacad5SJay Sternberg 82457dacad5SJay Sternberg nvmeq->cqe_seen = 1; 825a0fa9647SJens Axboe } 826a0fa9647SJens Axboe 827a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 828a0fa9647SJens Axboe { 829a0fa9647SJens Axboe __nvme_process_cq(nvmeq, NULL); 83057dacad5SJay Sternberg } 83157dacad5SJay Sternberg 83257dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 83357dacad5SJay Sternberg { 83457dacad5SJay Sternberg irqreturn_t result; 83557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 83657dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 83757dacad5SJay Sternberg nvme_process_cq(nvmeq); 83857dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 83957dacad5SJay Sternberg nvmeq->cqe_seen = 0; 84057dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 84157dacad5SJay Sternberg return result; 84257dacad5SJay Sternberg } 84357dacad5SJay Sternberg 84457dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 84557dacad5SJay Sternberg { 84657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 847d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 84857dacad5SJay Sternberg return IRQ_WAKE_THREAD; 849d783e0bdSMarta Rybczynska return IRQ_NONE; 85057dacad5SJay Sternberg } 85157dacad5SJay Sternberg 8527776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 853a0fa9647SJens Axboe { 854d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 855a0fa9647SJens Axboe spin_lock_irq(&nvmeq->q_lock); 856a0fa9647SJens Axboe __nvme_process_cq(nvmeq, &tag); 857a0fa9647SJens Axboe spin_unlock_irq(&nvmeq->q_lock); 858a0fa9647SJens Axboe 859a0fa9647SJens Axboe if (tag == -1) 860a0fa9647SJens Axboe return 1; 861a0fa9647SJens Axboe } 862a0fa9647SJens Axboe 863a0fa9647SJens Axboe return 0; 864a0fa9647SJens Axboe } 865a0fa9647SJens Axboe 8667776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 8677776db1cSKeith Busch { 8687776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 8697776db1cSKeith Busch 8707776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 8717776db1cSKeith Busch } 8727776db1cSKeith Busch 873f866fc42SChristoph Hellwig static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) 87457dacad5SJay Sternberg { 875f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 8769396dec9SChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[0]; 87757dacad5SJay Sternberg struct nvme_command c; 87857dacad5SJay Sternberg 87957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 88057dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 881f866fc42SChristoph Hellwig c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; 88257dacad5SJay Sternberg 8839396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 8849396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 8859396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 88657dacad5SJay Sternberg } 88757dacad5SJay Sternberg 88857dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 88957dacad5SJay Sternberg { 89057dacad5SJay Sternberg struct nvme_command c; 89157dacad5SJay Sternberg 89257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 89357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 89457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 89557dacad5SJay Sternberg 8961c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 89757dacad5SJay Sternberg } 89857dacad5SJay Sternberg 89957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 90057dacad5SJay Sternberg struct nvme_queue *nvmeq) 90157dacad5SJay Sternberg { 90257dacad5SJay Sternberg struct nvme_command c; 90357dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 90457dacad5SJay Sternberg 90557dacad5SJay Sternberg /* 90657dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 90757dacad5SJay Sternberg * is attached to the request. 90857dacad5SJay Sternberg */ 90957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 91057dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 91157dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 91257dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 91357dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 91457dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 91557dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 91657dacad5SJay Sternberg 9171c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 91857dacad5SJay Sternberg } 91957dacad5SJay Sternberg 92057dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 92157dacad5SJay Sternberg struct nvme_queue *nvmeq) 92257dacad5SJay Sternberg { 92357dacad5SJay Sternberg struct nvme_command c; 92481c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 92557dacad5SJay Sternberg 92657dacad5SJay Sternberg /* 92757dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 92857dacad5SJay Sternberg * is attached to the request. 92957dacad5SJay Sternberg */ 93057dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 93157dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 93257dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 93357dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 93457dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 93557dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 93657dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 93757dacad5SJay Sternberg 9381c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 93957dacad5SJay Sternberg } 94057dacad5SJay Sternberg 94157dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 94257dacad5SJay Sternberg { 94357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 94457dacad5SJay Sternberg } 94557dacad5SJay Sternberg 94657dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 94757dacad5SJay Sternberg { 94857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 94957dacad5SJay Sternberg } 95057dacad5SJay Sternberg 9512a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 95257dacad5SJay Sternberg { 953f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 954f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 95557dacad5SJay Sternberg 95627fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 95727fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 958e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 959e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 96057dacad5SJay Sternberg } 96157dacad5SJay Sternberg 96231c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 96357dacad5SJay Sternberg { 964f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 965f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 96657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 96757dacad5SJay Sternberg struct request *abort_req; 96857dacad5SJay Sternberg struct nvme_command cmd; 96957dacad5SJay Sternberg 97031c7c7d2SChristoph Hellwig /* 9717776db1cSKeith Busch * Did we miss an interrupt? 9727776db1cSKeith Busch */ 9737776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 9747776db1cSKeith Busch dev_warn(dev->ctrl.device, 9757776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 9767776db1cSKeith Busch req->tag, nvmeq->qid); 9777776db1cSKeith Busch return BLK_EH_HANDLED; 9787776db1cSKeith Busch } 9797776db1cSKeith Busch 9807776db1cSKeith Busch /* 981fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 982fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 983fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 984fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 985fd634f41SChristoph Hellwig */ 986bb8d261eSChristoph Hellwig if (dev->ctrl.state == NVME_CTRL_RESETTING) { 9871b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 988fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 989fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 990a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 99127fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 992fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 993fd634f41SChristoph Hellwig } 994fd634f41SChristoph Hellwig 995fd634f41SChristoph Hellwig /* 996e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 997e1569a16SKeith Busch * command was already aborted once before and still hasn't been 998e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 99931c7c7d2SChristoph Hellwig */ 1000f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 10011b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 100257dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 100357dacad5SJay Sternberg req->tag, nvmeq->qid); 1004a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1005c5f6ce97SKeith Busch nvme_reset(dev); 1006e1569a16SKeith Busch 1007e1569a16SKeith Busch /* 1008e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1009e1569a16SKeith Busch * forces all outstanding requests to complete. 1010e1569a16SKeith Busch */ 101127fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1012e1569a16SKeith Busch return BLK_EH_HANDLED; 101357dacad5SJay Sternberg } 101457dacad5SJay Sternberg 1015e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1016e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1017e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1018e7a2a87dSChristoph Hellwig } 10197bf7d778SKeith Busch iod->aborted = 1; 102057dacad5SJay Sternberg 102157dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 102257dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 102357dacad5SJay Sternberg cmd.abort.cid = req->tag; 102457dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 102557dacad5SJay Sternberg 10261b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 10271b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 102857dacad5SJay Sternberg req->tag, nvmeq->qid); 1029e7a2a87dSChristoph Hellwig 1030e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1031eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 10326bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 10336bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 103431c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 103557dacad5SJay Sternberg } 103657dacad5SJay Sternberg 1037e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1038e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1039e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 104057dacad5SJay Sternberg 104157dacad5SJay Sternberg /* 104257dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 104357dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 104457dacad5SJay Sternberg * as the device then is in a faulty state. 104557dacad5SJay Sternberg */ 104657dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 104757dacad5SJay Sternberg } 104857dacad5SJay Sternberg 104957dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 105057dacad5SJay Sternberg { 105157dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 105257dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 105357dacad5SJay Sternberg if (nvmeq->sq_cmds) 105457dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 105557dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 105657dacad5SJay Sternberg kfree(nvmeq); 105757dacad5SJay Sternberg } 105857dacad5SJay Sternberg 105957dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 106057dacad5SJay Sternberg { 106157dacad5SJay Sternberg int i; 106257dacad5SJay Sternberg 106357dacad5SJay Sternberg for (i = dev->queue_count - 1; i >= lowest; i--) { 106457dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[i]; 106557dacad5SJay Sternberg dev->queue_count--; 106657dacad5SJay Sternberg dev->queues[i] = NULL; 106757dacad5SJay Sternberg nvme_free_queue(nvmeq); 106857dacad5SJay Sternberg } 106957dacad5SJay Sternberg } 107057dacad5SJay Sternberg 107157dacad5SJay Sternberg /** 107257dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 107357dacad5SJay Sternberg * @nvmeq - queue to suspend 107457dacad5SJay Sternberg */ 107557dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 107657dacad5SJay Sternberg { 107757dacad5SJay Sternberg int vector; 107857dacad5SJay Sternberg 107957dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 108057dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 108157dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 108257dacad5SJay Sternberg return 1; 108357dacad5SJay Sternberg } 10840ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 108557dacad5SJay Sternberg nvmeq->dev->online_queues--; 108657dacad5SJay Sternberg nvmeq->cq_vector = -1; 108757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 108857dacad5SJay Sternberg 10891c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 109025646264SKeith Busch blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); 109157dacad5SJay Sternberg 10920ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 109357dacad5SJay Sternberg 109457dacad5SJay Sternberg return 0; 109557dacad5SJay Sternberg } 109657dacad5SJay Sternberg 1097a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 109857dacad5SJay Sternberg { 1099a5cdb68cSKeith Busch struct nvme_queue *nvmeq = dev->queues[0]; 110057dacad5SJay Sternberg 110157dacad5SJay Sternberg if (!nvmeq) 110257dacad5SJay Sternberg return; 110357dacad5SJay Sternberg if (nvme_suspend_queue(nvmeq)) 110457dacad5SJay Sternberg return; 110557dacad5SJay Sternberg 1106a5cdb68cSKeith Busch if (shutdown) 1107a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1108a5cdb68cSKeith Busch else 1109a5cdb68cSKeith Busch nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( 1110a5cdb68cSKeith Busch dev->bar + NVME_REG_CAP)); 111157dacad5SJay Sternberg 111257dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 111357dacad5SJay Sternberg nvme_process_cq(nvmeq); 111457dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 111557dacad5SJay Sternberg } 111657dacad5SJay Sternberg 111757dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 111857dacad5SJay Sternberg int entry_size) 111957dacad5SJay Sternberg { 112057dacad5SJay Sternberg int q_depth = dev->q_depth; 11215fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 11225fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 112357dacad5SJay Sternberg 112457dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 112557dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 11265fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 112757dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 112857dacad5SJay Sternberg 112957dacad5SJay Sternberg /* 113057dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 113157dacad5SJay Sternberg * would be better to map queues in system memory with the 113257dacad5SJay Sternberg * original depth 113357dacad5SJay Sternberg */ 113457dacad5SJay Sternberg if (q_depth < 64) 113557dacad5SJay Sternberg return -ENOMEM; 113657dacad5SJay Sternberg } 113757dacad5SJay Sternberg 113857dacad5SJay Sternberg return q_depth; 113957dacad5SJay Sternberg } 114057dacad5SJay Sternberg 114157dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 114257dacad5SJay Sternberg int qid, int depth) 114357dacad5SJay Sternberg { 114457dacad5SJay Sternberg if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 11455fd4ce1bSChristoph Hellwig unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 11465fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 114757dacad5SJay Sternberg nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 114857dacad5SJay Sternberg nvmeq->sq_cmds_io = dev->cmb + offset; 114957dacad5SJay Sternberg } else { 115057dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 115157dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 115257dacad5SJay Sternberg if (!nvmeq->sq_cmds) 115357dacad5SJay Sternberg return -ENOMEM; 115457dacad5SJay Sternberg } 115557dacad5SJay Sternberg 115657dacad5SJay Sternberg return 0; 115757dacad5SJay Sternberg } 115857dacad5SJay Sternberg 115957dacad5SJay Sternberg static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1160d3af3ecdSShaohua Li int depth, int node) 116157dacad5SJay Sternberg { 1162d3af3ecdSShaohua Li struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, 1163d3af3ecdSShaohua Li node); 116457dacad5SJay Sternberg if (!nvmeq) 116557dacad5SJay Sternberg return NULL; 116657dacad5SJay Sternberg 116757dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 116857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 116957dacad5SJay Sternberg if (!nvmeq->cqes) 117057dacad5SJay Sternberg goto free_nvmeq; 117157dacad5SJay Sternberg 117257dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 117357dacad5SJay Sternberg goto free_cqdma; 117457dacad5SJay Sternberg 117557dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 117657dacad5SJay Sternberg nvmeq->dev = dev; 117757dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 117857dacad5SJay Sternberg nvmeq->cq_head = 0; 117957dacad5SJay Sternberg nvmeq->cq_phase = 1; 118057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 118157dacad5SJay Sternberg nvmeq->q_depth = depth; 118257dacad5SJay Sternberg nvmeq->qid = qid; 118357dacad5SJay Sternberg nvmeq->cq_vector = -1; 118457dacad5SJay Sternberg dev->queues[qid] = nvmeq; 118557dacad5SJay Sternberg dev->queue_count++; 118657dacad5SJay Sternberg 118757dacad5SJay Sternberg return nvmeq; 118857dacad5SJay Sternberg 118957dacad5SJay Sternberg free_cqdma: 119057dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 119157dacad5SJay Sternberg nvmeq->cq_dma_addr); 119257dacad5SJay Sternberg free_nvmeq: 119357dacad5SJay Sternberg kfree(nvmeq); 119457dacad5SJay Sternberg return NULL; 119557dacad5SJay Sternberg } 119657dacad5SJay Sternberg 1197dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 119857dacad5SJay Sternberg { 11990ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 12000ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 12010ff199cbSChristoph Hellwig 12020ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 12030ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 12040ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12050ff199cbSChristoph Hellwig } else { 12060ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 12070ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12080ff199cbSChristoph Hellwig } 120957dacad5SJay Sternberg } 121057dacad5SJay Sternberg 121157dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 121257dacad5SJay Sternberg { 121357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 121457dacad5SJay Sternberg 121557dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 121657dacad5SJay Sternberg nvmeq->sq_tail = 0; 121757dacad5SJay Sternberg nvmeq->cq_head = 0; 121857dacad5SJay Sternberg nvmeq->cq_phase = 1; 121957dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 122057dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1221f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 122257dacad5SJay Sternberg dev->online_queues++; 122357dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 122457dacad5SJay Sternberg } 122557dacad5SJay Sternberg 122657dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 122757dacad5SJay Sternberg { 122857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 122957dacad5SJay Sternberg int result; 123057dacad5SJay Sternberg 123157dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 123257dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 123357dacad5SJay Sternberg if (result < 0) 123457dacad5SJay Sternberg return result; 123557dacad5SJay Sternberg 123657dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 123757dacad5SJay Sternberg if (result < 0) 123857dacad5SJay Sternberg goto release_cq; 123957dacad5SJay Sternberg 1240dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 124157dacad5SJay Sternberg if (result < 0) 124257dacad5SJay Sternberg goto release_sq; 124357dacad5SJay Sternberg 124457dacad5SJay Sternberg nvme_init_queue(nvmeq, qid); 124557dacad5SJay Sternberg return result; 124657dacad5SJay Sternberg 124757dacad5SJay Sternberg release_sq: 124857dacad5SJay Sternberg adapter_delete_sq(dev, qid); 124957dacad5SJay Sternberg release_cq: 125057dacad5SJay Sternberg adapter_delete_cq(dev, qid); 125157dacad5SJay Sternberg return result; 125257dacad5SJay Sternberg } 125357dacad5SJay Sternberg 1254f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 125557dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 125677f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 125757dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 125857dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 125957dacad5SJay Sternberg .init_request = nvme_admin_init_request, 126057dacad5SJay Sternberg .timeout = nvme_timeout, 126157dacad5SJay Sternberg }; 126257dacad5SJay Sternberg 1263f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 126457dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 126577f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 126657dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 126757dacad5SJay Sternberg .init_request = nvme_init_request, 1268dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 126957dacad5SJay Sternberg .timeout = nvme_timeout, 1270a0fa9647SJens Axboe .poll = nvme_poll, 127157dacad5SJay Sternberg }; 127257dacad5SJay Sternberg 127357dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 127457dacad5SJay Sternberg { 12751c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 127669d9a99cSKeith Busch /* 127769d9a99cSKeith Busch * If the controller was reset during removal, it's possible 127869d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 127969d9a99cSKeith Busch * queue to flush these to completion. 128069d9a99cSKeith Busch */ 128169d9a99cSKeith Busch blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); 12821c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 128357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 128457dacad5SJay Sternberg } 128557dacad5SJay Sternberg } 128657dacad5SJay Sternberg 128757dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 128857dacad5SJay Sternberg { 12891c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 129057dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 129157dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1292e3e9d50cSKeith Busch 1293e3e9d50cSKeith Busch /* 1294e3e9d50cSKeith Busch * Subtract one to leave an empty queue entry for 'Full Queue' 1295e3e9d50cSKeith Busch * condition. See NVM-Express 1.2 specification, section 4.1.2. 1296e3e9d50cSKeith Busch */ 1297e3e9d50cSKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; 129857dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 129957dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 130057dacad5SJay Sternberg dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1301d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 130257dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 130357dacad5SJay Sternberg 130457dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 130557dacad5SJay Sternberg return -ENOMEM; 130657dacad5SJay Sternberg 13071c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 13081c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 130957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 131057dacad5SJay Sternberg return -ENOMEM; 131157dacad5SJay Sternberg } 13121c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 131357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 13141c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 131557dacad5SJay Sternberg return -ENODEV; 131657dacad5SJay Sternberg } 131757dacad5SJay Sternberg } else 131825646264SKeith Busch blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); 131957dacad5SJay Sternberg 132057dacad5SJay Sternberg return 0; 132157dacad5SJay Sternberg } 132257dacad5SJay Sternberg 132357dacad5SJay Sternberg static int nvme_configure_admin_queue(struct nvme_dev *dev) 132457dacad5SJay Sternberg { 132557dacad5SJay Sternberg int result; 132657dacad5SJay Sternberg u32 aqa; 13277a67cbeaSChristoph Hellwig u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 132857dacad5SJay Sternberg struct nvme_queue *nvmeq; 132957dacad5SJay Sternberg 13308ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 133157dacad5SJay Sternberg NVME_CAP_NSSRC(cap) : 0; 133257dacad5SJay Sternberg 13337a67cbeaSChristoph Hellwig if (dev->subsystem && 13347a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 13357a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 133657dacad5SJay Sternberg 13375fd4ce1bSChristoph Hellwig result = nvme_disable_ctrl(&dev->ctrl, cap); 133857dacad5SJay Sternberg if (result < 0) 133957dacad5SJay Sternberg return result; 134057dacad5SJay Sternberg 134157dacad5SJay Sternberg nvmeq = dev->queues[0]; 134257dacad5SJay Sternberg if (!nvmeq) { 1343d3af3ecdSShaohua Li nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1344d3af3ecdSShaohua Li dev_to_node(dev->dev)); 134557dacad5SJay Sternberg if (!nvmeq) 134657dacad5SJay Sternberg return -ENOMEM; 134757dacad5SJay Sternberg } 134857dacad5SJay Sternberg 134957dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 135057dacad5SJay Sternberg aqa |= aqa << 16; 135157dacad5SJay Sternberg 13527a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 13537a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 13547a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 135557dacad5SJay Sternberg 13565fd4ce1bSChristoph Hellwig result = nvme_enable_ctrl(&dev->ctrl, cap); 135757dacad5SJay Sternberg if (result) 1358d4875622SKeith Busch return result; 135957dacad5SJay Sternberg 136057dacad5SJay Sternberg nvmeq->cq_vector = 0; 1361dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 136257dacad5SJay Sternberg if (result) { 136357dacad5SJay Sternberg nvmeq->cq_vector = -1; 1364d4875622SKeith Busch return result; 136557dacad5SJay Sternberg } 136657dacad5SJay Sternberg 136757dacad5SJay Sternberg return result; 136857dacad5SJay Sternberg } 136957dacad5SJay Sternberg 1370c875a709SGuilherme G. Piccoli static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1371c875a709SGuilherme G. Piccoli { 1372c875a709SGuilherme G. Piccoli 1373c875a709SGuilherme G. Piccoli /* If true, indicates loss of adapter communication, possibly by a 1374c875a709SGuilherme G. Piccoli * NVMe Subsystem reset. 1375c875a709SGuilherme G. Piccoli */ 1376c875a709SGuilherme G. Piccoli bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1377c875a709SGuilherme G. Piccoli 1378c875a709SGuilherme G. Piccoli /* If there is a reset ongoing, we shouldn't reset again. */ 137982b057caSRakesh Pandit if (dev->ctrl.state == NVME_CTRL_RESETTING) 1380c875a709SGuilherme G. Piccoli return false; 1381c875a709SGuilherme G. Piccoli 1382c875a709SGuilherme G. Piccoli /* We shouldn't reset unless the controller is on fatal error state 1383c875a709SGuilherme G. Piccoli * _or_ if we lost the communication with it. 1384c875a709SGuilherme G. Piccoli */ 1385c875a709SGuilherme G. Piccoli if (!(csts & NVME_CSTS_CFS) && !nssro) 1386c875a709SGuilherme G. Piccoli return false; 1387c875a709SGuilherme G. Piccoli 1388c875a709SGuilherme G. Piccoli /* If PCI error recovery process is happening, we cannot reset or 1389c875a709SGuilherme G. Piccoli * the recovery mechanism will surely fail. 1390c875a709SGuilherme G. Piccoli */ 1391c875a709SGuilherme G. Piccoli if (pci_channel_offline(to_pci_dev(dev->dev))) 1392c875a709SGuilherme G. Piccoli return false; 1393c875a709SGuilherme G. Piccoli 1394c875a709SGuilherme G. Piccoli return true; 1395c875a709SGuilherme G. Piccoli } 1396c875a709SGuilherme G. Piccoli 1397d2a61918SAndy Lutomirski static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1398d2a61918SAndy Lutomirski { 1399d2a61918SAndy Lutomirski /* Read a config register to help see what died. */ 1400d2a61918SAndy Lutomirski u16 pci_status; 1401d2a61918SAndy Lutomirski int result; 1402d2a61918SAndy Lutomirski 1403d2a61918SAndy Lutomirski result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1404d2a61918SAndy Lutomirski &pci_status); 1405d2a61918SAndy Lutomirski if (result == PCIBIOS_SUCCESSFUL) 14069bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1407d2a61918SAndy Lutomirski "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1408d2a61918SAndy Lutomirski csts, pci_status); 1409d2a61918SAndy Lutomirski else 14109bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1411d2a61918SAndy Lutomirski "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1412d2a61918SAndy Lutomirski csts, result); 1413d2a61918SAndy Lutomirski } 1414d2a61918SAndy Lutomirski 14152d55cd5fSChristoph Hellwig static void nvme_watchdog_timer(unsigned long data) 141657dacad5SJay Sternberg { 14172d55cd5fSChristoph Hellwig struct nvme_dev *dev = (struct nvme_dev *)data; 14187a67cbeaSChristoph Hellwig u32 csts = readl(dev->bar + NVME_REG_CSTS); 141957dacad5SJay Sternberg 1420c875a709SGuilherme G. Piccoli /* Skip controllers under certain specific conditions. */ 1421c875a709SGuilherme G. Piccoli if (nvme_should_reset(dev, csts)) { 1422c5f6ce97SKeith Busch if (!nvme_reset(dev)) 1423d2a61918SAndy Lutomirski nvme_warn_reset(dev, csts); 14242d55cd5fSChristoph Hellwig return; 142557dacad5SJay Sternberg } 142657dacad5SJay Sternberg 14272d55cd5fSChristoph Hellwig mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); 142857dacad5SJay Sternberg } 142957dacad5SJay Sternberg 1430749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 143157dacad5SJay Sternberg { 1432949928c1SKeith Busch unsigned i, max; 1433749941f2SChristoph Hellwig int ret = 0; 143457dacad5SJay Sternberg 1435749941f2SChristoph Hellwig for (i = dev->queue_count; i <= dev->max_qid; i++) { 1436d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1437d3af3ecdSShaohua Li if (!nvme_alloc_queue(dev, i, dev->q_depth, 1438d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1439749941f2SChristoph Hellwig ret = -ENOMEM; 144057dacad5SJay Sternberg break; 1441749941f2SChristoph Hellwig } 1442749941f2SChristoph Hellwig } 144357dacad5SJay Sternberg 1444949928c1SKeith Busch max = min(dev->max_qid, dev->queue_count - 1); 1445949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1446749941f2SChristoph Hellwig ret = nvme_create_queue(dev->queues[i], i); 1447d4875622SKeith Busch if (ret) 144857dacad5SJay Sternberg break; 144957dacad5SJay Sternberg } 145057dacad5SJay Sternberg 1451749941f2SChristoph Hellwig /* 1452749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 1453749941f2SChristoph Hellwig * than the desired aount of queues, and even a controller without 1454749941f2SChristoph Hellwig * I/O queues an still be used to issue admin commands. This might 1455749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1456749941f2SChristoph Hellwig */ 1457749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 145857dacad5SJay Sternberg } 145957dacad5SJay Sternberg 1460202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1461202021c1SStephen Bates struct device_attribute *attr, 1462202021c1SStephen Bates char *buf) 1463202021c1SStephen Bates { 1464202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1465202021c1SStephen Bates 1466c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1467202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1468202021c1SStephen Bates } 1469202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1470202021c1SStephen Bates 147157dacad5SJay Sternberg static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 147257dacad5SJay Sternberg { 147357dacad5SJay Sternberg u64 szu, size, offset; 147457dacad5SJay Sternberg resource_size_t bar_size; 147557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 147657dacad5SJay Sternberg void __iomem *cmb; 147757dacad5SJay Sternberg dma_addr_t dma_addr; 147857dacad5SJay Sternberg 14797a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 148057dacad5SJay Sternberg if (!(NVME_CMB_SZ(dev->cmbsz))) 148157dacad5SJay Sternberg return NULL; 1482202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 148357dacad5SJay Sternberg 1484202021c1SStephen Bates if (!use_cmb_sqes) 1485202021c1SStephen Bates return NULL; 148657dacad5SJay Sternberg 148757dacad5SJay Sternberg szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 148857dacad5SJay Sternberg size = szu * NVME_CMB_SZ(dev->cmbsz); 1489202021c1SStephen Bates offset = szu * NVME_CMB_OFST(dev->cmbloc); 1490202021c1SStephen Bates bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 149157dacad5SJay Sternberg 149257dacad5SJay Sternberg if (offset > bar_size) 149357dacad5SJay Sternberg return NULL; 149457dacad5SJay Sternberg 149557dacad5SJay Sternberg /* 149657dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 149757dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 149857dacad5SJay Sternberg * the reported size of the BAR 149957dacad5SJay Sternberg */ 150057dacad5SJay Sternberg if (size > bar_size - offset) 150157dacad5SJay Sternberg size = bar_size - offset; 150257dacad5SJay Sternberg 1503202021c1SStephen Bates dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 150457dacad5SJay Sternberg cmb = ioremap_wc(dma_addr, size); 150557dacad5SJay Sternberg if (!cmb) 150657dacad5SJay Sternberg return NULL; 150757dacad5SJay Sternberg 150857dacad5SJay Sternberg dev->cmb_dma_addr = dma_addr; 150957dacad5SJay Sternberg dev->cmb_size = size; 151057dacad5SJay Sternberg return cmb; 151157dacad5SJay Sternberg } 151257dacad5SJay Sternberg 151357dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 151457dacad5SJay Sternberg { 151557dacad5SJay Sternberg if (dev->cmb) { 151657dacad5SJay Sternberg iounmap(dev->cmb); 151757dacad5SJay Sternberg dev->cmb = NULL; 1518f63572dfSJon Derrick if (dev->cmbsz) { 1519f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1520f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1521f63572dfSJon Derrick dev->cmbsz = 0; 1522f63572dfSJon Derrick } 152357dacad5SJay Sternberg } 152457dacad5SJay Sternberg } 152557dacad5SJay Sternberg 152687ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 152787ad72a5SChristoph Hellwig { 152887ad72a5SChristoph Hellwig size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); 152987ad72a5SChristoph Hellwig struct nvme_command c; 153087ad72a5SChristoph Hellwig u64 dma_addr; 153187ad72a5SChristoph Hellwig int ret; 153287ad72a5SChristoph Hellwig 153387ad72a5SChristoph Hellwig dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, 153487ad72a5SChristoph Hellwig DMA_TO_DEVICE); 153587ad72a5SChristoph Hellwig if (dma_mapping_error(dev->dev, dma_addr)) 153687ad72a5SChristoph Hellwig return -ENOMEM; 153787ad72a5SChristoph Hellwig 153887ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 153987ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 154087ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 154187ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 154287ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 154387ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 154487ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 154587ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 154687ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 154787ad72a5SChristoph Hellwig 154887ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 154987ad72a5SChristoph Hellwig if (ret) { 155087ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 155187ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 155287ad72a5SChristoph Hellwig ret, bits); 155387ad72a5SChristoph Hellwig } 155487ad72a5SChristoph Hellwig dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); 155587ad72a5SChristoph Hellwig return ret; 155687ad72a5SChristoph Hellwig } 155787ad72a5SChristoph Hellwig 155887ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 155987ad72a5SChristoph Hellwig { 156087ad72a5SChristoph Hellwig int i; 156187ad72a5SChristoph Hellwig 156287ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 156387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 156487ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 156587ad72a5SChristoph Hellwig 156687ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 156787ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 156887ad72a5SChristoph Hellwig } 156987ad72a5SChristoph Hellwig 157087ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 157187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 157287ad72a5SChristoph Hellwig kfree(dev->host_mem_descs); 157387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 157487ad72a5SChristoph Hellwig } 157587ad72a5SChristoph Hellwig 157687ad72a5SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 157787ad72a5SChristoph Hellwig { 157887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 157987ad72a5SChristoph Hellwig u32 chunk_size, max_entries, i = 0; 158087ad72a5SChristoph Hellwig void **bufs; 158187ad72a5SChristoph Hellwig u64 size, tmp; 158287ad72a5SChristoph Hellwig 158387ad72a5SChristoph Hellwig /* start big and work our way down */ 158487ad72a5SChristoph Hellwig chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); 158587ad72a5SChristoph Hellwig retry: 158687ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 158787ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 158887ad72a5SChristoph Hellwig max_entries = tmp; 158987ad72a5SChristoph Hellwig descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); 159087ad72a5SChristoph Hellwig if (!descs) 159187ad72a5SChristoph Hellwig goto out; 159287ad72a5SChristoph Hellwig 159387ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 159487ad72a5SChristoph Hellwig if (!bufs) 159587ad72a5SChristoph Hellwig goto out_free_descs; 159687ad72a5SChristoph Hellwig 159787ad72a5SChristoph Hellwig for (size = 0; size < preferred; size += chunk_size) { 159887ad72a5SChristoph Hellwig u32 len = min_t(u64, chunk_size, preferred - size); 159987ad72a5SChristoph Hellwig dma_addr_t dma_addr; 160087ad72a5SChristoph Hellwig 160187ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 160287ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 160387ad72a5SChristoph Hellwig if (!bufs[i]) 160487ad72a5SChristoph Hellwig break; 160587ad72a5SChristoph Hellwig 160687ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 160787ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 160887ad72a5SChristoph Hellwig i++; 160987ad72a5SChristoph Hellwig } 161087ad72a5SChristoph Hellwig 161187ad72a5SChristoph Hellwig if (!size || (min && size < min)) { 161287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 161387ad72a5SChristoph Hellwig "failed to allocate host memory buffer.\n"); 161487ad72a5SChristoph Hellwig goto out_free_bufs; 161587ad72a5SChristoph Hellwig } 161687ad72a5SChristoph Hellwig 161787ad72a5SChristoph Hellwig dev_info(dev->ctrl.device, 161887ad72a5SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 161987ad72a5SChristoph Hellwig size >> ilog2(SZ_1M)); 162087ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 162187ad72a5SChristoph Hellwig dev->host_mem_size = size; 162287ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 162387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 162487ad72a5SChristoph Hellwig return 0; 162587ad72a5SChristoph Hellwig 162687ad72a5SChristoph Hellwig out_free_bufs: 162787ad72a5SChristoph Hellwig while (--i >= 0) { 162887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 162987ad72a5SChristoph Hellwig 163087ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 163187ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 163287ad72a5SChristoph Hellwig } 163387ad72a5SChristoph Hellwig 163487ad72a5SChristoph Hellwig kfree(bufs); 163587ad72a5SChristoph Hellwig out_free_descs: 163687ad72a5SChristoph Hellwig kfree(descs); 163787ad72a5SChristoph Hellwig out: 163887ad72a5SChristoph Hellwig /* try a smaller chunk size if we failed early */ 163987ad72a5SChristoph Hellwig if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { 164087ad72a5SChristoph Hellwig chunk_size /= 2; 164187ad72a5SChristoph Hellwig goto retry; 164287ad72a5SChristoph Hellwig } 164387ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 164487ad72a5SChristoph Hellwig return -ENOMEM; 164587ad72a5SChristoph Hellwig } 164687ad72a5SChristoph Hellwig 164787ad72a5SChristoph Hellwig static void nvme_setup_host_mem(struct nvme_dev *dev) 164887ad72a5SChristoph Hellwig { 164987ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 165087ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 165187ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 165287ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 165387ad72a5SChristoph Hellwig 165487ad72a5SChristoph Hellwig preferred = min(preferred, max); 165587ad72a5SChristoph Hellwig if (min > max) { 165687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 165787ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 165887ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 165987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 166087ad72a5SChristoph Hellwig return; 166187ad72a5SChristoph Hellwig } 166287ad72a5SChristoph Hellwig 166387ad72a5SChristoph Hellwig /* 166487ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 166587ad72a5SChristoph Hellwig */ 166687ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 166787ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 166887ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 166987ad72a5SChristoph Hellwig else 167087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 167187ad72a5SChristoph Hellwig } 167287ad72a5SChristoph Hellwig 167387ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 167487ad72a5SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) 167587ad72a5SChristoph Hellwig return; 167687ad72a5SChristoph Hellwig } 167787ad72a5SChristoph Hellwig 167887ad72a5SChristoph Hellwig if (nvme_set_host_mem(dev, enable_bits)) 167987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 168087ad72a5SChristoph Hellwig } 168187ad72a5SChristoph Hellwig 168257dacad5SJay Sternberg static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 168357dacad5SJay Sternberg { 168457dacad5SJay Sternberg return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); 168557dacad5SJay Sternberg } 168657dacad5SJay Sternberg 168757dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 168857dacad5SJay Sternberg { 168957dacad5SJay Sternberg struct nvme_queue *adminq = dev->queues[0]; 169057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 1691dca51e78SChristoph Hellwig int result, nr_io_queues, size; 169257dacad5SJay Sternberg 16932800b8e7SKeith Busch nr_io_queues = num_online_cpus(); 16949a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 16959a0be7abSChristoph Hellwig if (result < 0) 169657dacad5SJay Sternberg return result; 16979a0be7abSChristoph Hellwig 1698f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1699a5229050SKeith Busch return 0; 170057dacad5SJay Sternberg 170157dacad5SJay Sternberg if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 170257dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 170357dacad5SJay Sternberg sizeof(struct nvme_command)); 170457dacad5SJay Sternberg if (result > 0) 170557dacad5SJay Sternberg dev->q_depth = result; 170657dacad5SJay Sternberg else 170757dacad5SJay Sternberg nvme_release_cmb(dev); 170857dacad5SJay Sternberg } 170957dacad5SJay Sternberg 171057dacad5SJay Sternberg size = db_bar_size(dev, nr_io_queues); 171157dacad5SJay Sternberg if (size > 8192) { 171257dacad5SJay Sternberg iounmap(dev->bar); 171357dacad5SJay Sternberg do { 171457dacad5SJay Sternberg dev->bar = ioremap(pci_resource_start(pdev, 0), size); 171557dacad5SJay Sternberg if (dev->bar) 171657dacad5SJay Sternberg break; 171757dacad5SJay Sternberg if (!--nr_io_queues) 171857dacad5SJay Sternberg return -ENOMEM; 171957dacad5SJay Sternberg size = db_bar_size(dev, nr_io_queues); 172057dacad5SJay Sternberg } while (1); 17217a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 172257dacad5SJay Sternberg adminq->q_db = dev->dbs; 172357dacad5SJay Sternberg } 172457dacad5SJay Sternberg 172557dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 17260ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 172757dacad5SJay Sternberg 172857dacad5SJay Sternberg /* 172957dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 173057dacad5SJay Sternberg * setting up the full range we need. 173157dacad5SJay Sternberg */ 1732dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1733dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1734dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1735dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1736dca51e78SChristoph Hellwig return -EIO; 1737dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 173857dacad5SJay Sternberg 173957dacad5SJay Sternberg /* 174057dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 174157dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 174257dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 174357dacad5SJay Sternberg * number of interrupts. 174457dacad5SJay Sternberg */ 174557dacad5SJay Sternberg 1746dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 174757dacad5SJay Sternberg if (result) { 174857dacad5SJay Sternberg adminq->cq_vector = -1; 1749d4875622SKeith Busch return result; 175057dacad5SJay Sternberg } 1751749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 175257dacad5SJay Sternberg } 175357dacad5SJay Sternberg 17542a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1755db3cbfffSKeith Busch { 1756db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1757db3cbfffSKeith Busch 1758db3cbfffSKeith Busch blk_mq_free_request(req); 1759db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1760db3cbfffSKeith Busch } 1761db3cbfffSKeith Busch 17622a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1763db3cbfffSKeith Busch { 1764db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1765db3cbfffSKeith Busch 1766db3cbfffSKeith Busch if (!error) { 1767db3cbfffSKeith Busch unsigned long flags; 1768db3cbfffSKeith Busch 17692e39e0f6SMing Lin /* 17702e39e0f6SMing Lin * We might be called with the AQ q_lock held 17712e39e0f6SMing Lin * and the I/O queue q_lock should always 17722e39e0f6SMing Lin * nest inside the AQ one. 17732e39e0f6SMing Lin */ 17742e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 17752e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1776db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1777db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1778db3cbfffSKeith Busch } 1779db3cbfffSKeith Busch 1780db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1781db3cbfffSKeith Busch } 1782db3cbfffSKeith Busch 1783db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1784db3cbfffSKeith Busch { 1785db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1786db3cbfffSKeith Busch struct request *req; 1787db3cbfffSKeith Busch struct nvme_command cmd; 1788db3cbfffSKeith Busch 1789db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1790db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1791db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1792db3cbfffSKeith Busch 1793eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1794db3cbfffSKeith Busch if (IS_ERR(req)) 1795db3cbfffSKeith Busch return PTR_ERR(req); 1796db3cbfffSKeith Busch 1797db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1798db3cbfffSKeith Busch req->end_io_data = nvmeq; 1799db3cbfffSKeith Busch 1800db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1801db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1802db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1803db3cbfffSKeith Busch return 0; 1804db3cbfffSKeith Busch } 1805db3cbfffSKeith Busch 180670659060SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1807db3cbfffSKeith Busch { 180870659060SKeith Busch int pass; 1809db3cbfffSKeith Busch unsigned long timeout; 1810db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 1811db3cbfffSKeith Busch 1812db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 1813014a0d60SKeith Busch int sent = 0, i = queues; 1814db3cbfffSKeith Busch 1815db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 1816db3cbfffSKeith Busch retry: 1817db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 1818c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 1819c21377f8SGabriel Krisman Bertazi if (nvme_delete_queue(dev->queues[i], opcode)) 1820db3cbfffSKeith Busch break; 1821c21377f8SGabriel Krisman Bertazi 1822db3cbfffSKeith Busch while (sent--) { 1823db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 1824db3cbfffSKeith Busch if (timeout == 0) 1825db3cbfffSKeith Busch return; 1826db3cbfffSKeith Busch if (i) 1827db3cbfffSKeith Busch goto retry; 1828db3cbfffSKeith Busch } 1829db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 1830db3cbfffSKeith Busch } 1831db3cbfffSKeith Busch } 1832db3cbfffSKeith Busch 183357dacad5SJay Sternberg /* 183457dacad5SJay Sternberg * Return: error value if an error occurred setting up the queues or calling 183557dacad5SJay Sternberg * Identify Device. 0 if these succeeded, even if adding some of the 183657dacad5SJay Sternberg * namespaces failed. At the moment, these failures are silent. TBD which 183757dacad5SJay Sternberg * failures should be reported. 183857dacad5SJay Sternberg */ 183957dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 184057dacad5SJay Sternberg { 18415bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 184257dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 184357dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 184457dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 184557dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 184657dacad5SJay Sternberg dev->tagset.queue_depth = 184757dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 184857dacad5SJay Sternberg dev->tagset.cmd_size = nvme_cmd_size(dev); 184957dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 185057dacad5SJay Sternberg dev->tagset.driver_data = dev; 185157dacad5SJay Sternberg 185257dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->tagset)) 185357dacad5SJay Sternberg return 0; 18545bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 1855f9f38e33SHelen Koike 1856f9f38e33SHelen Koike nvme_dbbuf_set(dev); 1857949928c1SKeith Busch } else { 1858949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 1859949928c1SKeith Busch 1860949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 1861949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 186257dacad5SJay Sternberg } 1863949928c1SKeith Busch 186457dacad5SJay Sternberg return 0; 186557dacad5SJay Sternberg } 186657dacad5SJay Sternberg 1867b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 186857dacad5SJay Sternberg { 186957dacad5SJay Sternberg u64 cap; 1870b00a726aSKeith Busch int result = -ENOMEM; 187157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 187257dacad5SJay Sternberg 187357dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 187457dacad5SJay Sternberg return result; 187557dacad5SJay Sternberg 187657dacad5SJay Sternberg pci_set_master(pdev); 187757dacad5SJay Sternberg 187857dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 187957dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 188057dacad5SJay Sternberg goto disable; 188157dacad5SJay Sternberg 18827a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 188357dacad5SJay Sternberg result = -ENODEV; 1884b00a726aSKeith Busch goto disable; 188557dacad5SJay Sternberg } 188657dacad5SJay Sternberg 188757dacad5SJay Sternberg /* 1888a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 1889a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 1890a5229050SKeith Busch * adjust this later. 189157dacad5SJay Sternberg */ 1892dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1893dca51e78SChristoph Hellwig if (result < 0) 1894dca51e78SChristoph Hellwig return result; 189557dacad5SJay Sternberg 18967a67cbeaSChristoph Hellwig cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 18977a67cbeaSChristoph Hellwig 189857dacad5SJay Sternberg dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); 189957dacad5SJay Sternberg dev->db_stride = 1 << NVME_CAP_STRIDE(cap); 19007a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 19011f390c1fSStephan Günther 19021f390c1fSStephan Günther /* 19031f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 19041f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 19051f390c1fSStephan Günther */ 19061f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 19071f390c1fSStephan Günther dev->q_depth = 2; 19089bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 19099bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 19101f390c1fSStephan Günther dev->q_depth); 19111f390c1fSStephan Günther } 19121f390c1fSStephan Günther 1913202021c1SStephen Bates /* 1914202021c1SStephen Bates * CMBs can currently only exist on >=1.2 PCIe devices. We only 1915202021c1SStephen Bates * populate sysfs if a CMB is implemented. Note that we add the 1916202021c1SStephen Bates * CMB attribute to the nvme_ctrl kobj which removes the need to remove 1917202021c1SStephen Bates * it on exit. Since nvme_dev_attrs_group has no name we can pass 1918202021c1SStephen Bates * NULL as final argument to sysfs_add_file_to_group. 1919202021c1SStephen Bates */ 1920202021c1SStephen Bates 19218ef2074dSGabriel Krisman Bertazi if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 192257dacad5SJay Sternberg dev->cmb = nvme_map_cmb(dev); 192357dacad5SJay Sternberg 1924202021c1SStephen Bates if (dev->cmbsz) { 1925202021c1SStephen Bates if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1926202021c1SStephen Bates &dev_attr_cmb.attr, NULL)) 19279bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1928202021c1SStephen Bates "failed to add sysfs attribute for CMB\n"); 1929202021c1SStephen Bates } 1930202021c1SStephen Bates } 1931202021c1SStephen Bates 1932a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 1933a0a3408eSKeith Busch pci_save_state(pdev); 193457dacad5SJay Sternberg return 0; 193557dacad5SJay Sternberg 193657dacad5SJay Sternberg disable: 193757dacad5SJay Sternberg pci_disable_device(pdev); 193857dacad5SJay Sternberg return result; 193957dacad5SJay Sternberg } 194057dacad5SJay Sternberg 194157dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 194257dacad5SJay Sternberg { 1943b00a726aSKeith Busch if (dev->bar) 1944b00a726aSKeith Busch iounmap(dev->bar); 1945a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 1946b00a726aSKeith Busch } 1947b00a726aSKeith Busch 1948b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 1949b00a726aSKeith Busch { 195057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 195157dacad5SJay Sternberg 1952f63572dfSJon Derrick nvme_release_cmb(dev); 1953dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 195457dacad5SJay Sternberg 1955a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 1956a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 195757dacad5SJay Sternberg pci_disable_device(pdev); 195857dacad5SJay Sternberg } 1959a0a3408eSKeith Busch } 196057dacad5SJay Sternberg 1961a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 196257dacad5SJay Sternberg { 196370659060SKeith Busch int i, queues; 1964302ad8ccSKeith Busch bool dead = true; 1965302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 196657dacad5SJay Sternberg 19672d55cd5fSChristoph Hellwig del_timer_sync(&dev->watchdog_timer); 196857dacad5SJay Sternberg 196977bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 1970302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 1971302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1972302ad8ccSKeith Busch 1973302ad8ccSKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE) 1974302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 1975302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 1976302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 197757dacad5SJay Sternberg } 1978c21377f8SGabriel Krisman Bertazi 1979302ad8ccSKeith Busch /* 1980302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 1981302ad8ccSKeith Busch * doing a safe shutdown. 1982302ad8ccSKeith Busch */ 198387ad72a5SChristoph Hellwig if (!dead) { 198487ad72a5SChristoph Hellwig if (shutdown) 1985302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig /* 198887ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 198987ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 199087ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 199187ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 199287ad72a5SChristoph Hellwig */ 199387ad72a5SChristoph Hellwig if (dev->host_mem_descs) 199487ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 199587ad72a5SChristoph Hellwig 199687ad72a5SChristoph Hellwig } 1997302ad8ccSKeith Busch nvme_stop_queues(&dev->ctrl); 1998302ad8ccSKeith Busch 199970659060SKeith Busch queues = dev->online_queues - 1; 2000c21377f8SGabriel Krisman Bertazi for (i = dev->queue_count - 1; i > 0; i--) 2001c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[i]); 2002c21377f8SGabriel Krisman Bertazi 2003302ad8ccSKeith Busch if (dead) { 200482469c59SGabriel Krisman Bertazi /* A device might become IO incapable very soon during 200582469c59SGabriel Krisman Bertazi * probe, before the admin queue is configured. Thus, 200682469c59SGabriel Krisman Bertazi * queue_count can be 0 here. 200782469c59SGabriel Krisman Bertazi */ 200882469c59SGabriel Krisman Bertazi if (dev->queue_count) 2009c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[0]); 201057dacad5SJay Sternberg } else { 201170659060SKeith Busch nvme_disable_io_queues(dev, queues); 2012a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 201357dacad5SJay Sternberg } 2014b00a726aSKeith Busch nvme_pci_disable(dev); 201557dacad5SJay Sternberg 2016e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2017e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2018302ad8ccSKeith Busch 2019302ad8ccSKeith Busch /* 2020302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2021302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2022302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2023302ad8ccSKeith Busch */ 2024302ad8ccSKeith Busch if (shutdown) 2025302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 202677bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 202757dacad5SJay Sternberg } 202857dacad5SJay Sternberg 202957dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 203057dacad5SJay Sternberg { 203157dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 203257dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 203357dacad5SJay Sternberg if (!dev->prp_page_pool) 203457dacad5SJay Sternberg return -ENOMEM; 203557dacad5SJay Sternberg 203657dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 203757dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 203857dacad5SJay Sternberg 256, 256, 0); 203957dacad5SJay Sternberg if (!dev->prp_small_pool) { 204057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 204157dacad5SJay Sternberg return -ENOMEM; 204257dacad5SJay Sternberg } 204357dacad5SJay Sternberg return 0; 204457dacad5SJay Sternberg } 204557dacad5SJay Sternberg 204657dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 204757dacad5SJay Sternberg { 204857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 204957dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 205057dacad5SJay Sternberg } 205157dacad5SJay Sternberg 20521673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 205357dacad5SJay Sternberg { 20541673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 205557dacad5SJay Sternberg 2056f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 205757dacad5SJay Sternberg put_device(dev->dev); 205857dacad5SJay Sternberg if (dev->tagset.tags) 205957dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 20601c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 20611c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 206257dacad5SJay Sternberg kfree(dev->queues); 2063e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 206457dacad5SJay Sternberg kfree(dev); 206557dacad5SJay Sternberg } 206657dacad5SJay Sternberg 2067f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2068f58944e2SKeith Busch { 2069237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2070f58944e2SKeith Busch 2071f58944e2SKeith Busch kref_get(&dev->ctrl.kref); 207269d9a99cSKeith Busch nvme_dev_disable(dev, false); 2073f58944e2SKeith Busch if (!schedule_work(&dev->remove_work)) 2074f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2075f58944e2SKeith Busch } 2076f58944e2SKeith Busch 2077fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 207857dacad5SJay Sternberg { 2079fd634f41SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); 2080a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2081f58944e2SKeith Busch int result = -ENODEV; 208257dacad5SJay Sternberg 208382b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2084fd634f41SChristoph Hellwig goto out; 2085fd634f41SChristoph Hellwig 2086fd634f41SChristoph Hellwig /* 2087fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2088fd634f41SChristoph Hellwig * moving on. 2089fd634f41SChristoph Hellwig */ 2090b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2091a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2092fd634f41SChristoph Hellwig 2093b00a726aSKeith Busch result = nvme_pci_enable(dev); 209457dacad5SJay Sternberg if (result) 209557dacad5SJay Sternberg goto out; 209657dacad5SJay Sternberg 209757dacad5SJay Sternberg result = nvme_configure_admin_queue(dev); 209857dacad5SJay Sternberg if (result) 2099f58944e2SKeith Busch goto out; 210057dacad5SJay Sternberg 210157dacad5SJay Sternberg nvme_init_queue(dev->queues[0], 0); 210257dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 210357dacad5SJay Sternberg if (result) 2104f58944e2SKeith Busch goto out; 210557dacad5SJay Sternberg 2106ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2107ce4541f4SChristoph Hellwig if (result) 2108f58944e2SKeith Busch goto out; 2109ce4541f4SChristoph Hellwig 2110e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2111e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 21124f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 21134f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2114e286bcfcSScott Bauer else if (was_suspend) 21154f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2116e286bcfcSScott Bauer } else { 2117e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2118e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2119e286bcfcSScott Bauer } 2120a98e58e5SScott Bauer 2121f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2122f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2123f9f38e33SHelen Koike if (result) 2124f9f38e33SHelen Koike dev_warn(dev->dev, 2125f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2126f9f38e33SHelen Koike } 2127f9f38e33SHelen Koike 212887ad72a5SChristoph Hellwig if (dev->ctrl.hmpre) 212987ad72a5SChristoph Hellwig nvme_setup_host_mem(dev); 213087ad72a5SChristoph Hellwig 213157dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 213257dacad5SJay Sternberg if (result) 2133f58944e2SKeith Busch goto out; 213457dacad5SJay Sternberg 213521f033f7SKeith Busch /* 213621f033f7SKeith Busch * A controller that can not execute IO typically requires user 213721f033f7SKeith Busch * intervention to correct. For such degraded controllers, the driver 213821f033f7SKeith Busch * should not submit commands the user did not request, so skip 213921f033f7SKeith Busch * registering for asynchronous event notification on this condition. 214021f033f7SKeith Busch */ 2141f866fc42SChristoph Hellwig if (dev->online_queues > 1) 2142f866fc42SChristoph Hellwig nvme_queue_async_events(&dev->ctrl); 214357dacad5SJay Sternberg 21442d55cd5fSChristoph Hellwig mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); 214557dacad5SJay Sternberg 214657dacad5SJay Sternberg /* 214757dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 214857dacad5SJay Sternberg * any working I/O queue. 214957dacad5SJay Sternberg */ 215057dacad5SJay Sternberg if (dev->online_queues < 2) { 21511b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 21523b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 21535bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 215457dacad5SJay Sternberg } else { 215525646264SKeith Busch nvme_start_queues(&dev->ctrl); 2156302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 215757dacad5SJay Sternberg nvme_dev_add(dev); 2158302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 215957dacad5SJay Sternberg } 216057dacad5SJay Sternberg 2161bb8d261eSChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2162bb8d261eSChristoph Hellwig dev_warn(dev->ctrl.device, "failed to mark controller live\n"); 2163bb8d261eSChristoph Hellwig goto out; 2164bb8d261eSChristoph Hellwig } 216592911a55SChristoph Hellwig 216692911a55SChristoph Hellwig if (dev->online_queues > 1) 21675955be21SChristoph Hellwig nvme_queue_scan(&dev->ctrl); 216857dacad5SJay Sternberg return; 216957dacad5SJay Sternberg 217057dacad5SJay Sternberg out: 2171f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 217257dacad5SJay Sternberg } 217357dacad5SJay Sternberg 21745c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 217557dacad5SJay Sternberg { 21765c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 217757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 217857dacad5SJay Sternberg 217969d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 218057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2181921920abSKeith Busch device_release_driver(&pdev->dev); 21821673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 218357dacad5SJay Sternberg } 218457dacad5SJay Sternberg 218557dacad5SJay Sternberg static int nvme_reset(struct nvme_dev *dev) 218657dacad5SJay Sternberg { 21871c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 218857dacad5SJay Sternberg return -ENODEV; 218982b057caSRakesh Pandit if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) 219082b057caSRakesh Pandit return -EBUSY; 2191*9a6327d2SSagi Grimberg if (!queue_work(nvme_wq, &dev->reset_work)) 2192846cc05fSChristoph Hellwig return -EBUSY; 219357dacad5SJay Sternberg return 0; 219457dacad5SJay Sternberg } 219557dacad5SJay Sternberg 21961c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 219757dacad5SJay Sternberg { 21981c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 21991c63dc66SChristoph Hellwig return 0; 220057dacad5SJay Sternberg } 22011c63dc66SChristoph Hellwig 22025fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 22035fd4ce1bSChristoph Hellwig { 22045fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 22055fd4ce1bSChristoph Hellwig return 0; 22065fd4ce1bSChristoph Hellwig } 22075fd4ce1bSChristoph Hellwig 22087fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 22097fd8930fSChristoph Hellwig { 22107fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 22117fd8930fSChristoph Hellwig return 0; 22127fd8930fSChristoph Hellwig } 22137fd8930fSChristoph Hellwig 2214f3ca80fcSChristoph Hellwig static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 2215f3ca80fcSChristoph Hellwig { 2216c5f6ce97SKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 2217c5f6ce97SKeith Busch int ret = nvme_reset(dev); 2218c5f6ce97SKeith Busch 2219c5f6ce97SKeith Busch if (!ret) 2220c5f6ce97SKeith Busch flush_work(&dev->reset_work); 2221c5f6ce97SKeith Busch return ret; 2222f3ca80fcSChristoph Hellwig } 2223f3ca80fcSChristoph Hellwig 22241c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 22251a353d85SMing Lin .name = "pcie", 2226e439bb12SSagi Grimberg .module = THIS_MODULE, 2227c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 22281c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 22295fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 22307fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 2231f3ca80fcSChristoph Hellwig .reset_ctrl = nvme_pci_reset_ctrl, 22321673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2233f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 22341c63dc66SChristoph Hellwig }; 223557dacad5SJay Sternberg 2236b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2237b00a726aSKeith Busch { 2238b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2239b00a726aSKeith Busch 2240a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2241b00a726aSKeith Busch return -ENODEV; 2242b00a726aSKeith Busch 2243b00a726aSKeith Busch dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); 2244b00a726aSKeith Busch if (!dev->bar) 2245b00a726aSKeith Busch goto release; 2246b00a726aSKeith Busch 2247b00a726aSKeith Busch return 0; 2248b00a726aSKeith Busch release: 2249a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2250b00a726aSKeith Busch return -ENODEV; 2251b00a726aSKeith Busch } 2252b00a726aSKeith Busch 2253ff5350a8SAndy Lutomirski static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) 2254ff5350a8SAndy Lutomirski { 2255ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2256ff5350a8SAndy Lutomirski /* 2257ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2258ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2259ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2260ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2261ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2262ff5350a8SAndy Lutomirski * laptops. 2263ff5350a8SAndy Lutomirski */ 2264ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2265ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2266ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2267ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 2268ff5350a8SAndy Lutomirski } 2269ff5350a8SAndy Lutomirski 2270ff5350a8SAndy Lutomirski return 0; 2271ff5350a8SAndy Lutomirski } 2272ff5350a8SAndy Lutomirski 227357dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 227457dacad5SJay Sternberg { 227557dacad5SJay Sternberg int node, result = -ENOMEM; 227657dacad5SJay Sternberg struct nvme_dev *dev; 2277ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 227857dacad5SJay Sternberg 227957dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 228057dacad5SJay Sternberg if (node == NUMA_NO_NODE) 22812fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 228257dacad5SJay Sternberg 228357dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 228457dacad5SJay Sternberg if (!dev) 228557dacad5SJay Sternberg return -ENOMEM; 228657dacad5SJay Sternberg dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 228757dacad5SJay Sternberg GFP_KERNEL, node); 228857dacad5SJay Sternberg if (!dev->queues) 228957dacad5SJay Sternberg goto free; 229057dacad5SJay Sternberg 229157dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 229257dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 229357dacad5SJay Sternberg 2294b00a726aSKeith Busch result = nvme_dev_map(dev); 2295b00a726aSKeith Busch if (result) 2296b00a726aSKeith Busch goto free; 2297b00a726aSKeith Busch 2298f3ca80fcSChristoph Hellwig INIT_WORK(&dev->reset_work, nvme_reset_work); 22995c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 23002d55cd5fSChristoph Hellwig setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, 23012d55cd5fSChristoph Hellwig (unsigned long)dev); 230277bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2303db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2304f3ca80fcSChristoph Hellwig 2305f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2306f3ca80fcSChristoph Hellwig if (result) 2307f3ca80fcSChristoph Hellwig goto put_pci; 2308f3ca80fcSChristoph Hellwig 2309ff5350a8SAndy Lutomirski quirks |= check_dell_samsung_bug(pdev); 2310ff5350a8SAndy Lutomirski 2311f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2312ff5350a8SAndy Lutomirski quirks); 2313f3ca80fcSChristoph Hellwig if (result) 2314f3ca80fcSChristoph Hellwig goto release_pools; 2315f3ca80fcSChristoph Hellwig 231682b057caSRakesh Pandit nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); 23171b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 23181b3c47c1SSagi Grimberg 2319*9a6327d2SSagi Grimberg queue_work(nvme_wq, &dev->reset_work); 232057dacad5SJay Sternberg return 0; 232157dacad5SJay Sternberg 232257dacad5SJay Sternberg release_pools: 232357dacad5SJay Sternberg nvme_release_prp_pools(dev); 232457dacad5SJay Sternberg put_pci: 232557dacad5SJay Sternberg put_device(dev->dev); 2326b00a726aSKeith Busch nvme_dev_unmap(dev); 232757dacad5SJay Sternberg free: 232857dacad5SJay Sternberg kfree(dev->queues); 232957dacad5SJay Sternberg kfree(dev); 233057dacad5SJay Sternberg return result; 233157dacad5SJay Sternberg } 233257dacad5SJay Sternberg 233357dacad5SJay Sternberg static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) 233457dacad5SJay Sternberg { 233557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 233657dacad5SJay Sternberg 233757dacad5SJay Sternberg if (prepare) 2338a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 233957dacad5SJay Sternberg else 2340c5f6ce97SKeith Busch nvme_reset(dev); 234157dacad5SJay Sternberg } 234257dacad5SJay Sternberg 234357dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 234457dacad5SJay Sternberg { 234557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2346a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 234757dacad5SJay Sternberg } 234857dacad5SJay Sternberg 2349f58944e2SKeith Busch /* 2350f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2351f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2352f58944e2SKeith Busch * order to proceed. 2353f58944e2SKeith Busch */ 235457dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 235557dacad5SJay Sternberg { 235657dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 235757dacad5SJay Sternberg 2358bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2359bb8d261eSChristoph Hellwig 236082b057caSRakesh Pandit cancel_work_sync(&dev->reset_work); 236157dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 23620ff9d4e1SKeith Busch 23636db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 23640ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 23656db28edaSKeith Busch nvme_dev_disable(dev, false); 23666db28edaSKeith Busch } 23670ff9d4e1SKeith Busch 23689bf2b972SKeith Busch flush_work(&dev->reset_work); 236953029b04SKeith Busch nvme_uninit_ctrl(&dev->ctrl); 2370a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 237187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 237257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 237357dacad5SJay Sternberg nvme_free_queues(dev, 0); 237457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2375b00a726aSKeith Busch nvme_dev_unmap(dev); 23761673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 237757dacad5SJay Sternberg } 237857dacad5SJay Sternberg 237913880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 238013880f5bSKeith Busch { 238113880f5bSKeith Busch int ret = 0; 238213880f5bSKeith Busch 238313880f5bSKeith Busch if (numvfs == 0) { 238413880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 238513880f5bSKeith Busch dev_warn(&pdev->dev, 238613880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 238713880f5bSKeith Busch return -EPERM; 238813880f5bSKeith Busch } 238913880f5bSKeith Busch pci_disable_sriov(pdev); 239013880f5bSKeith Busch return 0; 239113880f5bSKeith Busch } 239213880f5bSKeith Busch 239313880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 239413880f5bSKeith Busch return ret ? ret : numvfs; 239513880f5bSKeith Busch } 239613880f5bSKeith Busch 239757dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 239857dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 239957dacad5SJay Sternberg { 240057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 240157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 240257dacad5SJay Sternberg 2403a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 240457dacad5SJay Sternberg return 0; 240557dacad5SJay Sternberg } 240657dacad5SJay Sternberg 240757dacad5SJay Sternberg static int nvme_resume(struct device *dev) 240857dacad5SJay Sternberg { 240957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 241057dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 241157dacad5SJay Sternberg 2412c5f6ce97SKeith Busch nvme_reset(ndev); 241357dacad5SJay Sternberg return 0; 241457dacad5SJay Sternberg } 241557dacad5SJay Sternberg #endif 241657dacad5SJay Sternberg 241757dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 241857dacad5SJay Sternberg 2419a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2420a0a3408eSKeith Busch pci_channel_state_t state) 2421a0a3408eSKeith Busch { 2422a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2423a0a3408eSKeith Busch 2424a0a3408eSKeith Busch /* 2425a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2426a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2427a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2428a0a3408eSKeith Busch */ 2429a0a3408eSKeith Busch switch (state) { 2430a0a3408eSKeith Busch case pci_channel_io_normal: 2431a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2432a0a3408eSKeith Busch case pci_channel_io_frozen: 2433d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2434d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2435a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2436a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2437a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2438d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2439d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2440a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2441a0a3408eSKeith Busch } 2442a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2443a0a3408eSKeith Busch } 2444a0a3408eSKeith Busch 2445a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2446a0a3408eSKeith Busch { 2447a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2448a0a3408eSKeith Busch 24491b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2450a0a3408eSKeith Busch pci_restore_state(pdev); 2451c5f6ce97SKeith Busch nvme_reset(dev); 2452a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2453a0a3408eSKeith Busch } 2454a0a3408eSKeith Busch 2455a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2456a0a3408eSKeith Busch { 2457a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2458a0a3408eSKeith Busch } 2459a0a3408eSKeith Busch 246057dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 246157dacad5SJay Sternberg .error_detected = nvme_error_detected, 246257dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 246357dacad5SJay Sternberg .resume = nvme_error_resume, 246457dacad5SJay Sternberg .reset_notify = nvme_reset_notify, 246557dacad5SJay Sternberg }; 246657dacad5SJay Sternberg 246757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2468106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 246908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2470e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247199466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 247299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2473e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247499466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 247599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2476e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247750af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 247850af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2479540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2480540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 248154adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 248254adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2483015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2484015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 248557dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2486c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2487124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 248857dacad5SJay Sternberg { 0, } 248957dacad5SJay Sternberg }; 249057dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 249157dacad5SJay Sternberg 249257dacad5SJay Sternberg static struct pci_driver nvme_driver = { 249357dacad5SJay Sternberg .name = "nvme", 249457dacad5SJay Sternberg .id_table = nvme_id_table, 249557dacad5SJay Sternberg .probe = nvme_probe, 249657dacad5SJay Sternberg .remove = nvme_remove, 249757dacad5SJay Sternberg .shutdown = nvme_shutdown, 249857dacad5SJay Sternberg .driver = { 249957dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 250057dacad5SJay Sternberg }, 250113880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 250257dacad5SJay Sternberg .err_handler = &nvme_err_handler, 250357dacad5SJay Sternberg }; 250457dacad5SJay Sternberg 250557dacad5SJay Sternberg static int __init nvme_init(void) 250657dacad5SJay Sternberg { 2507*9a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 250857dacad5SJay Sternberg } 250957dacad5SJay Sternberg 251057dacad5SJay Sternberg static void __exit nvme_exit(void) 251157dacad5SJay Sternberg { 251257dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 251357dacad5SJay Sternberg _nvme_check_size(); 251457dacad5SJay Sternberg } 251557dacad5SJay Sternberg 251657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 251757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 251857dacad5SJay Sternberg MODULE_VERSION("1.0"); 251957dacad5SJay Sternberg module_init(nvme_init); 252057dacad5SJay Sternberg module_exit(nvme_exit); 2521