157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/blkdev.h> 1757dacad5SJay Sternberg #include <linux/blk-mq.h> 18dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 19ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2057dacad5SJay Sternberg #include <linux/init.h> 2157dacad5SJay Sternberg #include <linux/interrupt.h> 2257dacad5SJay Sternberg #include <linux/io.h> 2357dacad5SJay Sternberg #include <linux/mm.h> 2457dacad5SJay Sternberg #include <linux/module.h> 2577bf25eaSKeith Busch #include <linux/mutex.h> 26d0877473SKeith Busch #include <linux/once.h> 2757dacad5SJay Sternberg #include <linux/pci.h> 2857dacad5SJay Sternberg #include <linux/t10-pi.h> 2957dacad5SJay Sternberg #include <linux/types.h> 309cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 31a98e58e5SScott Bauer #include <linux/sed-opal.h> 3257dacad5SJay Sternberg 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3657dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 4057dacad5SJay Sternberg static int use_threaded_interrupts; 4157dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4257dacad5SJay Sternberg 4357dacad5SJay Sternberg static bool use_cmb_sqes = true; 4457dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 4557dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4657dacad5SJay Sternberg 4787ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 4887ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 4987ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5087ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5157dacad5SJay Sternberg 52a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 53a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 54a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 55a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 56a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 57a7a7cbe3SChaitanya Kulkarni 58b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 59b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 60b27c1e68Sweiping zhang .set = io_queue_depth_set, 61b27c1e68Sweiping zhang .get = param_get_int, 62b27c1e68Sweiping zhang }; 63b27c1e68Sweiping zhang 64b27c1e68Sweiping zhang static int io_queue_depth = 1024; 65b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 66b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 67b27c1e68Sweiping zhang 681c63dc66SChristoph Hellwig struct nvme_dev; 691c63dc66SChristoph Hellwig struct nvme_queue; 7057dacad5SJay Sternberg 71a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 72a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 7357dacad5SJay Sternberg 7457dacad5SJay Sternberg /* 751c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 761c63dc66SChristoph Hellwig */ 771c63dc66SChristoph Hellwig struct nvme_dev { 78147b27e4SSagi Grimberg struct nvme_queue *queues; 791c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 801c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 811c63dc66SChristoph Hellwig u32 __iomem *dbs; 821c63dc66SChristoph Hellwig struct device *dev; 831c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 841c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 851c63dc66SChristoph Hellwig unsigned online_queues; 861c63dc66SChristoph Hellwig unsigned max_qid; 871c63dc66SChristoph Hellwig int q_depth; 881c63dc66SChristoph Hellwig u32 db_stride; 891c63dc66SChristoph Hellwig void __iomem *bar; 9097f6ef64SXu Yu unsigned long bar_mapped_size; 915c8809e6SChristoph Hellwig struct work_struct remove_work; 9277bf25eaSKeith Busch struct mutex shutdown_lock; 931c63dc66SChristoph Hellwig bool subsystem; 941c63dc66SChristoph Hellwig void __iomem *cmb; 958969f1f8SChristoph Hellwig pci_bus_addr_t cmb_bus_addr; 961c63dc66SChristoph Hellwig u64 cmb_size; 971c63dc66SChristoph Hellwig u32 cmbsz; 98202021c1SStephen Bates u32 cmbloc; 991c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 100db3cbfffSKeith Busch struct completion ioq_wait; 10187ad72a5SChristoph Hellwig 10287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 103f9f38e33SHelen Koike u32 *dbbuf_dbs; 104f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 105f9f38e33SHelen Koike u32 *dbbuf_eis; 106f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 10787ad72a5SChristoph Hellwig 10887ad72a5SChristoph Hellwig /* host memory buffer support: */ 10987ad72a5SChristoph Hellwig u64 host_mem_size; 11087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1114033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 11287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 11387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 11457dacad5SJay Sternberg }; 11557dacad5SJay Sternberg 116b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 117b27c1e68Sweiping zhang { 118b27c1e68Sweiping zhang int n = 0, ret; 119b27c1e68Sweiping zhang 120b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 121b27c1e68Sweiping zhang if (ret != 0 || n < 2) 122b27c1e68Sweiping zhang return -EINVAL; 123b27c1e68Sweiping zhang 124b27c1e68Sweiping zhang return param_set_int(val, kp); 125b27c1e68Sweiping zhang } 126b27c1e68Sweiping zhang 127f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 128f9f38e33SHelen Koike { 129f9f38e33SHelen Koike return qid * 2 * stride; 130f9f38e33SHelen Koike } 131f9f38e33SHelen Koike 132f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 133f9f38e33SHelen Koike { 134f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 135f9f38e33SHelen Koike } 136f9f38e33SHelen Koike 1371c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1381c63dc66SChristoph Hellwig { 1391c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1401c63dc66SChristoph Hellwig } 1411c63dc66SChristoph Hellwig 14257dacad5SJay Sternberg /* 14357dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14457dacad5SJay Sternberg * commands and one for I/O commands). 14557dacad5SJay Sternberg */ 14657dacad5SJay Sternberg struct nvme_queue { 14757dacad5SJay Sternberg struct device *q_dmadev; 14857dacad5SJay Sternberg struct nvme_dev *dev; 14957dacad5SJay Sternberg spinlock_t q_lock; 15057dacad5SJay Sternberg struct nvme_command *sq_cmds; 15157dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15257dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15357dacad5SJay Sternberg struct blk_mq_tags **tags; 15457dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15557dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15657dacad5SJay Sternberg u32 __iomem *q_db; 15757dacad5SJay Sternberg u16 q_depth; 15857dacad5SJay Sternberg s16 cq_vector; 15957dacad5SJay Sternberg u16 sq_tail; 16057dacad5SJay Sternberg u16 cq_head; 16157dacad5SJay Sternberg u16 qid; 16257dacad5SJay Sternberg u8 cq_phase; 16357dacad5SJay Sternberg u8 cqe_seen; 164f9f38e33SHelen Koike u32 *dbbuf_sq_db; 165f9f38e33SHelen Koike u32 *dbbuf_cq_db; 166f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 167f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16857dacad5SJay Sternberg }; 16957dacad5SJay Sternberg 17057dacad5SJay Sternberg /* 17171bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17271bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 173f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17471bd150cSChristoph Hellwig * allocated to store the PRP list. 17571bd150cSChristoph Hellwig */ 17671bd150cSChristoph Hellwig struct nvme_iod { 177d49187e9SChristoph Hellwig struct nvme_request req; 178f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 179a7a7cbe3SChaitanya Kulkarni bool use_sgl; 180f4800d6dSChristoph Hellwig int aborted; 18171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18371bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18471bd150cSChristoph Hellwig dma_addr_t first_dma; 185bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 186f4800d6dSChristoph Hellwig struct scatterlist *sg; 187f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18857dacad5SJay Sternberg }; 18957dacad5SJay Sternberg 19057dacad5SJay Sternberg /* 19157dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19257dacad5SJay Sternberg */ 19357dacad5SJay Sternberg static inline void _nvme_check_size(void) 19457dacad5SJay Sternberg { 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2030add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2040add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 20557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 207f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 208f9f38e33SHelen Koike } 209f9f38e33SHelen Koike 210f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 211f9f38e33SHelen Koike { 212f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 213f9f38e33SHelen Koike } 214f9f38e33SHelen Koike 215f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 216f9f38e33SHelen Koike { 217f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 218f9f38e33SHelen Koike 219f9f38e33SHelen Koike if (dev->dbbuf_dbs) 220f9f38e33SHelen Koike return 0; 221f9f38e33SHelen Koike 222f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 223f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 224f9f38e33SHelen Koike GFP_KERNEL); 225f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 226f9f38e33SHelen Koike return -ENOMEM; 227f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 228f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 229f9f38e33SHelen Koike GFP_KERNEL); 230f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 231f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 232f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 233f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 234f9f38e33SHelen Koike return -ENOMEM; 235f9f38e33SHelen Koike } 236f9f38e33SHelen Koike 237f9f38e33SHelen Koike return 0; 238f9f38e33SHelen Koike } 239f9f38e33SHelen Koike 240f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 241f9f38e33SHelen Koike { 242f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 243f9f38e33SHelen Koike 244f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 245f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 246f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 247f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike if (dev->dbbuf_eis) { 250f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 251f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 252f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 253f9f38e33SHelen Koike } 254f9f38e33SHelen Koike } 255f9f38e33SHelen Koike 256f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 257f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 258f9f38e33SHelen Koike { 259f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 260f9f38e33SHelen Koike return; 261f9f38e33SHelen Koike 262f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 263f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 265f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 266f9f38e33SHelen Koike } 267f9f38e33SHelen Koike 268f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 269f9f38e33SHelen Koike { 270f9f38e33SHelen Koike struct nvme_command c; 271f9f38e33SHelen Koike 272f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 273f9f38e33SHelen Koike return; 274f9f38e33SHelen Koike 275f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 276f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 277f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 278f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 279f9f38e33SHelen Koike 280f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2819bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 282f9f38e33SHelen Koike /* Free memory and continue on */ 283f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike 287f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 288f9f38e33SHelen Koike { 289f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 293f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 294f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 295f9f38e33SHelen Koike { 296f9f38e33SHelen Koike if (dbbuf_db) { 297f9f38e33SHelen Koike u16 old_value; 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike /* 300f9f38e33SHelen Koike * Ensure that the queue is written before updating 301f9f38e33SHelen Koike * the doorbell in memory 302f9f38e33SHelen Koike */ 303f9f38e33SHelen Koike wmb(); 304f9f38e33SHelen Koike 305f9f38e33SHelen Koike old_value = *dbbuf_db; 306f9f38e33SHelen Koike *dbbuf_db = value; 307f9f38e33SHelen Koike 308f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 309f9f38e33SHelen Koike return false; 310f9f38e33SHelen Koike } 311f9f38e33SHelen Koike 312f9f38e33SHelen Koike return true; 31357dacad5SJay Sternberg } 31457dacad5SJay Sternberg 31557dacad5SJay Sternberg /* 31657dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31757dacad5SJay Sternberg */ 31857dacad5SJay Sternberg #define NVME_INT_PAGES 2 3195fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 32057dacad5SJay Sternberg 32157dacad5SJay Sternberg /* 32257dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32357dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32457dacad5SJay Sternberg * the I/O. 32557dacad5SJay Sternberg */ 32657dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32757dacad5SJay Sternberg { 3285fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3295fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 33057dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 33157dacad5SJay Sternberg } 33257dacad5SJay Sternberg 333a7a7cbe3SChaitanya Kulkarni /* 334a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 335a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 336a7a7cbe3SChaitanya Kulkarni */ 337a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 338f4800d6dSChristoph Hellwig { 339a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 340f4800d6dSChristoph Hellwig } 341f4800d6dSChristoph Hellwig 342a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 343a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 34457dacad5SJay Sternberg { 345a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 346a7a7cbe3SChaitanya Kulkarni 347a7a7cbe3SChaitanya Kulkarni if (use_sgl) 348a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 349a7a7cbe3SChaitanya Kulkarni else 350a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 351a7a7cbe3SChaitanya Kulkarni 352a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 353a7a7cbe3SChaitanya Kulkarni } 354a7a7cbe3SChaitanya Kulkarni 355a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 356a7a7cbe3SChaitanya Kulkarni { 357a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 358a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 359a7a7cbe3SChaitanya Kulkarni use_sgl); 360a7a7cbe3SChaitanya Kulkarni 361a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 36257dacad5SJay Sternberg } 36357dacad5SJay Sternberg 36457dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 36557dacad5SJay Sternberg unsigned int hctx_idx) 36657dacad5SJay Sternberg { 36757dacad5SJay Sternberg struct nvme_dev *dev = data; 368147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 36957dacad5SJay Sternberg 37057dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 37157dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 37257dacad5SJay Sternberg WARN_ON(nvmeq->tags); 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg hctx->driver_data = nvmeq; 37557dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 37657dacad5SJay Sternberg return 0; 37757dacad5SJay Sternberg } 37857dacad5SJay Sternberg 37957dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 38057dacad5SJay Sternberg { 38157dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 38257dacad5SJay Sternberg 38357dacad5SJay Sternberg nvmeq->tags = NULL; 38457dacad5SJay Sternberg } 38557dacad5SJay Sternberg 38657dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38757dacad5SJay Sternberg unsigned int hctx_idx) 38857dacad5SJay Sternberg { 38957dacad5SJay Sternberg struct nvme_dev *dev = data; 390147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 39157dacad5SJay Sternberg 39257dacad5SJay Sternberg if (!nvmeq->tags) 39357dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 39457dacad5SJay Sternberg 39557dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 39657dacad5SJay Sternberg hctx->driver_data = nvmeq; 39757dacad5SJay Sternberg return 0; 39857dacad5SJay Sternberg } 39957dacad5SJay Sternberg 400d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 401d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 40257dacad5SJay Sternberg { 403d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 404f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4050350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 406147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 40757dacad5SJay Sternberg 40857dacad5SJay Sternberg BUG_ON(!nvmeq); 409f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 41057dacad5SJay Sternberg return 0; 41157dacad5SJay Sternberg } 41257dacad5SJay Sternberg 413dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 414dca51e78SChristoph Hellwig { 415dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 416dca51e78SChristoph Hellwig 417dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 418dca51e78SChristoph Hellwig } 419dca51e78SChristoph Hellwig 42057dacad5SJay Sternberg /** 421adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 42257dacad5SJay Sternberg * @nvmeq: The queue to use 42357dacad5SJay Sternberg * @cmd: The command to send 42457dacad5SJay Sternberg * 42557dacad5SJay Sternberg * Safe to use from interrupt context 42657dacad5SJay Sternberg */ 42757dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 42857dacad5SJay Sternberg struct nvme_command *cmd) 42957dacad5SJay Sternberg { 43057dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 43157dacad5SJay Sternberg 43257dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 43357dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 43457dacad5SJay Sternberg else 43557dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 43857dacad5SJay Sternberg tail = 0; 439f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 440f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 44157dacad5SJay Sternberg writel(tail, nvmeq->q_db); 44257dacad5SJay Sternberg nvmeq->sq_tail = tail; 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 445a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 44657dacad5SJay Sternberg { 447f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 448a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 44957dacad5SJay Sternberg } 45057dacad5SJay Sternberg 451fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 45257dacad5SJay Sternberg { 453f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 454f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 455b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 456f4800d6dSChristoph Hellwig 457f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 458a7a7cbe3SChaitanya Kulkarni size_t alloc_size = nvme_pci_iod_alloc_size(dev, size, nseg, 459a7a7cbe3SChaitanya Kulkarni iod->use_sgl); 460a7a7cbe3SChaitanya Kulkarni 461a7a7cbe3SChaitanya Kulkarni iod->sg = kmalloc(alloc_size, GFP_ATOMIC); 462f4800d6dSChristoph Hellwig if (!iod->sg) 463fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 464f4800d6dSChristoph Hellwig } else { 465f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 46657dacad5SJay Sternberg } 46757dacad5SJay Sternberg 468f4800d6dSChristoph Hellwig iod->aborted = 0; 46957dacad5SJay Sternberg iod->npages = -1; 47057dacad5SJay Sternberg iod->nents = 0; 471f4800d6dSChristoph Hellwig iod->length = size; 472f80ec966SKeith Busch 473fc17b653SChristoph Hellwig return BLK_STS_OK; 47457dacad5SJay Sternberg } 47557dacad5SJay Sternberg 476f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 47757dacad5SJay Sternberg { 478f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 479a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 480a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 481a7a7cbe3SChaitanya Kulkarni 48257dacad5SJay Sternberg int i; 48357dacad5SJay Sternberg 48457dacad5SJay Sternberg if (iod->npages == 0) 485a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 486a7a7cbe3SChaitanya Kulkarni dma_addr); 487a7a7cbe3SChaitanya Kulkarni 48857dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 489a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 490a7a7cbe3SChaitanya Kulkarni 491a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 492a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 493a7a7cbe3SChaitanya Kulkarni 494a7a7cbe3SChaitanya Kulkarni next_dma_addr = 495a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 496a7a7cbe3SChaitanya Kulkarni } else { 497a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 498a7a7cbe3SChaitanya Kulkarni 499a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 500a7a7cbe3SChaitanya Kulkarni } 501a7a7cbe3SChaitanya Kulkarni 502a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 503a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 50457dacad5SJay Sternberg } 50557dacad5SJay Sternberg 506f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 507f4800d6dSChristoph Hellwig kfree(iod->sg); 50857dacad5SJay Sternberg } 50957dacad5SJay Sternberg 51057dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 51157dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 51257dacad5SJay Sternberg { 51357dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 51457dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 51557dacad5SJay Sternberg } 51657dacad5SJay Sternberg 51757dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 51857dacad5SJay Sternberg { 51957dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 52057dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 52157dacad5SJay Sternberg } 52257dacad5SJay Sternberg 52357dacad5SJay Sternberg /** 52457dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 52557dacad5SJay Sternberg * 52657dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 52757dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 52857dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 52957dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 53057dacad5SJay Sternberg * 53157dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 53257dacad5SJay Sternberg */ 53357dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 53457dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 53557dacad5SJay Sternberg { 53657dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 53757dacad5SJay Sternberg struct bio_integrity_payload *bip; 53857dacad5SJay Sternberg struct t10_pi_tuple *pi; 53957dacad5SJay Sternberg void *p, *pmap; 54057dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 54157dacad5SJay Sternberg 54257dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 54357dacad5SJay Sternberg return; 54457dacad5SJay Sternberg 54557dacad5SJay Sternberg bip = bio_integrity(req->bio); 54657dacad5SJay Sternberg if (!bip) 54757dacad5SJay Sternberg return; 54857dacad5SJay Sternberg 54957dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 55057dacad5SJay Sternberg 55157dacad5SJay Sternberg p = pmap; 55257dacad5SJay Sternberg virt = bip_get_seed(bip); 55357dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 55457dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 555ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 55657dacad5SJay Sternberg 55757dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 55857dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 55957dacad5SJay Sternberg dif_swap(phys, virt, pi); 56057dacad5SJay Sternberg p += ts; 56157dacad5SJay Sternberg } 56257dacad5SJay Sternberg kunmap_atomic(pmap); 56357dacad5SJay Sternberg } 56457dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 56557dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 56657dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 56757dacad5SJay Sternberg { 56857dacad5SJay Sternberg } 56957dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 57057dacad5SJay Sternberg { 57157dacad5SJay Sternberg } 57257dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 57357dacad5SJay Sternberg { 57457dacad5SJay Sternberg } 57557dacad5SJay Sternberg #endif 57657dacad5SJay Sternberg 577d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 578d0877473SKeith Busch { 579d0877473SKeith Busch int i; 580d0877473SKeith Busch struct scatterlist *sg; 581d0877473SKeith Busch 582d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 583d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 584d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 585d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 586d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 587d0877473SKeith Busch sg_dma_len(sg)); 588d0877473SKeith Busch } 589d0877473SKeith Busch } 590d0877473SKeith Busch 591a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 592a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 59357dacad5SJay Sternberg { 594f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 59557dacad5SJay Sternberg struct dma_pool *pool; 596b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 59757dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 59857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 59957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6005fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 60157dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 60257dacad5SJay Sternberg __le64 *prp_list; 603a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 60457dacad5SJay Sternberg dma_addr_t prp_dma; 60557dacad5SJay Sternberg int nprps, i; 60657dacad5SJay Sternberg 607a7a7cbe3SChaitanya Kulkarni iod->use_sgl = false; 608a7a7cbe3SChaitanya Kulkarni 60957dacad5SJay Sternberg length -= (page_size - offset); 6105228b328SJan H. Schönherr if (length <= 0) { 6115228b328SJan H. Schönherr iod->first_dma = 0; 612a7a7cbe3SChaitanya Kulkarni goto done; 6135228b328SJan H. Schönherr } 61457dacad5SJay Sternberg 61557dacad5SJay Sternberg dma_len -= (page_size - offset); 61657dacad5SJay Sternberg if (dma_len) { 61757dacad5SJay Sternberg dma_addr += (page_size - offset); 61857dacad5SJay Sternberg } else { 61957dacad5SJay Sternberg sg = sg_next(sg); 62057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 62157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62257dacad5SJay Sternberg } 62357dacad5SJay Sternberg 62457dacad5SJay Sternberg if (length <= page_size) { 62557dacad5SJay Sternberg iod->first_dma = dma_addr; 626a7a7cbe3SChaitanya Kulkarni goto done; 62757dacad5SJay Sternberg } 62857dacad5SJay Sternberg 62957dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 63057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 63157dacad5SJay Sternberg pool = dev->prp_small_pool; 63257dacad5SJay Sternberg iod->npages = 0; 63357dacad5SJay Sternberg } else { 63457dacad5SJay Sternberg pool = dev->prp_page_pool; 63557dacad5SJay Sternberg iod->npages = 1; 63657dacad5SJay Sternberg } 63757dacad5SJay Sternberg 63869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 63957dacad5SJay Sternberg if (!prp_list) { 64057dacad5SJay Sternberg iod->first_dma = dma_addr; 64157dacad5SJay Sternberg iod->npages = -1; 64286eea289SKeith Busch return BLK_STS_RESOURCE; 64357dacad5SJay Sternberg } 64457dacad5SJay Sternberg list[0] = prp_list; 64557dacad5SJay Sternberg iod->first_dma = prp_dma; 64657dacad5SJay Sternberg i = 0; 64757dacad5SJay Sternberg for (;;) { 64857dacad5SJay Sternberg if (i == page_size >> 3) { 64957dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 65157dacad5SJay Sternberg if (!prp_list) 65286eea289SKeith Busch return BLK_STS_RESOURCE; 65357dacad5SJay Sternberg list[iod->npages++] = prp_list; 65457dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 65557dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 65657dacad5SJay Sternberg i = 1; 65757dacad5SJay Sternberg } 65857dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 65957dacad5SJay Sternberg dma_len -= page_size; 66057dacad5SJay Sternberg dma_addr += page_size; 66157dacad5SJay Sternberg length -= page_size; 66257dacad5SJay Sternberg if (length <= 0) 66357dacad5SJay Sternberg break; 66457dacad5SJay Sternberg if (dma_len > 0) 66557dacad5SJay Sternberg continue; 66686eea289SKeith Busch if (unlikely(dma_len < 0)) 66786eea289SKeith Busch goto bad_sgl; 66857dacad5SJay Sternberg sg = sg_next(sg); 66957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 67157dacad5SJay Sternberg } 67257dacad5SJay Sternberg 673a7a7cbe3SChaitanya Kulkarni done: 674a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 675a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 676a7a7cbe3SChaitanya Kulkarni 67786eea289SKeith Busch return BLK_STS_OK; 67886eea289SKeith Busch 67986eea289SKeith Busch bad_sgl: 680d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 681d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 682d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 68386eea289SKeith Busch return BLK_STS_IOERR; 68457dacad5SJay Sternberg } 68557dacad5SJay Sternberg 686a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 687a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 688a7a7cbe3SChaitanya Kulkarni { 689a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 690a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 691a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 692a7a7cbe3SChaitanya Kulkarni } 693a7a7cbe3SChaitanya Kulkarni 694a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 695a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 696a7a7cbe3SChaitanya Kulkarni { 697a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 698a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 699a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 700a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 701a7a7cbe3SChaitanya Kulkarni } else { 702a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 703a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 704a7a7cbe3SChaitanya Kulkarni } 705a7a7cbe3SChaitanya Kulkarni } 706a7a7cbe3SChaitanya Kulkarni 707a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 708a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmd) 709a7a7cbe3SChaitanya Kulkarni { 710a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 711a7a7cbe3SChaitanya Kulkarni int length = blk_rq_payload_bytes(req); 712a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 713a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 714a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 715a7a7cbe3SChaitanya Kulkarni int entries = iod->nents, i = 0; 716a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 717a7a7cbe3SChaitanya Kulkarni 718a7a7cbe3SChaitanya Kulkarni iod->use_sgl = true; 719a7a7cbe3SChaitanya Kulkarni 720a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 721a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 722a7a7cbe3SChaitanya Kulkarni 723a7a7cbe3SChaitanya Kulkarni if (length == sg_dma_len(sg)) { 724a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 725a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 726a7a7cbe3SChaitanya Kulkarni } 727a7a7cbe3SChaitanya Kulkarni 728a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 729a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 730a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 731a7a7cbe3SChaitanya Kulkarni } else { 732a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 733a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 734a7a7cbe3SChaitanya Kulkarni } 735a7a7cbe3SChaitanya Kulkarni 736a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 737a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 738a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 739a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 740a7a7cbe3SChaitanya Kulkarni } 741a7a7cbe3SChaitanya Kulkarni 742a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 743a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 744a7a7cbe3SChaitanya Kulkarni 745a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 746a7a7cbe3SChaitanya Kulkarni 747a7a7cbe3SChaitanya Kulkarni do { 748a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 749a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 750a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 751a7a7cbe3SChaitanya Kulkarni 752a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 753a7a7cbe3SChaitanya Kulkarni if (!sg_list) 754a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 755a7a7cbe3SChaitanya Kulkarni 756a7a7cbe3SChaitanya Kulkarni i = 0; 757a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 758a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 759a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 760a7a7cbe3SChaitanya Kulkarni } 761a7a7cbe3SChaitanya Kulkarni 762a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni length -= sg_dma_len(sg); 765a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 766a7a7cbe3SChaitanya Kulkarni entries--; 767a7a7cbe3SChaitanya Kulkarni } while (length > 0); 768a7a7cbe3SChaitanya Kulkarni 769a7a7cbe3SChaitanya Kulkarni WARN_ON(entries > 0); 770a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 771a7a7cbe3SChaitanya Kulkarni } 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 774a7a7cbe3SChaitanya Kulkarni { 775a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 776a7a7cbe3SChaitanya Kulkarni unsigned int avg_seg_size; 777a7a7cbe3SChaitanya Kulkarni 778a7a7cbe3SChaitanya Kulkarni avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), 779a7a7cbe3SChaitanya Kulkarni blk_rq_nr_phys_segments(req)); 780a7a7cbe3SChaitanya Kulkarni 781a7a7cbe3SChaitanya Kulkarni if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 782a7a7cbe3SChaitanya Kulkarni return false; 783a7a7cbe3SChaitanya Kulkarni if (!iod->nvmeq->qid) 784a7a7cbe3SChaitanya Kulkarni return false; 785a7a7cbe3SChaitanya Kulkarni if (!sgl_threshold || avg_seg_size < sgl_threshold) 786a7a7cbe3SChaitanya Kulkarni return false; 787a7a7cbe3SChaitanya Kulkarni return true; 788a7a7cbe3SChaitanya Kulkarni } 789a7a7cbe3SChaitanya Kulkarni 790fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 791b131c61dSChristoph Hellwig struct nvme_command *cmnd) 79257dacad5SJay Sternberg { 793f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 794ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 795ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 796ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 797fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 79857dacad5SJay Sternberg 799f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 800ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 801ba1ca37eSChristoph Hellwig if (!iod->nents) 802ba1ca37eSChristoph Hellwig goto out; 803ba1ca37eSChristoph Hellwig 804fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 8052b6b535dSMauricio Faria de Oliveira if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 8062b6b535dSMauricio Faria de Oliveira DMA_ATTR_NO_WARN)) 807ba1ca37eSChristoph Hellwig goto out; 808ba1ca37eSChristoph Hellwig 809a7a7cbe3SChaitanya Kulkarni if (nvme_pci_use_sgls(dev, req)) 810a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 811a7a7cbe3SChaitanya Kulkarni else 812a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 813a7a7cbe3SChaitanya Kulkarni 81486eea289SKeith Busch if (ret != BLK_STS_OK) 815ba1ca37eSChristoph Hellwig goto out_unmap; 816ba1ca37eSChristoph Hellwig 817fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 818ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 819ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 820ba1ca37eSChristoph Hellwig goto out_unmap; 821ba1ca37eSChristoph Hellwig 822bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 823bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 824ba1ca37eSChristoph Hellwig goto out_unmap; 825ba1ca37eSChristoph Hellwig 826b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_WRITE) 827ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 828ba1ca37eSChristoph Hellwig 829bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 830ba1ca37eSChristoph Hellwig goto out_unmap; 83157dacad5SJay Sternberg } 83257dacad5SJay Sternberg 833ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 834bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 835fc17b653SChristoph Hellwig return BLK_STS_OK; 836ba1ca37eSChristoph Hellwig 837ba1ca37eSChristoph Hellwig out_unmap: 838ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 839ba1ca37eSChristoph Hellwig out: 840ba1ca37eSChristoph Hellwig return ret; 84157dacad5SJay Sternberg } 84257dacad5SJay Sternberg 843f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 844d4f6c3abSChristoph Hellwig { 845f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 846d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 847d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 848d4f6c3abSChristoph Hellwig 849d4f6c3abSChristoph Hellwig if (iod->nents) { 850d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 851d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 852b5d8af5bSKeith Busch if (req_op(req) == REQ_OP_READ) 853d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 854bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 855d4f6c3abSChristoph Hellwig } 856d4f6c3abSChristoph Hellwig } 857d4f6c3abSChristoph Hellwig 858f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 859f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 86057dacad5SJay Sternberg } 86157dacad5SJay Sternberg 86257dacad5SJay Sternberg /* 86357dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 86457dacad5SJay Sternberg */ 865fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 86657dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 86757dacad5SJay Sternberg { 86857dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 86957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 87057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 87157dacad5SJay Sternberg struct request *req = bd->rq; 872ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 873ebe6d874SChristoph Hellwig blk_status_t ret; 87457dacad5SJay Sternberg 875f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 876fc17b653SChristoph Hellwig if (ret) 877f4800d6dSChristoph Hellwig return ret; 87857dacad5SJay Sternberg 879b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 880fc17b653SChristoph Hellwig if (ret) 881f9d03f96SChristoph Hellwig goto out_free_cmd; 88257dacad5SJay Sternberg 883fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 884b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 885fc17b653SChristoph Hellwig if (ret) 886f9d03f96SChristoph Hellwig goto out_cleanup_iod; 887fc17b653SChristoph Hellwig } 888ba1ca37eSChristoph Hellwig 889aae239e1SChristoph Hellwig blk_mq_start_request(req); 890ba1ca37eSChristoph Hellwig 891ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 892ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 893fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 894ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 895f9d03f96SChristoph Hellwig goto out_cleanup_iod; 896ae1fba20SKeith Busch } 897ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 89857dacad5SJay Sternberg nvme_process_cq(nvmeq); 89957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 900fc17b653SChristoph Hellwig return BLK_STS_OK; 901f9d03f96SChristoph Hellwig out_cleanup_iod: 902f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 903f9d03f96SChristoph Hellwig out_free_cmd: 904f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 905ba1ca37eSChristoph Hellwig return ret; 90657dacad5SJay Sternberg } 90757dacad5SJay Sternberg 90877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 909eee417b0SChristoph Hellwig { 910f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 911eee417b0SChristoph Hellwig 91277f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 91377f02a7aSChristoph Hellwig nvme_complete_rq(req); 91457dacad5SJay Sternberg } 91557dacad5SJay Sternberg 916d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 917d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 918d783e0bdSMarta Rybczynska u16 phase) 919d783e0bdSMarta Rybczynska { 920d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 921d783e0bdSMarta Rybczynska } 922d783e0bdSMarta Rybczynska 923eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 92457dacad5SJay Sternberg { 925eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 92657dacad5SJay Sternberg 927eb281c82SSagi Grimberg if (likely(nvmeq->cq_vector >= 0)) { 928eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 929eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 930eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 931eb281c82SSagi Grimberg } 93257dacad5SJay Sternberg } 933adf68f21SChristoph Hellwig 93483a12fb7SSagi Grimberg static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 93583a12fb7SSagi Grimberg struct nvme_completion *cqe) 93657dacad5SJay Sternberg { 93757dacad5SJay Sternberg struct request *req; 938adf68f21SChristoph Hellwig 93983a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9401b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 941aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 94283a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 94383a12fb7SSagi Grimberg return; 944aae239e1SChristoph Hellwig } 945aae239e1SChristoph Hellwig 946adf68f21SChristoph Hellwig /* 947adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 948adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 949adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 950adf68f21SChristoph Hellwig * for them but rather special case them here. 951adf68f21SChristoph Hellwig */ 952adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 95338dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9547bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 95583a12fb7SSagi Grimberg cqe->status, &cqe->result); 956a0fa9647SJens Axboe return; 95757dacad5SJay Sternberg } 95857dacad5SJay Sternberg 959e9d8a0fdSKeith Busch nvmeq->cqe_seen = 1; 96083a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 96183a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 96283a12fb7SSagi Grimberg } 96357dacad5SJay Sternberg 964920d13a8SSagi Grimberg static inline bool nvme_read_cqe(struct nvme_queue *nvmeq, 965920d13a8SSagi Grimberg struct nvme_completion *cqe) 96683a12fb7SSagi Grimberg { 967920d13a8SSagi Grimberg if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 968920d13a8SSagi Grimberg *cqe = nvmeq->cqes[nvmeq->cq_head]; 96983a12fb7SSagi Grimberg 970920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 971920d13a8SSagi Grimberg nvmeq->cq_head = 0; 972920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 973920d13a8SSagi Grimberg } 974920d13a8SSagi Grimberg return true; 975920d13a8SSagi Grimberg } 976920d13a8SSagi Grimberg return false; 977a0fa9647SJens Axboe } 978a0fa9647SJens Axboe 979a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 980a0fa9647SJens Axboe { 981920d13a8SSagi Grimberg struct nvme_completion cqe; 982920d13a8SSagi Grimberg int consumed = 0; 98383a12fb7SSagi Grimberg 984920d13a8SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 98583a12fb7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 986920d13a8SSagi Grimberg consumed++; 98757dacad5SJay Sternberg } 98857dacad5SJay Sternberg 989e9d8a0fdSKeith Busch if (consumed) 990eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 99157dacad5SJay Sternberg } 99257dacad5SJay Sternberg 99357dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 99457dacad5SJay Sternberg { 99557dacad5SJay Sternberg irqreturn_t result; 99657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 99757dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 99857dacad5SJay Sternberg nvme_process_cq(nvmeq); 99957dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 100057dacad5SJay Sternberg nvmeq->cqe_seen = 0; 100157dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 100257dacad5SJay Sternberg return result; 100357dacad5SJay Sternberg } 100457dacad5SJay Sternberg 100557dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 100657dacad5SJay Sternberg { 100757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1008d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 100957dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1010d783e0bdSMarta Rybczynska return IRQ_NONE; 101157dacad5SJay Sternberg } 101257dacad5SJay Sternberg 10137776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 1014a0fa9647SJens Axboe { 1015442e19b7SSagi Grimberg struct nvme_completion cqe; 1016442e19b7SSagi Grimberg int found = 0, consumed = 0; 1017a0fa9647SJens Axboe 1018442e19b7SSagi Grimberg if (!nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 1019442e19b7SSagi Grimberg return 0; 1020442e19b7SSagi Grimberg 1021442e19b7SSagi Grimberg spin_lock_irq(&nvmeq->q_lock); 1022442e19b7SSagi Grimberg while (nvme_read_cqe(nvmeq, &cqe)) { 1023442e19b7SSagi Grimberg nvme_handle_cqe(nvmeq, &cqe); 1024442e19b7SSagi Grimberg consumed++; 1025442e19b7SSagi Grimberg 1026442e19b7SSagi Grimberg if (tag == cqe.command_id) { 1027442e19b7SSagi Grimberg found = 1; 1028442e19b7SSagi Grimberg break; 1029442e19b7SSagi Grimberg } 1030a0fa9647SJens Axboe } 1031a0fa9647SJens Axboe 1032442e19b7SSagi Grimberg if (consumed) 1033442e19b7SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 1034442e19b7SSagi Grimberg spin_unlock_irq(&nvmeq->q_lock); 1035442e19b7SSagi Grimberg 1036442e19b7SSagi Grimberg return found; 1037a0fa9647SJens Axboe } 1038a0fa9647SJens Axboe 10397776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 10407776db1cSKeith Busch { 10417776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 10427776db1cSKeith Busch 10437776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 10447776db1cSKeith Busch } 10457776db1cSKeith Busch 1046ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 104757dacad5SJay Sternberg { 1048f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1049147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 105057dacad5SJay Sternberg struct nvme_command c; 105157dacad5SJay Sternberg 105257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 105357dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1054ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 105557dacad5SJay Sternberg 10569396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 10579396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 10589396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 105957dacad5SJay Sternberg } 106057dacad5SJay Sternberg 106157dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 106257dacad5SJay Sternberg { 106357dacad5SJay Sternberg struct nvme_command c; 106457dacad5SJay Sternberg 106557dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 106657dacad5SJay Sternberg c.delete_queue.opcode = opcode; 106757dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 106857dacad5SJay Sternberg 10691c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 107057dacad5SJay Sternberg } 107157dacad5SJay Sternberg 107257dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 107357dacad5SJay Sternberg struct nvme_queue *nvmeq) 107457dacad5SJay Sternberg { 107557dacad5SJay Sternberg struct nvme_command c; 107657dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 107757dacad5SJay Sternberg 107857dacad5SJay Sternberg /* 107916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 108057dacad5SJay Sternberg * is attached to the request. 108157dacad5SJay Sternberg */ 108257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 108357dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 108457dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 108557dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 108657dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 108757dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 108857dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 108957dacad5SJay Sternberg 10901c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 109157dacad5SJay Sternberg } 109257dacad5SJay Sternberg 109357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 109457dacad5SJay Sternberg struct nvme_queue *nvmeq) 109557dacad5SJay Sternberg { 109657dacad5SJay Sternberg struct nvme_command c; 109781c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 109857dacad5SJay Sternberg 109957dacad5SJay Sternberg /* 110016772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 110157dacad5SJay Sternberg * is attached to the request. 110257dacad5SJay Sternberg */ 110357dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 110457dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 110557dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 110657dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 110757dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 110857dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 110957dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 111057dacad5SJay Sternberg 11111c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 111257dacad5SJay Sternberg } 111357dacad5SJay Sternberg 111457dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 111557dacad5SJay Sternberg { 111657dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 111757dacad5SJay Sternberg } 111857dacad5SJay Sternberg 111957dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 112057dacad5SJay Sternberg { 112157dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 112257dacad5SJay Sternberg } 112357dacad5SJay Sternberg 11242a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 112557dacad5SJay Sternberg { 1126f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1127f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 112857dacad5SJay Sternberg 112927fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 113027fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1131e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1132e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 113357dacad5SJay Sternberg } 113457dacad5SJay Sternberg 1135b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1136b2a0eb1aSKeith Busch { 1137b2a0eb1aSKeith Busch 1138b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1139b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1140b2a0eb1aSKeith Busch */ 1141b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1142b2a0eb1aSKeith Busch 1143b2a0eb1aSKeith Busch /* If there is a reset ongoing, we shouldn't reset again. */ 1144b2a0eb1aSKeith Busch if (dev->ctrl.state == NVME_CTRL_RESETTING) 1145b2a0eb1aSKeith Busch return false; 1146b2a0eb1aSKeith Busch 1147b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1148b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1149b2a0eb1aSKeith Busch */ 1150b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1151b2a0eb1aSKeith Busch return false; 1152b2a0eb1aSKeith Busch 1153b2a0eb1aSKeith Busch /* If PCI error recovery process is happening, we cannot reset or 1154b2a0eb1aSKeith Busch * the recovery mechanism will surely fail. 1155b2a0eb1aSKeith Busch */ 1156b2a0eb1aSKeith Busch if (pci_channel_offline(to_pci_dev(dev->dev))) 1157b2a0eb1aSKeith Busch return false; 1158b2a0eb1aSKeith Busch 1159b2a0eb1aSKeith Busch return true; 1160b2a0eb1aSKeith Busch } 1161b2a0eb1aSKeith Busch 1162b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1163b2a0eb1aSKeith Busch { 1164b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1165b2a0eb1aSKeith Busch u16 pci_status; 1166b2a0eb1aSKeith Busch int result; 1167b2a0eb1aSKeith Busch 1168b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1169b2a0eb1aSKeith Busch &pci_status); 1170b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1171b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1172b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1173b2a0eb1aSKeith Busch csts, pci_status); 1174b2a0eb1aSKeith Busch else 1175b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1176b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1177b2a0eb1aSKeith Busch csts, result); 1178b2a0eb1aSKeith Busch } 1179b2a0eb1aSKeith Busch 118031c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 118157dacad5SJay Sternberg { 1182f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1183f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 118457dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 118557dacad5SJay Sternberg struct request *abort_req; 118657dacad5SJay Sternberg struct nvme_command cmd; 1187b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1188b2a0eb1aSKeith Busch 1189b2a0eb1aSKeith Busch /* 1190b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1191b2a0eb1aSKeith Busch */ 1192b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1193b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1194b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1195d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1196b2a0eb1aSKeith Busch return BLK_EH_HANDLED; 1197b2a0eb1aSKeith Busch } 119857dacad5SJay Sternberg 119931c7c7d2SChristoph Hellwig /* 12007776db1cSKeith Busch * Did we miss an interrupt? 12017776db1cSKeith Busch */ 12027776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 12037776db1cSKeith Busch dev_warn(dev->ctrl.device, 12047776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12057776db1cSKeith Busch req->tag, nvmeq->qid); 12067776db1cSKeith Busch return BLK_EH_HANDLED; 12077776db1cSKeith Busch } 12087776db1cSKeith Busch 12097776db1cSKeith Busch /* 1210fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1211fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1212fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1213fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 1214fd634f41SChristoph Hellwig */ 1215bb8d261eSChristoph Hellwig if (dev->ctrl.state == NVME_CTRL_RESETTING) { 12161b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 1217fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1218fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1219a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 122027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1221fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 1222fd634f41SChristoph Hellwig } 1223fd634f41SChristoph Hellwig 1224fd634f41SChristoph Hellwig /* 1225e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1226e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1227e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 122831c7c7d2SChristoph Hellwig */ 1229f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 12301b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 123157dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 123257dacad5SJay Sternberg req->tag, nvmeq->qid); 1233a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1234d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1235e1569a16SKeith Busch 1236e1569a16SKeith Busch /* 1237e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1238e1569a16SKeith Busch * forces all outstanding requests to complete. 1239e1569a16SKeith Busch */ 124027fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1241e1569a16SKeith Busch return BLK_EH_HANDLED; 124257dacad5SJay Sternberg } 124357dacad5SJay Sternberg 1244e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1245e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1246e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1247e7a2a87dSChristoph Hellwig } 12487bf7d778SKeith Busch iod->aborted = 1; 124957dacad5SJay Sternberg 125057dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 125157dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 125257dacad5SJay Sternberg cmd.abort.cid = req->tag; 125357dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 125457dacad5SJay Sternberg 12551b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 12561b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 125757dacad5SJay Sternberg req->tag, nvmeq->qid); 1258e7a2a87dSChristoph Hellwig 1259e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1260eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 12616bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 12626bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 126331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 126457dacad5SJay Sternberg } 126557dacad5SJay Sternberg 1266e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1267e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1268e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 126957dacad5SJay Sternberg 127057dacad5SJay Sternberg /* 127157dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 127257dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 127357dacad5SJay Sternberg * as the device then is in a faulty state. 127457dacad5SJay Sternberg */ 127557dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 127657dacad5SJay Sternberg } 127757dacad5SJay Sternberg 127857dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 127957dacad5SJay Sternberg { 128057dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 128157dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 128257dacad5SJay Sternberg if (nvmeq->sq_cmds) 128357dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 128457dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 128557dacad5SJay Sternberg } 128657dacad5SJay Sternberg 128757dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 128857dacad5SJay Sternberg { 128957dacad5SJay Sternberg int i; 129057dacad5SJay Sternberg 1291d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1292d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1293147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 129457dacad5SJay Sternberg } 129557dacad5SJay Sternberg } 129657dacad5SJay Sternberg 129757dacad5SJay Sternberg /** 129857dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 129957dacad5SJay Sternberg * @nvmeq - queue to suspend 130057dacad5SJay Sternberg */ 130157dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 130257dacad5SJay Sternberg { 130357dacad5SJay Sternberg int vector; 130457dacad5SJay Sternberg 130557dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 130657dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 130757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 130857dacad5SJay Sternberg return 1; 130957dacad5SJay Sternberg } 13100ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 131157dacad5SJay Sternberg nvmeq->dev->online_queues--; 131257dacad5SJay Sternberg nvmeq->cq_vector = -1; 131357dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 131457dacad5SJay Sternberg 13151c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1316c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 131757dacad5SJay Sternberg 13180ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 131957dacad5SJay Sternberg 132057dacad5SJay Sternberg return 0; 132157dacad5SJay Sternberg } 132257dacad5SJay Sternberg 1323a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 132457dacad5SJay Sternberg { 1325147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 132657dacad5SJay Sternberg 132757dacad5SJay Sternberg if (nvme_suspend_queue(nvmeq)) 132857dacad5SJay Sternberg return; 132957dacad5SJay Sternberg 1330a5cdb68cSKeith Busch if (shutdown) 1331a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1332a5cdb68cSKeith Busch else 133320d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 133457dacad5SJay Sternberg 133557dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 133657dacad5SJay Sternberg nvme_process_cq(nvmeq); 133757dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 133857dacad5SJay Sternberg } 133957dacad5SJay Sternberg 134057dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 134157dacad5SJay Sternberg int entry_size) 134257dacad5SJay Sternberg { 134357dacad5SJay Sternberg int q_depth = dev->q_depth; 13445fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 13455fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 134657dacad5SJay Sternberg 134757dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 134857dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 13495fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 135057dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 135157dacad5SJay Sternberg 135257dacad5SJay Sternberg /* 135357dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 135457dacad5SJay Sternberg * would be better to map queues in system memory with the 135557dacad5SJay Sternberg * original depth 135657dacad5SJay Sternberg */ 135757dacad5SJay Sternberg if (q_depth < 64) 135857dacad5SJay Sternberg return -ENOMEM; 135957dacad5SJay Sternberg } 136057dacad5SJay Sternberg 136157dacad5SJay Sternberg return q_depth; 136257dacad5SJay Sternberg } 136357dacad5SJay Sternberg 136457dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 136557dacad5SJay Sternberg int qid, int depth) 136657dacad5SJay Sternberg { 136757dacad5SJay Sternberg if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 13685fd4ce1bSChristoph Hellwig unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 13695fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 13708969f1f8SChristoph Hellwig nvmeq->sq_dma_addr = dev->cmb_bus_addr + offset; 137157dacad5SJay Sternberg nvmeq->sq_cmds_io = dev->cmb + offset; 137257dacad5SJay Sternberg } else { 137357dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 137457dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 137557dacad5SJay Sternberg if (!nvmeq->sq_cmds) 137657dacad5SJay Sternberg return -ENOMEM; 137757dacad5SJay Sternberg } 137857dacad5SJay Sternberg 137957dacad5SJay Sternberg return 0; 138057dacad5SJay Sternberg } 138157dacad5SJay Sternberg 1382147b27e4SSagi Grimberg static int nvme_alloc_queue(struct nvme_dev *dev, int qid, 1383d3af3ecdSShaohua Li int depth, int node) 138457dacad5SJay Sternberg { 1385147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 138657dacad5SJay Sternberg 138757dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 138857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 138957dacad5SJay Sternberg if (!nvmeq->cqes) 139057dacad5SJay Sternberg goto free_nvmeq; 139157dacad5SJay Sternberg 139257dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 139357dacad5SJay Sternberg goto free_cqdma; 139457dacad5SJay Sternberg 139557dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 139657dacad5SJay Sternberg nvmeq->dev = dev; 139757dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 139857dacad5SJay Sternberg nvmeq->cq_head = 0; 139957dacad5SJay Sternberg nvmeq->cq_phase = 1; 140057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 140157dacad5SJay Sternberg nvmeq->q_depth = depth; 140257dacad5SJay Sternberg nvmeq->qid = qid; 140357dacad5SJay Sternberg nvmeq->cq_vector = -1; 1404d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 140557dacad5SJay Sternberg 1406147b27e4SSagi Grimberg return 0; 140757dacad5SJay Sternberg 140857dacad5SJay Sternberg free_cqdma: 140957dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 141057dacad5SJay Sternberg nvmeq->cq_dma_addr); 141157dacad5SJay Sternberg free_nvmeq: 1412147b27e4SSagi Grimberg return -ENOMEM; 141357dacad5SJay Sternberg } 141457dacad5SJay Sternberg 1415dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 141657dacad5SJay Sternberg { 14170ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 14180ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 14190ff199cbSChristoph Hellwig 14200ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 14210ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 14220ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14230ff199cbSChristoph Hellwig } else { 14240ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 14250ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 14260ff199cbSChristoph Hellwig } 142757dacad5SJay Sternberg } 142857dacad5SJay Sternberg 142957dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 143057dacad5SJay Sternberg { 143157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 143257dacad5SJay Sternberg 143357dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 143457dacad5SJay Sternberg nvmeq->sq_tail = 0; 143557dacad5SJay Sternberg nvmeq->cq_head = 0; 143657dacad5SJay Sternberg nvmeq->cq_phase = 1; 143757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 143857dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1439f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 144057dacad5SJay Sternberg dev->online_queues++; 144157dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 144257dacad5SJay Sternberg } 144357dacad5SJay Sternberg 144457dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 144557dacad5SJay Sternberg { 144657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 144757dacad5SJay Sternberg int result; 144857dacad5SJay Sternberg 144957dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 145057dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 145157dacad5SJay Sternberg if (result < 0) 145257dacad5SJay Sternberg return result; 145357dacad5SJay Sternberg 145457dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 145557dacad5SJay Sternberg if (result < 0) 145657dacad5SJay Sternberg goto release_cq; 145757dacad5SJay Sternberg 1458161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 1459dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 146057dacad5SJay Sternberg if (result < 0) 146157dacad5SJay Sternberg goto release_sq; 146257dacad5SJay Sternberg 146357dacad5SJay Sternberg return result; 146457dacad5SJay Sternberg 146557dacad5SJay Sternberg release_sq: 146657dacad5SJay Sternberg adapter_delete_sq(dev, qid); 146757dacad5SJay Sternberg release_cq: 146857dacad5SJay Sternberg adapter_delete_cq(dev, qid); 146957dacad5SJay Sternberg return result; 147057dacad5SJay Sternberg } 147157dacad5SJay Sternberg 1472f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 147357dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 147477f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 147557dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 147657dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 14770350815aSChristoph Hellwig .init_request = nvme_init_request, 147857dacad5SJay Sternberg .timeout = nvme_timeout, 147957dacad5SJay Sternberg }; 148057dacad5SJay Sternberg 1481f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 148257dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 148377f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 148457dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 148557dacad5SJay Sternberg .init_request = nvme_init_request, 1486dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 148757dacad5SJay Sternberg .timeout = nvme_timeout, 1488a0fa9647SJens Axboe .poll = nvme_poll, 148957dacad5SJay Sternberg }; 149057dacad5SJay Sternberg 149157dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 149257dacad5SJay Sternberg { 14931c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 149469d9a99cSKeith Busch /* 149569d9a99cSKeith Busch * If the controller was reset during removal, it's possible 149669d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 149769d9a99cSKeith Busch * queue to flush these to completion. 149869d9a99cSKeith Busch */ 1499c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 15001c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 150157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 150257dacad5SJay Sternberg } 150357dacad5SJay Sternberg } 150457dacad5SJay Sternberg 150557dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 150657dacad5SJay Sternberg { 15071c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 150857dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 150957dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1510e3e9d50cSKeith Busch 151138dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 151257dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 151357dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1514a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1515d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 151657dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 151757dacad5SJay Sternberg 151857dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 151957dacad5SJay Sternberg return -ENOMEM; 152034b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 152157dacad5SJay Sternberg 15221c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 15231c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 152457dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 152557dacad5SJay Sternberg return -ENOMEM; 152657dacad5SJay Sternberg } 15271c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 152857dacad5SJay Sternberg nvme_dev_remove_admin(dev); 15291c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 153057dacad5SJay Sternberg return -ENODEV; 153157dacad5SJay Sternberg } 153257dacad5SJay Sternberg } else 1533c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 153457dacad5SJay Sternberg 153557dacad5SJay Sternberg return 0; 153657dacad5SJay Sternberg } 153757dacad5SJay Sternberg 153897f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 153997f6ef64SXu Yu { 154097f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 154197f6ef64SXu Yu } 154297f6ef64SXu Yu 154397f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 154497f6ef64SXu Yu { 154597f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 154697f6ef64SXu Yu 154797f6ef64SXu Yu if (size <= dev->bar_mapped_size) 154897f6ef64SXu Yu return 0; 154997f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 155097f6ef64SXu Yu return -ENOMEM; 155197f6ef64SXu Yu if (dev->bar) 155297f6ef64SXu Yu iounmap(dev->bar); 155397f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 155497f6ef64SXu Yu if (!dev->bar) { 155597f6ef64SXu Yu dev->bar_mapped_size = 0; 155697f6ef64SXu Yu return -ENOMEM; 155797f6ef64SXu Yu } 155897f6ef64SXu Yu dev->bar_mapped_size = size; 155997f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 156097f6ef64SXu Yu 156197f6ef64SXu Yu return 0; 156297f6ef64SXu Yu } 156397f6ef64SXu Yu 156401ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 156557dacad5SJay Sternberg { 156657dacad5SJay Sternberg int result; 156757dacad5SJay Sternberg u32 aqa; 156857dacad5SJay Sternberg struct nvme_queue *nvmeq; 156957dacad5SJay Sternberg 157097f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 157197f6ef64SXu Yu if (result < 0) 157297f6ef64SXu Yu return result; 157397f6ef64SXu Yu 15748ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 157520d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 157657dacad5SJay Sternberg 15777a67cbeaSChristoph Hellwig if (dev->subsystem && 15787a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 15797a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 158057dacad5SJay Sternberg 158120d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 158257dacad5SJay Sternberg if (result < 0) 158357dacad5SJay Sternberg return result; 158457dacad5SJay Sternberg 1585147b27e4SSagi Grimberg result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1586d3af3ecdSShaohua Li dev_to_node(dev->dev)); 1587147b27e4SSagi Grimberg if (result) 1588147b27e4SSagi Grimberg return result; 158957dacad5SJay Sternberg 1590147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 159157dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 159257dacad5SJay Sternberg aqa |= aqa << 16; 159357dacad5SJay Sternberg 15947a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 15957a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 15967a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 159757dacad5SJay Sternberg 159820d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 159957dacad5SJay Sternberg if (result) 1600d4875622SKeith Busch return result; 160157dacad5SJay Sternberg 160257dacad5SJay Sternberg nvmeq->cq_vector = 0; 1603161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1604dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 160557dacad5SJay Sternberg if (result) { 160657dacad5SJay Sternberg nvmeq->cq_vector = -1; 1607d4875622SKeith Busch return result; 160857dacad5SJay Sternberg } 160957dacad5SJay Sternberg 161057dacad5SJay Sternberg return result; 161157dacad5SJay Sternberg } 161257dacad5SJay Sternberg 1613749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 161457dacad5SJay Sternberg { 1615949928c1SKeith Busch unsigned i, max; 1616749941f2SChristoph Hellwig int ret = 0; 161757dacad5SJay Sternberg 1618d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1619d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1620147b27e4SSagi Grimberg if (nvme_alloc_queue(dev, i, dev->q_depth, 1621d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1622749941f2SChristoph Hellwig ret = -ENOMEM; 162357dacad5SJay Sternberg break; 1624749941f2SChristoph Hellwig } 1625749941f2SChristoph Hellwig } 162657dacad5SJay Sternberg 1627d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1628949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1629147b27e4SSagi Grimberg ret = nvme_create_queue(&dev->queues[i], i); 1630d4875622SKeith Busch if (ret) 163157dacad5SJay Sternberg break; 163257dacad5SJay Sternberg } 163357dacad5SJay Sternberg 1634749941f2SChristoph Hellwig /* 1635749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 16368adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 16378adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1638749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1639749941f2SChristoph Hellwig */ 1640749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 164157dacad5SJay Sternberg } 164257dacad5SJay Sternberg 1643202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1644202021c1SStephen Bates struct device_attribute *attr, 1645202021c1SStephen Bates char *buf) 1646202021c1SStephen Bates { 1647202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1648202021c1SStephen Bates 1649c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1650202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1651202021c1SStephen Bates } 1652202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1653202021c1SStephen Bates 165457dacad5SJay Sternberg static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 165557dacad5SJay Sternberg { 165657dacad5SJay Sternberg u64 szu, size, offset; 165757dacad5SJay Sternberg resource_size_t bar_size; 165857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 165957dacad5SJay Sternberg void __iomem *cmb; 16608969f1f8SChristoph Hellwig int bar; 166157dacad5SJay Sternberg 16627a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 166357dacad5SJay Sternberg if (!(NVME_CMB_SZ(dev->cmbsz))) 166457dacad5SJay Sternberg return NULL; 1665202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 166657dacad5SJay Sternberg 1667202021c1SStephen Bates if (!use_cmb_sqes) 1668202021c1SStephen Bates return NULL; 166957dacad5SJay Sternberg 167057dacad5SJay Sternberg szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 167157dacad5SJay Sternberg size = szu * NVME_CMB_SZ(dev->cmbsz); 1672202021c1SStephen Bates offset = szu * NVME_CMB_OFST(dev->cmbloc); 16738969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 16748969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 167557dacad5SJay Sternberg 167657dacad5SJay Sternberg if (offset > bar_size) 167757dacad5SJay Sternberg return NULL; 167857dacad5SJay Sternberg 167957dacad5SJay Sternberg /* 168057dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 168157dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 168257dacad5SJay Sternberg * the reported size of the BAR 168357dacad5SJay Sternberg */ 168457dacad5SJay Sternberg if (size > bar_size - offset) 168557dacad5SJay Sternberg size = bar_size - offset; 168657dacad5SJay Sternberg 16878969f1f8SChristoph Hellwig cmb = ioremap_wc(pci_resource_start(pdev, bar) + offset, size); 168857dacad5SJay Sternberg if (!cmb) 168957dacad5SJay Sternberg return NULL; 169057dacad5SJay Sternberg 16918969f1f8SChristoph Hellwig dev->cmb_bus_addr = pci_bus_address(pdev, bar) + offset; 169257dacad5SJay Sternberg dev->cmb_size = size; 169357dacad5SJay Sternberg return cmb; 169457dacad5SJay Sternberg } 169557dacad5SJay Sternberg 169657dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 169757dacad5SJay Sternberg { 169857dacad5SJay Sternberg if (dev->cmb) { 169957dacad5SJay Sternberg iounmap(dev->cmb); 170057dacad5SJay Sternberg dev->cmb = NULL; 1701f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1702f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1703f63572dfSJon Derrick dev->cmbsz = 0; 1704f63572dfSJon Derrick } 170557dacad5SJay Sternberg } 170657dacad5SJay Sternberg 170787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 170857dacad5SJay Sternberg { 17094033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 171087ad72a5SChristoph Hellwig struct nvme_command c; 171187ad72a5SChristoph Hellwig int ret; 171287ad72a5SChristoph Hellwig 171387ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 171487ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 171587ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 171687ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 171787ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 171887ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 171987ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 172087ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 172187ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 172287ad72a5SChristoph Hellwig 172387ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 172487ad72a5SChristoph Hellwig if (ret) { 172587ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 172687ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 172787ad72a5SChristoph Hellwig ret, bits); 172887ad72a5SChristoph Hellwig } 172987ad72a5SChristoph Hellwig return ret; 173087ad72a5SChristoph Hellwig } 173187ad72a5SChristoph Hellwig 173287ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 173387ad72a5SChristoph Hellwig { 173487ad72a5SChristoph Hellwig int i; 173587ad72a5SChristoph Hellwig 173687ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 173787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 173887ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 173987ad72a5SChristoph Hellwig 174087ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 174187ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 174287ad72a5SChristoph Hellwig } 174387ad72a5SChristoph Hellwig 174487ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 174587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 17464033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 17474033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 17484033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 174987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 17507e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 175187ad72a5SChristoph Hellwig } 175287ad72a5SChristoph Hellwig 175392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 175492dc6895SChristoph Hellwig u32 chunk_size) 175587ad72a5SChristoph Hellwig { 175687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 175792dc6895SChristoph Hellwig u32 max_entries, len; 17584033f35dSChristoph Hellwig dma_addr_t descs_dma; 17592ee0e4edSDan Carpenter int i = 0; 176087ad72a5SChristoph Hellwig void **bufs; 17616fbcde66SMinwoo Im u64 size, tmp; 176287ad72a5SChristoph Hellwig 176387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 176487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 176587ad72a5SChristoph Hellwig max_entries = tmp; 1766044a9df1SChristoph Hellwig 1767044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1768044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1769044a9df1SChristoph Hellwig 17704033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 17714033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 177287ad72a5SChristoph Hellwig if (!descs) 177387ad72a5SChristoph Hellwig goto out; 177487ad72a5SChristoph Hellwig 177587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 177687ad72a5SChristoph Hellwig if (!bufs) 177787ad72a5SChristoph Hellwig goto out_free_descs; 177887ad72a5SChristoph Hellwig 1779244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 178087ad72a5SChristoph Hellwig dma_addr_t dma_addr; 178187ad72a5SChristoph Hellwig 178250cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 178387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 178487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 178587ad72a5SChristoph Hellwig if (!bufs[i]) 178687ad72a5SChristoph Hellwig break; 178787ad72a5SChristoph Hellwig 178887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 178987ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 179087ad72a5SChristoph Hellwig i++; 179187ad72a5SChristoph Hellwig } 179287ad72a5SChristoph Hellwig 179392dc6895SChristoph Hellwig if (!size) 179487ad72a5SChristoph Hellwig goto out_free_bufs; 179587ad72a5SChristoph Hellwig 179687ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 179787ad72a5SChristoph Hellwig dev->host_mem_size = size; 179887ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 17994033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 180087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 180187ad72a5SChristoph Hellwig return 0; 180287ad72a5SChristoph Hellwig 180387ad72a5SChristoph Hellwig out_free_bufs: 180487ad72a5SChristoph Hellwig while (--i >= 0) { 180587ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 180687ad72a5SChristoph Hellwig 180787ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 180887ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 180987ad72a5SChristoph Hellwig } 181087ad72a5SChristoph Hellwig 181187ad72a5SChristoph Hellwig kfree(bufs); 181287ad72a5SChristoph Hellwig out_free_descs: 18134033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 18144033f35dSChristoph Hellwig descs_dma); 181587ad72a5SChristoph Hellwig out: 181687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 181787ad72a5SChristoph Hellwig return -ENOMEM; 181887ad72a5SChristoph Hellwig } 181987ad72a5SChristoph Hellwig 182092dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 182192dc6895SChristoph Hellwig { 182292dc6895SChristoph Hellwig u32 chunk_size; 182392dc6895SChristoph Hellwig 182492dc6895SChristoph Hellwig /* start big and work our way down */ 182530f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1826044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 182792dc6895SChristoph Hellwig chunk_size /= 2) { 182892dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 182992dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 183092dc6895SChristoph Hellwig return 0; 183192dc6895SChristoph Hellwig nvme_free_host_mem(dev); 183292dc6895SChristoph Hellwig } 183392dc6895SChristoph Hellwig } 183492dc6895SChristoph Hellwig 183592dc6895SChristoph Hellwig return -ENOMEM; 183692dc6895SChristoph Hellwig } 183792dc6895SChristoph Hellwig 18389620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 183987ad72a5SChristoph Hellwig { 184087ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 184187ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 184287ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 184387ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 18446fbcde66SMinwoo Im int ret; 184587ad72a5SChristoph Hellwig 184687ad72a5SChristoph Hellwig preferred = min(preferred, max); 184787ad72a5SChristoph Hellwig if (min > max) { 184887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 184987ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 185087ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 185187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18529620cfbaSChristoph Hellwig return 0; 185387ad72a5SChristoph Hellwig } 185487ad72a5SChristoph Hellwig 185587ad72a5SChristoph Hellwig /* 185687ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 185787ad72a5SChristoph Hellwig */ 185887ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 185987ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 186087ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 186187ad72a5SChristoph Hellwig else 186287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 186387ad72a5SChristoph Hellwig } 186487ad72a5SChristoph Hellwig 186587ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 186692dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 186792dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 186892dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 18699620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 187087ad72a5SChristoph Hellwig } 187187ad72a5SChristoph Hellwig 187292dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 187392dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 187492dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 187592dc6895SChristoph Hellwig } 187692dc6895SChristoph Hellwig 18779620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 18789620cfbaSChristoph Hellwig if (ret) 187987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 18809620cfbaSChristoph Hellwig return ret; 188157dacad5SJay Sternberg } 188257dacad5SJay Sternberg 188357dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 188457dacad5SJay Sternberg { 1885147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 188657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 188797f6ef64SXu Yu int result, nr_io_queues; 188897f6ef64SXu Yu unsigned long size; 188957dacad5SJay Sternberg 1890425a17cbSChristoph Hellwig nr_io_queues = num_present_cpus(); 18919a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 18929a0be7abSChristoph Hellwig if (result < 0) 189357dacad5SJay Sternberg return result; 18949a0be7abSChristoph Hellwig 1895f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1896a5229050SKeith Busch return 0; 189757dacad5SJay Sternberg 189857dacad5SJay Sternberg if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 189957dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 190057dacad5SJay Sternberg sizeof(struct nvme_command)); 190157dacad5SJay Sternberg if (result > 0) 190257dacad5SJay Sternberg dev->q_depth = result; 190357dacad5SJay Sternberg else 190457dacad5SJay Sternberg nvme_release_cmb(dev); 190557dacad5SJay Sternberg } 190657dacad5SJay Sternberg 190757dacad5SJay Sternberg do { 190897f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 190997f6ef64SXu Yu result = nvme_remap_bar(dev, size); 191097f6ef64SXu Yu if (!result) 191157dacad5SJay Sternberg break; 191257dacad5SJay Sternberg if (!--nr_io_queues) 191357dacad5SJay Sternberg return -ENOMEM; 191457dacad5SJay Sternberg } while (1); 191557dacad5SJay Sternberg adminq->q_db = dev->dbs; 191657dacad5SJay Sternberg 191757dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 19180ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 191957dacad5SJay Sternberg 192057dacad5SJay Sternberg /* 192157dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 192257dacad5SJay Sternberg * setting up the full range we need. 192357dacad5SJay Sternberg */ 1924dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1925dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1926dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1927dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1928dca51e78SChristoph Hellwig return -EIO; 1929dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 193057dacad5SJay Sternberg 193157dacad5SJay Sternberg /* 193257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 193357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 193457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 193557dacad5SJay Sternberg * number of interrupts. 193657dacad5SJay Sternberg */ 193757dacad5SJay Sternberg 1938dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 193957dacad5SJay Sternberg if (result) { 194057dacad5SJay Sternberg adminq->cq_vector = -1; 1941d4875622SKeith Busch return result; 194257dacad5SJay Sternberg } 1943749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 194457dacad5SJay Sternberg } 194557dacad5SJay Sternberg 19462a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1947db3cbfffSKeith Busch { 1948db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1949db3cbfffSKeith Busch 1950db3cbfffSKeith Busch blk_mq_free_request(req); 1951db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1952db3cbfffSKeith Busch } 1953db3cbfffSKeith Busch 19542a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1955db3cbfffSKeith Busch { 1956db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1957db3cbfffSKeith Busch 1958db3cbfffSKeith Busch if (!error) { 1959db3cbfffSKeith Busch unsigned long flags; 1960db3cbfffSKeith Busch 19612e39e0f6SMing Lin /* 19622e39e0f6SMing Lin * We might be called with the AQ q_lock held 19632e39e0f6SMing Lin * and the I/O queue q_lock should always 19642e39e0f6SMing Lin * nest inside the AQ one. 19652e39e0f6SMing Lin */ 19662e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 19672e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1968db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1969db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1970db3cbfffSKeith Busch } 1971db3cbfffSKeith Busch 1972db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1973db3cbfffSKeith Busch } 1974db3cbfffSKeith Busch 1975db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1976db3cbfffSKeith Busch { 1977db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1978db3cbfffSKeith Busch struct request *req; 1979db3cbfffSKeith Busch struct nvme_command cmd; 1980db3cbfffSKeith Busch 1981db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1982db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1983db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1984db3cbfffSKeith Busch 1985eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1986db3cbfffSKeith Busch if (IS_ERR(req)) 1987db3cbfffSKeith Busch return PTR_ERR(req); 1988db3cbfffSKeith Busch 1989db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1990db3cbfffSKeith Busch req->end_io_data = nvmeq; 1991db3cbfffSKeith Busch 1992db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1993db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1994db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1995db3cbfffSKeith Busch return 0; 1996db3cbfffSKeith Busch } 1997db3cbfffSKeith Busch 199870659060SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1999db3cbfffSKeith Busch { 200070659060SKeith Busch int pass; 2001db3cbfffSKeith Busch unsigned long timeout; 2002db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 2003db3cbfffSKeith Busch 2004db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 2005014a0d60SKeith Busch int sent = 0, i = queues; 2006db3cbfffSKeith Busch 2007db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 2008db3cbfffSKeith Busch retry: 2009db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 2010c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 2011147b27e4SSagi Grimberg if (nvme_delete_queue(&dev->queues[i], opcode)) 2012db3cbfffSKeith Busch break; 2013c21377f8SGabriel Krisman Bertazi 2014db3cbfffSKeith Busch while (sent--) { 2015db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 2016db3cbfffSKeith Busch if (timeout == 0) 2017db3cbfffSKeith Busch return; 2018db3cbfffSKeith Busch if (i) 2019db3cbfffSKeith Busch goto retry; 2020db3cbfffSKeith Busch } 2021db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 2022db3cbfffSKeith Busch } 2023db3cbfffSKeith Busch } 2024db3cbfffSKeith Busch 202557dacad5SJay Sternberg /* 20262b1b7e78SJianchao Wang * return error value only when tagset allocation failed 202757dacad5SJay Sternberg */ 202857dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 202957dacad5SJay Sternberg { 20302b1b7e78SJianchao Wang int ret; 20312b1b7e78SJianchao Wang 20325bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 203357dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 203457dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 203557dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 203657dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 203757dacad5SJay Sternberg dev->tagset.queue_depth = 203857dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2039a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2040a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2041a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2042a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2043a7a7cbe3SChaitanya Kulkarni } 204457dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 204557dacad5SJay Sternberg dev->tagset.driver_data = dev; 204657dacad5SJay Sternberg 20472b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 20482b1b7e78SJianchao Wang if (ret) { 20492b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 20502b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 20512b1b7e78SJianchao Wang return ret; 20522b1b7e78SJianchao Wang } 20535bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2054f9f38e33SHelen Koike 2055f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2056949928c1SKeith Busch } else { 2057949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2058949928c1SKeith Busch 2059949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2060949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 206157dacad5SJay Sternberg } 2062949928c1SKeith Busch 206357dacad5SJay Sternberg return 0; 206457dacad5SJay Sternberg } 206557dacad5SJay Sternberg 2066b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 206757dacad5SJay Sternberg { 2068b00a726aSKeith Busch int result = -ENOMEM; 206957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 207057dacad5SJay Sternberg 207157dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 207257dacad5SJay Sternberg return result; 207357dacad5SJay Sternberg 207457dacad5SJay Sternberg pci_set_master(pdev); 207557dacad5SJay Sternberg 207657dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 207757dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 207857dacad5SJay Sternberg goto disable; 207957dacad5SJay Sternberg 20807a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 208157dacad5SJay Sternberg result = -ENODEV; 2082b00a726aSKeith Busch goto disable; 208357dacad5SJay Sternberg } 208457dacad5SJay Sternberg 208557dacad5SJay Sternberg /* 2086a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2087a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2088a5229050SKeith Busch * adjust this later. 208957dacad5SJay Sternberg */ 2090dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2091dca51e78SChristoph Hellwig if (result < 0) 2092dca51e78SChristoph Hellwig return result; 209357dacad5SJay Sternberg 209420d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 20957a67cbeaSChristoph Hellwig 209620d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2097b27c1e68Sweiping zhang io_queue_depth); 209820d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 20997a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 21001f390c1fSStephan Günther 21011f390c1fSStephan Günther /* 21021f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 21031f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 21041f390c1fSStephan Günther */ 21051f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 21061f390c1fSStephan Günther dev->q_depth = 2; 21079bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 21089bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 21091f390c1fSStephan Günther dev->q_depth); 2110d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2111d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 211220d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2113d554b5e1SMartin K. Petersen dev->q_depth = 64; 2114d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2115d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 21161f390c1fSStephan Günther } 21171f390c1fSStephan Günther 2118202021c1SStephen Bates /* 2119202021c1SStephen Bates * CMBs can currently only exist on >=1.2 PCIe devices. We only 21201c78f773SMax Gurtovoy * populate sysfs if a CMB is implemented. Since nvme_dev_attrs_group 21211c78f773SMax Gurtovoy * has no name we can pass NULL as final argument to 21221c78f773SMax Gurtovoy * sysfs_add_file_to_group. 2123202021c1SStephen Bates */ 2124202021c1SStephen Bates 21258ef2074dSGabriel Krisman Bertazi if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 212657dacad5SJay Sternberg dev->cmb = nvme_map_cmb(dev); 21271c78f773SMax Gurtovoy if (dev->cmb) { 2128202021c1SStephen Bates if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 2129202021c1SStephen Bates &dev_attr_cmb.attr, NULL)) 21309bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 2131202021c1SStephen Bates "failed to add sysfs attribute for CMB\n"); 2132202021c1SStephen Bates } 2133202021c1SStephen Bates } 2134202021c1SStephen Bates 2135a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2136a0a3408eSKeith Busch pci_save_state(pdev); 213757dacad5SJay Sternberg return 0; 213857dacad5SJay Sternberg 213957dacad5SJay Sternberg disable: 214057dacad5SJay Sternberg pci_disable_device(pdev); 214157dacad5SJay Sternberg return result; 214257dacad5SJay Sternberg } 214357dacad5SJay Sternberg 214457dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 214557dacad5SJay Sternberg { 2146b00a726aSKeith Busch if (dev->bar) 2147b00a726aSKeith Busch iounmap(dev->bar); 2148a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2149b00a726aSKeith Busch } 2150b00a726aSKeith Busch 2151b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2152b00a726aSKeith Busch { 215357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 215457dacad5SJay Sternberg 2155f63572dfSJon Derrick nvme_release_cmb(dev); 2156dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 215757dacad5SJay Sternberg 2158a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2159a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 216057dacad5SJay Sternberg pci_disable_device(pdev); 216157dacad5SJay Sternberg } 2162a0a3408eSKeith Busch } 216357dacad5SJay Sternberg 2164a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 216557dacad5SJay Sternberg { 216670659060SKeith Busch int i, queues; 2167302ad8ccSKeith Busch bool dead = true; 2168302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 216957dacad5SJay Sternberg 217077bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2171302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2172302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2173302ad8ccSKeith Busch 2174ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2175ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2176302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2177302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2178302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 217957dacad5SJay Sternberg } 2180c21377f8SGabriel Krisman Bertazi 2181302ad8ccSKeith Busch /* 2182302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2183302ad8ccSKeith Busch * doing a safe shutdown. 2184302ad8ccSKeith Busch */ 218587ad72a5SChristoph Hellwig if (!dead) { 218687ad72a5SChristoph Hellwig if (shutdown) 2187302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 218887ad72a5SChristoph Hellwig 218987ad72a5SChristoph Hellwig /* 219087ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 219187ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 219287ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 219387ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 219487ad72a5SChristoph Hellwig */ 219587ad72a5SChristoph Hellwig if (dev->host_mem_descs) 219687ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 219787ad72a5SChristoph Hellwig 219887ad72a5SChristoph Hellwig } 2199302ad8ccSKeith Busch nvme_stop_queues(&dev->ctrl); 2200302ad8ccSKeith Busch 220170659060SKeith Busch queues = dev->online_queues - 1; 2202d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i > 0; i--) 2203147b27e4SSagi Grimberg nvme_suspend_queue(&dev->queues[i]); 2204c21377f8SGabriel Krisman Bertazi 2205302ad8ccSKeith Busch if (dead) { 220682469c59SGabriel Krisman Bertazi /* A device might become IO incapable very soon during 220782469c59SGabriel Krisman Bertazi * probe, before the admin queue is configured. Thus, 220882469c59SGabriel Krisman Bertazi * queue_count can be 0 here. 220982469c59SGabriel Krisman Bertazi */ 2210d858e5f0SSagi Grimberg if (dev->ctrl.queue_count) 2211147b27e4SSagi Grimberg nvme_suspend_queue(&dev->queues[0]); 221257dacad5SJay Sternberg } else { 221370659060SKeith Busch nvme_disable_io_queues(dev, queues); 2214a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 221557dacad5SJay Sternberg } 2216b00a726aSKeith Busch nvme_pci_disable(dev); 221757dacad5SJay Sternberg 2218e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2219e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2220302ad8ccSKeith Busch 2221302ad8ccSKeith Busch /* 2222302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2223302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2224302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2225302ad8ccSKeith Busch */ 2226302ad8ccSKeith Busch if (shutdown) 2227302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 222877bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 222957dacad5SJay Sternberg } 223057dacad5SJay Sternberg 223157dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 223257dacad5SJay Sternberg { 223357dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 223457dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 223557dacad5SJay Sternberg if (!dev->prp_page_pool) 223657dacad5SJay Sternberg return -ENOMEM; 223757dacad5SJay Sternberg 223857dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 223957dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 224057dacad5SJay Sternberg 256, 256, 0); 224157dacad5SJay Sternberg if (!dev->prp_small_pool) { 224257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 224357dacad5SJay Sternberg return -ENOMEM; 224457dacad5SJay Sternberg } 224557dacad5SJay Sternberg return 0; 224657dacad5SJay Sternberg } 224757dacad5SJay Sternberg 224857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 224957dacad5SJay Sternberg { 225057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 225157dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 225257dacad5SJay Sternberg } 225357dacad5SJay Sternberg 22541673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 225557dacad5SJay Sternberg { 22561673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 225757dacad5SJay Sternberg 2258f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 225957dacad5SJay Sternberg put_device(dev->dev); 226057dacad5SJay Sternberg if (dev->tagset.tags) 226157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 22621c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 22631c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 226457dacad5SJay Sternberg kfree(dev->queues); 2265e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 226657dacad5SJay Sternberg kfree(dev); 226757dacad5SJay Sternberg } 226857dacad5SJay Sternberg 2269f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2270f58944e2SKeith Busch { 2271237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2272f58944e2SKeith Busch 2273d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 227469d9a99cSKeith Busch nvme_dev_disable(dev, false); 227503e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2276f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2277f58944e2SKeith Busch } 2278f58944e2SKeith Busch 2279fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 228057dacad5SJay Sternberg { 2281d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2282d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2283a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2284f58944e2SKeith Busch int result = -ENODEV; 22852b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 228657dacad5SJay Sternberg 228782b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2288fd634f41SChristoph Hellwig goto out; 2289fd634f41SChristoph Hellwig 2290fd634f41SChristoph Hellwig /* 2291fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2292fd634f41SChristoph Hellwig * moving on. 2293fd634f41SChristoph Hellwig */ 2294b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2295a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2296fd634f41SChristoph Hellwig 2297b00a726aSKeith Busch result = nvme_pci_enable(dev); 229857dacad5SJay Sternberg if (result) 229957dacad5SJay Sternberg goto out; 230057dacad5SJay Sternberg 230101ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 230257dacad5SJay Sternberg if (result) 2303f58944e2SKeith Busch goto out; 230457dacad5SJay Sternberg 230557dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 230657dacad5SJay Sternberg if (result) 2307f58944e2SKeith Busch goto out; 230857dacad5SJay Sternberg 2309ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2310ce4541f4SChristoph Hellwig if (result) 2311f58944e2SKeith Busch goto out; 2312ce4541f4SChristoph Hellwig 2313e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2314e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 23154f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 23164f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2317e286bcfcSScott Bauer else if (was_suspend) 23184f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2319e286bcfcSScott Bauer } else { 2320e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2321e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2322e286bcfcSScott Bauer } 2323a98e58e5SScott Bauer 2324f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2325f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2326f9f38e33SHelen Koike if (result) 2327f9f38e33SHelen Koike dev_warn(dev->dev, 2328f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2329f9f38e33SHelen Koike } 2330f9f38e33SHelen Koike 23319620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 23329620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 23339620cfbaSChristoph Hellwig if (result < 0) 23349620cfbaSChristoph Hellwig goto out; 23359620cfbaSChristoph Hellwig } 233687ad72a5SChristoph Hellwig 233757dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 233857dacad5SJay Sternberg if (result) 2339f58944e2SKeith Busch goto out; 234057dacad5SJay Sternberg 234121f033f7SKeith Busch /* 234257dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 234357dacad5SJay Sternberg * any working I/O queue. 234457dacad5SJay Sternberg */ 234557dacad5SJay Sternberg if (dev->online_queues < 2) { 23461b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 23473b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 23485bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 23492b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 235057dacad5SJay Sternberg } else { 235125646264SKeith Busch nvme_start_queues(&dev->ctrl); 2352302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 23532b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 23542b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 23552b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2356302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 235757dacad5SJay Sternberg } 235857dacad5SJay Sternberg 23592b1b7e78SJianchao Wang /* 23602b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 23612b1b7e78SJianchao Wang * recovery. 23622b1b7e78SJianchao Wang */ 23632b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 23642b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23652b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2366bb8d261eSChristoph Hellwig goto out; 2367bb8d261eSChristoph Hellwig } 236892911a55SChristoph Hellwig 2369d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 237057dacad5SJay Sternberg return; 237157dacad5SJay Sternberg 237257dacad5SJay Sternberg out: 2373f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 237457dacad5SJay Sternberg } 237557dacad5SJay Sternberg 23765c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 237757dacad5SJay Sternberg { 23785c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 237957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 238057dacad5SJay Sternberg 238169d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 238257dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2383921920abSKeith Busch device_release_driver(&pdev->dev); 23841673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 238557dacad5SJay Sternberg } 238657dacad5SJay Sternberg 23871c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 238857dacad5SJay Sternberg { 23891c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 23901c63dc66SChristoph Hellwig return 0; 239157dacad5SJay Sternberg } 23921c63dc66SChristoph Hellwig 23935fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 23945fd4ce1bSChristoph Hellwig { 23955fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 23965fd4ce1bSChristoph Hellwig return 0; 23975fd4ce1bSChristoph Hellwig } 23985fd4ce1bSChristoph Hellwig 23997fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 24007fd8930fSChristoph Hellwig { 24017fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 24027fd8930fSChristoph Hellwig return 0; 24037fd8930fSChristoph Hellwig } 24047fd8930fSChristoph Hellwig 24051c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 24061a353d85SMing Lin .name = "pcie", 2407e439bb12SSagi Grimberg .module = THIS_MODULE, 2408c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 24091c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 24105fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 24117fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 24121673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2413f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 24141c63dc66SChristoph Hellwig }; 241557dacad5SJay Sternberg 2416b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2417b00a726aSKeith Busch { 2418b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2419b00a726aSKeith Busch 2420a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2421b00a726aSKeith Busch return -ENODEV; 2422b00a726aSKeith Busch 242397f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2424b00a726aSKeith Busch goto release; 2425b00a726aSKeith Busch 2426b00a726aSKeith Busch return 0; 2427b00a726aSKeith Busch release: 2428a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2429b00a726aSKeith Busch return -ENODEV; 2430b00a726aSKeith Busch } 2431b00a726aSKeith Busch 24328427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2433ff5350a8SAndy Lutomirski { 2434ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2435ff5350a8SAndy Lutomirski /* 2436ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2437ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2438ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2439ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2440ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2441ff5350a8SAndy Lutomirski * laptops. 2442ff5350a8SAndy Lutomirski */ 2443ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2444ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2445ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2446ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 24478427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 24488427bbc2SKai-Heng Feng /* 24498427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 24508427bbc2SKai-Heng Feng * suspend on a Ryzen board, ASUS PRIME B350M-A. 24518427bbc2SKai-Heng Feng */ 24528427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 24538427bbc2SKai-Heng Feng dmi_match(DMI_BOARD_NAME, "PRIME B350M-A")) 24548427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2455ff5350a8SAndy Lutomirski } 2456ff5350a8SAndy Lutomirski 2457ff5350a8SAndy Lutomirski return 0; 2458ff5350a8SAndy Lutomirski } 2459ff5350a8SAndy Lutomirski 246057dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 246157dacad5SJay Sternberg { 246257dacad5SJay Sternberg int node, result = -ENOMEM; 246357dacad5SJay Sternberg struct nvme_dev *dev; 2464ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 246557dacad5SJay Sternberg 246657dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 246757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 24682fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 246957dacad5SJay Sternberg 247057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 247157dacad5SJay Sternberg if (!dev) 247257dacad5SJay Sternberg return -ENOMEM; 2473147b27e4SSagi Grimberg 2474147b27e4SSagi Grimberg dev->queues = kcalloc_node(num_possible_cpus() + 1, 2475147b27e4SSagi Grimberg sizeof(struct nvme_queue), GFP_KERNEL, node); 247657dacad5SJay Sternberg if (!dev->queues) 247757dacad5SJay Sternberg goto free; 247857dacad5SJay Sternberg 247957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 248057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 248157dacad5SJay Sternberg 2482b00a726aSKeith Busch result = nvme_dev_map(dev); 2483b00a726aSKeith Busch if (result) 2484b00c9b7aSChristophe JAILLET goto put_pci; 2485b00a726aSKeith Busch 2486d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 24875c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 248877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2489db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2490f3ca80fcSChristoph Hellwig 2491f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2492f3ca80fcSChristoph Hellwig if (result) 2493b00c9b7aSChristophe JAILLET goto unmap; 2494f3ca80fcSChristoph Hellwig 24958427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2496ff5350a8SAndy Lutomirski 2497f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2498ff5350a8SAndy Lutomirski quirks); 2499f3ca80fcSChristoph Hellwig if (result) 2500f3ca80fcSChristoph Hellwig goto release_pools; 2501f3ca80fcSChristoph Hellwig 25021b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 25031b3c47c1SSagi Grimberg 25044caff8fcSSagi Grimberg nvme_reset_ctrl(&dev->ctrl); 25054caff8fcSSagi Grimberg 250657dacad5SJay Sternberg return 0; 250757dacad5SJay Sternberg 250857dacad5SJay Sternberg release_pools: 250957dacad5SJay Sternberg nvme_release_prp_pools(dev); 2510b00c9b7aSChristophe JAILLET unmap: 2511b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 251257dacad5SJay Sternberg put_pci: 251357dacad5SJay Sternberg put_device(dev->dev); 251457dacad5SJay Sternberg free: 251557dacad5SJay Sternberg kfree(dev->queues); 251657dacad5SJay Sternberg kfree(dev); 251757dacad5SJay Sternberg return result; 251857dacad5SJay Sternberg } 251957dacad5SJay Sternberg 2520775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 252157dacad5SJay Sternberg { 252257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2523a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2524775755edSChristoph Hellwig } 252557dacad5SJay Sternberg 2526775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2527775755edSChristoph Hellwig { 2528f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 252979c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 253057dacad5SJay Sternberg } 253157dacad5SJay Sternberg 253257dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 253357dacad5SJay Sternberg { 253457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2535a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 253657dacad5SJay Sternberg } 253757dacad5SJay Sternberg 2538f58944e2SKeith Busch /* 2539f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2540f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2541f58944e2SKeith Busch * order to proceed. 2542f58944e2SKeith Busch */ 254357dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 254457dacad5SJay Sternberg { 254557dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 254657dacad5SJay Sternberg 2547bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2548bb8d261eSChristoph Hellwig 2549d86c4d8eSChristoph Hellwig cancel_work_sync(&dev->ctrl.reset_work); 255057dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 25510ff9d4e1SKeith Busch 25526db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 25530ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 25546db28edaSKeith Busch nvme_dev_disable(dev, false); 25556db28edaSKeith Busch } 25560ff9d4e1SKeith Busch 2557d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2558d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2559d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2560a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 256187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 256257dacad5SJay Sternberg nvme_dev_remove_admin(dev); 256357dacad5SJay Sternberg nvme_free_queues(dev, 0); 2564d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 256557dacad5SJay Sternberg nvme_release_prp_pools(dev); 2566b00a726aSKeith Busch nvme_dev_unmap(dev); 25671673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 256857dacad5SJay Sternberg } 256957dacad5SJay Sternberg 257013880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 257113880f5bSKeith Busch { 257213880f5bSKeith Busch int ret = 0; 257313880f5bSKeith Busch 257413880f5bSKeith Busch if (numvfs == 0) { 257513880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 257613880f5bSKeith Busch dev_warn(&pdev->dev, 257713880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 257813880f5bSKeith Busch return -EPERM; 257913880f5bSKeith Busch } 258013880f5bSKeith Busch pci_disable_sriov(pdev); 258113880f5bSKeith Busch return 0; 258213880f5bSKeith Busch } 258313880f5bSKeith Busch 258413880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 258513880f5bSKeith Busch return ret ? ret : numvfs; 258613880f5bSKeith Busch } 258713880f5bSKeith Busch 258857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 258957dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 259057dacad5SJay Sternberg { 259157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 259257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 259357dacad5SJay Sternberg 2594a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 259557dacad5SJay Sternberg return 0; 259657dacad5SJay Sternberg } 259757dacad5SJay Sternberg 259857dacad5SJay Sternberg static int nvme_resume(struct device *dev) 259957dacad5SJay Sternberg { 260057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 260157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 260257dacad5SJay Sternberg 2603d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 260457dacad5SJay Sternberg return 0; 260557dacad5SJay Sternberg } 260657dacad5SJay Sternberg #endif 260757dacad5SJay Sternberg 260857dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 260957dacad5SJay Sternberg 2610a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2611a0a3408eSKeith Busch pci_channel_state_t state) 2612a0a3408eSKeith Busch { 2613a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2614a0a3408eSKeith Busch 2615a0a3408eSKeith Busch /* 2616a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2617a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2618a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2619a0a3408eSKeith Busch */ 2620a0a3408eSKeith Busch switch (state) { 2621a0a3408eSKeith Busch case pci_channel_io_normal: 2622a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2623a0a3408eSKeith Busch case pci_channel_io_frozen: 2624d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2625d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2626a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2627a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2628a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2629d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2630d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2631a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2632a0a3408eSKeith Busch } 2633a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2634a0a3408eSKeith Busch } 2635a0a3408eSKeith Busch 2636a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2637a0a3408eSKeith Busch { 2638a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2639a0a3408eSKeith Busch 26401b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2641a0a3408eSKeith Busch pci_restore_state(pdev); 2642d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2643a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2644a0a3408eSKeith Busch } 2645a0a3408eSKeith Busch 2646a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2647a0a3408eSKeith Busch { 2648a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2649a0a3408eSKeith Busch } 2650a0a3408eSKeith Busch 265157dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 265257dacad5SJay Sternberg .error_detected = nvme_error_detected, 265357dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 265457dacad5SJay Sternberg .resume = nvme_error_resume, 2655775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2656775755edSChristoph Hellwig .reset_done = nvme_reset_done, 265757dacad5SJay Sternberg }; 265857dacad5SJay Sternberg 265957dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2660106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 266108095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2662e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 266399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 266499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2665e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 266699466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 266799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2668e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2669f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2670f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2671f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 267250af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 267350af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2674540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2675540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 267654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 267754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 26788c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 26798c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2680015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2681015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2682d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2683d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2684d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2685d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2686608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2687608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2688608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2689608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 269057dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2691c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2692124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 269357dacad5SJay Sternberg { 0, } 269457dacad5SJay Sternberg }; 269557dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 269657dacad5SJay Sternberg 269757dacad5SJay Sternberg static struct pci_driver nvme_driver = { 269857dacad5SJay Sternberg .name = "nvme", 269957dacad5SJay Sternberg .id_table = nvme_id_table, 270057dacad5SJay Sternberg .probe = nvme_probe, 270157dacad5SJay Sternberg .remove = nvme_remove, 270257dacad5SJay Sternberg .shutdown = nvme_shutdown, 270357dacad5SJay Sternberg .driver = { 270457dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 270557dacad5SJay Sternberg }, 270613880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 270757dacad5SJay Sternberg .err_handler = &nvme_err_handler, 270857dacad5SJay Sternberg }; 270957dacad5SJay Sternberg 271057dacad5SJay Sternberg static int __init nvme_init(void) 271157dacad5SJay Sternberg { 27129a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 271357dacad5SJay Sternberg } 271457dacad5SJay Sternberg 271557dacad5SJay Sternberg static void __exit nvme_exit(void) 271657dacad5SJay Sternberg { 271757dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 271803e0f3a6SMing Lei flush_workqueue(nvme_wq); 271957dacad5SJay Sternberg _nvme_check_size(); 272057dacad5SJay Sternberg } 272157dacad5SJay Sternberg 272257dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 272357dacad5SJay Sternberg MODULE_LICENSE("GPL"); 272457dacad5SJay Sternberg MODULE_VERSION("1.0"); 272557dacad5SJay Sternberg module_init(nvme_init); 272657dacad5SJay Sternberg module_exit(nvme_exit); 2727