15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7a0a3408eSKeith Busch #include <linux/aer.h> 818119775SKeith Busch #include <linux/async.h> 957dacad5SJay Sternberg #include <linux/blkdev.h> 1057dacad5SJay Sternberg #include <linux/blk-mq.h> 11dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 12ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1357dacad5SJay Sternberg #include <linux/init.h> 1457dacad5SJay Sternberg #include <linux/interrupt.h> 1557dacad5SJay Sternberg #include <linux/io.h> 1657dacad5SJay Sternberg #include <linux/mm.h> 1757dacad5SJay Sternberg #include <linux/module.h> 1877bf25eaSKeith Busch #include <linux/mutex.h> 19d0877473SKeith Busch #include <linux/once.h> 2057dacad5SJay Sternberg #include <linux/pci.h> 2157dacad5SJay Sternberg #include <linux/t10-pi.h> 2257dacad5SJay Sternberg #include <linux/types.h> 239cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 24a98e58e5SScott Bauer #include <linux/sed-opal.h> 250f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 2657dacad5SJay Sternberg 27604c01d5Syupeng #include "trace.h" 2857dacad5SJay Sternberg #include "nvme.h" 2957dacad5SJay Sternberg 3057dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3157dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3257dacad5SJay Sternberg 33a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 34adf68f21SChristoph Hellwig 35943e942eSJens Axboe /* 36943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 37943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 38943e942eSJens Axboe */ 39943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 40943e942eSJens Axboe #define NVME_MAX_SEGS 127 41943e942eSJens Axboe 4257dacad5SJay Sternberg static int use_threaded_interrupts; 4357dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 4457dacad5SJay Sternberg 4557dacad5SJay Sternberg static bool use_cmb_sqes = true; 4669f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 4757dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 4857dacad5SJay Sternberg 4987ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5087ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5187ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5287ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5357dacad5SJay Sternberg 54a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 55a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 56a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 57a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 58a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 59a7a7cbe3SChaitanya Kulkarni 60b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 61b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 62b27c1e68Sweiping zhang .set = io_queue_depth_set, 63b27c1e68Sweiping zhang .get = param_get_int, 64b27c1e68Sweiping zhang }; 65b27c1e68Sweiping zhang 66b27c1e68Sweiping zhang static int io_queue_depth = 1024; 67b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 68b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 69b27c1e68Sweiping zhang 703b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 713b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 723b6592f7SJens Axboe .set = queue_count_set, 733b6592f7SJens Axboe .get = param_get_int, 743b6592f7SJens Axboe }; 753b6592f7SJens Axboe 763b6592f7SJens Axboe static int write_queues; 773b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 783b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 793b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 803b6592f7SJens Axboe "will share a queue set."); 813b6592f7SJens Axboe 82a4668d9bSJens Axboe static int poll_queues = 0; 834b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 844b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 854b04cc6aSJens Axboe 861c63dc66SChristoph Hellwig struct nvme_dev; 871c63dc66SChristoph Hellwig struct nvme_queue; 8857dacad5SJay Sternberg 89a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 908fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 9157dacad5SJay Sternberg 9257dacad5SJay Sternberg /* 931c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 941c63dc66SChristoph Hellwig */ 951c63dc66SChristoph Hellwig struct nvme_dev { 96147b27e4SSagi Grimberg struct nvme_queue *queues; 971c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 981c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 991c63dc66SChristoph Hellwig u32 __iomem *dbs; 1001c63dc66SChristoph Hellwig struct device *dev; 1011c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1021c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1031c63dc66SChristoph Hellwig unsigned online_queues; 1041c63dc66SChristoph Hellwig unsigned max_qid; 105e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 10622b55601SKeith Busch unsigned int num_vecs; 1071c63dc66SChristoph Hellwig int q_depth; 1081c63dc66SChristoph Hellwig u32 db_stride; 1091c63dc66SChristoph Hellwig void __iomem *bar; 11097f6ef64SXu Yu unsigned long bar_mapped_size; 1115c8809e6SChristoph Hellwig struct work_struct remove_work; 11277bf25eaSKeith Busch struct mutex shutdown_lock; 1131c63dc66SChristoph Hellwig bool subsystem; 1141c63dc66SChristoph Hellwig u64 cmb_size; 1150f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1161c63dc66SChristoph Hellwig u32 cmbsz; 117202021c1SStephen Bates u32 cmbloc; 1181c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 11987ad72a5SChristoph Hellwig 120943e942eSJens Axboe mempool_t *iod_mempool; 121943e942eSJens Axboe 12287ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 123f9f38e33SHelen Koike u32 *dbbuf_dbs; 124f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 125f9f38e33SHelen Koike u32 *dbbuf_eis; 126f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 12787ad72a5SChristoph Hellwig 12887ad72a5SChristoph Hellwig /* host memory buffer support: */ 12987ad72a5SChristoph Hellwig u64 host_mem_size; 13087ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1314033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 13457dacad5SJay Sternberg }; 13557dacad5SJay Sternberg 136b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 137b27c1e68Sweiping zhang { 138b27c1e68Sweiping zhang int n = 0, ret; 139b27c1e68Sweiping zhang 140b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 141b27c1e68Sweiping zhang if (ret != 0 || n < 2) 142b27c1e68Sweiping zhang return -EINVAL; 143b27c1e68Sweiping zhang 144b27c1e68Sweiping zhang return param_set_int(val, kp); 145b27c1e68Sweiping zhang } 146b27c1e68Sweiping zhang 1473b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1483b6592f7SJens Axboe { 1493b6592f7SJens Axboe int n = 0, ret; 1503b6592f7SJens Axboe 1513b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 152e895fedfSBart Van Assche if (ret) 153e895fedfSBart Van Assche return ret; 1543b6592f7SJens Axboe if (n > num_possible_cpus()) 1553b6592f7SJens Axboe n = num_possible_cpus(); 1563b6592f7SJens Axboe 1573b6592f7SJens Axboe return param_set_int(val, kp); 1583b6592f7SJens Axboe } 1593b6592f7SJens Axboe 160f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 161f9f38e33SHelen Koike { 162f9f38e33SHelen Koike return qid * 2 * stride; 163f9f38e33SHelen Koike } 164f9f38e33SHelen Koike 165f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 166f9f38e33SHelen Koike { 167f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 168f9f38e33SHelen Koike } 169f9f38e33SHelen Koike 1701c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1711c63dc66SChristoph Hellwig { 1721c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1731c63dc66SChristoph Hellwig } 1741c63dc66SChristoph Hellwig 17557dacad5SJay Sternberg /* 17657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 17757dacad5SJay Sternberg * commands and one for I/O commands). 17857dacad5SJay Sternberg */ 17957dacad5SJay Sternberg struct nvme_queue { 18057dacad5SJay Sternberg struct nvme_dev *dev; 1811ab0cd69SJens Axboe spinlock_t sq_lock; 18257dacad5SJay Sternberg struct nvme_command *sq_cmds; 1833a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1843a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 18557dacad5SJay Sternberg volatile struct nvme_completion *cqes; 18657dacad5SJay Sternberg struct blk_mq_tags **tags; 18757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 18857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 18957dacad5SJay Sternberg u32 __iomem *q_db; 19057dacad5SJay Sternberg u16 q_depth; 1917c349ddeSKeith Busch u16 cq_vector; 19257dacad5SJay Sternberg u16 sq_tail; 19304f3eafdSJens Axboe u16 last_sq_tail; 19457dacad5SJay Sternberg u16 cq_head; 19568fa9dbeSJens Axboe u16 last_cq_head; 19657dacad5SJay Sternberg u16 qid; 19757dacad5SJay Sternberg u8 cq_phase; 1984e224106SChristoph Hellwig unsigned long flags; 1994e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 201d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2027c349ddeSKeith Busch #define NVMEQ_POLLED 3 203f9f38e33SHelen Koike u32 *dbbuf_sq_db; 204f9f38e33SHelen Koike u32 *dbbuf_cq_db; 205f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 206f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 207d1ed6aa1SChristoph Hellwig struct completion delete_done; 20857dacad5SJay Sternberg }; 20957dacad5SJay Sternberg 21057dacad5SJay Sternberg /* 21171bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 21271bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 213f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 21471bd150cSChristoph Hellwig * allocated to store the PRP list. 21571bd150cSChristoph Hellwig */ 21671bd150cSChristoph Hellwig struct nvme_iod { 217d49187e9SChristoph Hellwig struct nvme_request req; 218f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 219a7a7cbe3SChaitanya Kulkarni bool use_sgl; 220f4800d6dSChristoph Hellwig int aborted; 22171bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22271bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22371bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 22471bd150cSChristoph Hellwig dma_addr_t first_dma; 225bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 226f4800d6dSChristoph Hellwig struct scatterlist *sg; 227f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 22857dacad5SJay Sternberg }; 22957dacad5SJay Sternberg 23057dacad5SJay Sternberg /* 23157dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23257dacad5SJay Sternberg */ 23357dacad5SJay Sternberg static inline void _nvme_check_size(void) 23457dacad5SJay Sternberg { 23557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 23657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 23757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 23857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2430add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2440add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 24657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 247f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 248f9f38e33SHelen Koike } 249f9f38e33SHelen Koike 2503b6592f7SJens Axboe static unsigned int max_io_queues(void) 2513b6592f7SJens Axboe { 2524b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2533b6592f7SJens Axboe } 2543b6592f7SJens Axboe 2553b6592f7SJens Axboe static unsigned int max_queue_count(void) 2563b6592f7SJens Axboe { 2573b6592f7SJens Axboe /* IO queues + admin queue */ 2583b6592f7SJens Axboe return 1 + max_io_queues(); 2593b6592f7SJens Axboe } 2603b6592f7SJens Axboe 261f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 262f9f38e33SHelen Koike { 2633b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 264f9f38e33SHelen Koike } 265f9f38e33SHelen Koike 266f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 267f9f38e33SHelen Koike { 268f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike if (dev->dbbuf_dbs) 271f9f38e33SHelen Koike return 0; 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 274f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 275f9f38e33SHelen Koike GFP_KERNEL); 276f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 277f9f38e33SHelen Koike return -ENOMEM; 278f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 279f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 280f9f38e33SHelen Koike GFP_KERNEL); 281f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 282f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 283f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 284f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 285f9f38e33SHelen Koike return -ENOMEM; 286f9f38e33SHelen Koike } 287f9f38e33SHelen Koike 288f9f38e33SHelen Koike return 0; 289f9f38e33SHelen Koike } 290f9f38e33SHelen Koike 291f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 292f9f38e33SHelen Koike { 293f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 296f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 297f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 298f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 299f9f38e33SHelen Koike } 300f9f38e33SHelen Koike if (dev->dbbuf_eis) { 301f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 302f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 303f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 304f9f38e33SHelen Koike } 305f9f38e33SHelen Koike } 306f9f38e33SHelen Koike 307f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 308f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 309f9f38e33SHelen Koike { 310f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 311f9f38e33SHelen Koike return; 312f9f38e33SHelen Koike 313f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 314f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 315f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 316f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 317f9f38e33SHelen Koike } 318f9f38e33SHelen Koike 319f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 320f9f38e33SHelen Koike { 321f9f38e33SHelen Koike struct nvme_command c; 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 324f9f38e33SHelen Koike return; 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 327f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 328f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 329f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 330f9f38e33SHelen Koike 331f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3329bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 333f9f38e33SHelen Koike /* Free memory and continue on */ 334f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike } 337f9f38e33SHelen Koike 338f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 339f9f38e33SHelen Koike { 340f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 341f9f38e33SHelen Koike } 342f9f38e33SHelen Koike 343f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 344f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 345f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 346f9f38e33SHelen Koike { 347f9f38e33SHelen Koike if (dbbuf_db) { 348f9f38e33SHelen Koike u16 old_value; 349f9f38e33SHelen Koike 350f9f38e33SHelen Koike /* 351f9f38e33SHelen Koike * Ensure that the queue is written before updating 352f9f38e33SHelen Koike * the doorbell in memory 353f9f38e33SHelen Koike */ 354f9f38e33SHelen Koike wmb(); 355f9f38e33SHelen Koike 356f9f38e33SHelen Koike old_value = *dbbuf_db; 357f9f38e33SHelen Koike *dbbuf_db = value; 358f9f38e33SHelen Koike 359f1ed3df2SMichal Wnukowski /* 360f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 361f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 362f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 363f1ed3df2SMichal Wnukowski * the doorbell. 364f1ed3df2SMichal Wnukowski */ 365f1ed3df2SMichal Wnukowski mb(); 366f1ed3df2SMichal Wnukowski 367f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 368f9f38e33SHelen Koike return false; 369f9f38e33SHelen Koike } 370f9f38e33SHelen Koike 371f9f38e33SHelen Koike return true; 37257dacad5SJay Sternberg } 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg /* 37557dacad5SJay Sternberg * Max size of iod being embedded in the request payload 37657dacad5SJay Sternberg */ 37757dacad5SJay Sternberg #define NVME_INT_PAGES 2 3785fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 37957dacad5SJay Sternberg 38057dacad5SJay Sternberg /* 38157dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38257dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38357dacad5SJay Sternberg * the I/O. 38457dacad5SJay Sternberg */ 38557dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 38657dacad5SJay Sternberg { 3875fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3885fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 38957dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 39057dacad5SJay Sternberg } 39157dacad5SJay Sternberg 392a7a7cbe3SChaitanya Kulkarni /* 393a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 394a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 395a7a7cbe3SChaitanya Kulkarni */ 396a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 397f4800d6dSChristoph Hellwig { 398a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 399f4800d6dSChristoph Hellwig } 400f4800d6dSChristoph Hellwig 401a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 402a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 40357dacad5SJay Sternberg { 404a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 405a7a7cbe3SChaitanya Kulkarni 406a7a7cbe3SChaitanya Kulkarni if (use_sgl) 407a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 408a7a7cbe3SChaitanya Kulkarni else 409a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 410a7a7cbe3SChaitanya Kulkarni 411a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 412a7a7cbe3SChaitanya Kulkarni } 413a7a7cbe3SChaitanya Kulkarni 414a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 415a7a7cbe3SChaitanya Kulkarni { 416a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 417a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 418a7a7cbe3SChaitanya Kulkarni use_sgl); 419a7a7cbe3SChaitanya Kulkarni 420a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42157dacad5SJay Sternberg } 42257dacad5SJay Sternberg 42357dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 42457dacad5SJay Sternberg unsigned int hctx_idx) 42557dacad5SJay Sternberg { 42657dacad5SJay Sternberg struct nvme_dev *dev = data; 427147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 42857dacad5SJay Sternberg 42957dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 43057dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43157dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43257dacad5SJay Sternberg 43357dacad5SJay Sternberg hctx->driver_data = nvmeq; 43457dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 43557dacad5SJay Sternberg return 0; 43657dacad5SJay Sternberg } 43757dacad5SJay Sternberg 43857dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 43957dacad5SJay Sternberg { 44057dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44157dacad5SJay Sternberg 44257dacad5SJay Sternberg nvmeq->tags = NULL; 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 44557dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 44657dacad5SJay Sternberg unsigned int hctx_idx) 44757dacad5SJay Sternberg { 44857dacad5SJay Sternberg struct nvme_dev *dev = data; 449147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 45057dacad5SJay Sternberg 45157dacad5SJay Sternberg if (!nvmeq->tags) 45257dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 45357dacad5SJay Sternberg 45457dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 45557dacad5SJay Sternberg hctx->driver_data = nvmeq; 45657dacad5SJay Sternberg return 0; 45757dacad5SJay Sternberg } 45857dacad5SJay Sternberg 459d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 460d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46157dacad5SJay Sternberg { 462d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 463f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4640350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 465147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 46657dacad5SJay Sternberg 46757dacad5SJay Sternberg BUG_ON(!nvmeq); 468f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 46959e29ce6SSagi Grimberg 47059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47157dacad5SJay Sternberg return 0; 47257dacad5SJay Sternberg } 47357dacad5SJay Sternberg 4743b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4753b6592f7SJens Axboe { 4763b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4773b6592f7SJens Axboe if (dev->num_vecs > 1) 4783b6592f7SJens Axboe return 1; 4793b6592f7SJens Axboe 4803b6592f7SJens Axboe return 0; 4813b6592f7SJens Axboe } 4823b6592f7SJens Axboe 483dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 484dca51e78SChristoph Hellwig { 485dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4863b6592f7SJens Axboe int i, qoff, offset; 487dca51e78SChristoph Hellwig 4883b6592f7SJens Axboe offset = queue_irq_offset(dev); 4893b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4903b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4913b6592f7SJens Axboe 4923b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4933b6592f7SJens Axboe if (!map->nr_queues) { 494e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4957e849dd9SChristoph Hellwig continue; 4963b6592f7SJens Axboe } 4973b6592f7SJens Axboe 4984b04cc6aSJens Axboe /* 4994b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 5004b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5014b04cc6aSJens Axboe */ 5023b6592f7SJens Axboe map->queue_offset = qoff; 503e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 5043b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5054b04cc6aSJens Axboe else 5064b04cc6aSJens Axboe blk_mq_map_queues(map); 5073b6592f7SJens Axboe qoff += map->nr_queues; 5083b6592f7SJens Axboe offset += map->nr_queues; 5093b6592f7SJens Axboe } 5103b6592f7SJens Axboe 5113b6592f7SJens Axboe return 0; 512dca51e78SChristoph Hellwig } 513dca51e78SChristoph Hellwig 51404f3eafdSJens Axboe /* 51504f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 51604f3eafdSJens Axboe */ 51704f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 51804f3eafdSJens Axboe { 51904f3eafdSJens Axboe if (!write_sq) { 52004f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 52104f3eafdSJens Axboe 52204f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 52304f3eafdSJens Axboe next_tail = 0; 52404f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 52504f3eafdSJens Axboe return; 52604f3eafdSJens Axboe } 52704f3eafdSJens Axboe 52804f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 52904f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 53004f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 53104f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 53204f3eafdSJens Axboe } 53304f3eafdSJens Axboe 53457dacad5SJay Sternberg /** 53590ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 53657dacad5SJay Sternberg * @nvmeq: The queue to use 53757dacad5SJay Sternberg * @cmd: The command to send 53804f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 53957dacad5SJay Sternberg */ 54004f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 54104f3eafdSJens Axboe bool write_sq) 54257dacad5SJay Sternberg { 54390ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 54490ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 54590ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 54690ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 54704f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 54804f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 54904f3eafdSJens Axboe } 55004f3eafdSJens Axboe 55104f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 55204f3eafdSJens Axboe { 55304f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 55404f3eafdSJens Axboe 55504f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 55604f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 55704f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 55890ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 55957dacad5SJay Sternberg } 56057dacad5SJay Sternberg 561a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 56257dacad5SJay Sternberg { 563f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 564a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 56557dacad5SJay Sternberg } 56657dacad5SJay Sternberg 567955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 568955b1b5aSMinwoo Im { 569955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 57020469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 571955b1b5aSMinwoo Im unsigned int avg_seg_size; 572955b1b5aSMinwoo Im 57320469a37SKeith Busch if (nseg == 0) 57420469a37SKeith Busch return false; 57520469a37SKeith Busch 57620469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 577955b1b5aSMinwoo Im 578955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 579955b1b5aSMinwoo Im return false; 580955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 581955b1b5aSMinwoo Im return false; 582955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 583955b1b5aSMinwoo Im return false; 584955b1b5aSMinwoo Im return true; 585955b1b5aSMinwoo Im } 586955b1b5aSMinwoo Im 587fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 58857dacad5SJay Sternberg { 589f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 590f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 591b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 592f4800d6dSChristoph Hellwig 593955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 594955b1b5aSMinwoo Im 595f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 596943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 597f4800d6dSChristoph Hellwig if (!iod->sg) 598fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 599f4800d6dSChristoph Hellwig } else { 600f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 60157dacad5SJay Sternberg } 60257dacad5SJay Sternberg 603f4800d6dSChristoph Hellwig iod->aborted = 0; 60457dacad5SJay Sternberg iod->npages = -1; 60557dacad5SJay Sternberg iod->nents = 0; 606f4800d6dSChristoph Hellwig iod->length = size; 607f80ec966SKeith Busch 608fc17b653SChristoph Hellwig return BLK_STS_OK; 60957dacad5SJay Sternberg } 61057dacad5SJay Sternberg 611f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 61257dacad5SJay Sternberg { 613f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 614a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 615a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 616a7a7cbe3SChaitanya Kulkarni 61757dacad5SJay Sternberg int i; 61857dacad5SJay Sternberg 61957dacad5SJay Sternberg if (iod->npages == 0) 620a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 621a7a7cbe3SChaitanya Kulkarni dma_addr); 622a7a7cbe3SChaitanya Kulkarni 62357dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 624a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 625a7a7cbe3SChaitanya Kulkarni 626a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 627a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 628a7a7cbe3SChaitanya Kulkarni 629a7a7cbe3SChaitanya Kulkarni next_dma_addr = 630a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 631a7a7cbe3SChaitanya Kulkarni } else { 632a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 633a7a7cbe3SChaitanya Kulkarni 634a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 635a7a7cbe3SChaitanya Kulkarni } 636a7a7cbe3SChaitanya Kulkarni 637a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 638a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 63957dacad5SJay Sternberg } 64057dacad5SJay Sternberg 641f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 642943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 64357dacad5SJay Sternberg } 64457dacad5SJay Sternberg 645d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 646d0877473SKeith Busch { 647d0877473SKeith Busch int i; 648d0877473SKeith Busch struct scatterlist *sg; 649d0877473SKeith Busch 650d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 651d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 652d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 653d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 654d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 655d0877473SKeith Busch sg_dma_len(sg)); 656d0877473SKeith Busch } 657d0877473SKeith Busch } 658d0877473SKeith Busch 659a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 660a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 66157dacad5SJay Sternberg { 662f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 66357dacad5SJay Sternberg struct dma_pool *pool; 664b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 66557dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 66657dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 66757dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6685fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 66957dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 67057dacad5SJay Sternberg __le64 *prp_list; 671a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 67257dacad5SJay Sternberg dma_addr_t prp_dma; 67357dacad5SJay Sternberg int nprps, i; 67457dacad5SJay Sternberg 67557dacad5SJay Sternberg length -= (page_size - offset); 6765228b328SJan H. Schönherr if (length <= 0) { 6775228b328SJan H. Schönherr iod->first_dma = 0; 678a7a7cbe3SChaitanya Kulkarni goto done; 6795228b328SJan H. Schönherr } 68057dacad5SJay Sternberg 68157dacad5SJay Sternberg dma_len -= (page_size - offset); 68257dacad5SJay Sternberg if (dma_len) { 68357dacad5SJay Sternberg dma_addr += (page_size - offset); 68457dacad5SJay Sternberg } else { 68557dacad5SJay Sternberg sg = sg_next(sg); 68657dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 68757dacad5SJay Sternberg dma_len = sg_dma_len(sg); 68857dacad5SJay Sternberg } 68957dacad5SJay Sternberg 69057dacad5SJay Sternberg if (length <= page_size) { 69157dacad5SJay Sternberg iod->first_dma = dma_addr; 692a7a7cbe3SChaitanya Kulkarni goto done; 69357dacad5SJay Sternberg } 69457dacad5SJay Sternberg 69557dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 69657dacad5SJay Sternberg if (nprps <= (256 / 8)) { 69757dacad5SJay Sternberg pool = dev->prp_small_pool; 69857dacad5SJay Sternberg iod->npages = 0; 69957dacad5SJay Sternberg } else { 70057dacad5SJay Sternberg pool = dev->prp_page_pool; 70157dacad5SJay Sternberg iod->npages = 1; 70257dacad5SJay Sternberg } 70357dacad5SJay Sternberg 70469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 70557dacad5SJay Sternberg if (!prp_list) { 70657dacad5SJay Sternberg iod->first_dma = dma_addr; 70757dacad5SJay Sternberg iod->npages = -1; 70886eea289SKeith Busch return BLK_STS_RESOURCE; 70957dacad5SJay Sternberg } 71057dacad5SJay Sternberg list[0] = prp_list; 71157dacad5SJay Sternberg iod->first_dma = prp_dma; 71257dacad5SJay Sternberg i = 0; 71357dacad5SJay Sternberg for (;;) { 71457dacad5SJay Sternberg if (i == page_size >> 3) { 71557dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 71669d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 71757dacad5SJay Sternberg if (!prp_list) 71886eea289SKeith Busch return BLK_STS_RESOURCE; 71957dacad5SJay Sternberg list[iod->npages++] = prp_list; 72057dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 72157dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 72257dacad5SJay Sternberg i = 1; 72357dacad5SJay Sternberg } 72457dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 72557dacad5SJay Sternberg dma_len -= page_size; 72657dacad5SJay Sternberg dma_addr += page_size; 72757dacad5SJay Sternberg length -= page_size; 72857dacad5SJay Sternberg if (length <= 0) 72957dacad5SJay Sternberg break; 73057dacad5SJay Sternberg if (dma_len > 0) 73157dacad5SJay Sternberg continue; 73286eea289SKeith Busch if (unlikely(dma_len < 0)) 73386eea289SKeith Busch goto bad_sgl; 73457dacad5SJay Sternberg sg = sg_next(sg); 73557dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 73657dacad5SJay Sternberg dma_len = sg_dma_len(sg); 73757dacad5SJay Sternberg } 73857dacad5SJay Sternberg 739a7a7cbe3SChaitanya Kulkarni done: 740a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 741a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 742a7a7cbe3SChaitanya Kulkarni 74386eea289SKeith Busch return BLK_STS_OK; 74486eea289SKeith Busch 74586eea289SKeith Busch bad_sgl: 746d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 747d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 748d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 74986eea289SKeith Busch return BLK_STS_IOERR; 75057dacad5SJay Sternberg } 75157dacad5SJay Sternberg 752a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 753a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 754a7a7cbe3SChaitanya Kulkarni { 755a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 756a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 757a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 758a7a7cbe3SChaitanya Kulkarni } 759a7a7cbe3SChaitanya Kulkarni 760a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 761a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 762a7a7cbe3SChaitanya Kulkarni { 763a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 764a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 765a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 766a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 767a7a7cbe3SChaitanya Kulkarni } else { 768a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 769a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 770a7a7cbe3SChaitanya Kulkarni } 771a7a7cbe3SChaitanya Kulkarni } 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 774b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 775a7a7cbe3SChaitanya Kulkarni { 776a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 777a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 778a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 779a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 780a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 781b0f2853bSChristoph Hellwig int i = 0; 782a7a7cbe3SChaitanya Kulkarni 783a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 784a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 785a7a7cbe3SChaitanya Kulkarni 786b0f2853bSChristoph Hellwig if (entries == 1) { 787a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 788a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 789a7a7cbe3SChaitanya Kulkarni } 790a7a7cbe3SChaitanya Kulkarni 791a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 792a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 793a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 794a7a7cbe3SChaitanya Kulkarni } else { 795a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 796a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 797a7a7cbe3SChaitanya Kulkarni } 798a7a7cbe3SChaitanya Kulkarni 799a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 800a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 801a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 802a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 803a7a7cbe3SChaitanya Kulkarni } 804a7a7cbe3SChaitanya Kulkarni 805a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 806a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 807a7a7cbe3SChaitanya Kulkarni 808a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 809a7a7cbe3SChaitanya Kulkarni 810a7a7cbe3SChaitanya Kulkarni do { 811a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 812a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 813a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 814a7a7cbe3SChaitanya Kulkarni 815a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 816a7a7cbe3SChaitanya Kulkarni if (!sg_list) 817a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 818a7a7cbe3SChaitanya Kulkarni 819a7a7cbe3SChaitanya Kulkarni i = 0; 820a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 821a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 822a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 823a7a7cbe3SChaitanya Kulkarni } 824a7a7cbe3SChaitanya Kulkarni 825a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 826a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 827b0f2853bSChristoph Hellwig } while (--entries > 0); 828a7a7cbe3SChaitanya Kulkarni 829a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 830a7a7cbe3SChaitanya Kulkarni } 831a7a7cbe3SChaitanya Kulkarni 832fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 833b131c61dSChristoph Hellwig struct nvme_command *cmnd) 83457dacad5SJay Sternberg { 835f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 836ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 837ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 838ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 839fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 840b0f2853bSChristoph Hellwig int nr_mapped; 84157dacad5SJay Sternberg 842f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 843ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 844ba1ca37eSChristoph Hellwig if (!iod->nents) 845ba1ca37eSChristoph Hellwig goto out; 846ba1ca37eSChristoph Hellwig 847fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 848e0596ab2SLogan Gunthorpe 849e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 850e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 851e0596ab2SLogan Gunthorpe dma_dir); 852e0596ab2SLogan Gunthorpe else 853e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 854e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 855b0f2853bSChristoph Hellwig if (!nr_mapped) 856ba1ca37eSChristoph Hellwig goto out; 857ba1ca37eSChristoph Hellwig 858955b1b5aSMinwoo Im if (iod->use_sgl) 859b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 860a7a7cbe3SChaitanya Kulkarni else 861a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 862a7a7cbe3SChaitanya Kulkarni 86386eea289SKeith Busch if (ret != BLK_STS_OK) 864ba1ca37eSChristoph Hellwig goto out_unmap; 865ba1ca37eSChristoph Hellwig 866fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 867ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 868ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 869ba1ca37eSChristoph Hellwig goto out_unmap; 870ba1ca37eSChristoph Hellwig 871bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 872bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 873ba1ca37eSChristoph Hellwig goto out_unmap; 874ba1ca37eSChristoph Hellwig 875bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 876ba1ca37eSChristoph Hellwig goto out_unmap; 8773045c0d0SChaitanya Kulkarni 8783045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 87957dacad5SJay Sternberg } 88057dacad5SJay Sternberg 881fc17b653SChristoph Hellwig return BLK_STS_OK; 882ba1ca37eSChristoph Hellwig 883ba1ca37eSChristoph Hellwig out_unmap: 884ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 885ba1ca37eSChristoph Hellwig out: 886ba1ca37eSChristoph Hellwig return ret; 88757dacad5SJay Sternberg } 88857dacad5SJay Sternberg 889f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 890d4f6c3abSChristoph Hellwig { 891f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 892d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 893d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 894d4f6c3abSChristoph Hellwig 895d4f6c3abSChristoph Hellwig if (iod->nents) { 896e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 897e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 898d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 899e0596ab2SLogan Gunthorpe 900f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 901bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 902d4f6c3abSChristoph Hellwig } 903d4f6c3abSChristoph Hellwig 904f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 905f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 90657dacad5SJay Sternberg } 90757dacad5SJay Sternberg 90857dacad5SJay Sternberg /* 90957dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91057dacad5SJay Sternberg */ 911fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91257dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91357dacad5SJay Sternberg { 91457dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 91657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 91757dacad5SJay Sternberg struct request *req = bd->rq; 918ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 919ebe6d874SChristoph Hellwig blk_status_t ret; 92057dacad5SJay Sternberg 921d1f06f4aSJens Axboe /* 922d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 923d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 924d1f06f4aSJens Axboe */ 9254e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 926d1f06f4aSJens Axboe return BLK_STS_IOERR; 927d1f06f4aSJens Axboe 928f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 929fc17b653SChristoph Hellwig if (ret) 930f4800d6dSChristoph Hellwig return ret; 93157dacad5SJay Sternberg 932b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 933fc17b653SChristoph Hellwig if (ret) 934f9d03f96SChristoph Hellwig goto out_free_cmd; 93557dacad5SJay Sternberg 936fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 937b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 938fc17b653SChristoph Hellwig if (ret) 939f9d03f96SChristoph Hellwig goto out_cleanup_iod; 940fc17b653SChristoph Hellwig } 941ba1ca37eSChristoph Hellwig 942aae239e1SChristoph Hellwig blk_mq_start_request(req); 94304f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 944fc17b653SChristoph Hellwig return BLK_STS_OK; 945f9d03f96SChristoph Hellwig out_cleanup_iod: 946f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 947f9d03f96SChristoph Hellwig out_free_cmd: 948f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 949ba1ca37eSChristoph Hellwig return ret; 95057dacad5SJay Sternberg } 95157dacad5SJay Sternberg 95277f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 953eee417b0SChristoph Hellwig { 954f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 955eee417b0SChristoph Hellwig 95677f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 95777f02a7aSChristoph Hellwig nvme_complete_rq(req); 95857dacad5SJay Sternberg } 95957dacad5SJay Sternberg 960d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 961750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 962d783e0bdSMarta Rybczynska { 963750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 964750dde44SChristoph Hellwig nvmeq->cq_phase; 965d783e0bdSMarta Rybczynska } 966d783e0bdSMarta Rybczynska 967eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 96857dacad5SJay Sternberg { 969eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 97057dacad5SJay Sternberg 971eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 972eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 973eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 974eb281c82SSagi Grimberg } 975adf68f21SChristoph Hellwig 9765cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 97757dacad5SJay Sternberg { 9785cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 97957dacad5SJay Sternberg struct request *req; 980adf68f21SChristoph Hellwig 98183a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9821b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 983aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 98483a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 98583a12fb7SSagi Grimberg return; 986aae239e1SChristoph Hellwig } 987aae239e1SChristoph Hellwig 988adf68f21SChristoph Hellwig /* 989adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 990adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 991adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 992adf68f21SChristoph Hellwig * for them but rather special case them here. 993adf68f21SChristoph Hellwig */ 994adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 99538dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 9967bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 99783a12fb7SSagi Grimberg cqe->status, &cqe->result); 998a0fa9647SJens Axboe return; 99957dacad5SJay Sternberg } 100057dacad5SJay Sternberg 100183a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 1002604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 100383a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 100483a12fb7SSagi Grimberg } 100557dacad5SJay Sternberg 10065cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 100783a12fb7SSagi Grimberg { 10085cb525c8SJens Axboe while (start != end) { 10095cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10105cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10115cb525c8SJens Axboe start = 0; 10125cb525c8SJens Axboe } 10135cb525c8SJens Axboe } 101483a12fb7SSagi Grimberg 10155cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10165cb525c8SJens Axboe { 1017dcca1662SHongbo Yao if (nvmeq->cq_head == nvmeq->q_depth - 1) { 1018920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1019920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1020dcca1662SHongbo Yao } else { 1021dcca1662SHongbo Yao nvmeq->cq_head++; 1022920d13a8SSagi Grimberg } 1023a0fa9647SJens Axboe } 1024a0fa9647SJens Axboe 10251052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10261052b8acSJens Axboe u16 *end, unsigned int tag) 1027a0fa9647SJens Axboe { 10281052b8acSJens Axboe int found = 0; 102983a12fb7SSagi Grimberg 10305cb525c8SJens Axboe *start = nvmeq->cq_head; 10311052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10321052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10331052b8acSJens Axboe found++; 10345cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 103557dacad5SJay Sternberg } 10365cb525c8SJens Axboe *end = nvmeq->cq_head; 103757dacad5SJay Sternberg 10385cb525c8SJens Axboe if (*start != *end) 1039eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10405cb525c8SJens Axboe return found; 104157dacad5SJay Sternberg } 104257dacad5SJay Sternberg 104357dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 104457dacad5SJay Sternberg { 104557dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 104668fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10475cb525c8SJens Axboe u16 start, end; 10485cb525c8SJens Axboe 10493a7afd8eSChristoph Hellwig /* 10503a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10513a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10523a7afd8eSChristoph Hellwig */ 10533a7afd8eSChristoph Hellwig rmb(); 105468fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 105568fa9dbeSJens Axboe ret = IRQ_HANDLED; 10565cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 105768fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10583a7afd8eSChristoph Hellwig wmb(); 10595cb525c8SJens Axboe 106068fa9dbeSJens Axboe if (start != end) { 10615cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10625cb525c8SJens Axboe return IRQ_HANDLED; 106357dacad5SJay Sternberg } 106457dacad5SJay Sternberg 106568fa9dbeSJens Axboe return ret; 106657dacad5SJay Sternberg } 106757dacad5SJay Sternberg 106857dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 106957dacad5SJay Sternberg { 107057dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1071750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107257dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1073d783e0bdSMarta Rybczynska return IRQ_NONE; 107457dacad5SJay Sternberg } 107557dacad5SJay Sternberg 10760b2a8a9fSChristoph Hellwig /* 10770b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10780b2a8a9fSChristoph Hellwig * Can be called from any context. 10790b2a8a9fSChristoph Hellwig */ 10800b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1081a0fa9647SJens Axboe { 10823a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10835cb525c8SJens Axboe u16 start, end; 10841052b8acSJens Axboe int found; 1085a0fa9647SJens Axboe 10863a7afd8eSChristoph Hellwig /* 10873a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10883a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10893a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10903a7afd8eSChristoph Hellwig */ 10917c349ddeSKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) { 10923a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 109391a509f8SChristoph Hellwig found = nvme_process_cq(nvmeq, &start, &end, tag); 109491a509f8SChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 109591a509f8SChristoph Hellwig } else { 10963a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10975cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10983a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 109991a509f8SChristoph Hellwig } 1100442e19b7SSagi Grimberg 11015cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1102442e19b7SSagi Grimberg return found; 1103a0fa9647SJens Axboe } 1104a0fa9647SJens Axboe 11059743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 11067776db1cSKeith Busch { 11077776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1108dabcefabSJens Axboe u16 start, end; 1109dabcefabSJens Axboe bool found; 1110dabcefabSJens Axboe 1111dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1112dabcefabSJens Axboe return 0; 1113dabcefabSJens Axboe 11143a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11159743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11163a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1117dabcefabSJens Axboe 1118dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1119dabcefabSJens Axboe return found; 1120dabcefabSJens Axboe } 1121dabcefabSJens Axboe 1122ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 112357dacad5SJay Sternberg { 1124f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1125147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 112657dacad5SJay Sternberg struct nvme_command c; 112757dacad5SJay Sternberg 112857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 112957dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1130ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 113104f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 113257dacad5SJay Sternberg } 113357dacad5SJay Sternberg 113457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 113557dacad5SJay Sternberg { 113657dacad5SJay Sternberg struct nvme_command c; 113757dacad5SJay Sternberg 113857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113957dacad5SJay Sternberg c.delete_queue.opcode = opcode; 114057dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 114157dacad5SJay Sternberg 11421c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 114357dacad5SJay Sternberg } 114457dacad5SJay Sternberg 114557dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1146a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 114757dacad5SJay Sternberg { 114857dacad5SJay Sternberg struct nvme_command c; 11494b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11504b04cc6aSJens Axboe 11517c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11524b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 115357dacad5SJay Sternberg 115457dacad5SJay Sternberg /* 115516772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 115657dacad5SJay Sternberg * is attached to the request. 115757dacad5SJay Sternberg */ 115857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 115957dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 116057dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 116157dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 116257dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 116357dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1164a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 116557dacad5SJay Sternberg 11661c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 116757dacad5SJay Sternberg } 116857dacad5SJay Sternberg 116957dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 117057dacad5SJay Sternberg struct nvme_queue *nvmeq) 117157dacad5SJay Sternberg { 11729abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 117357dacad5SJay Sternberg struct nvme_command c; 117481c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 117557dacad5SJay Sternberg 117657dacad5SJay Sternberg /* 11779abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11789abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11799abd68efSJens Axboe * URGENT. 11809abd68efSJens Axboe */ 11819abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11829abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11839abd68efSJens Axboe 11849abd68efSJens Axboe /* 118516772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 118657dacad5SJay Sternberg * is attached to the request. 118757dacad5SJay Sternberg */ 118857dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 118957dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 119057dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 119157dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 119257dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 119357dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 119457dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 119557dacad5SJay Sternberg 11961c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 119757dacad5SJay Sternberg } 119857dacad5SJay Sternberg 119957dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 120057dacad5SJay Sternberg { 120157dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 120257dacad5SJay Sternberg } 120357dacad5SJay Sternberg 120457dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 120557dacad5SJay Sternberg { 120657dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 120757dacad5SJay Sternberg } 120857dacad5SJay Sternberg 12092a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 121057dacad5SJay Sternberg { 1211f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1212f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 121357dacad5SJay Sternberg 121427fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 121527fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1216e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1217e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 121857dacad5SJay Sternberg } 121957dacad5SJay Sternberg 1220b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1221b2a0eb1aSKeith Busch { 1222b2a0eb1aSKeith Busch 1223b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1224b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1225b2a0eb1aSKeith Busch */ 1226b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1227b2a0eb1aSKeith Busch 1228ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1229ad70062cSJianchao Wang switch (dev->ctrl.state) { 1230ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1231ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1232b2a0eb1aSKeith Busch return false; 1233ad70062cSJianchao Wang default: 1234ad70062cSJianchao Wang break; 1235ad70062cSJianchao Wang } 1236b2a0eb1aSKeith Busch 1237b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1238b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1239b2a0eb1aSKeith Busch */ 1240b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1241b2a0eb1aSKeith Busch return false; 1242b2a0eb1aSKeith Busch 1243b2a0eb1aSKeith Busch return true; 1244b2a0eb1aSKeith Busch } 1245b2a0eb1aSKeith Busch 1246b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1247b2a0eb1aSKeith Busch { 1248b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1249b2a0eb1aSKeith Busch u16 pci_status; 1250b2a0eb1aSKeith Busch int result; 1251b2a0eb1aSKeith Busch 1252b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1253b2a0eb1aSKeith Busch &pci_status); 1254b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1255b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1256b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1257b2a0eb1aSKeith Busch csts, pci_status); 1258b2a0eb1aSKeith Busch else 1259b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1260b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1261b2a0eb1aSKeith Busch csts, result); 1262b2a0eb1aSKeith Busch } 1263b2a0eb1aSKeith Busch 126431c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 126557dacad5SJay Sternberg { 1266f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1267f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 126857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 126957dacad5SJay Sternberg struct request *abort_req; 127057dacad5SJay Sternberg struct nvme_command cmd; 1271b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1272b2a0eb1aSKeith Busch 1273651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1274651438bbSWen Xiong * the recovery mechanism will surely fail. 1275651438bbSWen Xiong */ 1276651438bbSWen Xiong mb(); 1277651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1278651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1279651438bbSWen Xiong 1280b2a0eb1aSKeith Busch /* 1281b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1282b2a0eb1aSKeith Busch */ 1283b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1284b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1285b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1286d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1287db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1288b2a0eb1aSKeith Busch } 128957dacad5SJay Sternberg 129031c7c7d2SChristoph Hellwig /* 12917776db1cSKeith Busch * Did we miss an interrupt? 12927776db1cSKeith Busch */ 12930b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12947776db1cSKeith Busch dev_warn(dev->ctrl.device, 12957776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 12967776db1cSKeith Busch req->tag, nvmeq->qid); 1297db8c48e4SChristoph Hellwig return BLK_EH_DONE; 12987776db1cSKeith Busch } 12997776db1cSKeith Busch 13007776db1cSKeith Busch /* 1301fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1302fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1303fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1304db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1305fd634f41SChristoph Hellwig */ 13064244140dSKeith Busch switch (dev->ctrl.state) { 13074244140dSKeith Busch case NVME_CTRL_CONNECTING: 13084244140dSKeith Busch case NVME_CTRL_RESETTING: 1309b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1310fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1311fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1312a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 131327fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1314db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13154244140dSKeith Busch default: 13164244140dSKeith Busch break; 1317fd634f41SChristoph Hellwig } 1318fd634f41SChristoph Hellwig 1319fd634f41SChristoph Hellwig /* 1320e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1321e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1322e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 132331c7c7d2SChristoph Hellwig */ 1324f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13251b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 132657dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 132757dacad5SJay Sternberg req->tag, nvmeq->qid); 1328a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1329d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1330e1569a16SKeith Busch 133127fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1332db8c48e4SChristoph Hellwig return BLK_EH_DONE; 133357dacad5SJay Sternberg } 133457dacad5SJay Sternberg 1335e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1336e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1337e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1338e7a2a87dSChristoph Hellwig } 13397bf7d778SKeith Busch iod->aborted = 1; 134057dacad5SJay Sternberg 134157dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 134257dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 134357dacad5SJay Sternberg cmd.abort.cid = req->tag; 134457dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 134557dacad5SJay Sternberg 13461b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13471b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 134857dacad5SJay Sternberg req->tag, nvmeq->qid); 1349e7a2a87dSChristoph Hellwig 1350e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1351eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13526bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13536bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 135431c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 135557dacad5SJay Sternberg } 135657dacad5SJay Sternberg 1357e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1358e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1359e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 136057dacad5SJay Sternberg 136157dacad5SJay Sternberg /* 136257dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 136357dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 136457dacad5SJay Sternberg * as the device then is in a faulty state. 136557dacad5SJay Sternberg */ 136657dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 136757dacad5SJay Sternberg } 136857dacad5SJay Sternberg 136957dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 137057dacad5SJay Sternberg { 137188a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq->q_depth), 137257dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 137363223078SChristoph Hellwig if (!nvmeq->sq_cmds) 137463223078SChristoph Hellwig return; 13750f238ff5SLogan Gunthorpe 137663223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 137788a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 137863223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 137963223078SChristoph Hellwig } else { 138088a041f4SKeith Busch dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq->q_depth), 138163223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13820f238ff5SLogan Gunthorpe } 138357dacad5SJay Sternberg } 138457dacad5SJay Sternberg 138557dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 138657dacad5SJay Sternberg { 138757dacad5SJay Sternberg int i; 138857dacad5SJay Sternberg 1389d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1390d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1391147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 139257dacad5SJay Sternberg } 139357dacad5SJay Sternberg } 139457dacad5SJay Sternberg 139557dacad5SJay Sternberg /** 139657dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 139740581d1aSBart Van Assche * @nvmeq: queue to suspend 139857dacad5SJay Sternberg */ 139957dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 140057dacad5SJay Sternberg { 14014e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 140257dacad5SJay Sternberg return 1; 140357dacad5SJay Sternberg 14044e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1405d1f06f4aSJens Axboe mb(); 140657dacad5SJay Sternberg 14074e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14081c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1409c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14107c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14114e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 141257dacad5SJay Sternberg return 0; 141357dacad5SJay Sternberg } 141457dacad5SJay Sternberg 14158fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14168fae268bSKeith Busch { 14178fae268bSKeith Busch int i; 14188fae268bSKeith Busch 14198fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 14208fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 14218fae268bSKeith Busch } 14228fae268bSKeith Busch 1423a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 142457dacad5SJay Sternberg { 1425147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 142657dacad5SJay Sternberg 1427a5cdb68cSKeith Busch if (shutdown) 1428a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1429a5cdb68cSKeith Busch else 143020d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 143157dacad5SJay Sternberg 14320b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 143357dacad5SJay Sternberg } 143457dacad5SJay Sternberg 143557dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 143657dacad5SJay Sternberg int entry_size) 143757dacad5SJay Sternberg { 143857dacad5SJay Sternberg int q_depth = dev->q_depth; 14395fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14405fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 144157dacad5SJay Sternberg 144257dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 144357dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14445fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 144557dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 144657dacad5SJay Sternberg 144757dacad5SJay Sternberg /* 144857dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 144957dacad5SJay Sternberg * would be better to map queues in system memory with the 145057dacad5SJay Sternberg * original depth 145157dacad5SJay Sternberg */ 145257dacad5SJay Sternberg if (q_depth < 64) 145357dacad5SJay Sternberg return -ENOMEM; 145457dacad5SJay Sternberg } 145557dacad5SJay Sternberg 145657dacad5SJay Sternberg return q_depth; 145757dacad5SJay Sternberg } 145857dacad5SJay Sternberg 145957dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 146057dacad5SJay Sternberg int qid, int depth) 146157dacad5SJay Sternberg { 14620f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1463815c6704SKeith Busch 14640f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14650f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14660f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14670f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 146863223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 146963223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 147063223078SChristoph Hellwig return 0; 147163223078SChristoph Hellwig } 14720f238ff5SLogan Gunthorpe } 14730f238ff5SLogan Gunthorpe 147457dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 147557dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 147657dacad5SJay Sternberg if (!nvmeq->sq_cmds) 147757dacad5SJay Sternberg return -ENOMEM; 147857dacad5SJay Sternberg return 0; 147957dacad5SJay Sternberg } 148057dacad5SJay Sternberg 1481a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 148257dacad5SJay Sternberg { 1483147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 148457dacad5SJay Sternberg 148562314e40SKeith Busch if (dev->ctrl.queue_count > qid) 148662314e40SKeith Busch return 0; 148757dacad5SJay Sternberg 1488750afb08SLuis Chamberlain nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(depth), 148957dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 149057dacad5SJay Sternberg if (!nvmeq->cqes) 149157dacad5SJay Sternberg goto free_nvmeq; 149257dacad5SJay Sternberg 149357dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 149457dacad5SJay Sternberg goto free_cqdma; 149557dacad5SJay Sternberg 149657dacad5SJay Sternberg nvmeq->dev = dev; 14971ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14983a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 149957dacad5SJay Sternberg nvmeq->cq_head = 0; 150057dacad5SJay Sternberg nvmeq->cq_phase = 1; 150157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 150257dacad5SJay Sternberg nvmeq->q_depth = depth; 150357dacad5SJay Sternberg nvmeq->qid = qid; 1504d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 150557dacad5SJay Sternberg 1506147b27e4SSagi Grimberg return 0; 150757dacad5SJay Sternberg 150857dacad5SJay Sternberg free_cqdma: 150957dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 151057dacad5SJay Sternberg nvmeq->cq_dma_addr); 151157dacad5SJay Sternberg free_nvmeq: 1512147b27e4SSagi Grimberg return -ENOMEM; 151357dacad5SJay Sternberg } 151457dacad5SJay Sternberg 1515dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 151657dacad5SJay Sternberg { 15170ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15180ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15190ff199cbSChristoph Hellwig 15200ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15210ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15220ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15230ff199cbSChristoph Hellwig } else { 15240ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15250ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15260ff199cbSChristoph Hellwig } 152757dacad5SJay Sternberg } 152857dacad5SJay Sternberg 152957dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 153057dacad5SJay Sternberg { 153157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153257dacad5SJay Sternberg 153357dacad5SJay Sternberg nvmeq->sq_tail = 0; 153404f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 153557dacad5SJay Sternberg nvmeq->cq_head = 0; 153657dacad5SJay Sternberg nvmeq->cq_phase = 1; 153757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 153857dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1539f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 154057dacad5SJay Sternberg dev->online_queues++; 15413a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 154257dacad5SJay Sternberg } 154357dacad5SJay Sternberg 15444b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 154557dacad5SJay Sternberg { 154657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154757dacad5SJay Sternberg int result; 15487c349ddeSKeith Busch u16 vector = 0; 154957dacad5SJay Sternberg 1550d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1551d1ed6aa1SChristoph Hellwig 155222b55601SKeith Busch /* 155322b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 155422b55601SKeith Busch * has only one vector available. 155522b55601SKeith Busch */ 15564b04cc6aSJens Axboe if (!polled) 1557a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15584b04cc6aSJens Axboe else 15597c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 15604b04cc6aSJens Axboe 1561a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1562ded45505SKeith Busch if (result) 1563ded45505SKeith Busch return result; 156457dacad5SJay Sternberg 156557dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 156657dacad5SJay Sternberg if (result < 0) 1567ded45505SKeith Busch return result; 1568ded45505SKeith Busch else if (result) 156957dacad5SJay Sternberg goto release_cq; 157057dacad5SJay Sternberg 1571a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1572161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15734b04cc6aSJens Axboe 15747c349ddeSKeith Busch if (!polled) { 15757c349ddeSKeith Busch nvmeq->cq_vector = vector; 1576dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 157757dacad5SJay Sternberg if (result < 0) 157857dacad5SJay Sternberg goto release_sq; 15794b04cc6aSJens Axboe } 158057dacad5SJay Sternberg 15814e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 158257dacad5SJay Sternberg return result; 158357dacad5SJay Sternberg 158457dacad5SJay Sternberg release_sq: 1585f25a2dfcSJianchao Wang dev->online_queues--; 158657dacad5SJay Sternberg adapter_delete_sq(dev, qid); 158757dacad5SJay Sternberg release_cq: 158857dacad5SJay Sternberg adapter_delete_cq(dev, qid); 158957dacad5SJay Sternberg return result; 159057dacad5SJay Sternberg } 159157dacad5SJay Sternberg 1592f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 159357dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 159477f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 159557dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 159657dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15970350815aSChristoph Hellwig .init_request = nvme_init_request, 159857dacad5SJay Sternberg .timeout = nvme_timeout, 159957dacad5SJay Sternberg }; 160057dacad5SJay Sternberg 1601f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1602376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1603376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1604376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1605376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1606376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1607376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1608376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1609c6d962aeSChristoph Hellwig .poll = nvme_poll, 1610dabcefabSJens Axboe }; 1611dabcefabSJens Axboe 161257dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 161357dacad5SJay Sternberg { 16141c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 161569d9a99cSKeith Busch /* 161669d9a99cSKeith Busch * If the controller was reset during removal, it's possible 161769d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 161869d9a99cSKeith Busch * queue to flush these to completion. 161969d9a99cSKeith Busch */ 1620c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16211c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 162257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 162357dacad5SJay Sternberg } 162457dacad5SJay Sternberg } 162557dacad5SJay Sternberg 162657dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 162757dacad5SJay Sternberg { 16281c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 162957dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 163057dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1631e3e9d50cSKeith Busch 163238dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 163357dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 163457dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1635a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1636d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 163757dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 163857dacad5SJay Sternberg 163957dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 164057dacad5SJay Sternberg return -ENOMEM; 164134b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 164257dacad5SJay Sternberg 16431c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16441c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 164557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 164657dacad5SJay Sternberg return -ENOMEM; 164757dacad5SJay Sternberg } 16481c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 164957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16501c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 165157dacad5SJay Sternberg return -ENODEV; 165257dacad5SJay Sternberg } 165357dacad5SJay Sternberg } else 1654c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 165557dacad5SJay Sternberg 165657dacad5SJay Sternberg return 0; 165757dacad5SJay Sternberg } 165857dacad5SJay Sternberg 165997f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 166097f6ef64SXu Yu { 166197f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 166297f6ef64SXu Yu } 166397f6ef64SXu Yu 166497f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 166597f6ef64SXu Yu { 166697f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 166797f6ef64SXu Yu 166897f6ef64SXu Yu if (size <= dev->bar_mapped_size) 166997f6ef64SXu Yu return 0; 167097f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 167197f6ef64SXu Yu return -ENOMEM; 167297f6ef64SXu Yu if (dev->bar) 167397f6ef64SXu Yu iounmap(dev->bar); 167497f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 167597f6ef64SXu Yu if (!dev->bar) { 167697f6ef64SXu Yu dev->bar_mapped_size = 0; 167797f6ef64SXu Yu return -ENOMEM; 167897f6ef64SXu Yu } 167997f6ef64SXu Yu dev->bar_mapped_size = size; 168097f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 168197f6ef64SXu Yu 168297f6ef64SXu Yu return 0; 168397f6ef64SXu Yu } 168497f6ef64SXu Yu 168501ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 168657dacad5SJay Sternberg { 168757dacad5SJay Sternberg int result; 168857dacad5SJay Sternberg u32 aqa; 168957dacad5SJay Sternberg struct nvme_queue *nvmeq; 169057dacad5SJay Sternberg 169197f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 169297f6ef64SXu Yu if (result < 0) 169397f6ef64SXu Yu return result; 169497f6ef64SXu Yu 16958ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 169620d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 169757dacad5SJay Sternberg 16987a67cbeaSChristoph Hellwig if (dev->subsystem && 16997a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17007a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 170157dacad5SJay Sternberg 170220d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 170357dacad5SJay Sternberg if (result < 0) 170457dacad5SJay Sternberg return result; 170557dacad5SJay Sternberg 1706a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1707147b27e4SSagi Grimberg if (result) 1708147b27e4SSagi Grimberg return result; 170957dacad5SJay Sternberg 1710147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 171157dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 171257dacad5SJay Sternberg aqa |= aqa << 16; 171357dacad5SJay Sternberg 17147a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17157a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17167a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 171757dacad5SJay Sternberg 171820d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 171957dacad5SJay Sternberg if (result) 1720d4875622SKeith Busch return result; 172157dacad5SJay Sternberg 172257dacad5SJay Sternberg nvmeq->cq_vector = 0; 1723161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1724dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 172557dacad5SJay Sternberg if (result) { 17267c349ddeSKeith Busch dev->online_queues--; 1727d4875622SKeith Busch return result; 172857dacad5SJay Sternberg } 172957dacad5SJay Sternberg 17304e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 173157dacad5SJay Sternberg return result; 173257dacad5SJay Sternberg } 173357dacad5SJay Sternberg 1734749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 173557dacad5SJay Sternberg { 17364b04cc6aSJens Axboe unsigned i, max, rw_queues; 1737749941f2SChristoph Hellwig int ret = 0; 173857dacad5SJay Sternberg 1739d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1740a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1741749941f2SChristoph Hellwig ret = -ENOMEM; 174257dacad5SJay Sternberg break; 1743749941f2SChristoph Hellwig } 1744749941f2SChristoph Hellwig } 174557dacad5SJay Sternberg 1746d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1747e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1748e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1749e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17504b04cc6aSJens Axboe } else { 17514b04cc6aSJens Axboe rw_queues = max; 17524b04cc6aSJens Axboe } 17534b04cc6aSJens Axboe 1754949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17554b04cc6aSJens Axboe bool polled = i > rw_queues; 17564b04cc6aSJens Axboe 17574b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1758d4875622SKeith Busch if (ret) 175957dacad5SJay Sternberg break; 176057dacad5SJay Sternberg } 176157dacad5SJay Sternberg 1762749941f2SChristoph Hellwig /* 1763749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17648adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17658adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1766749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1767749941f2SChristoph Hellwig */ 1768749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 176957dacad5SJay Sternberg } 177057dacad5SJay Sternberg 1771202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1772202021c1SStephen Bates struct device_attribute *attr, 1773202021c1SStephen Bates char *buf) 1774202021c1SStephen Bates { 1775202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1776202021c1SStephen Bates 1777c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1778202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1779202021c1SStephen Bates } 1780202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1781202021c1SStephen Bates 178288de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 178357dacad5SJay Sternberg { 178488de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 178588de4598SChristoph Hellwig 178688de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 178788de4598SChristoph Hellwig } 178888de4598SChristoph Hellwig 178988de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 179088de4598SChristoph Hellwig { 179188de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 179288de4598SChristoph Hellwig } 179388de4598SChristoph Hellwig 1794f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 179557dacad5SJay Sternberg { 179688de4598SChristoph Hellwig u64 size, offset; 179757dacad5SJay Sternberg resource_size_t bar_size; 179857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17998969f1f8SChristoph Hellwig int bar; 180057dacad5SJay Sternberg 18019fe5c59fSKeith Busch if (dev->cmb_size) 18029fe5c59fSKeith Busch return; 18039fe5c59fSKeith Busch 18047a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1805f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1806f65efd6dSChristoph Hellwig return; 1807202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 180857dacad5SJay Sternberg 180988de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 181088de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18118969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18128969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 181357dacad5SJay Sternberg 181457dacad5SJay Sternberg if (offset > bar_size) 1815f65efd6dSChristoph Hellwig return; 181657dacad5SJay Sternberg 181757dacad5SJay Sternberg /* 181857dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 181957dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 182057dacad5SJay Sternberg * the reported size of the BAR 182157dacad5SJay Sternberg */ 182257dacad5SJay Sternberg if (size > bar_size - offset) 182357dacad5SJay Sternberg size = bar_size - offset; 182457dacad5SJay Sternberg 18250f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18260f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18270f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1828f65efd6dSChristoph Hellwig return; 18290f238ff5SLogan Gunthorpe } 18300f238ff5SLogan Gunthorpe 183157dacad5SJay Sternberg dev->cmb_size = size; 18320f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18330f238ff5SLogan Gunthorpe 18340f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18350f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18360f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1837f65efd6dSChristoph Hellwig 1838f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1839f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1840f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1841f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 184257dacad5SJay Sternberg } 184357dacad5SJay Sternberg 184457dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 184557dacad5SJay Sternberg { 18460f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1847f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1848f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18490f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1850f63572dfSJon Derrick } 185157dacad5SJay Sternberg } 185257dacad5SJay Sternberg 185387ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 185457dacad5SJay Sternberg { 18554033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 185687ad72a5SChristoph Hellwig struct nvme_command c; 185787ad72a5SChristoph Hellwig int ret; 185887ad72a5SChristoph Hellwig 185987ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 186087ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 186187ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 186287ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 186387ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 186487ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 186587ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 186687ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 186787ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 186887ad72a5SChristoph Hellwig 186987ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 187087ad72a5SChristoph Hellwig if (ret) { 187187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 187287ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 187387ad72a5SChristoph Hellwig ret, bits); 187487ad72a5SChristoph Hellwig } 187587ad72a5SChristoph Hellwig return ret; 187687ad72a5SChristoph Hellwig } 187787ad72a5SChristoph Hellwig 187887ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 187987ad72a5SChristoph Hellwig { 188087ad72a5SChristoph Hellwig int i; 188187ad72a5SChristoph Hellwig 188287ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 188387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 188487ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 188587ad72a5SChristoph Hellwig 1886cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1887cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1888cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 188987ad72a5SChristoph Hellwig } 189087ad72a5SChristoph Hellwig 189187ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 189287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18934033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18944033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18954033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 189687ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18977e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 189887ad72a5SChristoph Hellwig } 189987ad72a5SChristoph Hellwig 190092dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 190192dc6895SChristoph Hellwig u32 chunk_size) 190287ad72a5SChristoph Hellwig { 190387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 190492dc6895SChristoph Hellwig u32 max_entries, len; 19054033f35dSChristoph Hellwig dma_addr_t descs_dma; 19062ee0e4edSDan Carpenter int i = 0; 190787ad72a5SChristoph Hellwig void **bufs; 19086fbcde66SMinwoo Im u64 size, tmp; 190987ad72a5SChristoph Hellwig 191087ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 191187ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 191287ad72a5SChristoph Hellwig max_entries = tmp; 1913044a9df1SChristoph Hellwig 1914044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1915044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1916044a9df1SChristoph Hellwig 1917750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19184033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 191987ad72a5SChristoph Hellwig if (!descs) 192087ad72a5SChristoph Hellwig goto out; 192187ad72a5SChristoph Hellwig 192287ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 192387ad72a5SChristoph Hellwig if (!bufs) 192487ad72a5SChristoph Hellwig goto out_free_descs; 192587ad72a5SChristoph Hellwig 1926244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 192787ad72a5SChristoph Hellwig dma_addr_t dma_addr; 192887ad72a5SChristoph Hellwig 192950cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 193087ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 193187ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 193287ad72a5SChristoph Hellwig if (!bufs[i]) 193387ad72a5SChristoph Hellwig break; 193487ad72a5SChristoph Hellwig 193587ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 193687ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 193787ad72a5SChristoph Hellwig i++; 193887ad72a5SChristoph Hellwig } 193987ad72a5SChristoph Hellwig 194092dc6895SChristoph Hellwig if (!size) 194187ad72a5SChristoph Hellwig goto out_free_bufs; 194287ad72a5SChristoph Hellwig 194387ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 194487ad72a5SChristoph Hellwig dev->host_mem_size = size; 194587ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19464033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 194787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 194887ad72a5SChristoph Hellwig return 0; 194987ad72a5SChristoph Hellwig 195087ad72a5SChristoph Hellwig out_free_bufs: 195187ad72a5SChristoph Hellwig while (--i >= 0) { 195287ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 195387ad72a5SChristoph Hellwig 1954cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1955cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1956cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 195787ad72a5SChristoph Hellwig } 195887ad72a5SChristoph Hellwig 195987ad72a5SChristoph Hellwig kfree(bufs); 196087ad72a5SChristoph Hellwig out_free_descs: 19614033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19624033f35dSChristoph Hellwig descs_dma); 196387ad72a5SChristoph Hellwig out: 196487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 196587ad72a5SChristoph Hellwig return -ENOMEM; 196687ad72a5SChristoph Hellwig } 196787ad72a5SChristoph Hellwig 196892dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 196992dc6895SChristoph Hellwig { 197092dc6895SChristoph Hellwig u32 chunk_size; 197192dc6895SChristoph Hellwig 197292dc6895SChristoph Hellwig /* start big and work our way down */ 197330f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1974044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 197592dc6895SChristoph Hellwig chunk_size /= 2) { 197692dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197792dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 197892dc6895SChristoph Hellwig return 0; 197992dc6895SChristoph Hellwig nvme_free_host_mem(dev); 198092dc6895SChristoph Hellwig } 198192dc6895SChristoph Hellwig } 198292dc6895SChristoph Hellwig 198392dc6895SChristoph Hellwig return -ENOMEM; 198492dc6895SChristoph Hellwig } 198592dc6895SChristoph Hellwig 19869620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198787ad72a5SChristoph Hellwig { 198887ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 198987ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 199087ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 199187ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19926fbcde66SMinwoo Im int ret; 199387ad72a5SChristoph Hellwig 199487ad72a5SChristoph Hellwig preferred = min(preferred, max); 199587ad72a5SChristoph Hellwig if (min > max) { 199687ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199787ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 199887ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 199987ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20009620cfbaSChristoph Hellwig return 0; 200187ad72a5SChristoph Hellwig } 200287ad72a5SChristoph Hellwig 200387ad72a5SChristoph Hellwig /* 200487ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 200587ad72a5SChristoph Hellwig */ 200687ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200787ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 200887ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 200987ad72a5SChristoph Hellwig else 201087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 201187ad72a5SChristoph Hellwig } 201287ad72a5SChristoph Hellwig 201387ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 201492dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 201592dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 201692dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20179620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 201887ad72a5SChristoph Hellwig } 201987ad72a5SChristoph Hellwig 202092dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 202192dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 202292dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 202392dc6895SChristoph Hellwig } 202492dc6895SChristoph Hellwig 20259620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20269620cfbaSChristoph Hellwig if (ret) 202787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20289620cfbaSChristoph Hellwig return ret; 202957dacad5SJay Sternberg } 203057dacad5SJay Sternberg 2031612b7286SMing Lei /* 2032612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2033612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2034612b7286SMing Lei */ 2035612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 20363b6592f7SJens Axboe { 2037612b7286SMing Lei struct nvme_dev *dev = affd->priv; 2038612b7286SMing Lei unsigned int nr_read_queues; 2039c45b1fa2SMing Lei 20403b6592f7SJens Axboe /* 2041612b7286SMing Lei * If there is no interupt available for queues, ensure that 2042612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2043612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2044612b7286SMing Lei * 2045612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2046612b7286SMing Lei * write and read queues. 2047612b7286SMing Lei * 2048612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2049612b7286SMing Lei * queue. 20503b6592f7SJens Axboe */ 2051612b7286SMing Lei if (!nrirqs) { 2052612b7286SMing Lei nrirqs = 1; 2053612b7286SMing Lei nr_read_queues = 0; 2054612b7286SMing Lei } else if (nrirqs == 1 || !write_queues) { 2055612b7286SMing Lei nr_read_queues = 0; 2056612b7286SMing Lei } else if (write_queues >= nrirqs) { 2057612b7286SMing Lei nr_read_queues = 1; 20583b6592f7SJens Axboe } else { 2059612b7286SMing Lei nr_read_queues = nrirqs - write_queues; 20603b6592f7SJens Axboe } 2061612b7286SMing Lei 2062612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2063612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2064612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2065612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2066612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 20673b6592f7SJens Axboe } 20683b6592f7SJens Axboe 20696451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20703b6592f7SJens Axboe { 20713b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20723b6592f7SJens Axboe struct irq_affinity affd = { 20733b6592f7SJens Axboe .pre_vectors = 1, 2074612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2075612b7286SMing Lei .priv = dev, 20763b6592f7SJens Axboe }; 20776451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20786451fe73SJens Axboe 20796451fe73SJens Axboe /* 20806451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20816451fe73SJens Axboe * queue left over for non-polled IO. 20826451fe73SJens Axboe */ 20836451fe73SJens Axboe this_p_queues = poll_queues; 20846451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20856451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20866451fe73SJens Axboe irq_queues = 1; 20876451fe73SJens Axboe } else { 2088c45b1fa2SMing Lei irq_queues = nr_io_queues - this_p_queues + 1; 20896451fe73SJens Axboe } 20906451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20913b6592f7SJens Axboe 2092612b7286SMing Lei /* Initialize for the single interrupt case */ 2093612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2094612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 20953b6592f7SJens Axboe 2096612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 20973b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 20983b6592f7SJens Axboe } 20993b6592f7SJens Axboe 21008fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 21018fae268bSKeith Busch { 21028fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 21038fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 21048fae268bSKeith Busch } 21058fae268bSKeith Busch 210657dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 210757dacad5SJay Sternberg { 2108147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 210957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 211097f6ef64SXu Yu int result, nr_io_queues; 211197f6ef64SXu Yu unsigned long size; 211257dacad5SJay Sternberg 21133b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21149a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21159a0be7abSChristoph Hellwig if (result < 0) 211657dacad5SJay Sternberg return result; 21179a0be7abSChristoph Hellwig 2118f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2119a5229050SKeith Busch return 0; 212057dacad5SJay Sternberg 21214e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21224e224106SChristoph Hellwig 21230f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 212457dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 212557dacad5SJay Sternberg sizeof(struct nvme_command)); 212657dacad5SJay Sternberg if (result > 0) 212757dacad5SJay Sternberg dev->q_depth = result; 212857dacad5SJay Sternberg else 21290f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 213057dacad5SJay Sternberg } 213157dacad5SJay Sternberg 213257dacad5SJay Sternberg do { 213397f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 213497f6ef64SXu Yu result = nvme_remap_bar(dev, size); 213597f6ef64SXu Yu if (!result) 213657dacad5SJay Sternberg break; 213757dacad5SJay Sternberg if (!--nr_io_queues) 213857dacad5SJay Sternberg return -ENOMEM; 213957dacad5SJay Sternberg } while (1); 214057dacad5SJay Sternberg adminq->q_db = dev->dbs; 214157dacad5SJay Sternberg 21428fae268bSKeith Busch retry: 214357dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21440ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 214557dacad5SJay Sternberg 214657dacad5SJay Sternberg /* 214757dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 214857dacad5SJay Sternberg * setting up the full range we need. 214957dacad5SJay Sternberg */ 2150dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21513b6592f7SJens Axboe 21523b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 215322b55601SKeith Busch if (result <= 0) 2154dca51e78SChristoph Hellwig return -EIO; 21553b6592f7SJens Axboe 215622b55601SKeith Busch dev->num_vecs = result; 21574b04cc6aSJens Axboe result = max(result - 1, 1); 2158e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 215957dacad5SJay Sternberg 216057dacad5SJay Sternberg /* 216157dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 216257dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 216357dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 216457dacad5SJay Sternberg * number of interrupts. 216557dacad5SJay Sternberg */ 2166dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 21677c349ddeSKeith Busch if (result) 2168d4875622SKeith Busch return result; 21694e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 21708fae268bSKeith Busch 21718fae268bSKeith Busch result = nvme_create_io_queues(dev); 21728fae268bSKeith Busch if (result || dev->online_queues < 2) 21738fae268bSKeith Busch return result; 21748fae268bSKeith Busch 21758fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 21768fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 21778fae268bSKeith Busch nvme_disable_io_queues(dev); 21788fae268bSKeith Busch nvme_suspend_io_queues(dev); 21798fae268bSKeith Busch goto retry; 21808fae268bSKeith Busch } 21818fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 21828fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 21838fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 21848fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 21858fae268bSKeith Busch return 0; 218657dacad5SJay Sternberg } 218757dacad5SJay Sternberg 21882a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2189db3cbfffSKeith Busch { 2190db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2191db3cbfffSKeith Busch 2192db3cbfffSKeith Busch blk_mq_free_request(req); 2193d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2194db3cbfffSKeith Busch } 2195db3cbfffSKeith Busch 21962a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2197db3cbfffSKeith Busch { 2198db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2199db3cbfffSKeith Busch 2200d1ed6aa1SChristoph Hellwig if (error) 2201d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2202db3cbfffSKeith Busch 2203db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2204db3cbfffSKeith Busch } 2205db3cbfffSKeith Busch 2206db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2207db3cbfffSKeith Busch { 2208db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2209db3cbfffSKeith Busch struct request *req; 2210db3cbfffSKeith Busch struct nvme_command cmd; 2211db3cbfffSKeith Busch 2212db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2213db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2214db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2215db3cbfffSKeith Busch 2216eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2217db3cbfffSKeith Busch if (IS_ERR(req)) 2218db3cbfffSKeith Busch return PTR_ERR(req); 2219db3cbfffSKeith Busch 2220db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2221db3cbfffSKeith Busch req->end_io_data = nvmeq; 2222db3cbfffSKeith Busch 2223d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2224db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2225db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2226db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2227db3cbfffSKeith Busch return 0; 2228db3cbfffSKeith Busch } 2229db3cbfffSKeith Busch 22308fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2231db3cbfffSKeith Busch { 22325271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2233db3cbfffSKeith Busch unsigned long timeout; 2234db3cbfffSKeith Busch 2235db3cbfffSKeith Busch retry: 2236db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22375271edd4SChristoph Hellwig while (nr_queues > 0) { 22385271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2239db3cbfffSKeith Busch break; 22405271edd4SChristoph Hellwig nr_queues--; 22415271edd4SChristoph Hellwig sent++; 22425271edd4SChristoph Hellwig } 2243d1ed6aa1SChristoph Hellwig while (sent) { 2244d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2245d1ed6aa1SChristoph Hellwig 2246d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22475271edd4SChristoph Hellwig timeout); 2248db3cbfffSKeith Busch if (timeout == 0) 22495271edd4SChristoph Hellwig return false; 2250d1ed6aa1SChristoph Hellwig 2251d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2252d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2253d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2254d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2255d1ed6aa1SChristoph Hellwig 2256d1ed6aa1SChristoph Hellwig sent--; 22575271edd4SChristoph Hellwig if (nr_queues) 2258db3cbfffSKeith Busch goto retry; 2259db3cbfffSKeith Busch } 22605271edd4SChristoph Hellwig return true; 2261db3cbfffSKeith Busch } 2262db3cbfffSKeith Busch 226357dacad5SJay Sternberg /* 22642b1b7e78SJianchao Wang * return error value only when tagset allocation failed 226557dacad5SJay Sternberg */ 226657dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 226757dacad5SJay Sternberg { 22682b1b7e78SJianchao Wang int ret; 22692b1b7e78SJianchao Wang 22705bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2271c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 227257dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2273ed92ad37SChristoph Hellwig dev->tagset.nr_maps = 2; /* default + read */ 2274ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2275ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 227657dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 227757dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 227857dacad5SJay Sternberg dev->tagset.queue_depth = 227957dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2280a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2281a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2282a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2283a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2284a7a7cbe3SChaitanya Kulkarni } 228557dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 228657dacad5SJay Sternberg dev->tagset.driver_data = dev; 228757dacad5SJay Sternberg 22882b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 22892b1b7e78SJianchao Wang if (ret) { 22902b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 22912b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 22922b1b7e78SJianchao Wang return ret; 22932b1b7e78SJianchao Wang } 22945bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2295f9f38e33SHelen Koike 2296f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2297949928c1SKeith Busch } else { 2298949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2299949928c1SKeith Busch 2300949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2301949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 230257dacad5SJay Sternberg } 2303949928c1SKeith Busch 230457dacad5SJay Sternberg return 0; 230557dacad5SJay Sternberg } 230657dacad5SJay Sternberg 2307b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 230857dacad5SJay Sternberg { 2309b00a726aSKeith Busch int result = -ENOMEM; 231057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 231157dacad5SJay Sternberg 231257dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 231357dacad5SJay Sternberg return result; 231457dacad5SJay Sternberg 231557dacad5SJay Sternberg pci_set_master(pdev); 231657dacad5SJay Sternberg 231757dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 231857dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 231957dacad5SJay Sternberg goto disable; 232057dacad5SJay Sternberg 23217a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 232257dacad5SJay Sternberg result = -ENODEV; 2323b00a726aSKeith Busch goto disable; 232457dacad5SJay Sternberg } 232557dacad5SJay Sternberg 232657dacad5SJay Sternberg /* 2327a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2328a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2329a5229050SKeith Busch * adjust this later. 233057dacad5SJay Sternberg */ 2331dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2332dca51e78SChristoph Hellwig if (result < 0) 2333dca51e78SChristoph Hellwig return result; 233457dacad5SJay Sternberg 233520d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23367a67cbeaSChristoph Hellwig 233720d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2338b27c1e68Sweiping zhang io_queue_depth); 233920d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23407a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23411f390c1fSStephan Günther 23421f390c1fSStephan Günther /* 23431f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23441f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23451f390c1fSStephan Günther */ 23461f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23471f390c1fSStephan Günther dev->q_depth = 2; 23489bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23499bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23501f390c1fSStephan Günther dev->q_depth); 2351d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2352d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 235320d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2354d554b5e1SMartin K. Petersen dev->q_depth = 64; 2355d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2356d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23571f390c1fSStephan Günther } 23581f390c1fSStephan Günther 2359f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2360202021c1SStephen Bates 2361a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2362a0a3408eSKeith Busch pci_save_state(pdev); 236357dacad5SJay Sternberg return 0; 236457dacad5SJay Sternberg 236557dacad5SJay Sternberg disable: 236657dacad5SJay Sternberg pci_disable_device(pdev); 236757dacad5SJay Sternberg return result; 236857dacad5SJay Sternberg } 236957dacad5SJay Sternberg 237057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 237157dacad5SJay Sternberg { 2372b00a726aSKeith Busch if (dev->bar) 2373b00a726aSKeith Busch iounmap(dev->bar); 2374a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2375b00a726aSKeith Busch } 2376b00a726aSKeith Busch 2377b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2378b00a726aSKeith Busch { 237957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 238057dacad5SJay Sternberg 2381dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 238257dacad5SJay Sternberg 2383a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2384a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 238557dacad5SJay Sternberg pci_disable_device(pdev); 238657dacad5SJay Sternberg } 2387a0a3408eSKeith Busch } 238857dacad5SJay Sternberg 2389a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 239057dacad5SJay Sternberg { 2391302ad8ccSKeith Busch bool dead = true; 2392302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 239357dacad5SJay Sternberg 239477bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2395302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2396302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2397302ad8ccSKeith Busch 2398ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2399ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2400302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2401302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2402302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 240357dacad5SJay Sternberg } 2404c21377f8SGabriel Krisman Bertazi 2405302ad8ccSKeith Busch /* 2406302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2407302ad8ccSKeith Busch * doing a safe shutdown. 2408302ad8ccSKeith Busch */ 240987ad72a5SChristoph Hellwig if (!dead) { 241087ad72a5SChristoph Hellwig if (shutdown) 2411302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24129a915a5bSJianchao Wang } 241387ad72a5SChristoph Hellwig 24149a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24159a915a5bSJianchao Wang 241664ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24178fae268bSKeith Busch nvme_disable_io_queues(dev); 2418a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 241957dacad5SJay Sternberg } 24208fae268bSKeith Busch nvme_suspend_io_queues(dev); 24218fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2422b00a726aSKeith Busch nvme_pci_disable(dev); 242357dacad5SJay Sternberg 2424e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2425e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2426302ad8ccSKeith Busch 2427302ad8ccSKeith Busch /* 2428302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2429302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2430302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2431302ad8ccSKeith Busch */ 2432302ad8ccSKeith Busch if (shutdown) 2433302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 243477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 243557dacad5SJay Sternberg } 243657dacad5SJay Sternberg 243757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 243857dacad5SJay Sternberg { 243957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 244057dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 244157dacad5SJay Sternberg if (!dev->prp_page_pool) 244257dacad5SJay Sternberg return -ENOMEM; 244357dacad5SJay Sternberg 244457dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 244557dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 244657dacad5SJay Sternberg 256, 256, 0); 244757dacad5SJay Sternberg if (!dev->prp_small_pool) { 244857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 244957dacad5SJay Sternberg return -ENOMEM; 245057dacad5SJay Sternberg } 245157dacad5SJay Sternberg return 0; 245257dacad5SJay Sternberg } 245357dacad5SJay Sternberg 245457dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 245557dacad5SJay Sternberg { 245657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 245757dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 245857dacad5SJay Sternberg } 245957dacad5SJay Sternberg 24601673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 246157dacad5SJay Sternberg { 24621673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 246357dacad5SJay Sternberg 2464f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 246557dacad5SJay Sternberg put_device(dev->dev); 246657dacad5SJay Sternberg if (dev->tagset.tags) 246757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24681c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24691c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 247057dacad5SJay Sternberg kfree(dev->queues); 2471e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2472943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 247357dacad5SJay Sternberg kfree(dev); 247457dacad5SJay Sternberg } 247557dacad5SJay Sternberg 2476f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2477f58944e2SKeith Busch { 2478237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2479f58944e2SKeith Busch 2480d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 248169d9a99cSKeith Busch nvme_dev_disable(dev, false); 24829f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 248303e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2484f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2485f58944e2SKeith Busch } 2486f58944e2SKeith Busch 2487fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 248857dacad5SJay Sternberg { 2489d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2490d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2491a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2492f58944e2SKeith Busch int result = -ENODEV; 24932b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 249457dacad5SJay Sternberg 249582b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2496fd634f41SChristoph Hellwig goto out; 2497fd634f41SChristoph Hellwig 2498fd634f41SChristoph Hellwig /* 2499fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2500fd634f41SChristoph Hellwig * moving on. 2501fd634f41SChristoph Hellwig */ 2502b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2503a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2504fd634f41SChristoph Hellwig 25055c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2506b00a726aSKeith Busch result = nvme_pci_enable(dev); 250757dacad5SJay Sternberg if (result) 25084726bcf3SKeith Busch goto out_unlock; 250957dacad5SJay Sternberg 251001ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 251157dacad5SJay Sternberg if (result) 25124726bcf3SKeith Busch goto out_unlock; 251357dacad5SJay Sternberg 251457dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 251557dacad5SJay Sternberg if (result) 25164726bcf3SKeith Busch goto out_unlock; 251757dacad5SJay Sternberg 2518943e942eSJens Axboe /* 2519943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2520943e942eSJens Axboe * over a single page. 2521943e942eSJens Axboe */ 2522943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2523943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 25245c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 25255c959d73SKeith Busch 25265c959d73SKeith Busch /* 25275c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 25285c959d73SKeith Busch * initializing procedure here. 25295c959d73SKeith Busch */ 25305c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 25315c959d73SKeith Busch dev_warn(dev->ctrl.device, 25325c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 25335c959d73SKeith Busch goto out; 25345c959d73SKeith Busch } 2535943e942eSJens Axboe 2536ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2537ce4541f4SChristoph Hellwig if (result) 2538f58944e2SKeith Busch goto out; 2539ce4541f4SChristoph Hellwig 2540e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2541e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25424f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25434f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2544e286bcfcSScott Bauer else if (was_suspend) 25454f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2546e286bcfcSScott Bauer } else { 2547e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2548e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2549e286bcfcSScott Bauer } 2550a98e58e5SScott Bauer 2551f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2552f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2553f9f38e33SHelen Koike if (result) 2554f9f38e33SHelen Koike dev_warn(dev->dev, 2555f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2556f9f38e33SHelen Koike } 2557f9f38e33SHelen Koike 25589620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25599620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25609620cfbaSChristoph Hellwig if (result < 0) 25619620cfbaSChristoph Hellwig goto out; 25629620cfbaSChristoph Hellwig } 256387ad72a5SChristoph Hellwig 256457dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 256557dacad5SJay Sternberg if (result) 2566f58944e2SKeith Busch goto out; 256757dacad5SJay Sternberg 256821f033f7SKeith Busch /* 256957dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 257057dacad5SJay Sternberg * any working I/O queue. 257157dacad5SJay Sternberg */ 257257dacad5SJay Sternberg if (dev->online_queues < 2) { 25731b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25743b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25755bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25762b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 257757dacad5SJay Sternberg } else { 257825646264SKeith Busch nvme_start_queues(&dev->ctrl); 2579302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25802b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25812b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 25822b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2583302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 258457dacad5SJay Sternberg } 258557dacad5SJay Sternberg 25862b1b7e78SJianchao Wang /* 25872b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 25882b1b7e78SJianchao Wang * recovery. 25892b1b7e78SJianchao Wang */ 25902b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 25912b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25922b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2593bb8d261eSChristoph Hellwig goto out; 2594bb8d261eSChristoph Hellwig } 259592911a55SChristoph Hellwig 2596d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 259757dacad5SJay Sternberg return; 259857dacad5SJay Sternberg 25994726bcf3SKeith Busch out_unlock: 26004726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 260157dacad5SJay Sternberg out: 2602f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 260357dacad5SJay Sternberg } 260457dacad5SJay Sternberg 26055c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 260657dacad5SJay Sternberg { 26075c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 260857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 260957dacad5SJay Sternberg 261057dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2611921920abSKeith Busch device_release_driver(&pdev->dev); 26121673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 261357dacad5SJay Sternberg } 261457dacad5SJay Sternberg 26151c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 261657dacad5SJay Sternberg { 26171c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26181c63dc66SChristoph Hellwig return 0; 261957dacad5SJay Sternberg } 26201c63dc66SChristoph Hellwig 26215fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26225fd4ce1bSChristoph Hellwig { 26235fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26245fd4ce1bSChristoph Hellwig return 0; 26255fd4ce1bSChristoph Hellwig } 26265fd4ce1bSChristoph Hellwig 26277fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26287fd8930fSChristoph Hellwig { 26297fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26307fd8930fSChristoph Hellwig return 0; 26317fd8930fSChristoph Hellwig } 26327fd8930fSChristoph Hellwig 263397c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 263497c12223SKeith Busch { 263597c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 263697c12223SKeith Busch 263797c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 263897c12223SKeith Busch } 263997c12223SKeith Busch 26401c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26411a353d85SMing Lin .name = "pcie", 2642e439bb12SSagi Grimberg .module = THIS_MODULE, 2643e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2644e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26451c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26465fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26477fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26481673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2649f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 265097c12223SKeith Busch .get_address = nvme_pci_get_address, 26511c63dc66SChristoph Hellwig }; 265257dacad5SJay Sternberg 2653b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2654b00a726aSKeith Busch { 2655b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2656b00a726aSKeith Busch 2657a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2658b00a726aSKeith Busch return -ENODEV; 2659b00a726aSKeith Busch 266097f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2661b00a726aSKeith Busch goto release; 2662b00a726aSKeith Busch 2663b00a726aSKeith Busch return 0; 2664b00a726aSKeith Busch release: 2665a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2666b00a726aSKeith Busch return -ENODEV; 2667b00a726aSKeith Busch } 2668b00a726aSKeith Busch 26698427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2670ff5350a8SAndy Lutomirski { 2671ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2672ff5350a8SAndy Lutomirski /* 2673ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2674ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2675ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2676ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2677ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2678ff5350a8SAndy Lutomirski * laptops. 2679ff5350a8SAndy Lutomirski */ 2680ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2681ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2682ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2683ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 26848427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 26858427bbc2SKai-Heng Feng /* 26868427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2687467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2688467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2689467c77d4SJarosław Janik * ASUS PRIME Z370-A 26908427bbc2SKai-Heng Feng */ 26918427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2692467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2693467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 26948427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2695ff5350a8SAndy Lutomirski } 2696ff5350a8SAndy Lutomirski 2697ff5350a8SAndy Lutomirski return 0; 2698ff5350a8SAndy Lutomirski } 2699ff5350a8SAndy Lutomirski 270018119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 270118119775SKeith Busch { 270218119775SKeith Busch struct nvme_dev *dev = data; 270380f513b5SKeith Busch 270418119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 270518119775SKeith Busch flush_work(&dev->ctrl.scan_work); 270680f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 270718119775SKeith Busch } 270818119775SKeith Busch 270957dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 271057dacad5SJay Sternberg { 271157dacad5SJay Sternberg int node, result = -ENOMEM; 271257dacad5SJay Sternberg struct nvme_dev *dev; 2713ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2714943e942eSJens Axboe size_t alloc_size; 271557dacad5SJay Sternberg 271657dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 271757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27182fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 271957dacad5SJay Sternberg 272057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 272157dacad5SJay Sternberg if (!dev) 272257dacad5SJay Sternberg return -ENOMEM; 2723147b27e4SSagi Grimberg 27243b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27253b6592f7SJens Axboe GFP_KERNEL, node); 272657dacad5SJay Sternberg if (!dev->queues) 272757dacad5SJay Sternberg goto free; 272857dacad5SJay Sternberg 272957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 273057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 273157dacad5SJay Sternberg 2732b00a726aSKeith Busch result = nvme_dev_map(dev); 2733b00a726aSKeith Busch if (result) 2734b00c9b7aSChristophe JAILLET goto put_pci; 2735b00a726aSKeith Busch 2736d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27375c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 273877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2739f3ca80fcSChristoph Hellwig 2740f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2741f3ca80fcSChristoph Hellwig if (result) 2742b00c9b7aSChristophe JAILLET goto unmap; 2743f3ca80fcSChristoph Hellwig 27448427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2745ff5350a8SAndy Lutomirski 2746943e942eSJens Axboe /* 2747943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2748943e942eSJens Axboe * command we support. 2749943e942eSJens Axboe */ 2750943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2751943e942eSJens Axboe NVME_MAX_SEGS, true); 2752943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2753943e942eSJens Axboe 2754943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2755943e942eSJens Axboe mempool_kfree, 2756943e942eSJens Axboe (void *) alloc_size, 2757943e942eSJens Axboe GFP_KERNEL, node); 2758943e942eSJens Axboe if (!dev->iod_mempool) { 2759943e942eSJens Axboe result = -ENOMEM; 2760943e942eSJens Axboe goto release_pools; 2761943e942eSJens Axboe } 2762943e942eSJens Axboe 2763b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2764b6e44b4cSKeith Busch quirks); 2765b6e44b4cSKeith Busch if (result) 2766b6e44b4cSKeith Busch goto release_mempool; 2767b6e44b4cSKeith Busch 27681b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27691b3c47c1SSagi Grimberg 277080f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 277118119775SKeith Busch async_schedule(nvme_async_probe, dev); 27724caff8fcSSagi Grimberg 277357dacad5SJay Sternberg return 0; 277457dacad5SJay Sternberg 2775b6e44b4cSKeith Busch release_mempool: 2776b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 277757dacad5SJay Sternberg release_pools: 277857dacad5SJay Sternberg nvme_release_prp_pools(dev); 2779b00c9b7aSChristophe JAILLET unmap: 2780b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 278157dacad5SJay Sternberg put_pci: 278257dacad5SJay Sternberg put_device(dev->dev); 278357dacad5SJay Sternberg free: 278457dacad5SJay Sternberg kfree(dev->queues); 278557dacad5SJay Sternberg kfree(dev); 278657dacad5SJay Sternberg return result; 278757dacad5SJay Sternberg } 278857dacad5SJay Sternberg 2789775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 279057dacad5SJay Sternberg { 279157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2792a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2793775755edSChristoph Hellwig } 279457dacad5SJay Sternberg 2795775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2796775755edSChristoph Hellwig { 2797f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 279879c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 279957dacad5SJay Sternberg } 280057dacad5SJay Sternberg 280157dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 280257dacad5SJay Sternberg { 280357dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2804a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 280557dacad5SJay Sternberg } 280657dacad5SJay Sternberg 2807f58944e2SKeith Busch /* 2808f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2809f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2810f58944e2SKeith Busch * order to proceed. 2811f58944e2SKeith Busch */ 281257dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 281357dacad5SJay Sternberg { 281457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 281557dacad5SJay Sternberg 2816bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 281757dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28180ff9d4e1SKeith Busch 28196db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28200ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28211d39e692SKeith Busch nvme_dev_disable(dev, true); 2822cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28236db28edaSKeith Busch } 28240ff9d4e1SKeith Busch 2825d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2826d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2827d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2828a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28299fe5c59fSKeith Busch nvme_release_cmb(dev); 283087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 283157dacad5SJay Sternberg nvme_dev_remove_admin(dev); 283257dacad5SJay Sternberg nvme_free_queues(dev, 0); 2833d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 283457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2835b00a726aSKeith Busch nvme_dev_unmap(dev); 28361673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 283757dacad5SJay Sternberg } 283857dacad5SJay Sternberg 283957dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 284057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 284157dacad5SJay Sternberg { 284257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 284357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 284457dacad5SJay Sternberg 2845a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 284657dacad5SJay Sternberg return 0; 284757dacad5SJay Sternberg } 284857dacad5SJay Sternberg 284957dacad5SJay Sternberg static int nvme_resume(struct device *dev) 285057dacad5SJay Sternberg { 285157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 285257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 285357dacad5SJay Sternberg 2854d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 285557dacad5SJay Sternberg return 0; 285657dacad5SJay Sternberg } 285757dacad5SJay Sternberg #endif 285857dacad5SJay Sternberg 285957dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 286057dacad5SJay Sternberg 2861a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2862a0a3408eSKeith Busch pci_channel_state_t state) 2863a0a3408eSKeith Busch { 2864a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2865a0a3408eSKeith Busch 2866a0a3408eSKeith Busch /* 2867a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2868a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2869a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2870a0a3408eSKeith Busch */ 2871a0a3408eSKeith Busch switch (state) { 2872a0a3408eSKeith Busch case pci_channel_io_normal: 2873a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2874a0a3408eSKeith Busch case pci_channel_io_frozen: 2875d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2876d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2877a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2878a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2879a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2880d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2881d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2882a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2883a0a3408eSKeith Busch } 2884a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2885a0a3408eSKeith Busch } 2886a0a3408eSKeith Busch 2887a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2888a0a3408eSKeith Busch { 2889a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2890a0a3408eSKeith Busch 28911b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2892a0a3408eSKeith Busch pci_restore_state(pdev); 2893d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2894a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2895a0a3408eSKeith Busch } 2896a0a3408eSKeith Busch 2897a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2898a0a3408eSKeith Busch { 289972cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 290072cd4cc2SKeith Busch 290172cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2902a0a3408eSKeith Busch } 2903a0a3408eSKeith Busch 290457dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 290557dacad5SJay Sternberg .error_detected = nvme_error_detected, 290657dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 290757dacad5SJay Sternberg .resume = nvme_error_resume, 2908775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2909775755edSChristoph Hellwig .reset_done = nvme_reset_done, 291057dacad5SJay Sternberg }; 291157dacad5SJay Sternberg 291257dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2913106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 291408095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2915e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 291699466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 291799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2918e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 291999466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 292099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2921e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2922f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2923f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2924f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 292550af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29269abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29279abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 29286299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 29296299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 2930540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 29317b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 29327b210e4eSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 29330302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29340302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 293554adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 293654adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29378c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29388c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2939015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2940015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2941d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2942d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2943d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2944d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2945608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2946608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2947608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2948608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2949ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2950ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 295157dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2952c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2953124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 295457dacad5SJay Sternberg { 0, } 295557dacad5SJay Sternberg }; 295657dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 295757dacad5SJay Sternberg 295857dacad5SJay Sternberg static struct pci_driver nvme_driver = { 295957dacad5SJay Sternberg .name = "nvme", 296057dacad5SJay Sternberg .id_table = nvme_id_table, 296157dacad5SJay Sternberg .probe = nvme_probe, 296257dacad5SJay Sternberg .remove = nvme_remove, 296357dacad5SJay Sternberg .shutdown = nvme_shutdown, 296457dacad5SJay Sternberg .driver = { 296557dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 296657dacad5SJay Sternberg }, 296774d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 296857dacad5SJay Sternberg .err_handler = &nvme_err_handler, 296957dacad5SJay Sternberg }; 297057dacad5SJay Sternberg 297157dacad5SJay Sternberg static int __init nvme_init(void) 297257dacad5SJay Sternberg { 2973612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 29749a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 297557dacad5SJay Sternberg } 297657dacad5SJay Sternberg 297757dacad5SJay Sternberg static void __exit nvme_exit(void) 297857dacad5SJay Sternberg { 297957dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 298003e0f3a6SMing Lei flush_workqueue(nvme_wq); 298157dacad5SJay Sternberg _nvme_check_size(); 298257dacad5SJay Sternberg } 298357dacad5SJay Sternberg 298457dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 298557dacad5SJay Sternberg MODULE_LICENSE("GPL"); 298657dacad5SJay Sternberg MODULE_VERSION("1.0"); 298757dacad5SJay Sternberg module_init(nvme_init); 298857dacad5SJay Sternberg module_exit(nvme_exit); 2989