157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1657dacad5SJay Sternberg #include <linux/bitops.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 2057dacad5SJay Sternberg #include <linux/cpu.h> 2157dacad5SJay Sternberg #include <linux/delay.h> 22ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2357dacad5SJay Sternberg #include <linux/errno.h> 2457dacad5SJay Sternberg #include <linux/fs.h> 2557dacad5SJay Sternberg #include <linux/genhd.h> 2657dacad5SJay Sternberg #include <linux/hdreg.h> 2757dacad5SJay Sternberg #include <linux/idr.h> 2857dacad5SJay Sternberg #include <linux/init.h> 2957dacad5SJay Sternberg #include <linux/interrupt.h> 3057dacad5SJay Sternberg #include <linux/io.h> 3157dacad5SJay Sternberg #include <linux/kdev_t.h> 3257dacad5SJay Sternberg #include <linux/kernel.h> 3357dacad5SJay Sternberg #include <linux/mm.h> 3457dacad5SJay Sternberg #include <linux/module.h> 3557dacad5SJay Sternberg #include <linux/moduleparam.h> 3677bf25eaSKeith Busch #include <linux/mutex.h> 3757dacad5SJay Sternberg #include <linux/pci.h> 3857dacad5SJay Sternberg #include <linux/poison.h> 3957dacad5SJay Sternberg #include <linux/ptrace.h> 4057dacad5SJay Sternberg #include <linux/sched.h> 4157dacad5SJay Sternberg #include <linux/slab.h> 4257dacad5SJay Sternberg #include <linux/t10-pi.h> 432d55cd5fSChristoph Hellwig #include <linux/timer.h> 4457dacad5SJay Sternberg #include <linux/types.h> 459cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 461d277a63SKeith Busch #include <asm/unaligned.h> 47a98e58e5SScott Bauer #include <linux/sed-opal.h> 4857dacad5SJay Sternberg 4957dacad5SJay Sternberg #include "nvme.h" 5057dacad5SJay Sternberg 5157dacad5SJay Sternberg #define NVME_Q_DEPTH 1024 5257dacad5SJay Sternberg #define NVME_AQ_DEPTH 256 5357dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 5457dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 5557dacad5SJay Sternberg 56adf68f21SChristoph Hellwig /* 57adf68f21SChristoph Hellwig * We handle AEN commands ourselves and don't even let the 58adf68f21SChristoph Hellwig * block layer know about them. 59adf68f21SChristoph Hellwig */ 60f866fc42SChristoph Hellwig #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS) 61adf68f21SChristoph Hellwig 6257dacad5SJay Sternberg static int use_threaded_interrupts; 6357dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 6457dacad5SJay Sternberg 6557dacad5SJay Sternberg static bool use_cmb_sqes = true; 6657dacad5SJay Sternberg module_param(use_cmb_sqes, bool, 0644); 6757dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 6857dacad5SJay Sternberg 6987ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 7087ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 7187ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 7287ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 7387ad72a5SChristoph Hellwig 7457dacad5SJay Sternberg static struct workqueue_struct *nvme_workq; 7557dacad5SJay Sternberg 761c63dc66SChristoph Hellwig struct nvme_dev; 771c63dc66SChristoph Hellwig struct nvme_queue; 7857dacad5SJay Sternberg 7957dacad5SJay Sternberg static int nvme_reset(struct nvme_dev *dev); 80a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq); 81a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 8257dacad5SJay Sternberg 8357dacad5SJay Sternberg /* 841c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 851c63dc66SChristoph Hellwig */ 861c63dc66SChristoph Hellwig struct nvme_dev { 871c63dc66SChristoph Hellwig struct nvme_queue **queues; 881c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 891c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 901c63dc66SChristoph Hellwig u32 __iomem *dbs; 911c63dc66SChristoph Hellwig struct device *dev; 921c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 931c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 941c63dc66SChristoph Hellwig unsigned queue_count; 951c63dc66SChristoph Hellwig unsigned online_queues; 961c63dc66SChristoph Hellwig unsigned max_qid; 971c63dc66SChristoph Hellwig int q_depth; 981c63dc66SChristoph Hellwig u32 db_stride; 991c63dc66SChristoph Hellwig void __iomem *bar; 1001c63dc66SChristoph Hellwig struct work_struct reset_work; 1015c8809e6SChristoph Hellwig struct work_struct remove_work; 1022d55cd5fSChristoph Hellwig struct timer_list watchdog_timer; 10377bf25eaSKeith Busch struct mutex shutdown_lock; 1041c63dc66SChristoph Hellwig bool subsystem; 1051c63dc66SChristoph Hellwig void __iomem *cmb; 1061c63dc66SChristoph Hellwig dma_addr_t cmb_dma_addr; 1071c63dc66SChristoph Hellwig u64 cmb_size; 1081c63dc66SChristoph Hellwig u32 cmbsz; 109202021c1SStephen Bates u32 cmbloc; 1101c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 111db3cbfffSKeith Busch struct completion ioq_wait; 11287ad72a5SChristoph Hellwig 11387ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 114f9f38e33SHelen Koike u32 *dbbuf_dbs; 115f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 116f9f38e33SHelen Koike u32 *dbbuf_eis; 117f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 11887ad72a5SChristoph Hellwig 11987ad72a5SChristoph Hellwig /* host memory buffer support: */ 12087ad72a5SChristoph Hellwig u64 host_mem_size; 12187ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 12287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 12387ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 12457dacad5SJay Sternberg }; 12557dacad5SJay Sternberg 126f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 127f9f38e33SHelen Koike { 128f9f38e33SHelen Koike return qid * 2 * stride; 129f9f38e33SHelen Koike } 130f9f38e33SHelen Koike 131f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 132f9f38e33SHelen Koike { 133f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 134f9f38e33SHelen Koike } 135f9f38e33SHelen Koike 1361c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1371c63dc66SChristoph Hellwig { 1381c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1391c63dc66SChristoph Hellwig } 1401c63dc66SChristoph Hellwig 14157dacad5SJay Sternberg /* 14257dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 14357dacad5SJay Sternberg * commands and one for I/O commands). 14457dacad5SJay Sternberg */ 14557dacad5SJay Sternberg struct nvme_queue { 14657dacad5SJay Sternberg struct device *q_dmadev; 14757dacad5SJay Sternberg struct nvme_dev *dev; 14857dacad5SJay Sternberg spinlock_t q_lock; 14957dacad5SJay Sternberg struct nvme_command *sq_cmds; 15057dacad5SJay Sternberg struct nvme_command __iomem *sq_cmds_io; 15157dacad5SJay Sternberg volatile struct nvme_completion *cqes; 15257dacad5SJay Sternberg struct blk_mq_tags **tags; 15357dacad5SJay Sternberg dma_addr_t sq_dma_addr; 15457dacad5SJay Sternberg dma_addr_t cq_dma_addr; 15557dacad5SJay Sternberg u32 __iomem *q_db; 15657dacad5SJay Sternberg u16 q_depth; 15757dacad5SJay Sternberg s16 cq_vector; 15857dacad5SJay Sternberg u16 sq_tail; 15957dacad5SJay Sternberg u16 cq_head; 16057dacad5SJay Sternberg u16 qid; 16157dacad5SJay Sternberg u8 cq_phase; 16257dacad5SJay Sternberg u8 cqe_seen; 163f9f38e33SHelen Koike u32 *dbbuf_sq_db; 164f9f38e33SHelen Koike u32 *dbbuf_cq_db; 165f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 166f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 16757dacad5SJay Sternberg }; 16857dacad5SJay Sternberg 16957dacad5SJay Sternberg /* 17071bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 17171bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 172f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 17371bd150cSChristoph Hellwig * allocated to store the PRP list. 17471bd150cSChristoph Hellwig */ 17571bd150cSChristoph Hellwig struct nvme_iod { 176d49187e9SChristoph Hellwig struct nvme_request req; 177f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 178f4800d6dSChristoph Hellwig int aborted; 17971bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 18071bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 18171bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 18271bd150cSChristoph Hellwig dma_addr_t first_dma; 183bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 184f4800d6dSChristoph Hellwig struct scatterlist *sg; 185f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 18657dacad5SJay Sternberg }; 18757dacad5SJay Sternberg 18857dacad5SJay Sternberg /* 18957dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 19057dacad5SJay Sternberg */ 19157dacad5SJay Sternberg static inline void _nvme_check_size(void) 19257dacad5SJay Sternberg { 19357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 19457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 19557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 19657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 19757dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 19857dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 19957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 20057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 20157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096); 20257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096); 20357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 20457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 205f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 206f9f38e33SHelen Koike } 207f9f38e33SHelen Koike 208f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 209f9f38e33SHelen Koike { 210f9f38e33SHelen Koike return ((num_possible_cpus() + 1) * 8 * stride); 211f9f38e33SHelen Koike } 212f9f38e33SHelen Koike 213f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 214f9f38e33SHelen Koike { 215f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 216f9f38e33SHelen Koike 217f9f38e33SHelen Koike if (dev->dbbuf_dbs) 218f9f38e33SHelen Koike return 0; 219f9f38e33SHelen Koike 220f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 221f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 222f9f38e33SHelen Koike GFP_KERNEL); 223f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 224f9f38e33SHelen Koike return -ENOMEM; 225f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 226f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 227f9f38e33SHelen Koike GFP_KERNEL); 228f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 229f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 230f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 231f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 232f9f38e33SHelen Koike return -ENOMEM; 233f9f38e33SHelen Koike } 234f9f38e33SHelen Koike 235f9f38e33SHelen Koike return 0; 236f9f38e33SHelen Koike } 237f9f38e33SHelen Koike 238f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 239f9f38e33SHelen Koike { 240f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 241f9f38e33SHelen Koike 242f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 243f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 244f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 245f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 246f9f38e33SHelen Koike } 247f9f38e33SHelen Koike if (dev->dbbuf_eis) { 248f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 249f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 250f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 251f9f38e33SHelen Koike } 252f9f38e33SHelen Koike } 253f9f38e33SHelen Koike 254f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 255f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 256f9f38e33SHelen Koike { 257f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 258f9f38e33SHelen Koike return; 259f9f38e33SHelen Koike 260f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 261f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 262f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 263f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 264f9f38e33SHelen Koike } 265f9f38e33SHelen Koike 266f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 267f9f38e33SHelen Koike { 268f9f38e33SHelen Koike struct nvme_command c; 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 271f9f38e33SHelen Koike return; 272f9f38e33SHelen Koike 273f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 274f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 275f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 276f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 277f9f38e33SHelen Koike 278f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 2799bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 280f9f38e33SHelen Koike /* Free memory and continue on */ 281f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 282f9f38e33SHelen Koike } 283f9f38e33SHelen Koike } 284f9f38e33SHelen Koike 285f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 286f9f38e33SHelen Koike { 287f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 288f9f38e33SHelen Koike } 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 291f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 292f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 293f9f38e33SHelen Koike { 294f9f38e33SHelen Koike if (dbbuf_db) { 295f9f38e33SHelen Koike u16 old_value; 296f9f38e33SHelen Koike 297f9f38e33SHelen Koike /* 298f9f38e33SHelen Koike * Ensure that the queue is written before updating 299f9f38e33SHelen Koike * the doorbell in memory 300f9f38e33SHelen Koike */ 301f9f38e33SHelen Koike wmb(); 302f9f38e33SHelen Koike 303f9f38e33SHelen Koike old_value = *dbbuf_db; 304f9f38e33SHelen Koike *dbbuf_db = value; 305f9f38e33SHelen Koike 306f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 307f9f38e33SHelen Koike return false; 308f9f38e33SHelen Koike } 309f9f38e33SHelen Koike 310f9f38e33SHelen Koike return true; 31157dacad5SJay Sternberg } 31257dacad5SJay Sternberg 31357dacad5SJay Sternberg /* 31457dacad5SJay Sternberg * Max size of iod being embedded in the request payload 31557dacad5SJay Sternberg */ 31657dacad5SJay Sternberg #define NVME_INT_PAGES 2 3175fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 31857dacad5SJay Sternberg 31957dacad5SJay Sternberg /* 32057dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 32157dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 32257dacad5SJay Sternberg * the I/O. 32357dacad5SJay Sternberg */ 32457dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 32557dacad5SJay Sternberg { 3265fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3275fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 32857dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 32957dacad5SJay Sternberg } 33057dacad5SJay Sternberg 331f4800d6dSChristoph Hellwig static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev, 332f4800d6dSChristoph Hellwig unsigned int size, unsigned int nseg) 333f4800d6dSChristoph Hellwig { 334f4800d6dSChristoph Hellwig return sizeof(__le64 *) * nvme_npages(size, dev) + 335f4800d6dSChristoph Hellwig sizeof(struct scatterlist) * nseg; 336f4800d6dSChristoph Hellwig } 337f4800d6dSChristoph Hellwig 33857dacad5SJay Sternberg static unsigned int nvme_cmd_size(struct nvme_dev *dev) 33957dacad5SJay Sternberg { 340f4800d6dSChristoph Hellwig return sizeof(struct nvme_iod) + 341f4800d6dSChristoph Hellwig nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES); 34257dacad5SJay Sternberg } 34357dacad5SJay Sternberg 34457dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 34557dacad5SJay Sternberg unsigned int hctx_idx) 34657dacad5SJay Sternberg { 34757dacad5SJay Sternberg struct nvme_dev *dev = data; 34857dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 34957dacad5SJay Sternberg 35057dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 35157dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 35257dacad5SJay Sternberg WARN_ON(nvmeq->tags); 35357dacad5SJay Sternberg 35457dacad5SJay Sternberg hctx->driver_data = nvmeq; 35557dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 35657dacad5SJay Sternberg return 0; 35757dacad5SJay Sternberg } 35857dacad5SJay Sternberg 35957dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 36057dacad5SJay Sternberg { 36157dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 36257dacad5SJay Sternberg 36357dacad5SJay Sternberg nvmeq->tags = NULL; 36457dacad5SJay Sternberg } 36557dacad5SJay Sternberg 366d6296d39SChristoph Hellwig static int nvme_admin_init_request(struct blk_mq_tag_set *set, 367d6296d39SChristoph Hellwig struct request *req, unsigned int hctx_idx, 36857dacad5SJay Sternberg unsigned int numa_node) 36957dacad5SJay Sternberg { 370d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 371f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 37257dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[0]; 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg BUG_ON(!nvmeq); 375f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 37657dacad5SJay Sternberg return 0; 37757dacad5SJay Sternberg } 37857dacad5SJay Sternberg 37957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 38057dacad5SJay Sternberg unsigned int hctx_idx) 38157dacad5SJay Sternberg { 38257dacad5SJay Sternberg struct nvme_dev *dev = data; 38357dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 38457dacad5SJay Sternberg 38557dacad5SJay Sternberg if (!nvmeq->tags) 38657dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 38757dacad5SJay Sternberg 38857dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 38957dacad5SJay Sternberg hctx->driver_data = nvmeq; 39057dacad5SJay Sternberg return 0; 39157dacad5SJay Sternberg } 39257dacad5SJay Sternberg 393d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 394d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 39557dacad5SJay Sternberg { 396d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 397f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 39857dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1]; 39957dacad5SJay Sternberg 40057dacad5SJay Sternberg BUG_ON(!nvmeq); 401f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 40257dacad5SJay Sternberg return 0; 40357dacad5SJay Sternberg } 40457dacad5SJay Sternberg 405dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 406dca51e78SChristoph Hellwig { 407dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 408dca51e78SChristoph Hellwig 409dca51e78SChristoph Hellwig return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev)); 410dca51e78SChristoph Hellwig } 411dca51e78SChristoph Hellwig 41257dacad5SJay Sternberg /** 413adf68f21SChristoph Hellwig * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 41457dacad5SJay Sternberg * @nvmeq: The queue to use 41557dacad5SJay Sternberg * @cmd: The command to send 41657dacad5SJay Sternberg * 41757dacad5SJay Sternberg * Safe to use from interrupt context 41857dacad5SJay Sternberg */ 41957dacad5SJay Sternberg static void __nvme_submit_cmd(struct nvme_queue *nvmeq, 42057dacad5SJay Sternberg struct nvme_command *cmd) 42157dacad5SJay Sternberg { 42257dacad5SJay Sternberg u16 tail = nvmeq->sq_tail; 42357dacad5SJay Sternberg 42457dacad5SJay Sternberg if (nvmeq->sq_cmds_io) 42557dacad5SJay Sternberg memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd)); 42657dacad5SJay Sternberg else 42757dacad5SJay Sternberg memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd)); 42857dacad5SJay Sternberg 42957dacad5SJay Sternberg if (++tail == nvmeq->q_depth) 43057dacad5SJay Sternberg tail = 0; 431f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db, 432f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei)) 43357dacad5SJay Sternberg writel(tail, nvmeq->q_db); 43457dacad5SJay Sternberg nvmeq->sq_tail = tail; 43557dacad5SJay Sternberg } 43657dacad5SJay Sternberg 437f4800d6dSChristoph Hellwig static __le64 **iod_list(struct request *req) 43857dacad5SJay Sternberg { 439f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 440f9d03f96SChristoph Hellwig return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req)); 44157dacad5SJay Sternberg } 44257dacad5SJay Sternberg 443fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 44457dacad5SJay Sternberg { 445f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 446f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 447b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 448f4800d6dSChristoph Hellwig 449f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 450f4800d6dSChristoph Hellwig iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC); 451f4800d6dSChristoph Hellwig if (!iod->sg) 452fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 453f4800d6dSChristoph Hellwig } else { 454f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 45557dacad5SJay Sternberg } 45657dacad5SJay Sternberg 457f4800d6dSChristoph Hellwig iod->aborted = 0; 45857dacad5SJay Sternberg iod->npages = -1; 45957dacad5SJay Sternberg iod->nents = 0; 460f4800d6dSChristoph Hellwig iod->length = size; 461f80ec966SKeith Busch 462fc17b653SChristoph Hellwig return BLK_STS_OK; 46357dacad5SJay Sternberg } 46457dacad5SJay Sternberg 465f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 46657dacad5SJay Sternberg { 467f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4685fd4ce1bSChristoph Hellwig const int last_prp = dev->ctrl.page_size / 8 - 1; 46957dacad5SJay Sternberg int i; 470f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 47157dacad5SJay Sternberg dma_addr_t prp_dma = iod->first_dma; 47257dacad5SJay Sternberg 47357dacad5SJay Sternberg if (iod->npages == 0) 47457dacad5SJay Sternberg dma_pool_free(dev->prp_small_pool, list[0], prp_dma); 47557dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 47657dacad5SJay Sternberg __le64 *prp_list = list[i]; 47757dacad5SJay Sternberg dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]); 47857dacad5SJay Sternberg dma_pool_free(dev->prp_page_pool, prp_list, prp_dma); 47957dacad5SJay Sternberg prp_dma = next_prp_dma; 48057dacad5SJay Sternberg } 48157dacad5SJay Sternberg 482f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 483f4800d6dSChristoph Hellwig kfree(iod->sg); 48457dacad5SJay Sternberg } 48557dacad5SJay Sternberg 48657dacad5SJay Sternberg #ifdef CONFIG_BLK_DEV_INTEGRITY 48757dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 48857dacad5SJay Sternberg { 48957dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == v) 49057dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(p); 49157dacad5SJay Sternberg } 49257dacad5SJay Sternberg 49357dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 49457dacad5SJay Sternberg { 49557dacad5SJay Sternberg if (be32_to_cpu(pi->ref_tag) == p) 49657dacad5SJay Sternberg pi->ref_tag = cpu_to_be32(v); 49757dacad5SJay Sternberg } 49857dacad5SJay Sternberg 49957dacad5SJay Sternberg /** 50057dacad5SJay Sternberg * nvme_dif_remap - remaps ref tags to bip seed and physical lba 50157dacad5SJay Sternberg * 50257dacad5SJay Sternberg * The virtual start sector is the one that was originally submitted by the 50357dacad5SJay Sternberg * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical 50457dacad5SJay Sternberg * start sector may be different. Remap protection information to match the 50557dacad5SJay Sternberg * physical LBA on writes, and back to the original seed on reads. 50657dacad5SJay Sternberg * 50757dacad5SJay Sternberg * Type 0 and 3 do not have a ref tag, so no remapping required. 50857dacad5SJay Sternberg */ 50957dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 51057dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 51157dacad5SJay Sternberg { 51257dacad5SJay Sternberg struct nvme_ns *ns = req->rq_disk->private_data; 51357dacad5SJay Sternberg struct bio_integrity_payload *bip; 51457dacad5SJay Sternberg struct t10_pi_tuple *pi; 51557dacad5SJay Sternberg void *p, *pmap; 51657dacad5SJay Sternberg u32 i, nlb, ts, phys, virt; 51757dacad5SJay Sternberg 51857dacad5SJay Sternberg if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3) 51957dacad5SJay Sternberg return; 52057dacad5SJay Sternberg 52157dacad5SJay Sternberg bip = bio_integrity(req->bio); 52257dacad5SJay Sternberg if (!bip) 52357dacad5SJay Sternberg return; 52457dacad5SJay Sternberg 52557dacad5SJay Sternberg pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset; 52657dacad5SJay Sternberg 52757dacad5SJay Sternberg p = pmap; 52857dacad5SJay Sternberg virt = bip_get_seed(bip); 52957dacad5SJay Sternberg phys = nvme_block_nr(ns, blk_rq_pos(req)); 53057dacad5SJay Sternberg nlb = (blk_rq_bytes(req) >> ns->lba_shift); 531ac6fc48cSDan Williams ts = ns->disk->queue->integrity.tuple_size; 53257dacad5SJay Sternberg 53357dacad5SJay Sternberg for (i = 0; i < nlb; i++, virt++, phys++) { 53457dacad5SJay Sternberg pi = (struct t10_pi_tuple *)p; 53557dacad5SJay Sternberg dif_swap(phys, virt, pi); 53657dacad5SJay Sternberg p += ts; 53757dacad5SJay Sternberg } 53857dacad5SJay Sternberg kunmap_atomic(pmap); 53957dacad5SJay Sternberg } 54057dacad5SJay Sternberg #else /* CONFIG_BLK_DEV_INTEGRITY */ 54157dacad5SJay Sternberg static void nvme_dif_remap(struct request *req, 54257dacad5SJay Sternberg void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi)) 54357dacad5SJay Sternberg { 54457dacad5SJay Sternberg } 54557dacad5SJay Sternberg static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 54657dacad5SJay Sternberg { 54757dacad5SJay Sternberg } 54857dacad5SJay Sternberg static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi) 54957dacad5SJay Sternberg { 55057dacad5SJay Sternberg } 55157dacad5SJay Sternberg #endif 55257dacad5SJay Sternberg 553b131c61dSChristoph Hellwig static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req) 55457dacad5SJay Sternberg { 555f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 55657dacad5SJay Sternberg struct dma_pool *pool; 557b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 55857dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 55957dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 56057dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5615fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 56257dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 56357dacad5SJay Sternberg __le64 *prp_list; 564f4800d6dSChristoph Hellwig __le64 **list = iod_list(req); 56557dacad5SJay Sternberg dma_addr_t prp_dma; 56657dacad5SJay Sternberg int nprps, i; 56757dacad5SJay Sternberg 56857dacad5SJay Sternberg length -= (page_size - offset); 56957dacad5SJay Sternberg if (length <= 0) 57069d2b571SChristoph Hellwig return true; 57157dacad5SJay Sternberg 57257dacad5SJay Sternberg dma_len -= (page_size - offset); 57357dacad5SJay Sternberg if (dma_len) { 57457dacad5SJay Sternberg dma_addr += (page_size - offset); 57557dacad5SJay Sternberg } else { 57657dacad5SJay Sternberg sg = sg_next(sg); 57757dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 57857dacad5SJay Sternberg dma_len = sg_dma_len(sg); 57957dacad5SJay Sternberg } 58057dacad5SJay Sternberg 58157dacad5SJay Sternberg if (length <= page_size) { 58257dacad5SJay Sternberg iod->first_dma = dma_addr; 58369d2b571SChristoph Hellwig return true; 58457dacad5SJay Sternberg } 58557dacad5SJay Sternberg 58657dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 58757dacad5SJay Sternberg if (nprps <= (256 / 8)) { 58857dacad5SJay Sternberg pool = dev->prp_small_pool; 58957dacad5SJay Sternberg iod->npages = 0; 59057dacad5SJay Sternberg } else { 59157dacad5SJay Sternberg pool = dev->prp_page_pool; 59257dacad5SJay Sternberg iod->npages = 1; 59357dacad5SJay Sternberg } 59457dacad5SJay Sternberg 59569d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 59657dacad5SJay Sternberg if (!prp_list) { 59757dacad5SJay Sternberg iod->first_dma = dma_addr; 59857dacad5SJay Sternberg iod->npages = -1; 59969d2b571SChristoph Hellwig return false; 60057dacad5SJay Sternberg } 60157dacad5SJay Sternberg list[0] = prp_list; 60257dacad5SJay Sternberg iod->first_dma = prp_dma; 60357dacad5SJay Sternberg i = 0; 60457dacad5SJay Sternberg for (;;) { 60557dacad5SJay Sternberg if (i == page_size >> 3) { 60657dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 60769d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 60857dacad5SJay Sternberg if (!prp_list) 60969d2b571SChristoph Hellwig return false; 61057dacad5SJay Sternberg list[iod->npages++] = prp_list; 61157dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 61257dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 61357dacad5SJay Sternberg i = 1; 61457dacad5SJay Sternberg } 61557dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 61657dacad5SJay Sternberg dma_len -= page_size; 61757dacad5SJay Sternberg dma_addr += page_size; 61857dacad5SJay Sternberg length -= page_size; 61957dacad5SJay Sternberg if (length <= 0) 62057dacad5SJay Sternberg break; 62157dacad5SJay Sternberg if (dma_len > 0) 62257dacad5SJay Sternberg continue; 62357dacad5SJay Sternberg BUG_ON(dma_len < 0); 62457dacad5SJay Sternberg sg = sg_next(sg); 62557dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 62657dacad5SJay Sternberg dma_len = sg_dma_len(sg); 62757dacad5SJay Sternberg } 62857dacad5SJay Sternberg 62969d2b571SChristoph Hellwig return true; 63057dacad5SJay Sternberg } 63157dacad5SJay Sternberg 632fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 633b131c61dSChristoph Hellwig struct nvme_command *cmnd) 63457dacad5SJay Sternberg { 635f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 636ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 637ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 638ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 639fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 64057dacad5SJay Sternberg 641f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 642ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 643ba1ca37eSChristoph Hellwig if (!iod->nents) 644ba1ca37eSChristoph Hellwig goto out; 645ba1ca37eSChristoph Hellwig 646fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 6472b6b535dSMauricio Faria de Oliveira if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir, 6482b6b535dSMauricio Faria de Oliveira DMA_ATTR_NO_WARN)) 649ba1ca37eSChristoph Hellwig goto out; 650ba1ca37eSChristoph Hellwig 651b131c61dSChristoph Hellwig if (!nvme_setup_prps(dev, req)) 652ba1ca37eSChristoph Hellwig goto out_unmap; 653ba1ca37eSChristoph Hellwig 654fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 655ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 656ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 657ba1ca37eSChristoph Hellwig goto out_unmap; 658ba1ca37eSChristoph Hellwig 659bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 660bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 661ba1ca37eSChristoph Hellwig goto out_unmap; 662ba1ca37eSChristoph Hellwig 663ba1ca37eSChristoph Hellwig if (rq_data_dir(req)) 664ba1ca37eSChristoph Hellwig nvme_dif_remap(req, nvme_dif_prep); 665ba1ca37eSChristoph Hellwig 666bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 667ba1ca37eSChristoph Hellwig goto out_unmap; 66857dacad5SJay Sternberg } 66957dacad5SJay Sternberg 670eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 671eb793e2cSChristoph Hellwig cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma); 672ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) 673bf684057SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 674fc17b653SChristoph Hellwig return BLK_STS_OK; 675ba1ca37eSChristoph Hellwig 676ba1ca37eSChristoph Hellwig out_unmap: 677ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 678ba1ca37eSChristoph Hellwig out: 679ba1ca37eSChristoph Hellwig return ret; 68057dacad5SJay Sternberg } 68157dacad5SJay Sternberg 682f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 683d4f6c3abSChristoph Hellwig { 684f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 685d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 686d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 687d4f6c3abSChristoph Hellwig 688d4f6c3abSChristoph Hellwig if (iod->nents) { 689d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 690d4f6c3abSChristoph Hellwig if (blk_integrity_rq(req)) { 691d4f6c3abSChristoph Hellwig if (!rq_data_dir(req)) 692d4f6c3abSChristoph Hellwig nvme_dif_remap(req, nvme_dif_complete); 693bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 694d4f6c3abSChristoph Hellwig } 695d4f6c3abSChristoph Hellwig } 696d4f6c3abSChristoph Hellwig 697f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 698f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 69957dacad5SJay Sternberg } 70057dacad5SJay Sternberg 70157dacad5SJay Sternberg /* 70257dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 70357dacad5SJay Sternberg */ 704fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 70557dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 70657dacad5SJay Sternberg { 70757dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 70857dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 70957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 71057dacad5SJay Sternberg struct request *req = bd->rq; 711ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 712fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_OK; 71357dacad5SJay Sternberg 71457dacad5SJay Sternberg /* 71557dacad5SJay Sternberg * If formated with metadata, require the block layer provide a buffer 71657dacad5SJay Sternberg * unless this namespace is formated such that the metadata can be 71757dacad5SJay Sternberg * stripped/generated by the controller with PRACT=1. 71857dacad5SJay Sternberg */ 71957dacad5SJay Sternberg if (ns && ns->ms && !blk_integrity_rq(req)) { 72057dacad5SJay Sternberg if (!(ns->pi_type && ns->ms == 8) && 721fc17b653SChristoph Hellwig !blk_rq_is_passthrough(req)) 722fc17b653SChristoph Hellwig return BLK_STS_NOTSUPP; 72357dacad5SJay Sternberg } 72457dacad5SJay Sternberg 725f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 726fc17b653SChristoph Hellwig if (ret) 727f4800d6dSChristoph Hellwig return ret; 72857dacad5SJay Sternberg 729b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 730fc17b653SChristoph Hellwig if (ret) 731f9d03f96SChristoph Hellwig goto out_free_cmd; 73257dacad5SJay Sternberg 733fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 734b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 735fc17b653SChristoph Hellwig if (ret) 736f9d03f96SChristoph Hellwig goto out_cleanup_iod; 737fc17b653SChristoph Hellwig } 738ba1ca37eSChristoph Hellwig 739aae239e1SChristoph Hellwig blk_mq_start_request(req); 740ba1ca37eSChristoph Hellwig 741ba1ca37eSChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 742ae1fba20SKeith Busch if (unlikely(nvmeq->cq_vector < 0)) { 743fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 744ae1fba20SKeith Busch spin_unlock_irq(&nvmeq->q_lock); 745f9d03f96SChristoph Hellwig goto out_cleanup_iod; 746ae1fba20SKeith Busch } 747ba1ca37eSChristoph Hellwig __nvme_submit_cmd(nvmeq, &cmnd); 74857dacad5SJay Sternberg nvme_process_cq(nvmeq); 74957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 750fc17b653SChristoph Hellwig return BLK_STS_OK; 751f9d03f96SChristoph Hellwig out_cleanup_iod: 752f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 753f9d03f96SChristoph Hellwig out_free_cmd: 754f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 755ba1ca37eSChristoph Hellwig return ret; 75657dacad5SJay Sternberg } 75757dacad5SJay Sternberg 75877f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 759eee417b0SChristoph Hellwig { 760f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 761eee417b0SChristoph Hellwig 76277f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 76377f02a7aSChristoph Hellwig nvme_complete_rq(req); 76457dacad5SJay Sternberg } 76557dacad5SJay Sternberg 766d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 767d783e0bdSMarta Rybczynska static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head, 768d783e0bdSMarta Rybczynska u16 phase) 769d783e0bdSMarta Rybczynska { 770d783e0bdSMarta Rybczynska return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase; 771d783e0bdSMarta Rybczynska } 772d783e0bdSMarta Rybczynska 773a0fa9647SJens Axboe static void __nvme_process_cq(struct nvme_queue *nvmeq, unsigned int *tag) 77457dacad5SJay Sternberg { 77557dacad5SJay Sternberg u16 head, phase; 77657dacad5SJay Sternberg 77757dacad5SJay Sternberg head = nvmeq->cq_head; 77857dacad5SJay Sternberg phase = nvmeq->cq_phase; 77957dacad5SJay Sternberg 780d783e0bdSMarta Rybczynska while (nvme_cqe_valid(nvmeq, head, phase)) { 78157dacad5SJay Sternberg struct nvme_completion cqe = nvmeq->cqes[head]; 782eee417b0SChristoph Hellwig struct request *req; 783adf68f21SChristoph Hellwig 78457dacad5SJay Sternberg if (++head == nvmeq->q_depth) { 78557dacad5SJay Sternberg head = 0; 78657dacad5SJay Sternberg phase = !phase; 78757dacad5SJay Sternberg } 788adf68f21SChristoph Hellwig 789a0fa9647SJens Axboe if (tag && *tag == cqe.command_id) 790a0fa9647SJens Axboe *tag = -1; 791adf68f21SChristoph Hellwig 792aae239e1SChristoph Hellwig if (unlikely(cqe.command_id >= nvmeq->q_depth)) { 7931b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 794aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 795aae239e1SChristoph Hellwig cqe.command_id, le16_to_cpu(cqe.sq_id)); 796aae239e1SChristoph Hellwig continue; 797aae239e1SChristoph Hellwig } 798aae239e1SChristoph Hellwig 799adf68f21SChristoph Hellwig /* 800adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 801adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 802adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 803adf68f21SChristoph Hellwig * for them but rather special case them here. 804adf68f21SChristoph Hellwig */ 805adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 806adf68f21SChristoph Hellwig cqe.command_id >= NVME_AQ_BLKMQ_DEPTH)) { 8077bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 8087bf58533SChristoph Hellwig cqe.status, &cqe.result); 809adf68f21SChristoph Hellwig continue; 810adf68f21SChristoph Hellwig } 811adf68f21SChristoph Hellwig 812eee417b0SChristoph Hellwig req = blk_mq_tag_to_rq(*nvmeq->tags, cqe.command_id); 81327fa9bc5SChristoph Hellwig nvme_end_request(req, cqe.status, cqe.result); 81457dacad5SJay Sternberg } 81557dacad5SJay Sternberg 81657dacad5SJay Sternberg if (head == nvmeq->cq_head && phase == nvmeq->cq_phase) 817a0fa9647SJens Axboe return; 81857dacad5SJay Sternberg 819604e8c8dSKeith Busch if (likely(nvmeq->cq_vector >= 0)) 820f9f38e33SHelen Koike if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 821f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei)) 82257dacad5SJay Sternberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 82357dacad5SJay Sternberg nvmeq->cq_head = head; 82457dacad5SJay Sternberg nvmeq->cq_phase = phase; 82557dacad5SJay Sternberg 82657dacad5SJay Sternberg nvmeq->cqe_seen = 1; 827a0fa9647SJens Axboe } 828a0fa9647SJens Axboe 829a0fa9647SJens Axboe static void nvme_process_cq(struct nvme_queue *nvmeq) 830a0fa9647SJens Axboe { 831a0fa9647SJens Axboe __nvme_process_cq(nvmeq, NULL); 83257dacad5SJay Sternberg } 83357dacad5SJay Sternberg 83457dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 83557dacad5SJay Sternberg { 83657dacad5SJay Sternberg irqreturn_t result; 83757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 83857dacad5SJay Sternberg spin_lock(&nvmeq->q_lock); 83957dacad5SJay Sternberg nvme_process_cq(nvmeq); 84057dacad5SJay Sternberg result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE; 84157dacad5SJay Sternberg nvmeq->cqe_seen = 0; 84257dacad5SJay Sternberg spin_unlock(&nvmeq->q_lock); 84357dacad5SJay Sternberg return result; 84457dacad5SJay Sternberg } 84557dacad5SJay Sternberg 84657dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 84757dacad5SJay Sternberg { 84857dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 849d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) 85057dacad5SJay Sternberg return IRQ_WAKE_THREAD; 851d783e0bdSMarta Rybczynska return IRQ_NONE; 85257dacad5SJay Sternberg } 85357dacad5SJay Sternberg 8547776db1cSKeith Busch static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag) 855a0fa9647SJens Axboe { 856d783e0bdSMarta Rybczynska if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) { 857a0fa9647SJens Axboe spin_lock_irq(&nvmeq->q_lock); 858a0fa9647SJens Axboe __nvme_process_cq(nvmeq, &tag); 859a0fa9647SJens Axboe spin_unlock_irq(&nvmeq->q_lock); 860a0fa9647SJens Axboe 861a0fa9647SJens Axboe if (tag == -1) 862a0fa9647SJens Axboe return 1; 863a0fa9647SJens Axboe } 864a0fa9647SJens Axboe 865a0fa9647SJens Axboe return 0; 866a0fa9647SJens Axboe } 867a0fa9647SJens Axboe 8687776db1cSKeith Busch static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag) 8697776db1cSKeith Busch { 8707776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 8717776db1cSKeith Busch 8727776db1cSKeith Busch return __nvme_poll(nvmeq, tag); 8737776db1cSKeith Busch } 8747776db1cSKeith Busch 875f866fc42SChristoph Hellwig static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx) 87657dacad5SJay Sternberg { 877f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 8789396dec9SChristoph Hellwig struct nvme_queue *nvmeq = dev->queues[0]; 87957dacad5SJay Sternberg struct nvme_command c; 88057dacad5SJay Sternberg 88157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 88257dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 883f866fc42SChristoph Hellwig c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx; 88457dacad5SJay Sternberg 8859396dec9SChristoph Hellwig spin_lock_irq(&nvmeq->q_lock); 8869396dec9SChristoph Hellwig __nvme_submit_cmd(nvmeq, &c); 8879396dec9SChristoph Hellwig spin_unlock_irq(&nvmeq->q_lock); 88857dacad5SJay Sternberg } 88957dacad5SJay Sternberg 89057dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 89157dacad5SJay Sternberg { 89257dacad5SJay Sternberg struct nvme_command c; 89357dacad5SJay Sternberg 89457dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 89557dacad5SJay Sternberg c.delete_queue.opcode = opcode; 89657dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 89757dacad5SJay Sternberg 8981c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 89957dacad5SJay Sternberg } 90057dacad5SJay Sternberg 90157dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 90257dacad5SJay Sternberg struct nvme_queue *nvmeq) 90357dacad5SJay Sternberg { 90457dacad5SJay Sternberg struct nvme_command c; 90557dacad5SJay Sternberg int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED; 90657dacad5SJay Sternberg 90757dacad5SJay Sternberg /* 90857dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 90957dacad5SJay Sternberg * is attached to the request. 91057dacad5SJay Sternberg */ 91157dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 91257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 91357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 91457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 91557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 91657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 91757dacad5SJay Sternberg c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector); 91857dacad5SJay Sternberg 9191c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 92057dacad5SJay Sternberg } 92157dacad5SJay Sternberg 92257dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 92357dacad5SJay Sternberg struct nvme_queue *nvmeq) 92457dacad5SJay Sternberg { 92557dacad5SJay Sternberg struct nvme_command c; 92681c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 92757dacad5SJay Sternberg 92857dacad5SJay Sternberg /* 92957dacad5SJay Sternberg * Note: we (ab)use the fact the the prp fields survive if no data 93057dacad5SJay Sternberg * is attached to the request. 93157dacad5SJay Sternberg */ 93257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 93357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 93457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 93557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 93657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 93757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 93857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 93957dacad5SJay Sternberg 9401c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 94157dacad5SJay Sternberg } 94257dacad5SJay Sternberg 94357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 94457dacad5SJay Sternberg { 94557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 94657dacad5SJay Sternberg } 94757dacad5SJay Sternberg 94857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 94957dacad5SJay Sternberg { 95057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 95157dacad5SJay Sternberg } 95257dacad5SJay Sternberg 9532a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 95457dacad5SJay Sternberg { 955f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 956f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 95757dacad5SJay Sternberg 95827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 95927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 960e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 961e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 96257dacad5SJay Sternberg } 96357dacad5SJay Sternberg 96431c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 96557dacad5SJay Sternberg { 966f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 967f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 96857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 96957dacad5SJay Sternberg struct request *abort_req; 97057dacad5SJay Sternberg struct nvme_command cmd; 97157dacad5SJay Sternberg 97231c7c7d2SChristoph Hellwig /* 9737776db1cSKeith Busch * Did we miss an interrupt? 9747776db1cSKeith Busch */ 9757776db1cSKeith Busch if (__nvme_poll(nvmeq, req->tag)) { 9767776db1cSKeith Busch dev_warn(dev->ctrl.device, 9777776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 9787776db1cSKeith Busch req->tag, nvmeq->qid); 9797776db1cSKeith Busch return BLK_EH_HANDLED; 9807776db1cSKeith Busch } 9817776db1cSKeith Busch 9827776db1cSKeith Busch /* 983fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 984fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 985fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 986fd634f41SChristoph Hellwig * shutdown, so we return BLK_EH_HANDLED. 987fd634f41SChristoph Hellwig */ 988bb8d261eSChristoph Hellwig if (dev->ctrl.state == NVME_CTRL_RESETTING) { 9891b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 990fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 991fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 992a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 99327fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 994fd634f41SChristoph Hellwig return BLK_EH_HANDLED; 995fd634f41SChristoph Hellwig } 996fd634f41SChristoph Hellwig 997fd634f41SChristoph Hellwig /* 998e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 999e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1000e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 100131c7c7d2SChristoph Hellwig */ 1002f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 10031b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 100457dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 100557dacad5SJay Sternberg req->tag, nvmeq->qid); 1006a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1007c5f6ce97SKeith Busch nvme_reset(dev); 1008e1569a16SKeith Busch 1009e1569a16SKeith Busch /* 1010e1569a16SKeith Busch * Mark the request as handled, since the inline shutdown 1011e1569a16SKeith Busch * forces all outstanding requests to complete. 1012e1569a16SKeith Busch */ 101327fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1014e1569a16SKeith Busch return BLK_EH_HANDLED; 101557dacad5SJay Sternberg } 101657dacad5SJay Sternberg 1017e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1018e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1019e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1020e7a2a87dSChristoph Hellwig } 10217bf7d778SKeith Busch iod->aborted = 1; 102257dacad5SJay Sternberg 102357dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 102457dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 102557dacad5SJay Sternberg cmd.abort.cid = req->tag; 102657dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 102757dacad5SJay Sternberg 10281b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 10291b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 103057dacad5SJay Sternberg req->tag, nvmeq->qid); 1031e7a2a87dSChristoph Hellwig 1032e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1033eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 10346bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 10356bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 103631c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 103757dacad5SJay Sternberg } 103857dacad5SJay Sternberg 1039e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1040e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1041e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 104257dacad5SJay Sternberg 104357dacad5SJay Sternberg /* 104457dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 104557dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 104657dacad5SJay Sternberg * as the device then is in a faulty state. 104757dacad5SJay Sternberg */ 104857dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 104957dacad5SJay Sternberg } 105057dacad5SJay Sternberg 105157dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 105257dacad5SJay Sternberg { 105357dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 105457dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 105557dacad5SJay Sternberg if (nvmeq->sq_cmds) 105657dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 105757dacad5SJay Sternberg nvmeq->sq_cmds, nvmeq->sq_dma_addr); 105857dacad5SJay Sternberg kfree(nvmeq); 105957dacad5SJay Sternberg } 106057dacad5SJay Sternberg 106157dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 106257dacad5SJay Sternberg { 106357dacad5SJay Sternberg int i; 106457dacad5SJay Sternberg 106557dacad5SJay Sternberg for (i = dev->queue_count - 1; i >= lowest; i--) { 106657dacad5SJay Sternberg struct nvme_queue *nvmeq = dev->queues[i]; 106757dacad5SJay Sternberg dev->queue_count--; 106857dacad5SJay Sternberg dev->queues[i] = NULL; 106957dacad5SJay Sternberg nvme_free_queue(nvmeq); 107057dacad5SJay Sternberg } 107157dacad5SJay Sternberg } 107257dacad5SJay Sternberg 107357dacad5SJay Sternberg /** 107457dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 107557dacad5SJay Sternberg * @nvmeq - queue to suspend 107657dacad5SJay Sternberg */ 107757dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 107857dacad5SJay Sternberg { 107957dacad5SJay Sternberg int vector; 108057dacad5SJay Sternberg 108157dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 108257dacad5SJay Sternberg if (nvmeq->cq_vector == -1) { 108357dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 108457dacad5SJay Sternberg return 1; 108557dacad5SJay Sternberg } 10860ff199cbSChristoph Hellwig vector = nvmeq->cq_vector; 108757dacad5SJay Sternberg nvmeq->dev->online_queues--; 108857dacad5SJay Sternberg nvmeq->cq_vector = -1; 108957dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 109057dacad5SJay Sternberg 10911c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 109225646264SKeith Busch blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q); 109357dacad5SJay Sternberg 10940ff199cbSChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq); 109557dacad5SJay Sternberg 109657dacad5SJay Sternberg return 0; 109757dacad5SJay Sternberg } 109857dacad5SJay Sternberg 1099a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 110057dacad5SJay Sternberg { 1101a5cdb68cSKeith Busch struct nvme_queue *nvmeq = dev->queues[0]; 110257dacad5SJay Sternberg 110357dacad5SJay Sternberg if (!nvmeq) 110457dacad5SJay Sternberg return; 110557dacad5SJay Sternberg if (nvme_suspend_queue(nvmeq)) 110657dacad5SJay Sternberg return; 110757dacad5SJay Sternberg 1108a5cdb68cSKeith Busch if (shutdown) 1109a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1110a5cdb68cSKeith Busch else 1111a5cdb68cSKeith Busch nvme_disable_ctrl(&dev->ctrl, lo_hi_readq( 1112a5cdb68cSKeith Busch dev->bar + NVME_REG_CAP)); 111357dacad5SJay Sternberg 111457dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 111557dacad5SJay Sternberg nvme_process_cq(nvmeq); 111657dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 111757dacad5SJay Sternberg } 111857dacad5SJay Sternberg 111957dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 112057dacad5SJay Sternberg int entry_size) 112157dacad5SJay Sternberg { 112257dacad5SJay Sternberg int q_depth = dev->q_depth; 11235fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 11245fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 112557dacad5SJay Sternberg 112657dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 112757dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 11285fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 112957dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 113057dacad5SJay Sternberg 113157dacad5SJay Sternberg /* 113257dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 113357dacad5SJay Sternberg * would be better to map queues in system memory with the 113457dacad5SJay Sternberg * original depth 113557dacad5SJay Sternberg */ 113657dacad5SJay Sternberg if (q_depth < 64) 113757dacad5SJay Sternberg return -ENOMEM; 113857dacad5SJay Sternberg } 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg return q_depth; 114157dacad5SJay Sternberg } 114257dacad5SJay Sternberg 114357dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 114457dacad5SJay Sternberg int qid, int depth) 114557dacad5SJay Sternberg { 114657dacad5SJay Sternberg if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) { 11475fd4ce1bSChristoph Hellwig unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth), 11485fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 114957dacad5SJay Sternberg nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset; 115057dacad5SJay Sternberg nvmeq->sq_cmds_io = dev->cmb + offset; 115157dacad5SJay Sternberg } else { 115257dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 115357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 115457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 115557dacad5SJay Sternberg return -ENOMEM; 115657dacad5SJay Sternberg } 115757dacad5SJay Sternberg 115857dacad5SJay Sternberg return 0; 115957dacad5SJay Sternberg } 116057dacad5SJay Sternberg 116157dacad5SJay Sternberg static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid, 1162d3af3ecdSShaohua Li int depth, int node) 116357dacad5SJay Sternberg { 1164d3af3ecdSShaohua Li struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL, 1165d3af3ecdSShaohua Li node); 116657dacad5SJay Sternberg if (!nvmeq) 116757dacad5SJay Sternberg return NULL; 116857dacad5SJay Sternberg 116957dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 117057dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 117157dacad5SJay Sternberg if (!nvmeq->cqes) 117257dacad5SJay Sternberg goto free_nvmeq; 117357dacad5SJay Sternberg 117457dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 117557dacad5SJay Sternberg goto free_cqdma; 117657dacad5SJay Sternberg 117757dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 117857dacad5SJay Sternberg nvmeq->dev = dev; 117957dacad5SJay Sternberg spin_lock_init(&nvmeq->q_lock); 118057dacad5SJay Sternberg nvmeq->cq_head = 0; 118157dacad5SJay Sternberg nvmeq->cq_phase = 1; 118257dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 118357dacad5SJay Sternberg nvmeq->q_depth = depth; 118457dacad5SJay Sternberg nvmeq->qid = qid; 118557dacad5SJay Sternberg nvmeq->cq_vector = -1; 118657dacad5SJay Sternberg dev->queues[qid] = nvmeq; 118757dacad5SJay Sternberg dev->queue_count++; 118857dacad5SJay Sternberg 118957dacad5SJay Sternberg return nvmeq; 119057dacad5SJay Sternberg 119157dacad5SJay Sternberg free_cqdma: 119257dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 119357dacad5SJay Sternberg nvmeq->cq_dma_addr); 119457dacad5SJay Sternberg free_nvmeq: 119557dacad5SJay Sternberg kfree(nvmeq); 119657dacad5SJay Sternberg return NULL; 119757dacad5SJay Sternberg } 119857dacad5SJay Sternberg 1199dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 120057dacad5SJay Sternberg { 12010ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 12020ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 12030ff199cbSChristoph Hellwig 12040ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 12050ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 12060ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12070ff199cbSChristoph Hellwig } else { 12080ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 12090ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 12100ff199cbSChristoph Hellwig } 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 121457dacad5SJay Sternberg { 121557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 121657dacad5SJay Sternberg 121757dacad5SJay Sternberg spin_lock_irq(&nvmeq->q_lock); 121857dacad5SJay Sternberg nvmeq->sq_tail = 0; 121957dacad5SJay Sternberg nvmeq->cq_head = 0; 122057dacad5SJay Sternberg nvmeq->cq_phase = 1; 122157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 122257dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1223f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 122457dacad5SJay Sternberg dev->online_queues++; 122557dacad5SJay Sternberg spin_unlock_irq(&nvmeq->q_lock); 122657dacad5SJay Sternberg } 122757dacad5SJay Sternberg 122857dacad5SJay Sternberg static int nvme_create_queue(struct nvme_queue *nvmeq, int qid) 122957dacad5SJay Sternberg { 123057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 123157dacad5SJay Sternberg int result; 123257dacad5SJay Sternberg 123357dacad5SJay Sternberg nvmeq->cq_vector = qid - 1; 123457dacad5SJay Sternberg result = adapter_alloc_cq(dev, qid, nvmeq); 123557dacad5SJay Sternberg if (result < 0) 123657dacad5SJay Sternberg return result; 123757dacad5SJay Sternberg 123857dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 123957dacad5SJay Sternberg if (result < 0) 124057dacad5SJay Sternberg goto release_cq; 124157dacad5SJay Sternberg 1242dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 124357dacad5SJay Sternberg if (result < 0) 124457dacad5SJay Sternberg goto release_sq; 124557dacad5SJay Sternberg 124657dacad5SJay Sternberg nvme_init_queue(nvmeq, qid); 124757dacad5SJay Sternberg return result; 124857dacad5SJay Sternberg 124957dacad5SJay Sternberg release_sq: 125057dacad5SJay Sternberg adapter_delete_sq(dev, qid); 125157dacad5SJay Sternberg release_cq: 125257dacad5SJay Sternberg adapter_delete_cq(dev, qid); 125357dacad5SJay Sternberg return result; 125457dacad5SJay Sternberg } 125557dacad5SJay Sternberg 1256f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 125757dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 125877f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 125957dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 126057dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 126157dacad5SJay Sternberg .init_request = nvme_admin_init_request, 126257dacad5SJay Sternberg .timeout = nvme_timeout, 126357dacad5SJay Sternberg }; 126457dacad5SJay Sternberg 1265f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 126657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 126777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 126857dacad5SJay Sternberg .init_hctx = nvme_init_hctx, 126957dacad5SJay Sternberg .init_request = nvme_init_request, 1270dca51e78SChristoph Hellwig .map_queues = nvme_pci_map_queues, 127157dacad5SJay Sternberg .timeout = nvme_timeout, 1272a0fa9647SJens Axboe .poll = nvme_poll, 127357dacad5SJay Sternberg }; 127457dacad5SJay Sternberg 127557dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 127657dacad5SJay Sternberg { 12771c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 127869d9a99cSKeith Busch /* 127969d9a99cSKeith Busch * If the controller was reset during removal, it's possible 128069d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 128169d9a99cSKeith Busch * queue to flush these to completion. 128269d9a99cSKeith Busch */ 128369d9a99cSKeith Busch blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); 12841c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 128557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 128657dacad5SJay Sternberg } 128757dacad5SJay Sternberg } 128857dacad5SJay Sternberg 128957dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 129057dacad5SJay Sternberg { 12911c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 129257dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 129357dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1294e3e9d50cSKeith Busch 1295e3e9d50cSKeith Busch /* 1296e3e9d50cSKeith Busch * Subtract one to leave an empty queue entry for 'Full Queue' 1297e3e9d50cSKeith Busch * condition. See NVM-Express 1.2 specification, section 4.1.2. 1298e3e9d50cSKeith Busch */ 1299e3e9d50cSKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1; 130057dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 130157dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 130257dacad5SJay Sternberg dev->admin_tagset.cmd_size = nvme_cmd_size(dev); 1303d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 130457dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 130557dacad5SJay Sternberg 130657dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 130757dacad5SJay Sternberg return -ENOMEM; 130857dacad5SJay Sternberg 13091c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 13101c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 131157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 131257dacad5SJay Sternberg return -ENOMEM; 131357dacad5SJay Sternberg } 13141c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 131557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 13161c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 131757dacad5SJay Sternberg return -ENODEV; 131857dacad5SJay Sternberg } 131957dacad5SJay Sternberg } else 132025646264SKeith Busch blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true); 132157dacad5SJay Sternberg 132257dacad5SJay Sternberg return 0; 132357dacad5SJay Sternberg } 132457dacad5SJay Sternberg 132557dacad5SJay Sternberg static int nvme_configure_admin_queue(struct nvme_dev *dev) 132657dacad5SJay Sternberg { 132757dacad5SJay Sternberg int result; 132857dacad5SJay Sternberg u32 aqa; 13297a67cbeaSChristoph Hellwig u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 133057dacad5SJay Sternberg struct nvme_queue *nvmeq; 133157dacad5SJay Sternberg 13328ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 133357dacad5SJay Sternberg NVME_CAP_NSSRC(cap) : 0; 133457dacad5SJay Sternberg 13357a67cbeaSChristoph Hellwig if (dev->subsystem && 13367a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 13377a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 133857dacad5SJay Sternberg 13395fd4ce1bSChristoph Hellwig result = nvme_disable_ctrl(&dev->ctrl, cap); 134057dacad5SJay Sternberg if (result < 0) 134157dacad5SJay Sternberg return result; 134257dacad5SJay Sternberg 134357dacad5SJay Sternberg nvmeq = dev->queues[0]; 134457dacad5SJay Sternberg if (!nvmeq) { 1345d3af3ecdSShaohua Li nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH, 1346d3af3ecdSShaohua Li dev_to_node(dev->dev)); 134757dacad5SJay Sternberg if (!nvmeq) 134857dacad5SJay Sternberg return -ENOMEM; 134957dacad5SJay Sternberg } 135057dacad5SJay Sternberg 135157dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 135257dacad5SJay Sternberg aqa |= aqa << 16; 135357dacad5SJay Sternberg 13547a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 13557a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 13567a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 135757dacad5SJay Sternberg 13585fd4ce1bSChristoph Hellwig result = nvme_enable_ctrl(&dev->ctrl, cap); 135957dacad5SJay Sternberg if (result) 1360d4875622SKeith Busch return result; 136157dacad5SJay Sternberg 136257dacad5SJay Sternberg nvmeq->cq_vector = 0; 1363dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 136457dacad5SJay Sternberg if (result) { 136557dacad5SJay Sternberg nvmeq->cq_vector = -1; 1366d4875622SKeith Busch return result; 136757dacad5SJay Sternberg } 136857dacad5SJay Sternberg 136957dacad5SJay Sternberg return result; 137057dacad5SJay Sternberg } 137157dacad5SJay Sternberg 1372c875a709SGuilherme G. Piccoli static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1373c875a709SGuilherme G. Piccoli { 1374c875a709SGuilherme G. Piccoli 1375c875a709SGuilherme G. Piccoli /* If true, indicates loss of adapter communication, possibly by a 1376c875a709SGuilherme G. Piccoli * NVMe Subsystem reset. 1377c875a709SGuilherme G. Piccoli */ 1378c875a709SGuilherme G. Piccoli bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1379c875a709SGuilherme G. Piccoli 1380c875a709SGuilherme G. Piccoli /* If there is a reset ongoing, we shouldn't reset again. */ 138182b057caSRakesh Pandit if (dev->ctrl.state == NVME_CTRL_RESETTING) 1382c875a709SGuilherme G. Piccoli return false; 1383c875a709SGuilherme G. Piccoli 1384c875a709SGuilherme G. Piccoli /* We shouldn't reset unless the controller is on fatal error state 1385c875a709SGuilherme G. Piccoli * _or_ if we lost the communication with it. 1386c875a709SGuilherme G. Piccoli */ 1387c875a709SGuilherme G. Piccoli if (!(csts & NVME_CSTS_CFS) && !nssro) 1388c875a709SGuilherme G. Piccoli return false; 1389c875a709SGuilherme G. Piccoli 1390c875a709SGuilherme G. Piccoli /* If PCI error recovery process is happening, we cannot reset or 1391c875a709SGuilherme G. Piccoli * the recovery mechanism will surely fail. 1392c875a709SGuilherme G. Piccoli */ 1393c875a709SGuilherme G. Piccoli if (pci_channel_offline(to_pci_dev(dev->dev))) 1394c875a709SGuilherme G. Piccoli return false; 1395c875a709SGuilherme G. Piccoli 1396c875a709SGuilherme G. Piccoli return true; 1397c875a709SGuilherme G. Piccoli } 1398c875a709SGuilherme G. Piccoli 1399d2a61918SAndy Lutomirski static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1400d2a61918SAndy Lutomirski { 1401d2a61918SAndy Lutomirski /* Read a config register to help see what died. */ 1402d2a61918SAndy Lutomirski u16 pci_status; 1403d2a61918SAndy Lutomirski int result; 1404d2a61918SAndy Lutomirski 1405d2a61918SAndy Lutomirski result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1406d2a61918SAndy Lutomirski &pci_status); 1407d2a61918SAndy Lutomirski if (result == PCIBIOS_SUCCESSFUL) 14089bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1409d2a61918SAndy Lutomirski "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1410d2a61918SAndy Lutomirski csts, pci_status); 1411d2a61918SAndy Lutomirski else 14129bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1413d2a61918SAndy Lutomirski "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1414d2a61918SAndy Lutomirski csts, result); 1415d2a61918SAndy Lutomirski } 1416d2a61918SAndy Lutomirski 14172d55cd5fSChristoph Hellwig static void nvme_watchdog_timer(unsigned long data) 141857dacad5SJay Sternberg { 14192d55cd5fSChristoph Hellwig struct nvme_dev *dev = (struct nvme_dev *)data; 14207a67cbeaSChristoph Hellwig u32 csts = readl(dev->bar + NVME_REG_CSTS); 142157dacad5SJay Sternberg 1422c875a709SGuilherme G. Piccoli /* Skip controllers under certain specific conditions. */ 1423c875a709SGuilherme G. Piccoli if (nvme_should_reset(dev, csts)) { 1424c5f6ce97SKeith Busch if (!nvme_reset(dev)) 1425d2a61918SAndy Lutomirski nvme_warn_reset(dev, csts); 14262d55cd5fSChristoph Hellwig return; 142757dacad5SJay Sternberg } 142857dacad5SJay Sternberg 14292d55cd5fSChristoph Hellwig mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); 143057dacad5SJay Sternberg } 143157dacad5SJay Sternberg 1432749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 143357dacad5SJay Sternberg { 1434949928c1SKeith Busch unsigned i, max; 1435749941f2SChristoph Hellwig int ret = 0; 143657dacad5SJay Sternberg 1437749941f2SChristoph Hellwig for (i = dev->queue_count; i <= dev->max_qid; i++) { 1438d3af3ecdSShaohua Li /* vector == qid - 1, match nvme_create_queue */ 1439d3af3ecdSShaohua Li if (!nvme_alloc_queue(dev, i, dev->q_depth, 1440d3af3ecdSShaohua Li pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) { 1441749941f2SChristoph Hellwig ret = -ENOMEM; 144257dacad5SJay Sternberg break; 1443749941f2SChristoph Hellwig } 1444749941f2SChristoph Hellwig } 144557dacad5SJay Sternberg 1446949928c1SKeith Busch max = min(dev->max_qid, dev->queue_count - 1); 1447949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 1448749941f2SChristoph Hellwig ret = nvme_create_queue(dev->queues[i], i); 1449d4875622SKeith Busch if (ret) 145057dacad5SJay Sternberg break; 145157dacad5SJay Sternberg } 145257dacad5SJay Sternberg 1453749941f2SChristoph Hellwig /* 1454749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 1455749941f2SChristoph Hellwig * than the desired aount of queues, and even a controller without 1456749941f2SChristoph Hellwig * I/O queues an still be used to issue admin commands. This might 1457749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1458749941f2SChristoph Hellwig */ 1459749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 146057dacad5SJay Sternberg } 146157dacad5SJay Sternberg 1462202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1463202021c1SStephen Bates struct device_attribute *attr, 1464202021c1SStephen Bates char *buf) 1465202021c1SStephen Bates { 1466202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1467202021c1SStephen Bates 1468c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1469202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1470202021c1SStephen Bates } 1471202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1472202021c1SStephen Bates 147357dacad5SJay Sternberg static void __iomem *nvme_map_cmb(struct nvme_dev *dev) 147457dacad5SJay Sternberg { 147557dacad5SJay Sternberg u64 szu, size, offset; 147657dacad5SJay Sternberg resource_size_t bar_size; 147757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 147857dacad5SJay Sternberg void __iomem *cmb; 147957dacad5SJay Sternberg dma_addr_t dma_addr; 148057dacad5SJay Sternberg 14817a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 148257dacad5SJay Sternberg if (!(NVME_CMB_SZ(dev->cmbsz))) 148357dacad5SJay Sternberg return NULL; 1484202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 148557dacad5SJay Sternberg 1486202021c1SStephen Bates if (!use_cmb_sqes) 1487202021c1SStephen Bates return NULL; 148857dacad5SJay Sternberg 148957dacad5SJay Sternberg szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz)); 149057dacad5SJay Sternberg size = szu * NVME_CMB_SZ(dev->cmbsz); 1491202021c1SStephen Bates offset = szu * NVME_CMB_OFST(dev->cmbloc); 1492202021c1SStephen Bates bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc)); 149357dacad5SJay Sternberg 149457dacad5SJay Sternberg if (offset > bar_size) 149557dacad5SJay Sternberg return NULL; 149657dacad5SJay Sternberg 149757dacad5SJay Sternberg /* 149857dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 149957dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 150057dacad5SJay Sternberg * the reported size of the BAR 150157dacad5SJay Sternberg */ 150257dacad5SJay Sternberg if (size > bar_size - offset) 150357dacad5SJay Sternberg size = bar_size - offset; 150457dacad5SJay Sternberg 1505202021c1SStephen Bates dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset; 150657dacad5SJay Sternberg cmb = ioremap_wc(dma_addr, size); 150757dacad5SJay Sternberg if (!cmb) 150857dacad5SJay Sternberg return NULL; 150957dacad5SJay Sternberg 151057dacad5SJay Sternberg dev->cmb_dma_addr = dma_addr; 151157dacad5SJay Sternberg dev->cmb_size = size; 151257dacad5SJay Sternberg return cmb; 151357dacad5SJay Sternberg } 151457dacad5SJay Sternberg 151557dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 151657dacad5SJay Sternberg { 151757dacad5SJay Sternberg if (dev->cmb) { 151857dacad5SJay Sternberg iounmap(dev->cmb); 151957dacad5SJay Sternberg dev->cmb = NULL; 1520f63572dfSJon Derrick if (dev->cmbsz) { 1521f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1522f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 1523f63572dfSJon Derrick dev->cmbsz = 0; 1524f63572dfSJon Derrick } 152557dacad5SJay Sternberg } 152657dacad5SJay Sternberg } 152757dacad5SJay Sternberg 152887ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 152987ad72a5SChristoph Hellwig { 153087ad72a5SChristoph Hellwig size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs); 153187ad72a5SChristoph Hellwig struct nvme_command c; 153287ad72a5SChristoph Hellwig u64 dma_addr; 153387ad72a5SChristoph Hellwig int ret; 153487ad72a5SChristoph Hellwig 153587ad72a5SChristoph Hellwig dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len, 153687ad72a5SChristoph Hellwig DMA_TO_DEVICE); 153787ad72a5SChristoph Hellwig if (dma_mapping_error(dev->dev, dma_addr)) 153887ad72a5SChristoph Hellwig return -ENOMEM; 153987ad72a5SChristoph Hellwig 154087ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 154187ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 154287ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 154387ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 154487ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 154587ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 154687ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 154787ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 154887ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 154987ad72a5SChristoph Hellwig 155087ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 155187ad72a5SChristoph Hellwig if (ret) { 155287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 155387ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 155487ad72a5SChristoph Hellwig ret, bits); 155587ad72a5SChristoph Hellwig } 155687ad72a5SChristoph Hellwig dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE); 155787ad72a5SChristoph Hellwig return ret; 155887ad72a5SChristoph Hellwig } 155987ad72a5SChristoph Hellwig 156087ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 156187ad72a5SChristoph Hellwig { 156287ad72a5SChristoph Hellwig int i; 156387ad72a5SChristoph Hellwig 156487ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 156587ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 156687ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 156787ad72a5SChristoph Hellwig 156887ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 156987ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 157087ad72a5SChristoph Hellwig } 157187ad72a5SChristoph Hellwig 157287ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 157387ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 157487ad72a5SChristoph Hellwig kfree(dev->host_mem_descs); 157587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 157687ad72a5SChristoph Hellwig } 157787ad72a5SChristoph Hellwig 157887ad72a5SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 157987ad72a5SChristoph Hellwig { 158087ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 158187ad72a5SChristoph Hellwig u32 chunk_size, max_entries, i = 0; 158287ad72a5SChristoph Hellwig void **bufs; 158387ad72a5SChristoph Hellwig u64 size, tmp; 158487ad72a5SChristoph Hellwig 158587ad72a5SChristoph Hellwig /* start big and work our way down */ 158687ad72a5SChristoph Hellwig chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER); 158787ad72a5SChristoph Hellwig retry: 158887ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 158987ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 159087ad72a5SChristoph Hellwig max_entries = tmp; 159187ad72a5SChristoph Hellwig descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL); 159287ad72a5SChristoph Hellwig if (!descs) 159387ad72a5SChristoph Hellwig goto out; 159487ad72a5SChristoph Hellwig 159587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 159687ad72a5SChristoph Hellwig if (!bufs) 159787ad72a5SChristoph Hellwig goto out_free_descs; 159887ad72a5SChristoph Hellwig 159987ad72a5SChristoph Hellwig for (size = 0; size < preferred; size += chunk_size) { 160087ad72a5SChristoph Hellwig u32 len = min_t(u64, chunk_size, preferred - size); 160187ad72a5SChristoph Hellwig dma_addr_t dma_addr; 160287ad72a5SChristoph Hellwig 160387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 160487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 160587ad72a5SChristoph Hellwig if (!bufs[i]) 160687ad72a5SChristoph Hellwig break; 160787ad72a5SChristoph Hellwig 160887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 160987ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 161087ad72a5SChristoph Hellwig i++; 161187ad72a5SChristoph Hellwig } 161287ad72a5SChristoph Hellwig 161387ad72a5SChristoph Hellwig if (!size || (min && size < min)) { 161487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 161587ad72a5SChristoph Hellwig "failed to allocate host memory buffer.\n"); 161687ad72a5SChristoph Hellwig goto out_free_bufs; 161787ad72a5SChristoph Hellwig } 161887ad72a5SChristoph Hellwig 161987ad72a5SChristoph Hellwig dev_info(dev->ctrl.device, 162087ad72a5SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 162187ad72a5SChristoph Hellwig size >> ilog2(SZ_1M)); 162287ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 162387ad72a5SChristoph Hellwig dev->host_mem_size = size; 162487ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 162587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 162687ad72a5SChristoph Hellwig return 0; 162787ad72a5SChristoph Hellwig 162887ad72a5SChristoph Hellwig out_free_bufs: 162987ad72a5SChristoph Hellwig while (--i >= 0) { 163087ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 163187ad72a5SChristoph Hellwig 163287ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 163387ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 163487ad72a5SChristoph Hellwig } 163587ad72a5SChristoph Hellwig 163687ad72a5SChristoph Hellwig kfree(bufs); 163787ad72a5SChristoph Hellwig out_free_descs: 163887ad72a5SChristoph Hellwig kfree(descs); 163987ad72a5SChristoph Hellwig out: 164087ad72a5SChristoph Hellwig /* try a smaller chunk size if we failed early */ 164187ad72a5SChristoph Hellwig if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) { 164287ad72a5SChristoph Hellwig chunk_size /= 2; 164387ad72a5SChristoph Hellwig goto retry; 164487ad72a5SChristoph Hellwig } 164587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 164687ad72a5SChristoph Hellwig return -ENOMEM; 164787ad72a5SChristoph Hellwig } 164887ad72a5SChristoph Hellwig 164987ad72a5SChristoph Hellwig static void nvme_setup_host_mem(struct nvme_dev *dev) 165087ad72a5SChristoph Hellwig { 165187ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 165287ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 165387ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 165487ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 165587ad72a5SChristoph Hellwig 165687ad72a5SChristoph Hellwig preferred = min(preferred, max); 165787ad72a5SChristoph Hellwig if (min > max) { 165887ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 165987ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 166087ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 166187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 166287ad72a5SChristoph Hellwig return; 166387ad72a5SChristoph Hellwig } 166487ad72a5SChristoph Hellwig 166587ad72a5SChristoph Hellwig /* 166687ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 166787ad72a5SChristoph Hellwig */ 166887ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 166987ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 167087ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 167187ad72a5SChristoph Hellwig else 167287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 167387ad72a5SChristoph Hellwig } 167487ad72a5SChristoph Hellwig 167587ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 167687ad72a5SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) 167787ad72a5SChristoph Hellwig return; 167887ad72a5SChristoph Hellwig } 167987ad72a5SChristoph Hellwig 168087ad72a5SChristoph Hellwig if (nvme_set_host_mem(dev, enable_bits)) 168187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 168287ad72a5SChristoph Hellwig } 168387ad72a5SChristoph Hellwig 168457dacad5SJay Sternberg static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 168557dacad5SJay Sternberg { 168657dacad5SJay Sternberg return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride); 168757dacad5SJay Sternberg } 168857dacad5SJay Sternberg 168957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 169057dacad5SJay Sternberg { 169157dacad5SJay Sternberg struct nvme_queue *adminq = dev->queues[0]; 169257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 1693dca51e78SChristoph Hellwig int result, nr_io_queues, size; 169457dacad5SJay Sternberg 16952800b8e7SKeith Busch nr_io_queues = num_online_cpus(); 16969a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 16979a0be7abSChristoph Hellwig if (result < 0) 169857dacad5SJay Sternberg return result; 16999a0be7abSChristoph Hellwig 1700f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 1701a5229050SKeith Busch return 0; 170257dacad5SJay Sternberg 170357dacad5SJay Sternberg if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) { 170457dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 170557dacad5SJay Sternberg sizeof(struct nvme_command)); 170657dacad5SJay Sternberg if (result > 0) 170757dacad5SJay Sternberg dev->q_depth = result; 170857dacad5SJay Sternberg else 170957dacad5SJay Sternberg nvme_release_cmb(dev); 171057dacad5SJay Sternberg } 171157dacad5SJay Sternberg 171257dacad5SJay Sternberg size = db_bar_size(dev, nr_io_queues); 171357dacad5SJay Sternberg if (size > 8192) { 171457dacad5SJay Sternberg iounmap(dev->bar); 171557dacad5SJay Sternberg do { 171657dacad5SJay Sternberg dev->bar = ioremap(pci_resource_start(pdev, 0), size); 171757dacad5SJay Sternberg if (dev->bar) 171857dacad5SJay Sternberg break; 171957dacad5SJay Sternberg if (!--nr_io_queues) 172057dacad5SJay Sternberg return -ENOMEM; 172157dacad5SJay Sternberg size = db_bar_size(dev, nr_io_queues); 172257dacad5SJay Sternberg } while (1); 17237a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 172457dacad5SJay Sternberg adminq->q_db = dev->dbs; 172557dacad5SJay Sternberg } 172657dacad5SJay Sternberg 172757dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 17280ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 172957dacad5SJay Sternberg 173057dacad5SJay Sternberg /* 173157dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 173257dacad5SJay Sternberg * setting up the full range we need. 173357dacad5SJay Sternberg */ 1734dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 1735dca51e78SChristoph Hellwig nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues, 1736dca51e78SChristoph Hellwig PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY); 1737dca51e78SChristoph Hellwig if (nr_io_queues <= 0) 1738dca51e78SChristoph Hellwig return -EIO; 1739dca51e78SChristoph Hellwig dev->max_qid = nr_io_queues; 174057dacad5SJay Sternberg 174157dacad5SJay Sternberg /* 174257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 174357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 174457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 174557dacad5SJay Sternberg * number of interrupts. 174657dacad5SJay Sternberg */ 174757dacad5SJay Sternberg 1748dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 174957dacad5SJay Sternberg if (result) { 175057dacad5SJay Sternberg adminq->cq_vector = -1; 1751d4875622SKeith Busch return result; 175257dacad5SJay Sternberg } 1753749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 175457dacad5SJay Sternberg } 175557dacad5SJay Sternberg 17562a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 1757db3cbfffSKeith Busch { 1758db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1759db3cbfffSKeith Busch 1760db3cbfffSKeith Busch blk_mq_free_request(req); 1761db3cbfffSKeith Busch complete(&nvmeq->dev->ioq_wait); 1762db3cbfffSKeith Busch } 1763db3cbfffSKeith Busch 17642a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 1765db3cbfffSKeith Busch { 1766db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 1767db3cbfffSKeith Busch 1768db3cbfffSKeith Busch if (!error) { 1769db3cbfffSKeith Busch unsigned long flags; 1770db3cbfffSKeith Busch 17712e39e0f6SMing Lin /* 17722e39e0f6SMing Lin * We might be called with the AQ q_lock held 17732e39e0f6SMing Lin * and the I/O queue q_lock should always 17742e39e0f6SMing Lin * nest inside the AQ one. 17752e39e0f6SMing Lin */ 17762e39e0f6SMing Lin spin_lock_irqsave_nested(&nvmeq->q_lock, flags, 17772e39e0f6SMing Lin SINGLE_DEPTH_NESTING); 1778db3cbfffSKeith Busch nvme_process_cq(nvmeq); 1779db3cbfffSKeith Busch spin_unlock_irqrestore(&nvmeq->q_lock, flags); 1780db3cbfffSKeith Busch } 1781db3cbfffSKeith Busch 1782db3cbfffSKeith Busch nvme_del_queue_end(req, error); 1783db3cbfffSKeith Busch } 1784db3cbfffSKeith Busch 1785db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 1786db3cbfffSKeith Busch { 1787db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 1788db3cbfffSKeith Busch struct request *req; 1789db3cbfffSKeith Busch struct nvme_command cmd; 1790db3cbfffSKeith Busch 1791db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 1792db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 1793db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 1794db3cbfffSKeith Busch 1795eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 1796db3cbfffSKeith Busch if (IS_ERR(req)) 1797db3cbfffSKeith Busch return PTR_ERR(req); 1798db3cbfffSKeith Busch 1799db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 1800db3cbfffSKeith Busch req->end_io_data = nvmeq; 1801db3cbfffSKeith Busch 1802db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 1803db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 1804db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 1805db3cbfffSKeith Busch return 0; 1806db3cbfffSKeith Busch } 1807db3cbfffSKeith Busch 180870659060SKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev, int queues) 1809db3cbfffSKeith Busch { 181070659060SKeith Busch int pass; 1811db3cbfffSKeith Busch unsigned long timeout; 1812db3cbfffSKeith Busch u8 opcode = nvme_admin_delete_sq; 1813db3cbfffSKeith Busch 1814db3cbfffSKeith Busch for (pass = 0; pass < 2; pass++) { 1815014a0d60SKeith Busch int sent = 0, i = queues; 1816db3cbfffSKeith Busch 1817db3cbfffSKeith Busch reinit_completion(&dev->ioq_wait); 1818db3cbfffSKeith Busch retry: 1819db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 1820c21377f8SGabriel Krisman Bertazi for (; i > 0; i--, sent++) 1821c21377f8SGabriel Krisman Bertazi if (nvme_delete_queue(dev->queues[i], opcode)) 1822db3cbfffSKeith Busch break; 1823c21377f8SGabriel Krisman Bertazi 1824db3cbfffSKeith Busch while (sent--) { 1825db3cbfffSKeith Busch timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout); 1826db3cbfffSKeith Busch if (timeout == 0) 1827db3cbfffSKeith Busch return; 1828db3cbfffSKeith Busch if (i) 1829db3cbfffSKeith Busch goto retry; 1830db3cbfffSKeith Busch } 1831db3cbfffSKeith Busch opcode = nvme_admin_delete_cq; 1832db3cbfffSKeith Busch } 1833db3cbfffSKeith Busch } 1834db3cbfffSKeith Busch 183557dacad5SJay Sternberg /* 183657dacad5SJay Sternberg * Return: error value if an error occurred setting up the queues or calling 183757dacad5SJay Sternberg * Identify Device. 0 if these succeeded, even if adding some of the 183857dacad5SJay Sternberg * namespaces failed. At the moment, these failures are silent. TBD which 183957dacad5SJay Sternberg * failures should be reported. 184057dacad5SJay Sternberg */ 184157dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 184257dacad5SJay Sternberg { 18435bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 184457dacad5SJay Sternberg dev->tagset.ops = &nvme_mq_ops; 184557dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 184657dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 184757dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 184857dacad5SJay Sternberg dev->tagset.queue_depth = 184957dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 185057dacad5SJay Sternberg dev->tagset.cmd_size = nvme_cmd_size(dev); 185157dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 185257dacad5SJay Sternberg dev->tagset.driver_data = dev; 185357dacad5SJay Sternberg 185457dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->tagset)) 185557dacad5SJay Sternberg return 0; 18565bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 1857f9f38e33SHelen Koike 1858f9f38e33SHelen Koike nvme_dbbuf_set(dev); 1859949928c1SKeith Busch } else { 1860949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 1861949928c1SKeith Busch 1862949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 1863949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 186457dacad5SJay Sternberg } 1865949928c1SKeith Busch 186657dacad5SJay Sternberg return 0; 186757dacad5SJay Sternberg } 186857dacad5SJay Sternberg 1869b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 187057dacad5SJay Sternberg { 187157dacad5SJay Sternberg u64 cap; 1872b00a726aSKeith Busch int result = -ENOMEM; 187357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 187457dacad5SJay Sternberg 187557dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 187657dacad5SJay Sternberg return result; 187757dacad5SJay Sternberg 187857dacad5SJay Sternberg pci_set_master(pdev); 187957dacad5SJay Sternberg 188057dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 188157dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 188257dacad5SJay Sternberg goto disable; 188357dacad5SJay Sternberg 18847a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 188557dacad5SJay Sternberg result = -ENODEV; 1886b00a726aSKeith Busch goto disable; 188757dacad5SJay Sternberg } 188857dacad5SJay Sternberg 188957dacad5SJay Sternberg /* 1890a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 1891a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 1892a5229050SKeith Busch * adjust this later. 189357dacad5SJay Sternberg */ 1894dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 1895dca51e78SChristoph Hellwig if (result < 0) 1896dca51e78SChristoph Hellwig return result; 189757dacad5SJay Sternberg 18987a67cbeaSChristoph Hellwig cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 18997a67cbeaSChristoph Hellwig 190057dacad5SJay Sternberg dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH); 190157dacad5SJay Sternberg dev->db_stride = 1 << NVME_CAP_STRIDE(cap); 19027a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 19031f390c1fSStephan Günther 19041f390c1fSStephan Günther /* 19051f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 19061f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 19071f390c1fSStephan Günther */ 19081f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 19091f390c1fSStephan Günther dev->q_depth = 2; 19109bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 19119bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 19121f390c1fSStephan Günther dev->q_depth); 19131f390c1fSStephan Günther } 19141f390c1fSStephan Günther 1915202021c1SStephen Bates /* 1916202021c1SStephen Bates * CMBs can currently only exist on >=1.2 PCIe devices. We only 1917202021c1SStephen Bates * populate sysfs if a CMB is implemented. Note that we add the 1918202021c1SStephen Bates * CMB attribute to the nvme_ctrl kobj which removes the need to remove 1919202021c1SStephen Bates * it on exit. Since nvme_dev_attrs_group has no name we can pass 1920202021c1SStephen Bates * NULL as final argument to sysfs_add_file_to_group. 1921202021c1SStephen Bates */ 1922202021c1SStephen Bates 19238ef2074dSGabriel Krisman Bertazi if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) { 192457dacad5SJay Sternberg dev->cmb = nvme_map_cmb(dev); 192557dacad5SJay Sternberg 1926202021c1SStephen Bates if (dev->cmbsz) { 1927202021c1SStephen Bates if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1928202021c1SStephen Bates &dev_attr_cmb.attr, NULL)) 19299bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, 1930202021c1SStephen Bates "failed to add sysfs attribute for CMB\n"); 1931202021c1SStephen Bates } 1932202021c1SStephen Bates } 1933202021c1SStephen Bates 1934a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 1935a0a3408eSKeith Busch pci_save_state(pdev); 193657dacad5SJay Sternberg return 0; 193757dacad5SJay Sternberg 193857dacad5SJay Sternberg disable: 193957dacad5SJay Sternberg pci_disable_device(pdev); 194057dacad5SJay Sternberg return result; 194157dacad5SJay Sternberg } 194257dacad5SJay Sternberg 194357dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 194457dacad5SJay Sternberg { 1945b00a726aSKeith Busch if (dev->bar) 1946b00a726aSKeith Busch iounmap(dev->bar); 1947a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 1948b00a726aSKeith Busch } 1949b00a726aSKeith Busch 1950b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 1951b00a726aSKeith Busch { 195257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 195357dacad5SJay Sternberg 1954f63572dfSJon Derrick nvme_release_cmb(dev); 1955dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 195657dacad5SJay Sternberg 1957a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 1958a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 195957dacad5SJay Sternberg pci_disable_device(pdev); 196057dacad5SJay Sternberg } 1961a0a3408eSKeith Busch } 196257dacad5SJay Sternberg 1963a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 196457dacad5SJay Sternberg { 196570659060SKeith Busch int i, queues; 1966302ad8ccSKeith Busch bool dead = true; 1967302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 196857dacad5SJay Sternberg 19692d55cd5fSChristoph Hellwig del_timer_sync(&dev->watchdog_timer); 197057dacad5SJay Sternberg 197177bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 1972302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 1973302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1974302ad8ccSKeith Busch 1975302ad8ccSKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE) 1976302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 1977302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 1978302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 197957dacad5SJay Sternberg } 1980c21377f8SGabriel Krisman Bertazi 1981302ad8ccSKeith Busch /* 1982302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 1983302ad8ccSKeith Busch * doing a safe shutdown. 1984302ad8ccSKeith Busch */ 198587ad72a5SChristoph Hellwig if (!dead) { 198687ad72a5SChristoph Hellwig if (shutdown) 1987302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 198887ad72a5SChristoph Hellwig 198987ad72a5SChristoph Hellwig /* 199087ad72a5SChristoph Hellwig * If the controller is still alive tell it to stop using the 199187ad72a5SChristoph Hellwig * host memory buffer. In theory the shutdown / reset should 199287ad72a5SChristoph Hellwig * make sure that it doesn't access the host memoery anymore, 199387ad72a5SChristoph Hellwig * but I'd rather be safe than sorry.. 199487ad72a5SChristoph Hellwig */ 199587ad72a5SChristoph Hellwig if (dev->host_mem_descs) 199687ad72a5SChristoph Hellwig nvme_set_host_mem(dev, 0); 199787ad72a5SChristoph Hellwig 199887ad72a5SChristoph Hellwig } 1999302ad8ccSKeith Busch nvme_stop_queues(&dev->ctrl); 2000302ad8ccSKeith Busch 200170659060SKeith Busch queues = dev->online_queues - 1; 2002c21377f8SGabriel Krisman Bertazi for (i = dev->queue_count - 1; i > 0; i--) 2003c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[i]); 2004c21377f8SGabriel Krisman Bertazi 2005302ad8ccSKeith Busch if (dead) { 200682469c59SGabriel Krisman Bertazi /* A device might become IO incapable very soon during 200782469c59SGabriel Krisman Bertazi * probe, before the admin queue is configured. Thus, 200882469c59SGabriel Krisman Bertazi * queue_count can be 0 here. 200982469c59SGabriel Krisman Bertazi */ 201082469c59SGabriel Krisman Bertazi if (dev->queue_count) 2011c21377f8SGabriel Krisman Bertazi nvme_suspend_queue(dev->queues[0]); 201257dacad5SJay Sternberg } else { 201370659060SKeith Busch nvme_disable_io_queues(dev, queues); 2014a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 201557dacad5SJay Sternberg } 2016b00a726aSKeith Busch nvme_pci_disable(dev); 201757dacad5SJay Sternberg 2018e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2019e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2020302ad8ccSKeith Busch 2021302ad8ccSKeith Busch /* 2022302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2023302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2024302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2025302ad8ccSKeith Busch */ 2026302ad8ccSKeith Busch if (shutdown) 2027302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 202877bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 202957dacad5SJay Sternberg } 203057dacad5SJay Sternberg 203157dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 203257dacad5SJay Sternberg { 203357dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 203457dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 203557dacad5SJay Sternberg if (!dev->prp_page_pool) 203657dacad5SJay Sternberg return -ENOMEM; 203757dacad5SJay Sternberg 203857dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 203957dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 204057dacad5SJay Sternberg 256, 256, 0); 204157dacad5SJay Sternberg if (!dev->prp_small_pool) { 204257dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 204357dacad5SJay Sternberg return -ENOMEM; 204457dacad5SJay Sternberg } 204557dacad5SJay Sternberg return 0; 204657dacad5SJay Sternberg } 204757dacad5SJay Sternberg 204857dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 204957dacad5SJay Sternberg { 205057dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 205157dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 205257dacad5SJay Sternberg } 205357dacad5SJay Sternberg 20541673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 205557dacad5SJay Sternberg { 20561673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 205757dacad5SJay Sternberg 2058f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 205957dacad5SJay Sternberg put_device(dev->dev); 206057dacad5SJay Sternberg if (dev->tagset.tags) 206157dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 20621c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 20631c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 206457dacad5SJay Sternberg kfree(dev->queues); 2065e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 206657dacad5SJay Sternberg kfree(dev); 206757dacad5SJay Sternberg } 206857dacad5SJay Sternberg 2069f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2070f58944e2SKeith Busch { 2071237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2072f58944e2SKeith Busch 2073f58944e2SKeith Busch kref_get(&dev->ctrl.kref); 207469d9a99cSKeith Busch nvme_dev_disable(dev, false); 2075f58944e2SKeith Busch if (!schedule_work(&dev->remove_work)) 2076f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2077f58944e2SKeith Busch } 2078f58944e2SKeith Busch 2079fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 208057dacad5SJay Sternberg { 2081fd634f41SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work); 2082a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2083f58944e2SKeith Busch int result = -ENODEV; 208457dacad5SJay Sternberg 208582b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2086fd634f41SChristoph Hellwig goto out; 2087fd634f41SChristoph Hellwig 2088fd634f41SChristoph Hellwig /* 2089fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2090fd634f41SChristoph Hellwig * moving on. 2091fd634f41SChristoph Hellwig */ 2092b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2093a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2094fd634f41SChristoph Hellwig 2095b00a726aSKeith Busch result = nvme_pci_enable(dev); 209657dacad5SJay Sternberg if (result) 209757dacad5SJay Sternberg goto out; 209857dacad5SJay Sternberg 209957dacad5SJay Sternberg result = nvme_configure_admin_queue(dev); 210057dacad5SJay Sternberg if (result) 2101f58944e2SKeith Busch goto out; 210257dacad5SJay Sternberg 210357dacad5SJay Sternberg nvme_init_queue(dev->queues[0], 0); 210457dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 210557dacad5SJay Sternberg if (result) 2106f58944e2SKeith Busch goto out; 210757dacad5SJay Sternberg 2108ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2109ce4541f4SChristoph Hellwig if (result) 2110f58944e2SKeith Busch goto out; 2111ce4541f4SChristoph Hellwig 2112e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2113e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 21144f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 21154f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2116e286bcfcSScott Bauer else if (was_suspend) 21174f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2118e286bcfcSScott Bauer } else { 2119e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2120e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2121e286bcfcSScott Bauer } 2122a98e58e5SScott Bauer 2123f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2124f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2125f9f38e33SHelen Koike if (result) 2126f9f38e33SHelen Koike dev_warn(dev->dev, 2127f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2128f9f38e33SHelen Koike } 2129f9f38e33SHelen Koike 213087ad72a5SChristoph Hellwig if (dev->ctrl.hmpre) 213187ad72a5SChristoph Hellwig nvme_setup_host_mem(dev); 213287ad72a5SChristoph Hellwig 213357dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 213457dacad5SJay Sternberg if (result) 2135f58944e2SKeith Busch goto out; 213657dacad5SJay Sternberg 213721f033f7SKeith Busch /* 213821f033f7SKeith Busch * A controller that can not execute IO typically requires user 213921f033f7SKeith Busch * intervention to correct. For such degraded controllers, the driver 214021f033f7SKeith Busch * should not submit commands the user did not request, so skip 214121f033f7SKeith Busch * registering for asynchronous event notification on this condition. 214221f033f7SKeith Busch */ 2143f866fc42SChristoph Hellwig if (dev->online_queues > 1) 2144f866fc42SChristoph Hellwig nvme_queue_async_events(&dev->ctrl); 214557dacad5SJay Sternberg 21462d55cd5fSChristoph Hellwig mod_timer(&dev->watchdog_timer, round_jiffies(jiffies + HZ)); 214757dacad5SJay Sternberg 214857dacad5SJay Sternberg /* 214957dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 215057dacad5SJay Sternberg * any working I/O queue. 215157dacad5SJay Sternberg */ 215257dacad5SJay Sternberg if (dev->online_queues < 2) { 21531b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 21543b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 21555bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 215657dacad5SJay Sternberg } else { 215725646264SKeith Busch nvme_start_queues(&dev->ctrl); 2158302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 215957dacad5SJay Sternberg nvme_dev_add(dev); 2160302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 216157dacad5SJay Sternberg } 216257dacad5SJay Sternberg 2163bb8d261eSChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 2164bb8d261eSChristoph Hellwig dev_warn(dev->ctrl.device, "failed to mark controller live\n"); 2165bb8d261eSChristoph Hellwig goto out; 2166bb8d261eSChristoph Hellwig } 216792911a55SChristoph Hellwig 216892911a55SChristoph Hellwig if (dev->online_queues > 1) 21695955be21SChristoph Hellwig nvme_queue_scan(&dev->ctrl); 217057dacad5SJay Sternberg return; 217157dacad5SJay Sternberg 217257dacad5SJay Sternberg out: 2173f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 217457dacad5SJay Sternberg } 217557dacad5SJay Sternberg 21765c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 217757dacad5SJay Sternberg { 21785c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 217957dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 218057dacad5SJay Sternberg 218169d9a99cSKeith Busch nvme_kill_queues(&dev->ctrl); 218257dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2183921920abSKeith Busch device_release_driver(&pdev->dev); 21841673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 218557dacad5SJay Sternberg } 218657dacad5SJay Sternberg 218757dacad5SJay Sternberg static int nvme_reset(struct nvme_dev *dev) 218857dacad5SJay Sternberg { 21891c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q || blk_queue_dying(dev->ctrl.admin_q)) 219057dacad5SJay Sternberg return -ENODEV; 219182b057caSRakesh Pandit if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING)) 219282b057caSRakesh Pandit return -EBUSY; 2193846cc05fSChristoph Hellwig if (!queue_work(nvme_workq, &dev->reset_work)) 2194846cc05fSChristoph Hellwig return -EBUSY; 219557dacad5SJay Sternberg return 0; 219657dacad5SJay Sternberg } 219757dacad5SJay Sternberg 21981c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 219957dacad5SJay Sternberg { 22001c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 22011c63dc66SChristoph Hellwig return 0; 220257dacad5SJay Sternberg } 22031c63dc66SChristoph Hellwig 22045fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 22055fd4ce1bSChristoph Hellwig { 22065fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 22075fd4ce1bSChristoph Hellwig return 0; 22085fd4ce1bSChristoph Hellwig } 22095fd4ce1bSChristoph Hellwig 22107fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 22117fd8930fSChristoph Hellwig { 22127fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 22137fd8930fSChristoph Hellwig return 0; 22147fd8930fSChristoph Hellwig } 22157fd8930fSChristoph Hellwig 2216f3ca80fcSChristoph Hellwig static int nvme_pci_reset_ctrl(struct nvme_ctrl *ctrl) 2217f3ca80fcSChristoph Hellwig { 2218c5f6ce97SKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 2219c5f6ce97SKeith Busch int ret = nvme_reset(dev); 2220c5f6ce97SKeith Busch 2221c5f6ce97SKeith Busch if (!ret) 2222c5f6ce97SKeith Busch flush_work(&dev->reset_work); 2223c5f6ce97SKeith Busch return ret; 2224f3ca80fcSChristoph Hellwig } 2225f3ca80fcSChristoph Hellwig 22261c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 22271a353d85SMing Lin .name = "pcie", 2228e439bb12SSagi Grimberg .module = THIS_MODULE, 2229c81bfba9SChristoph Hellwig .flags = NVME_F_METADATA_SUPPORTED, 22301c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 22315fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 22327fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 2233f3ca80fcSChristoph Hellwig .reset_ctrl = nvme_pci_reset_ctrl, 22341673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2235f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 22361c63dc66SChristoph Hellwig }; 223757dacad5SJay Sternberg 2238b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2239b00a726aSKeith Busch { 2240b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2241b00a726aSKeith Busch 2242a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2243b00a726aSKeith Busch return -ENODEV; 2244b00a726aSKeith Busch 2245b00a726aSKeith Busch dev->bar = ioremap(pci_resource_start(pdev, 0), 8192); 2246b00a726aSKeith Busch if (!dev->bar) 2247b00a726aSKeith Busch goto release; 2248b00a726aSKeith Busch 2249b00a726aSKeith Busch return 0; 2250b00a726aSKeith Busch release: 2251a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2252b00a726aSKeith Busch return -ENODEV; 2253b00a726aSKeith Busch } 2254b00a726aSKeith Busch 2255ff5350a8SAndy Lutomirski static unsigned long check_dell_samsung_bug(struct pci_dev *pdev) 2256ff5350a8SAndy Lutomirski { 2257ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2258ff5350a8SAndy Lutomirski /* 2259ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2260ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2261ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2262ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2263ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2264ff5350a8SAndy Lutomirski * laptops. 2265ff5350a8SAndy Lutomirski */ 2266ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2267ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2268ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2269ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 2270ff5350a8SAndy Lutomirski } 2271ff5350a8SAndy Lutomirski 2272ff5350a8SAndy Lutomirski return 0; 2273ff5350a8SAndy Lutomirski } 2274ff5350a8SAndy Lutomirski 227557dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 227657dacad5SJay Sternberg { 227757dacad5SJay Sternberg int node, result = -ENOMEM; 227857dacad5SJay Sternberg struct nvme_dev *dev; 2279ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 228057dacad5SJay Sternberg 228157dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 228257dacad5SJay Sternberg if (node == NUMA_NO_NODE) 22832fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 228457dacad5SJay Sternberg 228557dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 228657dacad5SJay Sternberg if (!dev) 228757dacad5SJay Sternberg return -ENOMEM; 228857dacad5SJay Sternberg dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *), 228957dacad5SJay Sternberg GFP_KERNEL, node); 229057dacad5SJay Sternberg if (!dev->queues) 229157dacad5SJay Sternberg goto free; 229257dacad5SJay Sternberg 229357dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 229457dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 229557dacad5SJay Sternberg 2296b00a726aSKeith Busch result = nvme_dev_map(dev); 2297b00a726aSKeith Busch if (result) 2298b00a726aSKeith Busch goto free; 2299b00a726aSKeith Busch 2300f3ca80fcSChristoph Hellwig INIT_WORK(&dev->reset_work, nvme_reset_work); 23015c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 23022d55cd5fSChristoph Hellwig setup_timer(&dev->watchdog_timer, nvme_watchdog_timer, 23032d55cd5fSChristoph Hellwig (unsigned long)dev); 230477bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2305db3cbfffSKeith Busch init_completion(&dev->ioq_wait); 2306f3ca80fcSChristoph Hellwig 2307f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2308f3ca80fcSChristoph Hellwig if (result) 2309f3ca80fcSChristoph Hellwig goto put_pci; 2310f3ca80fcSChristoph Hellwig 2311ff5350a8SAndy Lutomirski quirks |= check_dell_samsung_bug(pdev); 2312ff5350a8SAndy Lutomirski 2313f3ca80fcSChristoph Hellwig result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2314ff5350a8SAndy Lutomirski quirks); 2315f3ca80fcSChristoph Hellwig if (result) 2316f3ca80fcSChristoph Hellwig goto release_pools; 2317f3ca80fcSChristoph Hellwig 231882b057caSRakesh Pandit nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING); 23191b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 23201b3c47c1SSagi Grimberg 232192f7a162SKeith Busch queue_work(nvme_workq, &dev->reset_work); 232257dacad5SJay Sternberg return 0; 232357dacad5SJay Sternberg 232457dacad5SJay Sternberg release_pools: 232557dacad5SJay Sternberg nvme_release_prp_pools(dev); 232657dacad5SJay Sternberg put_pci: 232757dacad5SJay Sternberg put_device(dev->dev); 2328b00a726aSKeith Busch nvme_dev_unmap(dev); 232957dacad5SJay Sternberg free: 233057dacad5SJay Sternberg kfree(dev->queues); 233157dacad5SJay Sternberg kfree(dev); 233257dacad5SJay Sternberg return result; 233357dacad5SJay Sternberg } 233457dacad5SJay Sternberg 233557dacad5SJay Sternberg static void nvme_reset_notify(struct pci_dev *pdev, bool prepare) 233657dacad5SJay Sternberg { 233757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 233857dacad5SJay Sternberg 233957dacad5SJay Sternberg if (prepare) 2340a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 234157dacad5SJay Sternberg else 2342c5f6ce97SKeith Busch nvme_reset(dev); 234357dacad5SJay Sternberg } 234457dacad5SJay Sternberg 234557dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 234657dacad5SJay Sternberg { 234757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2348a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 234957dacad5SJay Sternberg } 235057dacad5SJay Sternberg 2351f58944e2SKeith Busch /* 2352f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2353f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2354f58944e2SKeith Busch * order to proceed. 2355f58944e2SKeith Busch */ 235657dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 235757dacad5SJay Sternberg { 235857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 235957dacad5SJay Sternberg 2360bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2361bb8d261eSChristoph Hellwig 236282b057caSRakesh Pandit cancel_work_sync(&dev->reset_work); 236357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 23640ff9d4e1SKeith Busch 23656db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 23660ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 23676db28edaSKeith Busch nvme_dev_disable(dev, false); 23686db28edaSKeith Busch } 23690ff9d4e1SKeith Busch 23709bf2b972SKeith Busch flush_work(&dev->reset_work); 237153029b04SKeith Busch nvme_uninit_ctrl(&dev->ctrl); 2372a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 237387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 237457dacad5SJay Sternberg nvme_dev_remove_admin(dev); 237557dacad5SJay Sternberg nvme_free_queues(dev, 0); 237657dacad5SJay Sternberg nvme_release_prp_pools(dev); 2377b00a726aSKeith Busch nvme_dev_unmap(dev); 23781673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 237957dacad5SJay Sternberg } 238057dacad5SJay Sternberg 238113880f5bSKeith Busch static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs) 238213880f5bSKeith Busch { 238313880f5bSKeith Busch int ret = 0; 238413880f5bSKeith Busch 238513880f5bSKeith Busch if (numvfs == 0) { 238613880f5bSKeith Busch if (pci_vfs_assigned(pdev)) { 238713880f5bSKeith Busch dev_warn(&pdev->dev, 238813880f5bSKeith Busch "Cannot disable SR-IOV VFs while assigned\n"); 238913880f5bSKeith Busch return -EPERM; 239013880f5bSKeith Busch } 239113880f5bSKeith Busch pci_disable_sriov(pdev); 239213880f5bSKeith Busch return 0; 239313880f5bSKeith Busch } 239413880f5bSKeith Busch 239513880f5bSKeith Busch ret = pci_enable_sriov(pdev, numvfs); 239613880f5bSKeith Busch return ret ? ret : numvfs; 239713880f5bSKeith Busch } 239813880f5bSKeith Busch 239957dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 240057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 240157dacad5SJay Sternberg { 240257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 240357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 240457dacad5SJay Sternberg 2405a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 240657dacad5SJay Sternberg return 0; 240757dacad5SJay Sternberg } 240857dacad5SJay Sternberg 240957dacad5SJay Sternberg static int nvme_resume(struct device *dev) 241057dacad5SJay Sternberg { 241157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 241257dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 241357dacad5SJay Sternberg 2414c5f6ce97SKeith Busch nvme_reset(ndev); 241557dacad5SJay Sternberg return 0; 241657dacad5SJay Sternberg } 241757dacad5SJay Sternberg #endif 241857dacad5SJay Sternberg 241957dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 242057dacad5SJay Sternberg 2421a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2422a0a3408eSKeith Busch pci_channel_state_t state) 2423a0a3408eSKeith Busch { 2424a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2425a0a3408eSKeith Busch 2426a0a3408eSKeith Busch /* 2427a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2428a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2429a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2430a0a3408eSKeith Busch */ 2431a0a3408eSKeith Busch switch (state) { 2432a0a3408eSKeith Busch case pci_channel_io_normal: 2433a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2434a0a3408eSKeith Busch case pci_channel_io_frozen: 2435d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2436d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2437a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2438a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2439a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2440d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2441d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2442a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2443a0a3408eSKeith Busch } 2444a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2445a0a3408eSKeith Busch } 2446a0a3408eSKeith Busch 2447a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2448a0a3408eSKeith Busch { 2449a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2450a0a3408eSKeith Busch 24511b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2452a0a3408eSKeith Busch pci_restore_state(pdev); 2453c5f6ce97SKeith Busch nvme_reset(dev); 2454a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2455a0a3408eSKeith Busch } 2456a0a3408eSKeith Busch 2457a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2458a0a3408eSKeith Busch { 2459a0a3408eSKeith Busch pci_cleanup_aer_uncorrect_error_status(pdev); 2460a0a3408eSKeith Busch } 2461a0a3408eSKeith Busch 246257dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 246357dacad5SJay Sternberg .error_detected = nvme_error_detected, 246457dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 246557dacad5SJay Sternberg .resume = nvme_error_resume, 246657dacad5SJay Sternberg .reset_notify = nvme_reset_notify, 246757dacad5SJay Sternberg }; 246857dacad5SJay Sternberg 246957dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2470106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 247108095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2472e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247399466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 247499466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2475e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247699466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 247799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2478e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 247950af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 248050af47d0SAndy Lutomirski .driver_data = NVME_QUIRK_NO_DEEPEST_PS }, 2481540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2482540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 248354adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 248454adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2485015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2486015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 248757dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2488c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2489124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 249057dacad5SJay Sternberg { 0, } 249157dacad5SJay Sternberg }; 249257dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 249357dacad5SJay Sternberg 249457dacad5SJay Sternberg static struct pci_driver nvme_driver = { 249557dacad5SJay Sternberg .name = "nvme", 249657dacad5SJay Sternberg .id_table = nvme_id_table, 249757dacad5SJay Sternberg .probe = nvme_probe, 249857dacad5SJay Sternberg .remove = nvme_remove, 249957dacad5SJay Sternberg .shutdown = nvme_shutdown, 250057dacad5SJay Sternberg .driver = { 250157dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 250257dacad5SJay Sternberg }, 250313880f5bSKeith Busch .sriov_configure = nvme_pci_sriov_configure, 250457dacad5SJay Sternberg .err_handler = &nvme_err_handler, 250557dacad5SJay Sternberg }; 250657dacad5SJay Sternberg 250757dacad5SJay Sternberg static int __init nvme_init(void) 250857dacad5SJay Sternberg { 250957dacad5SJay Sternberg int result; 251057dacad5SJay Sternberg 251192f7a162SKeith Busch nvme_workq = alloc_workqueue("nvme", WQ_UNBOUND | WQ_MEM_RECLAIM, 0); 251257dacad5SJay Sternberg if (!nvme_workq) 251357dacad5SJay Sternberg return -ENOMEM; 251457dacad5SJay Sternberg 251557dacad5SJay Sternberg result = pci_register_driver(&nvme_driver); 251657dacad5SJay Sternberg if (result) 251757dacad5SJay Sternberg destroy_workqueue(nvme_workq); 251857dacad5SJay Sternberg return result; 251957dacad5SJay Sternberg } 252057dacad5SJay Sternberg 252157dacad5SJay Sternberg static void __exit nvme_exit(void) 252257dacad5SJay Sternberg { 252357dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 252457dacad5SJay Sternberg destroy_workqueue(nvme_workq); 252557dacad5SJay Sternberg _nvme_check_size(); 252657dacad5SJay Sternberg } 252757dacad5SJay Sternberg 252857dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 252957dacad5SJay Sternberg MODULE_LICENSE("GPL"); 253057dacad5SJay Sternberg MODULE_VERSION("1.0"); 253157dacad5SJay Sternberg module_init(nvme_init); 253257dacad5SJay Sternberg module_exit(nvme_exit); 2533