157dacad5SJay Sternberg /* 257dacad5SJay Sternberg * NVM Express device driver 357dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 457dacad5SJay Sternberg * 557dacad5SJay Sternberg * This program is free software; you can redistribute it and/or modify it 657dacad5SJay Sternberg * under the terms and conditions of the GNU General Public License, 757dacad5SJay Sternberg * version 2, as published by the Free Software Foundation. 857dacad5SJay Sternberg * 957dacad5SJay Sternberg * This program is distributed in the hope it will be useful, but WITHOUT 1057dacad5SJay Sternberg * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1157dacad5SJay Sternberg * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1257dacad5SJay Sternberg * more details. 1357dacad5SJay Sternberg */ 1457dacad5SJay Sternberg 15a0a3408eSKeith Busch #include <linux/aer.h> 1618119775SKeith Busch #include <linux/async.h> 1757dacad5SJay Sternberg #include <linux/blkdev.h> 1857dacad5SJay Sternberg #include <linux/blk-mq.h> 19dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 20ff5350a8SAndy Lutomirski #include <linux/dmi.h> 2157dacad5SJay Sternberg #include <linux/init.h> 2257dacad5SJay Sternberg #include <linux/interrupt.h> 2357dacad5SJay Sternberg #include <linux/io.h> 2457dacad5SJay Sternberg #include <linux/mm.h> 2557dacad5SJay Sternberg #include <linux/module.h> 2677bf25eaSKeith Busch #include <linux/mutex.h> 27d0877473SKeith Busch #include <linux/once.h> 2857dacad5SJay Sternberg #include <linux/pci.h> 2957dacad5SJay Sternberg #include <linux/t10-pi.h> 3057dacad5SJay Sternberg #include <linux/types.h> 319cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 32a98e58e5SScott Bauer #include <linux/sed-opal.h> 330f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3457dacad5SJay Sternberg 3557dacad5SJay Sternberg #include "nvme.h" 3657dacad5SJay Sternberg 3757dacad5SJay Sternberg #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command)) 3857dacad5SJay Sternberg #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion)) 3957dacad5SJay Sternberg 40a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 41adf68f21SChristoph Hellwig 42943e942eSJens Axboe /* 43943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 44943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 45943e942eSJens Axboe */ 46943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 47943e942eSJens Axboe #define NVME_MAX_SEGS 127 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 5057dacad5SJay Sternberg module_param(use_threaded_interrupts, int, 0); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 70b27c1e68Sweiping zhang .get = param_get_int, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 73b27c1e68Sweiping zhang static int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 75b27c1e68Sweiping zhang MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2"); 76b27c1e68Sweiping zhang 773b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp); 783b6592f7SJens Axboe static const struct kernel_param_ops queue_count_ops = { 793b6592f7SJens Axboe .set = queue_count_set, 803b6592f7SJens Axboe .get = param_get_int, 813b6592f7SJens Axboe }; 823b6592f7SJens Axboe 833b6592f7SJens Axboe static int write_queues; 843b6592f7SJens Axboe module_param_cb(write_queues, &queue_count_ops, &write_queues, 0644); 853b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 863b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 873b6592f7SJens Axboe "will share a queue set."); 883b6592f7SJens Axboe 89a4668d9bSJens Axboe static int poll_queues = 0; 904b04cc6aSJens Axboe module_param_cb(poll_queues, &queue_count_ops, &poll_queues, 0644); 914b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 924b04cc6aSJens Axboe 931c63dc66SChristoph Hellwig struct nvme_dev; 941c63dc66SChristoph Hellwig struct nvme_queue; 9557dacad5SJay Sternberg 96a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 9757dacad5SJay Sternberg 9857dacad5SJay Sternberg /* 991c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1001c63dc66SChristoph Hellwig */ 1011c63dc66SChristoph Hellwig struct nvme_dev { 102147b27e4SSagi Grimberg struct nvme_queue *queues; 1031c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1041c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1051c63dc66SChristoph Hellwig u32 __iomem *dbs; 1061c63dc66SChristoph Hellwig struct device *dev; 1071c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1081c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1091c63dc66SChristoph Hellwig unsigned online_queues; 1101c63dc66SChristoph Hellwig unsigned max_qid; 111e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 11222b55601SKeith Busch unsigned int num_vecs; 1131c63dc66SChristoph Hellwig int q_depth; 1141c63dc66SChristoph Hellwig u32 db_stride; 1151c63dc66SChristoph Hellwig void __iomem *bar; 11697f6ef64SXu Yu unsigned long bar_mapped_size; 1175c8809e6SChristoph Hellwig struct work_struct remove_work; 11877bf25eaSKeith Busch struct mutex shutdown_lock; 1191c63dc66SChristoph Hellwig bool subsystem; 1201c63dc66SChristoph Hellwig u64 cmb_size; 1210f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1221c63dc66SChristoph Hellwig u32 cmbsz; 123202021c1SStephen Bates u32 cmbloc; 1241c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 12587ad72a5SChristoph Hellwig 126943e942eSJens Axboe mempool_t *iod_mempool; 127943e942eSJens Axboe 12887ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 129f9f38e33SHelen Koike u32 *dbbuf_dbs; 130f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 131f9f38e33SHelen Koike u32 *dbbuf_eis; 132f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 13387ad72a5SChristoph Hellwig 13487ad72a5SChristoph Hellwig /* host memory buffer support: */ 13587ad72a5SChristoph Hellwig u64 host_mem_size; 13687ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1374033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 13887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 13987ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 14057dacad5SJay Sternberg }; 14157dacad5SJay Sternberg 142b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 143b27c1e68Sweiping zhang { 144b27c1e68Sweiping zhang int n = 0, ret; 145b27c1e68Sweiping zhang 146b27c1e68Sweiping zhang ret = kstrtoint(val, 10, &n); 147b27c1e68Sweiping zhang if (ret != 0 || n < 2) 148b27c1e68Sweiping zhang return -EINVAL; 149b27c1e68Sweiping zhang 150b27c1e68Sweiping zhang return param_set_int(val, kp); 151b27c1e68Sweiping zhang } 152b27c1e68Sweiping zhang 1533b6592f7SJens Axboe static int queue_count_set(const char *val, const struct kernel_param *kp) 1543b6592f7SJens Axboe { 1553b6592f7SJens Axboe int n = 0, ret; 1563b6592f7SJens Axboe 1573b6592f7SJens Axboe ret = kstrtoint(val, 10, &n); 1583b6592f7SJens Axboe if (n > num_possible_cpus()) 1593b6592f7SJens Axboe n = num_possible_cpus(); 1603b6592f7SJens Axboe 1613b6592f7SJens Axboe return param_set_int(val, kp); 1623b6592f7SJens Axboe } 1633b6592f7SJens Axboe 164f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 165f9f38e33SHelen Koike { 166f9f38e33SHelen Koike return qid * 2 * stride; 167f9f38e33SHelen Koike } 168f9f38e33SHelen Koike 169f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 1741c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1751c63dc66SChristoph Hellwig { 1761c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1771c63dc66SChristoph Hellwig } 1781c63dc66SChristoph Hellwig 17957dacad5SJay Sternberg /* 18057dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18157dacad5SJay Sternberg * commands and one for I/O commands). 18257dacad5SJay Sternberg */ 18357dacad5SJay Sternberg struct nvme_queue { 18457dacad5SJay Sternberg struct device *q_dmadev; 18557dacad5SJay Sternberg struct nvme_dev *dev; 1861ab0cd69SJens Axboe spinlock_t sq_lock; 18757dacad5SJay Sternberg struct nvme_command *sq_cmds; 1883a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1893a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19057dacad5SJay Sternberg volatile struct nvme_completion *cqes; 19157dacad5SJay Sternberg struct blk_mq_tags **tags; 19257dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19357dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19457dacad5SJay Sternberg u32 __iomem *q_db; 19557dacad5SJay Sternberg u16 q_depth; 19657dacad5SJay Sternberg s16 cq_vector; 19757dacad5SJay Sternberg u16 sq_tail; 19804f3eafdSJens Axboe u16 last_sq_tail; 19957dacad5SJay Sternberg u16 cq_head; 20068fa9dbeSJens Axboe u16 last_cq_head; 20157dacad5SJay Sternberg u16 qid; 20257dacad5SJay Sternberg u8 cq_phase; 2034e224106SChristoph Hellwig unsigned long flags; 2044e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20563223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 206d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 207f9f38e33SHelen Koike u32 *dbbuf_sq_db; 208f9f38e33SHelen Koike u32 *dbbuf_cq_db; 209f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 210f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 211d1ed6aa1SChristoph Hellwig struct completion delete_done; 21257dacad5SJay Sternberg }; 21357dacad5SJay Sternberg 21457dacad5SJay Sternberg /* 21571bd150cSChristoph Hellwig * The nvme_iod describes the data in an I/O, including the list of PRP 21671bd150cSChristoph Hellwig * entries. You can't see it in this data structure because C doesn't let 217f4800d6dSChristoph Hellwig * me express that. Use nvme_init_iod to ensure there's enough space 21871bd150cSChristoph Hellwig * allocated to store the PRP list. 21971bd150cSChristoph Hellwig */ 22071bd150cSChristoph Hellwig struct nvme_iod { 221d49187e9SChristoph Hellwig struct nvme_request req; 222f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 223a7a7cbe3SChaitanya Kulkarni bool use_sgl; 224f4800d6dSChristoph Hellwig int aborted; 22571bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 22671bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 22771bd150cSChristoph Hellwig int length; /* Of data, in bytes */ 22871bd150cSChristoph Hellwig dma_addr_t first_dma; 229bf684057SChristoph Hellwig struct scatterlist meta_sg; /* metadata requires single contiguous buffer */ 230f4800d6dSChristoph Hellwig struct scatterlist *sg; 231f4800d6dSChristoph Hellwig struct scatterlist inline_sg[0]; 23257dacad5SJay Sternberg }; 23357dacad5SJay Sternberg 23457dacad5SJay Sternberg /* 23557dacad5SJay Sternberg * Check we didin't inadvertently grow the command struct 23657dacad5SJay Sternberg */ 23757dacad5SJay Sternberg static inline void _nvme_check_size(void) 23857dacad5SJay Sternberg { 23957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64); 24057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 24157dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 24257dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 24357dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_features) != 64); 24457dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64); 24557dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64); 24657dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_command) != 64); 2470add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE); 2480add5e8eSJohannes Thumshirn BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE); 24957dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64); 25057dacad5SJay Sternberg BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512); 251f9f38e33SHelen Koike BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64); 252f9f38e33SHelen Koike } 253f9f38e33SHelen Koike 2543b6592f7SJens Axboe static unsigned int max_io_queues(void) 2553b6592f7SJens Axboe { 2564b04cc6aSJens Axboe return num_possible_cpus() + write_queues + poll_queues; 2573b6592f7SJens Axboe } 2583b6592f7SJens Axboe 2593b6592f7SJens Axboe static unsigned int max_queue_count(void) 2603b6592f7SJens Axboe { 2613b6592f7SJens Axboe /* IO queues + admin queue */ 2623b6592f7SJens Axboe return 1 + max_io_queues(); 2633b6592f7SJens Axboe } 2643b6592f7SJens Axboe 265f9f38e33SHelen Koike static inline unsigned int nvme_dbbuf_size(u32 stride) 266f9f38e33SHelen Koike { 2673b6592f7SJens Axboe return (max_queue_count() * 8 * stride); 268f9f38e33SHelen Koike } 269f9f38e33SHelen Koike 270f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 271f9f38e33SHelen Koike { 272f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike if (dev->dbbuf_dbs) 275f9f38e33SHelen Koike return 0; 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 278f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 279f9f38e33SHelen Koike GFP_KERNEL); 280f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 281f9f38e33SHelen Koike return -ENOMEM; 282f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 283f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 284f9f38e33SHelen Koike GFP_KERNEL); 285f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 286f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 287f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 288f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 289f9f38e33SHelen Koike return -ENOMEM; 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike 292f9f38e33SHelen Koike return 0; 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 296f9f38e33SHelen Koike { 297f9f38e33SHelen Koike unsigned int mem_size = nvme_dbbuf_size(dev->db_stride); 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 300f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 301f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 302f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike if (dev->dbbuf_eis) { 305f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 306f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 307f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 308f9f38e33SHelen Koike } 309f9f38e33SHelen Koike } 310f9f38e33SHelen Koike 311f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 312f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 313f9f38e33SHelen Koike { 314f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 315f9f38e33SHelen Koike return; 316f9f38e33SHelen Koike 317f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 318f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 319f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 320f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 321f9f38e33SHelen Koike } 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 324f9f38e33SHelen Koike { 325f9f38e33SHelen Koike struct nvme_command c; 326f9f38e33SHelen Koike 327f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 328f9f38e33SHelen Koike return; 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike memset(&c, 0, sizeof(c)); 331f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 332f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 333f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 334f9f38e33SHelen Koike 335f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3369bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 337f9f38e33SHelen Koike /* Free memory and continue on */ 338f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 339f9f38e33SHelen Koike } 340f9f38e33SHelen Koike } 341f9f38e33SHelen Koike 342f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 343f9f38e33SHelen Koike { 344f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 345f9f38e33SHelen Koike } 346f9f38e33SHelen Koike 347f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 348f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 349f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 350f9f38e33SHelen Koike { 351f9f38e33SHelen Koike if (dbbuf_db) { 352f9f38e33SHelen Koike u16 old_value; 353f9f38e33SHelen Koike 354f9f38e33SHelen Koike /* 355f9f38e33SHelen Koike * Ensure that the queue is written before updating 356f9f38e33SHelen Koike * the doorbell in memory 357f9f38e33SHelen Koike */ 358f9f38e33SHelen Koike wmb(); 359f9f38e33SHelen Koike 360f9f38e33SHelen Koike old_value = *dbbuf_db; 361f9f38e33SHelen Koike *dbbuf_db = value; 362f9f38e33SHelen Koike 363f1ed3df2SMichal Wnukowski /* 364f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 365f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 366f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 367f1ed3df2SMichal Wnukowski * the doorbell. 368f1ed3df2SMichal Wnukowski */ 369f1ed3df2SMichal Wnukowski mb(); 370f1ed3df2SMichal Wnukowski 371f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 372f9f38e33SHelen Koike return false; 373f9f38e33SHelen Koike } 374f9f38e33SHelen Koike 375f9f38e33SHelen Koike return true; 37657dacad5SJay Sternberg } 37757dacad5SJay Sternberg 37857dacad5SJay Sternberg /* 37957dacad5SJay Sternberg * Max size of iod being embedded in the request payload 38057dacad5SJay Sternberg */ 38157dacad5SJay Sternberg #define NVME_INT_PAGES 2 3825fd4ce1bSChristoph Hellwig #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size) 38357dacad5SJay Sternberg 38457dacad5SJay Sternberg /* 38557dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38657dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38757dacad5SJay Sternberg * the I/O. 38857dacad5SJay Sternberg */ 38957dacad5SJay Sternberg static int nvme_npages(unsigned size, struct nvme_dev *dev) 39057dacad5SJay Sternberg { 3915fd4ce1bSChristoph Hellwig unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size, 3925fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 39357dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 39457dacad5SJay Sternberg } 39557dacad5SJay Sternberg 396a7a7cbe3SChaitanya Kulkarni /* 397a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 398a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 399a7a7cbe3SChaitanya Kulkarni */ 400a7a7cbe3SChaitanya Kulkarni static int nvme_pci_npages_sgl(unsigned int num_seg) 401f4800d6dSChristoph Hellwig { 402a7a7cbe3SChaitanya Kulkarni return DIV_ROUND_UP(num_seg * sizeof(struct nvme_sgl_desc), PAGE_SIZE); 403f4800d6dSChristoph Hellwig } 404f4800d6dSChristoph Hellwig 405a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_iod_alloc_size(struct nvme_dev *dev, 406a7a7cbe3SChaitanya Kulkarni unsigned int size, unsigned int nseg, bool use_sgl) 40757dacad5SJay Sternberg { 408a7a7cbe3SChaitanya Kulkarni size_t alloc_size; 409a7a7cbe3SChaitanya Kulkarni 410a7a7cbe3SChaitanya Kulkarni if (use_sgl) 411a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_pci_npages_sgl(nseg); 412a7a7cbe3SChaitanya Kulkarni else 413a7a7cbe3SChaitanya Kulkarni alloc_size = sizeof(__le64 *) * nvme_npages(size, dev); 414a7a7cbe3SChaitanya Kulkarni 415a7a7cbe3SChaitanya Kulkarni return alloc_size + sizeof(struct scatterlist) * nseg; 416a7a7cbe3SChaitanya Kulkarni } 417a7a7cbe3SChaitanya Kulkarni 418a7a7cbe3SChaitanya Kulkarni static unsigned int nvme_pci_cmd_size(struct nvme_dev *dev, bool use_sgl) 419a7a7cbe3SChaitanya Kulkarni { 420a7a7cbe3SChaitanya Kulkarni unsigned int alloc_size = nvme_pci_iod_alloc_size(dev, 421a7a7cbe3SChaitanya Kulkarni NVME_INT_BYTES(dev), NVME_INT_PAGES, 422a7a7cbe3SChaitanya Kulkarni use_sgl); 423a7a7cbe3SChaitanya Kulkarni 424a7a7cbe3SChaitanya Kulkarni return sizeof(struct nvme_iod) + alloc_size; 42557dacad5SJay Sternberg } 42657dacad5SJay Sternberg 42757dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 42857dacad5SJay Sternberg unsigned int hctx_idx) 42957dacad5SJay Sternberg { 43057dacad5SJay Sternberg struct nvme_dev *dev = data; 431147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 43257dacad5SJay Sternberg 43357dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 43457dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 43557dacad5SJay Sternberg WARN_ON(nvmeq->tags); 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg hctx->driver_data = nvmeq; 43857dacad5SJay Sternberg nvmeq->tags = &dev->admin_tagset.tags[0]; 43957dacad5SJay Sternberg return 0; 44057dacad5SJay Sternberg } 44157dacad5SJay Sternberg 44257dacad5SJay Sternberg static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx) 44357dacad5SJay Sternberg { 44457dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 44557dacad5SJay Sternberg 44657dacad5SJay Sternberg nvmeq->tags = NULL; 44757dacad5SJay Sternberg } 44857dacad5SJay Sternberg 44957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 45057dacad5SJay Sternberg unsigned int hctx_idx) 45157dacad5SJay Sternberg { 45257dacad5SJay Sternberg struct nvme_dev *dev = data; 453147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 45457dacad5SJay Sternberg 45557dacad5SJay Sternberg if (!nvmeq->tags) 45657dacad5SJay Sternberg nvmeq->tags = &dev->tagset.tags[hctx_idx]; 45757dacad5SJay Sternberg 45857dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 45957dacad5SJay Sternberg hctx->driver_data = nvmeq; 46057dacad5SJay Sternberg return 0; 46157dacad5SJay Sternberg } 46257dacad5SJay Sternberg 463d6296d39SChristoph Hellwig static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req, 464d6296d39SChristoph Hellwig unsigned int hctx_idx, unsigned int numa_node) 46557dacad5SJay Sternberg { 466d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 467f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4680350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 469147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 47057dacad5SJay Sternberg 47157dacad5SJay Sternberg BUG_ON(!nvmeq); 472f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 47359e29ce6SSagi Grimberg 47459e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 47557dacad5SJay Sternberg return 0; 47657dacad5SJay Sternberg } 47757dacad5SJay Sternberg 4783b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4793b6592f7SJens Axboe { 4803b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4813b6592f7SJens Axboe if (dev->num_vecs > 1) 4823b6592f7SJens Axboe return 1; 4833b6592f7SJens Axboe 4843b6592f7SJens Axboe return 0; 4853b6592f7SJens Axboe } 4863b6592f7SJens Axboe 487dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 488dca51e78SChristoph Hellwig { 489dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4903b6592f7SJens Axboe int i, qoff, offset; 491dca51e78SChristoph Hellwig 4923b6592f7SJens Axboe offset = queue_irq_offset(dev); 4933b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4943b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4953b6592f7SJens Axboe 4963b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4973b6592f7SJens Axboe if (!map->nr_queues) { 498e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4997e849dd9SChristoph Hellwig continue; 5003b6592f7SJens Axboe } 5013b6592f7SJens Axboe 5024b04cc6aSJens Axboe /* 5034b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 5044b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 5054b04cc6aSJens Axboe */ 5063b6592f7SJens Axboe map->queue_offset = qoff; 507e20ba6e1SChristoph Hellwig if (i != HCTX_TYPE_POLL) 5083b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 5094b04cc6aSJens Axboe else 5104b04cc6aSJens Axboe blk_mq_map_queues(map); 5113b6592f7SJens Axboe qoff += map->nr_queues; 5123b6592f7SJens Axboe offset += map->nr_queues; 5133b6592f7SJens Axboe } 5143b6592f7SJens Axboe 5153b6592f7SJens Axboe return 0; 516dca51e78SChristoph Hellwig } 517dca51e78SChristoph Hellwig 51804f3eafdSJens Axboe /* 51904f3eafdSJens Axboe * Write sq tail if we are asked to, or if the next command would wrap. 52004f3eafdSJens Axboe */ 52104f3eafdSJens Axboe static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 52204f3eafdSJens Axboe { 52304f3eafdSJens Axboe if (!write_sq) { 52404f3eafdSJens Axboe u16 next_tail = nvmeq->sq_tail + 1; 52504f3eafdSJens Axboe 52604f3eafdSJens Axboe if (next_tail == nvmeq->q_depth) 52704f3eafdSJens Axboe next_tail = 0; 52804f3eafdSJens Axboe if (next_tail != nvmeq->last_sq_tail) 52904f3eafdSJens Axboe return; 53004f3eafdSJens Axboe } 53104f3eafdSJens Axboe 53204f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 53304f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 53404f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 53504f3eafdSJens Axboe nvmeq->last_sq_tail = nvmeq->sq_tail; 53604f3eafdSJens Axboe } 53704f3eafdSJens Axboe 53857dacad5SJay Sternberg /** 53990ea5ca4SChristoph Hellwig * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell 54057dacad5SJay Sternberg * @nvmeq: The queue to use 54157dacad5SJay Sternberg * @cmd: The command to send 54204f3eafdSJens Axboe * @write_sq: whether to write to the SQ doorbell 54357dacad5SJay Sternberg */ 54404f3eafdSJens Axboe static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd, 54504f3eafdSJens Axboe bool write_sq) 54657dacad5SJay Sternberg { 54790ea5ca4SChristoph Hellwig spin_lock(&nvmeq->sq_lock); 54890ea5ca4SChristoph Hellwig memcpy(&nvmeq->sq_cmds[nvmeq->sq_tail], cmd, sizeof(*cmd)); 54990ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 55090ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 55104f3eafdSJens Axboe nvme_write_sq_db(nvmeq, write_sq); 55204f3eafdSJens Axboe spin_unlock(&nvmeq->sq_lock); 55304f3eafdSJens Axboe } 55404f3eafdSJens Axboe 55504f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 55604f3eafdSJens Axboe { 55704f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 55804f3eafdSJens Axboe 55904f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 56004f3eafdSJens Axboe if (nvmeq->sq_tail != nvmeq->last_sq_tail) 56104f3eafdSJens Axboe nvme_write_sq_db(nvmeq, true); 56290ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 56357dacad5SJay Sternberg } 56457dacad5SJay Sternberg 565a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 56657dacad5SJay Sternberg { 567f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 568a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 56957dacad5SJay Sternberg } 57057dacad5SJay Sternberg 571955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 572955b1b5aSMinwoo Im { 573955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 57420469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 575955b1b5aSMinwoo Im unsigned int avg_seg_size; 576955b1b5aSMinwoo Im 57720469a37SKeith Busch if (nseg == 0) 57820469a37SKeith Busch return false; 57920469a37SKeith Busch 58020469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 581955b1b5aSMinwoo Im 582955b1b5aSMinwoo Im if (!(dev->ctrl.sgls & ((1 << 0) | (1 << 1)))) 583955b1b5aSMinwoo Im return false; 584955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 585955b1b5aSMinwoo Im return false; 586955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 587955b1b5aSMinwoo Im return false; 588955b1b5aSMinwoo Im return true; 589955b1b5aSMinwoo Im } 590955b1b5aSMinwoo Im 591fc17b653SChristoph Hellwig static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev) 59257dacad5SJay Sternberg { 593f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(rq); 594f9d03f96SChristoph Hellwig int nseg = blk_rq_nr_phys_segments(rq); 595b131c61dSChristoph Hellwig unsigned int size = blk_rq_payload_bytes(rq); 596f4800d6dSChristoph Hellwig 597955b1b5aSMinwoo Im iod->use_sgl = nvme_pci_use_sgls(dev, rq); 598955b1b5aSMinwoo Im 599f4800d6dSChristoph Hellwig if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) { 600943e942eSJens Axboe iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 601f4800d6dSChristoph Hellwig if (!iod->sg) 602fc17b653SChristoph Hellwig return BLK_STS_RESOURCE; 603f4800d6dSChristoph Hellwig } else { 604f4800d6dSChristoph Hellwig iod->sg = iod->inline_sg; 60557dacad5SJay Sternberg } 60657dacad5SJay Sternberg 607f4800d6dSChristoph Hellwig iod->aborted = 0; 60857dacad5SJay Sternberg iod->npages = -1; 60957dacad5SJay Sternberg iod->nents = 0; 610f4800d6dSChristoph Hellwig iod->length = size; 611f80ec966SKeith Busch 612fc17b653SChristoph Hellwig return BLK_STS_OK; 61357dacad5SJay Sternberg } 61457dacad5SJay Sternberg 615f4800d6dSChristoph Hellwig static void nvme_free_iod(struct nvme_dev *dev, struct request *req) 61657dacad5SJay Sternberg { 617f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 618a7a7cbe3SChaitanya Kulkarni const int last_prp = dev->ctrl.page_size / sizeof(__le64) - 1; 619a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr = iod->first_dma, next_dma_addr; 620a7a7cbe3SChaitanya Kulkarni 62157dacad5SJay Sternberg int i; 62257dacad5SJay Sternberg 62357dacad5SJay Sternberg if (iod->npages == 0) 624a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 625a7a7cbe3SChaitanya Kulkarni dma_addr); 626a7a7cbe3SChaitanya Kulkarni 62757dacad5SJay Sternberg for (i = 0; i < iod->npages; i++) { 628a7a7cbe3SChaitanya Kulkarni void *addr = nvme_pci_iod_list(req)[i]; 629a7a7cbe3SChaitanya Kulkarni 630a7a7cbe3SChaitanya Kulkarni if (iod->use_sgl) { 631a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list = addr; 632a7a7cbe3SChaitanya Kulkarni 633a7a7cbe3SChaitanya Kulkarni next_dma_addr = 634a7a7cbe3SChaitanya Kulkarni le64_to_cpu((sg_list[SGES_PER_PAGE - 1]).addr); 635a7a7cbe3SChaitanya Kulkarni } else { 636a7a7cbe3SChaitanya Kulkarni __le64 *prp_list = addr; 637a7a7cbe3SChaitanya Kulkarni 638a7a7cbe3SChaitanya Kulkarni next_dma_addr = le64_to_cpu(prp_list[last_prp]); 639a7a7cbe3SChaitanya Kulkarni } 640a7a7cbe3SChaitanya Kulkarni 641a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_page_pool, addr, dma_addr); 642a7a7cbe3SChaitanya Kulkarni dma_addr = next_dma_addr; 64357dacad5SJay Sternberg } 64457dacad5SJay Sternberg 645f4800d6dSChristoph Hellwig if (iod->sg != iod->inline_sg) 646943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 64757dacad5SJay Sternberg } 64857dacad5SJay Sternberg 649d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 650d0877473SKeith Busch { 651d0877473SKeith Busch int i; 652d0877473SKeith Busch struct scatterlist *sg; 653d0877473SKeith Busch 654d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 655d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 656d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 657d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 658d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 659d0877473SKeith Busch sg_dma_len(sg)); 660d0877473SKeith Busch } 661d0877473SKeith Busch } 662d0877473SKeith Busch 663a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 664a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 66557dacad5SJay Sternberg { 666f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 66757dacad5SJay Sternberg struct dma_pool *pool; 668b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 66957dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 67057dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 67157dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6725fd4ce1bSChristoph Hellwig u32 page_size = dev->ctrl.page_size; 67357dacad5SJay Sternberg int offset = dma_addr & (page_size - 1); 67457dacad5SJay Sternberg __le64 *prp_list; 675a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 67657dacad5SJay Sternberg dma_addr_t prp_dma; 67757dacad5SJay Sternberg int nprps, i; 67857dacad5SJay Sternberg 67957dacad5SJay Sternberg length -= (page_size - offset); 6805228b328SJan H. Schönherr if (length <= 0) { 6815228b328SJan H. Schönherr iod->first_dma = 0; 682a7a7cbe3SChaitanya Kulkarni goto done; 6835228b328SJan H. Schönherr } 68457dacad5SJay Sternberg 68557dacad5SJay Sternberg dma_len -= (page_size - offset); 68657dacad5SJay Sternberg if (dma_len) { 68757dacad5SJay Sternberg dma_addr += (page_size - offset); 68857dacad5SJay Sternberg } else { 68957dacad5SJay Sternberg sg = sg_next(sg); 69057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 69157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 69257dacad5SJay Sternberg } 69357dacad5SJay Sternberg 69457dacad5SJay Sternberg if (length <= page_size) { 69557dacad5SJay Sternberg iod->first_dma = dma_addr; 696a7a7cbe3SChaitanya Kulkarni goto done; 69757dacad5SJay Sternberg } 69857dacad5SJay Sternberg 69957dacad5SJay Sternberg nprps = DIV_ROUND_UP(length, page_size); 70057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 70157dacad5SJay Sternberg pool = dev->prp_small_pool; 70257dacad5SJay Sternberg iod->npages = 0; 70357dacad5SJay Sternberg } else { 70457dacad5SJay Sternberg pool = dev->prp_page_pool; 70557dacad5SJay Sternberg iod->npages = 1; 70657dacad5SJay Sternberg } 70757dacad5SJay Sternberg 70869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 70957dacad5SJay Sternberg if (!prp_list) { 71057dacad5SJay Sternberg iod->first_dma = dma_addr; 71157dacad5SJay Sternberg iod->npages = -1; 71286eea289SKeith Busch return BLK_STS_RESOURCE; 71357dacad5SJay Sternberg } 71457dacad5SJay Sternberg list[0] = prp_list; 71557dacad5SJay Sternberg iod->first_dma = prp_dma; 71657dacad5SJay Sternberg i = 0; 71757dacad5SJay Sternberg for (;;) { 71857dacad5SJay Sternberg if (i == page_size >> 3) { 71957dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 72069d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 72157dacad5SJay Sternberg if (!prp_list) 72286eea289SKeith Busch return BLK_STS_RESOURCE; 72357dacad5SJay Sternberg list[iod->npages++] = prp_list; 72457dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 72557dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 72657dacad5SJay Sternberg i = 1; 72757dacad5SJay Sternberg } 72857dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 72957dacad5SJay Sternberg dma_len -= page_size; 73057dacad5SJay Sternberg dma_addr += page_size; 73157dacad5SJay Sternberg length -= page_size; 73257dacad5SJay Sternberg if (length <= 0) 73357dacad5SJay Sternberg break; 73457dacad5SJay Sternberg if (dma_len > 0) 73557dacad5SJay Sternberg continue; 73686eea289SKeith Busch if (unlikely(dma_len < 0)) 73786eea289SKeith Busch goto bad_sgl; 73857dacad5SJay Sternberg sg = sg_next(sg); 73957dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 74057dacad5SJay Sternberg dma_len = sg_dma_len(sg); 74157dacad5SJay Sternberg } 74257dacad5SJay Sternberg 743a7a7cbe3SChaitanya Kulkarni done: 744a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 745a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 746a7a7cbe3SChaitanya Kulkarni 74786eea289SKeith Busch return BLK_STS_OK; 74886eea289SKeith Busch 74986eea289SKeith Busch bad_sgl: 750d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 751d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 752d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 75386eea289SKeith Busch return BLK_STS_IOERR; 75457dacad5SJay Sternberg } 75557dacad5SJay Sternberg 756a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 757a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 758a7a7cbe3SChaitanya Kulkarni { 759a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 760a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 761a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 762a7a7cbe3SChaitanya Kulkarni } 763a7a7cbe3SChaitanya Kulkarni 764a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 765a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 766a7a7cbe3SChaitanya Kulkarni { 767a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 768a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 769a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 770a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 771a7a7cbe3SChaitanya Kulkarni } else { 772a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 773a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 774a7a7cbe3SChaitanya Kulkarni } 775a7a7cbe3SChaitanya Kulkarni } 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 778b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 779a7a7cbe3SChaitanya Kulkarni { 780a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 781a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 782a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 783a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 784a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 785b0f2853bSChristoph Hellwig int i = 0; 786a7a7cbe3SChaitanya Kulkarni 787a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 788a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 789a7a7cbe3SChaitanya Kulkarni 790b0f2853bSChristoph Hellwig if (entries == 1) { 791a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 792a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 793a7a7cbe3SChaitanya Kulkarni } 794a7a7cbe3SChaitanya Kulkarni 795a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 796a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 797a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 798a7a7cbe3SChaitanya Kulkarni } else { 799a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 800a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 801a7a7cbe3SChaitanya Kulkarni } 802a7a7cbe3SChaitanya Kulkarni 803a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 804a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 805a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 806a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 807a7a7cbe3SChaitanya Kulkarni } 808a7a7cbe3SChaitanya Kulkarni 809a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 810a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 811a7a7cbe3SChaitanya Kulkarni 812a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 813a7a7cbe3SChaitanya Kulkarni 814a7a7cbe3SChaitanya Kulkarni do { 815a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 816a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 817a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 818a7a7cbe3SChaitanya Kulkarni 819a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 820a7a7cbe3SChaitanya Kulkarni if (!sg_list) 821a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 822a7a7cbe3SChaitanya Kulkarni 823a7a7cbe3SChaitanya Kulkarni i = 0; 824a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 825a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 826a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 827a7a7cbe3SChaitanya Kulkarni } 828a7a7cbe3SChaitanya Kulkarni 829a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 830a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 831b0f2853bSChristoph Hellwig } while (--entries > 0); 832a7a7cbe3SChaitanya Kulkarni 833a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 834a7a7cbe3SChaitanya Kulkarni } 835a7a7cbe3SChaitanya Kulkarni 836fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 837b131c61dSChristoph Hellwig struct nvme_command *cmnd) 83857dacad5SJay Sternberg { 839f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 840ba1ca37eSChristoph Hellwig struct request_queue *q = req->q; 841ba1ca37eSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 842ba1ca37eSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 843fc17b653SChristoph Hellwig blk_status_t ret = BLK_STS_IOERR; 844b0f2853bSChristoph Hellwig int nr_mapped; 84557dacad5SJay Sternberg 846f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 847ba1ca37eSChristoph Hellwig iod->nents = blk_rq_map_sg(q, req, iod->sg); 848ba1ca37eSChristoph Hellwig if (!iod->nents) 849ba1ca37eSChristoph Hellwig goto out; 850ba1ca37eSChristoph Hellwig 851fc17b653SChristoph Hellwig ret = BLK_STS_RESOURCE; 852e0596ab2SLogan Gunthorpe 853e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 854e0596ab2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg(dev->dev, iod->sg, iod->nents, 855e0596ab2SLogan Gunthorpe dma_dir); 856e0596ab2SLogan Gunthorpe else 857e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 858e0596ab2SLogan Gunthorpe dma_dir, DMA_ATTR_NO_WARN); 859b0f2853bSChristoph Hellwig if (!nr_mapped) 860ba1ca37eSChristoph Hellwig goto out; 861ba1ca37eSChristoph Hellwig 862955b1b5aSMinwoo Im if (iod->use_sgl) 863b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 864a7a7cbe3SChaitanya Kulkarni else 865a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 866a7a7cbe3SChaitanya Kulkarni 86786eea289SKeith Busch if (ret != BLK_STS_OK) 868ba1ca37eSChristoph Hellwig goto out_unmap; 869ba1ca37eSChristoph Hellwig 870fc17b653SChristoph Hellwig ret = BLK_STS_IOERR; 871ba1ca37eSChristoph Hellwig if (blk_integrity_rq(req)) { 872ba1ca37eSChristoph Hellwig if (blk_rq_count_integrity_sg(q, req->bio) != 1) 873ba1ca37eSChristoph Hellwig goto out_unmap; 874ba1ca37eSChristoph Hellwig 875bf684057SChristoph Hellwig sg_init_table(&iod->meta_sg, 1); 876bf684057SChristoph Hellwig if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1) 877ba1ca37eSChristoph Hellwig goto out_unmap; 878ba1ca37eSChristoph Hellwig 879bf684057SChristoph Hellwig if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir)) 880ba1ca37eSChristoph Hellwig goto out_unmap; 8813045c0d0SChaitanya Kulkarni 8823045c0d0SChaitanya Kulkarni cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg)); 88357dacad5SJay Sternberg } 88457dacad5SJay Sternberg 885fc17b653SChristoph Hellwig return BLK_STS_OK; 886ba1ca37eSChristoph Hellwig 887ba1ca37eSChristoph Hellwig out_unmap: 888ba1ca37eSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 889ba1ca37eSChristoph Hellwig out: 890ba1ca37eSChristoph Hellwig return ret; 89157dacad5SJay Sternberg } 89257dacad5SJay Sternberg 893f4800d6dSChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 894d4f6c3abSChristoph Hellwig { 895f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 896d4f6c3abSChristoph Hellwig enum dma_data_direction dma_dir = rq_data_dir(req) ? 897d4f6c3abSChristoph Hellwig DMA_TO_DEVICE : DMA_FROM_DEVICE; 898d4f6c3abSChristoph Hellwig 899d4f6c3abSChristoph Hellwig if (iod->nents) { 900e0596ab2SLogan Gunthorpe /* P2PDMA requests do not need to be unmapped */ 901e0596ab2SLogan Gunthorpe if (!is_pci_p2pdma_page(sg_page(iod->sg))) 902d4f6c3abSChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir); 903e0596ab2SLogan Gunthorpe 904f7f1fc36SMax Gurtovoy if (blk_integrity_rq(req)) 905bf684057SChristoph Hellwig dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir); 906d4f6c3abSChristoph Hellwig } 907d4f6c3abSChristoph Hellwig 908f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 909f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 91057dacad5SJay Sternberg } 91157dacad5SJay Sternberg 91257dacad5SJay Sternberg /* 91357dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 91457dacad5SJay Sternberg */ 915fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 91657dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 91757dacad5SJay Sternberg { 91857dacad5SJay Sternberg struct nvme_ns *ns = hctx->queue->queuedata; 91957dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92057dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92157dacad5SJay Sternberg struct request *req = bd->rq; 922ba1ca37eSChristoph Hellwig struct nvme_command cmnd; 923ebe6d874SChristoph Hellwig blk_status_t ret; 92457dacad5SJay Sternberg 925d1f06f4aSJens Axboe /* 926d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 927d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 928d1f06f4aSJens Axboe */ 9294e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 930d1f06f4aSJens Axboe return BLK_STS_IOERR; 931d1f06f4aSJens Axboe 932f9d03f96SChristoph Hellwig ret = nvme_setup_cmd(ns, req, &cmnd); 933fc17b653SChristoph Hellwig if (ret) 934f4800d6dSChristoph Hellwig return ret; 93557dacad5SJay Sternberg 936b131c61dSChristoph Hellwig ret = nvme_init_iod(req, dev); 937fc17b653SChristoph Hellwig if (ret) 938f9d03f96SChristoph Hellwig goto out_free_cmd; 93957dacad5SJay Sternberg 940fc17b653SChristoph Hellwig if (blk_rq_nr_phys_segments(req)) { 941b131c61dSChristoph Hellwig ret = nvme_map_data(dev, req, &cmnd); 942fc17b653SChristoph Hellwig if (ret) 943f9d03f96SChristoph Hellwig goto out_cleanup_iod; 944fc17b653SChristoph Hellwig } 945ba1ca37eSChristoph Hellwig 946aae239e1SChristoph Hellwig blk_mq_start_request(req); 94704f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &cmnd, bd->last); 948fc17b653SChristoph Hellwig return BLK_STS_OK; 949f9d03f96SChristoph Hellwig out_cleanup_iod: 950f4800d6dSChristoph Hellwig nvme_free_iod(dev, req); 951f9d03f96SChristoph Hellwig out_free_cmd: 952f9d03f96SChristoph Hellwig nvme_cleanup_cmd(req); 953ba1ca37eSChristoph Hellwig return ret; 95457dacad5SJay Sternberg } 95557dacad5SJay Sternberg 95677f02a7aSChristoph Hellwig static void nvme_pci_complete_rq(struct request *req) 957eee417b0SChristoph Hellwig { 958f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 959eee417b0SChristoph Hellwig 96077f02a7aSChristoph Hellwig nvme_unmap_data(iod->nvmeq->dev, req); 96177f02a7aSChristoph Hellwig nvme_complete_rq(req); 96257dacad5SJay Sternberg } 96357dacad5SJay Sternberg 964d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 965750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 966d783e0bdSMarta Rybczynska { 967750dde44SChristoph Hellwig return (le16_to_cpu(nvmeq->cqes[nvmeq->cq_head].status) & 1) == 968750dde44SChristoph Hellwig nvmeq->cq_phase; 969d783e0bdSMarta Rybczynska } 970d783e0bdSMarta Rybczynska 971eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 97257dacad5SJay Sternberg { 973eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 97457dacad5SJay Sternberg 975eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 976eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 977eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 978eb281c82SSagi Grimberg } 979adf68f21SChristoph Hellwig 9805cb525c8SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx) 98157dacad5SJay Sternberg { 9825cb525c8SJens Axboe volatile struct nvme_completion *cqe = &nvmeq->cqes[idx]; 98357dacad5SJay Sternberg struct request *req; 984adf68f21SChristoph Hellwig 98583a12fb7SSagi Grimberg if (unlikely(cqe->command_id >= nvmeq->q_depth)) { 9861b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 987aae239e1SChristoph Hellwig "invalid id %d completed on queue %d\n", 98883a12fb7SSagi Grimberg cqe->command_id, le16_to_cpu(cqe->sq_id)); 98983a12fb7SSagi Grimberg return; 990aae239e1SChristoph Hellwig } 991aae239e1SChristoph Hellwig 992adf68f21SChristoph Hellwig /* 993adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 994adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 995adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 996adf68f21SChristoph Hellwig * for them but rather special case them here. 997adf68f21SChristoph Hellwig */ 998adf68f21SChristoph Hellwig if (unlikely(nvmeq->qid == 0 && 99938dabe21SKeith Busch cqe->command_id >= NVME_AQ_BLK_MQ_DEPTH)) { 10007bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 100183a12fb7SSagi Grimberg cqe->status, &cqe->result); 1002a0fa9647SJens Axboe return; 100357dacad5SJay Sternberg } 100457dacad5SJay Sternberg 100583a12fb7SSagi Grimberg req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id); 100683a12fb7SSagi Grimberg nvme_end_request(req, cqe->status, cqe->result); 100783a12fb7SSagi Grimberg } 100857dacad5SJay Sternberg 10095cb525c8SJens Axboe static void nvme_complete_cqes(struct nvme_queue *nvmeq, u16 start, u16 end) 101083a12fb7SSagi Grimberg { 10115cb525c8SJens Axboe while (start != end) { 10125cb525c8SJens Axboe nvme_handle_cqe(nvmeq, start); 10135cb525c8SJens Axboe if (++start == nvmeq->q_depth) 10145cb525c8SJens Axboe start = 0; 10155cb525c8SJens Axboe } 10165cb525c8SJens Axboe } 101783a12fb7SSagi Grimberg 10185cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10195cb525c8SJens Axboe { 1020920d13a8SSagi Grimberg if (++nvmeq->cq_head == nvmeq->q_depth) { 1021920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1022920d13a8SSagi Grimberg nvmeq->cq_phase = !nvmeq->cq_phase; 1023920d13a8SSagi Grimberg } 1024a0fa9647SJens Axboe } 1025a0fa9647SJens Axboe 10261052b8acSJens Axboe static inline int nvme_process_cq(struct nvme_queue *nvmeq, u16 *start, 10271052b8acSJens Axboe u16 *end, unsigned int tag) 1028a0fa9647SJens Axboe { 10291052b8acSJens Axboe int found = 0; 103083a12fb7SSagi Grimberg 10315cb525c8SJens Axboe *start = nvmeq->cq_head; 10321052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10331052b8acSJens Axboe if (tag == -1U || nvmeq->cqes[nvmeq->cq_head].command_id == tag) 10341052b8acSJens Axboe found++; 10355cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 103657dacad5SJay Sternberg } 10375cb525c8SJens Axboe *end = nvmeq->cq_head; 103857dacad5SJay Sternberg 10395cb525c8SJens Axboe if (*start != *end) 1040eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10415cb525c8SJens Axboe return found; 104257dacad5SJay Sternberg } 104357dacad5SJay Sternberg 104457dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 104557dacad5SJay Sternberg { 104657dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 104768fa9dbeSJens Axboe irqreturn_t ret = IRQ_NONE; 10485cb525c8SJens Axboe u16 start, end; 10495cb525c8SJens Axboe 10503a7afd8eSChristoph Hellwig /* 10513a7afd8eSChristoph Hellwig * The rmb/wmb pair ensures we see all updates from a previous run of 10523a7afd8eSChristoph Hellwig * the irq handler, even if that was on another CPU. 10533a7afd8eSChristoph Hellwig */ 10543a7afd8eSChristoph Hellwig rmb(); 105568fa9dbeSJens Axboe if (nvmeq->cq_head != nvmeq->last_cq_head) 105668fa9dbeSJens Axboe ret = IRQ_HANDLED; 10575cb525c8SJens Axboe nvme_process_cq(nvmeq, &start, &end, -1); 105868fa9dbeSJens Axboe nvmeq->last_cq_head = nvmeq->cq_head; 10593a7afd8eSChristoph Hellwig wmb(); 10605cb525c8SJens Axboe 106168fa9dbeSJens Axboe if (start != end) { 10625cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 10635cb525c8SJens Axboe return IRQ_HANDLED; 106457dacad5SJay Sternberg } 106557dacad5SJay Sternberg 106668fa9dbeSJens Axboe return ret; 106757dacad5SJay Sternberg } 106857dacad5SJay Sternberg 106957dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 107057dacad5SJay Sternberg { 107157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 1072750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 107357dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1074d783e0bdSMarta Rybczynska return IRQ_NONE; 107557dacad5SJay Sternberg } 107657dacad5SJay Sternberg 10770b2a8a9fSChristoph Hellwig /* 10780b2a8a9fSChristoph Hellwig * Poll for completions any queue, including those not dedicated to polling. 10790b2a8a9fSChristoph Hellwig * Can be called from any context. 10800b2a8a9fSChristoph Hellwig */ 10810b2a8a9fSChristoph Hellwig static int nvme_poll_irqdisable(struct nvme_queue *nvmeq, unsigned int tag) 1082a0fa9647SJens Axboe { 10833a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 10845cb525c8SJens Axboe u16 start, end; 10851052b8acSJens Axboe int found; 1086a0fa9647SJens Axboe 10873a7afd8eSChristoph Hellwig /* 10883a7afd8eSChristoph Hellwig * For a poll queue we need to protect against the polling thread 10893a7afd8eSChristoph Hellwig * using the CQ lock. For normal interrupt driven threads we have 10903a7afd8eSChristoph Hellwig * to disable the interrupt to avoid racing with it. 10913a7afd8eSChristoph Hellwig */ 10923a7afd8eSChristoph Hellwig if (nvmeq->cq_vector == -1) 10933a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 10943a7afd8eSChristoph Hellwig else 10953a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 10965cb525c8SJens Axboe found = nvme_process_cq(nvmeq, &start, &end, tag); 10973a7afd8eSChristoph Hellwig if (nvmeq->cq_vector == -1) 10983a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 10993a7afd8eSChristoph Hellwig else 11003a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1101442e19b7SSagi Grimberg 11025cb525c8SJens Axboe nvme_complete_cqes(nvmeq, start, end); 1103442e19b7SSagi Grimberg return found; 1104a0fa9647SJens Axboe } 1105a0fa9647SJens Axboe 11069743139cSJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx) 11077776db1cSKeith Busch { 11087776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1109dabcefabSJens Axboe u16 start, end; 1110dabcefabSJens Axboe bool found; 1111dabcefabSJens Axboe 1112dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1113dabcefabSJens Axboe return 0; 1114dabcefabSJens Axboe 11153a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 11169743139cSJens Axboe found = nvme_process_cq(nvmeq, &start, &end, -1); 11173a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1118dabcefabSJens Axboe 1119dabcefabSJens Axboe nvme_complete_cqes(nvmeq, start, end); 1120dabcefabSJens Axboe return found; 1121dabcefabSJens Axboe } 1122dabcefabSJens Axboe 1123ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 112457dacad5SJay Sternberg { 1125f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1126147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 112757dacad5SJay Sternberg struct nvme_command c; 112857dacad5SJay Sternberg 112957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 113057dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1131ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 113204f3eafdSJens Axboe nvme_submit_cmd(nvmeq, &c, true); 113357dacad5SJay Sternberg } 113457dacad5SJay Sternberg 113557dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 113657dacad5SJay Sternberg { 113757dacad5SJay Sternberg struct nvme_command c; 113857dacad5SJay Sternberg 113957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 114057dacad5SJay Sternberg c.delete_queue.opcode = opcode; 114157dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 114257dacad5SJay Sternberg 11431c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 114457dacad5SJay Sternberg } 114557dacad5SJay Sternberg 114657dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1147a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 114857dacad5SJay Sternberg { 114957dacad5SJay Sternberg struct nvme_command c; 11504b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11514b04cc6aSJens Axboe 11524b04cc6aSJens Axboe if (vector != -1) 11534b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 115457dacad5SJay Sternberg 115557dacad5SJay Sternberg /* 115616772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 115757dacad5SJay Sternberg * is attached to the request. 115857dacad5SJay Sternberg */ 115957dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 116057dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 116157dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 116257dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 116357dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 116457dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 11654b04cc6aSJens Axboe if (vector != -1) 1166a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 11674b04cc6aSJens Axboe else 11684b04cc6aSJens Axboe c.create_cq.irq_vector = 0; 116957dacad5SJay Sternberg 11701c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 117157dacad5SJay Sternberg } 117257dacad5SJay Sternberg 117357dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 117457dacad5SJay Sternberg struct nvme_queue *nvmeq) 117557dacad5SJay Sternberg { 11769abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 117757dacad5SJay Sternberg struct nvme_command c; 117881c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 117957dacad5SJay Sternberg 118057dacad5SJay Sternberg /* 11819abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11829abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11839abd68efSJens Axboe * URGENT. 11849abd68efSJens Axboe */ 11859abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11869abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11879abd68efSJens Axboe 11889abd68efSJens Axboe /* 118916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 119057dacad5SJay Sternberg * is attached to the request. 119157dacad5SJay Sternberg */ 119257dacad5SJay Sternberg memset(&c, 0, sizeof(c)); 119357dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 119457dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 119557dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 119657dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 119757dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 119857dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 119957dacad5SJay Sternberg 12001c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120157dacad5SJay Sternberg } 120257dacad5SJay Sternberg 120357dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 120457dacad5SJay Sternberg { 120557dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 120657dacad5SJay Sternberg } 120757dacad5SJay Sternberg 120857dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 120957dacad5SJay Sternberg { 121057dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 12132a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 121457dacad5SJay Sternberg { 1215f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1216f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 121757dacad5SJay Sternberg 121827fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 121927fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1220e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1221e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 122257dacad5SJay Sternberg } 122357dacad5SJay Sternberg 1224b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1225b2a0eb1aSKeith Busch { 1226b2a0eb1aSKeith Busch 1227b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1228b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1229b2a0eb1aSKeith Busch */ 1230b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1231b2a0eb1aSKeith Busch 1232ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1233ad70062cSJianchao Wang switch (dev->ctrl.state) { 1234ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1235ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1236b2a0eb1aSKeith Busch return false; 1237ad70062cSJianchao Wang default: 1238ad70062cSJianchao Wang break; 1239ad70062cSJianchao Wang } 1240b2a0eb1aSKeith Busch 1241b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1242b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1243b2a0eb1aSKeith Busch */ 1244b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1245b2a0eb1aSKeith Busch return false; 1246b2a0eb1aSKeith Busch 1247b2a0eb1aSKeith Busch return true; 1248b2a0eb1aSKeith Busch } 1249b2a0eb1aSKeith Busch 1250b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1251b2a0eb1aSKeith Busch { 1252b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1253b2a0eb1aSKeith Busch u16 pci_status; 1254b2a0eb1aSKeith Busch int result; 1255b2a0eb1aSKeith Busch 1256b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1257b2a0eb1aSKeith Busch &pci_status); 1258b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1259b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1260b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1261b2a0eb1aSKeith Busch csts, pci_status); 1262b2a0eb1aSKeith Busch else 1263b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1264b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1265b2a0eb1aSKeith Busch csts, result); 1266b2a0eb1aSKeith Busch } 1267b2a0eb1aSKeith Busch 126831c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 126957dacad5SJay Sternberg { 1270f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1271f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 127257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 127357dacad5SJay Sternberg struct request *abort_req; 127457dacad5SJay Sternberg struct nvme_command cmd; 1275b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1276b2a0eb1aSKeith Busch 1277651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1278651438bbSWen Xiong * the recovery mechanism will surely fail. 1279651438bbSWen Xiong */ 1280651438bbSWen Xiong mb(); 1281651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1282651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1283651438bbSWen Xiong 1284b2a0eb1aSKeith Busch /* 1285b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1286b2a0eb1aSKeith Busch */ 1287b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1288b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1289b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1290d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1291db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1292b2a0eb1aSKeith Busch } 129357dacad5SJay Sternberg 129431c7c7d2SChristoph Hellwig /* 12957776db1cSKeith Busch * Did we miss an interrupt? 12967776db1cSKeith Busch */ 12970b2a8a9fSChristoph Hellwig if (nvme_poll_irqdisable(nvmeq, req->tag)) { 12987776db1cSKeith Busch dev_warn(dev->ctrl.device, 12997776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13007776db1cSKeith Busch req->tag, nvmeq->qid); 1301db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13027776db1cSKeith Busch } 13037776db1cSKeith Busch 13047776db1cSKeith Busch /* 1305fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1306fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1307fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1308db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1309fd634f41SChristoph Hellwig */ 13104244140dSKeith Busch switch (dev->ctrl.state) { 13114244140dSKeith Busch case NVME_CTRL_CONNECTING: 13124244140dSKeith Busch case NVME_CTRL_RESETTING: 1313b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1314fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1315fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 1316a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 131727fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1318db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13194244140dSKeith Busch default: 13204244140dSKeith Busch break; 1321fd634f41SChristoph Hellwig } 1322fd634f41SChristoph Hellwig 1323fd634f41SChristoph Hellwig /* 1324e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1325e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1326e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 132731c7c7d2SChristoph Hellwig */ 1328f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13291b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 133057dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 133157dacad5SJay Sternberg req->tag, nvmeq->qid); 1332a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1333d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1334e1569a16SKeith Busch 133527fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1336db8c48e4SChristoph Hellwig return BLK_EH_DONE; 133757dacad5SJay Sternberg } 133857dacad5SJay Sternberg 1339e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1340e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1341e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1342e7a2a87dSChristoph Hellwig } 13437bf7d778SKeith Busch iod->aborted = 1; 134457dacad5SJay Sternberg 134557dacad5SJay Sternberg memset(&cmd, 0, sizeof(cmd)); 134657dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 134757dacad5SJay Sternberg cmd.abort.cid = req->tag; 134857dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 134957dacad5SJay Sternberg 13501b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 13511b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 135257dacad5SJay Sternberg req->tag, nvmeq->qid); 1353e7a2a87dSChristoph Hellwig 1354e7a2a87dSChristoph Hellwig abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd, 1355eb71f435SChristoph Hellwig BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 13566bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13576bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 135831c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 135957dacad5SJay Sternberg } 136057dacad5SJay Sternberg 1361e7a2a87dSChristoph Hellwig abort_req->timeout = ADMIN_TIMEOUT; 1362e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1363e7a2a87dSChristoph Hellwig blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio); 136457dacad5SJay Sternberg 136557dacad5SJay Sternberg /* 136657dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 136757dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 136857dacad5SJay Sternberg * as the device then is in a faulty state. 136957dacad5SJay Sternberg */ 137057dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 137157dacad5SJay Sternberg } 137257dacad5SJay Sternberg 137357dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 137457dacad5SJay Sternberg { 137557dacad5SJay Sternberg dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth), 137657dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 137763223078SChristoph Hellwig if (!nvmeq->sq_cmds) 137863223078SChristoph Hellwig return; 13790f238ff5SLogan Gunthorpe 138063223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 13810f238ff5SLogan Gunthorpe pci_free_p2pmem(to_pci_dev(nvmeq->q_dmadev), 138263223078SChristoph Hellwig nvmeq->sq_cmds, SQ_SIZE(nvmeq->q_depth)); 138363223078SChristoph Hellwig } else { 138463223078SChristoph Hellwig dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth), 138563223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 13860f238ff5SLogan Gunthorpe } 138757dacad5SJay Sternberg } 138857dacad5SJay Sternberg 138957dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 139057dacad5SJay Sternberg { 139157dacad5SJay Sternberg int i; 139257dacad5SJay Sternberg 1393d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1394d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1395147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 139657dacad5SJay Sternberg } 139757dacad5SJay Sternberg } 139857dacad5SJay Sternberg 139957dacad5SJay Sternberg /** 140057dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 140140581d1aSBart Van Assche * @nvmeq: queue to suspend 140257dacad5SJay Sternberg */ 140357dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 140457dacad5SJay Sternberg { 14054e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 140657dacad5SJay Sternberg return 1; 140757dacad5SJay Sternberg 14084e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1409d1f06f4aSJens Axboe mb(); 141057dacad5SJay Sternberg 14114e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14121c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 1413c81545f9SSagi Grimberg blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q); 14144e224106SChristoph Hellwig if (nvmeq->cq_vector == -1) 14154e224106SChristoph Hellwig return 0; 14164e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 14174e224106SChristoph Hellwig nvmeq->cq_vector = -1; 141857dacad5SJay Sternberg return 0; 141957dacad5SJay Sternberg } 142057dacad5SJay Sternberg 1421a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 142257dacad5SJay Sternberg { 1423147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 142457dacad5SJay Sternberg 1425a5cdb68cSKeith Busch if (shutdown) 1426a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1427a5cdb68cSKeith Busch else 142820d0dfe6SSagi Grimberg nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 142957dacad5SJay Sternberg 14300b2a8a9fSChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 143157dacad5SJay Sternberg } 143257dacad5SJay Sternberg 143357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 143457dacad5SJay Sternberg int entry_size) 143557dacad5SJay Sternberg { 143657dacad5SJay Sternberg int q_depth = dev->q_depth; 14375fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14385fd4ce1bSChristoph Hellwig dev->ctrl.page_size); 143957dacad5SJay Sternberg 144057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 144157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14425fd4ce1bSChristoph Hellwig mem_per_q = round_down(mem_per_q, dev->ctrl.page_size); 144357dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg /* 144657dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 144757dacad5SJay Sternberg * would be better to map queues in system memory with the 144857dacad5SJay Sternberg * original depth 144957dacad5SJay Sternberg */ 145057dacad5SJay Sternberg if (q_depth < 64) 145157dacad5SJay Sternberg return -ENOMEM; 145257dacad5SJay Sternberg } 145357dacad5SJay Sternberg 145457dacad5SJay Sternberg return q_depth; 145557dacad5SJay Sternberg } 145657dacad5SJay Sternberg 145757dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 145857dacad5SJay Sternberg int qid, int depth) 145957dacad5SJay Sternberg { 14600f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1461815c6704SKeith Busch 14620f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14630f238ff5SLogan Gunthorpe nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(depth)); 14640f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 14650f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 146663223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 146763223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 146863223078SChristoph Hellwig return 0; 146963223078SChristoph Hellwig } 14700f238ff5SLogan Gunthorpe } 14710f238ff5SLogan Gunthorpe 147257dacad5SJay Sternberg nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth), 147357dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 147457dacad5SJay Sternberg if (!nvmeq->sq_cmds) 147557dacad5SJay Sternberg return -ENOMEM; 147657dacad5SJay Sternberg return 0; 147757dacad5SJay Sternberg } 147857dacad5SJay Sternberg 1479a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 148057dacad5SJay Sternberg { 1481147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 148257dacad5SJay Sternberg 148362314e40SKeith Busch if (dev->ctrl.queue_count > qid) 148462314e40SKeith Busch return 0; 148557dacad5SJay Sternberg 148657dacad5SJay Sternberg nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth), 148757dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 148857dacad5SJay Sternberg if (!nvmeq->cqes) 148957dacad5SJay Sternberg goto free_nvmeq; 149057dacad5SJay Sternberg 149157dacad5SJay Sternberg if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth)) 149257dacad5SJay Sternberg goto free_cqdma; 149357dacad5SJay Sternberg 149457dacad5SJay Sternberg nvmeq->q_dmadev = dev->dev; 149557dacad5SJay Sternberg nvmeq->dev = dev; 14961ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 14973a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 149857dacad5SJay Sternberg nvmeq->cq_head = 0; 149957dacad5SJay Sternberg nvmeq->cq_phase = 1; 150057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 150157dacad5SJay Sternberg nvmeq->q_depth = depth; 150257dacad5SJay Sternberg nvmeq->qid = qid; 150357dacad5SJay Sternberg nvmeq->cq_vector = -1; 1504d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 150557dacad5SJay Sternberg 1506147b27e4SSagi Grimberg return 0; 150757dacad5SJay Sternberg 150857dacad5SJay Sternberg free_cqdma: 150957dacad5SJay Sternberg dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes, 151057dacad5SJay Sternberg nvmeq->cq_dma_addr); 151157dacad5SJay Sternberg free_nvmeq: 1512147b27e4SSagi Grimberg return -ENOMEM; 151357dacad5SJay Sternberg } 151457dacad5SJay Sternberg 1515dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 151657dacad5SJay Sternberg { 15170ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15180ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15190ff199cbSChristoph Hellwig 15200ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15210ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15220ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15230ff199cbSChristoph Hellwig } else { 15240ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15250ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15260ff199cbSChristoph Hellwig } 152757dacad5SJay Sternberg } 152857dacad5SJay Sternberg 152957dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 153057dacad5SJay Sternberg { 153157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 153257dacad5SJay Sternberg 153357dacad5SJay Sternberg nvmeq->sq_tail = 0; 153404f3eafdSJens Axboe nvmeq->last_sq_tail = 0; 153557dacad5SJay Sternberg nvmeq->cq_head = 0; 153657dacad5SJay Sternberg nvmeq->cq_phase = 1; 153757dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 153857dacad5SJay Sternberg memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth)); 1539f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 154057dacad5SJay Sternberg dev->online_queues++; 15413a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 154257dacad5SJay Sternberg } 154357dacad5SJay Sternberg 15444b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 154557dacad5SJay Sternberg { 154657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 154757dacad5SJay Sternberg int result; 1548a8e3e0bbSJianchao Wang s16 vector; 154957dacad5SJay Sternberg 1550d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1551d1ed6aa1SChristoph Hellwig 155222b55601SKeith Busch /* 155322b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 155422b55601SKeith Busch * has only one vector available. 155522b55601SKeith Busch */ 15564b04cc6aSJens Axboe if (!polled) 1557a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 15584b04cc6aSJens Axboe else 15594b04cc6aSJens Axboe vector = -1; 15604b04cc6aSJens Axboe 1561a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1562ded45505SKeith Busch if (result) 1563ded45505SKeith Busch return result; 156457dacad5SJay Sternberg 156557dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 156657dacad5SJay Sternberg if (result < 0) 1567ded45505SKeith Busch return result; 1568ded45505SKeith Busch else if (result) 156957dacad5SJay Sternberg goto release_cq; 157057dacad5SJay Sternberg 1571a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 1572161b8be2SKeith Busch nvme_init_queue(nvmeq, qid); 15734b04cc6aSJens Axboe 15744b04cc6aSJens Axboe if (vector != -1) { 1575dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 157657dacad5SJay Sternberg if (result < 0) 157757dacad5SJay Sternberg goto release_sq; 15784b04cc6aSJens Axboe } 157957dacad5SJay Sternberg 15804e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 158157dacad5SJay Sternberg return result; 158257dacad5SJay Sternberg 158357dacad5SJay Sternberg release_sq: 1584a8e3e0bbSJianchao Wang nvmeq->cq_vector = -1; 1585f25a2dfcSJianchao Wang dev->online_queues--; 158657dacad5SJay Sternberg adapter_delete_sq(dev, qid); 158757dacad5SJay Sternberg release_cq: 158857dacad5SJay Sternberg adapter_delete_cq(dev, qid); 158957dacad5SJay Sternberg return result; 159057dacad5SJay Sternberg } 159157dacad5SJay Sternberg 1592f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 159357dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 159477f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 159557dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 159657dacad5SJay Sternberg .exit_hctx = nvme_admin_exit_hctx, 15970350815aSChristoph Hellwig .init_request = nvme_init_request, 159857dacad5SJay Sternberg .timeout = nvme_timeout, 159957dacad5SJay Sternberg }; 160057dacad5SJay Sternberg 1601f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1602376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1603376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1604376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1605376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1606376f7ef8SChristoph Hellwig .init_request = nvme_init_request, 1607376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1608376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1609c6d962aeSChristoph Hellwig .poll = nvme_poll, 1610dabcefabSJens Axboe }; 1611dabcefabSJens Axboe 161257dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 161357dacad5SJay Sternberg { 16141c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 161569d9a99cSKeith Busch /* 161669d9a99cSKeith Busch * If the controller was reset during removal, it's possible 161769d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 161869d9a99cSKeith Busch * queue to flush these to completion. 161969d9a99cSKeith Busch */ 1620c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 16211c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 162257dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 162357dacad5SJay Sternberg } 162457dacad5SJay Sternberg } 162557dacad5SJay Sternberg 162657dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 162757dacad5SJay Sternberg { 16281c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 162957dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 163057dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1631e3e9d50cSKeith Busch 163238dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 163357dacad5SJay Sternberg dev->admin_tagset.timeout = ADMIN_TIMEOUT; 163457dacad5SJay Sternberg dev->admin_tagset.numa_node = dev_to_node(dev->dev); 1635a7a7cbe3SChaitanya Kulkarni dev->admin_tagset.cmd_size = nvme_pci_cmd_size(dev, false); 1636d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 163757dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 163857dacad5SJay Sternberg 163957dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 164057dacad5SJay Sternberg return -ENOMEM; 164134b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 164257dacad5SJay Sternberg 16431c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 16441c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 164557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 164657dacad5SJay Sternberg return -ENOMEM; 164757dacad5SJay Sternberg } 16481c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 164957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 16501c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 165157dacad5SJay Sternberg return -ENODEV; 165257dacad5SJay Sternberg } 165357dacad5SJay Sternberg } else 1654c81545f9SSagi Grimberg blk_mq_unquiesce_queue(dev->ctrl.admin_q); 165557dacad5SJay Sternberg 165657dacad5SJay Sternberg return 0; 165757dacad5SJay Sternberg } 165857dacad5SJay Sternberg 165997f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 166097f6ef64SXu Yu { 166197f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 166297f6ef64SXu Yu } 166397f6ef64SXu Yu 166497f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 166597f6ef64SXu Yu { 166697f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 166797f6ef64SXu Yu 166897f6ef64SXu Yu if (size <= dev->bar_mapped_size) 166997f6ef64SXu Yu return 0; 167097f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 167197f6ef64SXu Yu return -ENOMEM; 167297f6ef64SXu Yu if (dev->bar) 167397f6ef64SXu Yu iounmap(dev->bar); 167497f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 167597f6ef64SXu Yu if (!dev->bar) { 167697f6ef64SXu Yu dev->bar_mapped_size = 0; 167797f6ef64SXu Yu return -ENOMEM; 167897f6ef64SXu Yu } 167997f6ef64SXu Yu dev->bar_mapped_size = size; 168097f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 168197f6ef64SXu Yu 168297f6ef64SXu Yu return 0; 168397f6ef64SXu Yu } 168497f6ef64SXu Yu 168501ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 168657dacad5SJay Sternberg { 168757dacad5SJay Sternberg int result; 168857dacad5SJay Sternberg u32 aqa; 168957dacad5SJay Sternberg struct nvme_queue *nvmeq; 169057dacad5SJay Sternberg 169197f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 169297f6ef64SXu Yu if (result < 0) 169397f6ef64SXu Yu return result; 169497f6ef64SXu Yu 16958ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 169620d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 169757dacad5SJay Sternberg 16987a67cbeaSChristoph Hellwig if (dev->subsystem && 16997a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17007a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 170157dacad5SJay Sternberg 170220d0dfe6SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl, dev->ctrl.cap); 170357dacad5SJay Sternberg if (result < 0) 170457dacad5SJay Sternberg return result; 170557dacad5SJay Sternberg 1706a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1707147b27e4SSagi Grimberg if (result) 1708147b27e4SSagi Grimberg return result; 170957dacad5SJay Sternberg 1710147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 171157dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 171257dacad5SJay Sternberg aqa |= aqa << 16; 171357dacad5SJay Sternberg 17147a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17157a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17167a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 171757dacad5SJay Sternberg 171820d0dfe6SSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl, dev->ctrl.cap); 171957dacad5SJay Sternberg if (result) 1720d4875622SKeith Busch return result; 172157dacad5SJay Sternberg 172257dacad5SJay Sternberg nvmeq->cq_vector = 0; 1723161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1724dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 172557dacad5SJay Sternberg if (result) { 172657dacad5SJay Sternberg nvmeq->cq_vector = -1; 1727d4875622SKeith Busch return result; 172857dacad5SJay Sternberg } 172957dacad5SJay Sternberg 17304e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 173157dacad5SJay Sternberg return result; 173257dacad5SJay Sternberg } 173357dacad5SJay Sternberg 1734749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 173557dacad5SJay Sternberg { 17364b04cc6aSJens Axboe unsigned i, max, rw_queues; 1737749941f2SChristoph Hellwig int ret = 0; 173857dacad5SJay Sternberg 1739d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1740a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1741749941f2SChristoph Hellwig ret = -ENOMEM; 174257dacad5SJay Sternberg break; 1743749941f2SChristoph Hellwig } 1744749941f2SChristoph Hellwig } 174557dacad5SJay Sternberg 1746d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1747e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1748e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1749e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17504b04cc6aSJens Axboe } else { 17514b04cc6aSJens Axboe rw_queues = max; 17524b04cc6aSJens Axboe } 17534b04cc6aSJens Axboe 1754949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17554b04cc6aSJens Axboe bool polled = i > rw_queues; 17564b04cc6aSJens Axboe 17574b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1758d4875622SKeith Busch if (ret) 175957dacad5SJay Sternberg break; 176057dacad5SJay Sternberg } 176157dacad5SJay Sternberg 1762749941f2SChristoph Hellwig /* 1763749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 17648adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 17658adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1766749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1767749941f2SChristoph Hellwig */ 1768749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 176957dacad5SJay Sternberg } 177057dacad5SJay Sternberg 1771202021c1SStephen Bates static ssize_t nvme_cmb_show(struct device *dev, 1772202021c1SStephen Bates struct device_attribute *attr, 1773202021c1SStephen Bates char *buf) 1774202021c1SStephen Bates { 1775202021c1SStephen Bates struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 1776202021c1SStephen Bates 1777c965809cSStephen Bates return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz : x%08x\n", 1778202021c1SStephen Bates ndev->cmbloc, ndev->cmbsz); 1779202021c1SStephen Bates } 1780202021c1SStephen Bates static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL); 1781202021c1SStephen Bates 178288de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 178357dacad5SJay Sternberg { 178488de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 178588de4598SChristoph Hellwig 178688de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 178788de4598SChristoph Hellwig } 178888de4598SChristoph Hellwig 178988de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 179088de4598SChristoph Hellwig { 179188de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 179288de4598SChristoph Hellwig } 179388de4598SChristoph Hellwig 1794f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 179557dacad5SJay Sternberg { 179688de4598SChristoph Hellwig u64 size, offset; 179757dacad5SJay Sternberg resource_size_t bar_size; 179857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 17998969f1f8SChristoph Hellwig int bar; 180057dacad5SJay Sternberg 18019fe5c59fSKeith Busch if (dev->cmb_size) 18029fe5c59fSKeith Busch return; 18039fe5c59fSKeith Busch 18047a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1805f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1806f65efd6dSChristoph Hellwig return; 1807202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 180857dacad5SJay Sternberg 180988de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 181088de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18118969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18128969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 181357dacad5SJay Sternberg 181457dacad5SJay Sternberg if (offset > bar_size) 1815f65efd6dSChristoph Hellwig return; 181657dacad5SJay Sternberg 181757dacad5SJay Sternberg /* 181857dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 181957dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 182057dacad5SJay Sternberg * the reported size of the BAR 182157dacad5SJay Sternberg */ 182257dacad5SJay Sternberg if (size > bar_size - offset) 182357dacad5SJay Sternberg size = bar_size - offset; 182457dacad5SJay Sternberg 18250f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18260f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18270f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1828f65efd6dSChristoph Hellwig return; 18290f238ff5SLogan Gunthorpe } 18300f238ff5SLogan Gunthorpe 183157dacad5SJay Sternberg dev->cmb_size = size; 18320f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18330f238ff5SLogan Gunthorpe 18340f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18350f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18360f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 1837f65efd6dSChristoph Hellwig 1838f65efd6dSChristoph Hellwig if (sysfs_add_file_to_group(&dev->ctrl.device->kobj, 1839f65efd6dSChristoph Hellwig &dev_attr_cmb.attr, NULL)) 1840f65efd6dSChristoph Hellwig dev_warn(dev->ctrl.device, 1841f65efd6dSChristoph Hellwig "failed to add sysfs attribute for CMB\n"); 184257dacad5SJay Sternberg } 184357dacad5SJay Sternberg 184457dacad5SJay Sternberg static inline void nvme_release_cmb(struct nvme_dev *dev) 184557dacad5SJay Sternberg { 18460f238ff5SLogan Gunthorpe if (dev->cmb_size) { 1847f63572dfSJon Derrick sysfs_remove_file_from_group(&dev->ctrl.device->kobj, 1848f63572dfSJon Derrick &dev_attr_cmb.attr, NULL); 18490f238ff5SLogan Gunthorpe dev->cmb_size = 0; 1850f63572dfSJon Derrick } 185157dacad5SJay Sternberg } 185257dacad5SJay Sternberg 185387ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 185457dacad5SJay Sternberg { 18554033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 185687ad72a5SChristoph Hellwig struct nvme_command c; 185787ad72a5SChristoph Hellwig int ret; 185887ad72a5SChristoph Hellwig 185987ad72a5SChristoph Hellwig memset(&c, 0, sizeof(c)); 186087ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 186187ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 186287ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 186387ad72a5SChristoph Hellwig c.features.dword12 = cpu_to_le32(dev->host_mem_size >> 186487ad72a5SChristoph Hellwig ilog2(dev->ctrl.page_size)); 186587ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 186687ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 186787ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 186887ad72a5SChristoph Hellwig 186987ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 187087ad72a5SChristoph Hellwig if (ret) { 187187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 187287ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 187387ad72a5SChristoph Hellwig ret, bits); 187487ad72a5SChristoph Hellwig } 187587ad72a5SChristoph Hellwig return ret; 187687ad72a5SChristoph Hellwig } 187787ad72a5SChristoph Hellwig 187887ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 187987ad72a5SChristoph Hellwig { 188087ad72a5SChristoph Hellwig int i; 188187ad72a5SChristoph Hellwig 188287ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 188387ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 188487ad72a5SChristoph Hellwig size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size; 188587ad72a5SChristoph Hellwig 188687ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i], 188787ad72a5SChristoph Hellwig le64_to_cpu(desc->addr)); 188887ad72a5SChristoph Hellwig } 188987ad72a5SChristoph Hellwig 189087ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 189187ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 18924033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 18934033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 18944033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 189587ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 18967e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 189787ad72a5SChristoph Hellwig } 189887ad72a5SChristoph Hellwig 189992dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 190092dc6895SChristoph Hellwig u32 chunk_size) 190187ad72a5SChristoph Hellwig { 190287ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 190392dc6895SChristoph Hellwig u32 max_entries, len; 19044033f35dSChristoph Hellwig dma_addr_t descs_dma; 19052ee0e4edSDan Carpenter int i = 0; 190687ad72a5SChristoph Hellwig void **bufs; 19076fbcde66SMinwoo Im u64 size, tmp; 190887ad72a5SChristoph Hellwig 190987ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 191087ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 191187ad72a5SChristoph Hellwig max_entries = tmp; 1912044a9df1SChristoph Hellwig 1913044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1914044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1915044a9df1SChristoph Hellwig 19164033f35dSChristoph Hellwig descs = dma_zalloc_coherent(dev->dev, max_entries * sizeof(*descs), 19174033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 191887ad72a5SChristoph Hellwig if (!descs) 191987ad72a5SChristoph Hellwig goto out; 192087ad72a5SChristoph Hellwig 192187ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 192287ad72a5SChristoph Hellwig if (!bufs) 192387ad72a5SChristoph Hellwig goto out_free_descs; 192487ad72a5SChristoph Hellwig 1925244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 192687ad72a5SChristoph Hellwig dma_addr_t dma_addr; 192787ad72a5SChristoph Hellwig 192850cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 192987ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 193087ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 193187ad72a5SChristoph Hellwig if (!bufs[i]) 193287ad72a5SChristoph Hellwig break; 193387ad72a5SChristoph Hellwig 193487ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 193587ad72a5SChristoph Hellwig descs[i].size = cpu_to_le32(len / dev->ctrl.page_size); 193687ad72a5SChristoph Hellwig i++; 193787ad72a5SChristoph Hellwig } 193887ad72a5SChristoph Hellwig 193992dc6895SChristoph Hellwig if (!size) 194087ad72a5SChristoph Hellwig goto out_free_bufs; 194187ad72a5SChristoph Hellwig 194287ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 194387ad72a5SChristoph Hellwig dev->host_mem_size = size; 194487ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19454033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 194687ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 194787ad72a5SChristoph Hellwig return 0; 194887ad72a5SChristoph Hellwig 194987ad72a5SChristoph Hellwig out_free_bufs: 195087ad72a5SChristoph Hellwig while (--i >= 0) { 195187ad72a5SChristoph Hellwig size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size; 195287ad72a5SChristoph Hellwig 195387ad72a5SChristoph Hellwig dma_free_coherent(dev->dev, size, bufs[i], 195487ad72a5SChristoph Hellwig le64_to_cpu(descs[i].addr)); 195587ad72a5SChristoph Hellwig } 195687ad72a5SChristoph Hellwig 195787ad72a5SChristoph Hellwig kfree(bufs); 195887ad72a5SChristoph Hellwig out_free_descs: 19594033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19604033f35dSChristoph Hellwig descs_dma); 196187ad72a5SChristoph Hellwig out: 196287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 196387ad72a5SChristoph Hellwig return -ENOMEM; 196487ad72a5SChristoph Hellwig } 196587ad72a5SChristoph Hellwig 196692dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 196792dc6895SChristoph Hellwig { 196892dc6895SChristoph Hellwig u32 chunk_size; 196992dc6895SChristoph Hellwig 197092dc6895SChristoph Hellwig /* start big and work our way down */ 197130f92d62SAkinobu Mita for (chunk_size = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 1972044a9df1SChristoph Hellwig chunk_size >= max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 197392dc6895SChristoph Hellwig chunk_size /= 2) { 197492dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 197592dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 197692dc6895SChristoph Hellwig return 0; 197792dc6895SChristoph Hellwig nvme_free_host_mem(dev); 197892dc6895SChristoph Hellwig } 197992dc6895SChristoph Hellwig } 198092dc6895SChristoph Hellwig 198192dc6895SChristoph Hellwig return -ENOMEM; 198292dc6895SChristoph Hellwig } 198392dc6895SChristoph Hellwig 19849620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 198587ad72a5SChristoph Hellwig { 198687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 198787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 198887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 198987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 19906fbcde66SMinwoo Im int ret; 199187ad72a5SChristoph Hellwig 199287ad72a5SChristoph Hellwig preferred = min(preferred, max); 199387ad72a5SChristoph Hellwig if (min > max) { 199487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199587ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 199687ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 199787ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 19989620cfbaSChristoph Hellwig return 0; 199987ad72a5SChristoph Hellwig } 200087ad72a5SChristoph Hellwig 200187ad72a5SChristoph Hellwig /* 200287ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 200387ad72a5SChristoph Hellwig */ 200487ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 200587ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 200687ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 200787ad72a5SChristoph Hellwig else 200887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 200987ad72a5SChristoph Hellwig } 201087ad72a5SChristoph Hellwig 201187ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 201292dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 201392dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 201492dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20159620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 201687ad72a5SChristoph Hellwig } 201787ad72a5SChristoph Hellwig 201892dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 201992dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 202092dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 202192dc6895SChristoph Hellwig } 202292dc6895SChristoph Hellwig 20239620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20249620cfbaSChristoph Hellwig if (ret) 202587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20269620cfbaSChristoph Hellwig return ret; 202757dacad5SJay Sternberg } 202857dacad5SJay Sternberg 20296451fe73SJens Axboe static void nvme_calc_io_queues(struct nvme_dev *dev, unsigned int irq_queues) 20303b6592f7SJens Axboe { 20313b6592f7SJens Axboe unsigned int this_w_queues = write_queues; 20323b6592f7SJens Axboe 20333b6592f7SJens Axboe /* 20343b6592f7SJens Axboe * Setup read/write queue split 20353b6592f7SJens Axboe */ 20366451fe73SJens Axboe if (irq_queues == 1) { 2037e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2038e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 20393b6592f7SJens Axboe return; 20403b6592f7SJens Axboe } 20413b6592f7SJens Axboe 20423b6592f7SJens Axboe /* 20433b6592f7SJens Axboe * If 'write_queues' is set, ensure it leaves room for at least 20443b6592f7SJens Axboe * one read queue 20453b6592f7SJens Axboe */ 20466451fe73SJens Axboe if (this_w_queues >= irq_queues) 20476451fe73SJens Axboe this_w_queues = irq_queues - 1; 20483b6592f7SJens Axboe 20493b6592f7SJens Axboe /* 20503b6592f7SJens Axboe * If 'write_queues' is set to zero, reads and writes will share 20513b6592f7SJens Axboe * a queue set. 20523b6592f7SJens Axboe */ 20533b6592f7SJens Axboe if (!this_w_queues) { 20546451fe73SJens Axboe dev->io_queues[HCTX_TYPE_DEFAULT] = irq_queues; 2055e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ] = 0; 20563b6592f7SJens Axboe } else { 2057e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT] = this_w_queues; 20586451fe73SJens Axboe dev->io_queues[HCTX_TYPE_READ] = irq_queues - this_w_queues; 20593b6592f7SJens Axboe } 20603b6592f7SJens Axboe } 20613b6592f7SJens Axboe 20626451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 20633b6592f7SJens Axboe { 20643b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 20653b6592f7SJens Axboe int irq_sets[2]; 20663b6592f7SJens Axboe struct irq_affinity affd = { 20673b6592f7SJens Axboe .pre_vectors = 1, 20683b6592f7SJens Axboe .nr_sets = ARRAY_SIZE(irq_sets), 20693b6592f7SJens Axboe .sets = irq_sets, 20703b6592f7SJens Axboe }; 207130e06628SJens Axboe int result = 0; 20726451fe73SJens Axboe unsigned int irq_queues, this_p_queues; 20736451fe73SJens Axboe 20746451fe73SJens Axboe /* 20756451fe73SJens Axboe * Poll queues don't need interrupts, but we need at least one IO 20766451fe73SJens Axboe * queue left over for non-polled IO. 20776451fe73SJens Axboe */ 20786451fe73SJens Axboe this_p_queues = poll_queues; 20796451fe73SJens Axboe if (this_p_queues >= nr_io_queues) { 20806451fe73SJens Axboe this_p_queues = nr_io_queues - 1; 20816451fe73SJens Axboe irq_queues = 1; 20826451fe73SJens Axboe } else { 20836451fe73SJens Axboe irq_queues = nr_io_queues - this_p_queues; 20846451fe73SJens Axboe } 20856451fe73SJens Axboe dev->io_queues[HCTX_TYPE_POLL] = this_p_queues; 20863b6592f7SJens Axboe 20873b6592f7SJens Axboe /* 20883b6592f7SJens Axboe * For irq sets, we have to ask for minvec == maxvec. This passes 20893b6592f7SJens Axboe * any reduction back to us, so we can adjust our queue counts and 20903b6592f7SJens Axboe * IRQ vector needs. 20913b6592f7SJens Axboe */ 20923b6592f7SJens Axboe do { 20936451fe73SJens Axboe nvme_calc_io_queues(dev, irq_queues); 2094e20ba6e1SChristoph Hellwig irq_sets[0] = dev->io_queues[HCTX_TYPE_DEFAULT]; 2095e20ba6e1SChristoph Hellwig irq_sets[1] = dev->io_queues[HCTX_TYPE_READ]; 20963b6592f7SJens Axboe if (!irq_sets[1]) 20973b6592f7SJens Axboe affd.nr_sets = 1; 20983b6592f7SJens Axboe 20993b6592f7SJens Axboe /* 2100db29eb05SJens Axboe * If we got a failure and we're down to asking for just 2101db29eb05SJens Axboe * 1 + 1 queues, just ask for a single vector. We'll share 2102db29eb05SJens Axboe * that between the single IO queue and the admin queue. 21033b6592f7SJens Axboe */ 21046451fe73SJens Axboe if (result >= 0 && irq_queues > 1) 21056451fe73SJens Axboe irq_queues = irq_sets[0] + irq_sets[1] + 1; 21063b6592f7SJens Axboe 21076451fe73SJens Axboe result = pci_alloc_irq_vectors_affinity(pdev, irq_queues, 21086451fe73SJens Axboe irq_queues, 21093b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 21103b6592f7SJens Axboe 21113b6592f7SJens Axboe /* 2112db29eb05SJens Axboe * Need to reduce our vec counts. If we get ENOSPC, the 2113db29eb05SJens Axboe * platform should support mulitple vecs, we just need 2114db29eb05SJens Axboe * to decrease our ask. If we get EINVAL, the platform 2115db29eb05SJens Axboe * likely does not. Back down to ask for just one vector. 21163b6592f7SJens Axboe */ 21173b6592f7SJens Axboe if (result == -ENOSPC) { 21186451fe73SJens Axboe irq_queues--; 21196451fe73SJens Axboe if (!irq_queues) 21203b6592f7SJens Axboe return result; 21213b6592f7SJens Axboe continue; 2122db29eb05SJens Axboe } else if (result == -EINVAL) { 21236451fe73SJens Axboe irq_queues = 1; 2124db29eb05SJens Axboe continue; 21253b6592f7SJens Axboe } else if (result <= 0) 21263b6592f7SJens Axboe return -EIO; 21273b6592f7SJens Axboe break; 21283b6592f7SJens Axboe } while (1); 21293b6592f7SJens Axboe 21303b6592f7SJens Axboe return result; 21313b6592f7SJens Axboe } 21323b6592f7SJens Axboe 213357dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 213457dacad5SJay Sternberg { 2135147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 213657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 213797f6ef64SXu Yu int result, nr_io_queues; 213897f6ef64SXu Yu unsigned long size; 213957dacad5SJay Sternberg 21403b6592f7SJens Axboe nr_io_queues = max_io_queues(); 21419a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 21429a0be7abSChristoph Hellwig if (result < 0) 214357dacad5SJay Sternberg return result; 21449a0be7abSChristoph Hellwig 2145f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2146a5229050SKeith Busch return 0; 214757dacad5SJay Sternberg 21484e224106SChristoph Hellwig clear_bit(NVMEQ_ENABLED, &adminq->flags); 21494e224106SChristoph Hellwig 21500f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 215157dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 215257dacad5SJay Sternberg sizeof(struct nvme_command)); 215357dacad5SJay Sternberg if (result > 0) 215457dacad5SJay Sternberg dev->q_depth = result; 215557dacad5SJay Sternberg else 21560f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 215757dacad5SJay Sternberg } 215857dacad5SJay Sternberg 215957dacad5SJay Sternberg do { 216097f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 216197f6ef64SXu Yu result = nvme_remap_bar(dev, size); 216297f6ef64SXu Yu if (!result) 216357dacad5SJay Sternberg break; 216457dacad5SJay Sternberg if (!--nr_io_queues) 216557dacad5SJay Sternberg return -ENOMEM; 216657dacad5SJay Sternberg } while (1); 216757dacad5SJay Sternberg adminq->q_db = dev->dbs; 216857dacad5SJay Sternberg 216957dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 21700ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 217157dacad5SJay Sternberg 217257dacad5SJay Sternberg /* 217357dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 217457dacad5SJay Sternberg * setting up the full range we need. 217557dacad5SJay Sternberg */ 2176dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 21773b6592f7SJens Axboe 21783b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 217922b55601SKeith Busch if (result <= 0) 2180dca51e78SChristoph Hellwig return -EIO; 21813b6592f7SJens Axboe 218222b55601SKeith Busch dev->num_vecs = result; 21834b04cc6aSJens Axboe result = max(result - 1, 1); 2184e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 218557dacad5SJay Sternberg 2186e20ba6e1SChristoph Hellwig dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 2187e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_DEFAULT], 2188e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ], 2189e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_POLL]); 21903b6592f7SJens Axboe 219157dacad5SJay Sternberg /* 219257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 219357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 219457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 219557dacad5SJay Sternberg * number of interrupts. 219657dacad5SJay Sternberg */ 219757dacad5SJay Sternberg 2198dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 219957dacad5SJay Sternberg if (result) { 220057dacad5SJay Sternberg adminq->cq_vector = -1; 2201d4875622SKeith Busch return result; 220257dacad5SJay Sternberg } 22034e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2204749941f2SChristoph Hellwig return nvme_create_io_queues(dev); 220557dacad5SJay Sternberg } 220657dacad5SJay Sternberg 22072a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2208db3cbfffSKeith Busch { 2209db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2210db3cbfffSKeith Busch 2211db3cbfffSKeith Busch blk_mq_free_request(req); 2212d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2213db3cbfffSKeith Busch } 2214db3cbfffSKeith Busch 22152a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2216db3cbfffSKeith Busch { 2217db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2218db3cbfffSKeith Busch 2219d1ed6aa1SChristoph Hellwig if (error) 2220d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2221db3cbfffSKeith Busch 2222db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2223db3cbfffSKeith Busch } 2224db3cbfffSKeith Busch 2225db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2226db3cbfffSKeith Busch { 2227db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2228db3cbfffSKeith Busch struct request *req; 2229db3cbfffSKeith Busch struct nvme_command cmd; 2230db3cbfffSKeith Busch 2231db3cbfffSKeith Busch memset(&cmd, 0, sizeof(cmd)); 2232db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2233db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2234db3cbfffSKeith Busch 2235eb71f435SChristoph Hellwig req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY); 2236db3cbfffSKeith Busch if (IS_ERR(req)) 2237db3cbfffSKeith Busch return PTR_ERR(req); 2238db3cbfffSKeith Busch 2239db3cbfffSKeith Busch req->timeout = ADMIN_TIMEOUT; 2240db3cbfffSKeith Busch req->end_io_data = nvmeq; 2241db3cbfffSKeith Busch 2242d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2243db3cbfffSKeith Busch blk_execute_rq_nowait(q, NULL, req, false, 2244db3cbfffSKeith Busch opcode == nvme_admin_delete_cq ? 2245db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2246db3cbfffSKeith Busch return 0; 2247db3cbfffSKeith Busch } 2248db3cbfffSKeith Busch 22495271edd4SChristoph Hellwig static bool nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2250db3cbfffSKeith Busch { 22515271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2252db3cbfffSKeith Busch unsigned long timeout; 2253db3cbfffSKeith Busch 2254db3cbfffSKeith Busch retry: 2255db3cbfffSKeith Busch timeout = ADMIN_TIMEOUT; 22565271edd4SChristoph Hellwig while (nr_queues > 0) { 22575271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2258db3cbfffSKeith Busch break; 22595271edd4SChristoph Hellwig nr_queues--; 22605271edd4SChristoph Hellwig sent++; 22615271edd4SChristoph Hellwig } 2262d1ed6aa1SChristoph Hellwig while (sent) { 2263d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2264d1ed6aa1SChristoph Hellwig 2265d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 22665271edd4SChristoph Hellwig timeout); 2267db3cbfffSKeith Busch if (timeout == 0) 22685271edd4SChristoph Hellwig return false; 2269d1ed6aa1SChristoph Hellwig 2270d1ed6aa1SChristoph Hellwig /* handle any remaining CQEs */ 2271d1ed6aa1SChristoph Hellwig if (opcode == nvme_admin_delete_cq && 2272d1ed6aa1SChristoph Hellwig !test_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags)) 2273d1ed6aa1SChristoph Hellwig nvme_poll_irqdisable(nvmeq, -1); 2274d1ed6aa1SChristoph Hellwig 2275d1ed6aa1SChristoph Hellwig sent--; 22765271edd4SChristoph Hellwig if (nr_queues) 2277db3cbfffSKeith Busch goto retry; 2278db3cbfffSKeith Busch } 22795271edd4SChristoph Hellwig return true; 2280db3cbfffSKeith Busch } 2281db3cbfffSKeith Busch 228257dacad5SJay Sternberg /* 22832b1b7e78SJianchao Wang * return error value only when tagset allocation failed 228457dacad5SJay Sternberg */ 228557dacad5SJay Sternberg static int nvme_dev_add(struct nvme_dev *dev) 228657dacad5SJay Sternberg { 22872b1b7e78SJianchao Wang int ret; 22882b1b7e78SJianchao Wang 22895bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2290c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 229157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 2292e20ba6e1SChristoph Hellwig dev->tagset.nr_maps = HCTX_MAX_TYPES; 229357dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 229457dacad5SJay Sternberg dev->tagset.numa_node = dev_to_node(dev->dev); 229557dacad5SJay Sternberg dev->tagset.queue_depth = 229657dacad5SJay Sternberg min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 2297a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = nvme_pci_cmd_size(dev, false); 2298a7a7cbe3SChaitanya Kulkarni if ((dev->ctrl.sgls & ((1 << 0) | (1 << 1))) && sgl_threshold) { 2299a7a7cbe3SChaitanya Kulkarni dev->tagset.cmd_size = max(dev->tagset.cmd_size, 2300a7a7cbe3SChaitanya Kulkarni nvme_pci_cmd_size(dev, true)); 2301a7a7cbe3SChaitanya Kulkarni } 230257dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 230357dacad5SJay Sternberg dev->tagset.driver_data = dev; 230457dacad5SJay Sternberg 23052b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 23062b1b7e78SJianchao Wang if (ret) { 23072b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 23082b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 23092b1b7e78SJianchao Wang return ret; 23102b1b7e78SJianchao Wang } 23115bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2312f9f38e33SHelen Koike 2313f9f38e33SHelen Koike nvme_dbbuf_set(dev); 2314949928c1SKeith Busch } else { 2315949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2316949928c1SKeith Busch 2317949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2318949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 231957dacad5SJay Sternberg } 2320949928c1SKeith Busch 232157dacad5SJay Sternberg return 0; 232257dacad5SJay Sternberg } 232357dacad5SJay Sternberg 2324b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 232557dacad5SJay Sternberg { 2326b00a726aSKeith Busch int result = -ENOMEM; 232757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 232857dacad5SJay Sternberg 232957dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 233057dacad5SJay Sternberg return result; 233157dacad5SJay Sternberg 233257dacad5SJay Sternberg pci_set_master(pdev); 233357dacad5SJay Sternberg 233457dacad5SJay Sternberg if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) && 233557dacad5SJay Sternberg dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32))) 233657dacad5SJay Sternberg goto disable; 233757dacad5SJay Sternberg 23387a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 233957dacad5SJay Sternberg result = -ENODEV; 2340b00a726aSKeith Busch goto disable; 234157dacad5SJay Sternberg } 234257dacad5SJay Sternberg 234357dacad5SJay Sternberg /* 2344a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2345a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2346a5229050SKeith Busch * adjust this later. 234757dacad5SJay Sternberg */ 2348dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2349dca51e78SChristoph Hellwig if (result < 0) 2350dca51e78SChristoph Hellwig return result; 235157dacad5SJay Sternberg 235220d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 23537a67cbeaSChristoph Hellwig 235420d0dfe6SSagi Grimberg dev->q_depth = min_t(int, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2355b27c1e68Sweiping zhang io_queue_depth); 235620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 23577a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 23581f390c1fSStephan Günther 23591f390c1fSStephan Günther /* 23601f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 23611f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 23621f390c1fSStephan Günther */ 23631f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 23641f390c1fSStephan Günther dev->q_depth = 2; 23659bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 23669bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 23671f390c1fSStephan Günther dev->q_depth); 2368d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2369d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 237020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2371d554b5e1SMartin K. Petersen dev->q_depth = 64; 2372d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2373d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 23741f390c1fSStephan Günther } 23751f390c1fSStephan Günther 2376f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2377202021c1SStephen Bates 2378a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2379a0a3408eSKeith Busch pci_save_state(pdev); 238057dacad5SJay Sternberg return 0; 238157dacad5SJay Sternberg 238257dacad5SJay Sternberg disable: 238357dacad5SJay Sternberg pci_disable_device(pdev); 238457dacad5SJay Sternberg return result; 238557dacad5SJay Sternberg } 238657dacad5SJay Sternberg 238757dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 238857dacad5SJay Sternberg { 2389b00a726aSKeith Busch if (dev->bar) 2390b00a726aSKeith Busch iounmap(dev->bar); 2391a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2392b00a726aSKeith Busch } 2393b00a726aSKeith Busch 2394b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2395b00a726aSKeith Busch { 239657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 239757dacad5SJay Sternberg 2398dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 239957dacad5SJay Sternberg 2400a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2401a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 240257dacad5SJay Sternberg pci_disable_device(pdev); 240357dacad5SJay Sternberg } 2404a0a3408eSKeith Busch } 240557dacad5SJay Sternberg 2406a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 240757dacad5SJay Sternberg { 2408ee9aebb2SKeith Busch int i; 2409302ad8ccSKeith Busch bool dead = true; 2410302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 241157dacad5SJay Sternberg 241277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2413302ad8ccSKeith Busch if (pci_is_enabled(pdev)) { 2414302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2415302ad8ccSKeith Busch 2416ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2417ebef7368SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) 2418302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2419302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2420302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 242157dacad5SJay Sternberg } 2422c21377f8SGabriel Krisman Bertazi 2423302ad8ccSKeith Busch /* 2424302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2425302ad8ccSKeith Busch * doing a safe shutdown. 2426302ad8ccSKeith Busch */ 242787ad72a5SChristoph Hellwig if (!dead) { 242887ad72a5SChristoph Hellwig if (shutdown) 2429302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 24309a915a5bSJianchao Wang } 243187ad72a5SChristoph Hellwig 24329a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 24339a915a5bSJianchao Wang 243464ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 24355271edd4SChristoph Hellwig if (nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 24365271edd4SChristoph Hellwig nvme_disable_io_queues(dev, nvme_admin_delete_cq); 2437a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 243857dacad5SJay Sternberg } 2439ee9aebb2SKeith Busch for (i = dev->ctrl.queue_count - 1; i >= 0; i--) 2440ee9aebb2SKeith Busch nvme_suspend_queue(&dev->queues[i]); 2441ee9aebb2SKeith Busch 2442b00a726aSKeith Busch nvme_pci_disable(dev); 244357dacad5SJay Sternberg 2444e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2445e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2446302ad8ccSKeith Busch 2447302ad8ccSKeith Busch /* 2448302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2449302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2450302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2451302ad8ccSKeith Busch */ 2452302ad8ccSKeith Busch if (shutdown) 2453302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 245477bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 245557dacad5SJay Sternberg } 245657dacad5SJay Sternberg 245757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 245857dacad5SJay Sternberg { 245957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 246057dacad5SJay Sternberg PAGE_SIZE, PAGE_SIZE, 0); 246157dacad5SJay Sternberg if (!dev->prp_page_pool) 246257dacad5SJay Sternberg return -ENOMEM; 246357dacad5SJay Sternberg 246457dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 246557dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 246657dacad5SJay Sternberg 256, 256, 0); 246757dacad5SJay Sternberg if (!dev->prp_small_pool) { 246857dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 246957dacad5SJay Sternberg return -ENOMEM; 247057dacad5SJay Sternberg } 247157dacad5SJay Sternberg return 0; 247257dacad5SJay Sternberg } 247357dacad5SJay Sternberg 247457dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 247557dacad5SJay Sternberg { 247657dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 247757dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 247857dacad5SJay Sternberg } 247957dacad5SJay Sternberg 24801673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 248157dacad5SJay Sternberg { 24821673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 248357dacad5SJay Sternberg 2484f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 248557dacad5SJay Sternberg put_device(dev->dev); 248657dacad5SJay Sternberg if (dev->tagset.tags) 248757dacad5SJay Sternberg blk_mq_free_tag_set(&dev->tagset); 24881c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 24891c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 249057dacad5SJay Sternberg kfree(dev->queues); 2491e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2492943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 249357dacad5SJay Sternberg kfree(dev); 249457dacad5SJay Sternberg } 249557dacad5SJay Sternberg 2496f58944e2SKeith Busch static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status) 2497f58944e2SKeith Busch { 2498237045fcSLinus Torvalds dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status); 2499f58944e2SKeith Busch 2500d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 250169d9a99cSKeith Busch nvme_dev_disable(dev, false); 25029f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 250303e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2504f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2505f58944e2SKeith Busch } 2506f58944e2SKeith Busch 2507fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 250857dacad5SJay Sternberg { 2509d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2510d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2511a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2512f58944e2SKeith Busch int result = -ENODEV; 25132b1b7e78SJianchao Wang enum nvme_ctrl_state new_state = NVME_CTRL_LIVE; 251457dacad5SJay Sternberg 251582b057caSRakesh Pandit if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING)) 2516fd634f41SChristoph Hellwig goto out; 2517fd634f41SChristoph Hellwig 2518fd634f41SChristoph Hellwig /* 2519fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2520fd634f41SChristoph Hellwig * moving on. 2521fd634f41SChristoph Hellwig */ 2522b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2523a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2524fd634f41SChristoph Hellwig 2525ad70062cSJianchao Wang /* 2526ad6a0a52SMax Gurtovoy * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 2527ad70062cSJianchao Wang * initializing procedure here. 2528ad70062cSJianchao Wang */ 2529ad6a0a52SMax Gurtovoy if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 2530ad70062cSJianchao Wang dev_warn(dev->ctrl.device, 2531ad6a0a52SMax Gurtovoy "failed to mark controller CONNECTING\n"); 2532ad70062cSJianchao Wang goto out; 2533ad70062cSJianchao Wang } 2534ad70062cSJianchao Wang 2535b00a726aSKeith Busch result = nvme_pci_enable(dev); 253657dacad5SJay Sternberg if (result) 253757dacad5SJay Sternberg goto out; 253857dacad5SJay Sternberg 253901ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 254057dacad5SJay Sternberg if (result) 2541f58944e2SKeith Busch goto out; 254257dacad5SJay Sternberg 254357dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 254457dacad5SJay Sternberg if (result) 2545f58944e2SKeith Busch goto out; 254657dacad5SJay Sternberg 2547943e942eSJens Axboe /* 2548943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2549943e942eSJens Axboe * over a single page. 2550943e942eSJens Axboe */ 2551943e942eSJens Axboe dev->ctrl.max_hw_sectors = NVME_MAX_KB_SZ << 1; 2552943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2553943e942eSJens Axboe 2554ce4541f4SChristoph Hellwig result = nvme_init_identify(&dev->ctrl); 2555ce4541f4SChristoph Hellwig if (result) 2556f58944e2SKeith Busch goto out; 2557ce4541f4SChristoph Hellwig 2558e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2559e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 25604f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 25614f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2562e286bcfcSScott Bauer else if (was_suspend) 25634f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2564e286bcfcSScott Bauer } else { 2565e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2566e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2567e286bcfcSScott Bauer } 2568a98e58e5SScott Bauer 2569f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2570f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2571f9f38e33SHelen Koike if (result) 2572f9f38e33SHelen Koike dev_warn(dev->dev, 2573f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2574f9f38e33SHelen Koike } 2575f9f38e33SHelen Koike 25769620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 25779620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 25789620cfbaSChristoph Hellwig if (result < 0) 25799620cfbaSChristoph Hellwig goto out; 25809620cfbaSChristoph Hellwig } 258187ad72a5SChristoph Hellwig 258257dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 258357dacad5SJay Sternberg if (result) 2584f58944e2SKeith Busch goto out; 258557dacad5SJay Sternberg 258621f033f7SKeith Busch /* 258757dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 258857dacad5SJay Sternberg * any working I/O queue. 258957dacad5SJay Sternberg */ 259057dacad5SJay Sternberg if (dev->online_queues < 2) { 25911b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 25923b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 25935bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 25942b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 259557dacad5SJay Sternberg } else { 259625646264SKeith Busch nvme_start_queues(&dev->ctrl); 2597302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 25982b1b7e78SJianchao Wang /* hit this only when allocate tagset fails */ 25992b1b7e78SJianchao Wang if (nvme_dev_add(dev)) 26002b1b7e78SJianchao Wang new_state = NVME_CTRL_ADMIN_ONLY; 2601302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 260257dacad5SJay Sternberg } 260357dacad5SJay Sternberg 26042b1b7e78SJianchao Wang /* 26052b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 26062b1b7e78SJianchao Wang * recovery. 26072b1b7e78SJianchao Wang */ 26082b1b7e78SJianchao Wang if (!nvme_change_ctrl_state(&dev->ctrl, new_state)) { 26092b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 26102b1b7e78SJianchao Wang "failed to mark controller state %d\n", new_state); 2611bb8d261eSChristoph Hellwig goto out; 2612bb8d261eSChristoph Hellwig } 261392911a55SChristoph Hellwig 2614d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 261557dacad5SJay Sternberg return; 261657dacad5SJay Sternberg 261757dacad5SJay Sternberg out: 2618f58944e2SKeith Busch nvme_remove_dead_ctrl(dev, result); 261957dacad5SJay Sternberg } 262057dacad5SJay Sternberg 26215c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 262257dacad5SJay Sternberg { 26235c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 262457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 262557dacad5SJay Sternberg 262657dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2627921920abSKeith Busch device_release_driver(&pdev->dev); 26281673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 262957dacad5SJay Sternberg } 263057dacad5SJay Sternberg 26311c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 263257dacad5SJay Sternberg { 26331c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 26341c63dc66SChristoph Hellwig return 0; 263557dacad5SJay Sternberg } 26361c63dc66SChristoph Hellwig 26375fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 26385fd4ce1bSChristoph Hellwig { 26395fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 26405fd4ce1bSChristoph Hellwig return 0; 26415fd4ce1bSChristoph Hellwig } 26425fd4ce1bSChristoph Hellwig 26437fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 26447fd8930fSChristoph Hellwig { 26457fd8930fSChristoph Hellwig *val = readq(to_nvme_dev(ctrl)->bar + off); 26467fd8930fSChristoph Hellwig return 0; 26477fd8930fSChristoph Hellwig } 26487fd8930fSChristoph Hellwig 264997c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 265097c12223SKeith Busch { 265197c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 265297c12223SKeith Busch 265397c12223SKeith Busch return snprintf(buf, size, "%s", dev_name(&pdev->dev)); 265497c12223SKeith Busch } 265597c12223SKeith Busch 26561c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 26571a353d85SMing Lin .name = "pcie", 2658e439bb12SSagi Grimberg .module = THIS_MODULE, 2659e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2660e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 26611c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 26625fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 26637fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 26641673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2665f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 266697c12223SKeith Busch .get_address = nvme_pci_get_address, 26671c63dc66SChristoph Hellwig }; 266857dacad5SJay Sternberg 2669b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2670b00a726aSKeith Busch { 2671b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2672b00a726aSKeith Busch 2673a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2674b00a726aSKeith Busch return -ENODEV; 2675b00a726aSKeith Busch 267697f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2677b00a726aSKeith Busch goto release; 2678b00a726aSKeith Busch 2679b00a726aSKeith Busch return 0; 2680b00a726aSKeith Busch release: 2681a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2682b00a726aSKeith Busch return -ENODEV; 2683b00a726aSKeith Busch } 2684b00a726aSKeith Busch 26858427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2686ff5350a8SAndy Lutomirski { 2687ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2688ff5350a8SAndy Lutomirski /* 2689ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2690ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2691ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2692ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2693ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2694ff5350a8SAndy Lutomirski * laptops. 2695ff5350a8SAndy Lutomirski */ 2696ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2697ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2698ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2699ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 27008427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 27018427bbc2SKai-Heng Feng /* 27028427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2703467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2704467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2705467c77d4SJarosław Janik * ASUS PRIME Z370-A 27068427bbc2SKai-Heng Feng */ 27078427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2708467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2709467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 27108427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 2711ff5350a8SAndy Lutomirski } 2712ff5350a8SAndy Lutomirski 2713ff5350a8SAndy Lutomirski return 0; 2714ff5350a8SAndy Lutomirski } 2715ff5350a8SAndy Lutomirski 271618119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 271718119775SKeith Busch { 271818119775SKeith Busch struct nvme_dev *dev = data; 271980f513b5SKeith Busch 272018119775SKeith Busch nvme_reset_ctrl_sync(&dev->ctrl); 272118119775SKeith Busch flush_work(&dev->ctrl.scan_work); 272280f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 272318119775SKeith Busch } 272418119775SKeith Busch 272557dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 272657dacad5SJay Sternberg { 272757dacad5SJay Sternberg int node, result = -ENOMEM; 272857dacad5SJay Sternberg struct nvme_dev *dev; 2729ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 2730943e942eSJens Axboe size_t alloc_size; 273157dacad5SJay Sternberg 273257dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 273357dacad5SJay Sternberg if (node == NUMA_NO_NODE) 27342fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 273557dacad5SJay Sternberg 273657dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 273757dacad5SJay Sternberg if (!dev) 273857dacad5SJay Sternberg return -ENOMEM; 2739147b27e4SSagi Grimberg 27403b6592f7SJens Axboe dev->queues = kcalloc_node(max_queue_count(), sizeof(struct nvme_queue), 27413b6592f7SJens Axboe GFP_KERNEL, node); 274257dacad5SJay Sternberg if (!dev->queues) 274357dacad5SJay Sternberg goto free; 274457dacad5SJay Sternberg 274557dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 274657dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 274757dacad5SJay Sternberg 2748b00a726aSKeith Busch result = nvme_dev_map(dev); 2749b00a726aSKeith Busch if (result) 2750b00c9b7aSChristophe JAILLET goto put_pci; 2751b00a726aSKeith Busch 2752d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 27535c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 275477bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 2755f3ca80fcSChristoph Hellwig 2756f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 2757f3ca80fcSChristoph Hellwig if (result) 2758b00c9b7aSChristophe JAILLET goto unmap; 2759f3ca80fcSChristoph Hellwig 27608427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 2761ff5350a8SAndy Lutomirski 2762943e942eSJens Axboe /* 2763943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 2764943e942eSJens Axboe * command we support. 2765943e942eSJens Axboe */ 2766943e942eSJens Axboe alloc_size = nvme_pci_iod_alloc_size(dev, NVME_MAX_KB_SZ, 2767943e942eSJens Axboe NVME_MAX_SEGS, true); 2768943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2769943e942eSJens Axboe 2770943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 2771943e942eSJens Axboe mempool_kfree, 2772943e942eSJens Axboe (void *) alloc_size, 2773943e942eSJens Axboe GFP_KERNEL, node); 2774943e942eSJens Axboe if (!dev->iod_mempool) { 2775943e942eSJens Axboe result = -ENOMEM; 2776943e942eSJens Axboe goto release_pools; 2777943e942eSJens Axboe } 2778943e942eSJens Axboe 2779b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 2780b6e44b4cSKeith Busch quirks); 2781b6e44b4cSKeith Busch if (result) 2782b6e44b4cSKeith Busch goto release_mempool; 2783b6e44b4cSKeith Busch 27841b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 27851b3c47c1SSagi Grimberg 278680f513b5SKeith Busch nvme_get_ctrl(&dev->ctrl); 278718119775SKeith Busch async_schedule(nvme_async_probe, dev); 27884caff8fcSSagi Grimberg 278957dacad5SJay Sternberg return 0; 279057dacad5SJay Sternberg 2791b6e44b4cSKeith Busch release_mempool: 2792b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 279357dacad5SJay Sternberg release_pools: 279457dacad5SJay Sternberg nvme_release_prp_pools(dev); 2795b00c9b7aSChristophe JAILLET unmap: 2796b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 279757dacad5SJay Sternberg put_pci: 279857dacad5SJay Sternberg put_device(dev->dev); 279957dacad5SJay Sternberg free: 280057dacad5SJay Sternberg kfree(dev->queues); 280157dacad5SJay Sternberg kfree(dev); 280257dacad5SJay Sternberg return result; 280357dacad5SJay Sternberg } 280457dacad5SJay Sternberg 2805775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 280657dacad5SJay Sternberg { 280757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2808a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2809775755edSChristoph Hellwig } 281057dacad5SJay Sternberg 2811775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 2812775755edSChristoph Hellwig { 2813f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 281479c48ccfSSagi Grimberg nvme_reset_ctrl_sync(&dev->ctrl); 281557dacad5SJay Sternberg } 281657dacad5SJay Sternberg 281757dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 281857dacad5SJay Sternberg { 281957dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 2820a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 282157dacad5SJay Sternberg } 282257dacad5SJay Sternberg 2823f58944e2SKeith Busch /* 2824f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 2825f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 2826f58944e2SKeith Busch * order to proceed. 2827f58944e2SKeith Busch */ 282857dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 282957dacad5SJay Sternberg { 283057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 283157dacad5SJay Sternberg 2832bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 283357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 28340ff9d4e1SKeith Busch 28356db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 28360ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 28371d39e692SKeith Busch nvme_dev_disable(dev, true); 2838cb4bfda6SKeith Busch nvme_dev_remove_admin(dev); 28396db28edaSKeith Busch } 28400ff9d4e1SKeith Busch 2841d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 2842d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 2843d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 2844a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 28459fe5c59fSKeith Busch nvme_release_cmb(dev); 284687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 284757dacad5SJay Sternberg nvme_dev_remove_admin(dev); 284857dacad5SJay Sternberg nvme_free_queues(dev, 0); 2849d09f2b45SSagi Grimberg nvme_uninit_ctrl(&dev->ctrl); 285057dacad5SJay Sternberg nvme_release_prp_pools(dev); 2851b00a726aSKeith Busch nvme_dev_unmap(dev); 28521673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 285357dacad5SJay Sternberg } 285457dacad5SJay Sternberg 285557dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 285657dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 285757dacad5SJay Sternberg { 285857dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 285957dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 286057dacad5SJay Sternberg 2861a5cdb68cSKeith Busch nvme_dev_disable(ndev, true); 286257dacad5SJay Sternberg return 0; 286357dacad5SJay Sternberg } 286457dacad5SJay Sternberg 286557dacad5SJay Sternberg static int nvme_resume(struct device *dev) 286657dacad5SJay Sternberg { 286757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 286857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 286957dacad5SJay Sternberg 2870d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&ndev->ctrl); 287157dacad5SJay Sternberg return 0; 287257dacad5SJay Sternberg } 287357dacad5SJay Sternberg #endif 287457dacad5SJay Sternberg 287557dacad5SJay Sternberg static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume); 287657dacad5SJay Sternberg 2877a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 2878a0a3408eSKeith Busch pci_channel_state_t state) 2879a0a3408eSKeith Busch { 2880a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2881a0a3408eSKeith Busch 2882a0a3408eSKeith Busch /* 2883a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 2884a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 2885a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 2886a0a3408eSKeith Busch */ 2887a0a3408eSKeith Busch switch (state) { 2888a0a3408eSKeith Busch case pci_channel_io_normal: 2889a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 2890a0a3408eSKeith Busch case pci_channel_io_frozen: 2891d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2892d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 2893a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2894a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2895a0a3408eSKeith Busch case pci_channel_io_perm_failure: 2896d011fb31SKeith Busch dev_warn(dev->ctrl.device, 2897d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 2898a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 2899a0a3408eSKeith Busch } 2900a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 2901a0a3408eSKeith Busch } 2902a0a3408eSKeith Busch 2903a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 2904a0a3408eSKeith Busch { 2905a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 2906a0a3408eSKeith Busch 29071b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 2908a0a3408eSKeith Busch pci_restore_state(pdev); 2909d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 2910a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 2911a0a3408eSKeith Busch } 2912a0a3408eSKeith Busch 2913a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 2914a0a3408eSKeith Busch { 291572cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 291672cd4cc2SKeith Busch 291772cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 2918a0a3408eSKeith Busch } 2919a0a3408eSKeith Busch 292057dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 292157dacad5SJay Sternberg .error_detected = nvme_error_detected, 292257dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 292357dacad5SJay Sternberg .resume = nvme_error_resume, 2924775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 2925775755edSChristoph Hellwig .reset_done = nvme_reset_done, 292657dacad5SJay Sternberg }; 292757dacad5SJay Sternberg 292857dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 2929106198edSChristoph Hellwig { PCI_VDEVICE(INTEL, 0x0953), 293008095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2931e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 293299466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a53), 293399466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2934e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 293599466e70SKeith Busch { PCI_VDEVICE(INTEL, 0x0a54), 293699466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 2937e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 2938f99cb7afSDavid Wayne Fugate { PCI_VDEVICE(INTEL, 0x0a55), 2939f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 2940f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 294150af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 29429abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 29439abd68efSJens Axboe NVME_QUIRK_MEDIUM_PRIO_SQ }, 2944540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 2945540c801cSKeith Busch .driver_data = NVME_QUIRK_IDENTIFY_CNS, }, 29460302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 29470302ae60SMicah Parrish .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 294854adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 294954adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 29508c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 29518c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2952015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 2953015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2954d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 2955d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2956d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 2957d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 2958608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x1f1f), /* LighNVM qemu device */ 2959608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2960608cc4b1SChristoph Hellwig { PCI_DEVICE(0x1d1d, 0x2807), /* CNEX WL */ 2961608cc4b1SChristoph Hellwig .driver_data = NVME_QUIRK_LIGHTNVM, }, 2962ea48e877SWei Xu { PCI_DEVICE(0x1d1d, 0x2601), /* CNEX Granby */ 2963ea48e877SWei Xu .driver_data = NVME_QUIRK_LIGHTNVM, }, 296457dacad5SJay Sternberg { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 2965c74dc780SStephan Günther { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) }, 2966124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 296757dacad5SJay Sternberg { 0, } 296857dacad5SJay Sternberg }; 296957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 297057dacad5SJay Sternberg 297157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 297257dacad5SJay Sternberg .name = "nvme", 297357dacad5SJay Sternberg .id_table = nvme_id_table, 297457dacad5SJay Sternberg .probe = nvme_probe, 297557dacad5SJay Sternberg .remove = nvme_remove, 297657dacad5SJay Sternberg .shutdown = nvme_shutdown, 297757dacad5SJay Sternberg .driver = { 297857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 297957dacad5SJay Sternberg }, 298074d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 298157dacad5SJay Sternberg .err_handler = &nvme_err_handler, 298257dacad5SJay Sternberg }; 298357dacad5SJay Sternberg 298457dacad5SJay Sternberg static int __init nvme_init(void) 298557dacad5SJay Sternberg { 29869a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 298757dacad5SJay Sternberg } 298857dacad5SJay Sternberg 298957dacad5SJay Sternberg static void __exit nvme_exit(void) 299057dacad5SJay Sternberg { 299157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 299203e0f3a6SMing Lei flush_workqueue(nvme_wq); 299357dacad5SJay Sternberg _nvme_check_size(); 299457dacad5SJay Sternberg } 299557dacad5SJay Sternberg 299657dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 299757dacad5SJay Sternberg MODULE_LICENSE("GPL"); 299857dacad5SJay Sternberg MODULE_VERSION("1.0"); 299957dacad5SJay Sternberg module_init(nvme_init); 300057dacad5SJay Sternberg module_exit(nvme_exit); 3001