15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 1899722c8aSChristophe JAILLET #include <linux/kstrtox.h> 19dc90f084SChristoph Hellwig #include <linux/memremap.h> 2057dacad5SJay Sternberg #include <linux/mm.h> 2157dacad5SJay Sternberg #include <linux/module.h> 2277bf25eaSKeith Busch #include <linux/mutex.h> 23d0877473SKeith Busch #include <linux/once.h> 2457dacad5SJay Sternberg #include <linux/pci.h> 25d916b1beSKeith Busch #include <linux/suspend.h> 2657dacad5SJay Sternberg #include <linux/t10-pi.h> 2757dacad5SJay Sternberg #include <linux/types.h> 289cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2920d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 30a98e58e5SScott Bauer #include <linux/sed-opal.h> 310f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3257dacad5SJay Sternberg 33604c01d5Syupeng #include "trace.h" 3457dacad5SJay Sternberg #include "nvme.h" 3557dacad5SJay Sternberg 36c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 378a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3857dacad5SJay Sternberg 39a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40adf68f21SChristoph Hellwig 41943e942eSJens Axboe /* 42943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 43943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 44943e942eSJens Axboe */ 45943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 46943e942eSJens Axboe #define NVME_MAX_SEGS 127 47943e942eSJens Axboe 4857dacad5SJay Sternberg static int use_threaded_interrupts; 492e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 5057dacad5SJay Sternberg 5157dacad5SJay Sternberg static bool use_cmb_sqes = true; 5269f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5357dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5457dacad5SJay Sternberg 5587ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5687ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5787ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5887ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5957dacad5SJay Sternberg 60a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 61a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 62a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 63a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 64a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 65a7a7cbe3SChaitanya Kulkarni 6627453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6727453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 68b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 69b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 70b27c1e68Sweiping zhang .set = io_queue_depth_set, 7161f3b896SChaitanya Kulkarni .get = param_get_uint, 72b27c1e68Sweiping zhang }; 73b27c1e68Sweiping zhang 7461f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 75b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7627453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 77b27c1e68Sweiping zhang 789c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 799c9e76d5SWeiping Zhang { 809c9e76d5SWeiping Zhang unsigned int n; 819c9e76d5SWeiping Zhang int ret; 829c9e76d5SWeiping Zhang 839c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 849c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 859c9e76d5SWeiping Zhang return -EINVAL; 869c9e76d5SWeiping Zhang return param_set_uint(val, kp); 879c9e76d5SWeiping Zhang } 889c9e76d5SWeiping Zhang 899c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 909c9e76d5SWeiping Zhang .set = io_queue_count_set, 919c9e76d5SWeiping Zhang .get = param_get_uint, 929c9e76d5SWeiping Zhang }; 939c9e76d5SWeiping Zhang 943f68baf7SKeith Busch static unsigned int write_queues; 959c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 963b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 973b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 983b6592f7SJens Axboe "will share a queue set."); 993b6592f7SJens Axboe 1003f68baf7SKeith Busch static unsigned int poll_queues; 1019c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1024b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1034b04cc6aSJens Axboe 104df4f9bc4SDavid E. Box static bool noacpi; 105df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 106df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 107df4f9bc4SDavid E. Box 1081c63dc66SChristoph Hellwig struct nvme_dev; 1091c63dc66SChristoph Hellwig struct nvme_queue; 11057dacad5SJay Sternberg 111a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 112*7d879c90SChristoph Hellwig static void nvme_delete_io_queues(struct nvme_dev *dev); 11357dacad5SJay Sternberg 11457dacad5SJay Sternberg /* 1151c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1161c63dc66SChristoph Hellwig */ 1171c63dc66SChristoph Hellwig struct nvme_dev { 118147b27e4SSagi Grimberg struct nvme_queue *queues; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1201c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1211c63dc66SChristoph Hellwig u32 __iomem *dbs; 1221c63dc66SChristoph Hellwig struct device *dev; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1241c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1251c63dc66SChristoph Hellwig unsigned online_queues; 1261c63dc66SChristoph Hellwig unsigned max_qid; 127e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12822b55601SKeith Busch unsigned int num_vecs; 1297442ddceSJohn Garry u32 q_depth; 130c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1311c63dc66SChristoph Hellwig u32 db_stride; 1321c63dc66SChristoph Hellwig void __iomem *bar; 13397f6ef64SXu Yu unsigned long bar_mapped_size; 13477bf25eaSKeith Busch struct mutex shutdown_lock; 1351c63dc66SChristoph Hellwig bool subsystem; 1361c63dc66SChristoph Hellwig u64 cmb_size; 1370f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1381c63dc66SChristoph Hellwig u32 cmbsz; 139202021c1SStephen Bates u32 cmbloc; 1401c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 141d916b1beSKeith Busch u32 last_ps; 142a5df5e79SKeith Busch bool hmb; 14387ad72a5SChristoph Hellwig 144943e942eSJens Axboe mempool_t *iod_mempool; 145943e942eSJens Axboe 14687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 147f9f38e33SHelen Koike u32 *dbbuf_dbs; 148f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 149f9f38e33SHelen Koike u32 *dbbuf_eis; 150f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15187ad72a5SChristoph Hellwig 15287ad72a5SChristoph Hellwig /* host memory buffer support: */ 15387ad72a5SChristoph Hellwig u64 host_mem_size; 15487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1554033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1582a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 16157dacad5SJay Sternberg }; 16257dacad5SJay Sternberg 163b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 164b27c1e68Sweiping zhang { 16527453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16627453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 167b27c1e68Sweiping zhang } 168b27c1e68Sweiping zhang 169f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 170f9f38e33SHelen Koike { 171f9f38e33SHelen Koike return qid * 2 * stride; 172f9f38e33SHelen Koike } 173f9f38e33SHelen Koike 174f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 175f9f38e33SHelen Koike { 176f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 177f9f38e33SHelen Koike } 178f9f38e33SHelen Koike 1791c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1801c63dc66SChristoph Hellwig { 1811c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1821c63dc66SChristoph Hellwig } 1831c63dc66SChristoph Hellwig 18457dacad5SJay Sternberg /* 18557dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18657dacad5SJay Sternberg * commands and one for I/O commands). 18757dacad5SJay Sternberg */ 18857dacad5SJay Sternberg struct nvme_queue { 18957dacad5SJay Sternberg struct nvme_dev *dev; 1901ab0cd69SJens Axboe spinlock_t sq_lock; 191c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1923a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1933a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19474943d45SKeith Busch struct nvme_completion *cqes; 19557dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19657dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19757dacad5SJay Sternberg u32 __iomem *q_db; 1987442ddceSJohn Garry u32 q_depth; 1997c349ddeSKeith Busch u16 cq_vector; 20057dacad5SJay Sternberg u16 sq_tail; 20138210800SKeith Busch u16 last_sq_tail; 20257dacad5SJay Sternberg u16 cq_head; 20357dacad5SJay Sternberg u16 qid; 20457dacad5SJay Sternberg u8 cq_phase; 205c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2064e224106SChristoph Hellwig unsigned long flags; 2074e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20863223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 209d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2107c349ddeSKeith Busch #define NVMEQ_POLLED 3 211f9f38e33SHelen Koike u32 *dbbuf_sq_db; 212f9f38e33SHelen Koike u32 *dbbuf_cq_db; 213f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 214f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 215d1ed6aa1SChristoph Hellwig struct completion delete_done; 21657dacad5SJay Sternberg }; 21757dacad5SJay Sternberg 21857dacad5SJay Sternberg /* 2199b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2209b048119SChristoph Hellwig * 2219b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2229b048119SChristoph Hellwig * to the actual struct scatterlist. 22371bd150cSChristoph Hellwig */ 22471bd150cSChristoph Hellwig struct nvme_iod { 225d49187e9SChristoph Hellwig struct nvme_request req; 226af7fae85SKeith Busch struct nvme_command cmd; 227a7a7cbe3SChaitanya Kulkarni bool use_sgl; 22852da4f3fSKeith Busch bool aborted; 229c372cdd1SKeith Busch s8 nr_allocations; /* PRP list pool allocations. 0 means small 230c372cdd1SKeith Busch pool in use */ 231dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 232c4c22c52SKeith Busch dma_addr_t first_dma; 233783b94bdSChristoph Hellwig dma_addr_t meta_dma; 23491fb2b60SLogan Gunthorpe struct sg_table sgt; 23557dacad5SJay Sternberg }; 23657dacad5SJay Sternberg 2372a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2383b6592f7SJens Axboe { 2392a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 240f9f38e33SHelen Koike } 241f9f38e33SHelen Koike 24265a54646SChristoph Hellwig static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 243f9f38e33SHelen Koike { 2442a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 245f9f38e33SHelen Koike 24665a54646SChristoph Hellwig if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 24765a54646SChristoph Hellwig return; 24865a54646SChristoph Hellwig 24958847f12SKeith Busch if (dev->dbbuf_dbs) { 25058847f12SKeith Busch /* 25158847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25258847f12SKeith Busch * values from the previous instantiation. 25358847f12SKeith Busch */ 25458847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25558847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 25665a54646SChristoph Hellwig return; 25758847f12SKeith Busch } 258f9f38e33SHelen Koike 259f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 261f9f38e33SHelen Koike GFP_KERNEL); 262f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 26365a54646SChristoph Hellwig goto fail; 264f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 265f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 266f9f38e33SHelen Koike GFP_KERNEL); 26765a54646SChristoph Hellwig if (!dev->dbbuf_eis) 26865a54646SChristoph Hellwig goto fail_free_dbbuf_dbs; 26965a54646SChristoph Hellwig return; 270f9f38e33SHelen Koike 27165a54646SChristoph Hellwig fail_free_dbbuf_dbs: 27265a54646SChristoph Hellwig dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 27365a54646SChristoph Hellwig dev->dbbuf_dbs_dma_addr); 27465a54646SChristoph Hellwig dev->dbbuf_dbs = NULL; 27565a54646SChristoph Hellwig fail: 27665a54646SChristoph Hellwig dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 277f9f38e33SHelen Koike } 278f9f38e33SHelen Koike 279f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 280f9f38e33SHelen Koike { 2812a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 282f9f38e33SHelen Koike 283f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 284f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 285f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 286f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 287f9f38e33SHelen Koike } 288f9f38e33SHelen Koike if (dev->dbbuf_eis) { 289f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 290f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 291f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 292f9f38e33SHelen Koike } 293f9f38e33SHelen Koike } 294f9f38e33SHelen Koike 295f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 296f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 297f9f38e33SHelen Koike { 298f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 299f9f38e33SHelen Koike return; 300f9f38e33SHelen Koike 301f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 303f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 304f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 305f9f38e33SHelen Koike } 306f9f38e33SHelen Koike 3070f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3080f0d2c87SMinwoo Im { 3090f0d2c87SMinwoo Im if (!nvmeq->qid) 3100f0d2c87SMinwoo Im return; 3110f0d2c87SMinwoo Im 3120f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3130f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3140f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3150f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3160f0d2c87SMinwoo Im } 3170f0d2c87SMinwoo Im 318f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 319f9f38e33SHelen Koike { 320f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3210f0d2c87SMinwoo Im unsigned int i; 322f9f38e33SHelen Koike 323f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 324f9f38e33SHelen Koike return; 325f9f38e33SHelen Koike 326f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 327f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 328f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3319bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 332f9f38e33SHelen Koike /* Free memory and continue on */ 333f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3340f0d2c87SMinwoo Im 3350f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3360f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 337f9f38e33SHelen Koike } 338f9f38e33SHelen Koike } 339f9f38e33SHelen Koike 340f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 341f9f38e33SHelen Koike { 342f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 343f9f38e33SHelen Koike } 344f9f38e33SHelen Koike 345f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 346f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 347f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 348f9f38e33SHelen Koike { 349f9f38e33SHelen Koike if (dbbuf_db) { 350f9f38e33SHelen Koike u16 old_value; 351f9f38e33SHelen Koike 352f9f38e33SHelen Koike /* 353f9f38e33SHelen Koike * Ensure that the queue is written before updating 354f9f38e33SHelen Koike * the doorbell in memory 355f9f38e33SHelen Koike */ 356f9f38e33SHelen Koike wmb(); 357f9f38e33SHelen Koike 358f9f38e33SHelen Koike old_value = *dbbuf_db; 359f9f38e33SHelen Koike *dbbuf_db = value; 360f9f38e33SHelen Koike 361f1ed3df2SMichal Wnukowski /* 362f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 363f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 364f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 365f1ed3df2SMichal Wnukowski * the doorbell. 366f1ed3df2SMichal Wnukowski */ 367f1ed3df2SMichal Wnukowski mb(); 368f1ed3df2SMichal Wnukowski 369f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 370f9f38e33SHelen Koike return false; 371f9f38e33SHelen Koike } 372f9f38e33SHelen Koike 373f9f38e33SHelen Koike return true; 37457dacad5SJay Sternberg } 37557dacad5SJay Sternberg 37657dacad5SJay Sternberg /* 37757dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37857dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37957dacad5SJay Sternberg * the I/O. 38057dacad5SJay Sternberg */ 381b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 38257dacad5SJay Sternberg { 383b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3846c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38557dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38657dacad5SJay Sternberg } 38757dacad5SJay Sternberg 388a7a7cbe3SChaitanya Kulkarni /* 389a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 390a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 391a7a7cbe3SChaitanya Kulkarni */ 392b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 393f4800d6dSChristoph Hellwig { 394b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 395b13c6393SChaitanya Kulkarni PAGE_SIZE); 396f4800d6dSChristoph Hellwig } 397f4800d6dSChristoph Hellwig 39857dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39957dacad5SJay Sternberg unsigned int hctx_idx) 40057dacad5SJay Sternberg { 40157dacad5SJay Sternberg struct nvme_dev *dev = data; 402147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40357dacad5SJay Sternberg 40457dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40557dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40657dacad5SJay Sternberg 40757dacad5SJay Sternberg hctx->driver_data = nvmeq; 40857dacad5SJay Sternberg return 0; 40957dacad5SJay Sternberg } 41057dacad5SJay Sternberg 41157dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41257dacad5SJay Sternberg unsigned int hctx_idx) 41357dacad5SJay Sternberg { 41457dacad5SJay Sternberg struct nvme_dev *dev = data; 415147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41857dacad5SJay Sternberg hctx->driver_data = nvmeq; 41957dacad5SJay Sternberg return 0; 42057dacad5SJay Sternberg } 42157dacad5SJay Sternberg 422e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 423e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 424e559398fSChristoph Hellwig unsigned int numa_node) 42557dacad5SJay Sternberg { 426d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 427f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 42859e29ce6SSagi Grimberg 42959e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 430f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 43157dacad5SJay Sternberg return 0; 43257dacad5SJay Sternberg } 43357dacad5SJay Sternberg 4343b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4353b6592f7SJens Axboe { 4363b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4373b6592f7SJens Axboe if (dev->num_vecs > 1) 4383b6592f7SJens Axboe return 1; 4393b6592f7SJens Axboe 4403b6592f7SJens Axboe return 0; 4413b6592f7SJens Axboe } 4423b6592f7SJens Axboe 443a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 444dca51e78SChristoph Hellwig { 445dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4463b6592f7SJens Axboe int i, qoff, offset; 447dca51e78SChristoph Hellwig 4483b6592f7SJens Axboe offset = queue_irq_offset(dev); 4493b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4503b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4513b6592f7SJens Axboe 4523b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4533b6592f7SJens Axboe if (!map->nr_queues) { 454e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4557e849dd9SChristoph Hellwig continue; 4563b6592f7SJens Axboe } 4573b6592f7SJens Axboe 4584b04cc6aSJens Axboe /* 4594b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4604b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4614b04cc6aSJens Axboe */ 4623b6592f7SJens Axboe map->queue_offset = qoff; 463cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4643b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4654b04cc6aSJens Axboe else 4664b04cc6aSJens Axboe blk_mq_map_queues(map); 4673b6592f7SJens Axboe qoff += map->nr_queues; 4683b6592f7SJens Axboe offset += map->nr_queues; 4693b6592f7SJens Axboe } 470dca51e78SChristoph Hellwig } 471dca51e78SChristoph Hellwig 47238210800SKeith Busch /* 47338210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47438210800SKeith Busch */ 47538210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47604f3eafdSJens Axboe { 47738210800SKeith Busch if (!write_sq) { 47838210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47938210800SKeith Busch 48038210800SKeith Busch if (next_tail == nvmeq->q_depth) 48138210800SKeith Busch next_tail = 0; 48238210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48338210800SKeith Busch return; 48438210800SKeith Busch } 48538210800SKeith Busch 48604f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48704f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48804f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48938210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 49004f3eafdSJens Axboe } 49104f3eafdSJens Axboe 4923233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4933233b94cSJens Axboe struct nvme_command *cmd) 49457dacad5SJay Sternberg { 495c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 4963233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 49790ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49890ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49904f3eafdSJens Axboe } 50004f3eafdSJens Axboe 50104f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 50204f3eafdSJens Axboe { 50304f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50404f3eafdSJens Axboe 50504f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50638210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50738210800SKeith Busch nvme_write_sq_db(nvmeq, true); 50890ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50957dacad5SJay Sternberg } 51057dacad5SJay Sternberg 511a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 51257dacad5SJay Sternberg { 513f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 51491fb2b60SLogan Gunthorpe return (void **)(iod->sgt.sgl + blk_rq_nr_phys_segments(req)); 51557dacad5SJay Sternberg } 51657dacad5SJay Sternberg 517955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 518955b1b5aSMinwoo Im { 519a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 52020469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 521955b1b5aSMinwoo Im unsigned int avg_seg_size; 522955b1b5aSMinwoo Im 52320469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 524955b1b5aSMinwoo Im 525253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 526955b1b5aSMinwoo Im return false; 527a53232cbSKeith Busch if (!nvmeq->qid) 528955b1b5aSMinwoo Im return false; 529955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 530955b1b5aSMinwoo Im return false; 531955b1b5aSMinwoo Im return true; 532955b1b5aSMinwoo Im } 533955b1b5aSMinwoo Im 5349275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 53557dacad5SJay Sternberg { 5366c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5379275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5389275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 53957dacad5SJay Sternberg int i; 54057dacad5SJay Sternberg 541c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5429275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5439275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5449275c206SChristoph Hellwig 5459275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5469275c206SChristoph Hellwig dma_addr = next_dma_addr; 547dff824b2SChristoph Hellwig } 5489275c206SChristoph Hellwig } 5499275c206SChristoph Hellwig 5509275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5519275c206SChristoph Hellwig { 5529275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5539275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5549275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5559275c206SChristoph Hellwig int i; 5569275c206SChristoph Hellwig 557c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 5589275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5599275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5609275c206SChristoph Hellwig 5619275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5629275c206SChristoph Hellwig dma_addr = next_dma_addr; 5639275c206SChristoph Hellwig } 5649275c206SChristoph Hellwig } 5659275c206SChristoph Hellwig 5669275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5679275c206SChristoph Hellwig { 5689275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5697fe07d14SChristoph Hellwig 5709275c206SChristoph Hellwig if (iod->dma_len) { 5719275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5729275c206SChristoph Hellwig rq_dma_dir(req)); 5739275c206SChristoph Hellwig return; 5749275c206SChristoph Hellwig } 5759275c206SChristoph Hellwig 57691fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5779275c206SChristoph Hellwig 57891fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 57991fb2b60SLogan Gunthorpe 580c372cdd1SKeith Busch if (iod->nr_allocations == 0) 581a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 5829275c206SChristoph Hellwig iod->first_dma); 5839275c206SChristoph Hellwig else if (iod->use_sgl) 5849275c206SChristoph Hellwig nvme_free_sgls(dev, req); 5859275c206SChristoph Hellwig else 5869275c206SChristoph Hellwig nvme_free_prps(dev, req); 58791fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 58857dacad5SJay Sternberg } 58957dacad5SJay Sternberg 590d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 591d0877473SKeith Busch { 592d0877473SKeith Busch int i; 593d0877473SKeith Busch struct scatterlist *sg; 594d0877473SKeith Busch 595d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 596d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 597d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 598d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 599d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 600d0877473SKeith Busch sg_dma_len(sg)); 601d0877473SKeith Busch } 602d0877473SKeith Busch } 603d0877473SKeith Busch 604a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 605a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 60657dacad5SJay Sternberg { 607f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 60857dacad5SJay Sternberg struct dma_pool *pool; 609b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 61091fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 61157dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 61257dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6136c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 61457dacad5SJay Sternberg __le64 *prp_list; 615a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 61657dacad5SJay Sternberg dma_addr_t prp_dma; 61757dacad5SJay Sternberg int nprps, i; 61857dacad5SJay Sternberg 6196c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6205228b328SJan H. Schönherr if (length <= 0) { 6215228b328SJan H. Schönherr iod->first_dma = 0; 622a7a7cbe3SChaitanya Kulkarni goto done; 6235228b328SJan H. Schönherr } 62457dacad5SJay Sternberg 6256c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 62657dacad5SJay Sternberg if (dma_len) { 6276c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 62857dacad5SJay Sternberg } else { 62957dacad5SJay Sternberg sg = sg_next(sg); 63057dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 63157dacad5SJay Sternberg dma_len = sg_dma_len(sg); 63257dacad5SJay Sternberg } 63357dacad5SJay Sternberg 6346c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 63557dacad5SJay Sternberg iod->first_dma = dma_addr; 636a7a7cbe3SChaitanya Kulkarni goto done; 63757dacad5SJay Sternberg } 63857dacad5SJay Sternberg 6396c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 64057dacad5SJay Sternberg if (nprps <= (256 / 8)) { 64157dacad5SJay Sternberg pool = dev->prp_small_pool; 642c372cdd1SKeith Busch iod->nr_allocations = 0; 64357dacad5SJay Sternberg } else { 64457dacad5SJay Sternberg pool = dev->prp_page_pool; 645c372cdd1SKeith Busch iod->nr_allocations = 1; 64657dacad5SJay Sternberg } 64757dacad5SJay Sternberg 64869d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 64957dacad5SJay Sternberg if (!prp_list) { 650c372cdd1SKeith Busch iod->nr_allocations = -1; 65186eea289SKeith Busch return BLK_STS_RESOURCE; 65257dacad5SJay Sternberg } 65357dacad5SJay Sternberg list[0] = prp_list; 65457dacad5SJay Sternberg iod->first_dma = prp_dma; 65557dacad5SJay Sternberg i = 0; 65657dacad5SJay Sternberg for (;;) { 6576c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 65857dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 65969d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 66057dacad5SJay Sternberg if (!prp_list) 661fa073216SChristoph Hellwig goto free_prps; 662c372cdd1SKeith Busch list[iod->nr_allocations++] = prp_list; 66357dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 66457dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 66557dacad5SJay Sternberg i = 1; 66657dacad5SJay Sternberg } 66757dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6686c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6696c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6706c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 67157dacad5SJay Sternberg if (length <= 0) 67257dacad5SJay Sternberg break; 67357dacad5SJay Sternberg if (dma_len > 0) 67457dacad5SJay Sternberg continue; 67586eea289SKeith Busch if (unlikely(dma_len < 0)) 67686eea289SKeith Busch goto bad_sgl; 67757dacad5SJay Sternberg sg = sg_next(sg); 67857dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 67957dacad5SJay Sternberg dma_len = sg_dma_len(sg); 68057dacad5SJay Sternberg } 681a7a7cbe3SChaitanya Kulkarni done: 68291fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 683a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 68486eea289SKeith Busch return BLK_STS_OK; 685fa073216SChristoph Hellwig free_prps: 686fa073216SChristoph Hellwig nvme_free_prps(dev, req); 687fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 68886eea289SKeith Busch bad_sgl: 68991fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 690d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 69191fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 69286eea289SKeith Busch return BLK_STS_IOERR; 69357dacad5SJay Sternberg } 69457dacad5SJay Sternberg 695a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 696a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 697a7a7cbe3SChaitanya Kulkarni { 698a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 699a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 700a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 701a7a7cbe3SChaitanya Kulkarni } 702a7a7cbe3SChaitanya Kulkarni 703a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 704a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 705a7a7cbe3SChaitanya Kulkarni { 706a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 707a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 708a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 709a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 710a7a7cbe3SChaitanya Kulkarni } else { 711a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 712a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 713a7a7cbe3SChaitanya Kulkarni } 714a7a7cbe3SChaitanya Kulkarni } 715a7a7cbe3SChaitanya Kulkarni 716a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 71791fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 718a7a7cbe3SChaitanya Kulkarni { 719a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 720a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 721a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 72291fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 72391fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 724a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 725b0f2853bSChristoph Hellwig int i = 0; 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 728a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 729a7a7cbe3SChaitanya Kulkarni 730b0f2853bSChristoph Hellwig if (entries == 1) { 731a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 732a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 733a7a7cbe3SChaitanya Kulkarni } 734a7a7cbe3SChaitanya Kulkarni 735a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 736a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 737c372cdd1SKeith Busch iod->nr_allocations = 0; 738a7a7cbe3SChaitanya Kulkarni } else { 739a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 740c372cdd1SKeith Busch iod->nr_allocations = 1; 741a7a7cbe3SChaitanya Kulkarni } 742a7a7cbe3SChaitanya Kulkarni 743a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 744a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 745c372cdd1SKeith Busch iod->nr_allocations = -1; 746a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 747a7a7cbe3SChaitanya Kulkarni } 748a7a7cbe3SChaitanya Kulkarni 749a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 750a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 751a7a7cbe3SChaitanya Kulkarni 752a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 753a7a7cbe3SChaitanya Kulkarni 754a7a7cbe3SChaitanya Kulkarni do { 755a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 756a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 757a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 758a7a7cbe3SChaitanya Kulkarni 759a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 760a7a7cbe3SChaitanya Kulkarni if (!sg_list) 761fa073216SChristoph Hellwig goto free_sgls; 762a7a7cbe3SChaitanya Kulkarni 763a7a7cbe3SChaitanya Kulkarni i = 0; 764c372cdd1SKeith Busch nvme_pci_iod_list(req)[iod->nr_allocations++] = sg_list; 765a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 766a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 767a7a7cbe3SChaitanya Kulkarni } 768a7a7cbe3SChaitanya Kulkarni 769a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 770a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 771b0f2853bSChristoph Hellwig } while (--entries > 0); 772a7a7cbe3SChaitanya Kulkarni 773a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 774fa073216SChristoph Hellwig free_sgls: 775fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 776fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 777a7a7cbe3SChaitanya Kulkarni } 778a7a7cbe3SChaitanya Kulkarni 779dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 780dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 781dff824b2SChristoph Hellwig struct bio_vec *bv) 782dff824b2SChristoph Hellwig { 783dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7846c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7856c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 786dff824b2SChristoph Hellwig 787dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 788dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 789dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 790dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 791dff824b2SChristoph Hellwig 792dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 793dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 794dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 795359c1f88SBaolin Wang return BLK_STS_OK; 796dff824b2SChristoph Hellwig } 797dff824b2SChristoph Hellwig 79829791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 79929791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 80029791057SChristoph Hellwig struct bio_vec *bv) 80129791057SChristoph Hellwig { 80229791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 80329791057SChristoph Hellwig 80429791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 80529791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 80629791057SChristoph Hellwig return BLK_STS_RESOURCE; 80729791057SChristoph Hellwig iod->dma_len = bv->bv_len; 80829791057SChristoph Hellwig 809049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 81029791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 81129791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 81229791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 813359c1f88SBaolin Wang return BLK_STS_OK; 81429791057SChristoph Hellwig } 81529791057SChristoph Hellwig 816fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 817b131c61dSChristoph Hellwig struct nvme_command *cmnd) 81857dacad5SJay Sternberg { 819f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82070479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 82191fb2b60SLogan Gunthorpe int rc; 82257dacad5SJay Sternberg 823dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 824a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 825dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 826dff824b2SChristoph Hellwig 827dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8286c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 829dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 830dff824b2SChristoph Hellwig &cmnd->rw, &bv); 83129791057SChristoph Hellwig 832a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 833253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 83429791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 83529791057SChristoph Hellwig &cmnd->rw, &bv); 836dff824b2SChristoph Hellwig } 837dff824b2SChristoph Hellwig } 838dff824b2SChristoph Hellwig 839dff824b2SChristoph Hellwig iod->dma_len = 0; 84091fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 84191fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 8429b048119SChristoph Hellwig return BLK_STS_RESOURCE; 84391fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 84491fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 84591fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 846fa073216SChristoph Hellwig goto out_free_sg; 847ba1ca37eSChristoph Hellwig 84891fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 84991fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 85091fb2b60SLogan Gunthorpe if (rc) { 85191fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 85291fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 853fa073216SChristoph Hellwig goto out_free_sg; 85491fb2b60SLogan Gunthorpe } 855ba1ca37eSChristoph Hellwig 85670479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 857955b1b5aSMinwoo Im if (iod->use_sgl) 85891fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 859a7a7cbe3SChaitanya Kulkarni else 860a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8614aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 862fa073216SChristoph Hellwig goto out_unmap_sg; 863fa073216SChristoph Hellwig return BLK_STS_OK; 864fa073216SChristoph Hellwig 865fa073216SChristoph Hellwig out_unmap_sg: 86691fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 867fa073216SChristoph Hellwig out_free_sg: 86891fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 869ba1ca37eSChristoph Hellwig return ret; 87057dacad5SJay Sternberg } 87157dacad5SJay Sternberg 8724aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8734aedb705SChristoph Hellwig struct nvme_command *cmnd) 8744aedb705SChristoph Hellwig { 8754aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8764aedb705SChristoph Hellwig 8774aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8784aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8794aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8804aedb705SChristoph Hellwig return BLK_STS_IOERR; 8814aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 882359c1f88SBaolin Wang return BLK_STS_OK; 8834aedb705SChristoph Hellwig } 8844aedb705SChristoph Hellwig 88562451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 88662451a2bSJens Axboe { 88762451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 88862451a2bSJens Axboe blk_status_t ret; 88962451a2bSJens Axboe 89052da4f3fSKeith Busch iod->aborted = false; 891c372cdd1SKeith Busch iod->nr_allocations = -1; 89291fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 89362451a2bSJens Axboe 89462451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 89562451a2bSJens Axboe if (ret) 89662451a2bSJens Axboe return ret; 89762451a2bSJens Axboe 89862451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 89962451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 90062451a2bSJens Axboe if (ret) 90162451a2bSJens Axboe goto out_free_cmd; 90262451a2bSJens Axboe } 90362451a2bSJens Axboe 90462451a2bSJens Axboe if (blk_integrity_rq(req)) { 90562451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 90662451a2bSJens Axboe if (ret) 90762451a2bSJens Axboe goto out_unmap_data; 90862451a2bSJens Axboe } 90962451a2bSJens Axboe 9106887fc64SSagi Grimberg nvme_start_request(req); 91162451a2bSJens Axboe return BLK_STS_OK; 91262451a2bSJens Axboe out_unmap_data: 91362451a2bSJens Axboe nvme_unmap_data(dev, req); 91462451a2bSJens Axboe out_free_cmd: 91562451a2bSJens Axboe nvme_cleanup_cmd(req); 91662451a2bSJens Axboe return ret; 91762451a2bSJens Axboe } 91862451a2bSJens Axboe 91957dacad5SJay Sternberg /* 92057dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 92157dacad5SJay Sternberg */ 922fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 92357dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 92457dacad5SJay Sternberg { 92557dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 92657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 92757dacad5SJay Sternberg struct request *req = bd->rq; 9289b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 929ebe6d874SChristoph Hellwig blk_status_t ret; 93057dacad5SJay Sternberg 931d1f06f4aSJens Axboe /* 932d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 933d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 934d1f06f4aSJens Axboe */ 9354e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 936d1f06f4aSJens Axboe return BLK_STS_IOERR; 937d1f06f4aSJens Axboe 93862451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 939d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 940d4060d2bSTao Chiu 94162451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 94262451a2bSJens Axboe if (unlikely(ret)) 943f4800d6dSChristoph Hellwig return ret; 9443233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9453233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9463233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9473233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 948fc17b653SChristoph Hellwig return BLK_STS_OK; 94957dacad5SJay Sternberg } 95057dacad5SJay Sternberg 951d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 952d62cbcf6SJens Axboe { 953d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 954d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 955d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 956d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 957d62cbcf6SJens Axboe 958d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 959d62cbcf6SJens Axboe } 960d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 961d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 962d62cbcf6SJens Axboe } 963d62cbcf6SJens Axboe 964d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 965d62cbcf6SJens Axboe { 966d62cbcf6SJens Axboe /* 967d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 968d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 969d62cbcf6SJens Axboe */ 970d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 971d62cbcf6SJens Axboe return false; 972d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 973d62cbcf6SJens Axboe return false; 974d62cbcf6SJens Axboe 975d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 976d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 977d62cbcf6SJens Axboe } 978d62cbcf6SJens Axboe 979d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 980d62cbcf6SJens Axboe { 9816bfec799SKeith Busch struct request *req, *next, *prev = NULL; 982d62cbcf6SJens Axboe struct request *requeue_list = NULL; 983d62cbcf6SJens Axboe 9846bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 985d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 986d62cbcf6SJens Axboe 987d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 988d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9896bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9906bfec799SKeith Busch 9916bfec799SKeith Busch req = prev; 9926bfec799SKeith Busch if (!req) 9936bfec799SKeith Busch continue; 994d62cbcf6SJens Axboe } 995d62cbcf6SJens Axboe 9966bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 997d62cbcf6SJens Axboe /* detach rest of list, and submit */ 9986bfec799SKeith Busch req->rq_next = NULL; 999d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 10006bfec799SKeith Busch *rqlist = next; 10016bfec799SKeith Busch prev = NULL; 10026bfec799SKeith Busch } else 10036bfec799SKeith Busch prev = req; 1004d62cbcf6SJens Axboe } 1005d62cbcf6SJens Axboe 1006d62cbcf6SJens Axboe *rqlist = requeue_list; 1007d62cbcf6SJens Axboe } 1008d62cbcf6SJens Axboe 1009c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1010eee417b0SChristoph Hellwig { 1011a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1012a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 1013eee417b0SChristoph Hellwig 1014a53232cbSKeith Busch if (blk_integrity_rq(req)) { 1015a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1016a53232cbSKeith Busch 10174aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10184aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1019a53232cbSKeith Busch } 1020a53232cbSKeith Busch 1021b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10224aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1023c234a653SJens Axboe } 1024c234a653SJens Axboe 1025c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1026c234a653SJens Axboe { 1027c234a653SJens Axboe nvme_pci_unmap_rq(req); 102877f02a7aSChristoph Hellwig nvme_complete_rq(req); 102957dacad5SJay Sternberg } 103057dacad5SJay Sternberg 1031c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1032c234a653SJens Axboe { 1033c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1034c234a653SJens Axboe } 1035c234a653SJens Axboe 1036d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1037750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1038d783e0bdSMarta Rybczynska { 103974943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 104074943d45SKeith Busch 104174943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1042d783e0bdSMarta Rybczynska } 1043d783e0bdSMarta Rybczynska 1044eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 104557dacad5SJay Sternberg { 1046eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 104757dacad5SJay Sternberg 1048eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1049eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1050eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1051eb281c82SSagi Grimberg } 1052adf68f21SChristoph Hellwig 1053cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1054cfa27356SChristoph Hellwig { 1055cfa27356SChristoph Hellwig if (!nvmeq->qid) 1056cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1057cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1058cfa27356SChristoph Hellwig } 1059cfa27356SChristoph Hellwig 1060c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1061c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 106257dacad5SJay Sternberg { 106374943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 106462df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 106557dacad5SJay Sternberg struct request *req; 1066adf68f21SChristoph Hellwig 1067adf68f21SChristoph Hellwig /* 1068adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1069adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1070adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1071adf68f21SChristoph Hellwig * for them but rather special case them here. 1072adf68f21SChristoph Hellwig */ 107362df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10747bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 107583a12fb7SSagi Grimberg cqe->status, &cqe->result); 1076a0fa9647SJens Axboe return; 107757dacad5SJay Sternberg } 107857dacad5SJay Sternberg 1079e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 108050b7c243SXianting Tian if (unlikely(!req)) { 108150b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 108250b7c243SXianting Tian "invalid id %d completed on queue %d\n", 108362df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 108450b7c243SXianting Tian return; 108550b7c243SXianting Tian } 108650b7c243SXianting Tian 1087604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1088c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1089c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1090c234a653SJens Axboe nvme_pci_complete_batch)) 1091ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 109283a12fb7SSagi Grimberg } 109357dacad5SJay Sternberg 10945cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10955cb525c8SJens Axboe { 1096a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1097a8de6639SAlexey Dobriyan 1098a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1099920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1100e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1101a8de6639SAlexey Dobriyan } else { 1102a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1103920d13a8SSagi Grimberg } 1104a0fa9647SJens Axboe } 1105a0fa9647SJens Axboe 1106c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1107c234a653SJens Axboe struct io_comp_batch *iob) 1108a0fa9647SJens Axboe { 11091052b8acSJens Axboe int found = 0; 111083a12fb7SSagi Grimberg 11111052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11121052b8acSJens Axboe found++; 1113b69e2ef2SKeith Busch /* 1114b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1115b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1116b69e2ef2SKeith Busch */ 1117b69e2ef2SKeith Busch dma_rmb(); 1118c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11195cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 112057dacad5SJay Sternberg } 112157dacad5SJay Sternberg 1122324b494cSKeith Busch if (found) 1123eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11245cb525c8SJens Axboe return found; 112557dacad5SJay Sternberg } 112657dacad5SJay Sternberg 112757dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 112857dacad5SJay Sternberg { 112957dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11304f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11315cb525c8SJens Axboe 11324f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11334f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11344f502245SJens Axboe nvme_pci_complete_batch(&iob); 113505fae499SChaitanya Kulkarni return IRQ_HANDLED; 11364f502245SJens Axboe } 113705fae499SChaitanya Kulkarni return IRQ_NONE; 113857dacad5SJay Sternberg } 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 114157dacad5SJay Sternberg { 114257dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11434e523547SBaolin Wang 1144750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 114557dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1146d783e0bdSMarta Rybczynska return IRQ_NONE; 114757dacad5SJay Sternberg } 114857dacad5SJay Sternberg 11490b2a8a9fSChristoph Hellwig /* 1150fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11510b2a8a9fSChristoph Hellwig * Can be called from any context. 11520b2a8a9fSChristoph Hellwig */ 1153fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1154a0fa9647SJens Axboe { 11553a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1156a0fa9647SJens Axboe 1157fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1158fa059b85SKeith Busch 11593a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1160c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11613a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 116291a509f8SChristoph Hellwig } 1163442e19b7SSagi Grimberg 11645a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11657776db1cSKeith Busch { 11667776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1167dabcefabSJens Axboe bool found; 1168dabcefabSJens Axboe 1169dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1170dabcefabSJens Axboe return 0; 1171dabcefabSJens Axboe 11723a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1173c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11743a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1175dabcefabSJens Axboe 1176dabcefabSJens Axboe return found; 1177dabcefabSJens Axboe } 1178dabcefabSJens Axboe 1179ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 118057dacad5SJay Sternberg { 1181f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1182147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1183f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118457dacad5SJay Sternberg 118557dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1186ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11873233b94cSJens Axboe 11883233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11893233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11903233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11913233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 119257dacad5SJay Sternberg } 119357dacad5SJay Sternberg 119457dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 119557dacad5SJay Sternberg { 1196f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 119757dacad5SJay Sternberg 119857dacad5SJay Sternberg c.delete_queue.opcode = opcode; 119957dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 120057dacad5SJay Sternberg 12011c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120257dacad5SJay Sternberg } 120357dacad5SJay Sternberg 120457dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1205a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 120657dacad5SJay Sternberg { 1207f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12084b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12094b04cc6aSJens Axboe 12107c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12114b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg /* 121416772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 121557dacad5SJay Sternberg * is attached to the request. 121657dacad5SJay Sternberg */ 121757dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 121857dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 121957dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 122057dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 122157dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1222a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 122357dacad5SJay Sternberg 12241c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122557dacad5SJay Sternberg } 122657dacad5SJay Sternberg 122757dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 122857dacad5SJay Sternberg struct nvme_queue *nvmeq) 122957dacad5SJay Sternberg { 12309abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1231f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 123281c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 123357dacad5SJay Sternberg 123457dacad5SJay Sternberg /* 12359abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12369abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12379abd68efSJens Axboe * URGENT. 12389abd68efSJens Axboe */ 12399abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12409abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12419abd68efSJens Axboe 12429abd68efSJens Axboe /* 124316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 124457dacad5SJay Sternberg * is attached to the request. 124557dacad5SJay Sternberg */ 124657dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 124757dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 124857dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 124957dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 125057dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 125157dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 125257dacad5SJay Sternberg 12531c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 125457dacad5SJay Sternberg } 125557dacad5SJay Sternberg 125657dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 125757dacad5SJay Sternberg { 125857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 125957dacad5SJay Sternberg } 126057dacad5SJay Sternberg 126157dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 126257dacad5SJay Sternberg { 126357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 126457dacad5SJay Sternberg } 126557dacad5SJay Sternberg 1266de671d61SJens Axboe static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 126757dacad5SJay Sternberg { 1268a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 126957dacad5SJay Sternberg 127027fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 127127fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1272e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1273e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 1274de671d61SJens Axboe return RQ_END_IO_NONE; 127557dacad5SJay Sternberg } 127657dacad5SJay Sternberg 1277b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1278b2a0eb1aSKeith Busch { 1279b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1280b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1281b2a0eb1aSKeith Busch */ 1282b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1283b2a0eb1aSKeith Busch 1284ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1285ad70062cSJianchao Wang switch (dev->ctrl.state) { 1286ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1287ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1288b2a0eb1aSKeith Busch return false; 1289ad70062cSJianchao Wang default: 1290ad70062cSJianchao Wang break; 1291ad70062cSJianchao Wang } 1292b2a0eb1aSKeith Busch 1293b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1294b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1295b2a0eb1aSKeith Busch */ 1296b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1297b2a0eb1aSKeith Busch return false; 1298b2a0eb1aSKeith Busch 1299b2a0eb1aSKeith Busch return true; 1300b2a0eb1aSKeith Busch } 1301b2a0eb1aSKeith Busch 1302b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1303b2a0eb1aSKeith Busch { 1304b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1305b2a0eb1aSKeith Busch u16 pci_status; 1306b2a0eb1aSKeith Busch int result; 1307b2a0eb1aSKeith Busch 1308b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1309b2a0eb1aSKeith Busch &pci_status); 1310b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1311b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1312b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1313b2a0eb1aSKeith Busch csts, pci_status); 1314b2a0eb1aSKeith Busch else 1315b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1316b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1317b2a0eb1aSKeith Busch csts, result); 13184641a8e6SKeith Busch 13194641a8e6SKeith Busch if (csts != ~0) 13204641a8e6SKeith Busch return; 13214641a8e6SKeith Busch 13224641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13234641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 13244641a8e6SKeith Busch dev_warn(dev->ctrl.device, 13254641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1326b2a0eb1aSKeith Busch } 1327b2a0eb1aSKeith Busch 13289bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 132957dacad5SJay Sternberg { 1330f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1331a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 133257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 133357dacad5SJay Sternberg struct request *abort_req; 1334f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1335b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1336b2a0eb1aSKeith Busch 1337651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1338651438bbSWen Xiong * the recovery mechanism will surely fail. 1339651438bbSWen Xiong */ 1340651438bbSWen Xiong mb(); 1341651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1342651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1343651438bbSWen Xiong 1344b2a0eb1aSKeith Busch /* 1345b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1346b2a0eb1aSKeith Busch */ 1347b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1348b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1349b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1350d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1351db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1352b2a0eb1aSKeith Busch } 135357dacad5SJay Sternberg 135431c7c7d2SChristoph Hellwig /* 13557776db1cSKeith Busch * Did we miss an interrupt? 13567776db1cSKeith Busch */ 1357fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13585a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1359fa059b85SKeith Busch else 1360bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1361fa059b85SKeith Busch 1362bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13637776db1cSKeith Busch dev_warn(dev->ctrl.device, 13647776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13657776db1cSKeith Busch req->tag, nvmeq->qid); 1366db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13677776db1cSKeith Busch } 13687776db1cSKeith Busch 13697776db1cSKeith Busch /* 1370fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1371fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1372fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1373db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1374fd634f41SChristoph Hellwig */ 13754244140dSKeith Busch switch (dev->ctrl.state) { 13764244140dSKeith Busch case NVME_CTRL_CONNECTING: 13772036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1378df561f66SGustavo A. R. Silva fallthrough; 13792036f726SKeith Busch case NVME_CTRL_DELETING: 1380b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1381fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1382fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 138327fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13847ad92f65STong Zhang nvme_dev_disable(dev, true); 1385db8c48e4SChristoph Hellwig return BLK_EH_DONE; 138639a9dd81SKeith Busch case NVME_CTRL_RESETTING: 138739a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13884244140dSKeith Busch default: 13894244140dSKeith Busch break; 1390fd634f41SChristoph Hellwig } 1391fd634f41SChristoph Hellwig 1392fd634f41SChristoph Hellwig /* 1393e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1394e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1395e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 139631c7c7d2SChristoph Hellwig */ 1397f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13981b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 139957dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 140057dacad5SJay Sternberg req->tag, nvmeq->qid); 14017ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1402a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1403d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1404e1569a16SKeith Busch 1405db8c48e4SChristoph Hellwig return BLK_EH_DONE; 140657dacad5SJay Sternberg } 140757dacad5SJay Sternberg 1408e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1409e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1410e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1411e7a2a87dSChristoph Hellwig } 141252da4f3fSKeith Busch iod->aborted = true; 141357dacad5SJay Sternberg 141457dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 141585f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 141657dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 141757dacad5SJay Sternberg 14181b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 141986141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 142086141440SChristoph Hellwig req->tag, 142186141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 142286141440SChristoph Hellwig nvmeq->qid); 1423e7a2a87dSChristoph Hellwig 1424e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 142539dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14266bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14276bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 142831c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 142957dacad5SJay Sternberg } 1430e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 143157dacad5SJay Sternberg 1432e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1433e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1434128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1435e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 143657dacad5SJay Sternberg 143757dacad5SJay Sternberg /* 143857dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 143957dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 144057dacad5SJay Sternberg * as the device then is in a faulty state. 144157dacad5SJay Sternberg */ 144257dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 144357dacad5SJay Sternberg } 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 144657dacad5SJay Sternberg { 14478a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 144857dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 144963223078SChristoph Hellwig if (!nvmeq->sq_cmds) 145063223078SChristoph Hellwig return; 14510f238ff5SLogan Gunthorpe 145263223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 145388a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14548a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 145563223078SChristoph Hellwig } else { 14568a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 145763223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14580f238ff5SLogan Gunthorpe } 145957dacad5SJay Sternberg } 146057dacad5SJay Sternberg 146157dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 146257dacad5SJay Sternberg { 146357dacad5SJay Sternberg int i; 146457dacad5SJay Sternberg 1465d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1466d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1467147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 146857dacad5SJay Sternberg } 146957dacad5SJay Sternberg } 147057dacad5SJay Sternberg 147110981f23SChristoph Hellwig static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid) 147257dacad5SJay Sternberg { 147310981f23SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[qid]; 147410981f23SChristoph Hellwig 14754e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 147610981f23SChristoph Hellwig return; 147757dacad5SJay Sternberg 14784e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1479d1f06f4aSJens Axboe mb(); 148057dacad5SJay Sternberg 14814e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14821c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14839f27bd70SChristoph Hellwig nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 14847c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 148510981f23SChristoph Hellwig pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); 148657dacad5SJay Sternberg } 148757dacad5SJay Sternberg 14888fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14898fae268bSKeith Busch { 14908fae268bSKeith Busch int i; 14918fae268bSKeith Busch 14928fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 149310981f23SChristoph Hellwig nvme_suspend_queue(dev, i); 14948fae268bSKeith Busch } 14958fae268bSKeith Busch 1496fa46c6fbSKeith Busch /* 1497fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14989210c075SDongli Zhang * that can check this device's completion queues have synced, except 14999210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15009210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1501fa46c6fbSKeith Busch */ 1502fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1503fa46c6fbSKeith Busch { 1504fa46c6fbSKeith Busch int i; 1505fa46c6fbSKeith Busch 15069210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15079210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1508c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15099210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15109210c075SDongli Zhang } 1511fa46c6fbSKeith Busch } 1512fa46c6fbSKeith Busch 151357dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 151457dacad5SJay Sternberg int entry_size) 151557dacad5SJay Sternberg { 151657dacad5SJay Sternberg int q_depth = dev->q_depth; 15175fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15186c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 151957dacad5SJay Sternberg 152057dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 152157dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15224e523547SBaolin Wang 15236c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 152457dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 152557dacad5SJay Sternberg 152657dacad5SJay Sternberg /* 152757dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 152857dacad5SJay Sternberg * would be better to map queues in system memory with the 152957dacad5SJay Sternberg * original depth 153057dacad5SJay Sternberg */ 153157dacad5SJay Sternberg if (q_depth < 64) 153257dacad5SJay Sternberg return -ENOMEM; 153357dacad5SJay Sternberg } 153457dacad5SJay Sternberg 153557dacad5SJay Sternberg return q_depth; 153657dacad5SJay Sternberg } 153757dacad5SJay Sternberg 153857dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15398a1d09a6SBenjamin Herrenschmidt int qid) 154057dacad5SJay Sternberg { 15410f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1542815c6704SKeith Busch 15430f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15448a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1545bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15460f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15470f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 154863223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 154963223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 155063223078SChristoph Hellwig return 0; 155163223078SChristoph Hellwig } 1552bfac8e9fSAlan Mikhak 15538a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1554bfac8e9fSAlan Mikhak } 15550f238ff5SLogan Gunthorpe } 15560f238ff5SLogan Gunthorpe 15578a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 155857dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 155957dacad5SJay Sternberg if (!nvmeq->sq_cmds) 156057dacad5SJay Sternberg return -ENOMEM; 156157dacad5SJay Sternberg return 0; 156257dacad5SJay Sternberg } 156357dacad5SJay Sternberg 1564a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 156557dacad5SJay Sternberg { 1566147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 156757dacad5SJay Sternberg 156862314e40SKeith Busch if (dev->ctrl.queue_count > qid) 156962314e40SKeith Busch return 0; 157057dacad5SJay Sternberg 1571c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15728a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15738a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 157457dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 157557dacad5SJay Sternberg if (!nvmeq->cqes) 157657dacad5SJay Sternberg goto free_nvmeq; 157757dacad5SJay Sternberg 15788a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 157957dacad5SJay Sternberg goto free_cqdma; 158057dacad5SJay Sternberg 158157dacad5SJay Sternberg nvmeq->dev = dev; 15821ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15833a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 158457dacad5SJay Sternberg nvmeq->cq_head = 0; 158557dacad5SJay Sternberg nvmeq->cq_phase = 1; 158657dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 158757dacad5SJay Sternberg nvmeq->qid = qid; 1588d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 158957dacad5SJay Sternberg 1590147b27e4SSagi Grimberg return 0; 159157dacad5SJay Sternberg 159257dacad5SJay Sternberg free_cqdma: 15938a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 159457dacad5SJay Sternberg nvmeq->cq_dma_addr); 159557dacad5SJay Sternberg free_nvmeq: 1596147b27e4SSagi Grimberg return -ENOMEM; 159757dacad5SJay Sternberg } 159857dacad5SJay Sternberg 1599dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 160057dacad5SJay Sternberg { 16010ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16020ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16030ff199cbSChristoph Hellwig 16040ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16050ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16060ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16070ff199cbSChristoph Hellwig } else { 16080ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16090ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16100ff199cbSChristoph Hellwig } 161157dacad5SJay Sternberg } 161257dacad5SJay Sternberg 161357dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 161457dacad5SJay Sternberg { 161557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 161657dacad5SJay Sternberg 161757dacad5SJay Sternberg nvmeq->sq_tail = 0; 161838210800SKeith Busch nvmeq->last_sq_tail = 0; 161957dacad5SJay Sternberg nvmeq->cq_head = 0; 162057dacad5SJay Sternberg nvmeq->cq_phase = 1; 162157dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16228a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1623f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 162457dacad5SJay Sternberg dev->online_queues++; 16253a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 162657dacad5SJay Sternberg } 162757dacad5SJay Sternberg 1628e4b9852aSCasey Chen /* 1629e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1630e4b9852aSCasey Chen */ 1631e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1632e4b9852aSCasey Chen { 1633e4b9852aSCasey Chen /* 1634e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1635e4b9852aSCasey Chen */ 1636e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1637e4b9852aSCasey Chen return -ENODEV; 1638e4b9852aSCasey Chen 1639e4b9852aSCasey Chen /* 1640e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1641e4b9852aSCasey Chen */ 1642e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1643e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1644e4b9852aSCasey Chen return -ENODEV; 1645e4b9852aSCasey Chen } 1646e4b9852aSCasey Chen 1647e4b9852aSCasey Chen return 0; 1648e4b9852aSCasey Chen } 1649e4b9852aSCasey Chen 16504b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 165157dacad5SJay Sternberg { 165257dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 165357dacad5SJay Sternberg int result; 16547c349ddeSKeith Busch u16 vector = 0; 165557dacad5SJay Sternberg 1656d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1657d1ed6aa1SChristoph Hellwig 165822b55601SKeith Busch /* 165922b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 166022b55601SKeith Busch * has only one vector available. 166122b55601SKeith Busch */ 16624b04cc6aSJens Axboe if (!polled) 1663a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16644b04cc6aSJens Axboe else 16657c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16664b04cc6aSJens Axboe 1667a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1668ded45505SKeith Busch if (result) 1669ded45505SKeith Busch return result; 167057dacad5SJay Sternberg 167157dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 167257dacad5SJay Sternberg if (result < 0) 1673ded45505SKeith Busch return result; 1674c80b36cdSEdmund Nadolski if (result) 167557dacad5SJay Sternberg goto release_cq; 167657dacad5SJay Sternberg 1677a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16784b04cc6aSJens Axboe 1679e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1680e4b9852aSCasey Chen if (result) 1681e4b9852aSCasey Chen return result; 1682e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16837c349ddeSKeith Busch if (!polled) { 1684dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 168557dacad5SJay Sternberg if (result < 0) 168657dacad5SJay Sternberg goto release_sq; 16874b04cc6aSJens Axboe } 168857dacad5SJay Sternberg 16894e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1690e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 169157dacad5SJay Sternberg return result; 169257dacad5SJay Sternberg 169357dacad5SJay Sternberg release_sq: 1694f25a2dfcSJianchao Wang dev->online_queues--; 1695e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 169657dacad5SJay Sternberg adapter_delete_sq(dev, qid); 169757dacad5SJay Sternberg release_cq: 169857dacad5SJay Sternberg adapter_delete_cq(dev, qid); 169957dacad5SJay Sternberg return result; 170057dacad5SJay Sternberg } 170157dacad5SJay Sternberg 1702f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 170357dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 170477f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 170557dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1706e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 170757dacad5SJay Sternberg .timeout = nvme_timeout, 170857dacad5SJay Sternberg }; 170957dacad5SJay Sternberg 1710f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1711376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1712d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1713376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1714376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1715376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1716e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1717376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1718376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1719c6d962aeSChristoph Hellwig .poll = nvme_poll, 1720dabcefabSJens Axboe }; 1721dabcefabSJens Axboe 172257dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 172357dacad5SJay Sternberg { 17241c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 172569d9a99cSKeith Busch /* 172669d9a99cSKeith Busch * If the controller was reset during removal, it's possible 172769d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 172869d9a99cSKeith Busch * queue to flush these to completion. 172969d9a99cSKeith Busch */ 17309f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 17316f8191fdSChristoph Hellwig blk_mq_destroy_queue(dev->ctrl.admin_q); 173296ef1be5SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 173357dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 173457dacad5SJay Sternberg } 173557dacad5SJay Sternberg } 173657dacad5SJay Sternberg 1737f91b727cSChristoph Hellwig static int nvme_pci_alloc_admin_tag_set(struct nvme_dev *dev) 173857dacad5SJay Sternberg { 1739f91b727cSChristoph Hellwig struct blk_mq_tag_set *set = &dev->admin_tagset; 1740e3e9d50cSKeith Busch 1741f91b727cSChristoph Hellwig set->ops = &nvme_mq_admin_ops; 1742f91b727cSChristoph Hellwig set->nr_hw_queues = 1; 174357dacad5SJay Sternberg 1744f91b727cSChristoph Hellwig set->queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1745f91b727cSChristoph Hellwig set->timeout = NVME_ADMIN_TIMEOUT; 1746f91b727cSChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 1747f91b727cSChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 1748f91b727cSChristoph Hellwig set->flags = BLK_MQ_F_NO_SCHED; 1749f91b727cSChristoph Hellwig set->driver_data = dev; 1750f91b727cSChristoph Hellwig 1751f91b727cSChristoph Hellwig if (blk_mq_alloc_tag_set(set)) 175257dacad5SJay Sternberg return -ENOMEM; 1753f91b727cSChristoph Hellwig dev->ctrl.admin_tagset = set; 175457dacad5SJay Sternberg 1755f91b727cSChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(set); 17561c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 1757f91b727cSChristoph Hellwig blk_mq_free_tag_set(set); 1758da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 175957dacad5SJay Sternberg return -ENOMEM; 176057dacad5SJay Sternberg } 176157dacad5SJay Sternberg return 0; 176257dacad5SJay Sternberg } 176357dacad5SJay Sternberg 176497f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 176597f6ef64SXu Yu { 176697f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 176797f6ef64SXu Yu } 176897f6ef64SXu Yu 176997f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 177097f6ef64SXu Yu { 177197f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 177297f6ef64SXu Yu 177397f6ef64SXu Yu if (size <= dev->bar_mapped_size) 177497f6ef64SXu Yu return 0; 177597f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 177697f6ef64SXu Yu return -ENOMEM; 177797f6ef64SXu Yu if (dev->bar) 177897f6ef64SXu Yu iounmap(dev->bar); 177997f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 178097f6ef64SXu Yu if (!dev->bar) { 178197f6ef64SXu Yu dev->bar_mapped_size = 0; 178297f6ef64SXu Yu return -ENOMEM; 178397f6ef64SXu Yu } 178497f6ef64SXu Yu dev->bar_mapped_size = size; 178597f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 178697f6ef64SXu Yu 178797f6ef64SXu Yu return 0; 178897f6ef64SXu Yu } 178997f6ef64SXu Yu 179001ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 179157dacad5SJay Sternberg { 179257dacad5SJay Sternberg int result; 179357dacad5SJay Sternberg u32 aqa; 179457dacad5SJay Sternberg struct nvme_queue *nvmeq; 179557dacad5SJay Sternberg 179697f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 179797f6ef64SXu Yu if (result < 0) 179897f6ef64SXu Yu return result; 179997f6ef64SXu Yu 18008ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 180120d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 180257dacad5SJay Sternberg 18037a67cbeaSChristoph Hellwig if (dev->subsystem && 18047a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18057a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 180657dacad5SJay Sternberg 1807285b6e9bSChristoph Hellwig /* 1808285b6e9bSChristoph Hellwig * If the device has been passed off to us in an enabled state, just 1809285b6e9bSChristoph Hellwig * clear the enabled bit. The spec says we should set the 'shutdown 1810285b6e9bSChristoph Hellwig * notification bits', but doing so may cause the device to complete 1811285b6e9bSChristoph Hellwig * commands to the admin queue ... and we don't know what memory that 1812285b6e9bSChristoph Hellwig * might be pointing at! 1813285b6e9bSChristoph Hellwig */ 1814285b6e9bSChristoph Hellwig result = nvme_disable_ctrl(&dev->ctrl, false); 181557dacad5SJay Sternberg if (result < 0) 181657dacad5SJay Sternberg return result; 181757dacad5SJay Sternberg 1818a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1819147b27e4SSagi Grimberg if (result) 1820147b27e4SSagi Grimberg return result; 182157dacad5SJay Sternberg 1822635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1823635333e4SMax Gurtovoy 1824147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 182557dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 182657dacad5SJay Sternberg aqa |= aqa << 16; 182757dacad5SJay Sternberg 18287a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18297a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18307a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 183157dacad5SJay Sternberg 1832c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 183357dacad5SJay Sternberg if (result) 1834d4875622SKeith Busch return result; 183557dacad5SJay Sternberg 183657dacad5SJay Sternberg nvmeq->cq_vector = 0; 1837161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1838dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 183957dacad5SJay Sternberg if (result) { 18407c349ddeSKeith Busch dev->online_queues--; 1841d4875622SKeith Busch return result; 184257dacad5SJay Sternberg } 184357dacad5SJay Sternberg 18444e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 184557dacad5SJay Sternberg return result; 184657dacad5SJay Sternberg } 184757dacad5SJay Sternberg 1848749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 184957dacad5SJay Sternberg { 18504b04cc6aSJens Axboe unsigned i, max, rw_queues; 1851749941f2SChristoph Hellwig int ret = 0; 185257dacad5SJay Sternberg 1853d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1854a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1855749941f2SChristoph Hellwig ret = -ENOMEM; 185657dacad5SJay Sternberg break; 1857749941f2SChristoph Hellwig } 1858749941f2SChristoph Hellwig } 185957dacad5SJay Sternberg 1860d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1861e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1862e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1863e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18644b04cc6aSJens Axboe } else { 18654b04cc6aSJens Axboe rw_queues = max; 18664b04cc6aSJens Axboe } 18674b04cc6aSJens Axboe 1868949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18694b04cc6aSJens Axboe bool polled = i > rw_queues; 18704b04cc6aSJens Axboe 18714b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1872d4875622SKeith Busch if (ret) 187357dacad5SJay Sternberg break; 187457dacad5SJay Sternberg } 187557dacad5SJay Sternberg 1876749941f2SChristoph Hellwig /* 1877749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18788adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18798adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1880749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1881749941f2SChristoph Hellwig */ 1882749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 188357dacad5SJay Sternberg } 188457dacad5SJay Sternberg 188588de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 188657dacad5SJay Sternberg { 188788de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 188888de4598SChristoph Hellwig 188988de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 189088de4598SChristoph Hellwig } 189188de4598SChristoph Hellwig 189288de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 189388de4598SChristoph Hellwig { 189488de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 189588de4598SChristoph Hellwig } 189688de4598SChristoph Hellwig 1897f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 189857dacad5SJay Sternberg { 189988de4598SChristoph Hellwig u64 size, offset; 190057dacad5SJay Sternberg resource_size_t bar_size; 190157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19028969f1f8SChristoph Hellwig int bar; 190357dacad5SJay Sternberg 19049fe5c59fSKeith Busch if (dev->cmb_size) 19059fe5c59fSKeith Busch return; 19069fe5c59fSKeith Busch 190720d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 190820d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 190920d3bb92SKlaus Jensen 19107a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1911f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1912f65efd6dSChristoph Hellwig return; 1913202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 191457dacad5SJay Sternberg 191588de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 191688de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19178969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19188969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 191957dacad5SJay Sternberg 192057dacad5SJay Sternberg if (offset > bar_size) 1921f65efd6dSChristoph Hellwig return; 192257dacad5SJay Sternberg 192357dacad5SJay Sternberg /* 192420d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 192520d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 192620d3bb92SKlaus Jensen */ 192720d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 192820d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 192920d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 193020d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 193120d3bb92SKlaus Jensen } 193220d3bb92SKlaus Jensen 193320d3bb92SKlaus Jensen /* 193457dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 193557dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 193657dacad5SJay Sternberg * the reported size of the BAR 193757dacad5SJay Sternberg */ 193857dacad5SJay Sternberg if (size > bar_size - offset) 193957dacad5SJay Sternberg size = bar_size - offset; 194057dacad5SJay Sternberg 19410f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19420f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19430f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1944f65efd6dSChristoph Hellwig return; 19450f238ff5SLogan Gunthorpe } 19460f238ff5SLogan Gunthorpe 194757dacad5SJay Sternberg dev->cmb_size = size; 19480f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19490f238ff5SLogan Gunthorpe 19500f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19510f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19520f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 195357dacad5SJay Sternberg } 195457dacad5SJay Sternberg 195587ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 195657dacad5SJay Sternberg { 19576c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19584033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1959f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 196087ad72a5SChristoph Hellwig int ret; 196187ad72a5SChristoph Hellwig 196287ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 196387ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 196487ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19656c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 196687ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 196787ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 196887ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 196987ad72a5SChristoph Hellwig 197087ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 197187ad72a5SChristoph Hellwig if (ret) { 197287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 197387ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 197487ad72a5SChristoph Hellwig ret, bits); 1975a5df5e79SKeith Busch } else 1976a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1977a5df5e79SKeith Busch 197887ad72a5SChristoph Hellwig return ret; 197987ad72a5SChristoph Hellwig } 198087ad72a5SChristoph Hellwig 198187ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 198287ad72a5SChristoph Hellwig { 198387ad72a5SChristoph Hellwig int i; 198487ad72a5SChristoph Hellwig 198587ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 198687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19876c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 198887ad72a5SChristoph Hellwig 1989cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1990cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1991cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 199287ad72a5SChristoph Hellwig } 199387ad72a5SChristoph Hellwig 199487ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 199587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19964033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19974033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19984033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 199987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20007e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 200187ad72a5SChristoph Hellwig } 200287ad72a5SChristoph Hellwig 200392dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 200492dc6895SChristoph Hellwig u32 chunk_size) 200587ad72a5SChristoph Hellwig { 200687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 200792dc6895SChristoph Hellwig u32 max_entries, len; 20084033f35dSChristoph Hellwig dma_addr_t descs_dma; 20092ee0e4edSDan Carpenter int i = 0; 201087ad72a5SChristoph Hellwig void **bufs; 20116fbcde66SMinwoo Im u64 size, tmp; 201287ad72a5SChristoph Hellwig 201387ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 201487ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 201587ad72a5SChristoph Hellwig max_entries = tmp; 2016044a9df1SChristoph Hellwig 2017044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2018044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2019044a9df1SChristoph Hellwig 2020750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20214033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 202287ad72a5SChristoph Hellwig if (!descs) 202387ad72a5SChristoph Hellwig goto out; 202487ad72a5SChristoph Hellwig 202587ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 202687ad72a5SChristoph Hellwig if (!bufs) 202787ad72a5SChristoph Hellwig goto out_free_descs; 202887ad72a5SChristoph Hellwig 2029244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 203087ad72a5SChristoph Hellwig dma_addr_t dma_addr; 203187ad72a5SChristoph Hellwig 203250cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 203387ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 203487ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 203587ad72a5SChristoph Hellwig if (!bufs[i]) 203687ad72a5SChristoph Hellwig break; 203787ad72a5SChristoph Hellwig 203887ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20396c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 204087ad72a5SChristoph Hellwig i++; 204187ad72a5SChristoph Hellwig } 204287ad72a5SChristoph Hellwig 204392dc6895SChristoph Hellwig if (!size) 204487ad72a5SChristoph Hellwig goto out_free_bufs; 204587ad72a5SChristoph Hellwig 204687ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 204787ad72a5SChristoph Hellwig dev->host_mem_size = size; 204887ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20494033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 205087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 205187ad72a5SChristoph Hellwig return 0; 205287ad72a5SChristoph Hellwig 205387ad72a5SChristoph Hellwig out_free_bufs: 205487ad72a5SChristoph Hellwig while (--i >= 0) { 20556c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 205687ad72a5SChristoph Hellwig 2057cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2058cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2059cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 206087ad72a5SChristoph Hellwig } 206187ad72a5SChristoph Hellwig 206287ad72a5SChristoph Hellwig kfree(bufs); 206387ad72a5SChristoph Hellwig out_free_descs: 20644033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20654033f35dSChristoph Hellwig descs_dma); 206687ad72a5SChristoph Hellwig out: 206787ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 206887ad72a5SChristoph Hellwig return -ENOMEM; 206987ad72a5SChristoph Hellwig } 207087ad72a5SChristoph Hellwig 207192dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 207292dc6895SChristoph Hellwig { 20739dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20749dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20759dc54a0dSChaitanya Kulkarni u64 chunk_size; 207692dc6895SChristoph Hellwig 207792dc6895SChristoph Hellwig /* start big and work our way down */ 20789dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 207992dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 208092dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 208192dc6895SChristoph Hellwig return 0; 208292dc6895SChristoph Hellwig nvme_free_host_mem(dev); 208392dc6895SChristoph Hellwig } 208492dc6895SChristoph Hellwig } 208592dc6895SChristoph Hellwig 208692dc6895SChristoph Hellwig return -ENOMEM; 208792dc6895SChristoph Hellwig } 208892dc6895SChristoph Hellwig 20899620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 209087ad72a5SChristoph Hellwig { 209187ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 209287ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 209387ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 209487ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20956fbcde66SMinwoo Im int ret; 209687ad72a5SChristoph Hellwig 2097acb71e53SChristoph Hellwig if (!dev->ctrl.hmpre) 2098acb71e53SChristoph Hellwig return 0; 2099acb71e53SChristoph Hellwig 210087ad72a5SChristoph Hellwig preferred = min(preferred, max); 210187ad72a5SChristoph Hellwig if (min > max) { 210287ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 210387ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 210487ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 210587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21069620cfbaSChristoph Hellwig return 0; 210787ad72a5SChristoph Hellwig } 210887ad72a5SChristoph Hellwig 210987ad72a5SChristoph Hellwig /* 211087ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 211187ad72a5SChristoph Hellwig */ 211287ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 211387ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 211487ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 211587ad72a5SChristoph Hellwig else 211687ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 211787ad72a5SChristoph Hellwig } 211887ad72a5SChristoph Hellwig 211987ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 212092dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 212192dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 212292dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21239620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 212487ad72a5SChristoph Hellwig } 212587ad72a5SChristoph Hellwig 212692dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 212792dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 212892dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 212992dc6895SChristoph Hellwig } 213092dc6895SChristoph Hellwig 21319620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21329620cfbaSChristoph Hellwig if (ret) 213387ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21349620cfbaSChristoph Hellwig return ret; 213557dacad5SJay Sternberg } 213657dacad5SJay Sternberg 21370521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21380521905eSKeith Busch char *buf) 21390521905eSKeith Busch { 21400521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21410521905eSKeith Busch 21420521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21430521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21440521905eSKeith Busch } 21450521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21460521905eSKeith Busch 21471751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21481751e97aSKeith Busch char *buf) 21491751e97aSKeith Busch { 21501751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21511751e97aSKeith Busch 21521751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21531751e97aSKeith Busch } 21541751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21551751e97aSKeith Busch 21561751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21571751e97aSKeith Busch char *buf) 21581751e97aSKeith Busch { 21591751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21601751e97aSKeith Busch 21611751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21621751e97aSKeith Busch } 21631751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21641751e97aSKeith Busch 2165a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2166a5df5e79SKeith Busch char *buf) 2167a5df5e79SKeith Busch { 2168a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2169a5df5e79SKeith Busch 2170a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2171a5df5e79SKeith Busch } 2172a5df5e79SKeith Busch 2173a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2174a5df5e79SKeith Busch const char *buf, size_t count) 2175a5df5e79SKeith Busch { 2176a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2177a5df5e79SKeith Busch bool new; 2178a5df5e79SKeith Busch int ret; 2179a5df5e79SKeith Busch 218099722c8aSChristophe JAILLET if (kstrtobool(buf, &new) < 0) 2181a5df5e79SKeith Busch return -EINVAL; 2182a5df5e79SKeith Busch 2183a5df5e79SKeith Busch if (new == ndev->hmb) 2184a5df5e79SKeith Busch return count; 2185a5df5e79SKeith Busch 2186a5df5e79SKeith Busch if (new) { 2187a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2188a5df5e79SKeith Busch } else { 2189a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2190a5df5e79SKeith Busch if (!ret) 2191a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2192a5df5e79SKeith Busch } 2193a5df5e79SKeith Busch 2194a5df5e79SKeith Busch if (ret < 0) 2195a5df5e79SKeith Busch return ret; 2196a5df5e79SKeith Busch 2197a5df5e79SKeith Busch return count; 2198a5df5e79SKeith Busch } 2199a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2200a5df5e79SKeith Busch 22010521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22020521905eSKeith Busch struct attribute *a, int n) 22030521905eSKeith Busch { 22040521905eSKeith Busch struct nvme_ctrl *ctrl = 22050521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22060521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22070521905eSKeith Busch 22081751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22091751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22101751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22111751e97aSKeith Busch if (!dev->cmbsz) 22120521905eSKeith Busch return 0; 22131751e97aSKeith Busch } 2214a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2215a5df5e79SKeith Busch return 0; 2216a5df5e79SKeith Busch 22170521905eSKeith Busch return a->mode; 22180521905eSKeith Busch } 22190521905eSKeith Busch 22200521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22210521905eSKeith Busch &dev_attr_cmb.attr, 22221751e97aSKeith Busch &dev_attr_cmbloc.attr, 22231751e97aSKeith Busch &dev_attr_cmbsz.attr, 2224a5df5e79SKeith Busch &dev_attr_hmb.attr, 22250521905eSKeith Busch NULL, 22260521905eSKeith Busch }; 22270521905eSKeith Busch 222886adbf0cSChristoph Hellwig static const struct attribute_group nvme_pci_dev_attrs_group = { 22290521905eSKeith Busch .attrs = nvme_pci_attrs, 22300521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22310521905eSKeith Busch }; 22320521905eSKeith Busch 223386adbf0cSChristoph Hellwig static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 223486adbf0cSChristoph Hellwig &nvme_dev_attrs_group, 223586adbf0cSChristoph Hellwig &nvme_pci_dev_attrs_group, 223686adbf0cSChristoph Hellwig NULL, 223786adbf0cSChristoph Hellwig }; 223886adbf0cSChristoph Hellwig 2239612b7286SMing Lei /* 2240612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2241612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2242612b7286SMing Lei */ 2243612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22443b6592f7SJens Axboe { 2245612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22462a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2247c45b1fa2SMing Lei 22483b6592f7SJens Axboe /* 2249ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2250612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2251612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2252612b7286SMing Lei * 2253612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2254612b7286SMing Lei * write and read queues. 2255612b7286SMing Lei * 2256612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2257612b7286SMing Lei * queue. 22583b6592f7SJens Axboe */ 2259612b7286SMing Lei if (!nrirqs) { 2260612b7286SMing Lei nrirqs = 1; 2261612b7286SMing Lei nr_read_queues = 0; 22622a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2263612b7286SMing Lei nr_read_queues = 0; 22642a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2265612b7286SMing Lei nr_read_queues = 1; 22663b6592f7SJens Axboe } else { 22672a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22683b6592f7SJens Axboe } 2269612b7286SMing Lei 2270612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2271612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2272612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2273612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2274612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22753b6592f7SJens Axboe } 22763b6592f7SJens Axboe 22776451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22783b6592f7SJens Axboe { 22793b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22803b6592f7SJens Axboe struct irq_affinity affd = { 22813b6592f7SJens Axboe .pre_vectors = 1, 2282612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2283612b7286SMing Lei .priv = dev, 22843b6592f7SJens Axboe }; 228521cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22866451fe73SJens Axboe 22876451fe73SJens Axboe /* 228821cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 228921cc2f3fSJeffle Xu * left over for non-polled I/O. 22906451fe73SJens Axboe */ 229121cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 229221cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22933b6592f7SJens Axboe 229421cc2f3fSJeffle Xu /* 229521cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 229621cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 229721cc2f3fSJeffle Xu */ 2298612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2299612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23003b6592f7SJens Axboe 230166341331SBenjamin Herrenschmidt /* 230221cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 230321cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 230421cc2f3fSJeffle Xu * vector. 230566341331SBenjamin Herrenschmidt */ 230666341331SBenjamin Herrenschmidt irq_queues = 1; 230721cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 230821cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2309612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23103b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23113b6592f7SJens Axboe } 23123b6592f7SJens Axboe 23132a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23142a5bcfddSWeiping Zhang { 2315e3aef095SNiklas Schnelle /* 2316e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2317e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2318e3aef095SNiklas Schnelle */ 2319e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2320e3aef095SNiklas Schnelle return 1; 23212a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23222a5bcfddSWeiping Zhang } 23232a5bcfddSWeiping Zhang 232457dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 232557dacad5SJay Sternberg { 2326147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 232757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23282a5bcfddSWeiping Zhang unsigned int nr_io_queues; 232997f6ef64SXu Yu unsigned long size; 23302a5bcfddSWeiping Zhang int result; 233157dacad5SJay Sternberg 23322a5bcfddSWeiping Zhang /* 23332a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23342a5bcfddSWeiping Zhang * stable values to work with. 23352a5bcfddSWeiping Zhang */ 23362a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23372a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2338d38e9f04SBenjamin Herrenschmidt 2339ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23409a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23419a0be7abSChristoph Hellwig if (result < 0) 234257dacad5SJay Sternberg return result; 23439a0be7abSChristoph Hellwig 2344f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2345a5229050SKeith Busch return 0; 234657dacad5SJay Sternberg 2347e4b9852aSCasey Chen /* 2348e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2349e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2350e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2351e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2352e4b9852aSCasey Chen * nvme_dev_disable() path. 2353e4b9852aSCasey Chen */ 2354e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2355e4b9852aSCasey Chen if (result) 2356e4b9852aSCasey Chen return result; 2357e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2358e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23594e224106SChristoph Hellwig 23600f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 236157dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 236257dacad5SJay Sternberg sizeof(struct nvme_command)); 236357dacad5SJay Sternberg if (result > 0) 236457dacad5SJay Sternberg dev->q_depth = result; 236557dacad5SJay Sternberg else 23660f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 236757dacad5SJay Sternberg } 236857dacad5SJay Sternberg 236957dacad5SJay Sternberg do { 237097f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 237197f6ef64SXu Yu result = nvme_remap_bar(dev, size); 237297f6ef64SXu Yu if (!result) 237357dacad5SJay Sternberg break; 2374e4b9852aSCasey Chen if (!--nr_io_queues) { 2375e4b9852aSCasey Chen result = -ENOMEM; 2376e4b9852aSCasey Chen goto out_unlock; 2377e4b9852aSCasey Chen } 237857dacad5SJay Sternberg } while (1); 237957dacad5SJay Sternberg adminq->q_db = dev->dbs; 238057dacad5SJay Sternberg 23818fae268bSKeith Busch retry: 238257dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2383e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23840ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 238557dacad5SJay Sternberg 238657dacad5SJay Sternberg /* 238757dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 238857dacad5SJay Sternberg * setting up the full range we need. 238957dacad5SJay Sternberg */ 2390dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 23913b6592f7SJens Axboe 23923b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2393e4b9852aSCasey Chen if (result <= 0) { 2394e4b9852aSCasey Chen result = -EIO; 2395e4b9852aSCasey Chen goto out_unlock; 2396e4b9852aSCasey Chen } 23973b6592f7SJens Axboe 239822b55601SKeith Busch dev->num_vecs = result; 23994b04cc6aSJens Axboe result = max(result - 1, 1); 2400e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 240157dacad5SJay Sternberg 240257dacad5SJay Sternberg /* 240357dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 240457dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 240557dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 240657dacad5SJay Sternberg * number of interrupts. 240757dacad5SJay Sternberg */ 2408dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24097c349ddeSKeith Busch if (result) 2410e4b9852aSCasey Chen goto out_unlock; 24114e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2412e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24138fae268bSKeith Busch 24148fae268bSKeith Busch result = nvme_create_io_queues(dev); 24158fae268bSKeith Busch if (result || dev->online_queues < 2) 24168fae268bSKeith Busch return result; 24178fae268bSKeith Busch 24188fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24198fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 2420*7d879c90SChristoph Hellwig nvme_delete_io_queues(dev); 2421e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2422e4b9852aSCasey Chen if (result) 2423e4b9852aSCasey Chen return result; 24248fae268bSKeith Busch nvme_suspend_io_queues(dev); 24258fae268bSKeith Busch goto retry; 24268fae268bSKeith Busch } 24278fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24288fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24298fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24308fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24318fae268bSKeith Busch return 0; 2432e4b9852aSCasey Chen out_unlock: 2433e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2434e4b9852aSCasey Chen return result; 243557dacad5SJay Sternberg } 243657dacad5SJay Sternberg 2437de671d61SJens Axboe static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2438de671d61SJens Axboe blk_status_t error) 2439db3cbfffSKeith Busch { 2440db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2441db3cbfffSKeith Busch 2442db3cbfffSKeith Busch blk_mq_free_request(req); 2443d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2444de671d61SJens Axboe return RQ_END_IO_NONE; 2445db3cbfffSKeith Busch } 2446db3cbfffSKeith Busch 2447de671d61SJens Axboe static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2448de671d61SJens Axboe blk_status_t error) 2449db3cbfffSKeith Busch { 2450db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2451db3cbfffSKeith Busch 2452d1ed6aa1SChristoph Hellwig if (error) 2453d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2454db3cbfffSKeith Busch 2455de671d61SJens Axboe return nvme_del_queue_end(req, error); 2456db3cbfffSKeith Busch } 2457db3cbfffSKeith Busch 2458db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2459db3cbfffSKeith Busch { 2460db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2461db3cbfffSKeith Busch struct request *req; 2462f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2463db3cbfffSKeith Busch 2464db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2465db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2466db3cbfffSKeith Busch 2467e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2468db3cbfffSKeith Busch if (IS_ERR(req)) 2469db3cbfffSKeith Busch return PTR_ERR(req); 2470e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2471db3cbfffSKeith Busch 2472e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2473e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2474e2e53086SChristoph Hellwig else 2475e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2476db3cbfffSKeith Busch req->end_io_data = nvmeq; 2477db3cbfffSKeith Busch 2478d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2479128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2480e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2481db3cbfffSKeith Busch return 0; 2482db3cbfffSKeith Busch } 2483db3cbfffSKeith Busch 2484*7d879c90SChristoph Hellwig static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode) 2485db3cbfffSKeith Busch { 24865271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2487db3cbfffSKeith Busch unsigned long timeout; 2488db3cbfffSKeith Busch 2489db3cbfffSKeith Busch retry: 2490dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24915271edd4SChristoph Hellwig while (nr_queues > 0) { 24925271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2493db3cbfffSKeith Busch break; 24945271edd4SChristoph Hellwig nr_queues--; 24955271edd4SChristoph Hellwig sent++; 24965271edd4SChristoph Hellwig } 2497d1ed6aa1SChristoph Hellwig while (sent) { 2498d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2499d1ed6aa1SChristoph Hellwig 2500d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25015271edd4SChristoph Hellwig timeout); 2502db3cbfffSKeith Busch if (timeout == 0) 25035271edd4SChristoph Hellwig return false; 2504d1ed6aa1SChristoph Hellwig 2505d1ed6aa1SChristoph Hellwig sent--; 25065271edd4SChristoph Hellwig if (nr_queues) 2507db3cbfffSKeith Busch goto retry; 2508db3cbfffSKeith Busch } 25095271edd4SChristoph Hellwig return true; 2510db3cbfffSKeith Busch } 2511db3cbfffSKeith Busch 2512*7d879c90SChristoph Hellwig static void nvme_delete_io_queues(struct nvme_dev *dev) 2513*7d879c90SChristoph Hellwig { 2514*7d879c90SChristoph Hellwig if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq)) 2515*7d879c90SChristoph Hellwig __nvme_delete_io_queues(dev, nvme_admin_delete_cq); 2516*7d879c90SChristoph Hellwig } 2517*7d879c90SChristoph Hellwig 25182455a4b7SChristoph Hellwig static void nvme_pci_alloc_tag_set(struct nvme_dev *dev) 251957dacad5SJay Sternberg { 25202455a4b7SChristoph Hellwig struct blk_mq_tag_set * set = &dev->tagset; 25212b1b7e78SJianchao Wang int ret; 25222b1b7e78SJianchao Wang 25232455a4b7SChristoph Hellwig set->ops = &nvme_mq_ops; 25242455a4b7SChristoph Hellwig set->nr_hw_queues = dev->online_queues - 1; 25256ee742faSKeith Busch set->nr_maps = 1; 25266ee742faSKeith Busch if (dev->io_queues[HCTX_TYPE_READ]) 25276ee742faSKeith Busch set->nr_maps = 2; 2528ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 25296ee742faSKeith Busch set->nr_maps = 3; 25302455a4b7SChristoph Hellwig set->timeout = NVME_IO_TIMEOUT; 25312455a4b7SChristoph Hellwig set->numa_node = dev->ctrl.numa_node; 25322455a4b7SChristoph Hellwig set->queue_depth = min_t(unsigned, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1; 25332455a4b7SChristoph Hellwig set->cmd_size = sizeof(struct nvme_iod); 25342455a4b7SChristoph Hellwig set->flags = BLK_MQ_F_SHOULD_MERGE; 25352455a4b7SChristoph Hellwig set->driver_data = dev; 253657dacad5SJay Sternberg 2537d38e9f04SBenjamin Herrenschmidt /* 2538d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2539d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2540d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2541d38e9f04SBenjamin Herrenschmidt */ 2542d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 25432455a4b7SChristoph Hellwig set->reserved_tags = NVME_AQ_DEPTH; 2544d38e9f04SBenjamin Herrenschmidt 25452455a4b7SChristoph Hellwig ret = blk_mq_alloc_tag_set(set); 25462b1b7e78SJianchao Wang if (ret) { 25472b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25482b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25495d02a5c1SKeith Busch return; 25502b1b7e78SJianchao Wang } 25512455a4b7SChristoph Hellwig dev->ctrl.tagset = set; 255257dacad5SJay Sternberg } 2553949928c1SKeith Busch 25542455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 25552455a4b7SChristoph Hellwig { 25562455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 25572455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 25582455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 255957dacad5SJay Sternberg } 256057dacad5SJay Sternberg 2561b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 256257dacad5SJay Sternberg { 2563b00a726aSKeith Busch int result = -ENOMEM; 256457dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25654bdf2603SFilippo Sironi int dma_address_bits = 64; 256657dacad5SJay Sternberg 256757dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 256857dacad5SJay Sternberg return result; 256957dacad5SJay Sternberg 257057dacad5SJay Sternberg pci_set_master(pdev); 257157dacad5SJay Sternberg 25724bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25734bdf2603SFilippo Sironi dma_address_bits = 48; 25744bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 257557dacad5SJay Sternberg goto disable; 257657dacad5SJay Sternberg 25777a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 257857dacad5SJay Sternberg result = -ENODEV; 2579b00a726aSKeith Busch goto disable; 258057dacad5SJay Sternberg } 258157dacad5SJay Sternberg 258257dacad5SJay Sternberg /* 2583a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2584a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2585a5229050SKeith Busch * adjust this later. 258657dacad5SJay Sternberg */ 2587dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2588dca51e78SChristoph Hellwig if (result < 0) 2589dca51e78SChristoph Hellwig return result; 259057dacad5SJay Sternberg 259120d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25927a67cbeaSChristoph Hellwig 25937442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2594b27c1e68Sweiping zhang io_queue_depth); 2595aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 259620d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 25977a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 25981f390c1fSStephan Günther 25991f390c1fSStephan Günther /* 260066341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260166341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 260266341331SBenjamin Herrenschmidt * so we don't bother updating it here. 260366341331SBenjamin Herrenschmidt */ 260466341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 260566341331SBenjamin Herrenschmidt dev->io_sqes = 7; 260666341331SBenjamin Herrenschmidt else 2607c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26081f390c1fSStephan Günther 26091f390c1fSStephan Günther /* 26101f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26111f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26121f390c1fSStephan Günther */ 26131f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26141f390c1fSStephan Günther dev->q_depth = 2; 26159bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26169bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26171f390c1fSStephan Günther dev->q_depth); 2618d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2619d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262020d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2621d554b5e1SMartin K. Petersen dev->q_depth = 64; 2622d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2623d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26241f390c1fSStephan Günther } 26251f390c1fSStephan Günther 2626d38e9f04SBenjamin Herrenschmidt /* 2627d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2628d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2629d38e9f04SBenjamin Herrenschmidt */ 2630d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2631d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2632d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2633d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2634d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2635d38e9f04SBenjamin Herrenschmidt } 2636d38e9f04SBenjamin Herrenschmidt 2637d38e9f04SBenjamin Herrenschmidt 2638f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2639202021c1SStephen Bates 2640a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2641a0a3408eSKeith Busch pci_save_state(pdev); 2642a6ee7f19SChristoph Hellwig 2643a6ee7f19SChristoph Hellwig return nvme_pci_configure_admin_queue(dev); 264457dacad5SJay Sternberg 264557dacad5SJay Sternberg disable: 264657dacad5SJay Sternberg pci_disable_device(pdev); 264757dacad5SJay Sternberg return result; 264857dacad5SJay Sternberg } 264957dacad5SJay Sternberg 265057dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265157dacad5SJay Sternberg { 2652b00a726aSKeith Busch if (dev->bar) 2653b00a726aSKeith Busch iounmap(dev->bar); 2654a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2655b00a726aSKeith Busch } 2656b00a726aSKeith Busch 2657a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 265857dacad5SJay Sternberg { 2659e43269e6SKeith Busch bool dead = true, freeze = false; 2660302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 266157dacad5SJay Sternberg 266277bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2663081f5e75SKeith Busch if (pci_is_enabled(pdev)) { 2664081f5e75SKeith Busch u32 csts; 2665081f5e75SKeith Busch 2666081f5e75SKeith Busch if (pci_device_is_present(pdev)) 2667081f5e75SKeith Busch csts = readl(dev->bar + NVME_REG_CSTS); 2668081f5e75SKeith Busch else 2669081f5e75SKeith Busch csts = ~0; 2670302ad8ccSKeith Busch 2671ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2672e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2673e43269e6SKeith Busch freeze = true; 2674302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2675e43269e6SKeith Busch } 2676302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2677302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 267857dacad5SJay Sternberg } 2679c21377f8SGabriel Krisman Bertazi 2680302ad8ccSKeith Busch /* 2681302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2682302ad8ccSKeith Busch * doing a safe shutdown. 2683302ad8ccSKeith Busch */ 2684e43269e6SKeith Busch if (!dead && shutdown && freeze) 2685302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 268687ad72a5SChristoph Hellwig 26879f27bd70SChristoph Hellwig nvme_quiesce_io_queues(&dev->ctrl); 26889a915a5bSJianchao Wang 268964ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 2690*7d879c90SChristoph Hellwig nvme_delete_io_queues(dev); 269147d42d22SChristoph Hellwig nvme_disable_ctrl(&dev->ctrl, shutdown); 269247d42d22SChristoph Hellwig nvme_poll_irqdisable(&dev->queues[0]); 269357dacad5SJay Sternberg } 26948fae268bSKeith Busch nvme_suspend_io_queues(dev); 269510981f23SChristoph Hellwig nvme_suspend_queue(dev, 0); 2696c80767f7SChristoph Hellwig pci_free_irq_vectors(pdev); 2697c80767f7SChristoph Hellwig if (pci_is_enabled(pdev)) { 2698c80767f7SChristoph Hellwig pci_disable_pcie_error_reporting(pdev); 2699c80767f7SChristoph Hellwig pci_disable_device(pdev); 2700c80767f7SChristoph Hellwig } 2701fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 270257dacad5SJay Sternberg 27031fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 27041fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2705302ad8ccSKeith Busch 2706302ad8ccSKeith Busch /* 2707302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2708302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2709302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2710302ad8ccSKeith Busch */ 2711c8e9e9b7SKeith Busch if (shutdown) { 27129f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2713c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27149f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 2715c8e9e9b7SKeith Busch } 271677bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 271757dacad5SJay Sternberg } 271857dacad5SJay Sternberg 2719c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2720c1ac9a4bSKeith Busch { 2721c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2722c1ac9a4bSKeith Busch return -EBUSY; 2723c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2724c1ac9a4bSKeith Busch return 0; 2725c1ac9a4bSKeith Busch } 2726c1ac9a4bSKeith Busch 272757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 272857dacad5SJay Sternberg { 272957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2730c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2731c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 273257dacad5SJay Sternberg if (!dev->prp_page_pool) 273357dacad5SJay Sternberg return -ENOMEM; 273457dacad5SJay Sternberg 273557dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 273657dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 273757dacad5SJay Sternberg 256, 256, 0); 273857dacad5SJay Sternberg if (!dev->prp_small_pool) { 273957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 274057dacad5SJay Sternberg return -ENOMEM; 274157dacad5SJay Sternberg } 274257dacad5SJay Sternberg return 0; 274357dacad5SJay Sternberg } 274457dacad5SJay Sternberg 274557dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 274657dacad5SJay Sternberg { 274757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 274857dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 274957dacad5SJay Sternberg } 275057dacad5SJay Sternberg 2751081a7d95SChristoph Hellwig static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2752081a7d95SChristoph Hellwig { 2753081a7d95SChristoph Hellwig size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 2754081a7d95SChristoph Hellwig size_t alloc_size = sizeof(__le64 *) * npages + 2755081a7d95SChristoph Hellwig sizeof(struct scatterlist) * NVME_MAX_SEGS; 2756081a7d95SChristoph Hellwig 2757081a7d95SChristoph Hellwig WARN_ON_ONCE(alloc_size > PAGE_SIZE); 2758081a7d95SChristoph Hellwig dev->iod_mempool = mempool_create_node(1, 2759081a7d95SChristoph Hellwig mempool_kmalloc, mempool_kfree, 2760081a7d95SChristoph Hellwig (void *)alloc_size, GFP_KERNEL, 2761081a7d95SChristoph Hellwig dev_to_node(dev->dev)); 2762081a7d95SChristoph Hellwig if (!dev->iod_mempool) 2763081a7d95SChristoph Hellwig return -ENOMEM; 2764081a7d95SChristoph Hellwig return 0; 2765081a7d95SChristoph Hellwig } 2766081a7d95SChristoph Hellwig 2767770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2768770597ecSKeith Busch { 2769770597ecSKeith Busch if (dev->tagset.tags) 2770770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2771770597ecSKeith Busch dev->ctrl.tagset = NULL; 2772770597ecSKeith Busch } 2773770597ecSKeith Busch 27742e87570bSChristoph Hellwig /* pairs with nvme_pci_alloc_dev */ 27751673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 277657dacad5SJay Sternberg { 27771673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 277857dacad5SJay Sternberg 2779770597ecSKeith Busch nvme_free_tagset(dev); 2780253fd4acSIsrael Rukshin put_device(dev->dev); 2781253fd4acSIsrael Rukshin kfree(dev->queues); 278257dacad5SJay Sternberg kfree(dev); 278357dacad5SJay Sternberg } 278457dacad5SJay Sternberg 2785fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 278657dacad5SJay Sternberg { 2787d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2788d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2789a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2790e71afda4SChaitanya Kulkarni int result; 279157dacad5SJay Sternberg 27927764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 27937764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 27947764656bSZhihao Cheng dev->ctrl.state); 2795e71afda4SChaitanya Kulkarni result = -ENODEV; 2796fd634f41SChristoph Hellwig goto out; 2797e71afda4SChaitanya Kulkarni } 2798fd634f41SChristoph Hellwig 2799fd634f41SChristoph Hellwig /* 2800fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2801fd634f41SChristoph Hellwig * moving on. 2802fd634f41SChristoph Hellwig */ 2803b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2804a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2805d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2806fd634f41SChristoph Hellwig 28075c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2808b00a726aSKeith Busch result = nvme_pci_enable(dev); 280957dacad5SJay Sternberg if (result) 28104726bcf3SKeith Busch goto out_unlock; 28119f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 28125c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28135c959d73SKeith Busch 28145c959d73SKeith Busch /* 28155c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28165c959d73SKeith Busch * initializing procedure here. 28175c959d73SKeith Busch */ 28185c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28195c959d73SKeith Busch dev_warn(dev->ctrl.device, 28205c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2821cee6c269SMinwoo Im result = -EBUSY; 28225c959d73SKeith Busch goto out; 28235c959d73SKeith Busch } 2824943e942eSJens Axboe 282594cc781fSChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2826ce4541f4SChristoph Hellwig if (result) 2827f58944e2SKeith Busch goto out; 2828ce4541f4SChristoph Hellwig 282965a54646SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 2830f9f38e33SHelen Koike 28319620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28329620cfbaSChristoph Hellwig if (result < 0) 28339620cfbaSChristoph Hellwig goto out; 283487ad72a5SChristoph Hellwig 283557dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 283657dacad5SJay Sternberg if (result) 2837f58944e2SKeith Busch goto out; 283857dacad5SJay Sternberg 283921f033f7SKeith Busch /* 28400ffc7e98SChristoph Hellwig * Freeze and update the number of I/O queues as thos might have 2841eac3ef26SChristoph Hellwig * changed. If there are no I/O queues left after this reset, keep the 2842eac3ef26SChristoph Hellwig * controller around but remove all namespaces. 284357dacad5SJay Sternberg */ 28440ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 28459f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2846302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 28472455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 28482455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2849302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 28500ffc7e98SChristoph Hellwig } else { 28510ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues lost\n"); 2852cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 28539f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 28540ffc7e98SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 28550ffc7e98SChristoph Hellwig nvme_free_tagset(dev); 28560ffc7e98SChristoph Hellwig } 285757dacad5SJay Sternberg 28582b1b7e78SJianchao Wang /* 28592b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 28602b1b7e78SJianchao Wang * recovery. 28612b1b7e78SJianchao Wang */ 28625d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 28632b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 28645d02a5c1SKeith Busch "failed to mark controller live state\n"); 2865e71afda4SChaitanya Kulkarni result = -ENODEV; 2866bb8d261eSChristoph Hellwig goto out; 2867bb8d261eSChristoph Hellwig } 286892911a55SChristoph Hellwig 2869d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 287057dacad5SJay Sternberg return; 287157dacad5SJay Sternberg 28724726bcf3SKeith Busch out_unlock: 28734726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 287457dacad5SJay Sternberg out: 2875c7c16c5bSChristoph Hellwig /* 2876c7c16c5bSChristoph Hellwig * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2877c7c16c5bSChristoph Hellwig * may be holding this pci_dev's device lock. 2878c7c16c5bSChristoph Hellwig */ 2879c7c16c5bSChristoph Hellwig dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2880c7c16c5bSChristoph Hellwig result); 2881c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2882c7c16c5bSChristoph Hellwig nvme_dev_disable(dev, true); 2883c7c16c5bSChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 2884c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 288557dacad5SJay Sternberg } 288657dacad5SJay Sternberg 28871c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 288857dacad5SJay Sternberg { 28891c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 28901c63dc66SChristoph Hellwig return 0; 289157dacad5SJay Sternberg } 28921c63dc66SChristoph Hellwig 28935fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 28945fd4ce1bSChristoph Hellwig { 28955fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 28965fd4ce1bSChristoph Hellwig return 0; 28975fd4ce1bSChristoph Hellwig } 28985fd4ce1bSChristoph Hellwig 28997fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29007fd8930fSChristoph Hellwig { 29013a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29027fd8930fSChristoph Hellwig return 0; 29037fd8930fSChristoph Hellwig } 29047fd8930fSChristoph Hellwig 290597c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 290697c12223SKeith Busch { 290797c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 290897c12223SKeith Busch 29092db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 291097c12223SKeith Busch } 291197c12223SKeith Busch 29122f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 29132f0dad17SKeith Busch { 29142f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 29152f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 29162f0dad17SKeith Busch 29172f0dad17SKeith Busch dev_err(ctrl->device, 29182f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 29192f0dad17SKeith Busch pdev->vendor, pdev->device, 29202f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 29212f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 29222f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 29232f0dad17SKeith Busch subsys->firmware_rev); 29242f0dad17SKeith Busch } 29252f0dad17SKeith Busch 29262f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 29272f859441SLogan Gunthorpe { 29282f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 29292f859441SLogan Gunthorpe 29302f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 29312f859441SLogan Gunthorpe } 29322f859441SLogan Gunthorpe 29331c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29341a353d85SMing Lin .name = "pcie", 2935e439bb12SSagi Grimberg .module = THIS_MODULE, 29362f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 293786adbf0cSChristoph Hellwig .dev_attr_groups = nvme_pci_dev_attr_groups, 29381c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29395fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29407fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29411673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2942f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 294397c12223SKeith Busch .get_address = nvme_pci_get_address, 29442f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 29452f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 29461c63dc66SChristoph Hellwig }; 294757dacad5SJay Sternberg 2948b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2949b00a726aSKeith Busch { 2950b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2951b00a726aSKeith Busch 2952a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2953b00a726aSKeith Busch return -ENODEV; 2954b00a726aSKeith Busch 295597f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2956b00a726aSKeith Busch goto release; 2957b00a726aSKeith Busch 2958b00a726aSKeith Busch return 0; 2959b00a726aSKeith Busch release: 2960a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2961b00a726aSKeith Busch return -ENODEV; 2962b00a726aSKeith Busch } 2963b00a726aSKeith Busch 29648427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2965ff5350a8SAndy Lutomirski { 2966ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2967ff5350a8SAndy Lutomirski /* 2968ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2969ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2970ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2971ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2972ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2973ff5350a8SAndy Lutomirski * laptops. 2974ff5350a8SAndy Lutomirski */ 2975ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2976ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2977ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2978ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 29798427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 29808427bbc2SKai-Heng Feng /* 29818427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2982467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2983467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2984467c77d4SJarosław Janik * ASUS PRIME Z370-A 29858427bbc2SKai-Heng Feng */ 29868427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2987467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2988467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 29898427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 29901fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 29911fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 29921fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 29931fae37acSShyjumon N /* 29941fae37acSShyjumon N * Forcing to use host managed nvme power settings for 29951fae37acSShyjumon N * lowest idle power with quick resume latency on 29961fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 29971fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 29981fae37acSShyjumon N */ 29991fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30001fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30011fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3002ff5350a8SAndy Lutomirski } 3003ff5350a8SAndy Lutomirski 3004ff5350a8SAndy Lutomirski return 0; 3005ff5350a8SAndy Lutomirski } 3006ff5350a8SAndy Lutomirski 30072e87570bSChristoph Hellwig static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 30082e87570bSChristoph Hellwig const struct pci_device_id *id) 300957dacad5SJay Sternberg { 3010ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 30112e87570bSChristoph Hellwig int node = dev_to_node(&pdev->dev); 30122e87570bSChristoph Hellwig struct nvme_dev *dev; 30132e87570bSChristoph Hellwig int ret = -ENOMEM; 301457dacad5SJay Sternberg 301557dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30162fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 301757dacad5SJay Sternberg 301857dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 301957dacad5SJay Sternberg if (!dev) 30202e87570bSChristoph Hellwig return NULL; 30212e87570bSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30222e87570bSChristoph Hellwig mutex_init(&dev->shutdown_lock); 3023147b27e4SSagi Grimberg 30242a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30252a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 30262a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 30272a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30282a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 302957dacad5SJay Sternberg if (!dev->queues) 30302e87570bSChristoph Hellwig goto out_free_dev; 303157dacad5SJay Sternberg 303257dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 3033f3ca80fcSChristoph Hellwig 30348427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 30352744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3036df4f9bc4SDavid E. Box /* 3037df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3038df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3039df4f9bc4SDavid E. Box */ 3040df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3041df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3042df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3043df4f9bc4SDavid E. Box } 30442e87570bSChristoph Hellwig ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 30452e87570bSChristoph Hellwig quirks); 30462e87570bSChristoph Hellwig if (ret) 30472e87570bSChristoph Hellwig goto out_put_device; 30483f30a79cSChristoph Hellwig 30493f30a79cSChristoph Hellwig dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 30503f30a79cSChristoph Hellwig dma_set_max_seg_size(&pdev->dev, 0xffffffff); 30513f30a79cSChristoph Hellwig 30523f30a79cSChristoph Hellwig /* 30533f30a79cSChristoph Hellwig * Limit the max command size to prevent iod->sg allocations going 30543f30a79cSChristoph Hellwig * over a single page. 30553f30a79cSChristoph Hellwig */ 30563f30a79cSChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 30573f30a79cSChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 30583f30a79cSChristoph Hellwig dev->ctrl.max_segments = NVME_MAX_SEGS; 30593f30a79cSChristoph Hellwig 30603f30a79cSChristoph Hellwig /* 30613f30a79cSChristoph Hellwig * There is no support for SGLs for metadata (yet), so we are limited to 30623f30a79cSChristoph Hellwig * a single integrity segment for the separate metadata pointer. 30633f30a79cSChristoph Hellwig */ 30643f30a79cSChristoph Hellwig dev->ctrl.max_integrity_segments = 1; 30652e87570bSChristoph Hellwig return dev; 30662e87570bSChristoph Hellwig 30672e87570bSChristoph Hellwig out_put_device: 30682e87570bSChristoph Hellwig put_device(dev->dev); 30692e87570bSChristoph Hellwig kfree(dev->queues); 30702e87570bSChristoph Hellwig out_free_dev: 30712e87570bSChristoph Hellwig kfree(dev); 30722e87570bSChristoph Hellwig return ERR_PTR(ret); 30732e87570bSChristoph Hellwig } 30742e87570bSChristoph Hellwig 30752e87570bSChristoph Hellwig static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 30762e87570bSChristoph Hellwig { 30772e87570bSChristoph Hellwig struct nvme_dev *dev; 30782e87570bSChristoph Hellwig int result = -ENOMEM; 30792e87570bSChristoph Hellwig 30802e87570bSChristoph Hellwig dev = nvme_pci_alloc_dev(pdev, id); 30812e87570bSChristoph Hellwig if (!dev) 30822e87570bSChristoph Hellwig return -ENOMEM; 30832e87570bSChristoph Hellwig 30842e87570bSChristoph Hellwig result = nvme_dev_map(dev); 30852e87570bSChristoph Hellwig if (result) 30862e87570bSChristoph Hellwig goto out_uninit_ctrl; 30872e87570bSChristoph Hellwig 30882e87570bSChristoph Hellwig result = nvme_setup_prp_pools(dev); 30892e87570bSChristoph Hellwig if (result) 30902e87570bSChristoph Hellwig goto out_dev_unmap; 3091df4f9bc4SDavid E. Box 3092081a7d95SChristoph Hellwig result = nvme_pci_alloc_iod_mempool(dev); 3093081a7d95SChristoph Hellwig if (result) 30942e87570bSChristoph Hellwig goto out_release_prp_pools; 3095b6e44b4cSKeith Busch 30961b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 3097eac3ef26SChristoph Hellwig 3098eac3ef26SChristoph Hellwig result = nvme_pci_enable(dev); 3099eac3ef26SChristoph Hellwig if (result) 3100eac3ef26SChristoph Hellwig goto out_release_iod_mempool; 3101eac3ef26SChristoph Hellwig 3102eac3ef26SChristoph Hellwig result = nvme_pci_alloc_admin_tag_set(dev); 3103eac3ef26SChristoph Hellwig if (result) 3104eac3ef26SChristoph Hellwig goto out_disable; 3105eac3ef26SChristoph Hellwig 3106eac3ef26SChristoph Hellwig /* 3107eac3ef26SChristoph Hellwig * Mark the controller as connecting before sending admin commands to 3108eac3ef26SChristoph Hellwig * allow the timeout handler to do the right thing. 3109eac3ef26SChristoph Hellwig */ 3110eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3111eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3112eac3ef26SChristoph Hellwig "failed to mark controller CONNECTING\n"); 3113eac3ef26SChristoph Hellwig result = -EBUSY; 3114eac3ef26SChristoph Hellwig goto out_disable; 3115eac3ef26SChristoph Hellwig } 3116eac3ef26SChristoph Hellwig 3117eac3ef26SChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, false); 3118eac3ef26SChristoph Hellwig if (result) 3119eac3ef26SChristoph Hellwig goto out_disable; 3120eac3ef26SChristoph Hellwig 3121eac3ef26SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 3122eac3ef26SChristoph Hellwig 3123eac3ef26SChristoph Hellwig result = nvme_setup_host_mem(dev); 3124eac3ef26SChristoph Hellwig if (result < 0) 3125eac3ef26SChristoph Hellwig goto out_disable; 3126eac3ef26SChristoph Hellwig 3127eac3ef26SChristoph Hellwig result = nvme_setup_io_queues(dev); 3128eac3ef26SChristoph Hellwig if (result) 3129eac3ef26SChristoph Hellwig goto out_disable; 3130eac3ef26SChristoph Hellwig 3131eac3ef26SChristoph Hellwig if (dev->online_queues > 1) { 3132eac3ef26SChristoph Hellwig nvme_pci_alloc_tag_set(dev); 3133eac3ef26SChristoph Hellwig nvme_dbbuf_set(dev); 3134eac3ef26SChristoph Hellwig } else { 3135eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues not created\n"); 3136eac3ef26SChristoph Hellwig } 3137eac3ef26SChristoph Hellwig 3138eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3139eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3140eac3ef26SChristoph Hellwig "failed to mark controller live state\n"); 3141eac3ef26SChristoph Hellwig result = -ENODEV; 3142eac3ef26SChristoph Hellwig goto out_disable; 3143eac3ef26SChristoph Hellwig } 3144eac3ef26SChristoph Hellwig 31452e87570bSChristoph Hellwig pci_set_drvdata(pdev, dev); 31461b3c47c1SSagi Grimberg 3147eac3ef26SChristoph Hellwig nvme_start_ctrl(&dev->ctrl); 3148eac3ef26SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 314957dacad5SJay Sternberg return 0; 315057dacad5SJay Sternberg 3151eac3ef26SChristoph Hellwig out_disable: 3152eac3ef26SChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3153eac3ef26SChristoph Hellwig nvme_dev_disable(dev, true); 3154eac3ef26SChristoph Hellwig nvme_free_host_mem(dev); 3155eac3ef26SChristoph Hellwig nvme_dev_remove_admin(dev); 3156eac3ef26SChristoph Hellwig nvme_dbbuf_dma_free(dev); 3157eac3ef26SChristoph Hellwig nvme_free_queues(dev, 0); 3158eac3ef26SChristoph Hellwig out_release_iod_mempool: 3159eac3ef26SChristoph Hellwig mempool_destroy(dev->iod_mempool); 31602e87570bSChristoph Hellwig out_release_prp_pools: 316157dacad5SJay Sternberg nvme_release_prp_pools(dev); 31622e87570bSChristoph Hellwig out_dev_unmap: 3163b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 31642e87570bSChristoph Hellwig out_uninit_ctrl: 31652e87570bSChristoph Hellwig nvme_uninit_ctrl(&dev->ctrl); 316657dacad5SJay Sternberg return result; 316757dacad5SJay Sternberg } 316857dacad5SJay Sternberg 3169775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 317057dacad5SJay Sternberg { 317157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3172c1ac9a4bSKeith Busch 3173c1ac9a4bSKeith Busch /* 3174c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3175c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3176c1ac9a4bSKeith Busch * with ->remove(). 3177c1ac9a4bSKeith Busch */ 3178c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3179c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3180775755edSChristoph Hellwig } 318157dacad5SJay Sternberg 3182775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3183775755edSChristoph Hellwig { 3184f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3185c1ac9a4bSKeith Busch 3186c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3187c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 318857dacad5SJay Sternberg } 318957dacad5SJay Sternberg 319057dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 319157dacad5SJay Sternberg { 319257dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 31934e523547SBaolin Wang 3194c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 319557dacad5SJay Sternberg } 319657dacad5SJay Sternberg 3197f58944e2SKeith Busch /* 3198f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3199f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3200f58944e2SKeith Busch * order to proceed. 3201f58944e2SKeith Busch */ 320257dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 320357dacad5SJay Sternberg { 320457dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 320557dacad5SJay Sternberg 3206bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 320757dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 32080ff9d4e1SKeith Busch 32096db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 32100ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 32111d39e692SKeith Busch nvme_dev_disable(dev, true); 32126db28edaSKeith Busch } 32130ff9d4e1SKeith Busch 3214d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3215d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3216d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3217a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 321887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 321957dacad5SJay Sternberg nvme_dev_remove_admin(dev); 3220c11b7716SChristoph Hellwig nvme_dbbuf_dma_free(dev); 322157dacad5SJay Sternberg nvme_free_queues(dev, 0); 3222c11b7716SChristoph Hellwig mempool_destroy(dev->iod_mempool); 322357dacad5SJay Sternberg nvme_release_prp_pools(dev); 3224b00a726aSKeith Busch nvme_dev_unmap(dev); 3225726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 322657dacad5SJay Sternberg } 322757dacad5SJay Sternberg 322857dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3229d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3230d916b1beSKeith Busch { 3231d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3232d916b1beSKeith Busch } 3233d916b1beSKeith Busch 3234d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3235d916b1beSKeith Busch { 3236d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3237d916b1beSKeith Busch } 3238d916b1beSKeith Busch 3239d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3240d916b1beSKeith Busch { 3241d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3242d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3243d916b1beSKeith Busch 32444eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3245d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3246e5ad96f3SKeith Busch goto reset; 3247e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3248e5ad96f3SKeith Busch goto reset; 3249e5ad96f3SKeith Busch 3250d916b1beSKeith Busch return 0; 3251e5ad96f3SKeith Busch reset: 3252e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3253d916b1beSKeith Busch } 3254d916b1beSKeith Busch 325557dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 325657dacad5SJay Sternberg { 325757dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 325857dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3259d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3260d916b1beSKeith Busch int ret = -EBUSY; 3261d916b1beSKeith Busch 32624eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32634eaefe8cSRafael J. Wysocki 3264d916b1beSKeith Busch /* 3265d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3266d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3267d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3268d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3269d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3270d916b1beSKeith Busch * device fully. 32714eaefe8cSRafael J. Wysocki * 32724eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32734eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32744eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32754eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3276d916b1beSKeith Busch */ 32774eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3278cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3279c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3280c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3281d916b1beSKeith Busch 3282d916b1beSKeith Busch nvme_start_freeze(ctrl); 3283d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3284d916b1beSKeith Busch nvme_sync_queues(ctrl); 3285d916b1beSKeith Busch 32865d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3287d916b1beSKeith Busch goto unfreeze; 3288d916b1beSKeith Busch 3289e5ad96f3SKeith Busch /* 3290e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3291e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3292e5ad96f3SKeith Busch * non-operational power state. 3293e5ad96f3SKeith Busch */ 3294e5ad96f3SKeith Busch if (ndev->hmb) { 3295e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3296e5ad96f3SKeith Busch if (ret < 0) 3297e5ad96f3SKeith Busch goto unfreeze; 3298e5ad96f3SKeith Busch } 3299e5ad96f3SKeith Busch 3300d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3301d916b1beSKeith Busch if (ret < 0) 3302d916b1beSKeith Busch goto unfreeze; 3303d916b1beSKeith Busch 33047cbb5c6fSMario Limonciello /* 33057cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 33067cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 33077cbb5c6fSMario Limonciello * want pci interfering. 33087cbb5c6fSMario Limonciello */ 33097cbb5c6fSMario Limonciello pci_save_state(pdev); 33107cbb5c6fSMario Limonciello 3311d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3312d916b1beSKeith Busch if (ret < 0) 3313d916b1beSKeith Busch goto unfreeze; 3314d916b1beSKeith Busch 3315d916b1beSKeith Busch if (ret) { 33167cbb5c6fSMario Limonciello /* discard the saved state */ 33177cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33187cbb5c6fSMario Limonciello 3319d916b1beSKeith Busch /* 3320d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 332105d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3322d916b1beSKeith Busch */ 3323c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3324d916b1beSKeith Busch ctrl->npss = 0; 3325d916b1beSKeith Busch } 3326d916b1beSKeith Busch unfreeze: 3327d916b1beSKeith Busch nvme_unfreeze(ctrl); 3328d916b1beSKeith Busch return ret; 3329d916b1beSKeith Busch } 3330d916b1beSKeith Busch 3331d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3332d916b1beSKeith Busch { 3333d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33344e523547SBaolin Wang 3335c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 333657dacad5SJay Sternberg } 333757dacad5SJay Sternberg 3338d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 333957dacad5SJay Sternberg { 334057dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 334157dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 334257dacad5SJay Sternberg 3343c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 334457dacad5SJay Sternberg } 334557dacad5SJay Sternberg 334621774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3347d916b1beSKeith Busch .suspend = nvme_suspend, 3348d916b1beSKeith Busch .resume = nvme_resume, 3349d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3350d916b1beSKeith Busch .thaw = nvme_simple_resume, 3351d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3352d916b1beSKeith Busch .restore = nvme_simple_resume, 3353d916b1beSKeith Busch }; 3354d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 335557dacad5SJay Sternberg 3356a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3357a0a3408eSKeith Busch pci_channel_state_t state) 3358a0a3408eSKeith Busch { 3359a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3360a0a3408eSKeith Busch 3361a0a3408eSKeith Busch /* 3362a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3363a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3364a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3365a0a3408eSKeith Busch */ 3366a0a3408eSKeith Busch switch (state) { 3367a0a3408eSKeith Busch case pci_channel_io_normal: 3368a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3369a0a3408eSKeith Busch case pci_channel_io_frozen: 3370d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3371d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3372a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3373a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3374a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3375d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3376d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3377a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3378a0a3408eSKeith Busch } 3379a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3380a0a3408eSKeith Busch } 3381a0a3408eSKeith Busch 3382a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3383a0a3408eSKeith Busch { 3384a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3385a0a3408eSKeith Busch 33861b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3387a0a3408eSKeith Busch pci_restore_state(pdev); 3388d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3389a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3390a0a3408eSKeith Busch } 3391a0a3408eSKeith Busch 3392a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3393a0a3408eSKeith Busch { 339472cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 339572cd4cc2SKeith Busch 339672cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3397a0a3408eSKeith Busch } 3398a0a3408eSKeith Busch 339957dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 340057dacad5SJay Sternberg .error_detected = nvme_error_detected, 340157dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 340257dacad5SJay Sternberg .resume = nvme_error_resume, 3403775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3404775755edSChristoph Hellwig .reset_done = nvme_reset_done, 340557dacad5SJay Sternberg }; 340657dacad5SJay Sternberg 340757dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3408972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 340908095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3410e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3411972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 341299466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3413e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3414972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 341599466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 341625e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 341725e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3418972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3419f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3420f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 342150af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34229abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34236c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3424ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3425ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34266299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34276299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3428540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34297b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 343066dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 343166dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 343266dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 343366dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34345bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3435c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3436c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 34370302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34385e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34395e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 344054adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 344154adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34428c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34438c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3444015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3445015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3446d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3447d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3448d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34497ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3450abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34517ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34522cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 34532cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3454c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 345573029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 345673029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 3457d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3458d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3459d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3460d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34616e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34626e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34636e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3464e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3465e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 346608b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 34671629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 34681629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3469f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3470f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3471f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 347241f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 347341f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 34745611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34755611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3476c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3477c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 347802ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 347902ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348089919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 348189919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348243047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 348343047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348443047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 348543047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348643047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 348743047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 348843047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 348943047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3490dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3491dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3492538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3493538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3494ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3495ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3496ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3497ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3498ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3499ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3500ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3501ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3502ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3503ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 350470ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 350570ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3506a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3507a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3508a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3509a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 35103765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 35113765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3512f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3513f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 3514d5d3c100SXi Ruoyao { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3515d5d3c100SXi Ruoyao .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 35166b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 35176b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3518d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3519d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 3520200dccd0SShyamin Ayesh { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3521200dccd0SShyamin Ayesh .driver_data = NVME_QUIRK_BOGUS_NID, }, 352280b26240SAbhijit { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 352380b26240SAbhijit .driver_data = NVME_QUIRK_BOGUS_NID, }, 35244bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 35254bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35264bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 35274bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35284bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 35294bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35304bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 35314bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35324bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 35334bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 35344bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 35354bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 353698f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 353798f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3538124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 353966341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 354066341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3541d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3542a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3543a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 35440b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 354557dacad5SJay Sternberg { 0, } 354657dacad5SJay Sternberg }; 354757dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 354857dacad5SJay Sternberg 354957dacad5SJay Sternberg static struct pci_driver nvme_driver = { 355057dacad5SJay Sternberg .name = "nvme", 355157dacad5SJay Sternberg .id_table = nvme_id_table, 355257dacad5SJay Sternberg .probe = nvme_probe, 355357dacad5SJay Sternberg .remove = nvme_remove, 355457dacad5SJay Sternberg .shutdown = nvme_shutdown, 355557dacad5SJay Sternberg .driver = { 3556eac3ef26SChristoph Hellwig .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3557eac3ef26SChristoph Hellwig #ifdef CONFIG_PM_SLEEP 355857dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 3559d916b1beSKeith Busch #endif 3560eac3ef26SChristoph Hellwig }, 356174d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 356257dacad5SJay Sternberg .err_handler = &nvme_err_handler, 356357dacad5SJay Sternberg }; 356457dacad5SJay Sternberg 356557dacad5SJay Sternberg static int __init nvme_init(void) 356657dacad5SJay Sternberg { 356781101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 356881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 356981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3570612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 3571c372cdd1SKeith Busch BUILD_BUG_ON(DIV_ROUND_UP(nvme_pci_npages_prp(), NVME_CTRL_PAGE_SIZE) > 3572c372cdd1SKeith Busch S8_MAX); 357317c33167SKeith Busch 35749a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 357557dacad5SJay Sternberg } 357657dacad5SJay Sternberg 357757dacad5SJay Sternberg static void __exit nvme_exit(void) 357857dacad5SJay Sternberg { 357957dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 358003e0f3a6SMing Lei flush_workqueue(nvme_wq); 358157dacad5SJay Sternberg } 358257dacad5SJay Sternberg 358357dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 358457dacad5SJay Sternberg MODULE_LICENSE("GPL"); 358557dacad5SJay Sternberg MODULE_VERSION("1.0"); 358657dacad5SJay Sternberg module_init(nvme_init); 358757dacad5SJay Sternberg module_exit(nvme_exit); 3588