15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 1899722c8aSChristophe JAILLET #include <linux/kstrtox.h> 19dc90f084SChristoph Hellwig #include <linux/memremap.h> 2057dacad5SJay Sternberg #include <linux/mm.h> 2157dacad5SJay Sternberg #include <linux/module.h> 2277bf25eaSKeith Busch #include <linux/mutex.h> 23d0877473SKeith Busch #include <linux/once.h> 2457dacad5SJay Sternberg #include <linux/pci.h> 25d916b1beSKeith Busch #include <linux/suspend.h> 2657dacad5SJay Sternberg #include <linux/t10-pi.h> 2757dacad5SJay Sternberg #include <linux/types.h> 289cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2920d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 30a98e58e5SScott Bauer #include <linux/sed-opal.h> 310f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3257dacad5SJay Sternberg 33604c01d5Syupeng #include "trace.h" 3457dacad5SJay Sternberg #include "nvme.h" 3557dacad5SJay Sternberg 36c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 378a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3857dacad5SJay Sternberg 3984173423SKeith Busch #define SGES_PER_PAGE (NVME_CTRL_PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 40adf68f21SChristoph Hellwig 41943e942eSJens Axboe /* 42943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 43943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 44943e942eSJens Axboe */ 45*7846c1b5SKeith Busch #define NVME_MAX_KB_SZ 8192 46*7846c1b5SKeith Busch #define NVME_MAX_SEGS 128 47*7846c1b5SKeith Busch #define NVME_MAX_NR_ALLOCATIONS 5 48943e942eSJens Axboe 4957dacad5SJay Sternberg static int use_threaded_interrupts; 502e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 5157dacad5SJay Sternberg 5257dacad5SJay Sternberg static bool use_cmb_sqes = true; 5369f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5457dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5557dacad5SJay Sternberg 5687ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5787ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5887ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5987ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 6057dacad5SJay Sternberg 61a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 62a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 63a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 64a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 65a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 66a7a7cbe3SChaitanya Kulkarni 6727453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6827453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 69b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 70b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 71b27c1e68Sweiping zhang .set = io_queue_depth_set, 7261f3b896SChaitanya Kulkarni .get = param_get_uint, 73b27c1e68Sweiping zhang }; 74b27c1e68Sweiping zhang 7561f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 76b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7727453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 78b27c1e68Sweiping zhang 799c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 809c9e76d5SWeiping Zhang { 819c9e76d5SWeiping Zhang unsigned int n; 829c9e76d5SWeiping Zhang int ret; 839c9e76d5SWeiping Zhang 849c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 859c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 869c9e76d5SWeiping Zhang return -EINVAL; 879c9e76d5SWeiping Zhang return param_set_uint(val, kp); 889c9e76d5SWeiping Zhang } 899c9e76d5SWeiping Zhang 909c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 919c9e76d5SWeiping Zhang .set = io_queue_count_set, 929c9e76d5SWeiping Zhang .get = param_get_uint, 939c9e76d5SWeiping Zhang }; 949c9e76d5SWeiping Zhang 953f68baf7SKeith Busch static unsigned int write_queues; 969c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 973b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 983b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 993b6592f7SJens Axboe "will share a queue set."); 1003b6592f7SJens Axboe 1013f68baf7SKeith Busch static unsigned int poll_queues; 1029c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1034b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1044b04cc6aSJens Axboe 105df4f9bc4SDavid E. Box static bool noacpi; 106df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 107df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 108df4f9bc4SDavid E. Box 1091c63dc66SChristoph Hellwig struct nvme_dev; 1101c63dc66SChristoph Hellwig struct nvme_queue; 11157dacad5SJay Sternberg 112a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1137d879c90SChristoph Hellwig static void nvme_delete_io_queues(struct nvme_dev *dev); 11457dacad5SJay Sternberg 11557dacad5SJay Sternberg /* 1161c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1171c63dc66SChristoph Hellwig */ 1181c63dc66SChristoph Hellwig struct nvme_dev { 119147b27e4SSagi Grimberg struct nvme_queue *queues; 1201c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1211c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1221c63dc66SChristoph Hellwig u32 __iomem *dbs; 1231c63dc66SChristoph Hellwig struct device *dev; 1241c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1251c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1261c63dc66SChristoph Hellwig unsigned online_queues; 1271c63dc66SChristoph Hellwig unsigned max_qid; 128e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12922b55601SKeith Busch unsigned int num_vecs; 1307442ddceSJohn Garry u32 q_depth; 131c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1321c63dc66SChristoph Hellwig u32 db_stride; 1331c63dc66SChristoph Hellwig void __iomem *bar; 13497f6ef64SXu Yu unsigned long bar_mapped_size; 13577bf25eaSKeith Busch struct mutex shutdown_lock; 1361c63dc66SChristoph Hellwig bool subsystem; 1371c63dc66SChristoph Hellwig u64 cmb_size; 1380f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1391c63dc66SChristoph Hellwig u32 cmbsz; 140202021c1SStephen Bates u32 cmbloc; 1411c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 142d916b1beSKeith Busch u32 last_ps; 143a5df5e79SKeith Busch bool hmb; 14487ad72a5SChristoph Hellwig 145943e942eSJens Axboe mempool_t *iod_mempool; 146943e942eSJens Axboe 14787ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 148b5f96cb7SKlaus Jensen __le32 *dbbuf_dbs; 149f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 150b5f96cb7SKlaus Jensen __le32 *dbbuf_eis; 151f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15287ad72a5SChristoph Hellwig 15387ad72a5SChristoph Hellwig /* host memory buffer support: */ 15487ad72a5SChristoph Hellwig u64 host_mem_size; 15587ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1564033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15787ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15887ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1592a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1612a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 16257dacad5SJay Sternberg }; 16357dacad5SJay Sternberg 164b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 165b27c1e68Sweiping zhang { 16627453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16727453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 168b27c1e68Sweiping zhang } 169b27c1e68Sweiping zhang 170f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 171f9f38e33SHelen Koike { 172f9f38e33SHelen Koike return qid * 2 * stride; 173f9f38e33SHelen Koike } 174f9f38e33SHelen Koike 175f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 176f9f38e33SHelen Koike { 177f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 178f9f38e33SHelen Koike } 179f9f38e33SHelen Koike 1801c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1811c63dc66SChristoph Hellwig { 1821c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1831c63dc66SChristoph Hellwig } 1841c63dc66SChristoph Hellwig 18557dacad5SJay Sternberg /* 18657dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18757dacad5SJay Sternberg * commands and one for I/O commands). 18857dacad5SJay Sternberg */ 18957dacad5SJay Sternberg struct nvme_queue { 19057dacad5SJay Sternberg struct nvme_dev *dev; 1911ab0cd69SJens Axboe spinlock_t sq_lock; 192c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1933a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1943a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19574943d45SKeith Busch struct nvme_completion *cqes; 19657dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19757dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19857dacad5SJay Sternberg u32 __iomem *q_db; 1997442ddceSJohn Garry u32 q_depth; 2007c349ddeSKeith Busch u16 cq_vector; 20157dacad5SJay Sternberg u16 sq_tail; 20238210800SKeith Busch u16 last_sq_tail; 20357dacad5SJay Sternberg u16 cq_head; 20457dacad5SJay Sternberg u16 qid; 20557dacad5SJay Sternberg u8 cq_phase; 206c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2074e224106SChristoph Hellwig unsigned long flags; 2084e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 20963223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 210d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2117c349ddeSKeith Busch #define NVMEQ_POLLED 3 212b5f96cb7SKlaus Jensen __le32 *dbbuf_sq_db; 213b5f96cb7SKlaus Jensen __le32 *dbbuf_cq_db; 214b5f96cb7SKlaus Jensen __le32 *dbbuf_sq_ei; 215b5f96cb7SKlaus Jensen __le32 *dbbuf_cq_ei; 216d1ed6aa1SChristoph Hellwig struct completion delete_done; 21757dacad5SJay Sternberg }; 21857dacad5SJay Sternberg 219*7846c1b5SKeith Busch union nvme_descriptor { 220*7846c1b5SKeith Busch struct nvme_sgl_desc *sg_list; 221*7846c1b5SKeith Busch __le64 *prp_list; 222*7846c1b5SKeith Busch }; 223*7846c1b5SKeith Busch 22457dacad5SJay Sternberg /* 2259b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2269b048119SChristoph Hellwig * 2279b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2289b048119SChristoph Hellwig * to the actual struct scatterlist. 22971bd150cSChristoph Hellwig */ 23071bd150cSChristoph Hellwig struct nvme_iod { 231d49187e9SChristoph Hellwig struct nvme_request req; 232af7fae85SKeith Busch struct nvme_command cmd; 233a7a7cbe3SChaitanya Kulkarni bool use_sgl; 23452da4f3fSKeith Busch bool aborted; 235c372cdd1SKeith Busch s8 nr_allocations; /* PRP list pool allocations. 0 means small 236c372cdd1SKeith Busch pool in use */ 237dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 238c4c22c52SKeith Busch dma_addr_t first_dma; 239783b94bdSChristoph Hellwig dma_addr_t meta_dma; 24091fb2b60SLogan Gunthorpe struct sg_table sgt; 241*7846c1b5SKeith Busch union nvme_descriptor list[NVME_MAX_NR_ALLOCATIONS]; 24257dacad5SJay Sternberg }; 24357dacad5SJay Sternberg 2442a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2453b6592f7SJens Axboe { 2462a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 247f9f38e33SHelen Koike } 248f9f38e33SHelen Koike 24965a54646SChristoph Hellwig static void nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 250f9f38e33SHelen Koike { 2512a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 252f9f38e33SHelen Koike 25365a54646SChristoph Hellwig if (!(dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP)) 25465a54646SChristoph Hellwig return; 25565a54646SChristoph Hellwig 25658847f12SKeith Busch if (dev->dbbuf_dbs) { 25758847f12SKeith Busch /* 25858847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25958847f12SKeith Busch * values from the previous instantiation. 26058847f12SKeith Busch */ 26158847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 26258847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 26365a54646SChristoph Hellwig return; 26458847f12SKeith Busch } 265f9f38e33SHelen Koike 266f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 267f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 268f9f38e33SHelen Koike GFP_KERNEL); 269f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 27065a54646SChristoph Hellwig goto fail; 271f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 272f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 273f9f38e33SHelen Koike GFP_KERNEL); 27465a54646SChristoph Hellwig if (!dev->dbbuf_eis) 27565a54646SChristoph Hellwig goto fail_free_dbbuf_dbs; 27665a54646SChristoph Hellwig return; 277f9f38e33SHelen Koike 27865a54646SChristoph Hellwig fail_free_dbbuf_dbs: 27965a54646SChristoph Hellwig dma_free_coherent(dev->dev, mem_size, dev->dbbuf_dbs, 28065a54646SChristoph Hellwig dev->dbbuf_dbs_dma_addr); 28165a54646SChristoph Hellwig dev->dbbuf_dbs = NULL; 28265a54646SChristoph Hellwig fail: 28365a54646SChristoph Hellwig dev_warn(dev->dev, "unable to allocate dma for dbbuf\n"); 284f9f38e33SHelen Koike } 285f9f38e33SHelen Koike 286f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 287f9f38e33SHelen Koike { 2882a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 289f9f38e33SHelen Koike 290f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 291f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 292f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 293f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 294f9f38e33SHelen Koike } 295f9f38e33SHelen Koike if (dev->dbbuf_eis) { 296f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 297f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 298f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 299f9f38e33SHelen Koike } 300f9f38e33SHelen Koike } 301f9f38e33SHelen Koike 302f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 303f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 304f9f38e33SHelen Koike { 305f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 306f9f38e33SHelen Koike return; 307f9f38e33SHelen Koike 308f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 309f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 310f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 311f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 312f9f38e33SHelen Koike } 313f9f38e33SHelen Koike 3140f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3150f0d2c87SMinwoo Im { 3160f0d2c87SMinwoo Im if (!nvmeq->qid) 3170f0d2c87SMinwoo Im return; 3180f0d2c87SMinwoo Im 3190f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3200f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3210f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3220f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3230f0d2c87SMinwoo Im } 3240f0d2c87SMinwoo Im 325f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 326f9f38e33SHelen Koike { 327f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3280f0d2c87SMinwoo Im unsigned int i; 329f9f38e33SHelen Koike 330f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 331f9f38e33SHelen Koike return; 332f9f38e33SHelen Koike 333f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 334f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 335f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 336f9f38e33SHelen Koike 337f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3389bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 339f9f38e33SHelen Koike /* Free memory and continue on */ 340f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3410f0d2c87SMinwoo Im 3420f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3430f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 344f9f38e33SHelen Koike } 345f9f38e33SHelen Koike } 346f9f38e33SHelen Koike 347f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 348f9f38e33SHelen Koike { 349f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 350f9f38e33SHelen Koike } 351f9f38e33SHelen Koike 352f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 353b5f96cb7SKlaus Jensen static bool nvme_dbbuf_update_and_check_event(u16 value, __le32 *dbbuf_db, 354b5f96cb7SKlaus Jensen volatile __le32 *dbbuf_ei) 355f9f38e33SHelen Koike { 356f9f38e33SHelen Koike if (dbbuf_db) { 357b5f96cb7SKlaus Jensen u16 old_value, event_idx; 358f9f38e33SHelen Koike 359f9f38e33SHelen Koike /* 360f9f38e33SHelen Koike * Ensure that the queue is written before updating 361f9f38e33SHelen Koike * the doorbell in memory 362f9f38e33SHelen Koike */ 363f9f38e33SHelen Koike wmb(); 364f9f38e33SHelen Koike 365b5f96cb7SKlaus Jensen old_value = le32_to_cpu(*dbbuf_db); 366b5f96cb7SKlaus Jensen *dbbuf_db = cpu_to_le32(value); 367f9f38e33SHelen Koike 368f1ed3df2SMichal Wnukowski /* 369f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 370f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 371f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 372f1ed3df2SMichal Wnukowski * the doorbell. 373f1ed3df2SMichal Wnukowski */ 374f1ed3df2SMichal Wnukowski mb(); 375f1ed3df2SMichal Wnukowski 376b5f96cb7SKlaus Jensen event_idx = le32_to_cpu(*dbbuf_ei); 377b5f96cb7SKlaus Jensen if (!nvme_dbbuf_need_event(event_idx, value, old_value)) 378f9f38e33SHelen Koike return false; 379f9f38e33SHelen Koike } 380f9f38e33SHelen Koike 381f9f38e33SHelen Koike return true; 38257dacad5SJay Sternberg } 38357dacad5SJay Sternberg 38457dacad5SJay Sternberg /* 38557dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 38657dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 38757dacad5SJay Sternberg * the I/O. 38857dacad5SJay Sternberg */ 389b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 39057dacad5SJay Sternberg { 391c89a529eSKeith Busch unsigned max_bytes = (NVME_MAX_KB_SZ * 1024) + NVME_CTRL_PAGE_SIZE; 392c89a529eSKeith Busch unsigned nprps = DIV_ROUND_UP(max_bytes, NVME_CTRL_PAGE_SIZE); 39384173423SKeith Busch return DIV_ROUND_UP(8 * nprps, NVME_CTRL_PAGE_SIZE - 8); 39457dacad5SJay Sternberg } 39557dacad5SJay Sternberg 39657dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 39757dacad5SJay Sternberg unsigned int hctx_idx) 39857dacad5SJay Sternberg { 3990da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(data); 400147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40157dacad5SJay Sternberg 40257dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 40357dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 40457dacad5SJay Sternberg 40557dacad5SJay Sternberg hctx->driver_data = nvmeq; 40657dacad5SJay Sternberg return 0; 40757dacad5SJay Sternberg } 40857dacad5SJay Sternberg 40957dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41057dacad5SJay Sternberg unsigned int hctx_idx) 41157dacad5SJay Sternberg { 4120da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(data); 413147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 41457dacad5SJay Sternberg 41557dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 41657dacad5SJay Sternberg hctx->driver_data = nvmeq; 41757dacad5SJay Sternberg return 0; 41857dacad5SJay Sternberg } 41957dacad5SJay Sternberg 420e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 421e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 422e559398fSChristoph Hellwig unsigned int numa_node) 42357dacad5SJay Sternberg { 4240da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(set->driver_data); 425f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 42659e29ce6SSagi Grimberg 42759e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 428f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 42957dacad5SJay Sternberg return 0; 43057dacad5SJay Sternberg } 43157dacad5SJay Sternberg 4323b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4333b6592f7SJens Axboe { 4343b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4353b6592f7SJens Axboe if (dev->num_vecs > 1) 4363b6592f7SJens Axboe return 1; 4373b6592f7SJens Axboe 4383b6592f7SJens Axboe return 0; 4393b6592f7SJens Axboe } 4403b6592f7SJens Axboe 441a4e1d0b7SBart Van Assche static void nvme_pci_map_queues(struct blk_mq_tag_set *set) 442dca51e78SChristoph Hellwig { 4430da7feaaSChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(set->driver_data); 4443b6592f7SJens Axboe int i, qoff, offset; 445dca51e78SChristoph Hellwig 4463b6592f7SJens Axboe offset = queue_irq_offset(dev); 4473b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4483b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4493b6592f7SJens Axboe 4503b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4513b6592f7SJens Axboe if (!map->nr_queues) { 452e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4537e849dd9SChristoph Hellwig continue; 4543b6592f7SJens Axboe } 4553b6592f7SJens Axboe 4564b04cc6aSJens Axboe /* 4574b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4584b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4594b04cc6aSJens Axboe */ 4603b6592f7SJens Axboe map->queue_offset = qoff; 461cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4623b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4634b04cc6aSJens Axboe else 4644b04cc6aSJens Axboe blk_mq_map_queues(map); 4653b6592f7SJens Axboe qoff += map->nr_queues; 4663b6592f7SJens Axboe offset += map->nr_queues; 4673b6592f7SJens Axboe } 468dca51e78SChristoph Hellwig } 469dca51e78SChristoph Hellwig 47038210800SKeith Busch /* 47138210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 47238210800SKeith Busch */ 47338210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 47404f3eafdSJens Axboe { 47538210800SKeith Busch if (!write_sq) { 47638210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 47738210800SKeith Busch 47838210800SKeith Busch if (next_tail == nvmeq->q_depth) 47938210800SKeith Busch next_tail = 0; 48038210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 48138210800SKeith Busch return; 48238210800SKeith Busch } 48338210800SKeith Busch 48404f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 48504f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 48604f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 48738210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 48804f3eafdSJens Axboe } 48904f3eafdSJens Axboe 4903233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 4913233b94cSJens Axboe struct nvme_command *cmd) 49257dacad5SJay Sternberg { 493c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 4943233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 49590ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 49690ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 49704f3eafdSJens Axboe } 49804f3eafdSJens Axboe 49904f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 50004f3eafdSJens Axboe { 50104f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 50204f3eafdSJens Axboe 50304f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 50438210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 50538210800SKeith Busch nvme_write_sq_db(nvmeq, true); 50690ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 50757dacad5SJay Sternberg } 50857dacad5SJay Sternberg 509ae582935SKeith Busch static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req, 510ae582935SKeith Busch int nseg) 511955b1b5aSMinwoo Im { 512a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 513955b1b5aSMinwoo Im unsigned int avg_seg_size; 514955b1b5aSMinwoo Im 51520469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 516955b1b5aSMinwoo Im 517253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 518955b1b5aSMinwoo Im return false; 519a53232cbSKeith Busch if (!nvmeq->qid) 520955b1b5aSMinwoo Im return false; 521955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 522955b1b5aSMinwoo Im return false; 523955b1b5aSMinwoo Im return true; 524955b1b5aSMinwoo Im } 525955b1b5aSMinwoo Im 5269275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 52757dacad5SJay Sternberg { 5286c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5299275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5309275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 53157dacad5SJay Sternberg int i; 53257dacad5SJay Sternberg 533c372cdd1SKeith Busch for (i = 0; i < iod->nr_allocations; i++) { 534*7846c1b5SKeith Busch __le64 *prp_list = iod->list[i].prp_list; 5359275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5369275c206SChristoph Hellwig 5379275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5389275c206SChristoph Hellwig dma_addr = next_dma_addr; 539dff824b2SChristoph Hellwig } 5409275c206SChristoph Hellwig } 5419275c206SChristoph Hellwig 5429275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5439275c206SChristoph Hellwig { 5449275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5457fe07d14SChristoph Hellwig 5469275c206SChristoph Hellwig if (iod->dma_len) { 5479275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5489275c206SChristoph Hellwig rq_dma_dir(req)); 5499275c206SChristoph Hellwig return; 5509275c206SChristoph Hellwig } 5519275c206SChristoph Hellwig 55291fb2b60SLogan Gunthorpe WARN_ON_ONCE(!iod->sgt.nents); 5539275c206SChristoph Hellwig 55491fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 55591fb2b60SLogan Gunthorpe 556c372cdd1SKeith Busch if (iod->nr_allocations == 0) 557*7846c1b5SKeith Busch dma_pool_free(dev->prp_small_pool, iod->list[0].sg_list, 5589275c206SChristoph Hellwig iod->first_dma); 5599275c206SChristoph Hellwig else if (iod->use_sgl) 560*7846c1b5SKeith Busch dma_pool_free(dev->prp_page_pool, iod->list[0].sg_list, 56101df742dSKeith Busch iod->first_dma); 5629275c206SChristoph Hellwig else 5639275c206SChristoph Hellwig nvme_free_prps(dev, req); 56491fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 56557dacad5SJay Sternberg } 56657dacad5SJay Sternberg 567d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 568d0877473SKeith Busch { 569d0877473SKeith Busch int i; 570d0877473SKeith Busch struct scatterlist *sg; 571d0877473SKeith Busch 572d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 573d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 574d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 575d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 576d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 577d0877473SKeith Busch sg_dma_len(sg)); 578d0877473SKeith Busch } 579d0877473SKeith Busch } 580d0877473SKeith Busch 581a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 582a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 58357dacad5SJay Sternberg { 584f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 58557dacad5SJay Sternberg struct dma_pool *pool; 586b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 58791fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 58857dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 58957dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 5906c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 59157dacad5SJay Sternberg __le64 *prp_list; 59257dacad5SJay Sternberg dma_addr_t prp_dma; 59357dacad5SJay Sternberg int nprps, i; 59457dacad5SJay Sternberg 5956c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 5965228b328SJan H. Schönherr if (length <= 0) { 5975228b328SJan H. Schönherr iod->first_dma = 0; 598a7a7cbe3SChaitanya Kulkarni goto done; 5995228b328SJan H. Schönherr } 60057dacad5SJay Sternberg 6016c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 60257dacad5SJay Sternberg if (dma_len) { 6036c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 60457dacad5SJay Sternberg } else { 60557dacad5SJay Sternberg sg = sg_next(sg); 60657dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 60757dacad5SJay Sternberg dma_len = sg_dma_len(sg); 60857dacad5SJay Sternberg } 60957dacad5SJay Sternberg 6106c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 61157dacad5SJay Sternberg iod->first_dma = dma_addr; 612a7a7cbe3SChaitanya Kulkarni goto done; 61357dacad5SJay Sternberg } 61457dacad5SJay Sternberg 6156c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 61657dacad5SJay Sternberg if (nprps <= (256 / 8)) { 61757dacad5SJay Sternberg pool = dev->prp_small_pool; 618c372cdd1SKeith Busch iod->nr_allocations = 0; 61957dacad5SJay Sternberg } else { 62057dacad5SJay Sternberg pool = dev->prp_page_pool; 621c372cdd1SKeith Busch iod->nr_allocations = 1; 62257dacad5SJay Sternberg } 62357dacad5SJay Sternberg 62469d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 62557dacad5SJay Sternberg if (!prp_list) { 626c372cdd1SKeith Busch iod->nr_allocations = -1; 62786eea289SKeith Busch return BLK_STS_RESOURCE; 62857dacad5SJay Sternberg } 629*7846c1b5SKeith Busch iod->list[0].prp_list = prp_list; 63057dacad5SJay Sternberg iod->first_dma = prp_dma; 63157dacad5SJay Sternberg i = 0; 63257dacad5SJay Sternberg for (;;) { 6336c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 63457dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 63569d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 63657dacad5SJay Sternberg if (!prp_list) 637fa073216SChristoph Hellwig goto free_prps; 638*7846c1b5SKeith Busch iod->list[iod->nr_allocations++].prp_list = prp_list; 63957dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 64057dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 64157dacad5SJay Sternberg i = 1; 64257dacad5SJay Sternberg } 64357dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6446c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6456c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6466c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 64757dacad5SJay Sternberg if (length <= 0) 64857dacad5SJay Sternberg break; 64957dacad5SJay Sternberg if (dma_len > 0) 65057dacad5SJay Sternberg continue; 65186eea289SKeith Busch if (unlikely(dma_len < 0)) 65286eea289SKeith Busch goto bad_sgl; 65357dacad5SJay Sternberg sg = sg_next(sg); 65457dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65557dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65657dacad5SJay Sternberg } 657a7a7cbe3SChaitanya Kulkarni done: 65891fb2b60SLogan Gunthorpe cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sgt.sgl)); 659a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 66086eea289SKeith Busch return BLK_STS_OK; 661fa073216SChristoph Hellwig free_prps: 662fa073216SChristoph Hellwig nvme_free_prps(dev, req); 663fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 66486eea289SKeith Busch bad_sgl: 66591fb2b60SLogan Gunthorpe WARN(DO_ONCE(nvme_print_sgl, iod->sgt.sgl, iod->sgt.nents), 666d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 66791fb2b60SLogan Gunthorpe blk_rq_payload_bytes(req), iod->sgt.nents); 66886eea289SKeith Busch return BLK_STS_IOERR; 66957dacad5SJay Sternberg } 67057dacad5SJay Sternberg 671a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 672a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 673a7a7cbe3SChaitanya Kulkarni { 674a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 675a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 676a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 677a7a7cbe3SChaitanya Kulkarni } 678a7a7cbe3SChaitanya Kulkarni 679a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 680a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 681a7a7cbe3SChaitanya Kulkarni { 682a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 683a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 684a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 685a7a7cbe3SChaitanya Kulkarni } 686a7a7cbe3SChaitanya Kulkarni 687a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 68891fb2b60SLogan Gunthorpe struct request *req, struct nvme_rw_command *cmd) 689a7a7cbe3SChaitanya Kulkarni { 690a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 691a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 692a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 69391fb2b60SLogan Gunthorpe struct scatterlist *sg = iod->sgt.sgl; 69491fb2b60SLogan Gunthorpe unsigned int entries = iod->sgt.nents; 695a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 696b0f2853bSChristoph Hellwig int i = 0; 697a7a7cbe3SChaitanya Kulkarni 698a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 699a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 700a7a7cbe3SChaitanya Kulkarni 701b0f2853bSChristoph Hellwig if (entries == 1) { 702a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 703a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 704a7a7cbe3SChaitanya Kulkarni } 705a7a7cbe3SChaitanya Kulkarni 706a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 707a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 708c372cdd1SKeith Busch iod->nr_allocations = 0; 709a7a7cbe3SChaitanya Kulkarni } else { 710a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 711c372cdd1SKeith Busch iod->nr_allocations = 1; 712a7a7cbe3SChaitanya Kulkarni } 713a7a7cbe3SChaitanya Kulkarni 714a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 715a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 716c372cdd1SKeith Busch iod->nr_allocations = -1; 717a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 718a7a7cbe3SChaitanya Kulkarni } 719a7a7cbe3SChaitanya Kulkarni 720*7846c1b5SKeith Busch iod->list[0].sg_list = sg_list; 721a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 722a7a7cbe3SChaitanya Kulkarni 723a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 724a7a7cbe3SChaitanya Kulkarni do { 725a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 726a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 727b0f2853bSChristoph Hellwig } while (--entries > 0); 728a7a7cbe3SChaitanya Kulkarni 729a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 730a7a7cbe3SChaitanya Kulkarni } 731a7a7cbe3SChaitanya Kulkarni 732dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 733dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 734dff824b2SChristoph Hellwig struct bio_vec *bv) 735dff824b2SChristoph Hellwig { 736dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 7376c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 7386c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 739dff824b2SChristoph Hellwig 740dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 741dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 742dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 743dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 744dff824b2SChristoph Hellwig 745dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 746dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 747dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 748a56ea614SLei Rao else 749a56ea614SLei Rao cmnd->dptr.prp2 = 0; 750359c1f88SBaolin Wang return BLK_STS_OK; 751dff824b2SChristoph Hellwig } 752dff824b2SChristoph Hellwig 75329791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 75429791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 75529791057SChristoph Hellwig struct bio_vec *bv) 75629791057SChristoph Hellwig { 75729791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 75829791057SChristoph Hellwig 75929791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 76029791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 76129791057SChristoph Hellwig return BLK_STS_RESOURCE; 76229791057SChristoph Hellwig iod->dma_len = bv->bv_len; 76329791057SChristoph Hellwig 764049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 76529791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 76629791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 76729791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 768359c1f88SBaolin Wang return BLK_STS_OK; 76929791057SChristoph Hellwig } 77029791057SChristoph Hellwig 771fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 772b131c61dSChristoph Hellwig struct nvme_command *cmnd) 77357dacad5SJay Sternberg { 774f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 77570479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 77691fb2b60SLogan Gunthorpe int rc; 77757dacad5SJay Sternberg 778dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 779a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 780dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 781dff824b2SChristoph Hellwig 782dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 7836c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 784dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 785dff824b2SChristoph Hellwig &cmnd->rw, &bv); 78629791057SChristoph Hellwig 787a53232cbSKeith Busch if (nvmeq->qid && sgl_threshold && 788253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 78929791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 79029791057SChristoph Hellwig &cmnd->rw, &bv); 791dff824b2SChristoph Hellwig } 792dff824b2SChristoph Hellwig } 793dff824b2SChristoph Hellwig 794dff824b2SChristoph Hellwig iod->dma_len = 0; 79591fb2b60SLogan Gunthorpe iod->sgt.sgl = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 79691fb2b60SLogan Gunthorpe if (!iod->sgt.sgl) 7979b048119SChristoph Hellwig return BLK_STS_RESOURCE; 79891fb2b60SLogan Gunthorpe sg_init_table(iod->sgt.sgl, blk_rq_nr_phys_segments(req)); 79991fb2b60SLogan Gunthorpe iod->sgt.orig_nents = blk_rq_map_sg(req->q, req, iod->sgt.sgl); 80091fb2b60SLogan Gunthorpe if (!iod->sgt.orig_nents) 801fa073216SChristoph Hellwig goto out_free_sg; 802ba1ca37eSChristoph Hellwig 80391fb2b60SLogan Gunthorpe rc = dma_map_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 80491fb2b60SLogan Gunthorpe DMA_ATTR_NO_WARN); 80591fb2b60SLogan Gunthorpe if (rc) { 80691fb2b60SLogan Gunthorpe if (rc == -EREMOTEIO) 80791fb2b60SLogan Gunthorpe ret = BLK_STS_TARGET; 808fa073216SChristoph Hellwig goto out_free_sg; 80991fb2b60SLogan Gunthorpe } 810ba1ca37eSChristoph Hellwig 811ae582935SKeith Busch iod->use_sgl = nvme_pci_use_sgls(dev, req, iod->sgt.nents); 812955b1b5aSMinwoo Im if (iod->use_sgl) 81391fb2b60SLogan Gunthorpe ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw); 814a7a7cbe3SChaitanya Kulkarni else 815a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8164aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 817fa073216SChristoph Hellwig goto out_unmap_sg; 818fa073216SChristoph Hellwig return BLK_STS_OK; 819fa073216SChristoph Hellwig 820fa073216SChristoph Hellwig out_unmap_sg: 82191fb2b60SLogan Gunthorpe dma_unmap_sgtable(dev->dev, &iod->sgt, rq_dma_dir(req), 0); 822fa073216SChristoph Hellwig out_free_sg: 82391fb2b60SLogan Gunthorpe mempool_free(iod->sgt.sgl, dev->iod_mempool); 824ba1ca37eSChristoph Hellwig return ret; 82557dacad5SJay Sternberg } 82657dacad5SJay Sternberg 8274aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8284aedb705SChristoph Hellwig struct nvme_command *cmnd) 8294aedb705SChristoph Hellwig { 8304aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8314aedb705SChristoph Hellwig 8324aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 8334aedb705SChristoph Hellwig rq_dma_dir(req), 0); 8344aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 8354aedb705SChristoph Hellwig return BLK_STS_IOERR; 8364aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 837359c1f88SBaolin Wang return BLK_STS_OK; 8384aedb705SChristoph Hellwig } 8394aedb705SChristoph Hellwig 84062451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 84162451a2bSJens Axboe { 84262451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84362451a2bSJens Axboe blk_status_t ret; 84462451a2bSJens Axboe 84552da4f3fSKeith Busch iod->aborted = false; 846c372cdd1SKeith Busch iod->nr_allocations = -1; 84791fb2b60SLogan Gunthorpe iod->sgt.nents = 0; 84862451a2bSJens Axboe 84962451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 85062451a2bSJens Axboe if (ret) 85162451a2bSJens Axboe return ret; 85262451a2bSJens Axboe 85362451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 85462451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 85562451a2bSJens Axboe if (ret) 85662451a2bSJens Axboe goto out_free_cmd; 85762451a2bSJens Axboe } 85862451a2bSJens Axboe 85962451a2bSJens Axboe if (blk_integrity_rq(req)) { 86062451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 86162451a2bSJens Axboe if (ret) 86262451a2bSJens Axboe goto out_unmap_data; 86362451a2bSJens Axboe } 86462451a2bSJens Axboe 8656887fc64SSagi Grimberg nvme_start_request(req); 86662451a2bSJens Axboe return BLK_STS_OK; 86762451a2bSJens Axboe out_unmap_data: 86862451a2bSJens Axboe nvme_unmap_data(dev, req); 86962451a2bSJens Axboe out_free_cmd: 87062451a2bSJens Axboe nvme_cleanup_cmd(req); 87162451a2bSJens Axboe return ret; 87262451a2bSJens Axboe } 87362451a2bSJens Axboe 87457dacad5SJay Sternberg /* 87557dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 87657dacad5SJay Sternberg */ 877fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 87857dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 87957dacad5SJay Sternberg { 88057dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 88157dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 88257dacad5SJay Sternberg struct request *req = bd->rq; 8839b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 884ebe6d874SChristoph Hellwig blk_status_t ret; 88557dacad5SJay Sternberg 886d1f06f4aSJens Axboe /* 887d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 888d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 889d1f06f4aSJens Axboe */ 8904e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 891d1f06f4aSJens Axboe return BLK_STS_IOERR; 892d1f06f4aSJens Axboe 89362451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 894d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 895d4060d2bSTao Chiu 89662451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 89762451a2bSJens Axboe if (unlikely(ret)) 898f4800d6dSChristoph Hellwig return ret; 8993233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9003233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9013233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9023233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 903fc17b653SChristoph Hellwig return BLK_STS_OK; 90457dacad5SJay Sternberg } 90557dacad5SJay Sternberg 906d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 907d62cbcf6SJens Axboe { 908d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 909d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 910d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 911d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 912d62cbcf6SJens Axboe 913d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 914d62cbcf6SJens Axboe } 915d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 916d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 917d62cbcf6SJens Axboe } 918d62cbcf6SJens Axboe 919d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 920d62cbcf6SJens Axboe { 921d62cbcf6SJens Axboe /* 922d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 923d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 924d62cbcf6SJens Axboe */ 925d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 926d62cbcf6SJens Axboe return false; 927d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 928d62cbcf6SJens Axboe return false; 929d62cbcf6SJens Axboe 930d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 931d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 932d62cbcf6SJens Axboe } 933d62cbcf6SJens Axboe 934d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 935d62cbcf6SJens Axboe { 9366bfec799SKeith Busch struct request *req, *next, *prev = NULL; 937d62cbcf6SJens Axboe struct request *requeue_list = NULL; 938d62cbcf6SJens Axboe 9396bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 940d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 941d62cbcf6SJens Axboe 942d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 943d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 9446bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 9456bfec799SKeith Busch 9466bfec799SKeith Busch req = prev; 9476bfec799SKeith Busch if (!req) 9486bfec799SKeith Busch continue; 949d62cbcf6SJens Axboe } 950d62cbcf6SJens Axboe 9516bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 952d62cbcf6SJens Axboe /* detach rest of list, and submit */ 9536bfec799SKeith Busch req->rq_next = NULL; 954d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 9556bfec799SKeith Busch *rqlist = next; 9566bfec799SKeith Busch prev = NULL; 9576bfec799SKeith Busch } else 9586bfec799SKeith Busch prev = req; 959d62cbcf6SJens Axboe } 960d62cbcf6SJens Axboe 961d62cbcf6SJens Axboe *rqlist = requeue_list; 962d62cbcf6SJens Axboe } 963d62cbcf6SJens Axboe 964c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 965eee417b0SChristoph Hellwig { 966a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 967a53232cbSKeith Busch struct nvme_dev *dev = nvmeq->dev; 968eee417b0SChristoph Hellwig 969a53232cbSKeith Busch if (blk_integrity_rq(req)) { 970a53232cbSKeith Busch struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 971a53232cbSKeith Busch 9724aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 9734aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 974a53232cbSKeith Busch } 975a53232cbSKeith Busch 976b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 9774aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 978c234a653SJens Axboe } 979c234a653SJens Axboe 980c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 981c234a653SJens Axboe { 982c234a653SJens Axboe nvme_pci_unmap_rq(req); 98377f02a7aSChristoph Hellwig nvme_complete_rq(req); 98457dacad5SJay Sternberg } 98557dacad5SJay Sternberg 986c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 987c234a653SJens Axboe { 988c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 989c234a653SJens Axboe } 990c234a653SJens Axboe 991d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 992750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 993d783e0bdSMarta Rybczynska { 99474943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 99574943d45SKeith Busch 99674943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 997d783e0bdSMarta Rybczynska } 998d783e0bdSMarta Rybczynska 999eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 100057dacad5SJay Sternberg { 1001eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 100257dacad5SJay Sternberg 1003eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1004eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1005eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1006eb281c82SSagi Grimberg } 1007adf68f21SChristoph Hellwig 1008cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1009cfa27356SChristoph Hellwig { 1010cfa27356SChristoph Hellwig if (!nvmeq->qid) 1011cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1012cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1013cfa27356SChristoph Hellwig } 1014cfa27356SChristoph Hellwig 1015c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1016c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 101757dacad5SJay Sternberg { 101874943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 101962df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 102057dacad5SJay Sternberg struct request *req; 1021adf68f21SChristoph Hellwig 1022adf68f21SChristoph Hellwig /* 1023adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1024adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1025adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1026adf68f21SChristoph Hellwig * for them but rather special case them here. 1027adf68f21SChristoph Hellwig */ 102862df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10297bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 103083a12fb7SSagi Grimberg cqe->status, &cqe->result); 1031a0fa9647SJens Axboe return; 103257dacad5SJay Sternberg } 103357dacad5SJay Sternberg 1034e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 103550b7c243SXianting Tian if (unlikely(!req)) { 103650b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 103750b7c243SXianting Tian "invalid id %d completed on queue %d\n", 103862df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 103950b7c243SXianting Tian return; 104050b7c243SXianting Tian } 104150b7c243SXianting Tian 1042604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1043c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1044c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1045c234a653SJens Axboe nvme_pci_complete_batch)) 1046ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 104783a12fb7SSagi Grimberg } 104857dacad5SJay Sternberg 10495cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 10505cb525c8SJens Axboe { 1051a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1052a8de6639SAlexey Dobriyan 1053a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1054920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1055e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1056a8de6639SAlexey Dobriyan } else { 1057a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1058920d13a8SSagi Grimberg } 1059a0fa9647SJens Axboe } 1060a0fa9647SJens Axboe 1061c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1062c234a653SJens Axboe struct io_comp_batch *iob) 1063a0fa9647SJens Axboe { 10641052b8acSJens Axboe int found = 0; 106583a12fb7SSagi Grimberg 10661052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 10671052b8acSJens Axboe found++; 1068b69e2ef2SKeith Busch /* 1069b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1070b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1071b69e2ef2SKeith Busch */ 1072b69e2ef2SKeith Busch dma_rmb(); 1073c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 10745cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 107557dacad5SJay Sternberg } 107657dacad5SJay Sternberg 1077324b494cSKeith Busch if (found) 1078eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 10795cb525c8SJens Axboe return found; 108057dacad5SJay Sternberg } 108157dacad5SJay Sternberg 108257dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 108357dacad5SJay Sternberg { 108457dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10854f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 10865cb525c8SJens Axboe 10874f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 10884f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 10894f502245SJens Axboe nvme_pci_complete_batch(&iob); 109005fae499SChaitanya Kulkarni return IRQ_HANDLED; 10914f502245SJens Axboe } 109205fae499SChaitanya Kulkarni return IRQ_NONE; 109357dacad5SJay Sternberg } 109457dacad5SJay Sternberg 109557dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 109657dacad5SJay Sternberg { 109757dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 10984e523547SBaolin Wang 1099750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 110057dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1101d783e0bdSMarta Rybczynska return IRQ_NONE; 110257dacad5SJay Sternberg } 110357dacad5SJay Sternberg 11040b2a8a9fSChristoph Hellwig /* 1105fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11060b2a8a9fSChristoph Hellwig * Can be called from any context. 11070b2a8a9fSChristoph Hellwig */ 1108fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1109a0fa9647SJens Axboe { 11103a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1111a0fa9647SJens Axboe 1112fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1113fa059b85SKeith Busch 11143a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1115c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11163a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 111791a509f8SChristoph Hellwig } 1118442e19b7SSagi Grimberg 11195a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11207776db1cSKeith Busch { 11217776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1122dabcefabSJens Axboe bool found; 1123dabcefabSJens Axboe 1124dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1125dabcefabSJens Axboe return 0; 1126dabcefabSJens Axboe 11273a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1128c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11293a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1130dabcefabSJens Axboe 1131dabcefabSJens Axboe return found; 1132dabcefabSJens Axboe } 1133dabcefabSJens Axboe 1134ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 113557dacad5SJay Sternberg { 1136f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1137147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1138f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 113957dacad5SJay Sternberg 114057dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1141ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 11423233b94cSJens Axboe 11433233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 11443233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 11453233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 11463233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 114757dacad5SJay Sternberg } 114857dacad5SJay Sternberg 114957dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 115057dacad5SJay Sternberg { 1151f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 115257dacad5SJay Sternberg 115357dacad5SJay Sternberg c.delete_queue.opcode = opcode; 115457dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 115557dacad5SJay Sternberg 11561c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 115757dacad5SJay Sternberg } 115857dacad5SJay Sternberg 115957dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1160a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 116157dacad5SJay Sternberg { 1162f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 11634b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 11644b04cc6aSJens Axboe 11657c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 11664b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 116757dacad5SJay Sternberg 116857dacad5SJay Sternberg /* 116916772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 117057dacad5SJay Sternberg * is attached to the request. 117157dacad5SJay Sternberg */ 117257dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 117357dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 117457dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 117557dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 117657dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1177a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 117857dacad5SJay Sternberg 11791c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 118057dacad5SJay Sternberg } 118157dacad5SJay Sternberg 118257dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 118357dacad5SJay Sternberg struct nvme_queue *nvmeq) 118457dacad5SJay Sternberg { 11859abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1186f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 118781c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 118857dacad5SJay Sternberg 118957dacad5SJay Sternberg /* 11909abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 11919abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 11929abd68efSJens Axboe * URGENT. 11939abd68efSJens Axboe */ 11949abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 11959abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 11969abd68efSJens Axboe 11979abd68efSJens Axboe /* 119816772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 119957dacad5SJay Sternberg * is attached to the request. 120057dacad5SJay Sternberg */ 120157dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 120257dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 120357dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 120457dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 120557dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 120657dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 120757dacad5SJay Sternberg 12081c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 120957dacad5SJay Sternberg } 121057dacad5SJay Sternberg 121157dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 121257dacad5SJay Sternberg { 121357dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 121457dacad5SJay Sternberg } 121557dacad5SJay Sternberg 121657dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 121757dacad5SJay Sternberg { 121857dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 121957dacad5SJay Sternberg } 122057dacad5SJay Sternberg 1221de671d61SJens Axboe static enum rq_end_io_ret abort_endio(struct request *req, blk_status_t error) 122257dacad5SJay Sternberg { 1223a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 122457dacad5SJay Sternberg 122527fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 122627fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1227e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1228e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 1229de671d61SJens Axboe return RQ_END_IO_NONE; 123057dacad5SJay Sternberg } 123157dacad5SJay Sternberg 1232b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1233b2a0eb1aSKeith Busch { 1234b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1235b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1236b2a0eb1aSKeith Busch */ 1237b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1238b2a0eb1aSKeith Busch 1239ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1240ad70062cSJianchao Wang switch (dev->ctrl.state) { 1241ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1242ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1243b2a0eb1aSKeith Busch return false; 1244ad70062cSJianchao Wang default: 1245ad70062cSJianchao Wang break; 1246ad70062cSJianchao Wang } 1247b2a0eb1aSKeith Busch 1248b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1249b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1250b2a0eb1aSKeith Busch */ 1251b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1252b2a0eb1aSKeith Busch return false; 1253b2a0eb1aSKeith Busch 1254b2a0eb1aSKeith Busch return true; 1255b2a0eb1aSKeith Busch } 1256b2a0eb1aSKeith Busch 1257b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1258b2a0eb1aSKeith Busch { 1259b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1260b2a0eb1aSKeith Busch u16 pci_status; 1261b2a0eb1aSKeith Busch int result; 1262b2a0eb1aSKeith Busch 1263b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1264b2a0eb1aSKeith Busch &pci_status); 1265b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1266b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1267b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1268b2a0eb1aSKeith Busch csts, pci_status); 1269b2a0eb1aSKeith Busch else 1270b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1271b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1272b2a0eb1aSKeith Busch csts, result); 12734641a8e6SKeith Busch 12744641a8e6SKeith Busch if (csts != ~0) 12754641a8e6SKeith Busch return; 12764641a8e6SKeith Busch 12774641a8e6SKeith Busch dev_warn(dev->ctrl.device, 12784641a8e6SKeith Busch "Does your device have a faulty power saving mode enabled?\n"); 12794641a8e6SKeith Busch dev_warn(dev->ctrl.device, 12804641a8e6SKeith Busch "Try \"nvme_core.default_ps_max_latency_us=0 pcie_aspm=off\" and report a bug\n"); 1281b2a0eb1aSKeith Busch } 1282b2a0eb1aSKeith Busch 12839bdb4833SJohn Garry static enum blk_eh_timer_return nvme_timeout(struct request *req) 128457dacad5SJay Sternberg { 1285f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1286a53232cbSKeith Busch struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 128757dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 128857dacad5SJay Sternberg struct request *abort_req; 1289f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1290b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1291b2a0eb1aSKeith Busch 1292651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1293651438bbSWen Xiong * the recovery mechanism will surely fail. 1294651438bbSWen Xiong */ 1295651438bbSWen Xiong mb(); 1296651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1297651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1298651438bbSWen Xiong 1299b2a0eb1aSKeith Busch /* 1300b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1301b2a0eb1aSKeith Busch */ 1302b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1303b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1304b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1305d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1306db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1307b2a0eb1aSKeith Busch } 130857dacad5SJay Sternberg 130931c7c7d2SChristoph Hellwig /* 13107776db1cSKeith Busch * Did we miss an interrupt? 13117776db1cSKeith Busch */ 1312fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13135a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1314fa059b85SKeith Busch else 1315bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1316fa059b85SKeith Busch 13171c584208SKeith Busch if (blk_mq_rq_state(req) != MQ_RQ_IN_FLIGHT) { 13187776db1cSKeith Busch dev_warn(dev->ctrl.device, 13197776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13207776db1cSKeith Busch req->tag, nvmeq->qid); 1321db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13227776db1cSKeith Busch } 13237776db1cSKeith Busch 13247776db1cSKeith Busch /* 1325fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1326fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1327fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1328db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1329fd634f41SChristoph Hellwig */ 13304244140dSKeith Busch switch (dev->ctrl.state) { 13314244140dSKeith Busch case NVME_CTRL_CONNECTING: 13322036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1333df561f66SGustavo A. R. Silva fallthrough; 13342036f726SKeith Busch case NVME_CTRL_DELETING: 1335b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1336fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1337fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 133827fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13397ad92f65STong Zhang nvme_dev_disable(dev, true); 1340db8c48e4SChristoph Hellwig return BLK_EH_DONE; 134139a9dd81SKeith Busch case NVME_CTRL_RESETTING: 134239a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13434244140dSKeith Busch default: 13444244140dSKeith Busch break; 1345fd634f41SChristoph Hellwig } 1346fd634f41SChristoph Hellwig 1347fd634f41SChristoph Hellwig /* 1348e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1349e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1350e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 135131c7c7d2SChristoph Hellwig */ 1352f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 13531b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 135457dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 135557dacad5SJay Sternberg req->tag, nvmeq->qid); 13567ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1357a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1358d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1359e1569a16SKeith Busch 1360db8c48e4SChristoph Hellwig return BLK_EH_DONE; 136157dacad5SJay Sternberg } 136257dacad5SJay Sternberg 1363e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1364e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1365e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1366e7a2a87dSChristoph Hellwig } 136752da4f3fSKeith Busch iod->aborted = true; 136857dacad5SJay Sternberg 136957dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 137085f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 137157dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 137257dacad5SJay Sternberg 13731b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 137486141440SChristoph Hellwig "I/O %d (%s) QID %d timeout, aborting\n", 137586141440SChristoph Hellwig req->tag, 137686141440SChristoph Hellwig nvme_get_opcode_str(nvme_req(req)->cmd->common.opcode), 137786141440SChristoph Hellwig nvmeq->qid); 1378e7a2a87dSChristoph Hellwig 1379e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 138039dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 13816bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 13826bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 138331c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 138457dacad5SJay Sternberg } 1385e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 138657dacad5SJay Sternberg 1387e2e53086SChristoph Hellwig abort_req->end_io = abort_endio; 1388e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1389e2e53086SChristoph Hellwig blk_execute_rq_nowait(abort_req, false); 139057dacad5SJay Sternberg 139157dacad5SJay Sternberg /* 139257dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 139357dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 139457dacad5SJay Sternberg * as the device then is in a faulty state. 139557dacad5SJay Sternberg */ 139657dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 139757dacad5SJay Sternberg } 139857dacad5SJay Sternberg 139957dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 140057dacad5SJay Sternberg { 14018a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 140257dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 140363223078SChristoph Hellwig if (!nvmeq->sq_cmds) 140463223078SChristoph Hellwig return; 14050f238ff5SLogan Gunthorpe 140663223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 140788a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14088a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 140963223078SChristoph Hellwig } else { 14108a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 141163223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14120f238ff5SLogan Gunthorpe } 141357dacad5SJay Sternberg } 141457dacad5SJay Sternberg 141557dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 141657dacad5SJay Sternberg { 141757dacad5SJay Sternberg int i; 141857dacad5SJay Sternberg 1419d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1420d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1421147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 142257dacad5SJay Sternberg } 142357dacad5SJay Sternberg } 142457dacad5SJay Sternberg 142510981f23SChristoph Hellwig static void nvme_suspend_queue(struct nvme_dev *dev, unsigned int qid) 142657dacad5SJay Sternberg { 142710981f23SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[qid]; 142810981f23SChristoph Hellwig 14294e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 143010981f23SChristoph Hellwig return; 143157dacad5SJay Sternberg 14324e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1433d1f06f4aSJens Axboe mb(); 143457dacad5SJay Sternberg 14354e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14361c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14379f27bd70SChristoph Hellwig nvme_quiesce_admin_queue(&nvmeq->dev->ctrl); 14387c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 143910981f23SChristoph Hellwig pci_free_irq(to_pci_dev(dev->dev), nvmeq->cq_vector, nvmeq); 144057dacad5SJay Sternberg } 144157dacad5SJay Sternberg 14428fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 14438fae268bSKeith Busch { 14448fae268bSKeith Busch int i; 14458fae268bSKeith Busch 14468fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 144710981f23SChristoph Hellwig nvme_suspend_queue(dev, i); 144857dacad5SJay Sternberg } 144957dacad5SJay Sternberg 1450fa46c6fbSKeith Busch /* 1451fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 14529210c075SDongli Zhang * that can check this device's completion queues have synced, except 14539210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 14549210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1455fa46c6fbSKeith Busch */ 1456fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1457fa46c6fbSKeith Busch { 1458fa46c6fbSKeith Busch int i; 1459fa46c6fbSKeith Busch 14609210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 14619210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1462c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 14639210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 14649210c075SDongli Zhang } 1465fa46c6fbSKeith Busch } 1466fa46c6fbSKeith Busch 146757dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 146857dacad5SJay Sternberg int entry_size) 146957dacad5SJay Sternberg { 147057dacad5SJay Sternberg int q_depth = dev->q_depth; 14715fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 14726c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 147357dacad5SJay Sternberg 147457dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 147557dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 14764e523547SBaolin Wang 14776c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 147857dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 147957dacad5SJay Sternberg 148057dacad5SJay Sternberg /* 148157dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 148257dacad5SJay Sternberg * would be better to map queues in system memory with the 148357dacad5SJay Sternberg * original depth 148457dacad5SJay Sternberg */ 148557dacad5SJay Sternberg if (q_depth < 64) 148657dacad5SJay Sternberg return -ENOMEM; 148757dacad5SJay Sternberg } 148857dacad5SJay Sternberg 148957dacad5SJay Sternberg return q_depth; 149057dacad5SJay Sternberg } 149157dacad5SJay Sternberg 149257dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 14938a1d09a6SBenjamin Herrenschmidt int qid) 149457dacad5SJay Sternberg { 14950f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1496815c6704SKeith Busch 14970f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 14988a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1499bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15000f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15010f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 150263223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 150363223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 150463223078SChristoph Hellwig return 0; 150563223078SChristoph Hellwig } 1506bfac8e9fSAlan Mikhak 15078a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1508bfac8e9fSAlan Mikhak } 15090f238ff5SLogan Gunthorpe } 15100f238ff5SLogan Gunthorpe 15118a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 151257dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 151357dacad5SJay Sternberg if (!nvmeq->sq_cmds) 151457dacad5SJay Sternberg return -ENOMEM; 151557dacad5SJay Sternberg return 0; 151657dacad5SJay Sternberg } 151757dacad5SJay Sternberg 1518a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 151957dacad5SJay Sternberg { 1520147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 152157dacad5SJay Sternberg 152262314e40SKeith Busch if (dev->ctrl.queue_count > qid) 152362314e40SKeith Busch return 0; 152457dacad5SJay Sternberg 1525c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15268a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15278a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 152857dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 152957dacad5SJay Sternberg if (!nvmeq->cqes) 153057dacad5SJay Sternberg goto free_nvmeq; 153157dacad5SJay Sternberg 15328a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 153357dacad5SJay Sternberg goto free_cqdma; 153457dacad5SJay Sternberg 153557dacad5SJay Sternberg nvmeq->dev = dev; 15361ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 15373a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 153857dacad5SJay Sternberg nvmeq->cq_head = 0; 153957dacad5SJay Sternberg nvmeq->cq_phase = 1; 154057dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 154157dacad5SJay Sternberg nvmeq->qid = qid; 1542d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 154357dacad5SJay Sternberg 1544147b27e4SSagi Grimberg return 0; 154557dacad5SJay Sternberg 154657dacad5SJay Sternberg free_cqdma: 15478a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 154857dacad5SJay Sternberg nvmeq->cq_dma_addr); 154957dacad5SJay Sternberg free_nvmeq: 1550147b27e4SSagi Grimberg return -ENOMEM; 155157dacad5SJay Sternberg } 155257dacad5SJay Sternberg 1553dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 155457dacad5SJay Sternberg { 15550ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 15560ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 15570ff199cbSChristoph Hellwig 15580ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 15590ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 15600ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15610ff199cbSChristoph Hellwig } else { 15620ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 15630ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 15640ff199cbSChristoph Hellwig } 156557dacad5SJay Sternberg } 156657dacad5SJay Sternberg 156757dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 156857dacad5SJay Sternberg { 156957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 157057dacad5SJay Sternberg 157157dacad5SJay Sternberg nvmeq->sq_tail = 0; 157238210800SKeith Busch nvmeq->last_sq_tail = 0; 157357dacad5SJay Sternberg nvmeq->cq_head = 0; 157457dacad5SJay Sternberg nvmeq->cq_phase = 1; 157557dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 15768a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1577f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 157857dacad5SJay Sternberg dev->online_queues++; 15793a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 158057dacad5SJay Sternberg } 158157dacad5SJay Sternberg 1582e4b9852aSCasey Chen /* 1583e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1584e4b9852aSCasey Chen */ 1585e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1586e4b9852aSCasey Chen { 1587e4b9852aSCasey Chen /* 1588e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1589e4b9852aSCasey Chen */ 1590e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1591e4b9852aSCasey Chen return -ENODEV; 1592e4b9852aSCasey Chen 1593e4b9852aSCasey Chen /* 1594e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1595e4b9852aSCasey Chen */ 1596e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1597e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1598e4b9852aSCasey Chen return -ENODEV; 1599e4b9852aSCasey Chen } 1600e4b9852aSCasey Chen 1601e4b9852aSCasey Chen return 0; 1602e4b9852aSCasey Chen } 1603e4b9852aSCasey Chen 16044b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 160557dacad5SJay Sternberg { 160657dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 160757dacad5SJay Sternberg int result; 16087c349ddeSKeith Busch u16 vector = 0; 160957dacad5SJay Sternberg 1610d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1611d1ed6aa1SChristoph Hellwig 161222b55601SKeith Busch /* 161322b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 161422b55601SKeith Busch * has only one vector available. 161522b55601SKeith Busch */ 16164b04cc6aSJens Axboe if (!polled) 1617a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16184b04cc6aSJens Axboe else 16197c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16204b04cc6aSJens Axboe 1621a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1622ded45505SKeith Busch if (result) 1623ded45505SKeith Busch return result; 162457dacad5SJay Sternberg 162557dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 162657dacad5SJay Sternberg if (result < 0) 1627ded45505SKeith Busch return result; 1628c80b36cdSEdmund Nadolski if (result) 162957dacad5SJay Sternberg goto release_cq; 163057dacad5SJay Sternberg 1631a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 16324b04cc6aSJens Axboe 1633e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1634e4b9852aSCasey Chen if (result) 1635e4b9852aSCasey Chen return result; 1636e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 16377c349ddeSKeith Busch if (!polled) { 1638dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 163957dacad5SJay Sternberg if (result < 0) 164057dacad5SJay Sternberg goto release_sq; 16414b04cc6aSJens Axboe } 164257dacad5SJay Sternberg 16434e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1644e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 164557dacad5SJay Sternberg return result; 164657dacad5SJay Sternberg 164757dacad5SJay Sternberg release_sq: 1648f25a2dfcSJianchao Wang dev->online_queues--; 1649e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 165057dacad5SJay Sternberg adapter_delete_sq(dev, qid); 165157dacad5SJay Sternberg release_cq: 165257dacad5SJay Sternberg adapter_delete_cq(dev, qid); 165357dacad5SJay Sternberg return result; 165457dacad5SJay Sternberg } 165557dacad5SJay Sternberg 1656f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 165757dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 165877f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 165957dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1660e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 166157dacad5SJay Sternberg .timeout = nvme_timeout, 166257dacad5SJay Sternberg }; 166357dacad5SJay Sternberg 1664f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1665376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1666d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1667376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1668376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1669376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1670e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1671376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1672376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1673c6d962aeSChristoph Hellwig .poll = nvme_poll, 1674dabcefabSJens Axboe }; 1675dabcefabSJens Axboe 167657dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 167757dacad5SJay Sternberg { 16781c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 167969d9a99cSKeith Busch /* 168069d9a99cSKeith Busch * If the controller was reset during removal, it's possible 168169d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 168269d9a99cSKeith Busch * queue to flush these to completion. 168369d9a99cSKeith Busch */ 16849f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 16850da7feaaSChristoph Hellwig nvme_remove_admin_tag_set(&dev->ctrl); 168657dacad5SJay Sternberg } 168757dacad5SJay Sternberg } 168857dacad5SJay Sternberg 168997f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 169097f6ef64SXu Yu { 169197f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 169297f6ef64SXu Yu } 169397f6ef64SXu Yu 169497f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 169597f6ef64SXu Yu { 169697f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 169797f6ef64SXu Yu 169897f6ef64SXu Yu if (size <= dev->bar_mapped_size) 169997f6ef64SXu Yu return 0; 170097f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 170197f6ef64SXu Yu return -ENOMEM; 170297f6ef64SXu Yu if (dev->bar) 170397f6ef64SXu Yu iounmap(dev->bar); 170497f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 170597f6ef64SXu Yu if (!dev->bar) { 170697f6ef64SXu Yu dev->bar_mapped_size = 0; 170797f6ef64SXu Yu return -ENOMEM; 170897f6ef64SXu Yu } 170997f6ef64SXu Yu dev->bar_mapped_size = size; 171097f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 171197f6ef64SXu Yu 171297f6ef64SXu Yu return 0; 171397f6ef64SXu Yu } 171497f6ef64SXu Yu 171501ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 171657dacad5SJay Sternberg { 171757dacad5SJay Sternberg int result; 171857dacad5SJay Sternberg u32 aqa; 171957dacad5SJay Sternberg struct nvme_queue *nvmeq; 172057dacad5SJay Sternberg 172197f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 172297f6ef64SXu Yu if (result < 0) 172397f6ef64SXu Yu return result; 172497f6ef64SXu Yu 17258ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 172620d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 172757dacad5SJay Sternberg 17287a67cbeaSChristoph Hellwig if (dev->subsystem && 17297a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 17307a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 173157dacad5SJay Sternberg 1732285b6e9bSChristoph Hellwig /* 1733285b6e9bSChristoph Hellwig * If the device has been passed off to us in an enabled state, just 1734285b6e9bSChristoph Hellwig * clear the enabled bit. The spec says we should set the 'shutdown 1735285b6e9bSChristoph Hellwig * notification bits', but doing so may cause the device to complete 1736285b6e9bSChristoph Hellwig * commands to the admin queue ... and we don't know what memory that 1737285b6e9bSChristoph Hellwig * might be pointing at! 1738285b6e9bSChristoph Hellwig */ 1739285b6e9bSChristoph Hellwig result = nvme_disable_ctrl(&dev->ctrl, false); 174057dacad5SJay Sternberg if (result < 0) 174157dacad5SJay Sternberg return result; 174257dacad5SJay Sternberg 1743a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1744147b27e4SSagi Grimberg if (result) 1745147b27e4SSagi Grimberg return result; 174657dacad5SJay Sternberg 1747635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1748635333e4SMax Gurtovoy 1749147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 175057dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 175157dacad5SJay Sternberg aqa |= aqa << 16; 175257dacad5SJay Sternberg 17537a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 17547a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 17557a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 175657dacad5SJay Sternberg 1757c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 175857dacad5SJay Sternberg if (result) 1759d4875622SKeith Busch return result; 176057dacad5SJay Sternberg 176157dacad5SJay Sternberg nvmeq->cq_vector = 0; 1762161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1763dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 176457dacad5SJay Sternberg if (result) { 17657c349ddeSKeith Busch dev->online_queues--; 1766d4875622SKeith Busch return result; 176757dacad5SJay Sternberg } 176857dacad5SJay Sternberg 17694e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 177057dacad5SJay Sternberg return result; 177157dacad5SJay Sternberg } 177257dacad5SJay Sternberg 1773749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 177457dacad5SJay Sternberg { 17754b04cc6aSJens Axboe unsigned i, max, rw_queues; 1776749941f2SChristoph Hellwig int ret = 0; 177757dacad5SJay Sternberg 1778d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1779a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1780749941f2SChristoph Hellwig ret = -ENOMEM; 178157dacad5SJay Sternberg break; 1782749941f2SChristoph Hellwig } 1783749941f2SChristoph Hellwig } 178457dacad5SJay Sternberg 1785d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1786e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1787e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1788e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 17894b04cc6aSJens Axboe } else { 17904b04cc6aSJens Axboe rw_queues = max; 17914b04cc6aSJens Axboe } 17924b04cc6aSJens Axboe 1793949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 17944b04cc6aSJens Axboe bool polled = i > rw_queues; 17954b04cc6aSJens Axboe 17964b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1797d4875622SKeith Busch if (ret) 179857dacad5SJay Sternberg break; 179957dacad5SJay Sternberg } 180057dacad5SJay Sternberg 1801749941f2SChristoph Hellwig /* 1802749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 18038adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 18048adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1805749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1806749941f2SChristoph Hellwig */ 1807749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 180857dacad5SJay Sternberg } 180957dacad5SJay Sternberg 181088de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 181157dacad5SJay Sternberg { 181288de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 181388de4598SChristoph Hellwig 181488de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 181588de4598SChristoph Hellwig } 181688de4598SChristoph Hellwig 181788de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 181888de4598SChristoph Hellwig { 181988de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 182088de4598SChristoph Hellwig } 182188de4598SChristoph Hellwig 1822f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 182357dacad5SJay Sternberg { 182488de4598SChristoph Hellwig u64 size, offset; 182557dacad5SJay Sternberg resource_size_t bar_size; 182657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 18278969f1f8SChristoph Hellwig int bar; 182857dacad5SJay Sternberg 18299fe5c59fSKeith Busch if (dev->cmb_size) 18309fe5c59fSKeith Busch return; 18319fe5c59fSKeith Busch 183220d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 183320d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 183420d3bb92SKlaus Jensen 18357a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1836f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1837f65efd6dSChristoph Hellwig return; 1838202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 183957dacad5SJay Sternberg 184088de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 184188de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 18428969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 18438969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 184457dacad5SJay Sternberg 184557dacad5SJay Sternberg if (offset > bar_size) 1846f65efd6dSChristoph Hellwig return; 184757dacad5SJay Sternberg 184857dacad5SJay Sternberg /* 184920d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 185020d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 185120d3bb92SKlaus Jensen */ 185220d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 185320d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 185420d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 185520d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 185620d3bb92SKlaus Jensen } 185720d3bb92SKlaus Jensen 185820d3bb92SKlaus Jensen /* 185957dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 186057dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 186157dacad5SJay Sternberg * the reported size of the BAR 186257dacad5SJay Sternberg */ 186357dacad5SJay Sternberg if (size > bar_size - offset) 186457dacad5SJay Sternberg size = bar_size - offset; 186557dacad5SJay Sternberg 18660f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 18670f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 18680f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1869f65efd6dSChristoph Hellwig return; 18700f238ff5SLogan Gunthorpe } 18710f238ff5SLogan Gunthorpe 187257dacad5SJay Sternberg dev->cmb_size = size; 18730f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 18740f238ff5SLogan Gunthorpe 18750f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 18760f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 18770f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 187857dacad5SJay Sternberg } 187957dacad5SJay Sternberg 188087ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 188157dacad5SJay Sternberg { 18826c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 18834033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1884f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 188587ad72a5SChristoph Hellwig int ret; 188687ad72a5SChristoph Hellwig 188787ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 188887ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 188987ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 18906c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 189187ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 189287ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 189387ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 189487ad72a5SChristoph Hellwig 189587ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 189687ad72a5SChristoph Hellwig if (ret) { 189787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 189887ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 189987ad72a5SChristoph Hellwig ret, bits); 1900a5df5e79SKeith Busch } else 1901a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1902a5df5e79SKeith Busch 190387ad72a5SChristoph Hellwig return ret; 190487ad72a5SChristoph Hellwig } 190587ad72a5SChristoph Hellwig 190687ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 190787ad72a5SChristoph Hellwig { 190887ad72a5SChristoph Hellwig int i; 190987ad72a5SChristoph Hellwig 191087ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 191187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 19126c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 191387ad72a5SChristoph Hellwig 1914cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 1915cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 1916cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 191787ad72a5SChristoph Hellwig } 191887ad72a5SChristoph Hellwig 191987ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 192087ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 19214033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 19224033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 19234033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 192487ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 19257e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 192687ad72a5SChristoph Hellwig } 192787ad72a5SChristoph Hellwig 192892dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 192992dc6895SChristoph Hellwig u32 chunk_size) 193087ad72a5SChristoph Hellwig { 193187ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 193292dc6895SChristoph Hellwig u32 max_entries, len; 19334033f35dSChristoph Hellwig dma_addr_t descs_dma; 19342ee0e4edSDan Carpenter int i = 0; 193587ad72a5SChristoph Hellwig void **bufs; 19366fbcde66SMinwoo Im u64 size, tmp; 193787ad72a5SChristoph Hellwig 193887ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 193987ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 194087ad72a5SChristoph Hellwig max_entries = tmp; 1941044a9df1SChristoph Hellwig 1942044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 1943044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 1944044a9df1SChristoph Hellwig 1945750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 19464033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 194787ad72a5SChristoph Hellwig if (!descs) 194887ad72a5SChristoph Hellwig goto out; 194987ad72a5SChristoph Hellwig 195087ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 195187ad72a5SChristoph Hellwig if (!bufs) 195287ad72a5SChristoph Hellwig goto out_free_descs; 195387ad72a5SChristoph Hellwig 1954244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 195587ad72a5SChristoph Hellwig dma_addr_t dma_addr; 195687ad72a5SChristoph Hellwig 195750cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 195887ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 195987ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 196087ad72a5SChristoph Hellwig if (!bufs[i]) 196187ad72a5SChristoph Hellwig break; 196287ad72a5SChristoph Hellwig 196387ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 19646c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 196587ad72a5SChristoph Hellwig i++; 196687ad72a5SChristoph Hellwig } 196787ad72a5SChristoph Hellwig 196892dc6895SChristoph Hellwig if (!size) 196987ad72a5SChristoph Hellwig goto out_free_bufs; 197087ad72a5SChristoph Hellwig 197187ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 197287ad72a5SChristoph Hellwig dev->host_mem_size = size; 197387ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 19744033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 197587ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 197687ad72a5SChristoph Hellwig return 0; 197787ad72a5SChristoph Hellwig 197887ad72a5SChristoph Hellwig out_free_bufs: 197987ad72a5SChristoph Hellwig while (--i >= 0) { 19806c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 198187ad72a5SChristoph Hellwig 1982cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 1983cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 1984cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 198587ad72a5SChristoph Hellwig } 198687ad72a5SChristoph Hellwig 198787ad72a5SChristoph Hellwig kfree(bufs); 198887ad72a5SChristoph Hellwig out_free_descs: 19894033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 19904033f35dSChristoph Hellwig descs_dma); 199187ad72a5SChristoph Hellwig out: 199287ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 199387ad72a5SChristoph Hellwig return -ENOMEM; 199487ad72a5SChristoph Hellwig } 199587ad72a5SChristoph Hellwig 199692dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 199792dc6895SChristoph Hellwig { 19989dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 19999dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20009dc54a0dSChaitanya Kulkarni u64 chunk_size; 200192dc6895SChristoph Hellwig 200292dc6895SChristoph Hellwig /* start big and work our way down */ 20039dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 200492dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 200592dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 200692dc6895SChristoph Hellwig return 0; 200792dc6895SChristoph Hellwig nvme_free_host_mem(dev); 200892dc6895SChristoph Hellwig } 200992dc6895SChristoph Hellwig } 201092dc6895SChristoph Hellwig 201192dc6895SChristoph Hellwig return -ENOMEM; 201292dc6895SChristoph Hellwig } 201392dc6895SChristoph Hellwig 20149620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 201587ad72a5SChristoph Hellwig { 201687ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 201787ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 201887ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 201987ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 20206fbcde66SMinwoo Im int ret; 202187ad72a5SChristoph Hellwig 2022acb71e53SChristoph Hellwig if (!dev->ctrl.hmpre) 2023acb71e53SChristoph Hellwig return 0; 2024acb71e53SChristoph Hellwig 202587ad72a5SChristoph Hellwig preferred = min(preferred, max); 202687ad72a5SChristoph Hellwig if (min > max) { 202787ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 202887ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 202987ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 203087ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20319620cfbaSChristoph Hellwig return 0; 203287ad72a5SChristoph Hellwig } 203387ad72a5SChristoph Hellwig 203487ad72a5SChristoph Hellwig /* 203587ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 203687ad72a5SChristoph Hellwig */ 203787ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 203887ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 203987ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 204087ad72a5SChristoph Hellwig else 204187ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 204287ad72a5SChristoph Hellwig } 204387ad72a5SChristoph Hellwig 204487ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 204592dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 204692dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 204792dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 20489620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 204987ad72a5SChristoph Hellwig } 205087ad72a5SChristoph Hellwig 205192dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 205292dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 205392dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 205492dc6895SChristoph Hellwig } 205592dc6895SChristoph Hellwig 20569620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 20579620cfbaSChristoph Hellwig if (ret) 205887ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 20599620cfbaSChristoph Hellwig return ret; 206057dacad5SJay Sternberg } 206157dacad5SJay Sternberg 20620521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 20630521905eSKeith Busch char *buf) 20640521905eSKeith Busch { 20650521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20660521905eSKeith Busch 20670521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 20680521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 20690521905eSKeith Busch } 20700521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 20710521905eSKeith Busch 20721751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 20731751e97aSKeith Busch char *buf) 20741751e97aSKeith Busch { 20751751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20761751e97aSKeith Busch 20771751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 20781751e97aSKeith Busch } 20791751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 20801751e97aSKeith Busch 20811751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 20821751e97aSKeith Busch char *buf) 20831751e97aSKeith Busch { 20841751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 20851751e97aSKeith Busch 20861751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 20871751e97aSKeith Busch } 20881751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 20891751e97aSKeith Busch 2090a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2091a5df5e79SKeith Busch char *buf) 2092a5df5e79SKeith Busch { 2093a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2094a5df5e79SKeith Busch 2095a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2096a5df5e79SKeith Busch } 2097a5df5e79SKeith Busch 2098a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2099a5df5e79SKeith Busch const char *buf, size_t count) 2100a5df5e79SKeith Busch { 2101a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2102a5df5e79SKeith Busch bool new; 2103a5df5e79SKeith Busch int ret; 2104a5df5e79SKeith Busch 210599722c8aSChristophe JAILLET if (kstrtobool(buf, &new) < 0) 2106a5df5e79SKeith Busch return -EINVAL; 2107a5df5e79SKeith Busch 2108a5df5e79SKeith Busch if (new == ndev->hmb) 2109a5df5e79SKeith Busch return count; 2110a5df5e79SKeith Busch 2111a5df5e79SKeith Busch if (new) { 2112a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2113a5df5e79SKeith Busch } else { 2114a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2115a5df5e79SKeith Busch if (!ret) 2116a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2117a5df5e79SKeith Busch } 2118a5df5e79SKeith Busch 2119a5df5e79SKeith Busch if (ret < 0) 2120a5df5e79SKeith Busch return ret; 2121a5df5e79SKeith Busch 2122a5df5e79SKeith Busch return count; 2123a5df5e79SKeith Busch } 2124a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2125a5df5e79SKeith Busch 21260521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 21270521905eSKeith Busch struct attribute *a, int n) 21280521905eSKeith Busch { 21290521905eSKeith Busch struct nvme_ctrl *ctrl = 21300521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 21310521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 21320521905eSKeith Busch 21331751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 21341751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 21351751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 21361751e97aSKeith Busch if (!dev->cmbsz) 21370521905eSKeith Busch return 0; 21381751e97aSKeith Busch } 2139a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2140a5df5e79SKeith Busch return 0; 2141a5df5e79SKeith Busch 21420521905eSKeith Busch return a->mode; 21430521905eSKeith Busch } 21440521905eSKeith Busch 21450521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 21460521905eSKeith Busch &dev_attr_cmb.attr, 21471751e97aSKeith Busch &dev_attr_cmbloc.attr, 21481751e97aSKeith Busch &dev_attr_cmbsz.attr, 2149a5df5e79SKeith Busch &dev_attr_hmb.attr, 21500521905eSKeith Busch NULL, 21510521905eSKeith Busch }; 21520521905eSKeith Busch 215386adbf0cSChristoph Hellwig static const struct attribute_group nvme_pci_dev_attrs_group = { 21540521905eSKeith Busch .attrs = nvme_pci_attrs, 21550521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 21560521905eSKeith Busch }; 21570521905eSKeith Busch 215886adbf0cSChristoph Hellwig static const struct attribute_group *nvme_pci_dev_attr_groups[] = { 215986adbf0cSChristoph Hellwig &nvme_dev_attrs_group, 216086adbf0cSChristoph Hellwig &nvme_pci_dev_attrs_group, 216186adbf0cSChristoph Hellwig NULL, 216286adbf0cSChristoph Hellwig }; 216386adbf0cSChristoph Hellwig 2164612b7286SMing Lei /* 2165612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2166612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2167612b7286SMing Lei */ 2168612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 21693b6592f7SJens Axboe { 2170612b7286SMing Lei struct nvme_dev *dev = affd->priv; 21712a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2172c45b1fa2SMing Lei 21733b6592f7SJens Axboe /* 2174ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2175612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2176612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2177612b7286SMing Lei * 2178612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2179612b7286SMing Lei * write and read queues. 2180612b7286SMing Lei * 2181612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2182612b7286SMing Lei * queue. 21833b6592f7SJens Axboe */ 2184612b7286SMing Lei if (!nrirqs) { 2185612b7286SMing Lei nrirqs = 1; 2186612b7286SMing Lei nr_read_queues = 0; 21872a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2188612b7286SMing Lei nr_read_queues = 0; 21892a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2190612b7286SMing Lei nr_read_queues = 1; 21913b6592f7SJens Axboe } else { 21922a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 21933b6592f7SJens Axboe } 2194612b7286SMing Lei 2195612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2196612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2197612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2198612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2199612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22003b6592f7SJens Axboe } 22013b6592f7SJens Axboe 22026451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22033b6592f7SJens Axboe { 22043b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22053b6592f7SJens Axboe struct irq_affinity affd = { 22063b6592f7SJens Axboe .pre_vectors = 1, 2207612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2208612b7286SMing Lei .priv = dev, 22093b6592f7SJens Axboe }; 221021cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22116451fe73SJens Axboe 22126451fe73SJens Axboe /* 221321cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 221421cc2f3fSJeffle Xu * left over for non-polled I/O. 22156451fe73SJens Axboe */ 221621cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 221721cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 22183b6592f7SJens Axboe 221921cc2f3fSJeffle Xu /* 222021cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 222121cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 222221cc2f3fSJeffle Xu */ 2223612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2224612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 22253b6592f7SJens Axboe 222666341331SBenjamin Herrenschmidt /* 222721cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 222821cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 222921cc2f3fSJeffle Xu * vector. 223066341331SBenjamin Herrenschmidt */ 223166341331SBenjamin Herrenschmidt irq_queues = 1; 223221cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 223321cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2234612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 22353b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 22363b6592f7SJens Axboe } 22373b6592f7SJens Axboe 22382a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 22392a5bcfddSWeiping Zhang { 2240e3aef095SNiklas Schnelle /* 2241e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2242e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2243e3aef095SNiklas Schnelle */ 2244e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2245e3aef095SNiklas Schnelle return 1; 22462a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 22472a5bcfddSWeiping Zhang } 22482a5bcfddSWeiping Zhang 224957dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 225057dacad5SJay Sternberg { 2251147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 225257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 22532a5bcfddSWeiping Zhang unsigned int nr_io_queues; 225497f6ef64SXu Yu unsigned long size; 22552a5bcfddSWeiping Zhang int result; 225657dacad5SJay Sternberg 22572a5bcfddSWeiping Zhang /* 22582a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 22592a5bcfddSWeiping Zhang * stable values to work with. 22602a5bcfddSWeiping Zhang */ 22612a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 22622a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2263d38e9f04SBenjamin Herrenschmidt 2264ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 22659a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 22669a0be7abSChristoph Hellwig if (result < 0) 226757dacad5SJay Sternberg return result; 22689a0be7abSChristoph Hellwig 2269f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2270a5229050SKeith Busch return 0; 227157dacad5SJay Sternberg 2272e4b9852aSCasey Chen /* 2273e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2274e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2275e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2276e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2277e4b9852aSCasey Chen * nvme_dev_disable() path. 2278e4b9852aSCasey Chen */ 2279e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2280e4b9852aSCasey Chen if (result) 2281e4b9852aSCasey Chen return result; 2282e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2283e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 22844e224106SChristoph Hellwig 22850f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 228657dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 228757dacad5SJay Sternberg sizeof(struct nvme_command)); 228888d356caSChristoph Hellwig if (result > 0) { 228957dacad5SJay Sternberg dev->q_depth = result; 229088d356caSChristoph Hellwig dev->ctrl.sqsize = result - 1; 229188d356caSChristoph Hellwig } else { 22920f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 229357dacad5SJay Sternberg } 229488d356caSChristoph Hellwig } 229557dacad5SJay Sternberg 229657dacad5SJay Sternberg do { 229797f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 229897f6ef64SXu Yu result = nvme_remap_bar(dev, size); 229997f6ef64SXu Yu if (!result) 230057dacad5SJay Sternberg break; 2301e4b9852aSCasey Chen if (!--nr_io_queues) { 2302e4b9852aSCasey Chen result = -ENOMEM; 2303e4b9852aSCasey Chen goto out_unlock; 2304e4b9852aSCasey Chen } 230557dacad5SJay Sternberg } while (1); 230657dacad5SJay Sternberg adminq->q_db = dev->dbs; 230757dacad5SJay Sternberg 23088fae268bSKeith Busch retry: 230957dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2310e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 23110ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 231257dacad5SJay Sternberg 231357dacad5SJay Sternberg /* 231457dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 231557dacad5SJay Sternberg * setting up the full range we need. 231657dacad5SJay Sternberg */ 2317dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 23183b6592f7SJens Axboe 23193b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2320e4b9852aSCasey Chen if (result <= 0) { 2321e4b9852aSCasey Chen result = -EIO; 2322e4b9852aSCasey Chen goto out_unlock; 2323e4b9852aSCasey Chen } 23243b6592f7SJens Axboe 232522b55601SKeith Busch dev->num_vecs = result; 23264b04cc6aSJens Axboe result = max(result - 1, 1); 2327e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 232857dacad5SJay Sternberg 232957dacad5SJay Sternberg /* 233057dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 233157dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 233257dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 233357dacad5SJay Sternberg * number of interrupts. 233457dacad5SJay Sternberg */ 2335dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 23367c349ddeSKeith Busch if (result) 2337e4b9852aSCasey Chen goto out_unlock; 23384e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2339e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 23408fae268bSKeith Busch 23418fae268bSKeith Busch result = nvme_create_io_queues(dev); 23428fae268bSKeith Busch if (result || dev->online_queues < 2) 23438fae268bSKeith Busch return result; 23448fae268bSKeith Busch 23458fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 23468fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 23477d879c90SChristoph Hellwig nvme_delete_io_queues(dev); 2348e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2349e4b9852aSCasey Chen if (result) 2350e4b9852aSCasey Chen return result; 23518fae268bSKeith Busch nvme_suspend_io_queues(dev); 23528fae268bSKeith Busch goto retry; 23538fae268bSKeith Busch } 23548fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 23558fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 23568fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 23578fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 23588fae268bSKeith Busch return 0; 2359e4b9852aSCasey Chen out_unlock: 2360e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2361e4b9852aSCasey Chen return result; 236257dacad5SJay Sternberg } 236357dacad5SJay Sternberg 2364de671d61SJens Axboe static enum rq_end_io_ret nvme_del_queue_end(struct request *req, 2365de671d61SJens Axboe blk_status_t error) 2366db3cbfffSKeith Busch { 2367db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2368db3cbfffSKeith Busch 2369db3cbfffSKeith Busch blk_mq_free_request(req); 2370d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2371de671d61SJens Axboe return RQ_END_IO_NONE; 2372db3cbfffSKeith Busch } 2373db3cbfffSKeith Busch 2374de671d61SJens Axboe static enum rq_end_io_ret nvme_del_cq_end(struct request *req, 2375de671d61SJens Axboe blk_status_t error) 2376db3cbfffSKeith Busch { 2377db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2378db3cbfffSKeith Busch 2379d1ed6aa1SChristoph Hellwig if (error) 2380d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2381db3cbfffSKeith Busch 2382de671d61SJens Axboe return nvme_del_queue_end(req, error); 2383db3cbfffSKeith Busch } 2384db3cbfffSKeith Busch 2385db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2386db3cbfffSKeith Busch { 2387db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2388db3cbfffSKeith Busch struct request *req; 2389f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2390db3cbfffSKeith Busch 2391db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2392db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2393db3cbfffSKeith Busch 2394e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2395db3cbfffSKeith Busch if (IS_ERR(req)) 2396db3cbfffSKeith Busch return PTR_ERR(req); 2397e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2398db3cbfffSKeith Busch 2399e2e53086SChristoph Hellwig if (opcode == nvme_admin_delete_cq) 2400e2e53086SChristoph Hellwig req->end_io = nvme_del_cq_end; 2401e2e53086SChristoph Hellwig else 2402e2e53086SChristoph Hellwig req->end_io = nvme_del_queue_end; 2403db3cbfffSKeith Busch req->end_io_data = nvmeq; 2404db3cbfffSKeith Busch 2405d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2406e2e53086SChristoph Hellwig blk_execute_rq_nowait(req, false); 2407db3cbfffSKeith Busch return 0; 2408db3cbfffSKeith Busch } 2409db3cbfffSKeith Busch 24107d879c90SChristoph Hellwig static bool __nvme_delete_io_queues(struct nvme_dev *dev, u8 opcode) 2411db3cbfffSKeith Busch { 24125271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2413db3cbfffSKeith Busch unsigned long timeout; 2414db3cbfffSKeith Busch 2415db3cbfffSKeith Busch retry: 2416dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 24175271edd4SChristoph Hellwig while (nr_queues > 0) { 24185271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2419db3cbfffSKeith Busch break; 24205271edd4SChristoph Hellwig nr_queues--; 24215271edd4SChristoph Hellwig sent++; 24225271edd4SChristoph Hellwig } 2423d1ed6aa1SChristoph Hellwig while (sent) { 2424d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2425d1ed6aa1SChristoph Hellwig 2426d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 24275271edd4SChristoph Hellwig timeout); 2428db3cbfffSKeith Busch if (timeout == 0) 24295271edd4SChristoph Hellwig return false; 2430d1ed6aa1SChristoph Hellwig 2431d1ed6aa1SChristoph Hellwig sent--; 24325271edd4SChristoph Hellwig if (nr_queues) 2433db3cbfffSKeith Busch goto retry; 2434db3cbfffSKeith Busch } 24355271edd4SChristoph Hellwig return true; 2436db3cbfffSKeith Busch } 2437db3cbfffSKeith Busch 24387d879c90SChristoph Hellwig static void nvme_delete_io_queues(struct nvme_dev *dev) 243957dacad5SJay Sternberg { 24407d879c90SChristoph Hellwig if (__nvme_delete_io_queues(dev, nvme_admin_delete_sq)) 24417d879c90SChristoph Hellwig __nvme_delete_io_queues(dev, nvme_admin_delete_cq); 24422b1b7e78SJianchao Wang } 24437d879c90SChristoph Hellwig 24440da7feaaSChristoph Hellwig static unsigned int nvme_pci_nr_maps(struct nvme_dev *dev) 244557dacad5SJay Sternberg { 244657dacad5SJay Sternberg if (dev->io_queues[HCTX_TYPE_POLL]) 24470da7feaaSChristoph Hellwig return 3; 24480da7feaaSChristoph Hellwig if (dev->io_queues[HCTX_TYPE_READ]) 24490da7feaaSChristoph Hellwig return 2; 24500da7feaaSChristoph Hellwig return 1; 245157dacad5SJay Sternberg } 2452949928c1SKeith Busch 24532455a4b7SChristoph Hellwig static void nvme_pci_update_nr_queues(struct nvme_dev *dev) 24542455a4b7SChristoph Hellwig { 24552455a4b7SChristoph Hellwig blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 24562455a4b7SChristoph Hellwig /* free previously allocated queues that are no longer usable */ 24572455a4b7SChristoph Hellwig nvme_free_queues(dev, dev->online_queues); 245857dacad5SJay Sternberg } 245957dacad5SJay Sternberg 2460b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 246157dacad5SJay Sternberg { 2462b00a726aSKeith Busch int result = -ENOMEM; 246357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 24644bdf2603SFilippo Sironi int dma_address_bits = 64; 246557dacad5SJay Sternberg 246657dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 246757dacad5SJay Sternberg return result; 246857dacad5SJay Sternberg 246957dacad5SJay Sternberg pci_set_master(pdev); 247057dacad5SJay Sternberg 24714bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 24724bdf2603SFilippo Sironi dma_address_bits = 48; 24734bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 247457dacad5SJay Sternberg goto disable; 247557dacad5SJay Sternberg 24767a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 247757dacad5SJay Sternberg result = -ENODEV; 2478b00a726aSKeith Busch goto disable; 247957dacad5SJay Sternberg } 248057dacad5SJay Sternberg 248157dacad5SJay Sternberg /* 2482a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2483a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2484a5229050SKeith Busch * adjust this later. 248557dacad5SJay Sternberg */ 2486dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2487dca51e78SChristoph Hellwig if (result < 0) 248809113abfSTong Zhang goto disable; 248957dacad5SJay Sternberg 249020d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 24917a67cbeaSChristoph Hellwig 24927442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2493b27c1e68Sweiping zhang io_queue_depth); 249420d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 24957a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 24961f390c1fSStephan Günther 24971f390c1fSStephan Günther /* 249866341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 249966341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 250066341331SBenjamin Herrenschmidt * so we don't bother updating it here. 250166341331SBenjamin Herrenschmidt */ 250266341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 250366341331SBenjamin Herrenschmidt dev->io_sqes = 7; 250466341331SBenjamin Herrenschmidt else 2505c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 25061f390c1fSStephan Günther 25071f390c1fSStephan Günther /* 25081f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 25091f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 25101f390c1fSStephan Günther */ 25111f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 25121f390c1fSStephan Günther dev->q_depth = 2; 25139bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 25149bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 25151f390c1fSStephan Günther dev->q_depth); 2516d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2517d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 251820d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2519d554b5e1SMartin K. Petersen dev->q_depth = 64; 2520d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2521d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 25221f390c1fSStephan Günther } 25231f390c1fSStephan Günther 2524d38e9f04SBenjamin Herrenschmidt /* 2525d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2526d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2527d38e9f04SBenjamin Herrenschmidt */ 2528d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2529d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2530d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2531d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2532d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2533d38e9f04SBenjamin Herrenschmidt } 253488d356caSChristoph Hellwig dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 2535d38e9f04SBenjamin Herrenschmidt 2536f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2537202021c1SStephen Bates 2538a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2539a0a3408eSKeith Busch pci_save_state(pdev); 2540a6ee7f19SChristoph Hellwig 254109113abfSTong Zhang result = nvme_pci_configure_admin_queue(dev); 254209113abfSTong Zhang if (result) 254309113abfSTong Zhang goto free_irq; 254409113abfSTong Zhang return result; 254557dacad5SJay Sternberg 254609113abfSTong Zhang free_irq: 254709113abfSTong Zhang pci_free_irq_vectors(pdev); 254857dacad5SJay Sternberg disable: 254957dacad5SJay Sternberg pci_disable_device(pdev); 255057dacad5SJay Sternberg return result; 255157dacad5SJay Sternberg } 255257dacad5SJay Sternberg 255357dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 255457dacad5SJay Sternberg { 2555b00a726aSKeith Busch if (dev->bar) 2556b00a726aSKeith Busch iounmap(dev->bar); 2557a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2558b00a726aSKeith Busch } 2559b00a726aSKeith Busch 256068e81ebaSChristoph Hellwig static bool nvme_pci_ctrl_is_dead(struct nvme_dev *dev) 2561b00a726aSKeith Busch { 256257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 2563081f5e75SKeith Busch u32 csts; 256457dacad5SJay Sternberg 256568e81ebaSChristoph Hellwig if (!pci_is_enabled(pdev) || !pci_device_is_present(pdev)) 256668e81ebaSChristoph Hellwig return true; 256768e81ebaSChristoph Hellwig if (pdev->error_state != pci_channel_io_normal) 256868e81ebaSChristoph Hellwig return true; 256957dacad5SJay Sternberg 257068e81ebaSChristoph Hellwig csts = readl(dev->bar + NVME_REG_CSTS); 257168e81ebaSChristoph Hellwig return (csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY); 2572a0a3408eSKeith Busch } 257357dacad5SJay Sternberg 2574a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 257557dacad5SJay Sternberg { 2576302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 257768e81ebaSChristoph Hellwig bool dead; 257857dacad5SJay Sternberg 257977bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 258068e81ebaSChristoph Hellwig dead = nvme_pci_ctrl_is_dead(dev); 2581ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2582e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 258368e81ebaSChristoph Hellwig if (pci_is_enabled(pdev)) 2584302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2585302ad8ccSKeith Busch /* 258668e81ebaSChristoph Hellwig * Give the controller a chance to complete all entered requests 258768e81ebaSChristoph Hellwig * if doing a safe shutdown. 2588302ad8ccSKeith Busch */ 258968e81ebaSChristoph Hellwig if (!dead && shutdown) 2590302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 259168e81ebaSChristoph Hellwig } 259287ad72a5SChristoph Hellwig 25939f27bd70SChristoph Hellwig nvme_quiesce_io_queues(&dev->ctrl); 25949a915a5bSJianchao Wang 259564ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 25967d879c90SChristoph Hellwig nvme_delete_io_queues(dev); 259747d42d22SChristoph Hellwig nvme_disable_ctrl(&dev->ctrl, shutdown); 259847d42d22SChristoph Hellwig nvme_poll_irqdisable(&dev->queues[0]); 259957dacad5SJay Sternberg } 26008fae268bSKeith Busch nvme_suspend_io_queues(dev); 260110981f23SChristoph Hellwig nvme_suspend_queue(dev, 0); 2602c80767f7SChristoph Hellwig pci_free_irq_vectors(pdev); 2603c80767f7SChristoph Hellwig if (pci_is_enabled(pdev)) { 2604c80767f7SChristoph Hellwig pci_disable_pcie_error_reporting(pdev); 2605c80767f7SChristoph Hellwig pci_disable_device(pdev); 2606c80767f7SChristoph Hellwig } 2607fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 260857dacad5SJay Sternberg 26091fcfca78SGuixin Liu nvme_cancel_tagset(&dev->ctrl); 26101fcfca78SGuixin Liu nvme_cancel_admin_tagset(&dev->ctrl); 2611302ad8ccSKeith Busch 2612302ad8ccSKeith Busch /* 2613302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2614302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2615302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2616302ad8ccSKeith Busch */ 2617c8e9e9b7SKeith Busch if (shutdown) { 26189f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2619c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 26209f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 2621c8e9e9b7SKeith Busch } 262277bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 262357dacad5SJay Sternberg } 262457dacad5SJay Sternberg 2625c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2626c1ac9a4bSKeith Busch { 2627c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2628c1ac9a4bSKeith Busch return -EBUSY; 2629c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2630c1ac9a4bSKeith Busch return 0; 2631c1ac9a4bSKeith Busch } 2632c1ac9a4bSKeith Busch 263357dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 263457dacad5SJay Sternberg { 263557dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2636c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2637c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 263857dacad5SJay Sternberg if (!dev->prp_page_pool) 263957dacad5SJay Sternberg return -ENOMEM; 264057dacad5SJay Sternberg 264157dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 264257dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 264357dacad5SJay Sternberg 256, 256, 0); 264457dacad5SJay Sternberg if (!dev->prp_small_pool) { 264557dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 264657dacad5SJay Sternberg return -ENOMEM; 264757dacad5SJay Sternberg } 264857dacad5SJay Sternberg return 0; 264957dacad5SJay Sternberg } 265057dacad5SJay Sternberg 265157dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 265257dacad5SJay Sternberg { 265357dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 265457dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 265557dacad5SJay Sternberg } 265657dacad5SJay Sternberg 2657081a7d95SChristoph Hellwig static int nvme_pci_alloc_iod_mempool(struct nvme_dev *dev) 2658081a7d95SChristoph Hellwig { 2659*7846c1b5SKeith Busch size_t alloc_size = sizeof(struct scatterlist) * NVME_MAX_SEGS; 2660081a7d95SChristoph Hellwig 2661081a7d95SChristoph Hellwig dev->iod_mempool = mempool_create_node(1, 2662081a7d95SChristoph Hellwig mempool_kmalloc, mempool_kfree, 2663081a7d95SChristoph Hellwig (void *)alloc_size, GFP_KERNEL, 2664081a7d95SChristoph Hellwig dev_to_node(dev->dev)); 2665081a7d95SChristoph Hellwig if (!dev->iod_mempool) 2666081a7d95SChristoph Hellwig return -ENOMEM; 2667081a7d95SChristoph Hellwig return 0; 2668081a7d95SChristoph Hellwig } 2669081a7d95SChristoph Hellwig 2670770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2671770597ecSKeith Busch { 2672770597ecSKeith Busch if (dev->tagset.tags) 26730da7feaaSChristoph Hellwig nvme_remove_io_tag_set(&dev->ctrl); 2674770597ecSKeith Busch dev->ctrl.tagset = NULL; 2675770597ecSKeith Busch } 2676770597ecSKeith Busch 26772e87570bSChristoph Hellwig /* pairs with nvme_pci_alloc_dev */ 26781673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 267957dacad5SJay Sternberg { 26801673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 268157dacad5SJay Sternberg 2682770597ecSKeith Busch nvme_free_tagset(dev); 2683253fd4acSIsrael Rukshin put_device(dev->dev); 2684253fd4acSIsrael Rukshin kfree(dev->queues); 268557dacad5SJay Sternberg kfree(dev); 268657dacad5SJay Sternberg } 268757dacad5SJay Sternberg 2688fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 268957dacad5SJay Sternberg { 2690d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2691d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2692a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2693e71afda4SChaitanya Kulkarni int result; 269457dacad5SJay Sternberg 26957764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 26967764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 26977764656bSZhihao Cheng dev->ctrl.state); 26988cb9f10bSChristoph Hellwig return; 2699e71afda4SChaitanya Kulkarni } 2700fd634f41SChristoph Hellwig 2701fd634f41SChristoph Hellwig /* 2702fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2703fd634f41SChristoph Hellwig * moving on. 2704fd634f41SChristoph Hellwig */ 2705b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2706a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2707d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2708fd634f41SChristoph Hellwig 27095c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2710b00a726aSKeith Busch result = nvme_pci_enable(dev); 271157dacad5SJay Sternberg if (result) 27124726bcf3SKeith Busch goto out_unlock; 27139f27bd70SChristoph Hellwig nvme_unquiesce_admin_queue(&dev->ctrl); 27145c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 27155c959d73SKeith Busch 27165c959d73SKeith Busch /* 27175c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 27185c959d73SKeith Busch * initializing procedure here. 27195c959d73SKeith Busch */ 27205c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 27215c959d73SKeith Busch dev_warn(dev->ctrl.device, 27225c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2723cee6c269SMinwoo Im result = -EBUSY; 27245c959d73SKeith Busch goto out; 27255c959d73SKeith Busch } 2726943e942eSJens Axboe 272794cc781fSChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, was_suspend); 2728ce4541f4SChristoph Hellwig if (result) 2729f58944e2SKeith Busch goto out; 2730ce4541f4SChristoph Hellwig 273165a54646SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 2732a98e58e5SScott Bauer 27339620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 27349620cfbaSChristoph Hellwig if (result < 0) 27359620cfbaSChristoph Hellwig goto out; 273687ad72a5SChristoph Hellwig 273757dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 273857dacad5SJay Sternberg if (result) 2739f58944e2SKeith Busch goto out; 274057dacad5SJay Sternberg 274121f033f7SKeith Busch /* 27420ffc7e98SChristoph Hellwig * Freeze and update the number of I/O queues as thos might have 2743eac3ef26SChristoph Hellwig * changed. If there are no I/O queues left after this reset, keep the 2744eac3ef26SChristoph Hellwig * controller around but remove all namespaces. 274557dacad5SJay Sternberg */ 27460ffc7e98SChristoph Hellwig if (dev->online_queues > 1) { 27479f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 2748302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 27492455a4b7SChristoph Hellwig nvme_pci_update_nr_queues(dev); 27502455a4b7SChristoph Hellwig nvme_dbbuf_set(dev); 2751302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 27520ffc7e98SChristoph Hellwig } else { 27530ffc7e98SChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues lost\n"); 2754cd50f9b2SChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 27559f27bd70SChristoph Hellwig nvme_unquiesce_io_queues(&dev->ctrl); 27560ffc7e98SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 27570ffc7e98SChristoph Hellwig nvme_free_tagset(dev); 275857dacad5SJay Sternberg } 275957dacad5SJay Sternberg 27602b1b7e78SJianchao Wang /* 27612b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 27622b1b7e78SJianchao Wang * recovery. 27632b1b7e78SJianchao Wang */ 27645d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 27652b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 27665d02a5c1SKeith Busch "failed to mark controller live state\n"); 2767e71afda4SChaitanya Kulkarni result = -ENODEV; 2768bb8d261eSChristoph Hellwig goto out; 2769bb8d261eSChristoph Hellwig } 277092911a55SChristoph Hellwig 2771d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 277257dacad5SJay Sternberg return; 277357dacad5SJay Sternberg 27744726bcf3SKeith Busch out_unlock: 27754726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 277657dacad5SJay Sternberg out: 2777c7c16c5bSChristoph Hellwig /* 2778c7c16c5bSChristoph Hellwig * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2779c7c16c5bSChristoph Hellwig * may be holding this pci_dev's device lock. 2780c7c16c5bSChristoph Hellwig */ 2781c7c16c5bSChristoph Hellwig dev_warn(dev->ctrl.device, "Disabling device after reset failure: %d\n", 2782c7c16c5bSChristoph Hellwig result); 2783c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2784c7c16c5bSChristoph Hellwig nvme_dev_disable(dev, true); 2785c7c16c5bSChristoph Hellwig nvme_mark_namespaces_dead(&dev->ctrl); 2786c7c16c5bSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 278757dacad5SJay Sternberg } 278857dacad5SJay Sternberg 27891c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 279057dacad5SJay Sternberg { 27911c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 27921c63dc66SChristoph Hellwig return 0; 279357dacad5SJay Sternberg } 27941c63dc66SChristoph Hellwig 27955fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 27965fd4ce1bSChristoph Hellwig { 27975fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 27985fd4ce1bSChristoph Hellwig return 0; 27995fd4ce1bSChristoph Hellwig } 28005fd4ce1bSChristoph Hellwig 28017fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 28027fd8930fSChristoph Hellwig { 28033a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 28047fd8930fSChristoph Hellwig return 0; 28057fd8930fSChristoph Hellwig } 28067fd8930fSChristoph Hellwig 280797c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 280897c12223SKeith Busch { 280997c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 281097c12223SKeith Busch 28112db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 281297c12223SKeith Busch } 281397c12223SKeith Busch 28142f0dad17SKeith Busch static void nvme_pci_print_device_info(struct nvme_ctrl *ctrl) 28152f0dad17SKeith Busch { 28162f0dad17SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 28172f0dad17SKeith Busch struct nvme_subsystem *subsys = ctrl->subsys; 28182f0dad17SKeith Busch 28192f0dad17SKeith Busch dev_err(ctrl->device, 28202f0dad17SKeith Busch "VID:DID %04x:%04x model:%.*s firmware:%.*s\n", 28212f0dad17SKeith Busch pdev->vendor, pdev->device, 28222f0dad17SKeith Busch nvme_strlen(subsys->model, sizeof(subsys->model)), 28232f0dad17SKeith Busch subsys->model, nvme_strlen(subsys->firmware_rev, 28242f0dad17SKeith Busch sizeof(subsys->firmware_rev)), 28252f0dad17SKeith Busch subsys->firmware_rev); 28262f0dad17SKeith Busch } 28272f0dad17SKeith Busch 28282f859441SLogan Gunthorpe static bool nvme_pci_supports_pci_p2pdma(struct nvme_ctrl *ctrl) 28292f859441SLogan Gunthorpe { 28302f859441SLogan Gunthorpe struct nvme_dev *dev = to_nvme_dev(ctrl); 28312f859441SLogan Gunthorpe 28322f859441SLogan Gunthorpe return dma_pci_p2pdma_supported(dev->dev); 28332f859441SLogan Gunthorpe } 28342f859441SLogan Gunthorpe 28351c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 28361a353d85SMing Lin .name = "pcie", 2837e439bb12SSagi Grimberg .module = THIS_MODULE, 28382f859441SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED, 283986adbf0cSChristoph Hellwig .dev_attr_groups = nvme_pci_dev_attr_groups, 28401c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 28415fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 28427fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 28431673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2844f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 284597c12223SKeith Busch .get_address = nvme_pci_get_address, 28462f0dad17SKeith Busch .print_device_info = nvme_pci_print_device_info, 28472f859441SLogan Gunthorpe .supports_pci_p2pdma = nvme_pci_supports_pci_p2pdma, 28481c63dc66SChristoph Hellwig }; 284957dacad5SJay Sternberg 2850b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2851b00a726aSKeith Busch { 2852b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2853b00a726aSKeith Busch 2854a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2855b00a726aSKeith Busch return -ENODEV; 2856b00a726aSKeith Busch 285797f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2858b00a726aSKeith Busch goto release; 2859b00a726aSKeith Busch 2860b00a726aSKeith Busch return 0; 2861b00a726aSKeith Busch release: 2862a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 2863b00a726aSKeith Busch return -ENODEV; 2864b00a726aSKeith Busch } 2865b00a726aSKeith Busch 28668427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 2867ff5350a8SAndy Lutomirski { 2868ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 2869ff5350a8SAndy Lutomirski /* 2870ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 2871ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 2872ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 2873ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 2874ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 2875ff5350a8SAndy Lutomirski * laptops. 2876ff5350a8SAndy Lutomirski */ 2877ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 2878ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 2879ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 2880ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 28818427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 28828427bbc2SKai-Heng Feng /* 28838427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 2884467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 2885467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 2886467c77d4SJarosław Janik * ASUS PRIME Z370-A 28878427bbc2SKai-Heng Feng */ 28888427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 2889467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 2890467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 28918427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 28921fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 28931fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 28941fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 28951fae37acSShyjumon N /* 28961fae37acSShyjumon N * Forcing to use host managed nvme power settings for 28971fae37acSShyjumon N * lowest idle power with quick resume latency on 28981fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 28991fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 29001fae37acSShyjumon N */ 29011fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 29021fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 29031fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 2904ff5350a8SAndy Lutomirski } 2905ff5350a8SAndy Lutomirski 2906ff5350a8SAndy Lutomirski return 0; 2907ff5350a8SAndy Lutomirski } 2908ff5350a8SAndy Lutomirski 29092e87570bSChristoph Hellwig static struct nvme_dev *nvme_pci_alloc_dev(struct pci_dev *pdev, 29102e87570bSChristoph Hellwig const struct pci_device_id *id) 291118119775SKeith Busch { 2912ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 29132e87570bSChristoph Hellwig int node = dev_to_node(&pdev->dev); 29142e87570bSChristoph Hellwig struct nvme_dev *dev; 29152e87570bSChristoph Hellwig int ret = -ENOMEM; 291657dacad5SJay Sternberg 291757dacad5SJay Sternberg if (node == NUMA_NO_NODE) 29182fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 291957dacad5SJay Sternberg 292057dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 292157dacad5SJay Sternberg if (!dev) 29222e87570bSChristoph Hellwig return NULL; 29232e87570bSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 29242e87570bSChristoph Hellwig mutex_init(&dev->shutdown_lock); 2925147b27e4SSagi Grimberg 29262a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 29272a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 29282a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 29292a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 29302a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 293157dacad5SJay Sternberg if (!dev->queues) 29322e87570bSChristoph Hellwig goto out_free_dev; 293357dacad5SJay Sternberg 293457dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 2935f3ca80fcSChristoph Hellwig 29368427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 29372744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 2938df4f9bc4SDavid E. Box /* 2939df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 2940df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 2941df4f9bc4SDavid E. Box */ 2942df4f9bc4SDavid E. Box dev_info(&pdev->dev, 2943df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 2944df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 2945df4f9bc4SDavid E. Box } 29462e87570bSChristoph Hellwig ret = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 29472e87570bSChristoph Hellwig quirks); 29482e87570bSChristoph Hellwig if (ret) 29492e87570bSChristoph Hellwig goto out_put_device; 29503f30a79cSChristoph Hellwig 29513f30a79cSChristoph Hellwig dma_set_min_align_mask(&pdev->dev, NVME_CTRL_PAGE_SIZE - 1); 29523f30a79cSChristoph Hellwig dma_set_max_seg_size(&pdev->dev, 0xffffffff); 2953df4f9bc4SDavid E. Box 2954943e942eSJens Axboe /* 29553f30a79cSChristoph Hellwig * Limit the max command size to prevent iod->sg allocations going 29563f30a79cSChristoph Hellwig * over a single page. 2957943e942eSJens Axboe */ 29583f30a79cSChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 29593f30a79cSChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(&pdev->dev) >> 9); 29603f30a79cSChristoph Hellwig dev->ctrl.max_segments = NVME_MAX_SEGS; 2961943e942eSJens Axboe 29623f30a79cSChristoph Hellwig /* 29633f30a79cSChristoph Hellwig * There is no support for SGLs for metadata (yet), so we are limited to 29643f30a79cSChristoph Hellwig * a single integrity segment for the separate metadata pointer. 29653f30a79cSChristoph Hellwig */ 29663f30a79cSChristoph Hellwig dev->ctrl.max_integrity_segments = 1; 29672e87570bSChristoph Hellwig return dev; 29682e87570bSChristoph Hellwig 29692e87570bSChristoph Hellwig out_put_device: 29702e87570bSChristoph Hellwig put_device(dev->dev); 29712e87570bSChristoph Hellwig kfree(dev->queues); 29722e87570bSChristoph Hellwig out_free_dev: 29732e87570bSChristoph Hellwig kfree(dev); 29742e87570bSChristoph Hellwig return ERR_PTR(ret); 2975943e942eSJens Axboe } 2976943e942eSJens Axboe 29772e87570bSChristoph Hellwig static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 29782e87570bSChristoph Hellwig { 29792e87570bSChristoph Hellwig struct nvme_dev *dev; 29802e87570bSChristoph Hellwig int result = -ENOMEM; 29812e87570bSChristoph Hellwig 29822e87570bSChristoph Hellwig dev = nvme_pci_alloc_dev(pdev, id); 29832e87570bSChristoph Hellwig if (!dev) 29842e87570bSChristoph Hellwig return -ENOMEM; 29852e87570bSChristoph Hellwig 29862e87570bSChristoph Hellwig result = nvme_dev_map(dev); 2987b6e44b4cSKeith Busch if (result) 29882e87570bSChristoph Hellwig goto out_uninit_ctrl; 29892e87570bSChristoph Hellwig 29902e87570bSChristoph Hellwig result = nvme_setup_prp_pools(dev); 29912e87570bSChristoph Hellwig if (result) 29922e87570bSChristoph Hellwig goto out_dev_unmap; 299357dacad5SJay Sternberg 2994081a7d95SChristoph Hellwig result = nvme_pci_alloc_iod_mempool(dev); 2995081a7d95SChristoph Hellwig if (result) 29962e87570bSChristoph Hellwig goto out_release_prp_pools; 2997b6e44b4cSKeith Busch 299857dacad5SJay Sternberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 299957dacad5SJay Sternberg 3000eac3ef26SChristoph Hellwig result = nvme_pci_enable(dev); 3001eac3ef26SChristoph Hellwig if (result) 3002eac3ef26SChristoph Hellwig goto out_release_iod_mempool; 300357dacad5SJay Sternberg 30040da7feaaSChristoph Hellwig result = nvme_alloc_admin_tag_set(&dev->ctrl, &dev->admin_tagset, 30050da7feaaSChristoph Hellwig &nvme_mq_admin_ops, sizeof(struct nvme_iod)); 3006eac3ef26SChristoph Hellwig if (result) 3007eac3ef26SChristoph Hellwig goto out_disable; 3008eac3ef26SChristoph Hellwig 3009eac3ef26SChristoph Hellwig /* 3010eac3ef26SChristoph Hellwig * Mark the controller as connecting before sending admin commands to 3011eac3ef26SChristoph Hellwig * allow the timeout handler to do the right thing. 3012eac3ef26SChristoph Hellwig */ 3013eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 3014eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3015eac3ef26SChristoph Hellwig "failed to mark controller CONNECTING\n"); 3016eac3ef26SChristoph Hellwig result = -EBUSY; 3017eac3ef26SChristoph Hellwig goto out_disable; 3018eac3ef26SChristoph Hellwig } 3019eac3ef26SChristoph Hellwig 3020eac3ef26SChristoph Hellwig result = nvme_init_ctrl_finish(&dev->ctrl, false); 3021eac3ef26SChristoph Hellwig if (result) 3022eac3ef26SChristoph Hellwig goto out_disable; 3023eac3ef26SChristoph Hellwig 3024eac3ef26SChristoph Hellwig nvme_dbbuf_dma_alloc(dev); 3025eac3ef26SChristoph Hellwig 3026eac3ef26SChristoph Hellwig result = nvme_setup_host_mem(dev); 3027eac3ef26SChristoph Hellwig if (result < 0) 3028eac3ef26SChristoph Hellwig goto out_disable; 3029eac3ef26SChristoph Hellwig 3030eac3ef26SChristoph Hellwig result = nvme_setup_io_queues(dev); 3031eac3ef26SChristoph Hellwig if (result) 3032eac3ef26SChristoph Hellwig goto out_disable; 3033eac3ef26SChristoph Hellwig 3034eac3ef26SChristoph Hellwig if (dev->online_queues > 1) { 30350da7feaaSChristoph Hellwig nvme_alloc_io_tag_set(&dev->ctrl, &dev->tagset, &nvme_mq_ops, 30360da7feaaSChristoph Hellwig nvme_pci_nr_maps(dev), sizeof(struct nvme_iod)); 3037eac3ef26SChristoph Hellwig nvme_dbbuf_set(dev); 3038eac3ef26SChristoph Hellwig } 3039eac3ef26SChristoph Hellwig 30400da7feaaSChristoph Hellwig if (!dev->ctrl.tagset) 30410da7feaaSChristoph Hellwig dev_warn(dev->ctrl.device, "IO queues not created\n"); 30420da7feaaSChristoph Hellwig 3043eac3ef26SChristoph Hellwig if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 3044eac3ef26SChristoph Hellwig dev_warn(dev->ctrl.device, 3045eac3ef26SChristoph Hellwig "failed to mark controller live state\n"); 3046eac3ef26SChristoph Hellwig result = -ENODEV; 3047eac3ef26SChristoph Hellwig goto out_disable; 3048eac3ef26SChristoph Hellwig } 3049eac3ef26SChristoph Hellwig 30502e87570bSChristoph Hellwig pci_set_drvdata(pdev, dev); 305157dacad5SJay Sternberg 3052eac3ef26SChristoph Hellwig nvme_start_ctrl(&dev->ctrl); 3053eac3ef26SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 30545a5754a4SKeith Busch flush_work(&dev->ctrl.scan_work); 305557dacad5SJay Sternberg return 0; 305657dacad5SJay Sternberg 3057eac3ef26SChristoph Hellwig out_disable: 3058eac3ef26SChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 3059eac3ef26SChristoph Hellwig nvme_dev_disable(dev, true); 3060eac3ef26SChristoph Hellwig nvme_free_host_mem(dev); 3061eac3ef26SChristoph Hellwig nvme_dev_remove_admin(dev); 3062eac3ef26SChristoph Hellwig nvme_dbbuf_dma_free(dev); 3063eac3ef26SChristoph Hellwig nvme_free_queues(dev, 0); 3064eac3ef26SChristoph Hellwig out_release_iod_mempool: 3065b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 30662e87570bSChristoph Hellwig out_release_prp_pools: 306757dacad5SJay Sternberg nvme_release_prp_pools(dev); 30682e87570bSChristoph Hellwig out_dev_unmap: 306957dacad5SJay Sternberg nvme_dev_unmap(dev); 30702e87570bSChristoph Hellwig out_uninit_ctrl: 30712e87570bSChristoph Hellwig nvme_uninit_ctrl(&dev->ctrl); 307257dacad5SJay Sternberg return result; 307357dacad5SJay Sternberg } 307457dacad5SJay Sternberg 3075775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 307657dacad5SJay Sternberg { 307757dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3078c1ac9a4bSKeith Busch 3079c1ac9a4bSKeith Busch /* 3080c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3081c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3082c1ac9a4bSKeith Busch * with ->remove(). 3083c1ac9a4bSKeith Busch */ 3084c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3085c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3086775755edSChristoph Hellwig } 308757dacad5SJay Sternberg 3088775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3089775755edSChristoph Hellwig { 3090f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3091c1ac9a4bSKeith Busch 3092c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3093c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 309457dacad5SJay Sternberg } 309557dacad5SJay Sternberg 309657dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 309757dacad5SJay Sternberg { 309857dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 30994e523547SBaolin Wang 3100c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 310157dacad5SJay Sternberg } 310257dacad5SJay Sternberg 3103f58944e2SKeith Busch /* 3104f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3105f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3106f58944e2SKeith Busch * order to proceed. 3107f58944e2SKeith Busch */ 310857dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 310957dacad5SJay Sternberg { 311057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 311157dacad5SJay Sternberg 3112bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 311357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 31140ff9d4e1SKeith Busch 31156db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 31160ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 31171d39e692SKeith Busch nvme_dev_disable(dev, true); 31186db28edaSKeith Busch } 31190ff9d4e1SKeith Busch 3120d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3121d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3122d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3123a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 312487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 312557dacad5SJay Sternberg nvme_dev_remove_admin(dev); 3126c11b7716SChristoph Hellwig nvme_dbbuf_dma_free(dev); 312757dacad5SJay Sternberg nvme_free_queues(dev, 0); 3128c11b7716SChristoph Hellwig mempool_destroy(dev->iod_mempool); 312957dacad5SJay Sternberg nvme_release_prp_pools(dev); 3130b00a726aSKeith Busch nvme_dev_unmap(dev); 3131726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 313257dacad5SJay Sternberg } 313357dacad5SJay Sternberg 313457dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3135d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3136d916b1beSKeith Busch { 3137d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3138d916b1beSKeith Busch } 3139d916b1beSKeith Busch 3140d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3141d916b1beSKeith Busch { 3142d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3143d916b1beSKeith Busch } 3144d916b1beSKeith Busch 3145d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3146d916b1beSKeith Busch { 3147d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3148d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3149d916b1beSKeith Busch 31504eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3151d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3152e5ad96f3SKeith Busch goto reset; 3153e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3154e5ad96f3SKeith Busch goto reset; 3155e5ad96f3SKeith Busch 3156d916b1beSKeith Busch return 0; 3157e5ad96f3SKeith Busch reset: 3158e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3159d916b1beSKeith Busch } 3160d916b1beSKeith Busch 316157dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 316257dacad5SJay Sternberg { 316357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 316457dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3165d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3166d916b1beSKeith Busch int ret = -EBUSY; 3167d916b1beSKeith Busch 31684eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 31694eaefe8cSRafael J. Wysocki 3170d916b1beSKeith Busch /* 3171d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3172d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3173d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3174d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3175d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3176d916b1beSKeith Busch * device fully. 31774eaefe8cSRafael J. Wysocki * 31784eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 31794eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 31804eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 31814eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3182d916b1beSKeith Busch */ 31834eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3184cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3185c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3186c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3187d916b1beSKeith Busch 3188d916b1beSKeith Busch nvme_start_freeze(ctrl); 3189d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3190d916b1beSKeith Busch nvme_sync_queues(ctrl); 3191d916b1beSKeith Busch 31925d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3193d916b1beSKeith Busch goto unfreeze; 3194d916b1beSKeith Busch 3195e5ad96f3SKeith Busch /* 3196e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3197e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3198e5ad96f3SKeith Busch * non-operational power state. 3199e5ad96f3SKeith Busch */ 3200e5ad96f3SKeith Busch if (ndev->hmb) { 3201e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3202e5ad96f3SKeith Busch if (ret < 0) 3203e5ad96f3SKeith Busch goto unfreeze; 3204e5ad96f3SKeith Busch } 3205e5ad96f3SKeith Busch 3206d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3207d916b1beSKeith Busch if (ret < 0) 3208d916b1beSKeith Busch goto unfreeze; 3209d916b1beSKeith Busch 32107cbb5c6fSMario Limonciello /* 32117cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 32127cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 32137cbb5c6fSMario Limonciello * want pci interfering. 32147cbb5c6fSMario Limonciello */ 32157cbb5c6fSMario Limonciello pci_save_state(pdev); 32167cbb5c6fSMario Limonciello 3217d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3218d916b1beSKeith Busch if (ret < 0) 3219d916b1beSKeith Busch goto unfreeze; 3220d916b1beSKeith Busch 3221d916b1beSKeith Busch if (ret) { 32227cbb5c6fSMario Limonciello /* discard the saved state */ 32237cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 32247cbb5c6fSMario Limonciello 3225d916b1beSKeith Busch /* 3226d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 322705d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3228d916b1beSKeith Busch */ 3229c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3230d916b1beSKeith Busch ctrl->npss = 0; 3231d916b1beSKeith Busch } 3232d916b1beSKeith Busch unfreeze: 3233d916b1beSKeith Busch nvme_unfreeze(ctrl); 3234d916b1beSKeith Busch return ret; 3235d916b1beSKeith Busch } 3236d916b1beSKeith Busch 3237d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3238d916b1beSKeith Busch { 3239d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 32404e523547SBaolin Wang 3241c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 324257dacad5SJay Sternberg } 324357dacad5SJay Sternberg 3244d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 324557dacad5SJay Sternberg { 324657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 324757dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 324857dacad5SJay Sternberg 3249c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 325057dacad5SJay Sternberg } 325157dacad5SJay Sternberg 325221774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3253d916b1beSKeith Busch .suspend = nvme_suspend, 3254d916b1beSKeith Busch .resume = nvme_resume, 3255d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3256d916b1beSKeith Busch .thaw = nvme_simple_resume, 3257d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3258d916b1beSKeith Busch .restore = nvme_simple_resume, 3259d916b1beSKeith Busch }; 3260d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 326157dacad5SJay Sternberg 3262a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3263a0a3408eSKeith Busch pci_channel_state_t state) 3264a0a3408eSKeith Busch { 3265a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3266a0a3408eSKeith Busch 3267a0a3408eSKeith Busch /* 3268a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3269a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3270a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3271a0a3408eSKeith Busch */ 3272a0a3408eSKeith Busch switch (state) { 3273a0a3408eSKeith Busch case pci_channel_io_normal: 3274a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3275a0a3408eSKeith Busch case pci_channel_io_frozen: 3276d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3277d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3278a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3279a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3280a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3281d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3282d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3283a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3284a0a3408eSKeith Busch } 3285a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3286a0a3408eSKeith Busch } 3287a0a3408eSKeith Busch 3288a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3289a0a3408eSKeith Busch { 3290a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3291a0a3408eSKeith Busch 32921b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3293a0a3408eSKeith Busch pci_restore_state(pdev); 3294d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3295a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3296a0a3408eSKeith Busch } 3297a0a3408eSKeith Busch 3298a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3299a0a3408eSKeith Busch { 330072cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 330172cd4cc2SKeith Busch 330272cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3303a0a3408eSKeith Busch } 3304a0a3408eSKeith Busch 330557dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 330657dacad5SJay Sternberg .error_detected = nvme_error_detected, 330757dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 330857dacad5SJay Sternberg .resume = nvme_error_resume, 3309775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3310775755edSChristoph Hellwig .reset_done = nvme_reset_done, 331157dacad5SJay Sternberg }; 331257dacad5SJay Sternberg 331357dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3314972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 331508095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3316e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3317972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 331899466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3319e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3320972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 332199466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 332225e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 332325e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3324972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3325f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3326f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 332750af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 33289abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 33296c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3330ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3331ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33326299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 33336299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3334540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 33357b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 333666dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 333766dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 333866dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 333966dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 33405bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 3341c98a8793SKeith Busch .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 3342c98a8793SKeith Busch NVME_QUIRK_BOGUS_NID, }, 33430302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 33445e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 33455e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 334654adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 334754adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 33488c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 33498c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3350015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3351015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3352d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3353d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3354d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 33557ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3356abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 33577ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 33582cf7a77eSKeith Busch { PCI_DEVICE(0x1987, 0x5012), /* Phison E12 */ 33592cf7a77eSKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 3360c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 336173029c9bSKeith Busch .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 336273029c9bSKeith Busch NVME_QUIRK_BOGUS_NID, }, 3363d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5019), /* phison E19 */ 3364d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3365d14c2731STina Hsu { PCI_DEVICE(0x1987, 0x5021), /* Phison E21 */ 3366d14c2731STina Hsu .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 33676e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 33686e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 33696e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3370e1c70d79SLamarque Vieira Souza { PCI_DEVICE(0x1cc1, 0x33f8), /* ADATA IM2P33F8ABR1 1 TB */ 3371e1c70d79SLamarque Vieira Souza .driver_data = NVME_QUIRK_BOGUS_NID, }, 337208b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 33731629de0eSPablo Greco .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN | 33741629de0eSPablo Greco NVME_QUIRK_BOGUS_NID, }, 3375f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3376f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3377f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 337841f38043SLeo Savernik { PCI_DEVICE(0x1344, 0x5407), /* Micron Technology Inc NVMe SSD */ 337941f38043SLeo Savernik .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN }, 3380d5ceb4d1SBean Huo { PCI_DEVICE(0x1344, 0x6001), /* Micron Nitro NVMe */ 3381d5ceb4d1SBean Huo .driver_data = NVME_QUIRK_BOGUS_NID, }, 33825611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 33835611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3384c4f01a77SKeith Busch { PCI_DEVICE(0x1c5c, 0x174a), /* SK Hynix P31 SSD */ 3385c4f01a77SKeith Busch .driver_data = NVME_QUIRK_BOGUS_NID, }, 338602ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 338702ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 338889919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 338989919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 339043047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa80b), /* Samsung PM9B1 256G and 512G */ 339143047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 339243047e08Srasheed.hsueh { PCI_DEVICE(0x144d, 0xa809), /* Samsung MZALQ256HBJD 256G */ 339343047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 339443047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6303), /* UMIS RPJTJ512MGE1QDY 512G */ 339543047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 339643047e08Srasheed.hsueh { PCI_DEVICE(0x1cc4, 0x6302), /* UMIS RPJTJ256MGE1QDY 256G */ 339743047e08Srasheed.hsueh .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3398dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3399dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3400538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3401538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3402ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5018), /* KINGSTON OM8SFP4xxxxP OS21012 NVMe SSD */ 3403ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3404ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x5016), /* KINGSTON OM3PGP4xxxxP OS21011 NVMe SSD */ 3405ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3406ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501A), /* KINGSTON OM8PGP4xxxxP OS21005 NVMe SSD */ 3407ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3408ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501B), /* KINGSTON OM8PGP4xxxxQ OS21005 NVMe SSD */ 3409ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3410ac9b57d4SXander Li { PCI_DEVICE(0x2646, 0x501E), /* KINGSTON OM3PGP4xxxxQ OS21011 NVMe SSD */ 3411ac9b57d4SXander Li .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34128d6e38f6STiago Dias Ferreira { PCI_DEVICE(0x1f40, 0x5236), /* Netac Technologies Co. NV7000 NVMe SSD */ 34138d6e38f6STiago Dias Ferreira .driver_data = NVME_QUIRK_BOGUS_NID, }, 341470ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 341570ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3416a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3417a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3418a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3419a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34203765fad5SStefan Reiter { PCI_DEVICE(0x1cc1, 0x5350), /* ADATA XPG GAMMIX S50 */ 34213765fad5SStefan Reiter .driver_data = NVME_QUIRK_BOGUS_NID, }, 3422f37527a0SDennis P. Kliem { PCI_DEVICE(0x1dbe, 0x5236), /* ADATA XPG GAMMIX S70 */ 3423f37527a0SDennis P. Kliem .driver_data = NVME_QUIRK_BOGUS_NID, }, 3424d5d3c100SXi Ruoyao { PCI_DEVICE(0x1e49, 0x0021), /* ZHITAI TiPro5000 NVMe SSD */ 3425d5d3c100SXi Ruoyao .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 34266b961bceSNing Wang { PCI_DEVICE(0x1e49, 0x0041), /* ZHITAI TiPro7000 NVMe SSD */ 34276b961bceSNing Wang .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3428d6c52fa3STobias Gruetzmacher { PCI_DEVICE(0xc0a9, 0x540a), /* Crucial P2 */ 3429d6c52fa3STobias Gruetzmacher .driver_data = NVME_QUIRK_BOGUS_NID, }, 3430200dccd0SShyamin Ayesh { PCI_DEVICE(0x1d97, 0x2263), /* Lexar NM610 */ 3431200dccd0SShyamin Ayesh .driver_data = NVME_QUIRK_BOGUS_NID, }, 343280b26240SAbhijit { PCI_DEVICE(0x1d97, 0x2269), /* Lexar NM760 */ 343380b26240SAbhijit .driver_data = NVME_QUIRK_BOGUS_NID, }, 34344bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 34354bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34364bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 34374bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34384bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 34394bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34404bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 34414bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34424bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 34434bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34444bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 34454bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 344698f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 344798f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3448124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 344966341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 345066341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3451d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3452a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3453453116a4SHector Martin NVME_QUIRK_SKIP_CID_GEN | 3454453116a4SHector Martin NVME_QUIRK_IDENTIFY_CNS }, 34550b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 345657dacad5SJay Sternberg { 0, } 345757dacad5SJay Sternberg }; 345857dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 345957dacad5SJay Sternberg 346057dacad5SJay Sternberg static struct pci_driver nvme_driver = { 346157dacad5SJay Sternberg .name = "nvme", 346257dacad5SJay Sternberg .id_table = nvme_id_table, 346357dacad5SJay Sternberg .probe = nvme_probe, 346457dacad5SJay Sternberg .remove = nvme_remove, 346557dacad5SJay Sternberg .shutdown = nvme_shutdown, 346657dacad5SJay Sternberg .driver = { 3467eac3ef26SChristoph Hellwig .probe_type = PROBE_PREFER_ASYNCHRONOUS, 3468eac3ef26SChristoph Hellwig #ifdef CONFIG_PM_SLEEP 346957dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 3470d916b1beSKeith Busch #endif 3471eac3ef26SChristoph Hellwig }, 347274d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 347357dacad5SJay Sternberg .err_handler = &nvme_err_handler, 347457dacad5SJay Sternberg }; 347557dacad5SJay Sternberg 347657dacad5SJay Sternberg static int __init nvme_init(void) 347757dacad5SJay Sternberg { 347881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 347981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 348081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3481612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 348201df742dSKeith Busch BUILD_BUG_ON(NVME_MAX_SEGS > SGES_PER_PAGE); 3483*7846c1b5SKeith Busch BUILD_BUG_ON(sizeof(struct scatterlist) * NVME_MAX_SEGS > PAGE_SIZE); 3484*7846c1b5SKeith Busch BUILD_BUG_ON(nvme_pci_npages_prp() > NVME_MAX_NR_ALLOCATIONS); 348517c33167SKeith Busch 34869a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 348757dacad5SJay Sternberg } 348857dacad5SJay Sternberg 348957dacad5SJay Sternberg static void __exit nvme_exit(void) 349057dacad5SJay Sternberg { 349157dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 349203e0f3a6SMing Lei flush_workqueue(nvme_wq); 349357dacad5SJay Sternberg } 349457dacad5SJay Sternberg 349557dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 349657dacad5SJay Sternberg MODULE_LICENSE("GPL"); 349757dacad5SJay Sternberg MODULE_VERSION("1.0"); 349857dacad5SJay Sternberg module_init(nvme_init); 349957dacad5SJay Sternberg module_exit(nvme_exit); 3500