15f37396dSChristoph Hellwig // SPDX-License-Identifier: GPL-2.0 257dacad5SJay Sternberg /* 357dacad5SJay Sternberg * NVM Express device driver 457dacad5SJay Sternberg * Copyright (c) 2011-2014, Intel Corporation. 557dacad5SJay Sternberg */ 657dacad5SJay Sternberg 7df4f9bc4SDavid E. Box #include <linux/acpi.h> 8a0a3408eSKeith Busch #include <linux/aer.h> 918119775SKeith Busch #include <linux/async.h> 1057dacad5SJay Sternberg #include <linux/blkdev.h> 1157dacad5SJay Sternberg #include <linux/blk-mq.h> 12dca51e78SChristoph Hellwig #include <linux/blk-mq-pci.h> 13fe45e630SChristoph Hellwig #include <linux/blk-integrity.h> 14ff5350a8SAndy Lutomirski #include <linux/dmi.h> 1557dacad5SJay Sternberg #include <linux/init.h> 1657dacad5SJay Sternberg #include <linux/interrupt.h> 1757dacad5SJay Sternberg #include <linux/io.h> 18dc90f084SChristoph Hellwig #include <linux/memremap.h> 1957dacad5SJay Sternberg #include <linux/mm.h> 2057dacad5SJay Sternberg #include <linux/module.h> 2177bf25eaSKeith Busch #include <linux/mutex.h> 22d0877473SKeith Busch #include <linux/once.h> 2357dacad5SJay Sternberg #include <linux/pci.h> 24d916b1beSKeith Busch #include <linux/suspend.h> 2557dacad5SJay Sternberg #include <linux/t10-pi.h> 2657dacad5SJay Sternberg #include <linux/types.h> 279cf5c095SLinus Torvalds #include <linux/io-64-nonatomic-lo-hi.h> 2820d3bb92SKlaus Jensen #include <linux/io-64-nonatomic-hi-lo.h> 29a98e58e5SScott Bauer #include <linux/sed-opal.h> 300f238ff5SLogan Gunthorpe #include <linux/pci-p2pdma.h> 3157dacad5SJay Sternberg 32604c01d5Syupeng #include "trace.h" 3357dacad5SJay Sternberg #include "nvme.h" 3457dacad5SJay Sternberg 35c1e0cc7eSBenjamin Herrenschmidt #define SQ_SIZE(q) ((q)->q_depth << (q)->sqes) 368a1d09a6SBenjamin Herrenschmidt #define CQ_SIZE(q) ((q)->q_depth * sizeof(struct nvme_completion)) 3757dacad5SJay Sternberg 38a7a7cbe3SChaitanya Kulkarni #define SGES_PER_PAGE (PAGE_SIZE / sizeof(struct nvme_sgl_desc)) 39adf68f21SChristoph Hellwig 40943e942eSJens Axboe /* 41943e942eSJens Axboe * These can be higher, but we need to ensure that any command doesn't 42943e942eSJens Axboe * require an sg allocation that needs more than a page of data. 43943e942eSJens Axboe */ 44943e942eSJens Axboe #define NVME_MAX_KB_SZ 4096 45943e942eSJens Axboe #define NVME_MAX_SEGS 127 46943e942eSJens Axboe 4757dacad5SJay Sternberg static int use_threaded_interrupts; 482e21e445SXin Hao module_param(use_threaded_interrupts, int, 0444); 4957dacad5SJay Sternberg 5057dacad5SJay Sternberg static bool use_cmb_sqes = true; 5169f4eb9fSKeith Busch module_param(use_cmb_sqes, bool, 0444); 5257dacad5SJay Sternberg MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes"); 5357dacad5SJay Sternberg 5487ad72a5SChristoph Hellwig static unsigned int max_host_mem_size_mb = 128; 5587ad72a5SChristoph Hellwig module_param(max_host_mem_size_mb, uint, 0444); 5687ad72a5SChristoph Hellwig MODULE_PARM_DESC(max_host_mem_size_mb, 5787ad72a5SChristoph Hellwig "Maximum Host Memory Buffer (HMB) size per controller (in MiB)"); 5857dacad5SJay Sternberg 59a7a7cbe3SChaitanya Kulkarni static unsigned int sgl_threshold = SZ_32K; 60a7a7cbe3SChaitanya Kulkarni module_param(sgl_threshold, uint, 0644); 61a7a7cbe3SChaitanya Kulkarni MODULE_PARM_DESC(sgl_threshold, 62a7a7cbe3SChaitanya Kulkarni "Use SGLs when average request segment size is larger or equal to " 63a7a7cbe3SChaitanya Kulkarni "this size. Use 0 to disable SGLs."); 64a7a7cbe3SChaitanya Kulkarni 6527453b45SSagi Grimberg #define NVME_PCI_MIN_QUEUE_SIZE 2 6627453b45SSagi Grimberg #define NVME_PCI_MAX_QUEUE_SIZE 4095 67b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp); 68b27c1e68Sweiping zhang static const struct kernel_param_ops io_queue_depth_ops = { 69b27c1e68Sweiping zhang .set = io_queue_depth_set, 7061f3b896SChaitanya Kulkarni .get = param_get_uint, 71b27c1e68Sweiping zhang }; 72b27c1e68Sweiping zhang 7361f3b896SChaitanya Kulkarni static unsigned int io_queue_depth = 1024; 74b27c1e68Sweiping zhang module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644); 7527453b45SSagi Grimberg MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2 and < 4096"); 76b27c1e68Sweiping zhang 779c9e76d5SWeiping Zhang static int io_queue_count_set(const char *val, const struct kernel_param *kp) 789c9e76d5SWeiping Zhang { 799c9e76d5SWeiping Zhang unsigned int n; 809c9e76d5SWeiping Zhang int ret; 819c9e76d5SWeiping Zhang 829c9e76d5SWeiping Zhang ret = kstrtouint(val, 10, &n); 839c9e76d5SWeiping Zhang if (ret != 0 || n > num_possible_cpus()) 849c9e76d5SWeiping Zhang return -EINVAL; 859c9e76d5SWeiping Zhang return param_set_uint(val, kp); 869c9e76d5SWeiping Zhang } 879c9e76d5SWeiping Zhang 889c9e76d5SWeiping Zhang static const struct kernel_param_ops io_queue_count_ops = { 899c9e76d5SWeiping Zhang .set = io_queue_count_set, 909c9e76d5SWeiping Zhang .get = param_get_uint, 919c9e76d5SWeiping Zhang }; 929c9e76d5SWeiping Zhang 933f68baf7SKeith Busch static unsigned int write_queues; 949c9e76d5SWeiping Zhang module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644); 953b6592f7SJens Axboe MODULE_PARM_DESC(write_queues, 963b6592f7SJens Axboe "Number of queues to use for writes. If not set, reads and writes " 973b6592f7SJens Axboe "will share a queue set."); 983b6592f7SJens Axboe 993f68baf7SKeith Busch static unsigned int poll_queues; 1009c9e76d5SWeiping Zhang module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644); 1014b04cc6aSJens Axboe MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO."); 1024b04cc6aSJens Axboe 103df4f9bc4SDavid E. Box static bool noacpi; 104df4f9bc4SDavid E. Box module_param(noacpi, bool, 0444); 105df4f9bc4SDavid E. Box MODULE_PARM_DESC(noacpi, "disable acpi bios quirks"); 106df4f9bc4SDavid E. Box 1071c63dc66SChristoph Hellwig struct nvme_dev; 1081c63dc66SChristoph Hellwig struct nvme_queue; 10957dacad5SJay Sternberg 110a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown); 1118fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode); 11257dacad5SJay Sternberg 11357dacad5SJay Sternberg /* 1141c63dc66SChristoph Hellwig * Represents an NVM Express device. Each nvme_dev is a PCI function. 1151c63dc66SChristoph Hellwig */ 1161c63dc66SChristoph Hellwig struct nvme_dev { 117147b27e4SSagi Grimberg struct nvme_queue *queues; 1181c63dc66SChristoph Hellwig struct blk_mq_tag_set tagset; 1191c63dc66SChristoph Hellwig struct blk_mq_tag_set admin_tagset; 1201c63dc66SChristoph Hellwig u32 __iomem *dbs; 1211c63dc66SChristoph Hellwig struct device *dev; 1221c63dc66SChristoph Hellwig struct dma_pool *prp_page_pool; 1231c63dc66SChristoph Hellwig struct dma_pool *prp_small_pool; 1241c63dc66SChristoph Hellwig unsigned online_queues; 1251c63dc66SChristoph Hellwig unsigned max_qid; 126e20ba6e1SChristoph Hellwig unsigned io_queues[HCTX_MAX_TYPES]; 12722b55601SKeith Busch unsigned int num_vecs; 1287442ddceSJohn Garry u32 q_depth; 129c1e0cc7eSBenjamin Herrenschmidt int io_sqes; 1301c63dc66SChristoph Hellwig u32 db_stride; 1311c63dc66SChristoph Hellwig void __iomem *bar; 13297f6ef64SXu Yu unsigned long bar_mapped_size; 1335c8809e6SChristoph Hellwig struct work_struct remove_work; 13477bf25eaSKeith Busch struct mutex shutdown_lock; 1351c63dc66SChristoph Hellwig bool subsystem; 1361c63dc66SChristoph Hellwig u64 cmb_size; 1370f238ff5SLogan Gunthorpe bool cmb_use_sqes; 1381c63dc66SChristoph Hellwig u32 cmbsz; 139202021c1SStephen Bates u32 cmbloc; 1401c63dc66SChristoph Hellwig struct nvme_ctrl ctrl; 141d916b1beSKeith Busch u32 last_ps; 142a5df5e79SKeith Busch bool hmb; 14387ad72a5SChristoph Hellwig 144943e942eSJens Axboe mempool_t *iod_mempool; 145943e942eSJens Axboe 14687ad72a5SChristoph Hellwig /* shadow doorbell buffer support: */ 147f9f38e33SHelen Koike u32 *dbbuf_dbs; 148f9f38e33SHelen Koike dma_addr_t dbbuf_dbs_dma_addr; 149f9f38e33SHelen Koike u32 *dbbuf_eis; 150f9f38e33SHelen Koike dma_addr_t dbbuf_eis_dma_addr; 15187ad72a5SChristoph Hellwig 15287ad72a5SChristoph Hellwig /* host memory buffer support: */ 15387ad72a5SChristoph Hellwig u64 host_mem_size; 15487ad72a5SChristoph Hellwig u32 nr_host_mem_descs; 1554033f35dSChristoph Hellwig dma_addr_t host_mem_descs_dma; 15687ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *host_mem_descs; 15787ad72a5SChristoph Hellwig void **host_mem_desc_bufs; 1582a5bcfddSWeiping Zhang unsigned int nr_allocated_queues; 1592a5bcfddSWeiping Zhang unsigned int nr_write_queues; 1602a5bcfddSWeiping Zhang unsigned int nr_poll_queues; 1610521905eSKeith Busch 1620521905eSKeith Busch bool attrs_added; 16357dacad5SJay Sternberg }; 16457dacad5SJay Sternberg 165b27c1e68Sweiping zhang static int io_queue_depth_set(const char *val, const struct kernel_param *kp) 166b27c1e68Sweiping zhang { 16727453b45SSagi Grimberg return param_set_uint_minmax(val, kp, NVME_PCI_MIN_QUEUE_SIZE, 16827453b45SSagi Grimberg NVME_PCI_MAX_QUEUE_SIZE); 169b27c1e68Sweiping zhang } 170b27c1e68Sweiping zhang 171f9f38e33SHelen Koike static inline unsigned int sq_idx(unsigned int qid, u32 stride) 172f9f38e33SHelen Koike { 173f9f38e33SHelen Koike return qid * 2 * stride; 174f9f38e33SHelen Koike } 175f9f38e33SHelen Koike 176f9f38e33SHelen Koike static inline unsigned int cq_idx(unsigned int qid, u32 stride) 177f9f38e33SHelen Koike { 178f9f38e33SHelen Koike return (qid * 2 + 1) * stride; 179f9f38e33SHelen Koike } 180f9f38e33SHelen Koike 1811c63dc66SChristoph Hellwig static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl) 1821c63dc66SChristoph Hellwig { 1831c63dc66SChristoph Hellwig return container_of(ctrl, struct nvme_dev, ctrl); 1841c63dc66SChristoph Hellwig } 1851c63dc66SChristoph Hellwig 18657dacad5SJay Sternberg /* 18757dacad5SJay Sternberg * An NVM Express queue. Each device has at least two (one for admin 18857dacad5SJay Sternberg * commands and one for I/O commands). 18957dacad5SJay Sternberg */ 19057dacad5SJay Sternberg struct nvme_queue { 19157dacad5SJay Sternberg struct nvme_dev *dev; 1921ab0cd69SJens Axboe spinlock_t sq_lock; 193c1e0cc7eSBenjamin Herrenschmidt void *sq_cmds; 1943a7afd8eSChristoph Hellwig /* only used for poll queues: */ 1953a7afd8eSChristoph Hellwig spinlock_t cq_poll_lock ____cacheline_aligned_in_smp; 19674943d45SKeith Busch struct nvme_completion *cqes; 19757dacad5SJay Sternberg dma_addr_t sq_dma_addr; 19857dacad5SJay Sternberg dma_addr_t cq_dma_addr; 19957dacad5SJay Sternberg u32 __iomem *q_db; 2007442ddceSJohn Garry u32 q_depth; 2017c349ddeSKeith Busch u16 cq_vector; 20257dacad5SJay Sternberg u16 sq_tail; 20338210800SKeith Busch u16 last_sq_tail; 20457dacad5SJay Sternberg u16 cq_head; 20557dacad5SJay Sternberg u16 qid; 20657dacad5SJay Sternberg u8 cq_phase; 207c1e0cc7eSBenjamin Herrenschmidt u8 sqes; 2084e224106SChristoph Hellwig unsigned long flags; 2094e224106SChristoph Hellwig #define NVMEQ_ENABLED 0 21063223078SChristoph Hellwig #define NVMEQ_SQ_CMB 1 211d1ed6aa1SChristoph Hellwig #define NVMEQ_DELETE_ERROR 2 2127c349ddeSKeith Busch #define NVMEQ_POLLED 3 213f9f38e33SHelen Koike u32 *dbbuf_sq_db; 214f9f38e33SHelen Koike u32 *dbbuf_cq_db; 215f9f38e33SHelen Koike u32 *dbbuf_sq_ei; 216f9f38e33SHelen Koike u32 *dbbuf_cq_ei; 217d1ed6aa1SChristoph Hellwig struct completion delete_done; 21857dacad5SJay Sternberg }; 21957dacad5SJay Sternberg 22057dacad5SJay Sternberg /* 2219b048119SChristoph Hellwig * The nvme_iod describes the data in an I/O. 2229b048119SChristoph Hellwig * 2239b048119SChristoph Hellwig * The sg pointer contains the list of PRP/SGL chunk allocations in addition 2249b048119SChristoph Hellwig * to the actual struct scatterlist. 22571bd150cSChristoph Hellwig */ 22671bd150cSChristoph Hellwig struct nvme_iod { 227d49187e9SChristoph Hellwig struct nvme_request req; 228af7fae85SKeith Busch struct nvme_command cmd; 229f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq; 230a7a7cbe3SChaitanya Kulkarni bool use_sgl; 231f4800d6dSChristoph Hellwig int aborted; 23271bd150cSChristoph Hellwig int npages; /* In the PRP list. 0 means small pool in use */ 23371bd150cSChristoph Hellwig int nents; /* Used in scatterlist */ 23471bd150cSChristoph Hellwig dma_addr_t first_dma; 235dff824b2SChristoph Hellwig unsigned int dma_len; /* length of single DMA segment mapping */ 236783b94bdSChristoph Hellwig dma_addr_t meta_dma; 237f4800d6dSChristoph Hellwig struct scatterlist *sg; 23857dacad5SJay Sternberg }; 23957dacad5SJay Sternberg 2402a5bcfddSWeiping Zhang static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev) 2413b6592f7SJens Axboe { 2422a5bcfddSWeiping Zhang return dev->nr_allocated_queues * 8 * dev->db_stride; 243f9f38e33SHelen Koike } 244f9f38e33SHelen Koike 245f9f38e33SHelen Koike static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev) 246f9f38e33SHelen Koike { 2472a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 248f9f38e33SHelen Koike 24958847f12SKeith Busch if (dev->dbbuf_dbs) { 25058847f12SKeith Busch /* 25158847f12SKeith Busch * Clear the dbbuf memory so the driver doesn't observe stale 25258847f12SKeith Busch * values from the previous instantiation. 25358847f12SKeith Busch */ 25458847f12SKeith Busch memset(dev->dbbuf_dbs, 0, mem_size); 25558847f12SKeith Busch memset(dev->dbbuf_eis, 0, mem_size); 256f9f38e33SHelen Koike return 0; 25758847f12SKeith Busch } 258f9f38e33SHelen Koike 259f9f38e33SHelen Koike dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size, 260f9f38e33SHelen Koike &dev->dbbuf_dbs_dma_addr, 261f9f38e33SHelen Koike GFP_KERNEL); 262f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 263f9f38e33SHelen Koike return -ENOMEM; 264f9f38e33SHelen Koike dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size, 265f9f38e33SHelen Koike &dev->dbbuf_eis_dma_addr, 266f9f38e33SHelen Koike GFP_KERNEL); 267f9f38e33SHelen Koike if (!dev->dbbuf_eis) { 268f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 269f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 270f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 271f9f38e33SHelen Koike return -ENOMEM; 272f9f38e33SHelen Koike } 273f9f38e33SHelen Koike 274f9f38e33SHelen Koike return 0; 275f9f38e33SHelen Koike } 276f9f38e33SHelen Koike 277f9f38e33SHelen Koike static void nvme_dbbuf_dma_free(struct nvme_dev *dev) 278f9f38e33SHelen Koike { 2792a5bcfddSWeiping Zhang unsigned int mem_size = nvme_dbbuf_size(dev); 280f9f38e33SHelen Koike 281f9f38e33SHelen Koike if (dev->dbbuf_dbs) { 282f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 283f9f38e33SHelen Koike dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr); 284f9f38e33SHelen Koike dev->dbbuf_dbs = NULL; 285f9f38e33SHelen Koike } 286f9f38e33SHelen Koike if (dev->dbbuf_eis) { 287f9f38e33SHelen Koike dma_free_coherent(dev->dev, mem_size, 288f9f38e33SHelen Koike dev->dbbuf_eis, dev->dbbuf_eis_dma_addr); 289f9f38e33SHelen Koike dev->dbbuf_eis = NULL; 290f9f38e33SHelen Koike } 291f9f38e33SHelen Koike } 292f9f38e33SHelen Koike 293f9f38e33SHelen Koike static void nvme_dbbuf_init(struct nvme_dev *dev, 294f9f38e33SHelen Koike struct nvme_queue *nvmeq, int qid) 295f9f38e33SHelen Koike { 296f9f38e33SHelen Koike if (!dev->dbbuf_dbs || !qid) 297f9f38e33SHelen Koike return; 298f9f38e33SHelen Koike 299f9f38e33SHelen Koike nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)]; 300f9f38e33SHelen Koike nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)]; 301f9f38e33SHelen Koike nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)]; 302f9f38e33SHelen Koike nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)]; 303f9f38e33SHelen Koike } 304f9f38e33SHelen Koike 3050f0d2c87SMinwoo Im static void nvme_dbbuf_free(struct nvme_queue *nvmeq) 3060f0d2c87SMinwoo Im { 3070f0d2c87SMinwoo Im if (!nvmeq->qid) 3080f0d2c87SMinwoo Im return; 3090f0d2c87SMinwoo Im 3100f0d2c87SMinwoo Im nvmeq->dbbuf_sq_db = NULL; 3110f0d2c87SMinwoo Im nvmeq->dbbuf_cq_db = NULL; 3120f0d2c87SMinwoo Im nvmeq->dbbuf_sq_ei = NULL; 3130f0d2c87SMinwoo Im nvmeq->dbbuf_cq_ei = NULL; 3140f0d2c87SMinwoo Im } 3150f0d2c87SMinwoo Im 316f9f38e33SHelen Koike static void nvme_dbbuf_set(struct nvme_dev *dev) 317f9f38e33SHelen Koike { 318f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 3190f0d2c87SMinwoo Im unsigned int i; 320f9f38e33SHelen Koike 321f9f38e33SHelen Koike if (!dev->dbbuf_dbs) 322f9f38e33SHelen Koike return; 323f9f38e33SHelen Koike 324f9f38e33SHelen Koike c.dbbuf.opcode = nvme_admin_dbbuf; 325f9f38e33SHelen Koike c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr); 326f9f38e33SHelen Koike c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr); 327f9f38e33SHelen Koike 328f9f38e33SHelen Koike if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) { 3299bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "unable to set dbbuf\n"); 330f9f38e33SHelen Koike /* Free memory and continue on */ 331f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 3320f0d2c87SMinwoo Im 3330f0d2c87SMinwoo Im for (i = 1; i <= dev->online_queues; i++) 3340f0d2c87SMinwoo Im nvme_dbbuf_free(&dev->queues[i]); 335f9f38e33SHelen Koike } 336f9f38e33SHelen Koike } 337f9f38e33SHelen Koike 338f9f38e33SHelen Koike static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old) 339f9f38e33SHelen Koike { 340f9f38e33SHelen Koike return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old); 341f9f38e33SHelen Koike } 342f9f38e33SHelen Koike 343f9f38e33SHelen Koike /* Update dbbuf and return true if an MMIO is required */ 344f9f38e33SHelen Koike static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db, 345f9f38e33SHelen Koike volatile u32 *dbbuf_ei) 346f9f38e33SHelen Koike { 347f9f38e33SHelen Koike if (dbbuf_db) { 348f9f38e33SHelen Koike u16 old_value; 349f9f38e33SHelen Koike 350f9f38e33SHelen Koike /* 351f9f38e33SHelen Koike * Ensure that the queue is written before updating 352f9f38e33SHelen Koike * the doorbell in memory 353f9f38e33SHelen Koike */ 354f9f38e33SHelen Koike wmb(); 355f9f38e33SHelen Koike 356f9f38e33SHelen Koike old_value = *dbbuf_db; 357f9f38e33SHelen Koike *dbbuf_db = value; 358f9f38e33SHelen Koike 359f1ed3df2SMichal Wnukowski /* 360f1ed3df2SMichal Wnukowski * Ensure that the doorbell is updated before reading the event 361f1ed3df2SMichal Wnukowski * index from memory. The controller needs to provide similar 362f1ed3df2SMichal Wnukowski * ordering to ensure the envent index is updated before reading 363f1ed3df2SMichal Wnukowski * the doorbell. 364f1ed3df2SMichal Wnukowski */ 365f1ed3df2SMichal Wnukowski mb(); 366f1ed3df2SMichal Wnukowski 367f9f38e33SHelen Koike if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value)) 368f9f38e33SHelen Koike return false; 369f9f38e33SHelen Koike } 370f9f38e33SHelen Koike 371f9f38e33SHelen Koike return true; 37257dacad5SJay Sternberg } 37357dacad5SJay Sternberg 37457dacad5SJay Sternberg /* 37557dacad5SJay Sternberg * Will slightly overestimate the number of pages needed. This is OK 37657dacad5SJay Sternberg * as it only leads to a small amount of wasted memory for the lifetime of 37757dacad5SJay Sternberg * the I/O. 37857dacad5SJay Sternberg */ 379b13c6393SChaitanya Kulkarni static int nvme_pci_npages_prp(void) 38057dacad5SJay Sternberg { 381b13c6393SChaitanya Kulkarni unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE, 3826c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 38357dacad5SJay Sternberg return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8); 38457dacad5SJay Sternberg } 38557dacad5SJay Sternberg 386a7a7cbe3SChaitanya Kulkarni /* 387a7a7cbe3SChaitanya Kulkarni * Calculates the number of pages needed for the SGL segments. For example a 4k 388a7a7cbe3SChaitanya Kulkarni * page can accommodate 256 SGL descriptors. 389a7a7cbe3SChaitanya Kulkarni */ 390b13c6393SChaitanya Kulkarni static int nvme_pci_npages_sgl(void) 391f4800d6dSChristoph Hellwig { 392b13c6393SChaitanya Kulkarni return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc), 393b13c6393SChaitanya Kulkarni PAGE_SIZE); 394f4800d6dSChristoph Hellwig } 395f4800d6dSChristoph Hellwig 396b13c6393SChaitanya Kulkarni static size_t nvme_pci_iod_alloc_size(void) 39757dacad5SJay Sternberg { 398b13c6393SChaitanya Kulkarni size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl()); 399a7a7cbe3SChaitanya Kulkarni 400b13c6393SChaitanya Kulkarni return sizeof(__le64 *) * npages + 401b13c6393SChaitanya Kulkarni sizeof(struct scatterlist) * NVME_MAX_SEGS; 402a7a7cbe3SChaitanya Kulkarni } 403a7a7cbe3SChaitanya Kulkarni 40457dacad5SJay Sternberg static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 40557dacad5SJay Sternberg unsigned int hctx_idx) 40657dacad5SJay Sternberg { 40757dacad5SJay Sternberg struct nvme_dev *dev = data; 408147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 40957dacad5SJay Sternberg 41057dacad5SJay Sternberg WARN_ON(hctx_idx != 0); 41157dacad5SJay Sternberg WARN_ON(dev->admin_tagset.tags[0] != hctx->tags); 41257dacad5SJay Sternberg 41357dacad5SJay Sternberg hctx->driver_data = nvmeq; 41457dacad5SJay Sternberg return 0; 41557dacad5SJay Sternberg } 41657dacad5SJay Sternberg 41757dacad5SJay Sternberg static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data, 41857dacad5SJay Sternberg unsigned int hctx_idx) 41957dacad5SJay Sternberg { 42057dacad5SJay Sternberg struct nvme_dev *dev = data; 421147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1]; 42257dacad5SJay Sternberg 42357dacad5SJay Sternberg WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags); 42457dacad5SJay Sternberg hctx->driver_data = nvmeq; 42557dacad5SJay Sternberg return 0; 42657dacad5SJay Sternberg } 42757dacad5SJay Sternberg 428e559398fSChristoph Hellwig static int nvme_pci_init_request(struct blk_mq_tag_set *set, 429e559398fSChristoph Hellwig struct request *req, unsigned int hctx_idx, 430e559398fSChristoph Hellwig unsigned int numa_node) 43157dacad5SJay Sternberg { 432d6296d39SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 433f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 4340350815aSChristoph Hellwig int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0; 435147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[queue_idx]; 43657dacad5SJay Sternberg 43757dacad5SJay Sternberg BUG_ON(!nvmeq); 438f4800d6dSChristoph Hellwig iod->nvmeq = nvmeq; 43959e29ce6SSagi Grimberg 44059e29ce6SSagi Grimberg nvme_req(req)->ctrl = &dev->ctrl; 441f4b9e6c9SKeith Busch nvme_req(req)->cmd = &iod->cmd; 44257dacad5SJay Sternberg return 0; 44357dacad5SJay Sternberg } 44457dacad5SJay Sternberg 4453b6592f7SJens Axboe static int queue_irq_offset(struct nvme_dev *dev) 4463b6592f7SJens Axboe { 4473b6592f7SJens Axboe /* if we have more than 1 vec, admin queue offsets us by 1 */ 4483b6592f7SJens Axboe if (dev->num_vecs > 1) 4493b6592f7SJens Axboe return 1; 4503b6592f7SJens Axboe 4513b6592f7SJens Axboe return 0; 4523b6592f7SJens Axboe } 4533b6592f7SJens Axboe 454dca51e78SChristoph Hellwig static int nvme_pci_map_queues(struct blk_mq_tag_set *set) 455dca51e78SChristoph Hellwig { 456dca51e78SChristoph Hellwig struct nvme_dev *dev = set->driver_data; 4573b6592f7SJens Axboe int i, qoff, offset; 458dca51e78SChristoph Hellwig 4593b6592f7SJens Axboe offset = queue_irq_offset(dev); 4603b6592f7SJens Axboe for (i = 0, qoff = 0; i < set->nr_maps; i++) { 4613b6592f7SJens Axboe struct blk_mq_queue_map *map = &set->map[i]; 4623b6592f7SJens Axboe 4633b6592f7SJens Axboe map->nr_queues = dev->io_queues[i]; 4643b6592f7SJens Axboe if (!map->nr_queues) { 465e20ba6e1SChristoph Hellwig BUG_ON(i == HCTX_TYPE_DEFAULT); 4667e849dd9SChristoph Hellwig continue; 4673b6592f7SJens Axboe } 4683b6592f7SJens Axboe 4694b04cc6aSJens Axboe /* 4704b04cc6aSJens Axboe * The poll queue(s) doesn't have an IRQ (and hence IRQ 4714b04cc6aSJens Axboe * affinity), so use the regular blk-mq cpu mapping 4724b04cc6aSJens Axboe */ 4733b6592f7SJens Axboe map->queue_offset = qoff; 474cb9e0e50SKeith Busch if (i != HCTX_TYPE_POLL && offset) 4753b6592f7SJens Axboe blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset); 4764b04cc6aSJens Axboe else 4774b04cc6aSJens Axboe blk_mq_map_queues(map); 4783b6592f7SJens Axboe qoff += map->nr_queues; 4793b6592f7SJens Axboe offset += map->nr_queues; 4803b6592f7SJens Axboe } 4813b6592f7SJens Axboe 4823b6592f7SJens Axboe return 0; 483dca51e78SChristoph Hellwig } 484dca51e78SChristoph Hellwig 48538210800SKeith Busch /* 48638210800SKeith Busch * Write sq tail if we are asked to, or if the next command would wrap. 48738210800SKeith Busch */ 48838210800SKeith Busch static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq) 48904f3eafdSJens Axboe { 49038210800SKeith Busch if (!write_sq) { 49138210800SKeith Busch u16 next_tail = nvmeq->sq_tail + 1; 49238210800SKeith Busch 49338210800SKeith Busch if (next_tail == nvmeq->q_depth) 49438210800SKeith Busch next_tail = 0; 49538210800SKeith Busch if (next_tail != nvmeq->last_sq_tail) 49638210800SKeith Busch return; 49738210800SKeith Busch } 49838210800SKeith Busch 49904f3eafdSJens Axboe if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail, 50004f3eafdSJens Axboe nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei)) 50104f3eafdSJens Axboe writel(nvmeq->sq_tail, nvmeq->q_db); 50238210800SKeith Busch nvmeq->last_sq_tail = nvmeq->sq_tail; 50304f3eafdSJens Axboe } 50404f3eafdSJens Axboe 5053233b94cSJens Axboe static inline void nvme_sq_copy_cmd(struct nvme_queue *nvmeq, 5063233b94cSJens Axboe struct nvme_command *cmd) 50757dacad5SJay Sternberg { 508c1e0cc7eSBenjamin Herrenschmidt memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes), 5093233b94cSJens Axboe absolute_pointer(cmd), sizeof(*cmd)); 51090ea5ca4SChristoph Hellwig if (++nvmeq->sq_tail == nvmeq->q_depth) 51190ea5ca4SChristoph Hellwig nvmeq->sq_tail = 0; 51204f3eafdSJens Axboe } 51304f3eafdSJens Axboe 51404f3eafdSJens Axboe static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx) 51504f3eafdSJens Axboe { 51604f3eafdSJens Axboe struct nvme_queue *nvmeq = hctx->driver_data; 51704f3eafdSJens Axboe 51804f3eafdSJens Axboe spin_lock(&nvmeq->sq_lock); 51938210800SKeith Busch if (nvmeq->sq_tail != nvmeq->last_sq_tail) 52038210800SKeith Busch nvme_write_sq_db(nvmeq, true); 52190ea5ca4SChristoph Hellwig spin_unlock(&nvmeq->sq_lock); 52257dacad5SJay Sternberg } 52357dacad5SJay Sternberg 524a7a7cbe3SChaitanya Kulkarni static void **nvme_pci_iod_list(struct request *req) 52557dacad5SJay Sternberg { 526f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 527a7a7cbe3SChaitanya Kulkarni return (void **)(iod->sg + blk_rq_nr_phys_segments(req)); 52857dacad5SJay Sternberg } 52957dacad5SJay Sternberg 530955b1b5aSMinwoo Im static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req) 531955b1b5aSMinwoo Im { 532955b1b5aSMinwoo Im struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 53320469a37SKeith Busch int nseg = blk_rq_nr_phys_segments(req); 534955b1b5aSMinwoo Im unsigned int avg_seg_size; 535955b1b5aSMinwoo Im 53620469a37SKeith Busch avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg); 537955b1b5aSMinwoo Im 538253a0b76SChaitanya Kulkarni if (!nvme_ctrl_sgl_supported(&dev->ctrl)) 539955b1b5aSMinwoo Im return false; 540955b1b5aSMinwoo Im if (!iod->nvmeq->qid) 541955b1b5aSMinwoo Im return false; 542955b1b5aSMinwoo Im if (!sgl_threshold || avg_seg_size < sgl_threshold) 543955b1b5aSMinwoo Im return false; 544955b1b5aSMinwoo Im return true; 545955b1b5aSMinwoo Im } 546955b1b5aSMinwoo Im 5479275c206SChristoph Hellwig static void nvme_free_prps(struct nvme_dev *dev, struct request *req) 54857dacad5SJay Sternberg { 5496c3c05b0SChaitanya Kulkarni const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1; 5509275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5519275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 55257dacad5SJay Sternberg int i; 55357dacad5SJay Sternberg 5549275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5559275c206SChristoph Hellwig __le64 *prp_list = nvme_pci_iod_list(req)[i]; 5569275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]); 5579275c206SChristoph Hellwig 5589275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, prp_list, dma_addr); 5599275c206SChristoph Hellwig dma_addr = next_dma_addr; 560dff824b2SChristoph Hellwig } 5619275c206SChristoph Hellwig } 5629275c206SChristoph Hellwig 5639275c206SChristoph Hellwig static void nvme_free_sgls(struct nvme_dev *dev, struct request *req) 5649275c206SChristoph Hellwig { 5659275c206SChristoph Hellwig const int last_sg = SGES_PER_PAGE - 1; 5669275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5679275c206SChristoph Hellwig dma_addr_t dma_addr = iod->first_dma; 5689275c206SChristoph Hellwig int i; 5699275c206SChristoph Hellwig 5709275c206SChristoph Hellwig for (i = 0; i < iod->npages; i++) { 5719275c206SChristoph Hellwig struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i]; 5729275c206SChristoph Hellwig dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr); 5739275c206SChristoph Hellwig 5749275c206SChristoph Hellwig dma_pool_free(dev->prp_page_pool, sg_list, dma_addr); 5759275c206SChristoph Hellwig dma_addr = next_dma_addr; 5769275c206SChristoph Hellwig } 5779275c206SChristoph Hellwig } 5789275c206SChristoph Hellwig 5799275c206SChristoph Hellwig static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req) 5809275c206SChristoph Hellwig { 5819275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 582dff824b2SChristoph Hellwig 5837f73eac3SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 5847f73eac3SLogan Gunthorpe pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents, 5857f73eac3SLogan Gunthorpe rq_dma_dir(req)); 5867f73eac3SLogan Gunthorpe else 587dff824b2SChristoph Hellwig dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req)); 5889275c206SChristoph Hellwig } 5897fe07d14SChristoph Hellwig 5909275c206SChristoph Hellwig static void nvme_unmap_data(struct nvme_dev *dev, struct request *req) 5919275c206SChristoph Hellwig { 5929275c206SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 5937fe07d14SChristoph Hellwig 5949275c206SChristoph Hellwig if (iod->dma_len) { 5959275c206SChristoph Hellwig dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len, 5969275c206SChristoph Hellwig rq_dma_dir(req)); 5979275c206SChristoph Hellwig return; 5989275c206SChristoph Hellwig } 5999275c206SChristoph Hellwig 6009275c206SChristoph Hellwig WARN_ON_ONCE(!iod->nents); 6019275c206SChristoph Hellwig 6029275c206SChristoph Hellwig nvme_unmap_sg(dev, req); 60357dacad5SJay Sternberg if (iod->npages == 0) 604a7a7cbe3SChaitanya Kulkarni dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0], 6059275c206SChristoph Hellwig iod->first_dma); 6069275c206SChristoph Hellwig else if (iod->use_sgl) 6079275c206SChristoph Hellwig nvme_free_sgls(dev, req); 6089275c206SChristoph Hellwig else 6099275c206SChristoph Hellwig nvme_free_prps(dev, req); 610943e942eSJens Axboe mempool_free(iod->sg, dev->iod_mempool); 61157dacad5SJay Sternberg } 61257dacad5SJay Sternberg 613d0877473SKeith Busch static void nvme_print_sgl(struct scatterlist *sgl, int nents) 614d0877473SKeith Busch { 615d0877473SKeith Busch int i; 616d0877473SKeith Busch struct scatterlist *sg; 617d0877473SKeith Busch 618d0877473SKeith Busch for_each_sg(sgl, sg, nents, i) { 619d0877473SKeith Busch dma_addr_t phys = sg_phys(sg); 620d0877473SKeith Busch pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d " 621d0877473SKeith Busch "dma_address:%pad dma_length:%d\n", 622d0877473SKeith Busch i, &phys, sg->offset, sg->length, &sg_dma_address(sg), 623d0877473SKeith Busch sg_dma_len(sg)); 624d0877473SKeith Busch } 625d0877473SKeith Busch } 626d0877473SKeith Busch 627a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev, 628a7a7cbe3SChaitanya Kulkarni struct request *req, struct nvme_rw_command *cmnd) 62957dacad5SJay Sternberg { 630f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 63157dacad5SJay Sternberg struct dma_pool *pool; 632b131c61dSChristoph Hellwig int length = blk_rq_payload_bytes(req); 63357dacad5SJay Sternberg struct scatterlist *sg = iod->sg; 63457dacad5SJay Sternberg int dma_len = sg_dma_len(sg); 63557dacad5SJay Sternberg u64 dma_addr = sg_dma_address(sg); 6366c3c05b0SChaitanya Kulkarni int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1); 63757dacad5SJay Sternberg __le64 *prp_list; 638a7a7cbe3SChaitanya Kulkarni void **list = nvme_pci_iod_list(req); 63957dacad5SJay Sternberg dma_addr_t prp_dma; 64057dacad5SJay Sternberg int nprps, i; 64157dacad5SJay Sternberg 6426c3c05b0SChaitanya Kulkarni length -= (NVME_CTRL_PAGE_SIZE - offset); 6435228b328SJan H. Schönherr if (length <= 0) { 6445228b328SJan H. Schönherr iod->first_dma = 0; 645a7a7cbe3SChaitanya Kulkarni goto done; 6465228b328SJan H. Schönherr } 64757dacad5SJay Sternberg 6486c3c05b0SChaitanya Kulkarni dma_len -= (NVME_CTRL_PAGE_SIZE - offset); 64957dacad5SJay Sternberg if (dma_len) { 6506c3c05b0SChaitanya Kulkarni dma_addr += (NVME_CTRL_PAGE_SIZE - offset); 65157dacad5SJay Sternberg } else { 65257dacad5SJay Sternberg sg = sg_next(sg); 65357dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 65457dacad5SJay Sternberg dma_len = sg_dma_len(sg); 65557dacad5SJay Sternberg } 65657dacad5SJay Sternberg 6576c3c05b0SChaitanya Kulkarni if (length <= NVME_CTRL_PAGE_SIZE) { 65857dacad5SJay Sternberg iod->first_dma = dma_addr; 659a7a7cbe3SChaitanya Kulkarni goto done; 66057dacad5SJay Sternberg } 66157dacad5SJay Sternberg 6626c3c05b0SChaitanya Kulkarni nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE); 66357dacad5SJay Sternberg if (nprps <= (256 / 8)) { 66457dacad5SJay Sternberg pool = dev->prp_small_pool; 66557dacad5SJay Sternberg iod->npages = 0; 66657dacad5SJay Sternberg } else { 66757dacad5SJay Sternberg pool = dev->prp_page_pool; 66857dacad5SJay Sternberg iod->npages = 1; 66957dacad5SJay Sternberg } 67057dacad5SJay Sternberg 67169d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 67257dacad5SJay Sternberg if (!prp_list) { 67357dacad5SJay Sternberg iod->first_dma = dma_addr; 67457dacad5SJay Sternberg iod->npages = -1; 67586eea289SKeith Busch return BLK_STS_RESOURCE; 67657dacad5SJay Sternberg } 67757dacad5SJay Sternberg list[0] = prp_list; 67857dacad5SJay Sternberg iod->first_dma = prp_dma; 67957dacad5SJay Sternberg i = 0; 68057dacad5SJay Sternberg for (;;) { 6816c3c05b0SChaitanya Kulkarni if (i == NVME_CTRL_PAGE_SIZE >> 3) { 68257dacad5SJay Sternberg __le64 *old_prp_list = prp_list; 68369d2b571SChristoph Hellwig prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma); 68457dacad5SJay Sternberg if (!prp_list) 685fa073216SChristoph Hellwig goto free_prps; 68657dacad5SJay Sternberg list[iod->npages++] = prp_list; 68757dacad5SJay Sternberg prp_list[0] = old_prp_list[i - 1]; 68857dacad5SJay Sternberg old_prp_list[i - 1] = cpu_to_le64(prp_dma); 68957dacad5SJay Sternberg i = 1; 69057dacad5SJay Sternberg } 69157dacad5SJay Sternberg prp_list[i++] = cpu_to_le64(dma_addr); 6926c3c05b0SChaitanya Kulkarni dma_len -= NVME_CTRL_PAGE_SIZE; 6936c3c05b0SChaitanya Kulkarni dma_addr += NVME_CTRL_PAGE_SIZE; 6946c3c05b0SChaitanya Kulkarni length -= NVME_CTRL_PAGE_SIZE; 69557dacad5SJay Sternberg if (length <= 0) 69657dacad5SJay Sternberg break; 69757dacad5SJay Sternberg if (dma_len > 0) 69857dacad5SJay Sternberg continue; 69986eea289SKeith Busch if (unlikely(dma_len < 0)) 70086eea289SKeith Busch goto bad_sgl; 70157dacad5SJay Sternberg sg = sg_next(sg); 70257dacad5SJay Sternberg dma_addr = sg_dma_address(sg); 70357dacad5SJay Sternberg dma_len = sg_dma_len(sg); 70457dacad5SJay Sternberg } 705a7a7cbe3SChaitanya Kulkarni done: 706a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg)); 707a7a7cbe3SChaitanya Kulkarni cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma); 70886eea289SKeith Busch return BLK_STS_OK; 709fa073216SChristoph Hellwig free_prps: 710fa073216SChristoph Hellwig nvme_free_prps(dev, req); 711fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 71286eea289SKeith Busch bad_sgl: 713d0877473SKeith Busch WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents), 714d0877473SKeith Busch "Invalid SGL for payload:%d nents:%d\n", 715d0877473SKeith Busch blk_rq_payload_bytes(req), iod->nents); 71686eea289SKeith Busch return BLK_STS_IOERR; 71757dacad5SJay Sternberg } 71857dacad5SJay Sternberg 719a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge, 720a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg) 721a7a7cbe3SChaitanya Kulkarni { 722a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(sg_dma_address(sg)); 723a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(sg_dma_len(sg)); 724a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_DATA_DESC << 4; 725a7a7cbe3SChaitanya Kulkarni } 726a7a7cbe3SChaitanya Kulkarni 727a7a7cbe3SChaitanya Kulkarni static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge, 728a7a7cbe3SChaitanya Kulkarni dma_addr_t dma_addr, int entries) 729a7a7cbe3SChaitanya Kulkarni { 730a7a7cbe3SChaitanya Kulkarni sge->addr = cpu_to_le64(dma_addr); 731a7a7cbe3SChaitanya Kulkarni if (entries < SGES_PER_PAGE) { 732a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(entries * sizeof(*sge)); 733a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4; 734a7a7cbe3SChaitanya Kulkarni } else { 735a7a7cbe3SChaitanya Kulkarni sge->length = cpu_to_le32(PAGE_SIZE); 736a7a7cbe3SChaitanya Kulkarni sge->type = NVME_SGL_FMT_SEG_DESC << 4; 737a7a7cbe3SChaitanya Kulkarni } 738a7a7cbe3SChaitanya Kulkarni } 739a7a7cbe3SChaitanya Kulkarni 740a7a7cbe3SChaitanya Kulkarni static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev, 741b0f2853bSChristoph Hellwig struct request *req, struct nvme_rw_command *cmd, int entries) 742a7a7cbe3SChaitanya Kulkarni { 743a7a7cbe3SChaitanya Kulkarni struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 744a7a7cbe3SChaitanya Kulkarni struct dma_pool *pool; 745a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *sg_list; 746a7a7cbe3SChaitanya Kulkarni struct scatterlist *sg = iod->sg; 747a7a7cbe3SChaitanya Kulkarni dma_addr_t sgl_dma; 748b0f2853bSChristoph Hellwig int i = 0; 749a7a7cbe3SChaitanya Kulkarni 750a7a7cbe3SChaitanya Kulkarni /* setting the transfer type as SGL */ 751a7a7cbe3SChaitanya Kulkarni cmd->flags = NVME_CMD_SGL_METABUF; 752a7a7cbe3SChaitanya Kulkarni 753b0f2853bSChristoph Hellwig if (entries == 1) { 754a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg); 755a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 756a7a7cbe3SChaitanya Kulkarni } 757a7a7cbe3SChaitanya Kulkarni 758a7a7cbe3SChaitanya Kulkarni if (entries <= (256 / sizeof(struct nvme_sgl_desc))) { 759a7a7cbe3SChaitanya Kulkarni pool = dev->prp_small_pool; 760a7a7cbe3SChaitanya Kulkarni iod->npages = 0; 761a7a7cbe3SChaitanya Kulkarni } else { 762a7a7cbe3SChaitanya Kulkarni pool = dev->prp_page_pool; 763a7a7cbe3SChaitanya Kulkarni iod->npages = 1; 764a7a7cbe3SChaitanya Kulkarni } 765a7a7cbe3SChaitanya Kulkarni 766a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 767a7a7cbe3SChaitanya Kulkarni if (!sg_list) { 768a7a7cbe3SChaitanya Kulkarni iod->npages = -1; 769a7a7cbe3SChaitanya Kulkarni return BLK_STS_RESOURCE; 770a7a7cbe3SChaitanya Kulkarni } 771a7a7cbe3SChaitanya Kulkarni 772a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[0] = sg_list; 773a7a7cbe3SChaitanya Kulkarni iod->first_dma = sgl_dma; 774a7a7cbe3SChaitanya Kulkarni 775a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries); 776a7a7cbe3SChaitanya Kulkarni 777a7a7cbe3SChaitanya Kulkarni do { 778a7a7cbe3SChaitanya Kulkarni if (i == SGES_PER_PAGE) { 779a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *old_sg_desc = sg_list; 780a7a7cbe3SChaitanya Kulkarni struct nvme_sgl_desc *link = &old_sg_desc[i - 1]; 781a7a7cbe3SChaitanya Kulkarni 782a7a7cbe3SChaitanya Kulkarni sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma); 783a7a7cbe3SChaitanya Kulkarni if (!sg_list) 784fa073216SChristoph Hellwig goto free_sgls; 785a7a7cbe3SChaitanya Kulkarni 786a7a7cbe3SChaitanya Kulkarni i = 0; 787a7a7cbe3SChaitanya Kulkarni nvme_pci_iod_list(req)[iod->npages++] = sg_list; 788a7a7cbe3SChaitanya Kulkarni sg_list[i++] = *link; 789a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_seg(link, sgl_dma, entries); 790a7a7cbe3SChaitanya Kulkarni } 791a7a7cbe3SChaitanya Kulkarni 792a7a7cbe3SChaitanya Kulkarni nvme_pci_sgl_set_data(&sg_list[i++], sg); 793a7a7cbe3SChaitanya Kulkarni sg = sg_next(sg); 794b0f2853bSChristoph Hellwig } while (--entries > 0); 795a7a7cbe3SChaitanya Kulkarni 796a7a7cbe3SChaitanya Kulkarni return BLK_STS_OK; 797fa073216SChristoph Hellwig free_sgls: 798fa073216SChristoph Hellwig nvme_free_sgls(dev, req); 799fa073216SChristoph Hellwig return BLK_STS_RESOURCE; 800a7a7cbe3SChaitanya Kulkarni } 801a7a7cbe3SChaitanya Kulkarni 802dff824b2SChristoph Hellwig static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev, 803dff824b2SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 804dff824b2SChristoph Hellwig struct bio_vec *bv) 805dff824b2SChristoph Hellwig { 806dff824b2SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8076c3c05b0SChaitanya Kulkarni unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1); 8086c3c05b0SChaitanya Kulkarni unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset; 809dff824b2SChristoph Hellwig 810dff824b2SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 811dff824b2SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 812dff824b2SChristoph Hellwig return BLK_STS_RESOURCE; 813dff824b2SChristoph Hellwig iod->dma_len = bv->bv_len; 814dff824b2SChristoph Hellwig 815dff824b2SChristoph Hellwig cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma); 816dff824b2SChristoph Hellwig if (bv->bv_len > first_prp_len) 817dff824b2SChristoph Hellwig cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len); 818359c1f88SBaolin Wang return BLK_STS_OK; 819dff824b2SChristoph Hellwig } 820dff824b2SChristoph Hellwig 82129791057SChristoph Hellwig static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev, 82229791057SChristoph Hellwig struct request *req, struct nvme_rw_command *cmnd, 82329791057SChristoph Hellwig struct bio_vec *bv) 82429791057SChristoph Hellwig { 82529791057SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 82629791057SChristoph Hellwig 82729791057SChristoph Hellwig iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0); 82829791057SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->first_dma)) 82929791057SChristoph Hellwig return BLK_STS_RESOURCE; 83029791057SChristoph Hellwig iod->dma_len = bv->bv_len; 83129791057SChristoph Hellwig 832049bf372SKlaus Birkelund Jensen cmnd->flags = NVME_CMD_SGL_METABUF; 83329791057SChristoph Hellwig cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma); 83429791057SChristoph Hellwig cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len); 83529791057SChristoph Hellwig cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4; 836359c1f88SBaolin Wang return BLK_STS_OK; 83729791057SChristoph Hellwig } 83829791057SChristoph Hellwig 839fc17b653SChristoph Hellwig static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req, 840b131c61dSChristoph Hellwig struct nvme_command *cmnd) 84157dacad5SJay Sternberg { 842f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 84370479b71SChristoph Hellwig blk_status_t ret = BLK_STS_RESOURCE; 844b0f2853bSChristoph Hellwig int nr_mapped; 84557dacad5SJay Sternberg 846dff824b2SChristoph Hellwig if (blk_rq_nr_phys_segments(req) == 1) { 847dff824b2SChristoph Hellwig struct bio_vec bv = req_bvec(req); 848dff824b2SChristoph Hellwig 849dff824b2SChristoph Hellwig if (!is_pci_p2pdma_page(bv.bv_page)) { 8506c3c05b0SChaitanya Kulkarni if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2) 851dff824b2SChristoph Hellwig return nvme_setup_prp_simple(dev, req, 852dff824b2SChristoph Hellwig &cmnd->rw, &bv); 85329791057SChristoph Hellwig 854e51183beSNiklas Cassel if (iod->nvmeq->qid && sgl_threshold && 855253a0b76SChaitanya Kulkarni nvme_ctrl_sgl_supported(&dev->ctrl)) 85629791057SChristoph Hellwig return nvme_setup_sgl_simple(dev, req, 85729791057SChristoph Hellwig &cmnd->rw, &bv); 858dff824b2SChristoph Hellwig } 859dff824b2SChristoph Hellwig } 860dff824b2SChristoph Hellwig 861dff824b2SChristoph Hellwig iod->dma_len = 0; 8629b048119SChristoph Hellwig iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC); 8639b048119SChristoph Hellwig if (!iod->sg) 8649b048119SChristoph Hellwig return BLK_STS_RESOURCE; 865f9d03f96SChristoph Hellwig sg_init_table(iod->sg, blk_rq_nr_phys_segments(req)); 86670479b71SChristoph Hellwig iod->nents = blk_rq_map_sg(req->q, req, iod->sg); 867ba1ca37eSChristoph Hellwig if (!iod->nents) 868fa073216SChristoph Hellwig goto out_free_sg; 869ba1ca37eSChristoph Hellwig 870e0596ab2SLogan Gunthorpe if (is_pci_p2pdma_page(sg_page(iod->sg))) 8712b9f4bb2SLogan Gunthorpe nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg, 8722b9f4bb2SLogan Gunthorpe iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN); 873e0596ab2SLogan Gunthorpe else 874e0596ab2SLogan Gunthorpe nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, 87570479b71SChristoph Hellwig rq_dma_dir(req), DMA_ATTR_NO_WARN); 876b0f2853bSChristoph Hellwig if (!nr_mapped) 877fa073216SChristoph Hellwig goto out_free_sg; 878ba1ca37eSChristoph Hellwig 87970479b71SChristoph Hellwig iod->use_sgl = nvme_pci_use_sgls(dev, req); 880955b1b5aSMinwoo Im if (iod->use_sgl) 881b0f2853bSChristoph Hellwig ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped); 882a7a7cbe3SChaitanya Kulkarni else 883a7a7cbe3SChaitanya Kulkarni ret = nvme_pci_setup_prps(dev, req, &cmnd->rw); 8844aedb705SChristoph Hellwig if (ret != BLK_STS_OK) 885fa073216SChristoph Hellwig goto out_unmap_sg; 886fa073216SChristoph Hellwig return BLK_STS_OK; 887fa073216SChristoph Hellwig 888fa073216SChristoph Hellwig out_unmap_sg: 889fa073216SChristoph Hellwig nvme_unmap_sg(dev, req); 890fa073216SChristoph Hellwig out_free_sg: 891fa073216SChristoph Hellwig mempool_free(iod->sg, dev->iod_mempool); 892ba1ca37eSChristoph Hellwig return ret; 89357dacad5SJay Sternberg } 89457dacad5SJay Sternberg 8954aedb705SChristoph Hellwig static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req, 8964aedb705SChristoph Hellwig struct nvme_command *cmnd) 8974aedb705SChristoph Hellwig { 8984aedb705SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 8994aedb705SChristoph Hellwig 9004aedb705SChristoph Hellwig iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req), 9014aedb705SChristoph Hellwig rq_dma_dir(req), 0); 9024aedb705SChristoph Hellwig if (dma_mapping_error(dev->dev, iod->meta_dma)) 9034aedb705SChristoph Hellwig return BLK_STS_IOERR; 9044aedb705SChristoph Hellwig cmnd->rw.metadata = cpu_to_le64(iod->meta_dma); 905359c1f88SBaolin Wang return BLK_STS_OK; 9064aedb705SChristoph Hellwig } 9074aedb705SChristoph Hellwig 90862451a2bSJens Axboe static blk_status_t nvme_prep_rq(struct nvme_dev *dev, struct request *req) 90962451a2bSJens Axboe { 91062451a2bSJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 91162451a2bSJens Axboe blk_status_t ret; 91262451a2bSJens Axboe 91362451a2bSJens Axboe iod->aborted = 0; 91462451a2bSJens Axboe iod->npages = -1; 91562451a2bSJens Axboe iod->nents = 0; 91662451a2bSJens Axboe 91762451a2bSJens Axboe ret = nvme_setup_cmd(req->q->queuedata, req); 91862451a2bSJens Axboe if (ret) 91962451a2bSJens Axboe return ret; 92062451a2bSJens Axboe 92162451a2bSJens Axboe if (blk_rq_nr_phys_segments(req)) { 92262451a2bSJens Axboe ret = nvme_map_data(dev, req, &iod->cmd); 92362451a2bSJens Axboe if (ret) 92462451a2bSJens Axboe goto out_free_cmd; 92562451a2bSJens Axboe } 92662451a2bSJens Axboe 92762451a2bSJens Axboe if (blk_integrity_rq(req)) { 92862451a2bSJens Axboe ret = nvme_map_metadata(dev, req, &iod->cmd); 92962451a2bSJens Axboe if (ret) 93062451a2bSJens Axboe goto out_unmap_data; 93162451a2bSJens Axboe } 93262451a2bSJens Axboe 93362451a2bSJens Axboe blk_mq_start_request(req); 93462451a2bSJens Axboe return BLK_STS_OK; 93562451a2bSJens Axboe out_unmap_data: 93662451a2bSJens Axboe nvme_unmap_data(dev, req); 93762451a2bSJens Axboe out_free_cmd: 93862451a2bSJens Axboe nvme_cleanup_cmd(req); 93962451a2bSJens Axboe return ret; 94062451a2bSJens Axboe } 94162451a2bSJens Axboe 94257dacad5SJay Sternberg /* 94357dacad5SJay Sternberg * NOTE: ns is NULL when called on the admin queue. 94457dacad5SJay Sternberg */ 945fc17b653SChristoph Hellwig static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx, 94657dacad5SJay Sternberg const struct blk_mq_queue_data *bd) 94757dacad5SJay Sternberg { 94857dacad5SJay Sternberg struct nvme_queue *nvmeq = hctx->driver_data; 94957dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 95057dacad5SJay Sternberg struct request *req = bd->rq; 9519b048119SChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 952ebe6d874SChristoph Hellwig blk_status_t ret; 95357dacad5SJay Sternberg 954d1f06f4aSJens Axboe /* 955d1f06f4aSJens Axboe * We should not need to do this, but we're still using this to 956d1f06f4aSJens Axboe * ensure we can drain requests on a dying queue. 957d1f06f4aSJens Axboe */ 9584e224106SChristoph Hellwig if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 959d1f06f4aSJens Axboe return BLK_STS_IOERR; 960d1f06f4aSJens Axboe 96162451a2bSJens Axboe if (unlikely(!nvme_check_ready(&dev->ctrl, req, true))) 962d4060d2bSTao Chiu return nvme_fail_nonready_command(&dev->ctrl, req); 963d4060d2bSTao Chiu 96462451a2bSJens Axboe ret = nvme_prep_rq(dev, req); 96562451a2bSJens Axboe if (unlikely(ret)) 966f4800d6dSChristoph Hellwig return ret; 9673233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 9683233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 9693233b94cSJens Axboe nvme_write_sq_db(nvmeq, bd->last); 9703233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 971fc17b653SChristoph Hellwig return BLK_STS_OK; 97257dacad5SJay Sternberg } 97357dacad5SJay Sternberg 974d62cbcf6SJens Axboe static void nvme_submit_cmds(struct nvme_queue *nvmeq, struct request **rqlist) 975d62cbcf6SJens Axboe { 976d62cbcf6SJens Axboe spin_lock(&nvmeq->sq_lock); 977d62cbcf6SJens Axboe while (!rq_list_empty(*rqlist)) { 978d62cbcf6SJens Axboe struct request *req = rq_list_pop(rqlist); 979d62cbcf6SJens Axboe struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 980d62cbcf6SJens Axboe 981d62cbcf6SJens Axboe nvme_sq_copy_cmd(nvmeq, &iod->cmd); 982d62cbcf6SJens Axboe } 983d62cbcf6SJens Axboe nvme_write_sq_db(nvmeq, true); 984d62cbcf6SJens Axboe spin_unlock(&nvmeq->sq_lock); 985d62cbcf6SJens Axboe } 986d62cbcf6SJens Axboe 987d62cbcf6SJens Axboe static bool nvme_prep_rq_batch(struct nvme_queue *nvmeq, struct request *req) 988d62cbcf6SJens Axboe { 989d62cbcf6SJens Axboe /* 990d62cbcf6SJens Axboe * We should not need to do this, but we're still using this to 991d62cbcf6SJens Axboe * ensure we can drain requests on a dying queue. 992d62cbcf6SJens Axboe */ 993d62cbcf6SJens Axboe if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags))) 994d62cbcf6SJens Axboe return false; 995d62cbcf6SJens Axboe if (unlikely(!nvme_check_ready(&nvmeq->dev->ctrl, req, true))) 996d62cbcf6SJens Axboe return false; 997d62cbcf6SJens Axboe 998d62cbcf6SJens Axboe req->mq_hctx->tags->rqs[req->tag] = req; 999d62cbcf6SJens Axboe return nvme_prep_rq(nvmeq->dev, req) == BLK_STS_OK; 1000d62cbcf6SJens Axboe } 1001d62cbcf6SJens Axboe 1002d62cbcf6SJens Axboe static void nvme_queue_rqs(struct request **rqlist) 1003d62cbcf6SJens Axboe { 10046bfec799SKeith Busch struct request *req, *next, *prev = NULL; 1005d62cbcf6SJens Axboe struct request *requeue_list = NULL; 1006d62cbcf6SJens Axboe 10076bfec799SKeith Busch rq_list_for_each_safe(rqlist, req, next) { 1008d62cbcf6SJens Axboe struct nvme_queue *nvmeq = req->mq_hctx->driver_data; 1009d62cbcf6SJens Axboe 1010d62cbcf6SJens Axboe if (!nvme_prep_rq_batch(nvmeq, req)) { 1011d62cbcf6SJens Axboe /* detach 'req' and add to remainder list */ 10126bfec799SKeith Busch rq_list_move(rqlist, &requeue_list, req, prev); 10136bfec799SKeith Busch 10146bfec799SKeith Busch req = prev; 10156bfec799SKeith Busch if (!req) 10166bfec799SKeith Busch continue; 1017d62cbcf6SJens Axboe } 1018d62cbcf6SJens Axboe 10196bfec799SKeith Busch if (!next || req->mq_hctx != next->mq_hctx) { 1020d62cbcf6SJens Axboe /* detach rest of list, and submit */ 10216bfec799SKeith Busch req->rq_next = NULL; 1022d62cbcf6SJens Axboe nvme_submit_cmds(nvmeq, rqlist); 10236bfec799SKeith Busch *rqlist = next; 10246bfec799SKeith Busch prev = NULL; 10256bfec799SKeith Busch } else 10266bfec799SKeith Busch prev = req; 1027d62cbcf6SJens Axboe } 1028d62cbcf6SJens Axboe 1029d62cbcf6SJens Axboe *rqlist = requeue_list; 1030d62cbcf6SJens Axboe } 1031d62cbcf6SJens Axboe 1032c234a653SJens Axboe static __always_inline void nvme_pci_unmap_rq(struct request *req) 1033eee417b0SChristoph Hellwig { 1034f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 10354aedb705SChristoph Hellwig struct nvme_dev *dev = iod->nvmeq->dev; 1036eee417b0SChristoph Hellwig 10374aedb705SChristoph Hellwig if (blk_integrity_rq(req)) 10384aedb705SChristoph Hellwig dma_unmap_page(dev->dev, iod->meta_dma, 10394aedb705SChristoph Hellwig rq_integrity_vec(req)->bv_len, rq_data_dir(req)); 1040b15c592dSChristoph Hellwig if (blk_rq_nr_phys_segments(req)) 10414aedb705SChristoph Hellwig nvme_unmap_data(dev, req); 1042c234a653SJens Axboe } 1043c234a653SJens Axboe 1044c234a653SJens Axboe static void nvme_pci_complete_rq(struct request *req) 1045c234a653SJens Axboe { 1046c234a653SJens Axboe nvme_pci_unmap_rq(req); 104777f02a7aSChristoph Hellwig nvme_complete_rq(req); 104857dacad5SJay Sternberg } 104957dacad5SJay Sternberg 1050c234a653SJens Axboe static void nvme_pci_complete_batch(struct io_comp_batch *iob) 1051c234a653SJens Axboe { 1052c234a653SJens Axboe nvme_complete_batch(iob, nvme_pci_unmap_rq); 1053c234a653SJens Axboe } 1054c234a653SJens Axboe 1055d783e0bdSMarta Rybczynska /* We read the CQE phase first to check if the rest of the entry is valid */ 1056750dde44SChristoph Hellwig static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq) 1057d783e0bdSMarta Rybczynska { 105874943d45SKeith Busch struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head]; 105974943d45SKeith Busch 106074943d45SKeith Busch return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase; 1061d783e0bdSMarta Rybczynska } 1062d783e0bdSMarta Rybczynska 1063eb281c82SSagi Grimberg static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq) 106457dacad5SJay Sternberg { 1065eb281c82SSagi Grimberg u16 head = nvmeq->cq_head; 106657dacad5SJay Sternberg 1067eb281c82SSagi Grimberg if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db, 1068eb281c82SSagi Grimberg nvmeq->dbbuf_cq_ei)) 1069eb281c82SSagi Grimberg writel(head, nvmeq->q_db + nvmeq->dev->db_stride); 1070eb281c82SSagi Grimberg } 1071adf68f21SChristoph Hellwig 1072cfa27356SChristoph Hellwig static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq) 1073cfa27356SChristoph Hellwig { 1074cfa27356SChristoph Hellwig if (!nvmeq->qid) 1075cfa27356SChristoph Hellwig return nvmeq->dev->admin_tagset.tags[0]; 1076cfa27356SChristoph Hellwig return nvmeq->dev->tagset.tags[nvmeq->qid - 1]; 1077cfa27356SChristoph Hellwig } 1078cfa27356SChristoph Hellwig 1079c234a653SJens Axboe static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, 1080c234a653SJens Axboe struct io_comp_batch *iob, u16 idx) 108157dacad5SJay Sternberg { 108274943d45SKeith Busch struct nvme_completion *cqe = &nvmeq->cqes[idx]; 108362df8016SLalithambika Krishnakumar __u16 command_id = READ_ONCE(cqe->command_id); 108457dacad5SJay Sternberg struct request *req; 1085adf68f21SChristoph Hellwig 1086adf68f21SChristoph Hellwig /* 1087adf68f21SChristoph Hellwig * AEN requests are special as they don't time out and can 1088adf68f21SChristoph Hellwig * survive any kind of queue freeze and often don't respond to 1089adf68f21SChristoph Hellwig * aborts. We don't even bother to allocate a struct request 1090adf68f21SChristoph Hellwig * for them but rather special case them here. 1091adf68f21SChristoph Hellwig */ 109262df8016SLalithambika Krishnakumar if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) { 10937bf58533SChristoph Hellwig nvme_complete_async_event(&nvmeq->dev->ctrl, 109483a12fb7SSagi Grimberg cqe->status, &cqe->result); 1095a0fa9647SJens Axboe return; 109657dacad5SJay Sternberg } 109757dacad5SJay Sternberg 1098e7006de6SSagi Grimberg req = nvme_find_rq(nvme_queue_tagset(nvmeq), command_id); 109950b7c243SXianting Tian if (unlikely(!req)) { 110050b7c243SXianting Tian dev_warn(nvmeq->dev->ctrl.device, 110150b7c243SXianting Tian "invalid id %d completed on queue %d\n", 110262df8016SLalithambika Krishnakumar command_id, le16_to_cpu(cqe->sq_id)); 110350b7c243SXianting Tian return; 110450b7c243SXianting Tian } 110550b7c243SXianting Tian 1106604c01d5Syupeng trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail); 1107c234a653SJens Axboe if (!nvme_try_complete_req(req, cqe->status, cqe->result) && 1108c234a653SJens Axboe !blk_mq_add_to_batch(req, iob, nvme_req(req)->status, 1109c234a653SJens Axboe nvme_pci_complete_batch)) 1110ff029451SChristoph Hellwig nvme_pci_complete_rq(req); 111183a12fb7SSagi Grimberg } 111257dacad5SJay Sternberg 11135cb525c8SJens Axboe static inline void nvme_update_cq_head(struct nvme_queue *nvmeq) 11145cb525c8SJens Axboe { 1115a0aac973SJK Kim u32 tmp = nvmeq->cq_head + 1; 1116a8de6639SAlexey Dobriyan 1117a8de6639SAlexey Dobriyan if (tmp == nvmeq->q_depth) { 1118920d13a8SSagi Grimberg nvmeq->cq_head = 0; 1119e2a366a4SAlexey Dobriyan nvmeq->cq_phase ^= 1; 1120a8de6639SAlexey Dobriyan } else { 1121a8de6639SAlexey Dobriyan nvmeq->cq_head = tmp; 1122920d13a8SSagi Grimberg } 1123a0fa9647SJens Axboe } 1124a0fa9647SJens Axboe 1125c234a653SJens Axboe static inline int nvme_poll_cq(struct nvme_queue *nvmeq, 1126c234a653SJens Axboe struct io_comp_batch *iob) 1127a0fa9647SJens Axboe { 11281052b8acSJens Axboe int found = 0; 112983a12fb7SSagi Grimberg 11301052b8acSJens Axboe while (nvme_cqe_pending(nvmeq)) { 11311052b8acSJens Axboe found++; 1132b69e2ef2SKeith Busch /* 1133b69e2ef2SKeith Busch * load-load control dependency between phase and the rest of 1134b69e2ef2SKeith Busch * the cqe requires a full read memory barrier 1135b69e2ef2SKeith Busch */ 1136b69e2ef2SKeith Busch dma_rmb(); 1137c234a653SJens Axboe nvme_handle_cqe(nvmeq, iob, nvmeq->cq_head); 11385cb525c8SJens Axboe nvme_update_cq_head(nvmeq); 113957dacad5SJay Sternberg } 114057dacad5SJay Sternberg 1141324b494cSKeith Busch if (found) 1142eb281c82SSagi Grimberg nvme_ring_cq_doorbell(nvmeq); 11435cb525c8SJens Axboe return found; 114457dacad5SJay Sternberg } 114557dacad5SJay Sternberg 114657dacad5SJay Sternberg static irqreturn_t nvme_irq(int irq, void *data) 114757dacad5SJay Sternberg { 114857dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11494f502245SJens Axboe DEFINE_IO_COMP_BATCH(iob); 11505cb525c8SJens Axboe 11514f502245SJens Axboe if (nvme_poll_cq(nvmeq, &iob)) { 11524f502245SJens Axboe if (!rq_list_empty(iob.req_list)) 11534f502245SJens Axboe nvme_pci_complete_batch(&iob); 115405fae499SChaitanya Kulkarni return IRQ_HANDLED; 11554f502245SJens Axboe } 115605fae499SChaitanya Kulkarni return IRQ_NONE; 115757dacad5SJay Sternberg } 115857dacad5SJay Sternberg 115957dacad5SJay Sternberg static irqreturn_t nvme_irq_check(int irq, void *data) 116057dacad5SJay Sternberg { 116157dacad5SJay Sternberg struct nvme_queue *nvmeq = data; 11624e523547SBaolin Wang 1163750dde44SChristoph Hellwig if (nvme_cqe_pending(nvmeq)) 116457dacad5SJay Sternberg return IRQ_WAKE_THREAD; 1165d783e0bdSMarta Rybczynska return IRQ_NONE; 116657dacad5SJay Sternberg } 116757dacad5SJay Sternberg 11680b2a8a9fSChristoph Hellwig /* 1169fa059b85SKeith Busch * Poll for completions for any interrupt driven queue 11700b2a8a9fSChristoph Hellwig * Can be called from any context. 11710b2a8a9fSChristoph Hellwig */ 1172fa059b85SKeith Busch static void nvme_poll_irqdisable(struct nvme_queue *nvmeq) 1173a0fa9647SJens Axboe { 11743a7afd8eSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 1175a0fa9647SJens Axboe 1176fa059b85SKeith Busch WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags)); 1177fa059b85SKeith Busch 11783a7afd8eSChristoph Hellwig disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 1179c234a653SJens Axboe nvme_poll_cq(nvmeq, NULL); 11803a7afd8eSChristoph Hellwig enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector)); 118191a509f8SChristoph Hellwig } 1182442e19b7SSagi Grimberg 11835a72e899SJens Axboe static int nvme_poll(struct blk_mq_hw_ctx *hctx, struct io_comp_batch *iob) 11847776db1cSKeith Busch { 11857776db1cSKeith Busch struct nvme_queue *nvmeq = hctx->driver_data; 1186dabcefabSJens Axboe bool found; 1187dabcefabSJens Axboe 1188dabcefabSJens Axboe if (!nvme_cqe_pending(nvmeq)) 1189dabcefabSJens Axboe return 0; 1190dabcefabSJens Axboe 11913a7afd8eSChristoph Hellwig spin_lock(&nvmeq->cq_poll_lock); 1192c234a653SJens Axboe found = nvme_poll_cq(nvmeq, iob); 11933a7afd8eSChristoph Hellwig spin_unlock(&nvmeq->cq_poll_lock); 1194dabcefabSJens Axboe 1195dabcefabSJens Axboe return found; 1196dabcefabSJens Axboe } 1197dabcefabSJens Axboe 1198ad22c355SKeith Busch static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl) 119957dacad5SJay Sternberg { 1200f866fc42SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 1201147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 1202f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 120357dacad5SJay Sternberg 120457dacad5SJay Sternberg c.common.opcode = nvme_admin_async_event; 1205ad22c355SKeith Busch c.common.command_id = NVME_AQ_BLK_MQ_DEPTH; 12063233b94cSJens Axboe 12073233b94cSJens Axboe spin_lock(&nvmeq->sq_lock); 12083233b94cSJens Axboe nvme_sq_copy_cmd(nvmeq, &c); 12093233b94cSJens Axboe nvme_write_sq_db(nvmeq, true); 12103233b94cSJens Axboe spin_unlock(&nvmeq->sq_lock); 121157dacad5SJay Sternberg } 121257dacad5SJay Sternberg 121357dacad5SJay Sternberg static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id) 121457dacad5SJay Sternberg { 1215f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 121657dacad5SJay Sternberg 121757dacad5SJay Sternberg c.delete_queue.opcode = opcode; 121857dacad5SJay Sternberg c.delete_queue.qid = cpu_to_le16(id); 121957dacad5SJay Sternberg 12201c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 122157dacad5SJay Sternberg } 122257dacad5SJay Sternberg 122357dacad5SJay Sternberg static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid, 1224a8e3e0bbSJianchao Wang struct nvme_queue *nvmeq, s16 vector) 122557dacad5SJay Sternberg { 1226f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 12274b04cc6aSJens Axboe int flags = NVME_QUEUE_PHYS_CONTIG; 12284b04cc6aSJens Axboe 12297c349ddeSKeith Busch if (!test_bit(NVMEQ_POLLED, &nvmeq->flags)) 12304b04cc6aSJens Axboe flags |= NVME_CQ_IRQ_ENABLED; 123157dacad5SJay Sternberg 123257dacad5SJay Sternberg /* 123316772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 123457dacad5SJay Sternberg * is attached to the request. 123557dacad5SJay Sternberg */ 123657dacad5SJay Sternberg c.create_cq.opcode = nvme_admin_create_cq; 123757dacad5SJay Sternberg c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr); 123857dacad5SJay Sternberg c.create_cq.cqid = cpu_to_le16(qid); 123957dacad5SJay Sternberg c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 124057dacad5SJay Sternberg c.create_cq.cq_flags = cpu_to_le16(flags); 1241a8e3e0bbSJianchao Wang c.create_cq.irq_vector = cpu_to_le16(vector); 124257dacad5SJay Sternberg 12431c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 124457dacad5SJay Sternberg } 124557dacad5SJay Sternberg 124657dacad5SJay Sternberg static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid, 124757dacad5SJay Sternberg struct nvme_queue *nvmeq) 124857dacad5SJay Sternberg { 12499abd68efSJens Axboe struct nvme_ctrl *ctrl = &dev->ctrl; 1250f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 125181c1cd98SKeith Busch int flags = NVME_QUEUE_PHYS_CONTIG; 125257dacad5SJay Sternberg 125357dacad5SJay Sternberg /* 12549abd68efSJens Axboe * Some drives have a bug that auto-enables WRRU if MEDIUM isn't 12559abd68efSJens Axboe * set. Since URGENT priority is zeroes, it makes all queues 12569abd68efSJens Axboe * URGENT. 12579abd68efSJens Axboe */ 12589abd68efSJens Axboe if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ) 12599abd68efSJens Axboe flags |= NVME_SQ_PRIO_MEDIUM; 12609abd68efSJens Axboe 12619abd68efSJens Axboe /* 126216772ae6SMinwoo Im * Note: we (ab)use the fact that the prp fields survive if no data 126357dacad5SJay Sternberg * is attached to the request. 126457dacad5SJay Sternberg */ 126557dacad5SJay Sternberg c.create_sq.opcode = nvme_admin_create_sq; 126657dacad5SJay Sternberg c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr); 126757dacad5SJay Sternberg c.create_sq.sqid = cpu_to_le16(qid); 126857dacad5SJay Sternberg c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1); 126957dacad5SJay Sternberg c.create_sq.sq_flags = cpu_to_le16(flags); 127057dacad5SJay Sternberg c.create_sq.cqid = cpu_to_le16(qid); 127157dacad5SJay Sternberg 12721c63dc66SChristoph Hellwig return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 127357dacad5SJay Sternberg } 127457dacad5SJay Sternberg 127557dacad5SJay Sternberg static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid) 127657dacad5SJay Sternberg { 127757dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid); 127857dacad5SJay Sternberg } 127957dacad5SJay Sternberg 128057dacad5SJay Sternberg static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid) 128157dacad5SJay Sternberg { 128257dacad5SJay Sternberg return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid); 128357dacad5SJay Sternberg } 128457dacad5SJay Sternberg 12852a842acaSChristoph Hellwig static void abort_endio(struct request *req, blk_status_t error) 128657dacad5SJay Sternberg { 1287f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1288f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 128957dacad5SJay Sternberg 129027fa9bc5SChristoph Hellwig dev_warn(nvmeq->dev->ctrl.device, 129127fa9bc5SChristoph Hellwig "Abort status: 0x%x", nvme_req(req)->status); 1292e7a2a87dSChristoph Hellwig atomic_inc(&nvmeq->dev->ctrl.abort_limit); 1293e7a2a87dSChristoph Hellwig blk_mq_free_request(req); 129457dacad5SJay Sternberg } 129557dacad5SJay Sternberg 1296b2a0eb1aSKeith Busch static bool nvme_should_reset(struct nvme_dev *dev, u32 csts) 1297b2a0eb1aSKeith Busch { 1298b2a0eb1aSKeith Busch /* If true, indicates loss of adapter communication, possibly by a 1299b2a0eb1aSKeith Busch * NVMe Subsystem reset. 1300b2a0eb1aSKeith Busch */ 1301b2a0eb1aSKeith Busch bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO); 1302b2a0eb1aSKeith Busch 1303ad70062cSJianchao Wang /* If there is a reset/reinit ongoing, we shouldn't reset again. */ 1304ad70062cSJianchao Wang switch (dev->ctrl.state) { 1305ad70062cSJianchao Wang case NVME_CTRL_RESETTING: 1306ad6a0a52SMax Gurtovoy case NVME_CTRL_CONNECTING: 1307b2a0eb1aSKeith Busch return false; 1308ad70062cSJianchao Wang default: 1309ad70062cSJianchao Wang break; 1310ad70062cSJianchao Wang } 1311b2a0eb1aSKeith Busch 1312b2a0eb1aSKeith Busch /* We shouldn't reset unless the controller is on fatal error state 1313b2a0eb1aSKeith Busch * _or_ if we lost the communication with it. 1314b2a0eb1aSKeith Busch */ 1315b2a0eb1aSKeith Busch if (!(csts & NVME_CSTS_CFS) && !nssro) 1316b2a0eb1aSKeith Busch return false; 1317b2a0eb1aSKeith Busch 1318b2a0eb1aSKeith Busch return true; 1319b2a0eb1aSKeith Busch } 1320b2a0eb1aSKeith Busch 1321b2a0eb1aSKeith Busch static void nvme_warn_reset(struct nvme_dev *dev, u32 csts) 1322b2a0eb1aSKeith Busch { 1323b2a0eb1aSKeith Busch /* Read a config register to help see what died. */ 1324b2a0eb1aSKeith Busch u16 pci_status; 1325b2a0eb1aSKeith Busch int result; 1326b2a0eb1aSKeith Busch 1327b2a0eb1aSKeith Busch result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS, 1328b2a0eb1aSKeith Busch &pci_status); 1329b2a0eb1aSKeith Busch if (result == PCIBIOS_SUCCESSFUL) 1330b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1331b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n", 1332b2a0eb1aSKeith Busch csts, pci_status); 1333b2a0eb1aSKeith Busch else 1334b2a0eb1aSKeith Busch dev_warn(dev->ctrl.device, 1335b2a0eb1aSKeith Busch "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n", 1336b2a0eb1aSKeith Busch csts, result); 1337b2a0eb1aSKeith Busch } 1338b2a0eb1aSKeith Busch 133931c7c7d2SChristoph Hellwig static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved) 134057dacad5SJay Sternberg { 1341f4800d6dSChristoph Hellwig struct nvme_iod *iod = blk_mq_rq_to_pdu(req); 1342f4800d6dSChristoph Hellwig struct nvme_queue *nvmeq = iod->nvmeq; 134357dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 134457dacad5SJay Sternberg struct request *abort_req; 1345f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 1346b2a0eb1aSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 1347b2a0eb1aSKeith Busch 1348651438bbSWen Xiong /* If PCI error recovery process is happening, we cannot reset or 1349651438bbSWen Xiong * the recovery mechanism will surely fail. 1350651438bbSWen Xiong */ 1351651438bbSWen Xiong mb(); 1352651438bbSWen Xiong if (pci_channel_offline(to_pci_dev(dev->dev))) 1353651438bbSWen Xiong return BLK_EH_RESET_TIMER; 1354651438bbSWen Xiong 1355b2a0eb1aSKeith Busch /* 1356b2a0eb1aSKeith Busch * Reset immediately if the controller is failed 1357b2a0eb1aSKeith Busch */ 1358b2a0eb1aSKeith Busch if (nvme_should_reset(dev, csts)) { 1359b2a0eb1aSKeith Busch nvme_warn_reset(dev, csts); 1360b2a0eb1aSKeith Busch nvme_dev_disable(dev, false); 1361d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1362db8c48e4SChristoph Hellwig return BLK_EH_DONE; 1363b2a0eb1aSKeith Busch } 136457dacad5SJay Sternberg 136531c7c7d2SChristoph Hellwig /* 13667776db1cSKeith Busch * Did we miss an interrupt? 13677776db1cSKeith Busch */ 1368fa059b85SKeith Busch if (test_bit(NVMEQ_POLLED, &nvmeq->flags)) 13695a72e899SJens Axboe nvme_poll(req->mq_hctx, NULL); 1370fa059b85SKeith Busch else 1371bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 1372fa059b85SKeith Busch 1373bf392a5dSKeith Busch if (blk_mq_request_completed(req)) { 13747776db1cSKeith Busch dev_warn(dev->ctrl.device, 13757776db1cSKeith Busch "I/O %d QID %d timeout, completion polled\n", 13767776db1cSKeith Busch req->tag, nvmeq->qid); 1377db8c48e4SChristoph Hellwig return BLK_EH_DONE; 13787776db1cSKeith Busch } 13797776db1cSKeith Busch 13807776db1cSKeith Busch /* 1381fd634f41SChristoph Hellwig * Shutdown immediately if controller times out while starting. The 1382fd634f41SChristoph Hellwig * reset work will see the pci device disabled when it gets the forced 1383fd634f41SChristoph Hellwig * cancellation error. All outstanding requests are completed on 1384db8c48e4SChristoph Hellwig * shutdown, so we return BLK_EH_DONE. 1385fd634f41SChristoph Hellwig */ 13864244140dSKeith Busch switch (dev->ctrl.state) { 13874244140dSKeith Busch case NVME_CTRL_CONNECTING: 13882036f726SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 1389df561f66SGustavo A. R. Silva fallthrough; 13902036f726SKeith Busch case NVME_CTRL_DELETING: 1391b9cac43cSKeith Busch dev_warn_ratelimited(dev->ctrl.device, 1392fd634f41SChristoph Hellwig "I/O %d QID %d timeout, disable controller\n", 1393fd634f41SChristoph Hellwig req->tag, nvmeq->qid); 139427fa9bc5SChristoph Hellwig nvme_req(req)->flags |= NVME_REQ_CANCELLED; 13957ad92f65STong Zhang nvme_dev_disable(dev, true); 1396db8c48e4SChristoph Hellwig return BLK_EH_DONE; 139739a9dd81SKeith Busch case NVME_CTRL_RESETTING: 139839a9dd81SKeith Busch return BLK_EH_RESET_TIMER; 13994244140dSKeith Busch default: 14004244140dSKeith Busch break; 1401fd634f41SChristoph Hellwig } 1402fd634f41SChristoph Hellwig 1403fd634f41SChristoph Hellwig /* 1404e1569a16SKeith Busch * Shutdown the controller immediately and schedule a reset if the 1405e1569a16SKeith Busch * command was already aborted once before and still hasn't been 1406e1569a16SKeith Busch * returned to the driver, or if this is the admin queue. 140731c7c7d2SChristoph Hellwig */ 1408f4800d6dSChristoph Hellwig if (!nvmeq->qid || iod->aborted) { 14091b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, 141057dacad5SJay Sternberg "I/O %d QID %d timeout, reset controller\n", 141157dacad5SJay Sternberg req->tag, nvmeq->qid); 14127ad92f65STong Zhang nvme_req(req)->flags |= NVME_REQ_CANCELLED; 1413a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 1414d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 1415e1569a16SKeith Busch 1416db8c48e4SChristoph Hellwig return BLK_EH_DONE; 141757dacad5SJay Sternberg } 141857dacad5SJay Sternberg 1419e7a2a87dSChristoph Hellwig if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) { 1420e7a2a87dSChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 1421e7a2a87dSChristoph Hellwig return BLK_EH_RESET_TIMER; 1422e7a2a87dSChristoph Hellwig } 14237bf7d778SKeith Busch iod->aborted = 1; 142457dacad5SJay Sternberg 142557dacad5SJay Sternberg cmd.abort.opcode = nvme_admin_abort_cmd; 142685f74acfSKeith Busch cmd.abort.cid = nvme_cid(req); 142757dacad5SJay Sternberg cmd.abort.sqid = cpu_to_le16(nvmeq->qid); 142857dacad5SJay Sternberg 14291b3c47c1SSagi Grimberg dev_warn(nvmeq->dev->ctrl.device, 14301b3c47c1SSagi Grimberg "I/O %d QID %d timeout, aborting\n", 143157dacad5SJay Sternberg req->tag, nvmeq->qid); 1432e7a2a87dSChristoph Hellwig 1433e559398fSChristoph Hellwig abort_req = blk_mq_alloc_request(dev->ctrl.admin_q, nvme_req_op(&cmd), 143439dfe844SChaitanya Kulkarni BLK_MQ_REQ_NOWAIT); 14356bf25d16SChristoph Hellwig if (IS_ERR(abort_req)) { 14366bf25d16SChristoph Hellwig atomic_inc(&dev->ctrl.abort_limit); 143731c7c7d2SChristoph Hellwig return BLK_EH_RESET_TIMER; 143857dacad5SJay Sternberg } 1439e559398fSChristoph Hellwig nvme_init_request(abort_req, &cmd); 144057dacad5SJay Sternberg 1441e7a2a87dSChristoph Hellwig abort_req->end_io_data = NULL; 1442128126a7SChaitanya Kulkarni abort_req->rq_flags |= RQF_QUIET; 1443b84ba30bSChristoph Hellwig blk_execute_rq_nowait(abort_req, false, abort_endio); 144457dacad5SJay Sternberg 144557dacad5SJay Sternberg /* 144657dacad5SJay Sternberg * The aborted req will be completed on receiving the abort req. 144757dacad5SJay Sternberg * We enable the timer again. If hit twice, it'll cause a device reset, 144857dacad5SJay Sternberg * as the device then is in a faulty state. 144957dacad5SJay Sternberg */ 145057dacad5SJay Sternberg return BLK_EH_RESET_TIMER; 145157dacad5SJay Sternberg } 145257dacad5SJay Sternberg 145357dacad5SJay Sternberg static void nvme_free_queue(struct nvme_queue *nvmeq) 145457dacad5SJay Sternberg { 14558a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq), 145657dacad5SJay Sternberg (void *)nvmeq->cqes, nvmeq->cq_dma_addr); 145763223078SChristoph Hellwig if (!nvmeq->sq_cmds) 145863223078SChristoph Hellwig return; 14590f238ff5SLogan Gunthorpe 146063223078SChristoph Hellwig if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) { 146188a041f4SKeith Busch pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev), 14628a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 146363223078SChristoph Hellwig } else { 14648a1d09a6SBenjamin Herrenschmidt dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq), 146563223078SChristoph Hellwig nvmeq->sq_cmds, nvmeq->sq_dma_addr); 14660f238ff5SLogan Gunthorpe } 146757dacad5SJay Sternberg } 146857dacad5SJay Sternberg 146957dacad5SJay Sternberg static void nvme_free_queues(struct nvme_dev *dev, int lowest) 147057dacad5SJay Sternberg { 147157dacad5SJay Sternberg int i; 147257dacad5SJay Sternberg 1473d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) { 1474d858e5f0SSagi Grimberg dev->ctrl.queue_count--; 1475147b27e4SSagi Grimberg nvme_free_queue(&dev->queues[i]); 147657dacad5SJay Sternberg } 147757dacad5SJay Sternberg } 147857dacad5SJay Sternberg 147957dacad5SJay Sternberg /** 148057dacad5SJay Sternberg * nvme_suspend_queue - put queue into suspended state 148140581d1aSBart Van Assche * @nvmeq: queue to suspend 148257dacad5SJay Sternberg */ 148357dacad5SJay Sternberg static int nvme_suspend_queue(struct nvme_queue *nvmeq) 148457dacad5SJay Sternberg { 14854e224106SChristoph Hellwig if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags)) 148657dacad5SJay Sternberg return 1; 148757dacad5SJay Sternberg 14884e224106SChristoph Hellwig /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */ 1489d1f06f4aSJens Axboe mb(); 149057dacad5SJay Sternberg 14914e224106SChristoph Hellwig nvmeq->dev->online_queues--; 14921c63dc66SChristoph Hellwig if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q) 14936ca1d902SMing Lei nvme_stop_admin_queue(&nvmeq->dev->ctrl); 14947c349ddeSKeith Busch if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags)) 14954e224106SChristoph Hellwig pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq); 149657dacad5SJay Sternberg return 0; 149757dacad5SJay Sternberg } 149857dacad5SJay Sternberg 14998fae268bSKeith Busch static void nvme_suspend_io_queues(struct nvme_dev *dev) 15008fae268bSKeith Busch { 15018fae268bSKeith Busch int i; 15028fae268bSKeith Busch 15038fae268bSKeith Busch for (i = dev->ctrl.queue_count - 1; i > 0; i--) 15048fae268bSKeith Busch nvme_suspend_queue(&dev->queues[i]); 15058fae268bSKeith Busch } 15068fae268bSKeith Busch 1507a5cdb68cSKeith Busch static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown) 150857dacad5SJay Sternberg { 1509147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[0]; 151057dacad5SJay Sternberg 1511a5cdb68cSKeith Busch if (shutdown) 1512a5cdb68cSKeith Busch nvme_shutdown_ctrl(&dev->ctrl); 1513a5cdb68cSKeith Busch else 1514b5b05048SSagi Grimberg nvme_disable_ctrl(&dev->ctrl); 151557dacad5SJay Sternberg 1516bf392a5dSKeith Busch nvme_poll_irqdisable(nvmeq); 151757dacad5SJay Sternberg } 151857dacad5SJay Sternberg 1519fa46c6fbSKeith Busch /* 1520fa46c6fbSKeith Busch * Called only on a device that has been disabled and after all other threads 15219210c075SDongli Zhang * that can check this device's completion queues have synced, except 15229210c075SDongli Zhang * nvme_poll(). This is the last chance for the driver to see a natural 15239210c075SDongli Zhang * completion before nvme_cancel_request() terminates all incomplete requests. 1524fa46c6fbSKeith Busch */ 1525fa46c6fbSKeith Busch static void nvme_reap_pending_cqes(struct nvme_dev *dev) 1526fa46c6fbSKeith Busch { 1527fa46c6fbSKeith Busch int i; 1528fa46c6fbSKeith Busch 15299210c075SDongli Zhang for (i = dev->ctrl.queue_count - 1; i > 0; i--) { 15309210c075SDongli Zhang spin_lock(&dev->queues[i].cq_poll_lock); 1531c234a653SJens Axboe nvme_poll_cq(&dev->queues[i], NULL); 15329210c075SDongli Zhang spin_unlock(&dev->queues[i].cq_poll_lock); 15339210c075SDongli Zhang } 1534fa46c6fbSKeith Busch } 1535fa46c6fbSKeith Busch 153657dacad5SJay Sternberg static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues, 153757dacad5SJay Sternberg int entry_size) 153857dacad5SJay Sternberg { 153957dacad5SJay Sternberg int q_depth = dev->q_depth; 15405fd4ce1bSChristoph Hellwig unsigned q_size_aligned = roundup(q_depth * entry_size, 15416c3c05b0SChaitanya Kulkarni NVME_CTRL_PAGE_SIZE); 154257dacad5SJay Sternberg 154357dacad5SJay Sternberg if (q_size_aligned * nr_io_queues > dev->cmb_size) { 154457dacad5SJay Sternberg u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues); 15454e523547SBaolin Wang 15466c3c05b0SChaitanya Kulkarni mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE); 154757dacad5SJay Sternberg q_depth = div_u64(mem_per_q, entry_size); 154857dacad5SJay Sternberg 154957dacad5SJay Sternberg /* 155057dacad5SJay Sternberg * Ensure the reduced q_depth is above some threshold where it 155157dacad5SJay Sternberg * would be better to map queues in system memory with the 155257dacad5SJay Sternberg * original depth 155357dacad5SJay Sternberg */ 155457dacad5SJay Sternberg if (q_depth < 64) 155557dacad5SJay Sternberg return -ENOMEM; 155657dacad5SJay Sternberg } 155757dacad5SJay Sternberg 155857dacad5SJay Sternberg return q_depth; 155957dacad5SJay Sternberg } 156057dacad5SJay Sternberg 156157dacad5SJay Sternberg static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq, 15628a1d09a6SBenjamin Herrenschmidt int qid) 156357dacad5SJay Sternberg { 15640f238ff5SLogan Gunthorpe struct pci_dev *pdev = to_pci_dev(dev->dev); 1565815c6704SKeith Busch 15660f238ff5SLogan Gunthorpe if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) { 15678a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq)); 1568bfac8e9fSAlan Mikhak if (nvmeq->sq_cmds) { 15690f238ff5SLogan Gunthorpe nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev, 15700f238ff5SLogan Gunthorpe nvmeq->sq_cmds); 157163223078SChristoph Hellwig if (nvmeq->sq_dma_addr) { 157263223078SChristoph Hellwig set_bit(NVMEQ_SQ_CMB, &nvmeq->flags); 157363223078SChristoph Hellwig return 0; 157463223078SChristoph Hellwig } 1575bfac8e9fSAlan Mikhak 15768a1d09a6SBenjamin Herrenschmidt pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq)); 1577bfac8e9fSAlan Mikhak } 15780f238ff5SLogan Gunthorpe } 15790f238ff5SLogan Gunthorpe 15808a1d09a6SBenjamin Herrenschmidt nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq), 158157dacad5SJay Sternberg &nvmeq->sq_dma_addr, GFP_KERNEL); 158257dacad5SJay Sternberg if (!nvmeq->sq_cmds) 158357dacad5SJay Sternberg return -ENOMEM; 158457dacad5SJay Sternberg return 0; 158557dacad5SJay Sternberg } 158657dacad5SJay Sternberg 1587a6ff7262SKeith Busch static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth) 158857dacad5SJay Sternberg { 1589147b27e4SSagi Grimberg struct nvme_queue *nvmeq = &dev->queues[qid]; 159057dacad5SJay Sternberg 159162314e40SKeith Busch if (dev->ctrl.queue_count > qid) 159262314e40SKeith Busch return 0; 159357dacad5SJay Sternberg 1594c1e0cc7eSBenjamin Herrenschmidt nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES; 15958a1d09a6SBenjamin Herrenschmidt nvmeq->q_depth = depth; 15968a1d09a6SBenjamin Herrenschmidt nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq), 159757dacad5SJay Sternberg &nvmeq->cq_dma_addr, GFP_KERNEL); 159857dacad5SJay Sternberg if (!nvmeq->cqes) 159957dacad5SJay Sternberg goto free_nvmeq; 160057dacad5SJay Sternberg 16018a1d09a6SBenjamin Herrenschmidt if (nvme_alloc_sq_cmds(dev, nvmeq, qid)) 160257dacad5SJay Sternberg goto free_cqdma; 160357dacad5SJay Sternberg 160457dacad5SJay Sternberg nvmeq->dev = dev; 16051ab0cd69SJens Axboe spin_lock_init(&nvmeq->sq_lock); 16063a7afd8eSChristoph Hellwig spin_lock_init(&nvmeq->cq_poll_lock); 160757dacad5SJay Sternberg nvmeq->cq_head = 0; 160857dacad5SJay Sternberg nvmeq->cq_phase = 1; 160957dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 161057dacad5SJay Sternberg nvmeq->qid = qid; 1611d858e5f0SSagi Grimberg dev->ctrl.queue_count++; 161257dacad5SJay Sternberg 1613147b27e4SSagi Grimberg return 0; 161457dacad5SJay Sternberg 161557dacad5SJay Sternberg free_cqdma: 16168a1d09a6SBenjamin Herrenschmidt dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes, 161757dacad5SJay Sternberg nvmeq->cq_dma_addr); 161857dacad5SJay Sternberg free_nvmeq: 1619147b27e4SSagi Grimberg return -ENOMEM; 162057dacad5SJay Sternberg } 162157dacad5SJay Sternberg 1622dca51e78SChristoph Hellwig static int queue_request_irq(struct nvme_queue *nvmeq) 162357dacad5SJay Sternberg { 16240ff199cbSChristoph Hellwig struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev); 16250ff199cbSChristoph Hellwig int nr = nvmeq->dev->ctrl.instance; 16260ff199cbSChristoph Hellwig 16270ff199cbSChristoph Hellwig if (use_threaded_interrupts) { 16280ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check, 16290ff199cbSChristoph Hellwig nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16300ff199cbSChristoph Hellwig } else { 16310ff199cbSChristoph Hellwig return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq, 16320ff199cbSChristoph Hellwig NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid); 16330ff199cbSChristoph Hellwig } 163457dacad5SJay Sternberg } 163557dacad5SJay Sternberg 163657dacad5SJay Sternberg static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid) 163757dacad5SJay Sternberg { 163857dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 163957dacad5SJay Sternberg 164057dacad5SJay Sternberg nvmeq->sq_tail = 0; 164138210800SKeith Busch nvmeq->last_sq_tail = 0; 164257dacad5SJay Sternberg nvmeq->cq_head = 0; 164357dacad5SJay Sternberg nvmeq->cq_phase = 1; 164457dacad5SJay Sternberg nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride]; 16458a1d09a6SBenjamin Herrenschmidt memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq)); 1646f9f38e33SHelen Koike nvme_dbbuf_init(dev, nvmeq, qid); 164757dacad5SJay Sternberg dev->online_queues++; 16483a7afd8eSChristoph Hellwig wmb(); /* ensure the first interrupt sees the initialization */ 164957dacad5SJay Sternberg } 165057dacad5SJay Sternberg 1651e4b9852aSCasey Chen /* 1652e4b9852aSCasey Chen * Try getting shutdown_lock while setting up IO queues. 1653e4b9852aSCasey Chen */ 1654e4b9852aSCasey Chen static int nvme_setup_io_queues_trylock(struct nvme_dev *dev) 1655e4b9852aSCasey Chen { 1656e4b9852aSCasey Chen /* 1657e4b9852aSCasey Chen * Give up if the lock is being held by nvme_dev_disable. 1658e4b9852aSCasey Chen */ 1659e4b9852aSCasey Chen if (!mutex_trylock(&dev->shutdown_lock)) 1660e4b9852aSCasey Chen return -ENODEV; 1661e4b9852aSCasey Chen 1662e4b9852aSCasey Chen /* 1663e4b9852aSCasey Chen * Controller is in wrong state, fail early. 1664e4b9852aSCasey Chen */ 1665e4b9852aSCasey Chen if (dev->ctrl.state != NVME_CTRL_CONNECTING) { 1666e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 1667e4b9852aSCasey Chen return -ENODEV; 1668e4b9852aSCasey Chen } 1669e4b9852aSCasey Chen 1670e4b9852aSCasey Chen return 0; 1671e4b9852aSCasey Chen } 1672e4b9852aSCasey Chen 16734b04cc6aSJens Axboe static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled) 167457dacad5SJay Sternberg { 167557dacad5SJay Sternberg struct nvme_dev *dev = nvmeq->dev; 167657dacad5SJay Sternberg int result; 16777c349ddeSKeith Busch u16 vector = 0; 167857dacad5SJay Sternberg 1679d1ed6aa1SChristoph Hellwig clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 1680d1ed6aa1SChristoph Hellwig 168122b55601SKeith Busch /* 168222b55601SKeith Busch * A queue's vector matches the queue identifier unless the controller 168322b55601SKeith Busch * has only one vector available. 168422b55601SKeith Busch */ 16854b04cc6aSJens Axboe if (!polled) 1686a8e3e0bbSJianchao Wang vector = dev->num_vecs == 1 ? 0 : qid; 16874b04cc6aSJens Axboe else 16887c349ddeSKeith Busch set_bit(NVMEQ_POLLED, &nvmeq->flags); 16894b04cc6aSJens Axboe 1690a8e3e0bbSJianchao Wang result = adapter_alloc_cq(dev, qid, nvmeq, vector); 1691ded45505SKeith Busch if (result) 1692ded45505SKeith Busch return result; 169357dacad5SJay Sternberg 169457dacad5SJay Sternberg result = adapter_alloc_sq(dev, qid, nvmeq); 169557dacad5SJay Sternberg if (result < 0) 1696ded45505SKeith Busch return result; 1697c80b36cdSEdmund Nadolski if (result) 169857dacad5SJay Sternberg goto release_cq; 169957dacad5SJay Sternberg 1700a8e3e0bbSJianchao Wang nvmeq->cq_vector = vector; 17014b04cc6aSJens Axboe 1702e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 1703e4b9852aSCasey Chen if (result) 1704e4b9852aSCasey Chen return result; 1705e4b9852aSCasey Chen nvme_init_queue(nvmeq, qid); 17067c349ddeSKeith Busch if (!polled) { 1707dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 170857dacad5SJay Sternberg if (result < 0) 170957dacad5SJay Sternberg goto release_sq; 17104b04cc6aSJens Axboe } 171157dacad5SJay Sternberg 17124e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 1713e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171457dacad5SJay Sternberg return result; 171557dacad5SJay Sternberg 171657dacad5SJay Sternberg release_sq: 1717f25a2dfcSJianchao Wang dev->online_queues--; 1718e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 171957dacad5SJay Sternberg adapter_delete_sq(dev, qid); 172057dacad5SJay Sternberg release_cq: 172157dacad5SJay Sternberg adapter_delete_cq(dev, qid); 172257dacad5SJay Sternberg return result; 172357dacad5SJay Sternberg } 172457dacad5SJay Sternberg 1725f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_admin_ops = { 172657dacad5SJay Sternberg .queue_rq = nvme_queue_rq, 172777f02a7aSChristoph Hellwig .complete = nvme_pci_complete_rq, 172857dacad5SJay Sternberg .init_hctx = nvme_admin_init_hctx, 1729e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 173057dacad5SJay Sternberg .timeout = nvme_timeout, 173157dacad5SJay Sternberg }; 173257dacad5SJay Sternberg 1733f363b089SEric Biggers static const struct blk_mq_ops nvme_mq_ops = { 1734376f7ef8SChristoph Hellwig .queue_rq = nvme_queue_rq, 1735d62cbcf6SJens Axboe .queue_rqs = nvme_queue_rqs, 1736376f7ef8SChristoph Hellwig .complete = nvme_pci_complete_rq, 1737376f7ef8SChristoph Hellwig .commit_rqs = nvme_commit_rqs, 1738376f7ef8SChristoph Hellwig .init_hctx = nvme_init_hctx, 1739e559398fSChristoph Hellwig .init_request = nvme_pci_init_request, 1740376f7ef8SChristoph Hellwig .map_queues = nvme_pci_map_queues, 1741376f7ef8SChristoph Hellwig .timeout = nvme_timeout, 1742c6d962aeSChristoph Hellwig .poll = nvme_poll, 1743dabcefabSJens Axboe }; 1744dabcefabSJens Axboe 174557dacad5SJay Sternberg static void nvme_dev_remove_admin(struct nvme_dev *dev) 174657dacad5SJay Sternberg { 17471c63dc66SChristoph Hellwig if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) { 174869d9a99cSKeith Busch /* 174969d9a99cSKeith Busch * If the controller was reset during removal, it's possible 175069d9a99cSKeith Busch * user requests may be waiting on a stopped queue. Start the 175169d9a99cSKeith Busch * queue to flush these to completion. 175269d9a99cSKeith Busch */ 17536ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 17541c63dc66SChristoph Hellwig blk_cleanup_queue(dev->ctrl.admin_q); 175557dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 175657dacad5SJay Sternberg } 175757dacad5SJay Sternberg } 175857dacad5SJay Sternberg 175957dacad5SJay Sternberg static int nvme_alloc_admin_tags(struct nvme_dev *dev) 176057dacad5SJay Sternberg { 17611c63dc66SChristoph Hellwig if (!dev->ctrl.admin_q) { 176257dacad5SJay Sternberg dev->admin_tagset.ops = &nvme_mq_admin_ops; 176357dacad5SJay Sternberg dev->admin_tagset.nr_hw_queues = 1; 1764e3e9d50cSKeith Busch 176538dabe21SKeith Busch dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH; 1766dc96f938SChaitanya Kulkarni dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT; 1767d4ec47f1SMax Gurtovoy dev->admin_tagset.numa_node = dev->ctrl.numa_node; 1768d43f1ccfSChristoph Hellwig dev->admin_tagset.cmd_size = sizeof(struct nvme_iod); 1769d3484991SJens Axboe dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED; 177057dacad5SJay Sternberg dev->admin_tagset.driver_data = dev; 177157dacad5SJay Sternberg 177257dacad5SJay Sternberg if (blk_mq_alloc_tag_set(&dev->admin_tagset)) 177357dacad5SJay Sternberg return -ENOMEM; 177434b6c231SSagi Grimberg dev->ctrl.admin_tagset = &dev->admin_tagset; 177557dacad5SJay Sternberg 17761c63dc66SChristoph Hellwig dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset); 17771c63dc66SChristoph Hellwig if (IS_ERR(dev->ctrl.admin_q)) { 177857dacad5SJay Sternberg blk_mq_free_tag_set(&dev->admin_tagset); 1779da427611SSmith, Kyle Miller (Nimble Kernel) dev->ctrl.admin_q = NULL; 178057dacad5SJay Sternberg return -ENOMEM; 178157dacad5SJay Sternberg } 17821c63dc66SChristoph Hellwig if (!blk_get_queue(dev->ctrl.admin_q)) { 178357dacad5SJay Sternberg nvme_dev_remove_admin(dev); 17841c63dc66SChristoph Hellwig dev->ctrl.admin_q = NULL; 178557dacad5SJay Sternberg return -ENODEV; 178657dacad5SJay Sternberg } 178757dacad5SJay Sternberg } else 17886ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 178957dacad5SJay Sternberg 179057dacad5SJay Sternberg return 0; 179157dacad5SJay Sternberg } 179257dacad5SJay Sternberg 179397f6ef64SXu Yu static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues) 179497f6ef64SXu Yu { 179597f6ef64SXu Yu return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride); 179697f6ef64SXu Yu } 179797f6ef64SXu Yu 179897f6ef64SXu Yu static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size) 179997f6ef64SXu Yu { 180097f6ef64SXu Yu struct pci_dev *pdev = to_pci_dev(dev->dev); 180197f6ef64SXu Yu 180297f6ef64SXu Yu if (size <= dev->bar_mapped_size) 180397f6ef64SXu Yu return 0; 180497f6ef64SXu Yu if (size > pci_resource_len(pdev, 0)) 180597f6ef64SXu Yu return -ENOMEM; 180697f6ef64SXu Yu if (dev->bar) 180797f6ef64SXu Yu iounmap(dev->bar); 180897f6ef64SXu Yu dev->bar = ioremap(pci_resource_start(pdev, 0), size); 180997f6ef64SXu Yu if (!dev->bar) { 181097f6ef64SXu Yu dev->bar_mapped_size = 0; 181197f6ef64SXu Yu return -ENOMEM; 181297f6ef64SXu Yu } 181397f6ef64SXu Yu dev->bar_mapped_size = size; 181497f6ef64SXu Yu dev->dbs = dev->bar + NVME_REG_DBS; 181597f6ef64SXu Yu 181697f6ef64SXu Yu return 0; 181797f6ef64SXu Yu } 181897f6ef64SXu Yu 181901ad0990SSagi Grimberg static int nvme_pci_configure_admin_queue(struct nvme_dev *dev) 182057dacad5SJay Sternberg { 182157dacad5SJay Sternberg int result; 182257dacad5SJay Sternberg u32 aqa; 182357dacad5SJay Sternberg struct nvme_queue *nvmeq; 182457dacad5SJay Sternberg 182597f6ef64SXu Yu result = nvme_remap_bar(dev, db_bar_size(dev, 0)); 182697f6ef64SXu Yu if (result < 0) 182797f6ef64SXu Yu return result; 182897f6ef64SXu Yu 18298ef2074dSGabriel Krisman Bertazi dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ? 183020d0dfe6SSagi Grimberg NVME_CAP_NSSRC(dev->ctrl.cap) : 0; 183157dacad5SJay Sternberg 18327a67cbeaSChristoph Hellwig if (dev->subsystem && 18337a67cbeaSChristoph Hellwig (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO)) 18347a67cbeaSChristoph Hellwig writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS); 183557dacad5SJay Sternberg 1836b5b05048SSagi Grimberg result = nvme_disable_ctrl(&dev->ctrl); 183757dacad5SJay Sternberg if (result < 0) 183857dacad5SJay Sternberg return result; 183957dacad5SJay Sternberg 1840a6ff7262SKeith Busch result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH); 1841147b27e4SSagi Grimberg if (result) 1842147b27e4SSagi Grimberg return result; 184357dacad5SJay Sternberg 1844635333e4SMax Gurtovoy dev->ctrl.numa_node = dev_to_node(dev->dev); 1845635333e4SMax Gurtovoy 1846147b27e4SSagi Grimberg nvmeq = &dev->queues[0]; 184757dacad5SJay Sternberg aqa = nvmeq->q_depth - 1; 184857dacad5SJay Sternberg aqa |= aqa << 16; 184957dacad5SJay Sternberg 18507a67cbeaSChristoph Hellwig writel(aqa, dev->bar + NVME_REG_AQA); 18517a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ); 18527a67cbeaSChristoph Hellwig lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ); 185357dacad5SJay Sternberg 1854c0f2f45bSSagi Grimberg result = nvme_enable_ctrl(&dev->ctrl); 185557dacad5SJay Sternberg if (result) 1856d4875622SKeith Busch return result; 185757dacad5SJay Sternberg 185857dacad5SJay Sternberg nvmeq->cq_vector = 0; 1859161b8be2SKeith Busch nvme_init_queue(nvmeq, 0); 1860dca51e78SChristoph Hellwig result = queue_request_irq(nvmeq); 186157dacad5SJay Sternberg if (result) { 18627c349ddeSKeith Busch dev->online_queues--; 1863d4875622SKeith Busch return result; 186457dacad5SJay Sternberg } 186557dacad5SJay Sternberg 18664e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &nvmeq->flags); 186757dacad5SJay Sternberg return result; 186857dacad5SJay Sternberg } 186957dacad5SJay Sternberg 1870749941f2SChristoph Hellwig static int nvme_create_io_queues(struct nvme_dev *dev) 187157dacad5SJay Sternberg { 18724b04cc6aSJens Axboe unsigned i, max, rw_queues; 1873749941f2SChristoph Hellwig int ret = 0; 187457dacad5SJay Sternberg 1875d858e5f0SSagi Grimberg for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) { 1876a6ff7262SKeith Busch if (nvme_alloc_queue(dev, i, dev->q_depth)) { 1877749941f2SChristoph Hellwig ret = -ENOMEM; 187857dacad5SJay Sternberg break; 1879749941f2SChristoph Hellwig } 1880749941f2SChristoph Hellwig } 188157dacad5SJay Sternberg 1882d858e5f0SSagi Grimberg max = min(dev->max_qid, dev->ctrl.queue_count - 1); 1883e20ba6e1SChristoph Hellwig if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) { 1884e20ba6e1SChristoph Hellwig rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] + 1885e20ba6e1SChristoph Hellwig dev->io_queues[HCTX_TYPE_READ]; 18864b04cc6aSJens Axboe } else { 18874b04cc6aSJens Axboe rw_queues = max; 18884b04cc6aSJens Axboe } 18894b04cc6aSJens Axboe 1890949928c1SKeith Busch for (i = dev->online_queues; i <= max; i++) { 18914b04cc6aSJens Axboe bool polled = i > rw_queues; 18924b04cc6aSJens Axboe 18934b04cc6aSJens Axboe ret = nvme_create_queue(&dev->queues[i], i, polled); 1894d4875622SKeith Busch if (ret) 189557dacad5SJay Sternberg break; 189657dacad5SJay Sternberg } 189757dacad5SJay Sternberg 1898749941f2SChristoph Hellwig /* 1899749941f2SChristoph Hellwig * Ignore failing Create SQ/CQ commands, we can continue with less 19008adb8c14SMinwoo Im * than the desired amount of queues, and even a controller without 19018adb8c14SMinwoo Im * I/O queues can still be used to issue admin commands. This might 1902749941f2SChristoph Hellwig * be useful to upgrade a buggy firmware for example. 1903749941f2SChristoph Hellwig */ 1904749941f2SChristoph Hellwig return ret >= 0 ? 0 : ret; 190557dacad5SJay Sternberg } 190657dacad5SJay Sternberg 190788de4598SChristoph Hellwig static u64 nvme_cmb_size_unit(struct nvme_dev *dev) 190857dacad5SJay Sternberg { 190988de4598SChristoph Hellwig u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK; 191088de4598SChristoph Hellwig 191188de4598SChristoph Hellwig return 1ULL << (12 + 4 * szu); 191288de4598SChristoph Hellwig } 191388de4598SChristoph Hellwig 191488de4598SChristoph Hellwig static u32 nvme_cmb_size(struct nvme_dev *dev) 191588de4598SChristoph Hellwig { 191688de4598SChristoph Hellwig return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK; 191788de4598SChristoph Hellwig } 191888de4598SChristoph Hellwig 1919f65efd6dSChristoph Hellwig static void nvme_map_cmb(struct nvme_dev *dev) 192057dacad5SJay Sternberg { 192188de4598SChristoph Hellwig u64 size, offset; 192257dacad5SJay Sternberg resource_size_t bar_size; 192357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 19248969f1f8SChristoph Hellwig int bar; 192557dacad5SJay Sternberg 19269fe5c59fSKeith Busch if (dev->cmb_size) 19279fe5c59fSKeith Busch return; 19289fe5c59fSKeith Busch 192920d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) 193020d3bb92SKlaus Jensen writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC); 193120d3bb92SKlaus Jensen 19327a67cbeaSChristoph Hellwig dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ); 1933f65efd6dSChristoph Hellwig if (!dev->cmbsz) 1934f65efd6dSChristoph Hellwig return; 1935202021c1SStephen Bates dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC); 193657dacad5SJay Sternberg 193788de4598SChristoph Hellwig size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev); 193888de4598SChristoph Hellwig offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc); 19398969f1f8SChristoph Hellwig bar = NVME_CMB_BIR(dev->cmbloc); 19408969f1f8SChristoph Hellwig bar_size = pci_resource_len(pdev, bar); 194157dacad5SJay Sternberg 194257dacad5SJay Sternberg if (offset > bar_size) 1943f65efd6dSChristoph Hellwig return; 194457dacad5SJay Sternberg 194557dacad5SJay Sternberg /* 194620d3bb92SKlaus Jensen * Tell the controller about the host side address mapping the CMB, 194720d3bb92SKlaus Jensen * and enable CMB decoding for the NVMe 1.4+ scheme: 194820d3bb92SKlaus Jensen */ 194920d3bb92SKlaus Jensen if (NVME_CAP_CMBS(dev->ctrl.cap)) { 195020d3bb92SKlaus Jensen hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE | 195120d3bb92SKlaus Jensen (pci_bus_address(pdev, bar) + offset), 195220d3bb92SKlaus Jensen dev->bar + NVME_REG_CMBMSC); 195320d3bb92SKlaus Jensen } 195420d3bb92SKlaus Jensen 195520d3bb92SKlaus Jensen /* 195657dacad5SJay Sternberg * Controllers may support a CMB size larger than their BAR, 195757dacad5SJay Sternberg * for example, due to being behind a bridge. Reduce the CMB to 195857dacad5SJay Sternberg * the reported size of the BAR 195957dacad5SJay Sternberg */ 196057dacad5SJay Sternberg if (size > bar_size - offset) 196157dacad5SJay Sternberg size = bar_size - offset; 196257dacad5SJay Sternberg 19630f238ff5SLogan Gunthorpe if (pci_p2pdma_add_resource(pdev, bar, size, offset)) { 19640f238ff5SLogan Gunthorpe dev_warn(dev->ctrl.device, 19650f238ff5SLogan Gunthorpe "failed to register the CMB\n"); 1966f65efd6dSChristoph Hellwig return; 19670f238ff5SLogan Gunthorpe } 19680f238ff5SLogan Gunthorpe 196957dacad5SJay Sternberg dev->cmb_size = size; 19700f238ff5SLogan Gunthorpe dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS); 19710f238ff5SLogan Gunthorpe 19720f238ff5SLogan Gunthorpe if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) == 19730f238ff5SLogan Gunthorpe (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) 19740f238ff5SLogan Gunthorpe pci_p2pmem_publish(pdev, true); 197557dacad5SJay Sternberg } 197657dacad5SJay Sternberg 197787ad72a5SChristoph Hellwig static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits) 197857dacad5SJay Sternberg { 19796c3c05b0SChaitanya Kulkarni u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT; 19804033f35dSChristoph Hellwig u64 dma_addr = dev->host_mem_descs_dma; 1981f66e2804SChaitanya Kulkarni struct nvme_command c = { }; 198287ad72a5SChristoph Hellwig int ret; 198387ad72a5SChristoph Hellwig 198487ad72a5SChristoph Hellwig c.features.opcode = nvme_admin_set_features; 198587ad72a5SChristoph Hellwig c.features.fid = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF); 198687ad72a5SChristoph Hellwig c.features.dword11 = cpu_to_le32(bits); 19876c3c05b0SChaitanya Kulkarni c.features.dword12 = cpu_to_le32(host_mem_size); 198887ad72a5SChristoph Hellwig c.features.dword13 = cpu_to_le32(lower_32_bits(dma_addr)); 198987ad72a5SChristoph Hellwig c.features.dword14 = cpu_to_le32(upper_32_bits(dma_addr)); 199087ad72a5SChristoph Hellwig c.features.dword15 = cpu_to_le32(dev->nr_host_mem_descs); 199187ad72a5SChristoph Hellwig 199287ad72a5SChristoph Hellwig ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0); 199387ad72a5SChristoph Hellwig if (ret) { 199487ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 199587ad72a5SChristoph Hellwig "failed to set host mem (err %d, flags %#x).\n", 199687ad72a5SChristoph Hellwig ret, bits); 1997a5df5e79SKeith Busch } else 1998a5df5e79SKeith Busch dev->hmb = bits & NVME_HOST_MEM_ENABLE; 1999a5df5e79SKeith Busch 200087ad72a5SChristoph Hellwig return ret; 200187ad72a5SChristoph Hellwig } 200287ad72a5SChristoph Hellwig 200387ad72a5SChristoph Hellwig static void nvme_free_host_mem(struct nvme_dev *dev) 200487ad72a5SChristoph Hellwig { 200587ad72a5SChristoph Hellwig int i; 200687ad72a5SChristoph Hellwig 200787ad72a5SChristoph Hellwig for (i = 0; i < dev->nr_host_mem_descs; i++) { 200887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i]; 20096c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE; 201087ad72a5SChristoph Hellwig 2011cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i], 2012cc667f6dSLiviu Dudau le64_to_cpu(desc->addr), 2013cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 201487ad72a5SChristoph Hellwig } 201587ad72a5SChristoph Hellwig 201687ad72a5SChristoph Hellwig kfree(dev->host_mem_desc_bufs); 201787ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = NULL; 20184033f35dSChristoph Hellwig dma_free_coherent(dev->dev, 20194033f35dSChristoph Hellwig dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs), 20204033f35dSChristoph Hellwig dev->host_mem_descs, dev->host_mem_descs_dma); 202187ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 20227e5dd57eSMinwoo Im dev->nr_host_mem_descs = 0; 202387ad72a5SChristoph Hellwig } 202487ad72a5SChristoph Hellwig 202592dc6895SChristoph Hellwig static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred, 202692dc6895SChristoph Hellwig u32 chunk_size) 202787ad72a5SChristoph Hellwig { 202887ad72a5SChristoph Hellwig struct nvme_host_mem_buf_desc *descs; 202992dc6895SChristoph Hellwig u32 max_entries, len; 20304033f35dSChristoph Hellwig dma_addr_t descs_dma; 20312ee0e4edSDan Carpenter int i = 0; 203287ad72a5SChristoph Hellwig void **bufs; 20336fbcde66SMinwoo Im u64 size, tmp; 203487ad72a5SChristoph Hellwig 203587ad72a5SChristoph Hellwig tmp = (preferred + chunk_size - 1); 203687ad72a5SChristoph Hellwig do_div(tmp, chunk_size); 203787ad72a5SChristoph Hellwig max_entries = tmp; 2038044a9df1SChristoph Hellwig 2039044a9df1SChristoph Hellwig if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries) 2040044a9df1SChristoph Hellwig max_entries = dev->ctrl.hmmaxd; 2041044a9df1SChristoph Hellwig 2042750afb08SLuis Chamberlain descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs), 20434033f35dSChristoph Hellwig &descs_dma, GFP_KERNEL); 204487ad72a5SChristoph Hellwig if (!descs) 204587ad72a5SChristoph Hellwig goto out; 204687ad72a5SChristoph Hellwig 204787ad72a5SChristoph Hellwig bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL); 204887ad72a5SChristoph Hellwig if (!bufs) 204987ad72a5SChristoph Hellwig goto out_free_descs; 205087ad72a5SChristoph Hellwig 2051244a8fe4SMinwoo Im for (size = 0; size < preferred && i < max_entries; size += len) { 205287ad72a5SChristoph Hellwig dma_addr_t dma_addr; 205387ad72a5SChristoph Hellwig 205450cdb7c6SChristoph Hellwig len = min_t(u64, chunk_size, preferred - size); 205587ad72a5SChristoph Hellwig bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL, 205687ad72a5SChristoph Hellwig DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 205787ad72a5SChristoph Hellwig if (!bufs[i]) 205887ad72a5SChristoph Hellwig break; 205987ad72a5SChristoph Hellwig 206087ad72a5SChristoph Hellwig descs[i].addr = cpu_to_le64(dma_addr); 20616c3c05b0SChaitanya Kulkarni descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE); 206287ad72a5SChristoph Hellwig i++; 206387ad72a5SChristoph Hellwig } 206487ad72a5SChristoph Hellwig 206592dc6895SChristoph Hellwig if (!size) 206687ad72a5SChristoph Hellwig goto out_free_bufs; 206787ad72a5SChristoph Hellwig 206887ad72a5SChristoph Hellwig dev->nr_host_mem_descs = i; 206987ad72a5SChristoph Hellwig dev->host_mem_size = size; 207087ad72a5SChristoph Hellwig dev->host_mem_descs = descs; 20714033f35dSChristoph Hellwig dev->host_mem_descs_dma = descs_dma; 207287ad72a5SChristoph Hellwig dev->host_mem_desc_bufs = bufs; 207387ad72a5SChristoph Hellwig return 0; 207487ad72a5SChristoph Hellwig 207587ad72a5SChristoph Hellwig out_free_bufs: 207687ad72a5SChristoph Hellwig while (--i >= 0) { 20776c3c05b0SChaitanya Kulkarni size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE; 207887ad72a5SChristoph Hellwig 2079cc667f6dSLiviu Dudau dma_free_attrs(dev->dev, size, bufs[i], 2080cc667f6dSLiviu Dudau le64_to_cpu(descs[i].addr), 2081cc667f6dSLiviu Dudau DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN); 208287ad72a5SChristoph Hellwig } 208387ad72a5SChristoph Hellwig 208487ad72a5SChristoph Hellwig kfree(bufs); 208587ad72a5SChristoph Hellwig out_free_descs: 20864033f35dSChristoph Hellwig dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs, 20874033f35dSChristoph Hellwig descs_dma); 208887ad72a5SChristoph Hellwig out: 208987ad72a5SChristoph Hellwig dev->host_mem_descs = NULL; 209087ad72a5SChristoph Hellwig return -ENOMEM; 209187ad72a5SChristoph Hellwig } 209287ad72a5SChristoph Hellwig 209392dc6895SChristoph Hellwig static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred) 209492dc6895SChristoph Hellwig { 20959dc54a0dSChaitanya Kulkarni u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES); 20969dc54a0dSChaitanya Kulkarni u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2); 20979dc54a0dSChaitanya Kulkarni u64 chunk_size; 209892dc6895SChristoph Hellwig 209992dc6895SChristoph Hellwig /* start big and work our way down */ 21009dc54a0dSChaitanya Kulkarni for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) { 210192dc6895SChristoph Hellwig if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) { 210292dc6895SChristoph Hellwig if (!min || dev->host_mem_size >= min) 210392dc6895SChristoph Hellwig return 0; 210492dc6895SChristoph Hellwig nvme_free_host_mem(dev); 210592dc6895SChristoph Hellwig } 210692dc6895SChristoph Hellwig } 210792dc6895SChristoph Hellwig 210892dc6895SChristoph Hellwig return -ENOMEM; 210992dc6895SChristoph Hellwig } 211092dc6895SChristoph Hellwig 21119620cfbaSChristoph Hellwig static int nvme_setup_host_mem(struct nvme_dev *dev) 211287ad72a5SChristoph Hellwig { 211387ad72a5SChristoph Hellwig u64 max = (u64)max_host_mem_size_mb * SZ_1M; 211487ad72a5SChristoph Hellwig u64 preferred = (u64)dev->ctrl.hmpre * 4096; 211587ad72a5SChristoph Hellwig u64 min = (u64)dev->ctrl.hmmin * 4096; 211687ad72a5SChristoph Hellwig u32 enable_bits = NVME_HOST_MEM_ENABLE; 21176fbcde66SMinwoo Im int ret; 211887ad72a5SChristoph Hellwig 211987ad72a5SChristoph Hellwig preferred = min(preferred, max); 212087ad72a5SChristoph Hellwig if (min > max) { 212187ad72a5SChristoph Hellwig dev_warn(dev->ctrl.device, 212287ad72a5SChristoph Hellwig "min host memory (%lld MiB) above limit (%d MiB).\n", 212387ad72a5SChristoph Hellwig min >> ilog2(SZ_1M), max_host_mem_size_mb); 212487ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21259620cfbaSChristoph Hellwig return 0; 212687ad72a5SChristoph Hellwig } 212787ad72a5SChristoph Hellwig 212887ad72a5SChristoph Hellwig /* 212987ad72a5SChristoph Hellwig * If we already have a buffer allocated check if we can reuse it. 213087ad72a5SChristoph Hellwig */ 213187ad72a5SChristoph Hellwig if (dev->host_mem_descs) { 213287ad72a5SChristoph Hellwig if (dev->host_mem_size >= min) 213387ad72a5SChristoph Hellwig enable_bits |= NVME_HOST_MEM_RETURN; 213487ad72a5SChristoph Hellwig else 213587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 213687ad72a5SChristoph Hellwig } 213787ad72a5SChristoph Hellwig 213887ad72a5SChristoph Hellwig if (!dev->host_mem_descs) { 213992dc6895SChristoph Hellwig if (nvme_alloc_host_mem(dev, min, preferred)) { 214092dc6895SChristoph Hellwig dev_warn(dev->ctrl.device, 214192dc6895SChristoph Hellwig "failed to allocate host memory buffer.\n"); 21429620cfbaSChristoph Hellwig return 0; /* controller must work without HMB */ 214387ad72a5SChristoph Hellwig } 214487ad72a5SChristoph Hellwig 214592dc6895SChristoph Hellwig dev_info(dev->ctrl.device, 214692dc6895SChristoph Hellwig "allocated %lld MiB host memory buffer.\n", 214792dc6895SChristoph Hellwig dev->host_mem_size >> ilog2(SZ_1M)); 214892dc6895SChristoph Hellwig } 214992dc6895SChristoph Hellwig 21509620cfbaSChristoph Hellwig ret = nvme_set_host_mem(dev, enable_bits); 21519620cfbaSChristoph Hellwig if (ret) 215287ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 21539620cfbaSChristoph Hellwig return ret; 215457dacad5SJay Sternberg } 215557dacad5SJay Sternberg 21560521905eSKeith Busch static ssize_t cmb_show(struct device *dev, struct device_attribute *attr, 21570521905eSKeith Busch char *buf) 21580521905eSKeith Busch { 21590521905eSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21600521905eSKeith Busch 21610521905eSKeith Busch return sysfs_emit(buf, "cmbloc : x%08x\ncmbsz : x%08x\n", 21620521905eSKeith Busch ndev->cmbloc, ndev->cmbsz); 21630521905eSKeith Busch } 21640521905eSKeith Busch static DEVICE_ATTR_RO(cmb); 21650521905eSKeith Busch 21661751e97aSKeith Busch static ssize_t cmbloc_show(struct device *dev, struct device_attribute *attr, 21671751e97aSKeith Busch char *buf) 21681751e97aSKeith Busch { 21691751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21701751e97aSKeith Busch 21711751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbloc); 21721751e97aSKeith Busch } 21731751e97aSKeith Busch static DEVICE_ATTR_RO(cmbloc); 21741751e97aSKeith Busch 21751751e97aSKeith Busch static ssize_t cmbsz_show(struct device *dev, struct device_attribute *attr, 21761751e97aSKeith Busch char *buf) 21771751e97aSKeith Busch { 21781751e97aSKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 21791751e97aSKeith Busch 21801751e97aSKeith Busch return sysfs_emit(buf, "%u\n", ndev->cmbsz); 21811751e97aSKeith Busch } 21821751e97aSKeith Busch static DEVICE_ATTR_RO(cmbsz); 21831751e97aSKeith Busch 2184a5df5e79SKeith Busch static ssize_t hmb_show(struct device *dev, struct device_attribute *attr, 2185a5df5e79SKeith Busch char *buf) 2186a5df5e79SKeith Busch { 2187a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2188a5df5e79SKeith Busch 2189a5df5e79SKeith Busch return sysfs_emit(buf, "%d\n", ndev->hmb); 2190a5df5e79SKeith Busch } 2191a5df5e79SKeith Busch 2192a5df5e79SKeith Busch static ssize_t hmb_store(struct device *dev, struct device_attribute *attr, 2193a5df5e79SKeith Busch const char *buf, size_t count) 2194a5df5e79SKeith Busch { 2195a5df5e79SKeith Busch struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev)); 2196a5df5e79SKeith Busch bool new; 2197a5df5e79SKeith Busch int ret; 2198a5df5e79SKeith Busch 2199a5df5e79SKeith Busch if (strtobool(buf, &new) < 0) 2200a5df5e79SKeith Busch return -EINVAL; 2201a5df5e79SKeith Busch 2202a5df5e79SKeith Busch if (new == ndev->hmb) 2203a5df5e79SKeith Busch return count; 2204a5df5e79SKeith Busch 2205a5df5e79SKeith Busch if (new) { 2206a5df5e79SKeith Busch ret = nvme_setup_host_mem(ndev); 2207a5df5e79SKeith Busch } else { 2208a5df5e79SKeith Busch ret = nvme_set_host_mem(ndev, 0); 2209a5df5e79SKeith Busch if (!ret) 2210a5df5e79SKeith Busch nvme_free_host_mem(ndev); 2211a5df5e79SKeith Busch } 2212a5df5e79SKeith Busch 2213a5df5e79SKeith Busch if (ret < 0) 2214a5df5e79SKeith Busch return ret; 2215a5df5e79SKeith Busch 2216a5df5e79SKeith Busch return count; 2217a5df5e79SKeith Busch } 2218a5df5e79SKeith Busch static DEVICE_ATTR_RW(hmb); 2219a5df5e79SKeith Busch 22200521905eSKeith Busch static umode_t nvme_pci_attrs_are_visible(struct kobject *kobj, 22210521905eSKeith Busch struct attribute *a, int n) 22220521905eSKeith Busch { 22230521905eSKeith Busch struct nvme_ctrl *ctrl = 22240521905eSKeith Busch dev_get_drvdata(container_of(kobj, struct device, kobj)); 22250521905eSKeith Busch struct nvme_dev *dev = to_nvme_dev(ctrl); 22260521905eSKeith Busch 22271751e97aSKeith Busch if (a == &dev_attr_cmb.attr || 22281751e97aSKeith Busch a == &dev_attr_cmbloc.attr || 22291751e97aSKeith Busch a == &dev_attr_cmbsz.attr) { 22301751e97aSKeith Busch if (!dev->cmbsz) 22310521905eSKeith Busch return 0; 22321751e97aSKeith Busch } 2233a5df5e79SKeith Busch if (a == &dev_attr_hmb.attr && !ctrl->hmpre) 2234a5df5e79SKeith Busch return 0; 2235a5df5e79SKeith Busch 22360521905eSKeith Busch return a->mode; 22370521905eSKeith Busch } 22380521905eSKeith Busch 22390521905eSKeith Busch static struct attribute *nvme_pci_attrs[] = { 22400521905eSKeith Busch &dev_attr_cmb.attr, 22411751e97aSKeith Busch &dev_attr_cmbloc.attr, 22421751e97aSKeith Busch &dev_attr_cmbsz.attr, 2243a5df5e79SKeith Busch &dev_attr_hmb.attr, 22440521905eSKeith Busch NULL, 22450521905eSKeith Busch }; 22460521905eSKeith Busch 22470521905eSKeith Busch static const struct attribute_group nvme_pci_attr_group = { 22480521905eSKeith Busch .attrs = nvme_pci_attrs, 22490521905eSKeith Busch .is_visible = nvme_pci_attrs_are_visible, 22500521905eSKeith Busch }; 22510521905eSKeith Busch 2252612b7286SMing Lei /* 2253612b7286SMing Lei * nirqs is the number of interrupts available for write and read 2254612b7286SMing Lei * queues. The core already reserved an interrupt for the admin queue. 2255612b7286SMing Lei */ 2256612b7286SMing Lei static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs) 22573b6592f7SJens Axboe { 2258612b7286SMing Lei struct nvme_dev *dev = affd->priv; 22592a5bcfddSWeiping Zhang unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues; 2260c45b1fa2SMing Lei 22613b6592f7SJens Axboe /* 2262ee0d96d3SBaolin Wang * If there is no interrupt available for queues, ensure that 2263612b7286SMing Lei * the default queue is set to 1. The affinity set size is 2264612b7286SMing Lei * also set to one, but the irq core ignores it for this case. 2265612b7286SMing Lei * 2266612b7286SMing Lei * If only one interrupt is available or 'write_queue' == 0, combine 2267612b7286SMing Lei * write and read queues. 2268612b7286SMing Lei * 2269612b7286SMing Lei * If 'write_queues' > 0, ensure it leaves room for at least one read 2270612b7286SMing Lei * queue. 22713b6592f7SJens Axboe */ 2272612b7286SMing Lei if (!nrirqs) { 2273612b7286SMing Lei nrirqs = 1; 2274612b7286SMing Lei nr_read_queues = 0; 22752a5bcfddSWeiping Zhang } else if (nrirqs == 1 || !nr_write_queues) { 2276612b7286SMing Lei nr_read_queues = 0; 22772a5bcfddSWeiping Zhang } else if (nr_write_queues >= nrirqs) { 2278612b7286SMing Lei nr_read_queues = 1; 22793b6592f7SJens Axboe } else { 22802a5bcfddSWeiping Zhang nr_read_queues = nrirqs - nr_write_queues; 22813b6592f7SJens Axboe } 2282612b7286SMing Lei 2283612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2284612b7286SMing Lei affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues; 2285612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = nr_read_queues; 2286612b7286SMing Lei affd->set_size[HCTX_TYPE_READ] = nr_read_queues; 2287612b7286SMing Lei affd->nr_sets = nr_read_queues ? 2 : 1; 22883b6592f7SJens Axboe } 22893b6592f7SJens Axboe 22906451fe73SJens Axboe static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues) 22913b6592f7SJens Axboe { 22923b6592f7SJens Axboe struct pci_dev *pdev = to_pci_dev(dev->dev); 22933b6592f7SJens Axboe struct irq_affinity affd = { 22943b6592f7SJens Axboe .pre_vectors = 1, 2295612b7286SMing Lei .calc_sets = nvme_calc_irq_sets, 2296612b7286SMing Lei .priv = dev, 22973b6592f7SJens Axboe }; 229821cc2f3fSJeffle Xu unsigned int irq_queues, poll_queues; 22996451fe73SJens Axboe 23006451fe73SJens Axboe /* 230121cc2f3fSJeffle Xu * Poll queues don't need interrupts, but we need at least one I/O queue 230221cc2f3fSJeffle Xu * left over for non-polled I/O. 23036451fe73SJens Axboe */ 230421cc2f3fSJeffle Xu poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1); 230521cc2f3fSJeffle Xu dev->io_queues[HCTX_TYPE_POLL] = poll_queues; 23063b6592f7SJens Axboe 230721cc2f3fSJeffle Xu /* 230821cc2f3fSJeffle Xu * Initialize for the single interrupt case, will be updated in 230921cc2f3fSJeffle Xu * nvme_calc_irq_sets(). 231021cc2f3fSJeffle Xu */ 2311612b7286SMing Lei dev->io_queues[HCTX_TYPE_DEFAULT] = 1; 2312612b7286SMing Lei dev->io_queues[HCTX_TYPE_READ] = 0; 23133b6592f7SJens Axboe 231466341331SBenjamin Herrenschmidt /* 231521cc2f3fSJeffle Xu * We need interrupts for the admin queue and each non-polled I/O queue, 231621cc2f3fSJeffle Xu * but some Apple controllers require all queues to use the first 231721cc2f3fSJeffle Xu * vector. 231866341331SBenjamin Herrenschmidt */ 231966341331SBenjamin Herrenschmidt irq_queues = 1; 232021cc2f3fSJeffle Xu if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR)) 232121cc2f3fSJeffle Xu irq_queues += (nr_io_queues - poll_queues); 2322612b7286SMing Lei return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues, 23233b6592f7SJens Axboe PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd); 23243b6592f7SJens Axboe } 23253b6592f7SJens Axboe 23268fae268bSKeith Busch static void nvme_disable_io_queues(struct nvme_dev *dev) 23278fae268bSKeith Busch { 23288fae268bSKeith Busch if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq)) 23298fae268bSKeith Busch __nvme_disable_io_queues(dev, nvme_admin_delete_cq); 23308fae268bSKeith Busch } 23318fae268bSKeith Busch 23322a5bcfddSWeiping Zhang static unsigned int nvme_max_io_queues(struct nvme_dev *dev) 23332a5bcfddSWeiping Zhang { 2334e3aef095SNiklas Schnelle /* 2335e3aef095SNiklas Schnelle * If tags are shared with admin queue (Apple bug), then 2336e3aef095SNiklas Schnelle * make sure we only use one IO queue. 2337e3aef095SNiklas Schnelle */ 2338e3aef095SNiklas Schnelle if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2339e3aef095SNiklas Schnelle return 1; 23402a5bcfddSWeiping Zhang return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues; 23412a5bcfddSWeiping Zhang } 23422a5bcfddSWeiping Zhang 234357dacad5SJay Sternberg static int nvme_setup_io_queues(struct nvme_dev *dev) 234457dacad5SJay Sternberg { 2345147b27e4SSagi Grimberg struct nvme_queue *adminq = &dev->queues[0]; 234657dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 23472a5bcfddSWeiping Zhang unsigned int nr_io_queues; 234897f6ef64SXu Yu unsigned long size; 23492a5bcfddSWeiping Zhang int result; 235057dacad5SJay Sternberg 23512a5bcfddSWeiping Zhang /* 23522a5bcfddSWeiping Zhang * Sample the module parameters once at reset time so that we have 23532a5bcfddSWeiping Zhang * stable values to work with. 23542a5bcfddSWeiping Zhang */ 23552a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 23562a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 2357d38e9f04SBenjamin Herrenschmidt 2358ff4e5fbaSNiklas Schnelle nr_io_queues = dev->nr_allocated_queues - 1; 23599a0be7abSChristoph Hellwig result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues); 23609a0be7abSChristoph Hellwig if (result < 0) 236157dacad5SJay Sternberg return result; 23629a0be7abSChristoph Hellwig 2363f5fa90dcSChristoph Hellwig if (nr_io_queues == 0) 2364a5229050SKeith Busch return 0; 236557dacad5SJay Sternberg 2366e4b9852aSCasey Chen /* 2367e4b9852aSCasey Chen * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions 2368e4b9852aSCasey Chen * from set to unset. If there is a window to it is truely freed, 2369e4b9852aSCasey Chen * pci_free_irq_vectors() jumping into this window will crash. 2370e4b9852aSCasey Chen * And take lock to avoid racing with pci_free_irq_vectors() in 2371e4b9852aSCasey Chen * nvme_dev_disable() path. 2372e4b9852aSCasey Chen */ 2373e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2374e4b9852aSCasey Chen if (result) 2375e4b9852aSCasey Chen return result; 2376e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 2377e4b9852aSCasey Chen pci_free_irq(pdev, 0, adminq); 23784e224106SChristoph Hellwig 23790f238ff5SLogan Gunthorpe if (dev->cmb_use_sqes) { 238057dacad5SJay Sternberg result = nvme_cmb_qdepth(dev, nr_io_queues, 238157dacad5SJay Sternberg sizeof(struct nvme_command)); 238257dacad5SJay Sternberg if (result > 0) 238357dacad5SJay Sternberg dev->q_depth = result; 238457dacad5SJay Sternberg else 23850f238ff5SLogan Gunthorpe dev->cmb_use_sqes = false; 238657dacad5SJay Sternberg } 238757dacad5SJay Sternberg 238857dacad5SJay Sternberg do { 238997f6ef64SXu Yu size = db_bar_size(dev, nr_io_queues); 239097f6ef64SXu Yu result = nvme_remap_bar(dev, size); 239197f6ef64SXu Yu if (!result) 239257dacad5SJay Sternberg break; 2393e4b9852aSCasey Chen if (!--nr_io_queues) { 2394e4b9852aSCasey Chen result = -ENOMEM; 2395e4b9852aSCasey Chen goto out_unlock; 2396e4b9852aSCasey Chen } 239757dacad5SJay Sternberg } while (1); 239857dacad5SJay Sternberg adminq->q_db = dev->dbs; 239957dacad5SJay Sternberg 24008fae268bSKeith Busch retry: 240157dacad5SJay Sternberg /* Deregister the admin queue's interrupt */ 2402e4b9852aSCasey Chen if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags)) 24030ff199cbSChristoph Hellwig pci_free_irq(pdev, 0, adminq); 240457dacad5SJay Sternberg 240557dacad5SJay Sternberg /* 240657dacad5SJay Sternberg * If we enable msix early due to not intx, disable it again before 240757dacad5SJay Sternberg * setting up the full range we need. 240857dacad5SJay Sternberg */ 2409dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 24103b6592f7SJens Axboe 24113b6592f7SJens Axboe result = nvme_setup_irqs(dev, nr_io_queues); 2412e4b9852aSCasey Chen if (result <= 0) { 2413e4b9852aSCasey Chen result = -EIO; 2414e4b9852aSCasey Chen goto out_unlock; 2415e4b9852aSCasey Chen } 24163b6592f7SJens Axboe 241722b55601SKeith Busch dev->num_vecs = result; 24184b04cc6aSJens Axboe result = max(result - 1, 1); 2419e20ba6e1SChristoph Hellwig dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL]; 242057dacad5SJay Sternberg 242157dacad5SJay Sternberg /* 242257dacad5SJay Sternberg * Should investigate if there's a performance win from allocating 242357dacad5SJay Sternberg * more queues than interrupt vectors; it might allow the submission 242457dacad5SJay Sternberg * path to scale better, even if the receive path is limited by the 242557dacad5SJay Sternberg * number of interrupts. 242657dacad5SJay Sternberg */ 2427dca51e78SChristoph Hellwig result = queue_request_irq(adminq); 24287c349ddeSKeith Busch if (result) 2429e4b9852aSCasey Chen goto out_unlock; 24304e224106SChristoph Hellwig set_bit(NVMEQ_ENABLED, &adminq->flags); 2431e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 24328fae268bSKeith Busch 24338fae268bSKeith Busch result = nvme_create_io_queues(dev); 24348fae268bSKeith Busch if (result || dev->online_queues < 2) 24358fae268bSKeith Busch return result; 24368fae268bSKeith Busch 24378fae268bSKeith Busch if (dev->online_queues - 1 < dev->max_qid) { 24388fae268bSKeith Busch nr_io_queues = dev->online_queues - 1; 24398fae268bSKeith Busch nvme_disable_io_queues(dev); 2440e4b9852aSCasey Chen result = nvme_setup_io_queues_trylock(dev); 2441e4b9852aSCasey Chen if (result) 2442e4b9852aSCasey Chen return result; 24438fae268bSKeith Busch nvme_suspend_io_queues(dev); 24448fae268bSKeith Busch goto retry; 24458fae268bSKeith Busch } 24468fae268bSKeith Busch dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n", 24478fae268bSKeith Busch dev->io_queues[HCTX_TYPE_DEFAULT], 24488fae268bSKeith Busch dev->io_queues[HCTX_TYPE_READ], 24498fae268bSKeith Busch dev->io_queues[HCTX_TYPE_POLL]); 24508fae268bSKeith Busch return 0; 2451e4b9852aSCasey Chen out_unlock: 2452e4b9852aSCasey Chen mutex_unlock(&dev->shutdown_lock); 2453e4b9852aSCasey Chen return result; 245457dacad5SJay Sternberg } 245557dacad5SJay Sternberg 24562a842acaSChristoph Hellwig static void nvme_del_queue_end(struct request *req, blk_status_t error) 2457db3cbfffSKeith Busch { 2458db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2459db3cbfffSKeith Busch 2460db3cbfffSKeith Busch blk_mq_free_request(req); 2461d1ed6aa1SChristoph Hellwig complete(&nvmeq->delete_done); 2462db3cbfffSKeith Busch } 2463db3cbfffSKeith Busch 24642a842acaSChristoph Hellwig static void nvme_del_cq_end(struct request *req, blk_status_t error) 2465db3cbfffSKeith Busch { 2466db3cbfffSKeith Busch struct nvme_queue *nvmeq = req->end_io_data; 2467db3cbfffSKeith Busch 2468d1ed6aa1SChristoph Hellwig if (error) 2469d1ed6aa1SChristoph Hellwig set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags); 2470db3cbfffSKeith Busch 2471db3cbfffSKeith Busch nvme_del_queue_end(req, error); 2472db3cbfffSKeith Busch } 2473db3cbfffSKeith Busch 2474db3cbfffSKeith Busch static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode) 2475db3cbfffSKeith Busch { 2476db3cbfffSKeith Busch struct request_queue *q = nvmeq->dev->ctrl.admin_q; 2477db3cbfffSKeith Busch struct request *req; 2478f66e2804SChaitanya Kulkarni struct nvme_command cmd = { }; 2479db3cbfffSKeith Busch 2480db3cbfffSKeith Busch cmd.delete_queue.opcode = opcode; 2481db3cbfffSKeith Busch cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid); 2482db3cbfffSKeith Busch 2483e559398fSChristoph Hellwig req = blk_mq_alloc_request(q, nvme_req_op(&cmd), BLK_MQ_REQ_NOWAIT); 2484db3cbfffSKeith Busch if (IS_ERR(req)) 2485db3cbfffSKeith Busch return PTR_ERR(req); 2486e559398fSChristoph Hellwig nvme_init_request(req, &cmd); 2487db3cbfffSKeith Busch 2488db3cbfffSKeith Busch req->end_io_data = nvmeq; 2489db3cbfffSKeith Busch 2490d1ed6aa1SChristoph Hellwig init_completion(&nvmeq->delete_done); 2491128126a7SChaitanya Kulkarni req->rq_flags |= RQF_QUIET; 2492b84ba30bSChristoph Hellwig blk_execute_rq_nowait(req, false, opcode == nvme_admin_delete_cq ? 2493db3cbfffSKeith Busch nvme_del_cq_end : nvme_del_queue_end); 2494db3cbfffSKeith Busch return 0; 2495db3cbfffSKeith Busch } 2496db3cbfffSKeith Busch 24978fae268bSKeith Busch static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode) 2498db3cbfffSKeith Busch { 24995271edd4SChristoph Hellwig int nr_queues = dev->online_queues - 1, sent = 0; 2500db3cbfffSKeith Busch unsigned long timeout; 2501db3cbfffSKeith Busch 2502db3cbfffSKeith Busch retry: 2503dc96f938SChaitanya Kulkarni timeout = NVME_ADMIN_TIMEOUT; 25045271edd4SChristoph Hellwig while (nr_queues > 0) { 25055271edd4SChristoph Hellwig if (nvme_delete_queue(&dev->queues[nr_queues], opcode)) 2506db3cbfffSKeith Busch break; 25075271edd4SChristoph Hellwig nr_queues--; 25085271edd4SChristoph Hellwig sent++; 25095271edd4SChristoph Hellwig } 2510d1ed6aa1SChristoph Hellwig while (sent) { 2511d1ed6aa1SChristoph Hellwig struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent]; 2512d1ed6aa1SChristoph Hellwig 2513d1ed6aa1SChristoph Hellwig timeout = wait_for_completion_io_timeout(&nvmeq->delete_done, 25145271edd4SChristoph Hellwig timeout); 2515db3cbfffSKeith Busch if (timeout == 0) 25165271edd4SChristoph Hellwig return false; 2517d1ed6aa1SChristoph Hellwig 2518d1ed6aa1SChristoph Hellwig sent--; 25195271edd4SChristoph Hellwig if (nr_queues) 2520db3cbfffSKeith Busch goto retry; 2521db3cbfffSKeith Busch } 25225271edd4SChristoph Hellwig return true; 2523db3cbfffSKeith Busch } 2524db3cbfffSKeith Busch 25255d02a5c1SKeith Busch static void nvme_dev_add(struct nvme_dev *dev) 252657dacad5SJay Sternberg { 25272b1b7e78SJianchao Wang int ret; 25282b1b7e78SJianchao Wang 25295bae7f73SChristoph Hellwig if (!dev->ctrl.tagset) { 2530c6d962aeSChristoph Hellwig dev->tagset.ops = &nvme_mq_ops; 253157dacad5SJay Sternberg dev->tagset.nr_hw_queues = dev->online_queues - 1; 25328fe34be1Syangerkun dev->tagset.nr_maps = 2; /* default + read */ 2533ed92ad37SChristoph Hellwig if (dev->io_queues[HCTX_TYPE_POLL]) 2534ed92ad37SChristoph Hellwig dev->tagset.nr_maps++; 253557dacad5SJay Sternberg dev->tagset.timeout = NVME_IO_TIMEOUT; 2536d4ec47f1SMax Gurtovoy dev->tagset.numa_node = dev->ctrl.numa_node; 253761f3b896SChaitanya Kulkarni dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth, 253861f3b896SChaitanya Kulkarni BLK_MQ_MAX_DEPTH) - 1; 2539d43f1ccfSChristoph Hellwig dev->tagset.cmd_size = sizeof(struct nvme_iod); 254057dacad5SJay Sternberg dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE; 254157dacad5SJay Sternberg dev->tagset.driver_data = dev; 254257dacad5SJay Sternberg 2543d38e9f04SBenjamin Herrenschmidt /* 2544d38e9f04SBenjamin Herrenschmidt * Some Apple controllers requires tags to be unique 2545d38e9f04SBenjamin Herrenschmidt * across admin and IO queue, so reserve the first 32 2546d38e9f04SBenjamin Herrenschmidt * tags of the IO queue. 2547d38e9f04SBenjamin Herrenschmidt */ 2548d38e9f04SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) 2549d38e9f04SBenjamin Herrenschmidt dev->tagset.reserved_tags = NVME_AQ_DEPTH; 2550d38e9f04SBenjamin Herrenschmidt 25512b1b7e78SJianchao Wang ret = blk_mq_alloc_tag_set(&dev->tagset); 25522b1b7e78SJianchao Wang if (ret) { 25532b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 25542b1b7e78SJianchao Wang "IO queues tagset allocation failed %d\n", ret); 25555d02a5c1SKeith Busch return; 25562b1b7e78SJianchao Wang } 25575bae7f73SChristoph Hellwig dev->ctrl.tagset = &dev->tagset; 2558949928c1SKeith Busch } else { 2559949928c1SKeith Busch blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1); 2560949928c1SKeith Busch 2561949928c1SKeith Busch /* Free previously allocated queues that are no longer usable */ 2562949928c1SKeith Busch nvme_free_queues(dev, dev->online_queues); 256357dacad5SJay Sternberg } 2564949928c1SKeith Busch 2565e8fd41bbSMaxim Levitsky nvme_dbbuf_set(dev); 256657dacad5SJay Sternberg } 256757dacad5SJay Sternberg 2568b00a726aSKeith Busch static int nvme_pci_enable(struct nvme_dev *dev) 256957dacad5SJay Sternberg { 2570b00a726aSKeith Busch int result = -ENOMEM; 257157dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 25724bdf2603SFilippo Sironi int dma_address_bits = 64; 257357dacad5SJay Sternberg 257457dacad5SJay Sternberg if (pci_enable_device_mem(pdev)) 257557dacad5SJay Sternberg return result; 257657dacad5SJay Sternberg 257757dacad5SJay Sternberg pci_set_master(pdev); 257857dacad5SJay Sternberg 25794bdf2603SFilippo Sironi if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48) 25804bdf2603SFilippo Sironi dma_address_bits = 48; 25814bdf2603SFilippo Sironi if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits))) 258257dacad5SJay Sternberg goto disable; 258357dacad5SJay Sternberg 25847a67cbeaSChristoph Hellwig if (readl(dev->bar + NVME_REG_CSTS) == -1) { 258557dacad5SJay Sternberg result = -ENODEV; 2586b00a726aSKeith Busch goto disable; 258757dacad5SJay Sternberg } 258857dacad5SJay Sternberg 258957dacad5SJay Sternberg /* 2590a5229050SKeith Busch * Some devices and/or platforms don't advertise or work with INTx 2591a5229050SKeith Busch * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll 2592a5229050SKeith Busch * adjust this later. 259357dacad5SJay Sternberg */ 2594dca51e78SChristoph Hellwig result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); 2595dca51e78SChristoph Hellwig if (result < 0) 2596dca51e78SChristoph Hellwig return result; 259757dacad5SJay Sternberg 259820d0dfe6SSagi Grimberg dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP); 25997a67cbeaSChristoph Hellwig 26007442ddceSJohn Garry dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1, 2601b27c1e68Sweiping zhang io_queue_depth); 2602aa22c8e6SSagi Grimberg dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */ 260320d0dfe6SSagi Grimberg dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap); 26047a67cbeaSChristoph Hellwig dev->dbs = dev->bar + 4096; 26051f390c1fSStephan Günther 26061f390c1fSStephan Günther /* 260766341331SBenjamin Herrenschmidt * Some Apple controllers require a non-standard SQE size. 260866341331SBenjamin Herrenschmidt * Interestingly they also seem to ignore the CC:IOSQES register 260966341331SBenjamin Herrenschmidt * so we don't bother updating it here. 261066341331SBenjamin Herrenschmidt */ 261166341331SBenjamin Herrenschmidt if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES) 261266341331SBenjamin Herrenschmidt dev->io_sqes = 7; 261366341331SBenjamin Herrenschmidt else 2614c1e0cc7eSBenjamin Herrenschmidt dev->io_sqes = NVME_NVM_IOSQES; 26151f390c1fSStephan Günther 26161f390c1fSStephan Günther /* 26171f390c1fSStephan Günther * Temporary fix for the Apple controller found in the MacBook8,1 and 26181f390c1fSStephan Günther * some MacBook7,1 to avoid controller resets and data loss. 26191f390c1fSStephan Günther */ 26201f390c1fSStephan Günther if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) { 26211f390c1fSStephan Günther dev->q_depth = 2; 26229bdcfb10SChristoph Hellwig dev_warn(dev->ctrl.device, "detected Apple NVMe controller, " 26239bdcfb10SChristoph Hellwig "set queue depth=%u to work around controller resets\n", 26241f390c1fSStephan Günther dev->q_depth); 2625d554b5e1SMartin K. Petersen } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG && 2626d554b5e1SMartin K. Petersen (pdev->device == 0xa821 || pdev->device == 0xa822) && 262720d0dfe6SSagi Grimberg NVME_CAP_MQES(dev->ctrl.cap) == 0) { 2628d554b5e1SMartin K. Petersen dev->q_depth = 64; 2629d554b5e1SMartin K. Petersen dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, " 2630d554b5e1SMartin K. Petersen "set queue depth=%u\n", dev->q_depth); 26311f390c1fSStephan Günther } 26321f390c1fSStephan Günther 2633d38e9f04SBenjamin Herrenschmidt /* 2634d38e9f04SBenjamin Herrenschmidt * Controllers with the shared tags quirk need the IO queue to be 2635d38e9f04SBenjamin Herrenschmidt * big enough so that we get 32 tags for the admin queue 2636d38e9f04SBenjamin Herrenschmidt */ 2637d38e9f04SBenjamin Herrenschmidt if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) && 2638d38e9f04SBenjamin Herrenschmidt (dev->q_depth < (NVME_AQ_DEPTH + 2))) { 2639d38e9f04SBenjamin Herrenschmidt dev->q_depth = NVME_AQ_DEPTH + 2; 2640d38e9f04SBenjamin Herrenschmidt dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n", 2641d38e9f04SBenjamin Herrenschmidt dev->q_depth); 2642d38e9f04SBenjamin Herrenschmidt } 2643d38e9f04SBenjamin Herrenschmidt 2644d38e9f04SBenjamin Herrenschmidt 2645f65efd6dSChristoph Hellwig nvme_map_cmb(dev); 2646202021c1SStephen Bates 2647a0a3408eSKeith Busch pci_enable_pcie_error_reporting(pdev); 2648a0a3408eSKeith Busch pci_save_state(pdev); 264957dacad5SJay Sternberg return 0; 265057dacad5SJay Sternberg 265157dacad5SJay Sternberg disable: 265257dacad5SJay Sternberg pci_disable_device(pdev); 265357dacad5SJay Sternberg return result; 265457dacad5SJay Sternberg } 265557dacad5SJay Sternberg 265657dacad5SJay Sternberg static void nvme_dev_unmap(struct nvme_dev *dev) 265757dacad5SJay Sternberg { 2658b00a726aSKeith Busch if (dev->bar) 2659b00a726aSKeith Busch iounmap(dev->bar); 2660a1f447b3SJohannes Thumshirn pci_release_mem_regions(to_pci_dev(dev->dev)); 2661b00a726aSKeith Busch } 2662b00a726aSKeith Busch 2663b00a726aSKeith Busch static void nvme_pci_disable(struct nvme_dev *dev) 2664b00a726aSKeith Busch { 266557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 266657dacad5SJay Sternberg 2667dca51e78SChristoph Hellwig pci_free_irq_vectors(pdev); 266857dacad5SJay Sternberg 2669a0a3408eSKeith Busch if (pci_is_enabled(pdev)) { 2670a0a3408eSKeith Busch pci_disable_pcie_error_reporting(pdev); 267157dacad5SJay Sternberg pci_disable_device(pdev); 267257dacad5SJay Sternberg } 2673a0a3408eSKeith Busch } 267457dacad5SJay Sternberg 2675a5cdb68cSKeith Busch static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown) 267657dacad5SJay Sternberg { 2677e43269e6SKeith Busch bool dead = true, freeze = false; 2678302ad8ccSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 267957dacad5SJay Sternberg 268077bf25eaSKeith Busch mutex_lock(&dev->shutdown_lock); 2681b98235d3SStefan Roese if (pci_device_is_present(pdev) && pci_is_enabled(pdev)) { 2682302ad8ccSKeith Busch u32 csts = readl(dev->bar + NVME_REG_CSTS); 2683302ad8ccSKeith Busch 2684ebef7368SKeith Busch if (dev->ctrl.state == NVME_CTRL_LIVE || 2685e43269e6SKeith Busch dev->ctrl.state == NVME_CTRL_RESETTING) { 2686e43269e6SKeith Busch freeze = true; 2687302ad8ccSKeith Busch nvme_start_freeze(&dev->ctrl); 2688e43269e6SKeith Busch } 2689302ad8ccSKeith Busch dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) || 2690302ad8ccSKeith Busch pdev->error_state != pci_channel_io_normal); 269157dacad5SJay Sternberg } 2692c21377f8SGabriel Krisman Bertazi 2693302ad8ccSKeith Busch /* 2694302ad8ccSKeith Busch * Give the controller a chance to complete all entered requests if 2695302ad8ccSKeith Busch * doing a safe shutdown. 2696302ad8ccSKeith Busch */ 2697e43269e6SKeith Busch if (!dead && shutdown && freeze) 2698302ad8ccSKeith Busch nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT); 269987ad72a5SChristoph Hellwig 27009a915a5bSJianchao Wang nvme_stop_queues(&dev->ctrl); 27019a915a5bSJianchao Wang 270264ee0ac0SKeith Busch if (!dead && dev->ctrl.queue_count > 0) { 27038fae268bSKeith Busch nvme_disable_io_queues(dev); 2704a5cdb68cSKeith Busch nvme_disable_admin_queue(dev, shutdown); 270557dacad5SJay Sternberg } 27068fae268bSKeith Busch nvme_suspend_io_queues(dev); 27078fae268bSKeith Busch nvme_suspend_queue(&dev->queues[0]); 2708b00a726aSKeith Busch nvme_pci_disable(dev); 2709fa46c6fbSKeith Busch nvme_reap_pending_cqes(dev); 271057dacad5SJay Sternberg 2711e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl); 2712e1958e65SMing Lin blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl); 2713622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->tagset); 2714622b8b68SMing Lei blk_mq_tagset_wait_completed_request(&dev->admin_tagset); 2715302ad8ccSKeith Busch 2716302ad8ccSKeith Busch /* 2717302ad8ccSKeith Busch * The driver will not be starting up queues again if shutting down so 2718302ad8ccSKeith Busch * must flush all entered requests to their failed completion to avoid 2719302ad8ccSKeith Busch * deadlocking blk-mq hot-cpu notifier. 2720302ad8ccSKeith Busch */ 2721c8e9e9b7SKeith Busch if (shutdown) { 2722302ad8ccSKeith Busch nvme_start_queues(&dev->ctrl); 2723c8e9e9b7SKeith Busch if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) 27246ca1d902SMing Lei nvme_start_admin_queue(&dev->ctrl); 2725c8e9e9b7SKeith Busch } 272677bf25eaSKeith Busch mutex_unlock(&dev->shutdown_lock); 272757dacad5SJay Sternberg } 272857dacad5SJay Sternberg 2729c1ac9a4bSKeith Busch static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown) 2730c1ac9a4bSKeith Busch { 2731c1ac9a4bSKeith Busch if (!nvme_wait_reset(&dev->ctrl)) 2732c1ac9a4bSKeith Busch return -EBUSY; 2733c1ac9a4bSKeith Busch nvme_dev_disable(dev, shutdown); 2734c1ac9a4bSKeith Busch return 0; 2735c1ac9a4bSKeith Busch } 2736c1ac9a4bSKeith Busch 273757dacad5SJay Sternberg static int nvme_setup_prp_pools(struct nvme_dev *dev) 273857dacad5SJay Sternberg { 273957dacad5SJay Sternberg dev->prp_page_pool = dma_pool_create("prp list page", dev->dev, 2740c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 2741c61b82c7SChristoph Hellwig NVME_CTRL_PAGE_SIZE, 0); 274257dacad5SJay Sternberg if (!dev->prp_page_pool) 274357dacad5SJay Sternberg return -ENOMEM; 274457dacad5SJay Sternberg 274557dacad5SJay Sternberg /* Optimisation for I/Os between 4k and 128k */ 274657dacad5SJay Sternberg dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev, 274757dacad5SJay Sternberg 256, 256, 0); 274857dacad5SJay Sternberg if (!dev->prp_small_pool) { 274957dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275057dacad5SJay Sternberg return -ENOMEM; 275157dacad5SJay Sternberg } 275257dacad5SJay Sternberg return 0; 275357dacad5SJay Sternberg } 275457dacad5SJay Sternberg 275557dacad5SJay Sternberg static void nvme_release_prp_pools(struct nvme_dev *dev) 275657dacad5SJay Sternberg { 275757dacad5SJay Sternberg dma_pool_destroy(dev->prp_page_pool); 275857dacad5SJay Sternberg dma_pool_destroy(dev->prp_small_pool); 275957dacad5SJay Sternberg } 276057dacad5SJay Sternberg 2761770597ecSKeith Busch static void nvme_free_tagset(struct nvme_dev *dev) 2762770597ecSKeith Busch { 2763770597ecSKeith Busch if (dev->tagset.tags) 2764770597ecSKeith Busch blk_mq_free_tag_set(&dev->tagset); 2765770597ecSKeith Busch dev->ctrl.tagset = NULL; 2766770597ecSKeith Busch } 2767770597ecSKeith Busch 27681673f1f0SChristoph Hellwig static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl) 276957dacad5SJay Sternberg { 27701673f1f0SChristoph Hellwig struct nvme_dev *dev = to_nvme_dev(ctrl); 277157dacad5SJay Sternberg 2772f9f38e33SHelen Koike nvme_dbbuf_dma_free(dev); 2773770597ecSKeith Busch nvme_free_tagset(dev); 27741c63dc66SChristoph Hellwig if (dev->ctrl.admin_q) 27751c63dc66SChristoph Hellwig blk_put_queue(dev->ctrl.admin_q); 2776e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2777943e942eSJens Axboe mempool_destroy(dev->iod_mempool); 2778253fd4acSIsrael Rukshin put_device(dev->dev); 2779253fd4acSIsrael Rukshin kfree(dev->queues); 278057dacad5SJay Sternberg kfree(dev); 278157dacad5SJay Sternberg } 278257dacad5SJay Sternberg 27837c1ce408SChaitanya Kulkarni static void nvme_remove_dead_ctrl(struct nvme_dev *dev) 2784f58944e2SKeith Busch { 2785c1ac9a4bSKeith Busch /* 2786c1ac9a4bSKeith Busch * Set state to deleting now to avoid blocking nvme_wait_reset(), which 2787c1ac9a4bSKeith Busch * may be holding this pci_dev's device lock. 2788c1ac9a4bSKeith Busch */ 2789c1ac9a4bSKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 2790d22524a4SChristoph Hellwig nvme_get_ctrl(&dev->ctrl); 279169d9a99cSKeith Busch nvme_dev_disable(dev, false); 27929f9cafc1SJianchao Wang nvme_kill_queues(&dev->ctrl); 279303e0f3a6SMing Lei if (!queue_work(nvme_wq, &dev->remove_work)) 2794f58944e2SKeith Busch nvme_put_ctrl(&dev->ctrl); 2795f58944e2SKeith Busch } 2796f58944e2SKeith Busch 2797fd634f41SChristoph Hellwig static void nvme_reset_work(struct work_struct *work) 279857dacad5SJay Sternberg { 2799d86c4d8eSChristoph Hellwig struct nvme_dev *dev = 2800d86c4d8eSChristoph Hellwig container_of(work, struct nvme_dev, ctrl.reset_work); 2801a98e58e5SScott Bauer bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL); 2802e71afda4SChaitanya Kulkarni int result; 280357dacad5SJay Sternberg 28047764656bSZhihao Cheng if (dev->ctrl.state != NVME_CTRL_RESETTING) { 28057764656bSZhihao Cheng dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n", 28067764656bSZhihao Cheng dev->ctrl.state); 2807e71afda4SChaitanya Kulkarni result = -ENODEV; 2808fd634f41SChristoph Hellwig goto out; 2809e71afda4SChaitanya Kulkarni } 2810fd634f41SChristoph Hellwig 2811fd634f41SChristoph Hellwig /* 2812fd634f41SChristoph Hellwig * If we're called to reset a live controller first shut it down before 2813fd634f41SChristoph Hellwig * moving on. 2814fd634f41SChristoph Hellwig */ 2815b00a726aSKeith Busch if (dev->ctrl.ctrl_config & NVME_CC_ENABLE) 2816a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 2817d6135c3aSKeith Busch nvme_sync_queues(&dev->ctrl); 2818fd634f41SChristoph Hellwig 28195c959d73SKeith Busch mutex_lock(&dev->shutdown_lock); 2820b00a726aSKeith Busch result = nvme_pci_enable(dev); 282157dacad5SJay Sternberg if (result) 28224726bcf3SKeith Busch goto out_unlock; 282357dacad5SJay Sternberg 282401ad0990SSagi Grimberg result = nvme_pci_configure_admin_queue(dev); 282557dacad5SJay Sternberg if (result) 28264726bcf3SKeith Busch goto out_unlock; 282757dacad5SJay Sternberg 282857dacad5SJay Sternberg result = nvme_alloc_admin_tags(dev); 282957dacad5SJay Sternberg if (result) 28304726bcf3SKeith Busch goto out_unlock; 283157dacad5SJay Sternberg 2832943e942eSJens Axboe /* 2833943e942eSJens Axboe * Limit the max command size to prevent iod->sg allocations going 2834943e942eSJens Axboe * over a single page. 2835943e942eSJens Axboe */ 28367637de31SChristoph Hellwig dev->ctrl.max_hw_sectors = min_t(u32, 28377637de31SChristoph Hellwig NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9); 2838943e942eSJens Axboe dev->ctrl.max_segments = NVME_MAX_SEGS; 2839a48bc520SChristoph Hellwig 2840a48bc520SChristoph Hellwig /* 2841a48bc520SChristoph Hellwig * Don't limit the IOMMU merged segment size. 2842a48bc520SChristoph Hellwig */ 2843a48bc520SChristoph Hellwig dma_set_max_seg_size(dev->dev, 0xffffffff); 28443d2d861eSJianxiong Gao dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1); 2845a48bc520SChristoph Hellwig 28465c959d73SKeith Busch mutex_unlock(&dev->shutdown_lock); 28475c959d73SKeith Busch 28485c959d73SKeith Busch /* 28495c959d73SKeith Busch * Introduce CONNECTING state from nvme-fc/rdma transports to mark the 28505c959d73SKeith Busch * initializing procedure here. 28515c959d73SKeith Busch */ 28525c959d73SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) { 28535c959d73SKeith Busch dev_warn(dev->ctrl.device, 28545c959d73SKeith Busch "failed to mark controller CONNECTING\n"); 2855cee6c269SMinwoo Im result = -EBUSY; 28565c959d73SKeith Busch goto out; 28575c959d73SKeith Busch } 2858943e942eSJens Axboe 285995093350SMax Gurtovoy /* 286095093350SMax Gurtovoy * We do not support an SGL for metadata (yet), so we are limited to a 286195093350SMax Gurtovoy * single integrity segment for the separate metadata pointer. 286295093350SMax Gurtovoy */ 286395093350SMax Gurtovoy dev->ctrl.max_integrity_segments = 1; 286495093350SMax Gurtovoy 2865f21c4769SChaitanya Kulkarni result = nvme_init_ctrl_finish(&dev->ctrl); 2866ce4541f4SChristoph Hellwig if (result) 2867f58944e2SKeith Busch goto out; 2868ce4541f4SChristoph Hellwig 2869e286bcfcSScott Bauer if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) { 2870e286bcfcSScott Bauer if (!dev->ctrl.opal_dev) 28714f1244c8SChristoph Hellwig dev->ctrl.opal_dev = 28724f1244c8SChristoph Hellwig init_opal_dev(&dev->ctrl, &nvme_sec_submit); 2873e286bcfcSScott Bauer else if (was_suspend) 28744f1244c8SChristoph Hellwig opal_unlock_from_suspend(dev->ctrl.opal_dev); 2875e286bcfcSScott Bauer } else { 2876e286bcfcSScott Bauer free_opal_dev(dev->ctrl.opal_dev); 2877e286bcfcSScott Bauer dev->ctrl.opal_dev = NULL; 2878e286bcfcSScott Bauer } 2879a98e58e5SScott Bauer 2880f9f38e33SHelen Koike if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) { 2881f9f38e33SHelen Koike result = nvme_dbbuf_dma_alloc(dev); 2882f9f38e33SHelen Koike if (result) 2883f9f38e33SHelen Koike dev_warn(dev->dev, 2884f9f38e33SHelen Koike "unable to allocate dma for dbbuf\n"); 2885f9f38e33SHelen Koike } 2886f9f38e33SHelen Koike 28879620cfbaSChristoph Hellwig if (dev->ctrl.hmpre) { 28889620cfbaSChristoph Hellwig result = nvme_setup_host_mem(dev); 28899620cfbaSChristoph Hellwig if (result < 0) 28909620cfbaSChristoph Hellwig goto out; 28919620cfbaSChristoph Hellwig } 289287ad72a5SChristoph Hellwig 289357dacad5SJay Sternberg result = nvme_setup_io_queues(dev); 289457dacad5SJay Sternberg if (result) 2895f58944e2SKeith Busch goto out; 289657dacad5SJay Sternberg 289721f033f7SKeith Busch /* 289857dacad5SJay Sternberg * Keep the controller around but remove all namespaces if we don't have 289957dacad5SJay Sternberg * any working I/O queue. 290057dacad5SJay Sternberg */ 290157dacad5SJay Sternberg if (dev->online_queues < 2) { 29021b3c47c1SSagi Grimberg dev_warn(dev->ctrl.device, "IO queues not created\n"); 29033b24774eSKeith Busch nvme_kill_queues(&dev->ctrl); 29045bae7f73SChristoph Hellwig nvme_remove_namespaces(&dev->ctrl); 2905770597ecSKeith Busch nvme_free_tagset(dev); 290657dacad5SJay Sternberg } else { 290725646264SKeith Busch nvme_start_queues(&dev->ctrl); 2908302ad8ccSKeith Busch nvme_wait_freeze(&dev->ctrl); 29095d02a5c1SKeith Busch nvme_dev_add(dev); 2910302ad8ccSKeith Busch nvme_unfreeze(&dev->ctrl); 291157dacad5SJay Sternberg } 291257dacad5SJay Sternberg 29132b1b7e78SJianchao Wang /* 29142b1b7e78SJianchao Wang * If only admin queue live, keep it to do further investigation or 29152b1b7e78SJianchao Wang * recovery. 29162b1b7e78SJianchao Wang */ 29175d02a5c1SKeith Busch if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) { 29182b1b7e78SJianchao Wang dev_warn(dev->ctrl.device, 29195d02a5c1SKeith Busch "failed to mark controller live state\n"); 2920e71afda4SChaitanya Kulkarni result = -ENODEV; 2921bb8d261eSChristoph Hellwig goto out; 2922bb8d261eSChristoph Hellwig } 292392911a55SChristoph Hellwig 29240521905eSKeith Busch if (!dev->attrs_added && !sysfs_create_group(&dev->ctrl.device->kobj, 29250521905eSKeith Busch &nvme_pci_attr_group)) 29260521905eSKeith Busch dev->attrs_added = true; 29270521905eSKeith Busch 2928d09f2b45SSagi Grimberg nvme_start_ctrl(&dev->ctrl); 292957dacad5SJay Sternberg return; 293057dacad5SJay Sternberg 29314726bcf3SKeith Busch out_unlock: 29324726bcf3SKeith Busch mutex_unlock(&dev->shutdown_lock); 293357dacad5SJay Sternberg out: 29347c1ce408SChaitanya Kulkarni if (result) 29357c1ce408SChaitanya Kulkarni dev_warn(dev->ctrl.device, 29367c1ce408SChaitanya Kulkarni "Removing after probe failure status: %d\n", result); 29377c1ce408SChaitanya Kulkarni nvme_remove_dead_ctrl(dev); 293857dacad5SJay Sternberg } 293957dacad5SJay Sternberg 29405c8809e6SChristoph Hellwig static void nvme_remove_dead_ctrl_work(struct work_struct *work) 294157dacad5SJay Sternberg { 29425c8809e6SChristoph Hellwig struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work); 294357dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev->dev); 294457dacad5SJay Sternberg 294557dacad5SJay Sternberg if (pci_get_drvdata(pdev)) 2946921920abSKeith Busch device_release_driver(&pdev->dev); 29471673f1f0SChristoph Hellwig nvme_put_ctrl(&dev->ctrl); 294857dacad5SJay Sternberg } 294957dacad5SJay Sternberg 29501c63dc66SChristoph Hellwig static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val) 295157dacad5SJay Sternberg { 29521c63dc66SChristoph Hellwig *val = readl(to_nvme_dev(ctrl)->bar + off); 29531c63dc66SChristoph Hellwig return 0; 295457dacad5SJay Sternberg } 29551c63dc66SChristoph Hellwig 29565fd4ce1bSChristoph Hellwig static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val) 29575fd4ce1bSChristoph Hellwig { 29585fd4ce1bSChristoph Hellwig writel(val, to_nvme_dev(ctrl)->bar + off); 29595fd4ce1bSChristoph Hellwig return 0; 29605fd4ce1bSChristoph Hellwig } 29615fd4ce1bSChristoph Hellwig 29627fd8930fSChristoph Hellwig static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val) 29637fd8930fSChristoph Hellwig { 29643a8ecc93SArd Biesheuvel *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off); 29657fd8930fSChristoph Hellwig return 0; 29667fd8930fSChristoph Hellwig } 29677fd8930fSChristoph Hellwig 296897c12223SKeith Busch static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size) 296997c12223SKeith Busch { 297097c12223SKeith Busch struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev); 297197c12223SKeith Busch 29722db24e4aSMax Gurtovoy return snprintf(buf, size, "%s\n", dev_name(&pdev->dev)); 297397c12223SKeith Busch } 297497c12223SKeith Busch 29751c63dc66SChristoph Hellwig static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = { 29761a353d85SMing Lin .name = "pcie", 2977e439bb12SSagi Grimberg .module = THIS_MODULE, 2978e0596ab2SLogan Gunthorpe .flags = NVME_F_METADATA_SUPPORTED | 2979e0596ab2SLogan Gunthorpe NVME_F_PCI_P2PDMA, 29801c63dc66SChristoph Hellwig .reg_read32 = nvme_pci_reg_read32, 29815fd4ce1bSChristoph Hellwig .reg_write32 = nvme_pci_reg_write32, 29827fd8930fSChristoph Hellwig .reg_read64 = nvme_pci_reg_read64, 29831673f1f0SChristoph Hellwig .free_ctrl = nvme_pci_free_ctrl, 2984f866fc42SChristoph Hellwig .submit_async_event = nvme_pci_submit_async_event, 298597c12223SKeith Busch .get_address = nvme_pci_get_address, 29861c63dc66SChristoph Hellwig }; 298757dacad5SJay Sternberg 2988b00a726aSKeith Busch static int nvme_dev_map(struct nvme_dev *dev) 2989b00a726aSKeith Busch { 2990b00a726aSKeith Busch struct pci_dev *pdev = to_pci_dev(dev->dev); 2991b00a726aSKeith Busch 2992a1f447b3SJohannes Thumshirn if (pci_request_mem_regions(pdev, "nvme")) 2993b00a726aSKeith Busch return -ENODEV; 2994b00a726aSKeith Busch 299597f6ef64SXu Yu if (nvme_remap_bar(dev, NVME_REG_DBS + 4096)) 2996b00a726aSKeith Busch goto release; 2997b00a726aSKeith Busch 2998b00a726aSKeith Busch return 0; 2999b00a726aSKeith Busch release: 3000a1f447b3SJohannes Thumshirn pci_release_mem_regions(pdev); 3001b00a726aSKeith Busch return -ENODEV; 3002b00a726aSKeith Busch } 3003b00a726aSKeith Busch 30048427bbc2SKai-Heng Feng static unsigned long check_vendor_combination_bug(struct pci_dev *pdev) 3005ff5350a8SAndy Lutomirski { 3006ff5350a8SAndy Lutomirski if (pdev->vendor == 0x144d && pdev->device == 0xa802) { 3007ff5350a8SAndy Lutomirski /* 3008ff5350a8SAndy Lutomirski * Several Samsung devices seem to drop off the PCIe bus 3009ff5350a8SAndy Lutomirski * randomly when APST is on and uses the deepest sleep state. 3010ff5350a8SAndy Lutomirski * This has been observed on a Samsung "SM951 NVMe SAMSUNG 3011ff5350a8SAndy Lutomirski * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD 3012ff5350a8SAndy Lutomirski * 950 PRO 256GB", but it seems to be restricted to two Dell 3013ff5350a8SAndy Lutomirski * laptops. 3014ff5350a8SAndy Lutomirski */ 3015ff5350a8SAndy Lutomirski if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") && 3016ff5350a8SAndy Lutomirski (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") || 3017ff5350a8SAndy Lutomirski dmi_match(DMI_PRODUCT_NAME, "Precision 5510"))) 3018ff5350a8SAndy Lutomirski return NVME_QUIRK_NO_DEEPEST_PS; 30198427bbc2SKai-Heng Feng } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) { 30208427bbc2SKai-Heng Feng /* 30218427bbc2SKai-Heng Feng * Samsung SSD 960 EVO drops off the PCIe bus after system 3022467c77d4SJarosław Janik * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as 3023467c77d4SJarosław Janik * within few minutes after bootup on a Coffee Lake board - 3024467c77d4SJarosław Janik * ASUS PRIME Z370-A 30258427bbc2SKai-Heng Feng */ 30268427bbc2SKai-Heng Feng if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") && 3027467c77d4SJarosław Janik (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") || 3028467c77d4SJarosław Janik dmi_match(DMI_BOARD_NAME, "PRIME Z370-A"))) 30298427bbc2SKai-Heng Feng return NVME_QUIRK_NO_APST; 30301fae37acSShyjumon N } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 || 30311fae37acSShyjumon N pdev->device == 0xa808 || pdev->device == 0xa809)) || 30321fae37acSShyjumon N (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) { 30331fae37acSShyjumon N /* 30341fae37acSShyjumon N * Forcing to use host managed nvme power settings for 30351fae37acSShyjumon N * lowest idle power with quick resume latency on 30361fae37acSShyjumon N * Samsung and Toshiba SSDs based on suspend behavior 30371fae37acSShyjumon N * on Coffee Lake board for LENOVO C640 30381fae37acSShyjumon N */ 30391fae37acSShyjumon N if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) && 30401fae37acSShyjumon N dmi_match(DMI_BOARD_NAME, "LNVNB161216")) 30411fae37acSShyjumon N return NVME_QUIRK_SIMPLE_SUSPEND; 3042ff5350a8SAndy Lutomirski } 3043ff5350a8SAndy Lutomirski 3044ff5350a8SAndy Lutomirski return 0; 3045ff5350a8SAndy Lutomirski } 3046ff5350a8SAndy Lutomirski 304718119775SKeith Busch static void nvme_async_probe(void *data, async_cookie_t cookie) 304818119775SKeith Busch { 304918119775SKeith Busch struct nvme_dev *dev = data; 305080f513b5SKeith Busch 3051bd46a906SKeith Busch flush_work(&dev->ctrl.reset_work); 305218119775SKeith Busch flush_work(&dev->ctrl.scan_work); 305380f513b5SKeith Busch nvme_put_ctrl(&dev->ctrl); 305418119775SKeith Busch } 305518119775SKeith Busch 305657dacad5SJay Sternberg static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id) 305757dacad5SJay Sternberg { 305857dacad5SJay Sternberg int node, result = -ENOMEM; 305957dacad5SJay Sternberg struct nvme_dev *dev; 3060ff5350a8SAndy Lutomirski unsigned long quirks = id->driver_data; 3061943e942eSJens Axboe size_t alloc_size; 306257dacad5SJay Sternberg 306357dacad5SJay Sternberg node = dev_to_node(&pdev->dev); 306457dacad5SJay Sternberg if (node == NUMA_NO_NODE) 30652fa84351SMasayoshi Mizuma set_dev_node(&pdev->dev, first_memory_node); 306657dacad5SJay Sternberg 306757dacad5SJay Sternberg dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node); 306857dacad5SJay Sternberg if (!dev) 306957dacad5SJay Sternberg return -ENOMEM; 3070147b27e4SSagi Grimberg 30712a5bcfddSWeiping Zhang dev->nr_write_queues = write_queues; 30722a5bcfddSWeiping Zhang dev->nr_poll_queues = poll_queues; 30732a5bcfddSWeiping Zhang dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1; 30742a5bcfddSWeiping Zhang dev->queues = kcalloc_node(dev->nr_allocated_queues, 30752a5bcfddSWeiping Zhang sizeof(struct nvme_queue), GFP_KERNEL, node); 307657dacad5SJay Sternberg if (!dev->queues) 307757dacad5SJay Sternberg goto free; 307857dacad5SJay Sternberg 307957dacad5SJay Sternberg dev->dev = get_device(&pdev->dev); 308057dacad5SJay Sternberg pci_set_drvdata(pdev, dev); 308157dacad5SJay Sternberg 3082b00a726aSKeith Busch result = nvme_dev_map(dev); 3083b00a726aSKeith Busch if (result) 3084b00c9b7aSChristophe JAILLET goto put_pci; 3085b00a726aSKeith Busch 3086d86c4d8eSChristoph Hellwig INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work); 30875c8809e6SChristoph Hellwig INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work); 308877bf25eaSKeith Busch mutex_init(&dev->shutdown_lock); 3089f3ca80fcSChristoph Hellwig 3090f3ca80fcSChristoph Hellwig result = nvme_setup_prp_pools(dev); 3091f3ca80fcSChristoph Hellwig if (result) 3092b00c9b7aSChristophe JAILLET goto unmap; 3093f3ca80fcSChristoph Hellwig 30948427bbc2SKai-Heng Feng quirks |= check_vendor_combination_bug(pdev); 3095ff5350a8SAndy Lutomirski 30962744d7a0SMario Limonciello if (!noacpi && acpi_storage_d3(&pdev->dev)) { 3097df4f9bc4SDavid E. Box /* 3098df4f9bc4SDavid E. Box * Some systems use a bios work around to ask for D3 on 3099df4f9bc4SDavid E. Box * platforms that support kernel managed suspend. 3100df4f9bc4SDavid E. Box */ 3101df4f9bc4SDavid E. Box dev_info(&pdev->dev, 3102df4f9bc4SDavid E. Box "platform quirk: setting simple suspend\n"); 3103df4f9bc4SDavid E. Box quirks |= NVME_QUIRK_SIMPLE_SUSPEND; 3104df4f9bc4SDavid E. Box } 3105df4f9bc4SDavid E. Box 3106943e942eSJens Axboe /* 3107943e942eSJens Axboe * Double check that our mempool alloc size will cover the biggest 3108943e942eSJens Axboe * command we support. 3109943e942eSJens Axboe */ 3110b13c6393SChaitanya Kulkarni alloc_size = nvme_pci_iod_alloc_size(); 3111943e942eSJens Axboe WARN_ON_ONCE(alloc_size > PAGE_SIZE); 3112943e942eSJens Axboe 3113943e942eSJens Axboe dev->iod_mempool = mempool_create_node(1, mempool_kmalloc, 3114943e942eSJens Axboe mempool_kfree, 3115943e942eSJens Axboe (void *) alloc_size, 3116943e942eSJens Axboe GFP_KERNEL, node); 3117943e942eSJens Axboe if (!dev->iod_mempool) { 3118943e942eSJens Axboe result = -ENOMEM; 3119943e942eSJens Axboe goto release_pools; 3120943e942eSJens Axboe } 3121943e942eSJens Axboe 3122b6e44b4cSKeith Busch result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops, 3123b6e44b4cSKeith Busch quirks); 3124b6e44b4cSKeith Busch if (result) 3125b6e44b4cSKeith Busch goto release_mempool; 3126b6e44b4cSKeith Busch 31271b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev)); 31281b3c47c1SSagi Grimberg 3129bd46a906SKeith Busch nvme_reset_ctrl(&dev->ctrl); 313018119775SKeith Busch async_schedule(nvme_async_probe, dev); 31314caff8fcSSagi Grimberg 313257dacad5SJay Sternberg return 0; 313357dacad5SJay Sternberg 3134b6e44b4cSKeith Busch release_mempool: 3135b6e44b4cSKeith Busch mempool_destroy(dev->iod_mempool); 313657dacad5SJay Sternberg release_pools: 313757dacad5SJay Sternberg nvme_release_prp_pools(dev); 3138b00c9b7aSChristophe JAILLET unmap: 3139b00c9b7aSChristophe JAILLET nvme_dev_unmap(dev); 314057dacad5SJay Sternberg put_pci: 314157dacad5SJay Sternberg put_device(dev->dev); 314257dacad5SJay Sternberg free: 314357dacad5SJay Sternberg kfree(dev->queues); 314457dacad5SJay Sternberg kfree(dev); 314557dacad5SJay Sternberg return result; 314657dacad5SJay Sternberg } 314757dacad5SJay Sternberg 3148775755edSChristoph Hellwig static void nvme_reset_prepare(struct pci_dev *pdev) 314957dacad5SJay Sternberg { 315057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 3151c1ac9a4bSKeith Busch 3152c1ac9a4bSKeith Busch /* 3153c1ac9a4bSKeith Busch * We don't need to check the return value from waiting for the reset 3154c1ac9a4bSKeith Busch * state as pci_dev device lock is held, making it impossible to race 3155c1ac9a4bSKeith Busch * with ->remove(). 3156c1ac9a4bSKeith Busch */ 3157c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, false); 3158c1ac9a4bSKeith Busch nvme_sync_queues(&dev->ctrl); 3159775755edSChristoph Hellwig } 316057dacad5SJay Sternberg 3161775755edSChristoph Hellwig static void nvme_reset_done(struct pci_dev *pdev) 3162775755edSChristoph Hellwig { 3163f263fbb8SLinus Torvalds struct nvme_dev *dev = pci_get_drvdata(pdev); 3164c1ac9a4bSKeith Busch 3165c1ac9a4bSKeith Busch if (!nvme_try_sched_reset(&dev->ctrl)) 3166c1ac9a4bSKeith Busch flush_work(&dev->ctrl.reset_work); 316757dacad5SJay Sternberg } 316857dacad5SJay Sternberg 316957dacad5SJay Sternberg static void nvme_shutdown(struct pci_dev *pdev) 317057dacad5SJay Sternberg { 317157dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 31724e523547SBaolin Wang 3173c1ac9a4bSKeith Busch nvme_disable_prepare_reset(dev, true); 317457dacad5SJay Sternberg } 317557dacad5SJay Sternberg 31760521905eSKeith Busch static void nvme_remove_attrs(struct nvme_dev *dev) 31770521905eSKeith Busch { 31780521905eSKeith Busch if (dev->attrs_added) 31790521905eSKeith Busch sysfs_remove_group(&dev->ctrl.device->kobj, 31800521905eSKeith Busch &nvme_pci_attr_group); 31810521905eSKeith Busch } 31820521905eSKeith Busch 3183f58944e2SKeith Busch /* 3184f58944e2SKeith Busch * The driver's remove may be called on a device in a partially initialized 3185f58944e2SKeith Busch * state. This function must not have any dependencies on the device state in 3186f58944e2SKeith Busch * order to proceed. 3187f58944e2SKeith Busch */ 318857dacad5SJay Sternberg static void nvme_remove(struct pci_dev *pdev) 318957dacad5SJay Sternberg { 319057dacad5SJay Sternberg struct nvme_dev *dev = pci_get_drvdata(pdev); 319157dacad5SJay Sternberg 3192bb8d261eSChristoph Hellwig nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING); 319357dacad5SJay Sternberg pci_set_drvdata(pdev, NULL); 31940ff9d4e1SKeith Busch 31956db28edaSKeith Busch if (!pci_device_is_present(pdev)) { 31960ff9d4e1SKeith Busch nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD); 31971d39e692SKeith Busch nvme_dev_disable(dev, true); 31986db28edaSKeith Busch } 31990ff9d4e1SKeith Busch 3200d86c4d8eSChristoph Hellwig flush_work(&dev->ctrl.reset_work); 3201d09f2b45SSagi Grimberg nvme_stop_ctrl(&dev->ctrl); 3202d09f2b45SSagi Grimberg nvme_remove_namespaces(&dev->ctrl); 3203a5cdb68cSKeith Busch nvme_dev_disable(dev, true); 32040521905eSKeith Busch nvme_remove_attrs(dev); 320587ad72a5SChristoph Hellwig nvme_free_host_mem(dev); 320657dacad5SJay Sternberg nvme_dev_remove_admin(dev); 320757dacad5SJay Sternberg nvme_free_queues(dev, 0); 320857dacad5SJay Sternberg nvme_release_prp_pools(dev); 3209b00a726aSKeith Busch nvme_dev_unmap(dev); 3210726612b6SIsrael Rukshin nvme_uninit_ctrl(&dev->ctrl); 321157dacad5SJay Sternberg } 321257dacad5SJay Sternberg 321357dacad5SJay Sternberg #ifdef CONFIG_PM_SLEEP 3214d916b1beSKeith Busch static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps) 3215d916b1beSKeith Busch { 3216d916b1beSKeith Busch return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps); 3217d916b1beSKeith Busch } 3218d916b1beSKeith Busch 3219d916b1beSKeith Busch static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps) 3220d916b1beSKeith Busch { 3221d916b1beSKeith Busch return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL); 3222d916b1beSKeith Busch } 3223d916b1beSKeith Busch 3224d916b1beSKeith Busch static int nvme_resume(struct device *dev) 3225d916b1beSKeith Busch { 3226d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 3227d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3228d916b1beSKeith Busch 32294eaefe8cSRafael J. Wysocki if (ndev->last_ps == U32_MAX || 3230d916b1beSKeith Busch nvme_set_power_state(ctrl, ndev->last_ps) != 0) 3231e5ad96f3SKeith Busch goto reset; 3232e5ad96f3SKeith Busch if (ctrl->hmpre && nvme_setup_host_mem(ndev)) 3233e5ad96f3SKeith Busch goto reset; 3234e5ad96f3SKeith Busch 3235d916b1beSKeith Busch return 0; 3236e5ad96f3SKeith Busch reset: 3237e5ad96f3SKeith Busch return nvme_try_sched_reset(ctrl); 3238d916b1beSKeith Busch } 3239d916b1beSKeith Busch 324057dacad5SJay Sternberg static int nvme_suspend(struct device *dev) 324157dacad5SJay Sternberg { 324257dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 324357dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 3244d916b1beSKeith Busch struct nvme_ctrl *ctrl = &ndev->ctrl; 3245d916b1beSKeith Busch int ret = -EBUSY; 3246d916b1beSKeith Busch 32474eaefe8cSRafael J. Wysocki ndev->last_ps = U32_MAX; 32484eaefe8cSRafael J. Wysocki 3249d916b1beSKeith Busch /* 3250d916b1beSKeith Busch * The platform does not remove power for a kernel managed suspend so 3251d916b1beSKeith Busch * use host managed nvme power settings for lowest idle power if 3252d916b1beSKeith Busch * possible. This should have quicker resume latency than a full device 3253d916b1beSKeith Busch * shutdown. But if the firmware is involved after the suspend or the 3254d916b1beSKeith Busch * device does not support any non-default power states, shut down the 3255d916b1beSKeith Busch * device fully. 32564eaefe8cSRafael J. Wysocki * 32574eaefe8cSRafael J. Wysocki * If ASPM is not enabled for the device, shut down the device and allow 32584eaefe8cSRafael J. Wysocki * the PCI bus layer to put it into D3 in order to take the PCIe link 32594eaefe8cSRafael J. Wysocki * down, so as to allow the platform to achieve its minimum low-power 32604eaefe8cSRafael J. Wysocki * state (which may not be possible if the link is up). 3261d916b1beSKeith Busch */ 32624eaefe8cSRafael J. Wysocki if (pm_suspend_via_firmware() || !ctrl->npss || 3263cb32de1bSMario Limonciello !pcie_aspm_enabled(pdev) || 3264c1ac9a4bSKeith Busch (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND)) 3265c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 3266d916b1beSKeith Busch 3267d916b1beSKeith Busch nvme_start_freeze(ctrl); 3268d916b1beSKeith Busch nvme_wait_freeze(ctrl); 3269d916b1beSKeith Busch nvme_sync_queues(ctrl); 3270d916b1beSKeith Busch 32715d02a5c1SKeith Busch if (ctrl->state != NVME_CTRL_LIVE) 3272d916b1beSKeith Busch goto unfreeze; 3273d916b1beSKeith Busch 3274e5ad96f3SKeith Busch /* 3275e5ad96f3SKeith Busch * Host memory access may not be successful in a system suspend state, 3276e5ad96f3SKeith Busch * but the specification allows the controller to access memory in a 3277e5ad96f3SKeith Busch * non-operational power state. 3278e5ad96f3SKeith Busch */ 3279e5ad96f3SKeith Busch if (ndev->hmb) { 3280e5ad96f3SKeith Busch ret = nvme_set_host_mem(ndev, 0); 3281e5ad96f3SKeith Busch if (ret < 0) 3282e5ad96f3SKeith Busch goto unfreeze; 3283e5ad96f3SKeith Busch } 3284e5ad96f3SKeith Busch 3285d916b1beSKeith Busch ret = nvme_get_power_state(ctrl, &ndev->last_ps); 3286d916b1beSKeith Busch if (ret < 0) 3287d916b1beSKeith Busch goto unfreeze; 3288d916b1beSKeith Busch 32897cbb5c6fSMario Limonciello /* 32907cbb5c6fSMario Limonciello * A saved state prevents pci pm from generically controlling the 32917cbb5c6fSMario Limonciello * device's power. If we're using protocol specific settings, we don't 32927cbb5c6fSMario Limonciello * want pci interfering. 32937cbb5c6fSMario Limonciello */ 32947cbb5c6fSMario Limonciello pci_save_state(pdev); 32957cbb5c6fSMario Limonciello 3296d916b1beSKeith Busch ret = nvme_set_power_state(ctrl, ctrl->npss); 3297d916b1beSKeith Busch if (ret < 0) 3298d916b1beSKeith Busch goto unfreeze; 3299d916b1beSKeith Busch 3300d916b1beSKeith Busch if (ret) { 33017cbb5c6fSMario Limonciello /* discard the saved state */ 33027cbb5c6fSMario Limonciello pci_load_saved_state(pdev, NULL); 33037cbb5c6fSMario Limonciello 3304d916b1beSKeith Busch /* 3305d916b1beSKeith Busch * Clearing npss forces a controller reset on resume. The 330605d3046fSGeert Uytterhoeven * correct value will be rediscovered then. 3307d916b1beSKeith Busch */ 3308c1ac9a4bSKeith Busch ret = nvme_disable_prepare_reset(ndev, true); 3309d916b1beSKeith Busch ctrl->npss = 0; 3310d916b1beSKeith Busch } 3311d916b1beSKeith Busch unfreeze: 3312d916b1beSKeith Busch nvme_unfreeze(ctrl); 3313d916b1beSKeith Busch return ret; 3314d916b1beSKeith Busch } 3315d916b1beSKeith Busch 3316d916b1beSKeith Busch static int nvme_simple_suspend(struct device *dev) 3317d916b1beSKeith Busch { 3318d916b1beSKeith Busch struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev)); 33194e523547SBaolin Wang 3320c1ac9a4bSKeith Busch return nvme_disable_prepare_reset(ndev, true); 332157dacad5SJay Sternberg } 332257dacad5SJay Sternberg 3323d916b1beSKeith Busch static int nvme_simple_resume(struct device *dev) 332457dacad5SJay Sternberg { 332557dacad5SJay Sternberg struct pci_dev *pdev = to_pci_dev(dev); 332657dacad5SJay Sternberg struct nvme_dev *ndev = pci_get_drvdata(pdev); 332757dacad5SJay Sternberg 3328c1ac9a4bSKeith Busch return nvme_try_sched_reset(&ndev->ctrl); 332957dacad5SJay Sternberg } 333057dacad5SJay Sternberg 333121774222SYueHaibing static const struct dev_pm_ops nvme_dev_pm_ops = { 3332d916b1beSKeith Busch .suspend = nvme_suspend, 3333d916b1beSKeith Busch .resume = nvme_resume, 3334d916b1beSKeith Busch .freeze = nvme_simple_suspend, 3335d916b1beSKeith Busch .thaw = nvme_simple_resume, 3336d916b1beSKeith Busch .poweroff = nvme_simple_suspend, 3337d916b1beSKeith Busch .restore = nvme_simple_resume, 3338d916b1beSKeith Busch }; 3339d916b1beSKeith Busch #endif /* CONFIG_PM_SLEEP */ 334057dacad5SJay Sternberg 3341a0a3408eSKeith Busch static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev, 3342a0a3408eSKeith Busch pci_channel_state_t state) 3343a0a3408eSKeith Busch { 3344a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3345a0a3408eSKeith Busch 3346a0a3408eSKeith Busch /* 3347a0a3408eSKeith Busch * A frozen channel requires a reset. When detected, this method will 3348a0a3408eSKeith Busch * shutdown the controller to quiesce. The controller will be restarted 3349a0a3408eSKeith Busch * after the slot reset through driver's slot_reset callback. 3350a0a3408eSKeith Busch */ 3351a0a3408eSKeith Busch switch (state) { 3352a0a3408eSKeith Busch case pci_channel_io_normal: 3353a0a3408eSKeith Busch return PCI_ERS_RESULT_CAN_RECOVER; 3354a0a3408eSKeith Busch case pci_channel_io_frozen: 3355d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3356d011fb31SKeith Busch "frozen state error detected, reset controller\n"); 3357a5cdb68cSKeith Busch nvme_dev_disable(dev, false); 3358a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3359a0a3408eSKeith Busch case pci_channel_io_perm_failure: 3360d011fb31SKeith Busch dev_warn(dev->ctrl.device, 3361d011fb31SKeith Busch "failure state error detected, request disconnect\n"); 3362a0a3408eSKeith Busch return PCI_ERS_RESULT_DISCONNECT; 3363a0a3408eSKeith Busch } 3364a0a3408eSKeith Busch return PCI_ERS_RESULT_NEED_RESET; 3365a0a3408eSKeith Busch } 3366a0a3408eSKeith Busch 3367a0a3408eSKeith Busch static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev) 3368a0a3408eSKeith Busch { 3369a0a3408eSKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 3370a0a3408eSKeith Busch 33711b3c47c1SSagi Grimberg dev_info(dev->ctrl.device, "restart after slot reset\n"); 3372a0a3408eSKeith Busch pci_restore_state(pdev); 3373d86c4d8eSChristoph Hellwig nvme_reset_ctrl(&dev->ctrl); 3374a0a3408eSKeith Busch return PCI_ERS_RESULT_RECOVERED; 3375a0a3408eSKeith Busch } 3376a0a3408eSKeith Busch 3377a0a3408eSKeith Busch static void nvme_error_resume(struct pci_dev *pdev) 3378a0a3408eSKeith Busch { 337972cd4cc2SKeith Busch struct nvme_dev *dev = pci_get_drvdata(pdev); 338072cd4cc2SKeith Busch 338172cd4cc2SKeith Busch flush_work(&dev->ctrl.reset_work); 3382a0a3408eSKeith Busch } 3383a0a3408eSKeith Busch 338457dacad5SJay Sternberg static const struct pci_error_handlers nvme_err_handler = { 338557dacad5SJay Sternberg .error_detected = nvme_error_detected, 338657dacad5SJay Sternberg .slot_reset = nvme_slot_reset, 338757dacad5SJay Sternberg .resume = nvme_error_resume, 3388775755edSChristoph Hellwig .reset_prepare = nvme_reset_prepare, 3389775755edSChristoph Hellwig .reset_done = nvme_reset_done, 339057dacad5SJay Sternberg }; 339157dacad5SJay Sternberg 339257dacad5SJay Sternberg static const struct pci_device_id nvme_id_table[] = { 3393972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0953), /* Intel 750/P3500/P3600/P3700 */ 339408095e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3395e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3396972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a53), /* Intel P3520 */ 339799466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 3398e850fd16SChristoph Hellwig NVME_QUIRK_DEALLOCATE_ZEROES, }, 3399972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a54), /* Intel P4500/P4600 */ 340099466e70SKeith Busch .driver_data = NVME_QUIRK_STRIPE_SIZE | 340125e58af4SWu Zheng NVME_QUIRK_DEALLOCATE_ZEROES | 340225e58af4SWu Zheng NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3403972b13e2SDavid Fugate { PCI_VDEVICE(INTEL, 0x0a55), /* Dell Express Flash P4600 */ 3404f99cb7afSDavid Wayne Fugate .driver_data = NVME_QUIRK_STRIPE_SIZE | 3405f99cb7afSDavid Wayne Fugate NVME_QUIRK_DEALLOCATE_ZEROES, }, 340650af47d0SAndy Lutomirski { PCI_VDEVICE(INTEL, 0xf1a5), /* Intel 600P/P3100 */ 34079abd68efSJens Axboe .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 34086c6aa2f2SAkinobu Mita NVME_QUIRK_MEDIUM_PRIO_SQ | 3409ce4cc313SDavid Milburn NVME_QUIRK_NO_TEMP_THRESH_CHANGE | 3410ce4cc313SDavid Milburn NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 34116299358dSJames Dingwall { PCI_VDEVICE(INTEL, 0xf1a6), /* Intel 760p/Pro 7600p */ 34126299358dSJames Dingwall .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3413540c801cSKeith Busch { PCI_VDEVICE(INTEL, 0x5845), /* Qemu emulated controller */ 34147b210e4eSChristoph Hellwig .driver_data = NVME_QUIRK_IDENTIFY_CNS | 341566dd346bSChristoph Hellwig NVME_QUIRK_DISABLE_WRITE_ZEROES | 341666dd346bSChristoph Hellwig NVME_QUIRK_BOGUS_NID, }, 341766dd346bSChristoph Hellwig { PCI_VDEVICE(REDHAT, 0x0010), /* Qemu emulated controller */ 341866dd346bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34195bedd3afSChristoph Hellwig { PCI_DEVICE(0x126f, 0x2263), /* Silicon Motion unidentified */ 34205bedd3afSChristoph Hellwig .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, }, 34210302ae60SMicah Parrish { PCI_DEVICE(0x1bb1, 0x0100), /* Seagate Nytro Flash Storage */ 34225e112d3fSJulian Einwag .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 34235e112d3fSJulian Einwag NVME_QUIRK_NO_NS_DESC_LIST, }, 342454adc010SGuilherme G. Piccoli { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */ 342554adc010SGuilherme G. Piccoli .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 34268c97eeccSJeff Lien { PCI_DEVICE(0x1c58, 0x0023), /* WDC SN200 adapter */ 34278c97eeccSJeff Lien .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3428015282c9SWenbo Wang { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */ 3429015282c9SWenbo Wang .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3430d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa821), /* Samsung PM1725 */ 3431d554b5e1SMartin K. Petersen .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, }, 3432d554b5e1SMartin K. Petersen { PCI_DEVICE(0x144d, 0xa822), /* Samsung PM1725a */ 34337ee5c78cSGopal Tiwari .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY | 3434abbb5f59SDmitry Monakhov NVME_QUIRK_DISABLE_WRITE_ZEROES| 34357ee5c78cSGopal Tiwari NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3436c9e95c39SClaus Stovgaard { PCI_DEVICE(0x1987, 0x5016), /* Phison E16 */ 3437c9e95c39SClaus Stovgaard .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34386e6a6828SPascal Terjan { PCI_DEVICE(0x1b4b, 0x1092), /* Lexar 256 GB SSD */ 34396e6a6828SPascal Terjan .driver_data = NVME_QUIRK_NO_NS_DESC_LIST | 34406e6a6828SPascal Terjan NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 344108b903b5SMisha Nasledov { PCI_DEVICE(0x10ec, 0x5762), /* ADATA SX6000LNP */ 344208b903b5SMisha Nasledov .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 3443f03e42c6SGabriel Craciunescu { PCI_DEVICE(0x1cc1, 0x8201), /* ADATA SX8200PNP 512GB */ 3444f03e42c6SGabriel Craciunescu .driver_data = NVME_QUIRK_NO_DEEPEST_PS | 3445f03e42c6SGabriel Craciunescu NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34465611ec2bSKai-Heng Feng { PCI_DEVICE(0x1c5c, 0x1504), /* SK Hynix PC400 */ 34475611ec2bSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 344802ca079cSKai-Heng Feng { PCI_DEVICE(0x15b7, 0x2001), /* Sandisk Skyhawk */ 344902ca079cSKai-Heng Feng .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 345089919929SChaitanya Kulkarni { PCI_DEVICE(0x1d97, 0x2263), /* SPCC */ 345189919929SChaitanya Kulkarni .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, }, 3452dc22c1c0SZoltán Böszörményi { PCI_DEVICE(0x2646, 0x2262), /* KINGSTON SKC2000 NVMe SSD */ 3453dc22c1c0SZoltán Böszörményi .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3454538e4a8cSThorsten Leemhuis { PCI_DEVICE(0x2646, 0x2263), /* KINGSTON A2000 NVMe SSD */ 3455538e4a8cSThorsten Leemhuis .driver_data = NVME_QUIRK_NO_DEEPEST_PS, }, 3456*70ce3455SChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1001), /* MAXIO MAP1001 */ 3457*70ce3455SChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3458a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1002), /* MAXIO MAP1002 */ 3459a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 3460a98a945bSChristoph Hellwig { PCI_DEVICE(0x1e4B, 0x1202), /* MAXIO MAP1202 */ 3461a98a945bSChristoph Hellwig .driver_data = NVME_QUIRK_BOGUS_NID, }, 34624bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061), 34634bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34644bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065), 34654bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34664bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061), 34674bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34684bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00), 34694bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34704bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01), 34714bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 34724bdf2603SFilippo Sironi { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02), 34734bdf2603SFilippo Sironi .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, }, 347498f7b86aSAndy Shevchenko { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001), 347598f7b86aSAndy Shevchenko .driver_data = NVME_QUIRK_SINGLE_VECTOR }, 3476124298bdSDaniel Roschka { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) }, 347766341331SBenjamin Herrenschmidt { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005), 347866341331SBenjamin Herrenschmidt .driver_data = NVME_QUIRK_SINGLE_VECTOR | 3479d38e9f04SBenjamin Herrenschmidt NVME_QUIRK_128_BYTES_SQES | 3480a2941f6aSKeith Busch NVME_QUIRK_SHARED_TAGS | 3481a2941f6aSKeith Busch NVME_QUIRK_SKIP_CID_GEN }, 3482bc360b0bSMonish Kumar R { PCI_DEVICE(0x144d, 0xa808), /* Samsung X5 */ 3483bc360b0bSMonish Kumar R .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY| 3484bc360b0bSMonish Kumar R NVME_QUIRK_NO_DEEPEST_PS | 3485bc360b0bSMonish Kumar R NVME_QUIRK_IGNORE_DEV_SUBNQN, }, 34860b85f59dSAndy Shevchenko { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) }, 348757dacad5SJay Sternberg { 0, } 348857dacad5SJay Sternberg }; 348957dacad5SJay Sternberg MODULE_DEVICE_TABLE(pci, nvme_id_table); 349057dacad5SJay Sternberg 349157dacad5SJay Sternberg static struct pci_driver nvme_driver = { 349257dacad5SJay Sternberg .name = "nvme", 349357dacad5SJay Sternberg .id_table = nvme_id_table, 349457dacad5SJay Sternberg .probe = nvme_probe, 349557dacad5SJay Sternberg .remove = nvme_remove, 349657dacad5SJay Sternberg .shutdown = nvme_shutdown, 3497d916b1beSKeith Busch #ifdef CONFIG_PM_SLEEP 349857dacad5SJay Sternberg .driver = { 349957dacad5SJay Sternberg .pm = &nvme_dev_pm_ops, 350057dacad5SJay Sternberg }, 3501d916b1beSKeith Busch #endif 350274d986abSAlexander Duyck .sriov_configure = pci_sriov_configure_simple, 350357dacad5SJay Sternberg .err_handler = &nvme_err_handler, 350457dacad5SJay Sternberg }; 350557dacad5SJay Sternberg 350657dacad5SJay Sternberg static int __init nvme_init(void) 350757dacad5SJay Sternberg { 350881101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64); 350981101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64); 351081101540SChristoph Hellwig BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64); 3511612b7286SMing Lei BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2); 351217c33167SKeith Busch 35139a6327d2SSagi Grimberg return pci_register_driver(&nvme_driver); 351457dacad5SJay Sternberg } 351557dacad5SJay Sternberg 351657dacad5SJay Sternberg static void __exit nvme_exit(void) 351757dacad5SJay Sternberg { 351857dacad5SJay Sternberg pci_unregister_driver(&nvme_driver); 351903e0f3a6SMing Lei flush_workqueue(nvme_wq); 352057dacad5SJay Sternberg } 352157dacad5SJay Sternberg 352257dacad5SJay Sternberg MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>"); 352357dacad5SJay Sternberg MODULE_LICENSE("GPL"); 352457dacad5SJay Sternberg MODULE_VERSION("1.0"); 352557dacad5SJay Sternberg module_init(nvme_init); 352657dacad5SJay Sternberg module_exit(nvme_exit); 3527